1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 2 * All Rights Reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef _I915_REG_H_ 26 #define _I915_REG_H_ 27 28 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) 29 30 /* 31 * The Bridge device's PCI config space has information about the 32 * fb aperture size and the amount of pre-reserved memory. 33 * This is all handled in the intel-gtt.ko module. i915.ko only 34 * cares about the vga bit for the vga rbiter. 35 */ 36 #define INTEL_GMCH_CTRL 0x52 37 #define INTEL_GMCH_VGA_DISABLE (1 << 1) 38 39 /* PCI config space */ 40 41 #define HPLLCC 0xc0 /* 855 only */ 42 #define GC_CLOCK_CONTROL_MASK (0xf << 0) 43 #define GC_CLOCK_133_200 (0 << 0) 44 #define GC_CLOCK_100_200 (1 << 0) 45 #define GC_CLOCK_100_133 (2 << 0) 46 #define GC_CLOCK_166_250 (3 << 0) 47 #define GCFGC2 0xda 48 #define GCFGC 0xf0 /* 915+ only */ 49 #define GC_LOW_FREQUENCY_ENABLE (1 << 7) 50 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) 51 #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) 52 #define GC_DISPLAY_CLOCK_MASK (7 << 4) 53 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) 54 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) 55 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) 56 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) 57 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) 58 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0) 59 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) 60 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) 61 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) 62 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) 63 #define I945_GC_RENDER_CLOCK_MASK (7 << 0) 64 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) 65 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) 66 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) 67 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) 68 #define I915_GC_RENDER_CLOCK_MASK (7 << 0) 69 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) 70 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) 71 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) 72 #define LBB 0xf4 73 74 /* Graphics reset regs */ 75 #define I965_GDRST 0xc0 /* PCI config register */ 76 #define ILK_GDSR 0x2ca4 /* MCHBAR offset */ 77 #define GRDOM_FULL (0<<2) 78 #define GRDOM_RENDER (1<<2) 79 #define GRDOM_MEDIA (3<<2) 80 81 #define GEN6_GDRST 0x941c 82 #define GEN6_GRDOM_FULL (1 << 0) 83 #define GEN6_GRDOM_RENDER (1 << 1) 84 #define GEN6_GRDOM_MEDIA (1 << 2) 85 #define GEN6_GRDOM_BLT (1 << 3) 86 87 /* VGA stuff */ 88 89 #define VGA_ST01_MDA 0x3ba 90 #define VGA_ST01_CGA 0x3da 91 92 #define VGA_MSR_WRITE 0x3c2 93 #define VGA_MSR_READ 0x3cc 94 #define VGA_MSR_MEM_EN (1<<1) 95 #define VGA_MSR_CGA_MODE (1<<0) 96 97 #define VGA_SR_INDEX 0x3c4 98 #define VGA_SR_DATA 0x3c5 99 100 #define VGA_AR_INDEX 0x3c0 101 #define VGA_AR_VID_EN (1<<5) 102 #define VGA_AR_DATA_WRITE 0x3c0 103 #define VGA_AR_DATA_READ 0x3c1 104 105 #define VGA_GR_INDEX 0x3ce 106 #define VGA_GR_DATA 0x3cf 107 /* GR05 */ 108 #define VGA_GR_MEM_READ_MODE_SHIFT 3 109 #define VGA_GR_MEM_READ_MODE_PLANE 1 110 /* GR06 */ 111 #define VGA_GR_MEM_MODE_MASK 0xc 112 #define VGA_GR_MEM_MODE_SHIFT 2 113 #define VGA_GR_MEM_A0000_AFFFF 0 114 #define VGA_GR_MEM_A0000_BFFFF 1 115 #define VGA_GR_MEM_B0000_B7FFF 2 116 #define VGA_GR_MEM_B0000_BFFFF 3 117 118 #define VGA_DACMASK 0x3c6 119 #define VGA_DACRX 0x3c7 120 #define VGA_DACWX 0x3c8 121 #define VGA_DACDATA 0x3c9 122 123 #define VGA_CR_INDEX_MDA 0x3b4 124 #define VGA_CR_DATA_MDA 0x3b5 125 #define VGA_CR_INDEX_CGA 0x3d4 126 #define VGA_CR_DATA_CGA 0x3d5 127 128 /* 129 * Memory interface instructions used by the kernel 130 */ 131 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) 132 133 #define MI_NOOP MI_INSTR(0, 0) 134 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0) 135 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) 136 #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) 137 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) 138 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) 139 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) 140 #define MI_FLUSH MI_INSTR(0x04, 0) 141 #define MI_READ_FLUSH (1 << 0) 142 #define MI_EXE_FLUSH (1 << 1) 143 #define MI_NO_WRITE_FLUSH (1 << 2) 144 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ 145 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ 146 #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ 147 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) 148 #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0) 149 #define MI_SUSPEND_FLUSH_EN (1<<0) 150 #define MI_REPORT_HEAD MI_INSTR(0x07, 0) 151 #define MI_OVERLAY_FLIP MI_INSTR(0x11,0) 152 #define MI_OVERLAY_CONTINUE (0x0<<21) 153 #define MI_OVERLAY_ON (0x1<<21) 154 #define MI_OVERLAY_OFF (0x2<<21) 155 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) 156 #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) 157 #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) 158 #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) 159 #define MI_SET_CONTEXT MI_INSTR(0x18, 0) 160 #define MI_MM_SPACE_GTT (1<<8) 161 #define MI_MM_SPACE_PHYSICAL (0<<8) 162 #define MI_SAVE_EXT_STATE_EN (1<<3) 163 #define MI_RESTORE_EXT_STATE_EN (1<<2) 164 #define MI_FORCE_RESTORE (1<<1) 165 #define MI_RESTORE_INHIBIT (1<<0) 166 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) 167 #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ 168 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) 169 #define MI_STORE_DWORD_INDEX_SHIFT 2 170 /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM: 171 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw 172 * simply ignores the register load under certain conditions. 173 * - One can actually load arbitrary many arbitrary registers: Simply issue x 174 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold! 175 */ 176 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1) 177 #define MI_FLUSH_DW MI_INSTR(0x26, 2) /* for GEN6 */ 178 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) 179 #define MI_BATCH_NON_SECURE (1) 180 #define MI_BATCH_NON_SECURE_I965 (1<<8) 181 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) 182 #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */ 183 #define MI_SEMAPHORE_GLOBAL_GTT (1<<22) 184 #define MI_SEMAPHORE_UPDATE (1<<21) 185 #define MI_SEMAPHORE_COMPARE (1<<20) 186 #define MI_SEMAPHORE_REGISTER (1<<18) 187 /* 188 * 3D instructions used by the kernel 189 */ 190 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) 191 192 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) 193 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 194 #define SC_UPDATE_SCISSOR (0x1<<1) 195 #define SC_ENABLE_MASK (0x1<<0) 196 #define SC_ENABLE (0x1<<0) 197 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) 198 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) 199 #define SCI_YMIN_MASK (0xffff<<16) 200 #define SCI_XMIN_MASK (0xffff<<0) 201 #define SCI_YMAX_MASK (0xffff<<16) 202 #define SCI_XMAX_MASK (0xffff<<0) 203 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 204 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) 205 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) 206 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) 207 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) 208 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) 209 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) 210 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) 211 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) 212 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) 213 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) 214 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) 215 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) 216 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) 217 #define BLT_DEPTH_8 (0<<24) 218 #define BLT_DEPTH_16_565 (1<<24) 219 #define BLT_DEPTH_16_1555 (2<<24) 220 #define BLT_DEPTH_32 (3<<24) 221 #define BLT_ROP_GXCOPY (0xcc<<16) 222 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ 223 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ 224 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) 225 #define ASYNC_FLIP (1<<22) 226 #define DISPLAY_PLANE_A (0<<20) 227 #define DISPLAY_PLANE_B (1<<20) 228 #define GFX_OP_PIPE_CONTROL ((0x3<<29)|(0x3<<27)|(0x2<<24)|2) 229 #define PIPE_CONTROL_QW_WRITE (1<<14) 230 #define PIPE_CONTROL_DEPTH_STALL (1<<13) 231 #define PIPE_CONTROL_WC_FLUSH (1<<12) 232 #define PIPE_CONTROL_IS_FLUSH (1<<11) /* MBZ on Ironlake */ 233 #define PIPE_CONTROL_TC_FLUSH (1<<10) /* GM45+ only */ 234 #define PIPE_CONTROL_ISP_DIS (1<<9) 235 #define PIPE_CONTROL_NOTIFY (1<<8) 236 #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ 237 #define PIPE_CONTROL_STALL_EN (1<<1) /* in addr word, Ironlake+ only */ 238 239 240 /* 241 * Reset registers 242 */ 243 #define DEBUG_RESET_I830 0x6070 244 #define DEBUG_RESET_FULL (1<<7) 245 #define DEBUG_RESET_RENDER (1<<8) 246 #define DEBUG_RESET_DISPLAY (1<<9) 247 248 249 /* 250 * Fence registers 251 */ 252 #define FENCE_REG_830_0 0x2000 253 #define FENCE_REG_945_8 0x3000 254 #define I830_FENCE_START_MASK 0x07f80000 255 #define I830_FENCE_TILING_Y_SHIFT 12 256 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) 257 #define I830_FENCE_PITCH_SHIFT 4 258 #define I830_FENCE_REG_VALID (1<<0) 259 #define I915_FENCE_MAX_PITCH_VAL 4 260 #define I830_FENCE_MAX_PITCH_VAL 6 261 #define I830_FENCE_MAX_SIZE_VAL (1<<8) 262 263 #define I915_FENCE_START_MASK 0x0ff00000 264 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) 265 266 #define FENCE_REG_965_0 0x03000 267 #define I965_FENCE_PITCH_SHIFT 2 268 #define I965_FENCE_TILING_Y_SHIFT 1 269 #define I965_FENCE_REG_VALID (1<<0) 270 #define I965_FENCE_MAX_PITCH_VAL 0x0400 271 272 #define FENCE_REG_SANDYBRIDGE_0 0x100000 273 #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 274 275 /* 276 * Instruction and interrupt control regs 277 */ 278 #define PGTBL_ER 0x02024 279 #define RENDER_RING_BASE 0x02000 280 #define BSD_RING_BASE 0x04000 281 #define GEN6_BSD_RING_BASE 0x12000 282 #define BLT_RING_BASE 0x22000 283 #define RING_TAIL(base) ((base)+0x30) 284 #define RING_HEAD(base) ((base)+0x34) 285 #define RING_START(base) ((base)+0x38) 286 #define RING_CTL(base) ((base)+0x3c) 287 #define RING_SYNC_0(base) ((base)+0x40) 288 #define RING_SYNC_1(base) ((base)+0x44) 289 #define RING_MAX_IDLE(base) ((base)+0x54) 290 #define RING_HWS_PGA(base) ((base)+0x80) 291 #define RING_HWS_PGA_GEN6(base) ((base)+0x2080) 292 #define RING_ACTHD(base) ((base)+0x74) 293 #define RING_NOPID(base) ((base)+0x94) 294 #define RING_IMR(base) ((base)+0xa8) 295 #define TAIL_ADDR 0x001FFFF8 296 #define HEAD_WRAP_COUNT 0xFFE00000 297 #define HEAD_WRAP_ONE 0x00200000 298 #define HEAD_ADDR 0x001FFFFC 299 #define RING_NR_PAGES 0x001FF000 300 #define RING_REPORT_MASK 0x00000006 301 #define RING_REPORT_64K 0x00000002 302 #define RING_REPORT_128K 0x00000004 303 #define RING_NO_REPORT 0x00000000 304 #define RING_VALID_MASK 0x00000001 305 #define RING_VALID 0x00000001 306 #define RING_INVALID 0x00000000 307 #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */ 308 #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */ 309 #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */ 310 #if 0 311 #define PRB0_TAIL 0x02030 312 #define PRB0_HEAD 0x02034 313 #define PRB0_START 0x02038 314 #define PRB0_CTL 0x0203c 315 #define PRB1_TAIL 0x02040 /* 915+ only */ 316 #define PRB1_HEAD 0x02044 /* 915+ only */ 317 #define PRB1_START 0x02048 /* 915+ only */ 318 #define PRB1_CTL 0x0204c /* 915+ only */ 319 #endif 320 #define IPEIR_I965 0x02064 321 #define IPEHR_I965 0x02068 322 #define INSTDONE_I965 0x0206c 323 #define INSTPS 0x02070 /* 965+ only */ 324 #define INSTDONE1 0x0207c /* 965+ only */ 325 #define ACTHD_I965 0x02074 326 #define HWS_PGA 0x02080 327 #define HWS_ADDRESS_MASK 0xfffff000 328 #define HWS_START_ADDRESS_SHIFT 4 329 #define PWRCTXA 0x2088 /* 965GM+ only */ 330 #define PWRCTX_EN (1<<0) 331 #define IPEIR 0x02088 332 #define IPEHR 0x0208c 333 #define INSTDONE 0x02090 334 #define NOPID 0x02094 335 #define HWSTAM 0x02098 336 #define VCS_INSTDONE 0x1206C 337 #define VCS_IPEIR 0x12064 338 #define VCS_IPEHR 0x12068 339 #define VCS_ACTHD 0x12074 340 #define BCS_INSTDONE 0x2206C 341 #define BCS_IPEIR 0x22064 342 #define BCS_IPEHR 0x22068 343 #define BCS_ACTHD 0x22074 344 345 #define ERROR_GEN6 0x040a0 346 347 /* GM45+ chicken bits -- debug workaround bits that may be required 348 * for various sorts of correct behavior. The top 16 bits of each are 349 * the enables for writing to the corresponding low bit. 350 */ 351 #define _3D_CHICKEN 0x02084 352 #define _3D_CHICKEN2 0x0208c 353 /* Disables pipelining of read flushes past the SF-WIZ interface. 354 * Required on all Ironlake steppings according to the B-Spec, but the 355 * particular danger of not doing so is not specified. 356 */ 357 # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) 358 #define _3D_CHICKEN3 0x02090 359 360 #define MI_MODE 0x0209c 361 # define VS_TIMER_DISPATCH (1 << 6) 362 # define MI_FLUSH_ENABLE (1 << 11) 363 364 #define GFX_MODE 0x02520 365 #define GFX_RUN_LIST_ENABLE (1<<15) 366 #define GFX_TLB_INVALIDATE_ALWAYS (1<<13) 367 #define GFX_SURFACE_FAULT_ENABLE (1<<12) 368 #define GFX_REPLAY_MODE (1<<11) 369 #define GFX_PSMI_GRANULARITY (1<<10) 370 #define GFX_PPGTT_ENABLE (1<<9) 371 372 #define SCPD0 0x0209c /* 915+ only */ 373 #define IER 0x020a0 374 #define IIR 0x020a4 375 #define IMR 0x020a8 376 #define ISR 0x020ac 377 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) 378 #define I915_DISPLAY_PORT_INTERRUPT (1<<17) 379 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) 380 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ 381 #define I915_HWB_OOM_INTERRUPT (1<<13) 382 #define I915_SYNC_STATUS_INTERRUPT (1<<12) 383 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) 384 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) 385 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) 386 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) 387 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) 388 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) 389 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) 390 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) 391 #define I915_DEBUG_INTERRUPT (1<<2) 392 #define I915_USER_INTERRUPT (1<<1) 393 #define I915_ASLE_INTERRUPT (1<<0) 394 #define I915_BSD_USER_INTERRUPT (1<<25) 395 #define EIR 0x020b0 396 #define EMR 0x020b4 397 #define ESR 0x020b8 398 #define GM45_ERROR_PAGE_TABLE (1<<5) 399 #define GM45_ERROR_MEM_PRIV (1<<4) 400 #define I915_ERROR_PAGE_TABLE (1<<4) 401 #define GM45_ERROR_CP_PRIV (1<<3) 402 #define I915_ERROR_MEMORY_REFRESH (1<<1) 403 #define I915_ERROR_INSTRUCTION (1<<0) 404 #define INSTPM 0x020c0 405 #define INSTPM_SELF_EN (1<<12) /* 915GM only */ 406 #define ACTHD 0x020c8 407 #define FW_BLC 0x020d8 408 #define FW_BLC2 0x020dc 409 #define FW_BLC_SELF 0x020e0 /* 915+ only */ 410 #define FW_BLC_SELF_EN_MASK (1<<31) 411 #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ 412 #define FW_BLC_SELF_EN (1<<15) /* 945 only */ 413 #define MM_BURST_LENGTH 0x00700000 414 #define MM_FIFO_WATERMARK 0x0001F000 415 #define LM_BURST_LENGTH 0x00000700 416 #define LM_FIFO_WATERMARK 0x0000001F 417 #define MI_ARB_STATE 0x020e4 /* 915+ only */ 418 #define MI_ARB_MASK_SHIFT 16 /* shift for enable bits */ 419 420 /* Make render/texture TLB fetches lower priorty than associated data 421 * fetches. This is not turned on by default 422 */ 423 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) 424 425 /* Isoch request wait on GTT enable (Display A/B/C streams). 426 * Make isoch requests stall on the TLB update. May cause 427 * display underruns (test mode only) 428 */ 429 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14) 430 431 /* Block grant count for isoch requests when block count is 432 * set to a finite value. 433 */ 434 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12) 435 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ 436 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ 437 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ 438 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ 439 440 /* Enable render writes to complete in C2/C3/C4 power states. 441 * If this isn't enabled, render writes are prevented in low 442 * power states. That seems bad to me. 443 */ 444 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) 445 446 /* This acknowledges an async flip immediately instead 447 * of waiting for 2TLB fetches. 448 */ 449 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) 450 451 /* Enables non-sequential data reads through arbiter 452 */ 453 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) 454 455 /* Disable FSB snooping of cacheable write cycles from binner/render 456 * command stream 457 */ 458 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) 459 460 /* Arbiter time slice for non-isoch streams */ 461 #define MI_ARB_TIME_SLICE_MASK (7 << 5) 462 #define MI_ARB_TIME_SLICE_1 (0 << 5) 463 #define MI_ARB_TIME_SLICE_2 (1 << 5) 464 #define MI_ARB_TIME_SLICE_4 (2 << 5) 465 #define MI_ARB_TIME_SLICE_6 (3 << 5) 466 #define MI_ARB_TIME_SLICE_8 (4 << 5) 467 #define MI_ARB_TIME_SLICE_10 (5 << 5) 468 #define MI_ARB_TIME_SLICE_14 (6 << 5) 469 #define MI_ARB_TIME_SLICE_16 (7 << 5) 470 471 /* Low priority grace period page size */ 472 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ 473 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) 474 475 /* Disable display A/B trickle feed */ 476 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) 477 478 /* Set display plane priority */ 479 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ 480 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ 481 482 #define CACHE_MODE_0 0x02120 /* 915+ only */ 483 #define CM0_MASK_SHIFT 16 484 #define CM0_IZ_OPT_DISABLE (1<<6) 485 #define CM0_ZR_OPT_DISABLE (1<<5) 486 #define CM0_DEPTH_EVICT_DISABLE (1<<4) 487 #define CM0_COLOR_EVICT_DISABLE (1<<3) 488 #define CM0_DEPTH_WRITE_DISABLE (1<<1) 489 #define CM0_RC_OP_FLUSH_DISABLE (1<<0) 490 #define BB_ADDR 0x02140 /* 8 bytes */ 491 #define GFX_FLSH_CNTL 0x02170 /* 915+ only */ 492 #define ECOSKPD 0x021d0 493 #define ECO_GATING_CX_ONLY (1<<3) 494 #define ECO_FLIP_DONE (1<<0) 495 496 /* GEN6 interrupt control */ 497 #define GEN6_RENDER_HWSTAM 0x2098 498 #define GEN6_RENDER_IMR 0x20a8 499 #define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8) 500 #define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7) 501 #define GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED (1 << 6) 502 #define GEN6_RENDER_L3_PARITY_ERROR (1 << 5) 503 #define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4) 504 #define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3) 505 #define GEN6_RENDER_SYNC_STATUS (1 << 2) 506 #define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1) 507 #define GEN6_RENDER_USER_INTERRUPT (1 << 0) 508 509 #define GEN6_BLITTER_HWSTAM 0x22098 510 #define GEN6_BLITTER_IMR 0x220a8 511 #define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26) 512 #define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25) 513 #define GEN6_BLITTER_SYNC_STATUS (1 << 24) 514 #define GEN6_BLITTER_USER_INTERRUPT (1 << 22) 515 516 #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050 517 #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK (1 << 16) 518 #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE (1 << 0) 519 #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE 0 520 #define GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR (1 << 3) 521 522 #define GEN6_BSD_IMR 0x120a8 523 #define GEN6_BSD_USER_INTERRUPT (1 << 12) 524 525 #define GEN6_BSD_RNCID 0x12198 526 527 /* 528 * Framebuffer compression (915+ only) 529 */ 530 531 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */ 532 #define FBC_LL_BASE 0x03204 /* 4k page aligned */ 533 #define FBC_CONTROL 0x03208 534 #define FBC_CTL_EN (1<<31) 535 #define FBC_CTL_PERIODIC (1<<30) 536 #define FBC_CTL_INTERVAL_SHIFT (16) 537 #define FBC_CTL_UNCOMPRESSIBLE (1<<14) 538 #define FBC_CTL_C3_IDLE (1<<13) 539 #define FBC_CTL_STRIDE_SHIFT (5) 540 #define FBC_CTL_FENCENO (1<<0) 541 #define FBC_COMMAND 0x0320c 542 #define FBC_CMD_COMPRESS (1<<0) 543 #define FBC_STATUS 0x03210 544 #define FBC_STAT_COMPRESSING (1<<31) 545 #define FBC_STAT_COMPRESSED (1<<30) 546 #define FBC_STAT_MODIFIED (1<<29) 547 #define FBC_STAT_CURRENT_LINE (1<<0) 548 #define FBC_CONTROL2 0x03214 549 #define FBC_CTL_FENCE_DBL (0<<4) 550 #define FBC_CTL_IDLE_IMM (0<<2) 551 #define FBC_CTL_IDLE_FULL (1<<2) 552 #define FBC_CTL_IDLE_LINE (2<<2) 553 #define FBC_CTL_IDLE_DEBUG (3<<2) 554 #define FBC_CTL_CPU_FENCE (1<<1) 555 #define FBC_CTL_PLANEA (0<<0) 556 #define FBC_CTL_PLANEB (1<<0) 557 #define FBC_FENCE_OFF 0x0321b 558 #define FBC_TAG 0x03300 559 560 #define FBC_LL_SIZE (1536) 561 562 /* Framebuffer compression for GM45+ */ 563 #define DPFC_CB_BASE 0x3200 564 #define DPFC_CONTROL 0x3208 565 #define DPFC_CTL_EN (1<<31) 566 #define DPFC_CTL_PLANEA (0<<30) 567 #define DPFC_CTL_PLANEB (1<<30) 568 #define DPFC_CTL_FENCE_EN (1<<29) 569 #define DPFC_SR_EN (1<<10) 570 #define DPFC_CTL_LIMIT_1X (0<<6) 571 #define DPFC_CTL_LIMIT_2X (1<<6) 572 #define DPFC_CTL_LIMIT_4X (2<<6) 573 #define DPFC_RECOMP_CTL 0x320c 574 #define DPFC_RECOMP_STALL_EN (1<<27) 575 #define DPFC_RECOMP_STALL_WM_SHIFT (16) 576 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) 577 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) 578 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) 579 #define DPFC_STATUS 0x3210 580 #define DPFC_INVAL_SEG_SHIFT (16) 581 #define DPFC_INVAL_SEG_MASK (0x07ff0000) 582 #define DPFC_COMP_SEG_SHIFT (0) 583 #define DPFC_COMP_SEG_MASK (0x000003ff) 584 #define DPFC_STATUS2 0x3214 585 #define DPFC_FENCE_YOFF 0x3218 586 #define DPFC_CHICKEN 0x3224 587 #define DPFC_HT_MODIFY (1<<31) 588 589 /* Framebuffer compression for Ironlake */ 590 #define ILK_DPFC_CB_BASE 0x43200 591 #define ILK_DPFC_CONTROL 0x43208 592 /* The bit 28-8 is reserved */ 593 #define DPFC_RESERVED (0x1FFFFF00) 594 #define ILK_DPFC_RECOMP_CTL 0x4320c 595 #define ILK_DPFC_STATUS 0x43210 596 #define ILK_DPFC_FENCE_YOFF 0x43218 597 #define ILK_DPFC_CHICKEN 0x43224 598 #define ILK_FBC_RT_BASE 0x2128 599 #define ILK_FBC_RT_VALID (1<<0) 600 601 #define ILK_DISPLAY_CHICKEN1 0x42000 602 #define ILK_FBCQ_DIS (1<<22) 603 #define ILK_PABSTRETCH_DIS (1<<21) 604 605 606 /* 607 * Framebuffer compression for Sandybridge 608 * 609 * The following two registers are of type GTTMMADR 610 */ 611 #define SNB_DPFC_CTL_SA 0x100100 612 #define SNB_CPU_FENCE_ENABLE (1<<29) 613 #define DPFC_CPU_FENCE_OFFSET 0x100104 614 615 616 /* 617 * GPIO regs 618 */ 619 #define GPIOA 0x5010 620 #define GPIOB 0x5014 621 #define GPIOC 0x5018 622 #define GPIOD 0x501c 623 #define GPIOE 0x5020 624 #define GPIOF 0x5024 625 #define GPIOG 0x5028 626 #define GPIOH 0x502c 627 # define GPIO_CLOCK_DIR_MASK (1 << 0) 628 # define GPIO_CLOCK_DIR_IN (0 << 1) 629 # define GPIO_CLOCK_DIR_OUT (1 << 1) 630 # define GPIO_CLOCK_VAL_MASK (1 << 2) 631 # define GPIO_CLOCK_VAL_OUT (1 << 3) 632 # define GPIO_CLOCK_VAL_IN (1 << 4) 633 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) 634 # define GPIO_DATA_DIR_MASK (1 << 8) 635 # define GPIO_DATA_DIR_IN (0 << 9) 636 # define GPIO_DATA_DIR_OUT (1 << 9) 637 # define GPIO_DATA_VAL_MASK (1 << 10) 638 # define GPIO_DATA_VAL_OUT (1 << 11) 639 # define GPIO_DATA_VAL_IN (1 << 12) 640 # define GPIO_DATA_PULLUP_DISABLE (1 << 13) 641 642 #define GMBUS0 0x5100 /* clock/port select */ 643 #define GMBUS_RATE_100KHZ (0<<8) 644 #define GMBUS_RATE_50KHZ (1<<8) 645 #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ 646 #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */ 647 #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */ 648 #define GMBUS_PORT_DISABLED 0 649 #define GMBUS_PORT_SSC 1 650 #define GMBUS_PORT_VGADDC 2 651 #define GMBUS_PORT_PANEL 3 652 #define GMBUS_PORT_DPC 4 /* HDMIC */ 653 #define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */ 654 /* 6 reserved */ 655 #define GMBUS_PORT_DPD 7 /* HDMID */ 656 #define GMBUS_NUM_PORTS 8 657 #define GMBUS1 0x5104 /* command/status */ 658 #define GMBUS_SW_CLR_INT (1<<31) 659 #define GMBUS_SW_RDY (1<<30) 660 #define GMBUS_ENT (1<<29) /* enable timeout */ 661 #define GMBUS_CYCLE_NONE (0<<25) 662 #define GMBUS_CYCLE_WAIT (1<<25) 663 #define GMBUS_CYCLE_INDEX (2<<25) 664 #define GMBUS_CYCLE_STOP (4<<25) 665 #define GMBUS_BYTE_COUNT_SHIFT 16 666 #define GMBUS_SLAVE_INDEX_SHIFT 8 667 #define GMBUS_SLAVE_ADDR_SHIFT 1 668 #define GMBUS_SLAVE_READ (1<<0) 669 #define GMBUS_SLAVE_WRITE (0<<0) 670 #define GMBUS2 0x5108 /* status */ 671 #define GMBUS_INUSE (1<<15) 672 #define GMBUS_HW_WAIT_PHASE (1<<14) 673 #define GMBUS_STALL_TIMEOUT (1<<13) 674 #define GMBUS_INT (1<<12) 675 #define GMBUS_HW_RDY (1<<11) 676 #define GMBUS_SATOER (1<<10) 677 #define GMBUS_ACTIVE (1<<9) 678 #define GMBUS3 0x510c /* data buffer bytes 3-0 */ 679 #define GMBUS4 0x5110 /* interrupt mask (Pineview+) */ 680 #define GMBUS_SLAVE_TIMEOUT_EN (1<<4) 681 #define GMBUS_NAK_EN (1<<3) 682 #define GMBUS_IDLE_EN (1<<2) 683 #define GMBUS_HW_WAIT_EN (1<<1) 684 #define GMBUS_HW_RDY_EN (1<<0) 685 #define GMBUS5 0x5120 /* byte index */ 686 #define GMBUS_2BYTE_INDEX_EN (1<<31) 687 688 /* 689 * Clock control & power management 690 */ 691 692 #define VGA0 0x6000 693 #define VGA1 0x6004 694 #define VGA_PD 0x6010 695 #define VGA0_PD_P2_DIV_4 (1 << 7) 696 #define VGA0_PD_P1_DIV_2 (1 << 5) 697 #define VGA0_PD_P1_SHIFT 0 698 #define VGA0_PD_P1_MASK (0x1f << 0) 699 #define VGA1_PD_P2_DIV_4 (1 << 15) 700 #define VGA1_PD_P1_DIV_2 (1 << 13) 701 #define VGA1_PD_P1_SHIFT 8 702 #define VGA1_PD_P1_MASK (0x1f << 8) 703 #define DPLL_A 0x06014 704 #define DPLL_B 0x06018 705 #define DPLL(pipe) _PIPE(pipe, DPLL_A, DPLL_B) 706 #define DPLL_VCO_ENABLE (1 << 31) 707 #define DPLL_DVO_HIGH_SPEED (1 << 30) 708 #define DPLL_SYNCLOCK_ENABLE (1 << 29) 709 #define DPLL_VGA_MODE_DIS (1 << 28) 710 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 711 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 712 #define DPLL_MODE_MASK (3 << 26) 713 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 714 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 715 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 716 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 717 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 718 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 719 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ 720 721 #define SRX_INDEX 0x3c4 722 #define SRX_DATA 0x3c5 723 #define SR01 1 724 #define SR01_SCREEN_OFF (1<<5) 725 726 #define PPCR 0x61204 727 #define PPCR_ON (1<<0) 728 729 #define DVOB 0x61140 730 #define DVOB_ON (1<<31) 731 #define DVOC 0x61160 732 #define DVOC_ON (1<<31) 733 #define LVDS 0x61180 734 #define LVDS_ON (1<<31) 735 736 /* Scratch pad debug 0 reg: 737 */ 738 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 739 /* 740 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 741 * this field (only one bit may be set). 742 */ 743 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 744 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 745 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 746 /* i830, required in DVO non-gang */ 747 #define PLL_P2_DIVIDE_BY_4 (1 << 23) 748 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 749 #define PLL_REF_INPUT_DREFCLK (0 << 13) 750 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 751 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 752 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 753 #define PLL_REF_INPUT_MASK (3 << 13) 754 #define PLL_LOAD_PULSE_PHASE_SHIFT 9 755 /* Ironlake */ 756 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 757 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) 758 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9) 759 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 760 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff 761 762 /* 763 * Parallel to Serial Load Pulse phase selection. 764 * Selects the phase for the 10X DPLL clock for the PCIe 765 * digital display port. The range is 4 to 13; 10 or more 766 * is just a flip delay. The default is 6 767 */ 768 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 769 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 770 /* 771 * SDVO multiplier for 945G/GM. Not used on 965. 772 */ 773 #define SDVO_MULTIPLIER_MASK 0x000000ff 774 #define SDVO_MULTIPLIER_SHIFT_HIRES 4 775 #define SDVO_MULTIPLIER_SHIFT_VGA 0 776 #define DPLL_A_MD 0x0601c /* 965+ only */ 777 /* 778 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 779 * 780 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 781 */ 782 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 783 #define DPLL_MD_UDI_DIVIDER_SHIFT 24 784 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 785 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 786 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 787 /* 788 * SDVO/UDI pixel multiplier. 789 * 790 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 791 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 792 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 793 * dummy bytes in the datastream at an increased clock rate, with both sides of 794 * the link knowing how many bytes are fill. 795 * 796 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 797 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 798 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 799 * through an SDVO command. 800 * 801 * This register field has values of multiplication factor minus 1, with 802 * a maximum multiplier of 5 for SDVO. 803 */ 804 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 805 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 806 /* 807 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 808 * This best be set to the default value (3) or the CRT won't work. No, 809 * I don't entirely understand what this does... 810 */ 811 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 812 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 813 #define DPLL_B_MD 0x06020 /* 965+ only */ 814 #define DPLL_MD(pipe) _PIPE(pipe, DPLL_A_MD, DPLL_B_MD) 815 #define FPA0 0x06040 816 #define FPA1 0x06044 817 #define FPB0 0x06048 818 #define FPB1 0x0604c 819 #define FP0(pipe) _PIPE(pipe, FPA0, FPB0) 820 #define FP1(pipe) _PIPE(pipe, FPA1, FPB1) 821 #define FP_N_DIV_MASK 0x003f0000 822 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 823 #define FP_N_DIV_SHIFT 16 824 #define FP_M1_DIV_MASK 0x00003f00 825 #define FP_M1_DIV_SHIFT 8 826 #define FP_M2_DIV_MASK 0x0000003f 827 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff 828 #define FP_M2_DIV_SHIFT 0 829 #define DPLL_TEST 0x606c 830 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 831 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 832 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 833 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 834 #define DPLLB_TEST_N_BYPASS (1 << 19) 835 #define DPLLB_TEST_M_BYPASS (1 << 18) 836 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 837 #define DPLLA_TEST_N_BYPASS (1 << 3) 838 #define DPLLA_TEST_M_BYPASS (1 << 2) 839 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 840 #define D_STATE 0x6104 841 #define DSTATE_GFX_RESET_I830 (1<<6) 842 #define DSTATE_PLL_D3_OFF (1<<3) 843 #define DSTATE_GFX_CLOCK_GATING (1<<1) 844 #define DSTATE_DOT_CLOCK_GATING (1<<0) 845 #define DSPCLK_GATE_D 0x6200 846 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ 847 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ 848 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ 849 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ 850 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ 851 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ 852 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ 853 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ 854 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ 855 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ 856 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ 857 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ 858 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ 859 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ 860 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ 861 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ 862 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ 863 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ 864 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ 865 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) 866 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) 867 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) 868 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) 869 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ 870 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ 871 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ 872 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) 873 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) 874 /** 875 * This bit must be set on the 830 to prevent hangs when turning off the 876 * overlay scaler. 877 */ 878 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) 879 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) 880 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) 881 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ 882 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ 883 884 #define RENCLK_GATE_D1 0x6204 885 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ 886 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ 887 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) 888 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) 889 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) 890 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) 891 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) 892 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) 893 # define MAG_CLOCK_GATE_DISABLE (1 << 5) 894 /** This bit must be unset on 855,865 */ 895 # define MECI_CLOCK_GATE_DISABLE (1 << 4) 896 # define DCMP_CLOCK_GATE_DISABLE (1 << 3) 897 # define MEC_CLOCK_GATE_DISABLE (1 << 2) 898 # define MECO_CLOCK_GATE_DISABLE (1 << 1) 899 /** This bit must be set on 855,865. */ 900 # define SV_CLOCK_GATE_DISABLE (1 << 0) 901 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) 902 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) 903 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) 904 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) 905 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) 906 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) 907 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) 908 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) 909 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) 910 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) 911 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) 912 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) 913 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) 914 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) 915 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) 916 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) 917 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) 918 919 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) 920 /** This bit must always be set on 965G/965GM */ 921 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) 922 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) 923 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) 924 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) 925 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) 926 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) 927 /** This bit must always be set on 965G */ 928 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) 929 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) 930 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) 931 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) 932 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) 933 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) 934 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) 935 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) 936 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) 937 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) 938 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) 939 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) 940 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) 941 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) 942 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) 943 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) 944 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) 945 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) 946 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) 947 948 #define RENCLK_GATE_D2 0x6208 949 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) 950 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) 951 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) 952 #define RAMCLK_GATE_D 0x6210 /* CRL only */ 953 #define DEUC 0x6214 /* CRL only */ 954 955 /* 956 * Palette regs 957 */ 958 959 #define PALETTE_A 0x0a000 960 #define PALETTE_B 0x0a800 961 962 /* MCH MMIO space */ 963 964 /* 965 * MCHBAR mirror. 966 * 967 * This mirrors the MCHBAR MMIO space whose location is determined by 968 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in 969 * every way. It is not accessible from the CP register read instructions. 970 * 971 */ 972 #define MCHBAR_MIRROR_BASE 0x10000 973 974 #define MCHBAR_MIRROR_BASE_SNB 0x140000 975 976 /** 915-945 and GM965 MCH register controlling DRAM channel access */ 977 #define DCC 0x10200 978 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) 979 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) 980 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) 981 #define DCC_ADDRESSING_MODE_MASK (3 << 0) 982 #define DCC_CHANNEL_XOR_DISABLE (1 << 10) 983 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9) 984 985 /** Pineview MCH register contains DDR3 setting */ 986 #define CSHRDDR3CTL 0x101a8 987 #define CSHRDDR3CTL_DDR3 (1 << 2) 988 989 /** 965 MCH register controlling DRAM channel configuration */ 990 #define C0DRB3 0x10206 991 #define C1DRB3 0x10606 992 993 /* Clocking configuration register */ 994 #define CLKCFG 0x10c00 995 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */ 996 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */ 997 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */ 998 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */ 999 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */ 1000 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */ 1001 /* Note, below two are guess */ 1002 #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */ 1003 #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */ 1004 #define CLKCFG_FSB_MASK (7 << 0) 1005 #define CLKCFG_MEM_533 (1 << 4) 1006 #define CLKCFG_MEM_667 (2 << 4) 1007 #define CLKCFG_MEM_800 (3 << 4) 1008 #define CLKCFG_MEM_MASK (7 << 4) 1009 1010 #define TSC1 0x11001 1011 #define TSE (1<<0) 1012 #define TR1 0x11006 1013 #define TSFS 0x11020 1014 #define TSFS_SLOPE_MASK 0x0000ff00 1015 #define TSFS_SLOPE_SHIFT 8 1016 #define TSFS_INTR_MASK 0x000000ff 1017 1018 #define CRSTANDVID 0x11100 1019 #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ 1020 #define PXVFREQ_PX_MASK 0x7f000000 1021 #define PXVFREQ_PX_SHIFT 24 1022 #define VIDFREQ_BASE 0x11110 1023 #define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */ 1024 #define VIDFREQ2 0x11114 1025 #define VIDFREQ3 0x11118 1026 #define VIDFREQ4 0x1111c 1027 #define VIDFREQ_P0_MASK 0x1f000000 1028 #define VIDFREQ_P0_SHIFT 24 1029 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000 1030 #define VIDFREQ_P0_CSCLK_SHIFT 20 1031 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000 1032 #define VIDFREQ_P0_CRCLK_SHIFT 16 1033 #define VIDFREQ_P1_MASK 0x00001f00 1034 #define VIDFREQ_P1_SHIFT 8 1035 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0 1036 #define VIDFREQ_P1_CSCLK_SHIFT 4 1037 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f 1038 #define INTTOEXT_BASE_ILK 0x11300 1039 #define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */ 1040 #define INTTOEXT_MAP3_SHIFT 24 1041 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) 1042 #define INTTOEXT_MAP2_SHIFT 16 1043 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) 1044 #define INTTOEXT_MAP1_SHIFT 8 1045 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) 1046 #define INTTOEXT_MAP0_SHIFT 0 1047 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) 1048 #define MEMSWCTL 0x11170 /* Ironlake only */ 1049 #define MEMCTL_CMD_MASK 0xe000 1050 #define MEMCTL_CMD_SHIFT 13 1051 #define MEMCTL_CMD_RCLK_OFF 0 1052 #define MEMCTL_CMD_RCLK_ON 1 1053 #define MEMCTL_CMD_CHFREQ 2 1054 #define MEMCTL_CMD_CHVID 3 1055 #define MEMCTL_CMD_VMMOFF 4 1056 #define MEMCTL_CMD_VMMON 5 1057 #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears 1058 when command complete */ 1059 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ 1060 #define MEMCTL_FREQ_SHIFT 8 1061 #define MEMCTL_SFCAVM (1<<7) 1062 #define MEMCTL_TGT_VID_MASK 0x007f 1063 #define MEMIHYST 0x1117c 1064 #define MEMINTREN 0x11180 /* 16 bits */ 1065 #define MEMINT_RSEXIT_EN (1<<8) 1066 #define MEMINT_CX_SUPR_EN (1<<7) 1067 #define MEMINT_CONT_BUSY_EN (1<<6) 1068 #define MEMINT_AVG_BUSY_EN (1<<5) 1069 #define MEMINT_EVAL_CHG_EN (1<<4) 1070 #define MEMINT_MON_IDLE_EN (1<<3) 1071 #define MEMINT_UP_EVAL_EN (1<<2) 1072 #define MEMINT_DOWN_EVAL_EN (1<<1) 1073 #define MEMINT_SW_CMD_EN (1<<0) 1074 #define MEMINTRSTR 0x11182 /* 16 bits */ 1075 #define MEM_RSEXIT_MASK 0xc000 1076 #define MEM_RSEXIT_SHIFT 14 1077 #define MEM_CONT_BUSY_MASK 0x3000 1078 #define MEM_CONT_BUSY_SHIFT 12 1079 #define MEM_AVG_BUSY_MASK 0x0c00 1080 #define MEM_AVG_BUSY_SHIFT 10 1081 #define MEM_EVAL_CHG_MASK 0x0300 1082 #define MEM_EVAL_BUSY_SHIFT 8 1083 #define MEM_MON_IDLE_MASK 0x00c0 1084 #define MEM_MON_IDLE_SHIFT 6 1085 #define MEM_UP_EVAL_MASK 0x0030 1086 #define MEM_UP_EVAL_SHIFT 4 1087 #define MEM_DOWN_EVAL_MASK 0x000c 1088 #define MEM_DOWN_EVAL_SHIFT 2 1089 #define MEM_SW_CMD_MASK 0x0003 1090 #define MEM_INT_STEER_GFX 0 1091 #define MEM_INT_STEER_CMR 1 1092 #define MEM_INT_STEER_SMI 2 1093 #define MEM_INT_STEER_SCI 3 1094 #define MEMINTRSTS 0x11184 1095 #define MEMINT_RSEXIT (1<<7) 1096 #define MEMINT_CONT_BUSY (1<<6) 1097 #define MEMINT_AVG_BUSY (1<<5) 1098 #define MEMINT_EVAL_CHG (1<<4) 1099 #define MEMINT_MON_IDLE (1<<3) 1100 #define MEMINT_UP_EVAL (1<<2) 1101 #define MEMINT_DOWN_EVAL (1<<1) 1102 #define MEMINT_SW_CMD (1<<0) 1103 #define MEMMODECTL 0x11190 1104 #define MEMMODE_BOOST_EN (1<<31) 1105 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ 1106 #define MEMMODE_BOOST_FREQ_SHIFT 24 1107 #define MEMMODE_IDLE_MODE_MASK 0x00030000 1108 #define MEMMODE_IDLE_MODE_SHIFT 16 1109 #define MEMMODE_IDLE_MODE_EVAL 0 1110 #define MEMMODE_IDLE_MODE_CONT 1 1111 #define MEMMODE_HWIDLE_EN (1<<15) 1112 #define MEMMODE_SWMODE_EN (1<<14) 1113 #define MEMMODE_RCLK_GATE (1<<13) 1114 #define MEMMODE_HW_UPDATE (1<<12) 1115 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ 1116 #define MEMMODE_FSTART_SHIFT 8 1117 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ 1118 #define MEMMODE_FMAX_SHIFT 4 1119 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ 1120 #define RCBMAXAVG 0x1119c 1121 #define MEMSWCTL2 0x1119e /* Cantiga only */ 1122 #define SWMEMCMD_RENDER_OFF (0 << 13) 1123 #define SWMEMCMD_RENDER_ON (1 << 13) 1124 #define SWMEMCMD_SWFREQ (2 << 13) 1125 #define SWMEMCMD_TARVID (3 << 13) 1126 #define SWMEMCMD_VRM_OFF (4 << 13) 1127 #define SWMEMCMD_VRM_ON (5 << 13) 1128 #define CMDSTS (1<<12) 1129 #define SFCAVM (1<<11) 1130 #define SWFREQ_MASK 0x0380 /* P0-7 */ 1131 #define SWFREQ_SHIFT 7 1132 #define TARVID_MASK 0x001f 1133 #define MEMSTAT_CTG 0x111a0 1134 #define RCBMINAVG 0x111a0 1135 #define RCUPEI 0x111b0 1136 #define RCDNEI 0x111b4 1137 #define RSTDBYCTL 0x111b8 1138 #define RS1EN (1<<31) 1139 #define RS2EN (1<<30) 1140 #define RS3EN (1<<29) 1141 #define D3RS3EN (1<<28) /* Display D3 imlies RS3 */ 1142 #define SWPROMORSX (1<<27) /* RSx promotion timers ignored */ 1143 #define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */ 1144 #define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */ 1145 #define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */ 1146 #define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */ 1147 #define RSX_STATUS_MASK (7<<20) 1148 #define RSX_STATUS_ON (0<<20) 1149 #define RSX_STATUS_RC1 (1<<20) 1150 #define RSX_STATUS_RC1E (2<<20) 1151 #define RSX_STATUS_RS1 (3<<20) 1152 #define RSX_STATUS_RS2 (4<<20) /* aka rc6 */ 1153 #define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */ 1154 #define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */ 1155 #define RSX_STATUS_RSVD2 (7<<20) 1156 #define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */ 1157 #define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */ 1158 #define JRSC (1<<17) /* rsx coupled to cpu c-state */ 1159 #define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */ 1160 #define RS1CONTSAV_MASK (3<<14) 1161 #define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */ 1162 #define RS1CONTSAV_RSVD (1<<14) 1163 #define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */ 1164 #define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */ 1165 #define NORMSLEXLAT_MASK (3<<12) 1166 #define SLOW_RS123 (0<<12) 1167 #define SLOW_RS23 (1<<12) 1168 #define SLOW_RS3 (2<<12) 1169 #define NORMAL_RS123 (3<<12) 1170 #define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */ 1171 #define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */ 1172 #define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */ 1173 #define STATELOCK (1<<7) /* locked to rs_cstate if 0 */ 1174 #define RS_CSTATE_MASK (3<<4) 1175 #define RS_CSTATE_C367_RS1 (0<<4) 1176 #define RS_CSTATE_C36_RS1_C7_RS2 (1<<4) 1177 #define RS_CSTATE_RSVD (2<<4) 1178 #define RS_CSTATE_C367_RS2 (3<<4) 1179 #define REDSAVES (1<<3) /* no context save if was idle during rs0 */ 1180 #define REDRESTORES (1<<2) /* no restore if was idle during rs0 */ 1181 #define VIDCTL 0x111c0 1182 #define VIDSTS 0x111c8 1183 #define VIDSTART 0x111cc /* 8 bits */ 1184 #define MEMSTAT_ILK 0x111f8 1185 #define MEMSTAT_VID_MASK 0x7f00 1186 #define MEMSTAT_VID_SHIFT 8 1187 #define MEMSTAT_PSTATE_MASK 0x00f8 1188 #define MEMSTAT_PSTATE_SHIFT 3 1189 #define MEMSTAT_MON_ACTV (1<<2) 1190 #define MEMSTAT_SRC_CTL_MASK 0x0003 1191 #define MEMSTAT_SRC_CTL_CORE 0 1192 #define MEMSTAT_SRC_CTL_TRB 1 1193 #define MEMSTAT_SRC_CTL_THM 2 1194 #define MEMSTAT_SRC_CTL_STDBY 3 1195 #define RCPREVBSYTUPAVG 0x113b8 1196 #define RCPREVBSYTDNAVG 0x113bc 1197 #define PMMISC 0x11214 1198 #define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */ 1199 #define SDEW 0x1124c 1200 #define CSIEW0 0x11250 1201 #define CSIEW1 0x11254 1202 #define CSIEW2 0x11258 1203 #define PEW 0x1125c 1204 #define DEW 0x11270 1205 #define MCHAFE 0x112c0 1206 #define CSIEC 0x112e0 1207 #define DMIEC 0x112e4 1208 #define DDREC 0x112e8 1209 #define PEG0EC 0x112ec 1210 #define PEG1EC 0x112f0 1211 #define GFXEC 0x112f4 1212 #define RPPREVBSYTUPAVG 0x113b8 1213 #define RPPREVBSYTDNAVG 0x113bc 1214 #define ECR 0x11600 1215 #define ECR_GPFE (1<<31) 1216 #define ECR_IMONE (1<<30) 1217 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */ 1218 #define OGW0 0x11608 1219 #define OGW1 0x1160c 1220 #define EG0 0x11610 1221 #define EG1 0x11614 1222 #define EG2 0x11618 1223 #define EG3 0x1161c 1224 #define EG4 0x11620 1225 #define EG5 0x11624 1226 #define EG6 0x11628 1227 #define EG7 0x1162c 1228 #define PXW 0x11664 1229 #define PXWL 0x11680 1230 #define LCFUSE02 0x116c0 1231 #define LCFUSE_HIV_MASK 0x000000ff 1232 #define CSIPLL0 0x12c10 1233 #define DDRMPLL1 0X12c20 1234 #define PEG_BAND_GAP_DATA 0x14d68 1235 1236 #define GEN6_GT_PERF_STATUS 0x145948 1237 #define GEN6_RP_STATE_LIMITS 0x145994 1238 #define GEN6_RP_STATE_CAP 0x145998 1239 1240 /* 1241 * Logical Context regs 1242 */ 1243 #define CCID 0x2180 1244 #define CCID_EN (1<<0) 1245 /* 1246 * Overlay regs 1247 */ 1248 1249 #define OVADD 0x30000 1250 #define DOVSTA 0x30008 1251 #define OC_BUF (0x3<<20) 1252 #define OGAMC5 0x30010 1253 #define OGAMC4 0x30014 1254 #define OGAMC3 0x30018 1255 #define OGAMC2 0x3001c 1256 #define OGAMC1 0x30020 1257 #define OGAMC0 0x30024 1258 1259 /* 1260 * Display engine regs 1261 */ 1262 1263 /* Pipe A timing regs */ 1264 #define HTOTAL_A 0x60000 1265 #define HBLANK_A 0x60004 1266 #define HSYNC_A 0x60008 1267 #define VTOTAL_A 0x6000c 1268 #define VBLANK_A 0x60010 1269 #define VSYNC_A 0x60014 1270 #define PIPEASRC 0x6001c 1271 #define BCLRPAT_A 0x60020 1272 1273 /* Pipe B timing regs */ 1274 #define HTOTAL_B 0x61000 1275 #define HBLANK_B 0x61004 1276 #define HSYNC_B 0x61008 1277 #define VTOTAL_B 0x6100c 1278 #define VBLANK_B 0x61010 1279 #define VSYNC_B 0x61014 1280 #define PIPEBSRC 0x6101c 1281 #define BCLRPAT_B 0x61020 1282 1283 #define HTOTAL(pipe) _PIPE(pipe, HTOTAL_A, HTOTAL_B) 1284 #define HBLANK(pipe) _PIPE(pipe, HBLANK_A, HBLANK_B) 1285 #define HSYNC(pipe) _PIPE(pipe, HSYNC_A, HSYNC_B) 1286 #define VTOTAL(pipe) _PIPE(pipe, VTOTAL_A, VTOTAL_B) 1287 #define VBLANK(pipe) _PIPE(pipe, VBLANK_A, VBLANK_B) 1288 #define VSYNC(pipe) _PIPE(pipe, VSYNC_A, VSYNC_B) 1289 #define BCLRPAT(pipe) _PIPE(pipe, BCLRPAT_A, BCLRPAT_B) 1290 1291 /* VGA port control */ 1292 #define ADPA 0x61100 1293 #define ADPA_DAC_ENABLE (1<<31) 1294 #define ADPA_DAC_DISABLE 0 1295 #define ADPA_PIPE_SELECT_MASK (1<<30) 1296 #define ADPA_PIPE_A_SELECT 0 1297 #define ADPA_PIPE_B_SELECT (1<<30) 1298 #define ADPA_USE_VGA_HVPOLARITY (1<<15) 1299 #define ADPA_SETS_HVPOLARITY 0 1300 #define ADPA_VSYNC_CNTL_DISABLE (1<<11) 1301 #define ADPA_VSYNC_CNTL_ENABLE 0 1302 #define ADPA_HSYNC_CNTL_DISABLE (1<<10) 1303 #define ADPA_HSYNC_CNTL_ENABLE 0 1304 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4) 1305 #define ADPA_VSYNC_ACTIVE_LOW 0 1306 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3) 1307 #define ADPA_HSYNC_ACTIVE_LOW 0 1308 #define ADPA_DPMS_MASK (~(3<<10)) 1309 #define ADPA_DPMS_ON (0<<10) 1310 #define ADPA_DPMS_SUSPEND (1<<10) 1311 #define ADPA_DPMS_STANDBY (2<<10) 1312 #define ADPA_DPMS_OFF (3<<10) 1313 1314 1315 /* Hotplug control (945+ only) */ 1316 #define PORT_HOTPLUG_EN 0x61110 1317 #define HDMIB_HOTPLUG_INT_EN (1 << 29) 1318 #define DPB_HOTPLUG_INT_EN (1 << 29) 1319 #define HDMIC_HOTPLUG_INT_EN (1 << 28) 1320 #define DPC_HOTPLUG_INT_EN (1 << 28) 1321 #define HDMID_HOTPLUG_INT_EN (1 << 27) 1322 #define DPD_HOTPLUG_INT_EN (1 << 27) 1323 #define SDVOB_HOTPLUG_INT_EN (1 << 26) 1324 #define SDVOC_HOTPLUG_INT_EN (1 << 25) 1325 #define TV_HOTPLUG_INT_EN (1 << 18) 1326 #define CRT_HOTPLUG_INT_EN (1 << 9) 1327 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 1328 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) 1329 /* must use period 64 on GM45 according to docs */ 1330 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) 1331 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) 1332 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) 1333 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) 1334 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) 1335 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) 1336 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) 1337 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) 1338 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) 1339 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) 1340 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) 1341 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 1342 1343 #define PORT_HOTPLUG_STAT 0x61114 1344 #define HDMIB_HOTPLUG_INT_STATUS (1 << 29) 1345 #define DPB_HOTPLUG_INT_STATUS (1 << 29) 1346 #define HDMIC_HOTPLUG_INT_STATUS (1 << 28) 1347 #define DPC_HOTPLUG_INT_STATUS (1 << 28) 1348 #define HDMID_HOTPLUG_INT_STATUS (1 << 27) 1349 #define DPD_HOTPLUG_INT_STATUS (1 << 27) 1350 #define CRT_HOTPLUG_INT_STATUS (1 << 11) 1351 #define TV_HOTPLUG_INT_STATUS (1 << 10) 1352 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 1353 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 1354 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 1355 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 1356 #define SDVOC_HOTPLUG_INT_STATUS (1 << 7) 1357 #define SDVOB_HOTPLUG_INT_STATUS (1 << 6) 1358 1359 /* SDVO port control */ 1360 #define SDVOB 0x61140 1361 #define SDVOC 0x61160 1362 #define SDVO_ENABLE (1 << 31) 1363 #define SDVO_PIPE_B_SELECT (1 << 30) 1364 #define SDVO_STALL_SELECT (1 << 29) 1365 #define SDVO_INTERRUPT_ENABLE (1 << 26) 1366 /** 1367 * 915G/GM SDVO pixel multiplier. 1368 * 1369 * Programmed value is multiplier - 1, up to 5x. 1370 * 1371 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 1372 */ 1373 #define SDVO_PORT_MULTIPLY_MASK (7 << 23) 1374 #define SDVO_PORT_MULTIPLY_SHIFT 23 1375 #define SDVO_PHASE_SELECT_MASK (15 << 19) 1376 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 1377 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 1378 #define SDVOC_GANG_MODE (1 << 16) 1379 #define SDVO_ENCODING_SDVO (0x0 << 10) 1380 #define SDVO_ENCODING_HDMI (0x2 << 10) 1381 /** Requird for HDMI operation */ 1382 #define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9) 1383 #define SDVO_BORDER_ENABLE (1 << 7) 1384 #define SDVO_AUDIO_ENABLE (1 << 6) 1385 /** New with 965, default is to be set */ 1386 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) 1387 /** New with 965, default is to be set */ 1388 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) 1389 #define SDVOB_PCIE_CONCURRENCY (1 << 3) 1390 #define SDVO_DETECTED (1 << 2) 1391 /* Bits to be preserved when writing */ 1392 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26)) 1393 #define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26)) 1394 1395 /* DVO port control */ 1396 #define DVOA 0x61120 1397 #define DVOB 0x61140 1398 #define DVOC 0x61160 1399 #define DVO_ENABLE (1 << 31) 1400 #define DVO_PIPE_B_SELECT (1 << 30) 1401 #define DVO_PIPE_STALL_UNUSED (0 << 28) 1402 #define DVO_PIPE_STALL (1 << 28) 1403 #define DVO_PIPE_STALL_TV (2 << 28) 1404 #define DVO_PIPE_STALL_MASK (3 << 28) 1405 #define DVO_USE_VGA_SYNC (1 << 15) 1406 #define DVO_DATA_ORDER_I740 (0 << 14) 1407 #define DVO_DATA_ORDER_FP (1 << 14) 1408 #define DVO_VSYNC_DISABLE (1 << 11) 1409 #define DVO_HSYNC_DISABLE (1 << 10) 1410 #define DVO_VSYNC_TRISTATE (1 << 9) 1411 #define DVO_HSYNC_TRISTATE (1 << 8) 1412 #define DVO_BORDER_ENABLE (1 << 7) 1413 #define DVO_DATA_ORDER_GBRG (1 << 6) 1414 #define DVO_DATA_ORDER_RGGB (0 << 6) 1415 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) 1416 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) 1417 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4) 1418 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3) 1419 #define DVO_BLANK_ACTIVE_HIGH (1 << 2) 1420 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ 1421 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ 1422 #define DVO_PRESERVE_MASK (0x7<<24) 1423 #define DVOA_SRCDIM 0x61124 1424 #define DVOB_SRCDIM 0x61144 1425 #define DVOC_SRCDIM 0x61164 1426 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12 1427 #define DVO_SRCDIM_VERTICAL_SHIFT 0 1428 1429 /* LVDS port control */ 1430 #define LVDS 0x61180 1431 /* 1432 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 1433 * the DPLL semantics change when the LVDS is assigned to that pipe. 1434 */ 1435 #define LVDS_PORT_EN (1 << 31) 1436 /* Selects pipe B for LVDS data. Must be set on pre-965. */ 1437 #define LVDS_PIPEB_SELECT (1 << 30) 1438 /* LVDS dithering flag on 965/g4x platform */ 1439 #define LVDS_ENABLE_DITHER (1 << 25) 1440 /* Enable border for unscaled (or aspect-scaled) display */ 1441 #define LVDS_BORDER_ENABLE (1 << 15) 1442 /* 1443 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 1444 * pixel. 1445 */ 1446 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) 1447 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) 1448 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 1449 /* 1450 * Controls the A3 data pair, which contains the additional LSBs for 24 bit 1451 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be 1452 * on. 1453 */ 1454 #define LVDS_A3_POWER_MASK (3 << 6) 1455 #define LVDS_A3_POWER_DOWN (0 << 6) 1456 #define LVDS_A3_POWER_UP (3 << 6) 1457 /* 1458 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP 1459 * is set. 1460 */ 1461 #define LVDS_CLKB_POWER_MASK (3 << 4) 1462 #define LVDS_CLKB_POWER_DOWN (0 << 4) 1463 #define LVDS_CLKB_POWER_UP (3 << 4) 1464 /* 1465 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 1466 * setting for whether we are in dual-channel mode. The B3 pair will 1467 * additionally only be powered up when LVDS_A3_POWER_UP is set. 1468 */ 1469 #define LVDS_B0B3_POWER_MASK (3 << 2) 1470 #define LVDS_B0B3_POWER_DOWN (0 << 2) 1471 #define LVDS_B0B3_POWER_UP (3 << 2) 1472 1473 /* Video Data Island Packet control */ 1474 #define VIDEO_DIP_DATA 0x61178 1475 #define VIDEO_DIP_CTL 0x61170 1476 #define VIDEO_DIP_ENABLE (1 << 31) 1477 #define VIDEO_DIP_PORT_B (1 << 29) 1478 #define VIDEO_DIP_PORT_C (2 << 29) 1479 #define VIDEO_DIP_ENABLE_AVI (1 << 21) 1480 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) 1481 #define VIDEO_DIP_ENABLE_SPD (8 << 21) 1482 #define VIDEO_DIP_SELECT_AVI (0 << 19) 1483 #define VIDEO_DIP_SELECT_VENDOR (1 << 19) 1484 #define VIDEO_DIP_SELECT_SPD (3 << 19) 1485 #define VIDEO_DIP_FREQ_ONCE (0 << 16) 1486 #define VIDEO_DIP_FREQ_VSYNC (1 << 16) 1487 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) 1488 1489 /* Panel power sequencing */ 1490 #define PP_STATUS 0x61200 1491 #define PP_ON (1 << 31) 1492 /* 1493 * Indicates that all dependencies of the panel are on: 1494 * 1495 * - PLL enabled 1496 * - pipe enabled 1497 * - LVDS/DVOB/DVOC on 1498 */ 1499 #define PP_READY (1 << 30) 1500 #define PP_SEQUENCE_NONE (0 << 28) 1501 #define PP_SEQUENCE_ON (1 << 28) 1502 #define PP_SEQUENCE_OFF (2 << 28) 1503 #define PP_SEQUENCE_MASK 0x30000000 1504 #define PP_CYCLE_DELAY_ACTIVE (1 << 27) 1505 #define PP_SEQUENCE_STATE_ON_IDLE (1 << 3) 1506 #define PP_SEQUENCE_STATE_MASK 0x0000000f 1507 #define PP_CONTROL 0x61204 1508 #define POWER_TARGET_ON (1 << 0) 1509 #define PP_ON_DELAYS 0x61208 1510 #define PP_OFF_DELAYS 0x6120c 1511 #define PP_DIVISOR 0x61210 1512 1513 /* Panel fitting */ 1514 #define PFIT_CONTROL 0x61230 1515 #define PFIT_ENABLE (1 << 31) 1516 #define PFIT_PIPE_MASK (3 << 29) 1517 #define PFIT_PIPE_SHIFT 29 1518 #define VERT_INTERP_DISABLE (0 << 10) 1519 #define VERT_INTERP_BILINEAR (1 << 10) 1520 #define VERT_INTERP_MASK (3 << 10) 1521 #define VERT_AUTO_SCALE (1 << 9) 1522 #define HORIZ_INTERP_DISABLE (0 << 6) 1523 #define HORIZ_INTERP_BILINEAR (1 << 6) 1524 #define HORIZ_INTERP_MASK (3 << 6) 1525 #define HORIZ_AUTO_SCALE (1 << 5) 1526 #define PANEL_8TO6_DITHER_ENABLE (1 << 3) 1527 #define PFIT_FILTER_FUZZY (0 << 24) 1528 #define PFIT_SCALING_AUTO (0 << 26) 1529 #define PFIT_SCALING_PROGRAMMED (1 << 26) 1530 #define PFIT_SCALING_PILLAR (2 << 26) 1531 #define PFIT_SCALING_LETTER (3 << 26) 1532 #define PFIT_PGM_RATIOS 0x61234 1533 #define PFIT_VERT_SCALE_MASK 0xfff00000 1534 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 1535 /* Pre-965 */ 1536 #define PFIT_VERT_SCALE_SHIFT 20 1537 #define PFIT_VERT_SCALE_MASK 0xfff00000 1538 #define PFIT_HORIZ_SCALE_SHIFT 4 1539 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 1540 /* 965+ */ 1541 #define PFIT_VERT_SCALE_SHIFT_965 16 1542 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000 1543 #define PFIT_HORIZ_SCALE_SHIFT_965 0 1544 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff 1545 1546 #define PFIT_AUTO_RATIOS 0x61238 1547 1548 /* Backlight control */ 1549 #define BLC_PWM_CTL 0x61254 1550 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) 1551 #define BLC_PWM_CTL2 0x61250 /* 965+ only */ 1552 #define BLM_COMBINATION_MODE (1 << 30) 1553 /* 1554 * This is the most significant 15 bits of the number of backlight cycles in a 1555 * complete cycle of the modulated backlight control. 1556 * 1557 * The actual value is this field multiplied by two. 1558 */ 1559 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) 1560 #define BLM_LEGACY_MODE (1 << 16) 1561 /* 1562 * This is the number of cycles out of the backlight modulation cycle for which 1563 * the backlight is on. 1564 * 1565 * This field must be no greater than the number of cycles in the complete 1566 * backlight modulation cycle. 1567 */ 1568 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) 1569 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) 1570 1571 #define BLC_HIST_CTL 0x61260 1572 1573 /* TV port control */ 1574 #define TV_CTL 0x68000 1575 /** Enables the TV encoder */ 1576 # define TV_ENC_ENABLE (1 << 31) 1577 /** Sources the TV encoder input from pipe B instead of A. */ 1578 # define TV_ENC_PIPEB_SELECT (1 << 30) 1579 /** Outputs composite video (DAC A only) */ 1580 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28) 1581 /** Outputs SVideo video (DAC B/C) */ 1582 # define TV_ENC_OUTPUT_SVIDEO (1 << 28) 1583 /** Outputs Component video (DAC A/B/C) */ 1584 # define TV_ENC_OUTPUT_COMPONENT (2 << 28) 1585 /** Outputs Composite and SVideo (DAC A/B/C) */ 1586 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) 1587 # define TV_TRILEVEL_SYNC (1 << 21) 1588 /** Enables slow sync generation (945GM only) */ 1589 # define TV_SLOW_SYNC (1 << 20) 1590 /** Selects 4x oversampling for 480i and 576p */ 1591 # define TV_OVERSAMPLE_4X (0 << 18) 1592 /** Selects 2x oversampling for 720p and 1080i */ 1593 # define TV_OVERSAMPLE_2X (1 << 18) 1594 /** Selects no oversampling for 1080p */ 1595 # define TV_OVERSAMPLE_NONE (2 << 18) 1596 /** Selects 8x oversampling */ 1597 # define TV_OVERSAMPLE_8X (3 << 18) 1598 /** Selects progressive mode rather than interlaced */ 1599 # define TV_PROGRESSIVE (1 << 17) 1600 /** Sets the colorburst to PAL mode. Required for non-M PAL modes. */ 1601 # define TV_PAL_BURST (1 << 16) 1602 /** Field for setting delay of Y compared to C */ 1603 # define TV_YC_SKEW_MASK (7 << 12) 1604 /** Enables a fix for 480p/576p standard definition modes on the 915GM only */ 1605 # define TV_ENC_SDP_FIX (1 << 11) 1606 /** 1607 * Enables a fix for the 915GM only. 1608 * 1609 * Not sure what it does. 1610 */ 1611 # define TV_ENC_C0_FIX (1 << 10) 1612 /** Bits that must be preserved by software */ 1613 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) 1614 # define TV_FUSE_STATE_MASK (3 << 4) 1615 /** Read-only state that reports all features enabled */ 1616 # define TV_FUSE_STATE_ENABLED (0 << 4) 1617 /** Read-only state that reports that Macrovision is disabled in hardware*/ 1618 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4) 1619 /** Read-only state that reports that TV-out is disabled in hardware. */ 1620 # define TV_FUSE_STATE_DISABLED (2 << 4) 1621 /** Normal operation */ 1622 # define TV_TEST_MODE_NORMAL (0 << 0) 1623 /** Encoder test pattern 1 - combo pattern */ 1624 # define TV_TEST_MODE_PATTERN_1 (1 << 0) 1625 /** Encoder test pattern 2 - full screen vertical 75% color bars */ 1626 # define TV_TEST_MODE_PATTERN_2 (2 << 0) 1627 /** Encoder test pattern 3 - full screen horizontal 75% color bars */ 1628 # define TV_TEST_MODE_PATTERN_3 (3 << 0) 1629 /** Encoder test pattern 4 - random noise */ 1630 # define TV_TEST_MODE_PATTERN_4 (4 << 0) 1631 /** Encoder test pattern 5 - linear color ramps */ 1632 # define TV_TEST_MODE_PATTERN_5 (5 << 0) 1633 /** 1634 * This test mode forces the DACs to 50% of full output. 1635 * 1636 * This is used for load detection in combination with TVDAC_SENSE_MASK 1637 */ 1638 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0) 1639 # define TV_TEST_MODE_MASK (7 << 0) 1640 1641 #define TV_DAC 0x68004 1642 # define TV_DAC_SAVE 0x00ffff00 1643 /** 1644 * Reports that DAC state change logic has reported change (RO). 1645 * 1646 * This gets cleared when TV_DAC_STATE_EN is cleared 1647 */ 1648 # define TVDAC_STATE_CHG (1 << 31) 1649 # define TVDAC_SENSE_MASK (7 << 28) 1650 /** Reports that DAC A voltage is above the detect threshold */ 1651 # define TVDAC_A_SENSE (1 << 30) 1652 /** Reports that DAC B voltage is above the detect threshold */ 1653 # define TVDAC_B_SENSE (1 << 29) 1654 /** Reports that DAC C voltage is above the detect threshold */ 1655 # define TVDAC_C_SENSE (1 << 28) 1656 /** 1657 * Enables DAC state detection logic, for load-based TV detection. 1658 * 1659 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set 1660 * to off, for load detection to work. 1661 */ 1662 # define TVDAC_STATE_CHG_EN (1 << 27) 1663 /** Sets the DAC A sense value to high */ 1664 # define TVDAC_A_SENSE_CTL (1 << 26) 1665 /** Sets the DAC B sense value to high */ 1666 # define TVDAC_B_SENSE_CTL (1 << 25) 1667 /** Sets the DAC C sense value to high */ 1668 # define TVDAC_C_SENSE_CTL (1 << 24) 1669 /** Overrides the ENC_ENABLE and DAC voltage levels */ 1670 # define DAC_CTL_OVERRIDE (1 << 7) 1671 /** Sets the slew rate. Must be preserved in software */ 1672 # define ENC_TVDAC_SLEW_FAST (1 << 6) 1673 # define DAC_A_1_3_V (0 << 4) 1674 # define DAC_A_1_1_V (1 << 4) 1675 # define DAC_A_0_7_V (2 << 4) 1676 # define DAC_A_MASK (3 << 4) 1677 # define DAC_B_1_3_V (0 << 2) 1678 # define DAC_B_1_1_V (1 << 2) 1679 # define DAC_B_0_7_V (2 << 2) 1680 # define DAC_B_MASK (3 << 2) 1681 # define DAC_C_1_3_V (0 << 0) 1682 # define DAC_C_1_1_V (1 << 0) 1683 # define DAC_C_0_7_V (2 << 0) 1684 # define DAC_C_MASK (3 << 0) 1685 1686 /** 1687 * CSC coefficients are stored in a floating point format with 9 bits of 1688 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, 1689 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with 1690 * -1 (0x3) being the only legal negative value. 1691 */ 1692 #define TV_CSC_Y 0x68010 1693 # define TV_RY_MASK 0x07ff0000 1694 # define TV_RY_SHIFT 16 1695 # define TV_GY_MASK 0x00000fff 1696 # define TV_GY_SHIFT 0 1697 1698 #define TV_CSC_Y2 0x68014 1699 # define TV_BY_MASK 0x07ff0000 1700 # define TV_BY_SHIFT 16 1701 /** 1702 * Y attenuation for component video. 1703 * 1704 * Stored in 1.9 fixed point. 1705 */ 1706 # define TV_AY_MASK 0x000003ff 1707 # define TV_AY_SHIFT 0 1708 1709 #define TV_CSC_U 0x68018 1710 # define TV_RU_MASK 0x07ff0000 1711 # define TV_RU_SHIFT 16 1712 # define TV_GU_MASK 0x000007ff 1713 # define TV_GU_SHIFT 0 1714 1715 #define TV_CSC_U2 0x6801c 1716 # define TV_BU_MASK 0x07ff0000 1717 # define TV_BU_SHIFT 16 1718 /** 1719 * U attenuation for component video. 1720 * 1721 * Stored in 1.9 fixed point. 1722 */ 1723 # define TV_AU_MASK 0x000003ff 1724 # define TV_AU_SHIFT 0 1725 1726 #define TV_CSC_V 0x68020 1727 # define TV_RV_MASK 0x0fff0000 1728 # define TV_RV_SHIFT 16 1729 # define TV_GV_MASK 0x000007ff 1730 # define TV_GV_SHIFT 0 1731 1732 #define TV_CSC_V2 0x68024 1733 # define TV_BV_MASK 0x07ff0000 1734 # define TV_BV_SHIFT 16 1735 /** 1736 * V attenuation for component video. 1737 * 1738 * Stored in 1.9 fixed point. 1739 */ 1740 # define TV_AV_MASK 0x000007ff 1741 # define TV_AV_SHIFT 0 1742 1743 #define TV_CLR_KNOBS 0x68028 1744 /** 2s-complement brightness adjustment */ 1745 # define TV_BRIGHTNESS_MASK 0xff000000 1746 # define TV_BRIGHTNESS_SHIFT 24 1747 /** Contrast adjustment, as a 2.6 unsigned floating point number */ 1748 # define TV_CONTRAST_MASK 0x00ff0000 1749 # define TV_CONTRAST_SHIFT 16 1750 /** Saturation adjustment, as a 2.6 unsigned floating point number */ 1751 # define TV_SATURATION_MASK 0x0000ff00 1752 # define TV_SATURATION_SHIFT 8 1753 /** Hue adjustment, as an integer phase angle in degrees */ 1754 # define TV_HUE_MASK 0x000000ff 1755 # define TV_HUE_SHIFT 0 1756 1757 #define TV_CLR_LEVEL 0x6802c 1758 /** Controls the DAC level for black */ 1759 # define TV_BLACK_LEVEL_MASK 0x01ff0000 1760 # define TV_BLACK_LEVEL_SHIFT 16 1761 /** Controls the DAC level for blanking */ 1762 # define TV_BLANK_LEVEL_MASK 0x000001ff 1763 # define TV_BLANK_LEVEL_SHIFT 0 1764 1765 #define TV_H_CTL_1 0x68030 1766 /** Number of pixels in the hsync. */ 1767 # define TV_HSYNC_END_MASK 0x1fff0000 1768 # define TV_HSYNC_END_SHIFT 16 1769 /** Total number of pixels minus one in the line (display and blanking). */ 1770 # define TV_HTOTAL_MASK 0x00001fff 1771 # define TV_HTOTAL_SHIFT 0 1772 1773 #define TV_H_CTL_2 0x68034 1774 /** Enables the colorburst (needed for non-component color) */ 1775 # define TV_BURST_ENA (1 << 31) 1776 /** Offset of the colorburst from the start of hsync, in pixels minus one. */ 1777 # define TV_HBURST_START_SHIFT 16 1778 # define TV_HBURST_START_MASK 0x1fff0000 1779 /** Length of the colorburst */ 1780 # define TV_HBURST_LEN_SHIFT 0 1781 # define TV_HBURST_LEN_MASK 0x0001fff 1782 1783 #define TV_H_CTL_3 0x68038 1784 /** End of hblank, measured in pixels minus one from start of hsync */ 1785 # define TV_HBLANK_END_SHIFT 16 1786 # define TV_HBLANK_END_MASK 0x1fff0000 1787 /** Start of hblank, measured in pixels minus one from start of hsync */ 1788 # define TV_HBLANK_START_SHIFT 0 1789 # define TV_HBLANK_START_MASK 0x0001fff 1790 1791 #define TV_V_CTL_1 0x6803c 1792 /** XXX */ 1793 # define TV_NBR_END_SHIFT 16 1794 # define TV_NBR_END_MASK 0x07ff0000 1795 /** XXX */ 1796 # define TV_VI_END_F1_SHIFT 8 1797 # define TV_VI_END_F1_MASK 0x00003f00 1798 /** XXX */ 1799 # define TV_VI_END_F2_SHIFT 0 1800 # define TV_VI_END_F2_MASK 0x0000003f 1801 1802 #define TV_V_CTL_2 0x68040 1803 /** Length of vsync, in half lines */ 1804 # define TV_VSYNC_LEN_MASK 0x07ff0000 1805 # define TV_VSYNC_LEN_SHIFT 16 1806 /** Offset of the start of vsync in field 1, measured in one less than the 1807 * number of half lines. 1808 */ 1809 # define TV_VSYNC_START_F1_MASK 0x00007f00 1810 # define TV_VSYNC_START_F1_SHIFT 8 1811 /** 1812 * Offset of the start of vsync in field 2, measured in one less than the 1813 * number of half lines. 1814 */ 1815 # define TV_VSYNC_START_F2_MASK 0x0000007f 1816 # define TV_VSYNC_START_F2_SHIFT 0 1817 1818 #define TV_V_CTL_3 0x68044 1819 /** Enables generation of the equalization signal */ 1820 # define TV_EQUAL_ENA (1 << 31) 1821 /** Length of vsync, in half lines */ 1822 # define TV_VEQ_LEN_MASK 0x007f0000 1823 # define TV_VEQ_LEN_SHIFT 16 1824 /** Offset of the start of equalization in field 1, measured in one less than 1825 * the number of half lines. 1826 */ 1827 # define TV_VEQ_START_F1_MASK 0x0007f00 1828 # define TV_VEQ_START_F1_SHIFT 8 1829 /** 1830 * Offset of the start of equalization in field 2, measured in one less than 1831 * the number of half lines. 1832 */ 1833 # define TV_VEQ_START_F2_MASK 0x000007f 1834 # define TV_VEQ_START_F2_SHIFT 0 1835 1836 #define TV_V_CTL_4 0x68048 1837 /** 1838 * Offset to start of vertical colorburst, measured in one less than the 1839 * number of lines from vertical start. 1840 */ 1841 # define TV_VBURST_START_F1_MASK 0x003f0000 1842 # define TV_VBURST_START_F1_SHIFT 16 1843 /** 1844 * Offset to the end of vertical colorburst, measured in one less than the 1845 * number of lines from the start of NBR. 1846 */ 1847 # define TV_VBURST_END_F1_MASK 0x000000ff 1848 # define TV_VBURST_END_F1_SHIFT 0 1849 1850 #define TV_V_CTL_5 0x6804c 1851 /** 1852 * Offset to start of vertical colorburst, measured in one less than the 1853 * number of lines from vertical start. 1854 */ 1855 # define TV_VBURST_START_F2_MASK 0x003f0000 1856 # define TV_VBURST_START_F2_SHIFT 16 1857 /** 1858 * Offset to the end of vertical colorburst, measured in one less than the 1859 * number of lines from the start of NBR. 1860 */ 1861 # define TV_VBURST_END_F2_MASK 0x000000ff 1862 # define TV_VBURST_END_F2_SHIFT 0 1863 1864 #define TV_V_CTL_6 0x68050 1865 /** 1866 * Offset to start of vertical colorburst, measured in one less than the 1867 * number of lines from vertical start. 1868 */ 1869 # define TV_VBURST_START_F3_MASK 0x003f0000 1870 # define TV_VBURST_START_F3_SHIFT 16 1871 /** 1872 * Offset to the end of vertical colorburst, measured in one less than the 1873 * number of lines from the start of NBR. 1874 */ 1875 # define TV_VBURST_END_F3_MASK 0x000000ff 1876 # define TV_VBURST_END_F3_SHIFT 0 1877 1878 #define TV_V_CTL_7 0x68054 1879 /** 1880 * Offset to start of vertical colorburst, measured in one less than the 1881 * number of lines from vertical start. 1882 */ 1883 # define TV_VBURST_START_F4_MASK 0x003f0000 1884 # define TV_VBURST_START_F4_SHIFT 16 1885 /** 1886 * Offset to the end of vertical colorburst, measured in one less than the 1887 * number of lines from the start of NBR. 1888 */ 1889 # define TV_VBURST_END_F4_MASK 0x000000ff 1890 # define TV_VBURST_END_F4_SHIFT 0 1891 1892 #define TV_SC_CTL_1 0x68060 1893 /** Turns on the first subcarrier phase generation DDA */ 1894 # define TV_SC_DDA1_EN (1 << 31) 1895 /** Turns on the first subcarrier phase generation DDA */ 1896 # define TV_SC_DDA2_EN (1 << 30) 1897 /** Turns on the first subcarrier phase generation DDA */ 1898 # define TV_SC_DDA3_EN (1 << 29) 1899 /** Sets the subcarrier DDA to reset frequency every other field */ 1900 # define TV_SC_RESET_EVERY_2 (0 << 24) 1901 /** Sets the subcarrier DDA to reset frequency every fourth field */ 1902 # define TV_SC_RESET_EVERY_4 (1 << 24) 1903 /** Sets the subcarrier DDA to reset frequency every eighth field */ 1904 # define TV_SC_RESET_EVERY_8 (2 << 24) 1905 /** Sets the subcarrier DDA to never reset the frequency */ 1906 # define TV_SC_RESET_NEVER (3 << 24) 1907 /** Sets the peak amplitude of the colorburst.*/ 1908 # define TV_BURST_LEVEL_MASK 0x00ff0000 1909 # define TV_BURST_LEVEL_SHIFT 16 1910 /** Sets the increment of the first subcarrier phase generation DDA */ 1911 # define TV_SCDDA1_INC_MASK 0x00000fff 1912 # define TV_SCDDA1_INC_SHIFT 0 1913 1914 #define TV_SC_CTL_2 0x68064 1915 /** Sets the rollover for the second subcarrier phase generation DDA */ 1916 # define TV_SCDDA2_SIZE_MASK 0x7fff0000 1917 # define TV_SCDDA2_SIZE_SHIFT 16 1918 /** Sets the increent of the second subcarrier phase generation DDA */ 1919 # define TV_SCDDA2_INC_MASK 0x00007fff 1920 # define TV_SCDDA2_INC_SHIFT 0 1921 1922 #define TV_SC_CTL_3 0x68068 1923 /** Sets the rollover for the third subcarrier phase generation DDA */ 1924 # define TV_SCDDA3_SIZE_MASK 0x7fff0000 1925 # define TV_SCDDA3_SIZE_SHIFT 16 1926 /** Sets the increent of the third subcarrier phase generation DDA */ 1927 # define TV_SCDDA3_INC_MASK 0x00007fff 1928 # define TV_SCDDA3_INC_SHIFT 0 1929 1930 #define TV_WIN_POS 0x68070 1931 /** X coordinate of the display from the start of horizontal active */ 1932 # define TV_XPOS_MASK 0x1fff0000 1933 # define TV_XPOS_SHIFT 16 1934 /** Y coordinate of the display from the start of vertical active (NBR) */ 1935 # define TV_YPOS_MASK 0x00000fff 1936 # define TV_YPOS_SHIFT 0 1937 1938 #define TV_WIN_SIZE 0x68074 1939 /** Horizontal size of the display window, measured in pixels*/ 1940 # define TV_XSIZE_MASK 0x1fff0000 1941 # define TV_XSIZE_SHIFT 16 1942 /** 1943 * Vertical size of the display window, measured in pixels. 1944 * 1945 * Must be even for interlaced modes. 1946 */ 1947 # define TV_YSIZE_MASK 0x00000fff 1948 # define TV_YSIZE_SHIFT 0 1949 1950 #define TV_FILTER_CTL_1 0x68080 1951 /** 1952 * Enables automatic scaling calculation. 1953 * 1954 * If set, the rest of the registers are ignored, and the calculated values can 1955 * be read back from the register. 1956 */ 1957 # define TV_AUTO_SCALE (1 << 31) 1958 /** 1959 * Disables the vertical filter. 1960 * 1961 * This is required on modes more than 1024 pixels wide */ 1962 # define TV_V_FILTER_BYPASS (1 << 29) 1963 /** Enables adaptive vertical filtering */ 1964 # define TV_VADAPT (1 << 28) 1965 # define TV_VADAPT_MODE_MASK (3 << 26) 1966 /** Selects the least adaptive vertical filtering mode */ 1967 # define TV_VADAPT_MODE_LEAST (0 << 26) 1968 /** Selects the moderately adaptive vertical filtering mode */ 1969 # define TV_VADAPT_MODE_MODERATE (1 << 26) 1970 /** Selects the most adaptive vertical filtering mode */ 1971 # define TV_VADAPT_MODE_MOST (3 << 26) 1972 /** 1973 * Sets the horizontal scaling factor. 1974 * 1975 * This should be the fractional part of the horizontal scaling factor divided 1976 * by the oversampling rate. TV_HSCALE should be less than 1, and set to: 1977 * 1978 * (src width - 1) / ((oversample * dest width) - 1) 1979 */ 1980 # define TV_HSCALE_FRAC_MASK 0x00003fff 1981 # define TV_HSCALE_FRAC_SHIFT 0 1982 1983 #define TV_FILTER_CTL_2 0x68084 1984 /** 1985 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 1986 * 1987 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) 1988 */ 1989 # define TV_VSCALE_INT_MASK 0x00038000 1990 # define TV_VSCALE_INT_SHIFT 15 1991 /** 1992 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 1993 * 1994 * \sa TV_VSCALE_INT_MASK 1995 */ 1996 # define TV_VSCALE_FRAC_MASK 0x00007fff 1997 # define TV_VSCALE_FRAC_SHIFT 0 1998 1999 #define TV_FILTER_CTL_3 0x68088 2000 /** 2001 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 2002 * 2003 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) 2004 * 2005 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 2006 */ 2007 # define TV_VSCALE_IP_INT_MASK 0x00038000 2008 # define TV_VSCALE_IP_INT_SHIFT 15 2009 /** 2010 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 2011 * 2012 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 2013 * 2014 * \sa TV_VSCALE_IP_INT_MASK 2015 */ 2016 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff 2017 # define TV_VSCALE_IP_FRAC_SHIFT 0 2018 2019 #define TV_CC_CONTROL 0x68090 2020 # define TV_CC_ENABLE (1 << 31) 2021 /** 2022 * Specifies which field to send the CC data in. 2023 * 2024 * CC data is usually sent in field 0. 2025 */ 2026 # define TV_CC_FID_MASK (1 << 27) 2027 # define TV_CC_FID_SHIFT 27 2028 /** Sets the horizontal position of the CC data. Usually 135. */ 2029 # define TV_CC_HOFF_MASK 0x03ff0000 2030 # define TV_CC_HOFF_SHIFT 16 2031 /** Sets the vertical position of the CC data. Usually 21 */ 2032 # define TV_CC_LINE_MASK 0x0000003f 2033 # define TV_CC_LINE_SHIFT 0 2034 2035 #define TV_CC_DATA 0x68094 2036 # define TV_CC_RDY (1 << 31) 2037 /** Second word of CC data to be transmitted. */ 2038 # define TV_CC_DATA_2_MASK 0x007f0000 2039 # define TV_CC_DATA_2_SHIFT 16 2040 /** First word of CC data to be transmitted. */ 2041 # define TV_CC_DATA_1_MASK 0x0000007f 2042 # define TV_CC_DATA_1_SHIFT 0 2043 2044 #define TV_H_LUMA_0 0x68100 2045 #define TV_H_LUMA_59 0x681ec 2046 #define TV_H_CHROMA_0 0x68200 2047 #define TV_H_CHROMA_59 0x682ec 2048 #define TV_V_LUMA_0 0x68300 2049 #define TV_V_LUMA_42 0x683a8 2050 #define TV_V_CHROMA_0 0x68400 2051 #define TV_V_CHROMA_42 0x684a8 2052 2053 /* Display Port */ 2054 #define DP_A 0x64000 /* eDP */ 2055 #define DP_B 0x64100 2056 #define DP_C 0x64200 2057 #define DP_D 0x64300 2058 2059 #define DP_PORT_EN (1 << 31) 2060 #define DP_PIPEB_SELECT (1 << 30) 2061 2062 /* Link training mode - select a suitable mode for each stage */ 2063 #define DP_LINK_TRAIN_PAT_1 (0 << 28) 2064 #define DP_LINK_TRAIN_PAT_2 (1 << 28) 2065 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) 2066 #define DP_LINK_TRAIN_OFF (3 << 28) 2067 #define DP_LINK_TRAIN_MASK (3 << 28) 2068 #define DP_LINK_TRAIN_SHIFT 28 2069 2070 /* CPT Link training mode */ 2071 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) 2072 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) 2073 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) 2074 #define DP_LINK_TRAIN_OFF_CPT (3 << 8) 2075 #define DP_LINK_TRAIN_MASK_CPT (7 << 8) 2076 #define DP_LINK_TRAIN_SHIFT_CPT 8 2077 2078 /* Signal voltages. These are mostly controlled by the other end */ 2079 #define DP_VOLTAGE_0_4 (0 << 25) 2080 #define DP_VOLTAGE_0_6 (1 << 25) 2081 #define DP_VOLTAGE_0_8 (2 << 25) 2082 #define DP_VOLTAGE_1_2 (3 << 25) 2083 #define DP_VOLTAGE_MASK (7 << 25) 2084 #define DP_VOLTAGE_SHIFT 25 2085 2086 /* Signal pre-emphasis levels, like voltages, the other end tells us what 2087 * they want 2088 */ 2089 #define DP_PRE_EMPHASIS_0 (0 << 22) 2090 #define DP_PRE_EMPHASIS_3_5 (1 << 22) 2091 #define DP_PRE_EMPHASIS_6 (2 << 22) 2092 #define DP_PRE_EMPHASIS_9_5 (3 << 22) 2093 #define DP_PRE_EMPHASIS_MASK (7 << 22) 2094 #define DP_PRE_EMPHASIS_SHIFT 22 2095 2096 /* How many wires to use. I guess 3 was too hard */ 2097 #define DP_PORT_WIDTH_1 (0 << 19) 2098 #define DP_PORT_WIDTH_2 (1 << 19) 2099 #define DP_PORT_WIDTH_4 (3 << 19) 2100 #define DP_PORT_WIDTH_MASK (7 << 19) 2101 2102 /* Mystic DPCD version 1.1 special mode */ 2103 #define DP_ENHANCED_FRAMING (1 << 18) 2104 2105 /* eDP */ 2106 #define DP_PLL_FREQ_270MHZ (0 << 16) 2107 #define DP_PLL_FREQ_160MHZ (1 << 16) 2108 #define DP_PLL_FREQ_MASK (3 << 16) 2109 2110 /** locked once port is enabled */ 2111 #define DP_PORT_REVERSAL (1 << 15) 2112 2113 /* eDP */ 2114 #define DP_PLL_ENABLE (1 << 14) 2115 2116 /** sends the clock on lane 15 of the PEG for debug */ 2117 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) 2118 2119 #define DP_SCRAMBLING_DISABLE (1 << 12) 2120 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) 2121 2122 /** limit RGB values to avoid confusing TVs */ 2123 #define DP_COLOR_RANGE_16_235 (1 << 8) 2124 2125 /** Turn on the audio link */ 2126 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) 2127 2128 /** vs and hs sync polarity */ 2129 #define DP_SYNC_VS_HIGH (1 << 4) 2130 #define DP_SYNC_HS_HIGH (1 << 3) 2131 2132 /** A fantasy */ 2133 #define DP_DETECTED (1 << 2) 2134 2135 /** The aux channel provides a way to talk to the 2136 * signal sink for DDC etc. Max packet size supported 2137 * is 20 bytes in each direction, hence the 5 fixed 2138 * data registers 2139 */ 2140 #define DPA_AUX_CH_CTL 0x64010 2141 #define DPA_AUX_CH_DATA1 0x64014 2142 #define DPA_AUX_CH_DATA2 0x64018 2143 #define DPA_AUX_CH_DATA3 0x6401c 2144 #define DPA_AUX_CH_DATA4 0x64020 2145 #define DPA_AUX_CH_DATA5 0x64024 2146 2147 #define DPB_AUX_CH_CTL 0x64110 2148 #define DPB_AUX_CH_DATA1 0x64114 2149 #define DPB_AUX_CH_DATA2 0x64118 2150 #define DPB_AUX_CH_DATA3 0x6411c 2151 #define DPB_AUX_CH_DATA4 0x64120 2152 #define DPB_AUX_CH_DATA5 0x64124 2153 2154 #define DPC_AUX_CH_CTL 0x64210 2155 #define DPC_AUX_CH_DATA1 0x64214 2156 #define DPC_AUX_CH_DATA2 0x64218 2157 #define DPC_AUX_CH_DATA3 0x6421c 2158 #define DPC_AUX_CH_DATA4 0x64220 2159 #define DPC_AUX_CH_DATA5 0x64224 2160 2161 #define DPD_AUX_CH_CTL 0x64310 2162 #define DPD_AUX_CH_DATA1 0x64314 2163 #define DPD_AUX_CH_DATA2 0x64318 2164 #define DPD_AUX_CH_DATA3 0x6431c 2165 #define DPD_AUX_CH_DATA4 0x64320 2166 #define DPD_AUX_CH_DATA5 0x64324 2167 2168 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) 2169 #define DP_AUX_CH_CTL_DONE (1 << 30) 2170 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) 2171 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) 2172 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) 2173 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) 2174 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) 2175 #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26) 2176 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) 2177 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) 2178 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) 2179 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 2180 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) 2181 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 2182 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) 2183 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) 2184 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) 2185 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) 2186 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) 2187 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) 2188 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 2189 2190 /* 2191 * Computing GMCH M and N values for the Display Port link 2192 * 2193 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes 2194 * 2195 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) 2196 * 2197 * The GMCH value is used internally 2198 * 2199 * bytes_per_pixel is the number of bytes coming out of the plane, 2200 * which is after the LUTs, so we want the bytes for our color format. 2201 * For our current usage, this is always 3, one byte for R, G and B. 2202 */ 2203 #define PIPEA_GMCH_DATA_M 0x70050 2204 #define PIPEB_GMCH_DATA_M 0x71050 2205 2206 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ 2207 #define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25) 2208 #define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25 2209 2210 #define PIPE_GMCH_DATA_M_MASK (0xffffff) 2211 2212 #define PIPEA_GMCH_DATA_N 0x70054 2213 #define PIPEB_GMCH_DATA_N 0x71054 2214 #define PIPE_GMCH_DATA_N_MASK (0xffffff) 2215 2216 /* 2217 * Computing Link M and N values for the Display Port link 2218 * 2219 * Link M / N = pixel_clock / ls_clk 2220 * 2221 * (the DP spec calls pixel_clock the 'strm_clk') 2222 * 2223 * The Link value is transmitted in the Main Stream 2224 * Attributes and VB-ID. 2225 */ 2226 2227 #define PIPEA_DP_LINK_M 0x70060 2228 #define PIPEB_DP_LINK_M 0x71060 2229 #define PIPEA_DP_LINK_M_MASK (0xffffff) 2230 2231 #define PIPEA_DP_LINK_N 0x70064 2232 #define PIPEB_DP_LINK_N 0x71064 2233 #define PIPEA_DP_LINK_N_MASK (0xffffff) 2234 2235 /* Display & cursor control */ 2236 2237 /* Pipe A */ 2238 #define PIPEADSL 0x70000 2239 #define DSL_LINEMASK 0x00000fff 2240 #define PIPEACONF 0x70008 2241 #define PIPECONF_ENABLE (1<<31) 2242 #define PIPECONF_DISABLE 0 2243 #define PIPECONF_DOUBLE_WIDE (1<<30) 2244 #define I965_PIPECONF_ACTIVE (1<<30) 2245 #define PIPECONF_SINGLE_WIDE 0 2246 #define PIPECONF_PIPE_UNLOCKED 0 2247 #define PIPECONF_PIPE_LOCKED (1<<25) 2248 #define PIPECONF_PALETTE 0 2249 #define PIPECONF_GAMMA (1<<24) 2250 #define PIPECONF_FORCE_BORDER (1<<25) 2251 #define PIPECONF_PROGRESSIVE (0 << 21) 2252 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 2253 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) 2254 #define PIPECONF_CXSR_DOWNCLOCK (1<<16) 2255 #define PIPECONF_BPP_MASK (0x000000e0) 2256 #define PIPECONF_BPP_8 (0<<5) 2257 #define PIPECONF_BPP_10 (1<<5) 2258 #define PIPECONF_BPP_6 (2<<5) 2259 #define PIPECONF_BPP_12 (3<<5) 2260 #define PIPECONF_DITHER_EN (1<<4) 2261 #define PIPECONF_DITHER_TYPE_MASK (0x0000000c) 2262 #define PIPECONF_DITHER_TYPE_SP (0<<2) 2263 #define PIPECONF_DITHER_TYPE_ST1 (1<<2) 2264 #define PIPECONF_DITHER_TYPE_ST2 (2<<2) 2265 #define PIPECONF_DITHER_TYPE_TEMP (3<<2) 2266 #define PIPEASTAT 0x70024 2267 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) 2268 #define PIPE_CRC_ERROR_ENABLE (1UL<<29) 2269 #define PIPE_CRC_DONE_ENABLE (1UL<<28) 2270 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) 2271 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) 2272 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) 2273 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) 2274 #define PIPE_DPST_EVENT_ENABLE (1UL<<23) 2275 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) 2276 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) 2277 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) 2278 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ 2279 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ 2280 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) 2281 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) 2282 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) 2283 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) 2284 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) 2285 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) 2286 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) 2287 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) 2288 #define PIPE_DPST_EVENT_STATUS (1UL<<7) 2289 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) 2290 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) 2291 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) 2292 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ 2293 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ 2294 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) 2295 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) 2296 #define PIPE_BPC_MASK (7 << 5) /* Ironlake */ 2297 #define PIPE_8BPC (0 << 5) 2298 #define PIPE_10BPC (1 << 5) 2299 #define PIPE_6BPC (2 << 5) 2300 #define PIPE_12BPC (3 << 5) 2301 2302 #define PIPESRC(pipe) _PIPE(pipe, PIPEASRC, PIPEBSRC) 2303 #define PIPECONF(pipe) _PIPE(pipe, PIPEACONF, PIPEBCONF) 2304 #define PIPEDSL(pipe) _PIPE(pipe, PIPEADSL, PIPEBDSL) 2305 #define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, PIPEAFRAMEPIXEL, PIPEBFRAMEPIXEL) 2306 2307 #define DSPARB 0x70030 2308 #define DSPARB_CSTART_MASK (0x7f << 7) 2309 #define DSPARB_CSTART_SHIFT 7 2310 #define DSPARB_BSTART_MASK (0x7f) 2311 #define DSPARB_BSTART_SHIFT 0 2312 #define DSPARB_BEND_SHIFT 9 /* on 855 */ 2313 #define DSPARB_AEND_SHIFT 0 2314 2315 #define DSPFW1 0x70034 2316 #define DSPFW_SR_SHIFT 23 2317 #define DSPFW_SR_MASK (0x1ff<<23) 2318 #define DSPFW_CURSORB_SHIFT 16 2319 #define DSPFW_CURSORB_MASK (0x3f<<16) 2320 #define DSPFW_PLANEB_SHIFT 8 2321 #define DSPFW_PLANEB_MASK (0x7f<<8) 2322 #define DSPFW_PLANEA_MASK (0x7f) 2323 #define DSPFW2 0x70038 2324 #define DSPFW_CURSORA_MASK 0x00003f00 2325 #define DSPFW_CURSORA_SHIFT 8 2326 #define DSPFW_PLANEC_MASK (0x7f) 2327 #define DSPFW3 0x7003c 2328 #define DSPFW_HPLL_SR_EN (1<<31) 2329 #define DSPFW_CURSOR_SR_SHIFT 24 2330 #define PINEVIEW_SELF_REFRESH_EN (1<<30) 2331 #define DSPFW_CURSOR_SR_MASK (0x3f<<24) 2332 #define DSPFW_HPLL_CURSOR_SHIFT 16 2333 #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) 2334 #define DSPFW_HPLL_SR_MASK (0x1ff) 2335 2336 /* FIFO watermark sizes etc */ 2337 #define G4X_FIFO_LINE_SIZE 64 2338 #define I915_FIFO_LINE_SIZE 64 2339 #define I830_FIFO_LINE_SIZE 32 2340 2341 #define G4X_FIFO_SIZE 127 2342 #define I965_FIFO_SIZE 512 2343 #define I945_FIFO_SIZE 127 2344 #define I915_FIFO_SIZE 95 2345 #define I855GM_FIFO_SIZE 127 /* In cachelines */ 2346 #define I830_FIFO_SIZE 95 2347 2348 #define G4X_MAX_WM 0x3f 2349 #define I915_MAX_WM 0x3f 2350 2351 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ 2352 #define PINEVIEW_FIFO_LINE_SIZE 64 2353 #define PINEVIEW_MAX_WM 0x1ff 2354 #define PINEVIEW_DFT_WM 0x3f 2355 #define PINEVIEW_DFT_HPLLOFF_WM 0 2356 #define PINEVIEW_GUARD_WM 10 2357 #define PINEVIEW_CURSOR_FIFO 64 2358 #define PINEVIEW_CURSOR_MAX_WM 0x3f 2359 #define PINEVIEW_CURSOR_DFT_WM 0 2360 #define PINEVIEW_CURSOR_GUARD_WM 5 2361 2362 #define I965_CURSOR_FIFO 64 2363 #define I965_CURSOR_MAX_WM 32 2364 #define I965_CURSOR_DFT_WM 8 2365 2366 /* define the Watermark register on Ironlake */ 2367 #define WM0_PIPEA_ILK 0x45100 2368 #define WM0_PIPE_PLANE_MASK (0x7f<<16) 2369 #define WM0_PIPE_PLANE_SHIFT 16 2370 #define WM0_PIPE_SPRITE_MASK (0x3f<<8) 2371 #define WM0_PIPE_SPRITE_SHIFT 8 2372 #define WM0_PIPE_CURSOR_MASK (0x1f) 2373 2374 #define WM0_PIPEB_ILK 0x45104 2375 #define WM1_LP_ILK 0x45108 2376 #define WM1_LP_SR_EN (1<<31) 2377 #define WM1_LP_LATENCY_SHIFT 24 2378 #define WM1_LP_LATENCY_MASK (0x7f<<24) 2379 #define WM1_LP_FBC_MASK (0xf<<20) 2380 #define WM1_LP_FBC_SHIFT 20 2381 #define WM1_LP_SR_MASK (0x1ff<<8) 2382 #define WM1_LP_SR_SHIFT 8 2383 #define WM1_LP_CURSOR_MASK (0x3f) 2384 #define WM2_LP_ILK 0x4510c 2385 #define WM2_LP_EN (1<<31) 2386 #define WM3_LP_ILK 0x45110 2387 #define WM3_LP_EN (1<<31) 2388 #define WM1S_LP_ILK 0x45120 2389 #define WM1S_LP_EN (1<<31) 2390 2391 /* Memory latency timer register */ 2392 #define MLTR_ILK 0x11222 2393 #define MLTR_WM1_SHIFT 0 2394 #define MLTR_WM2_SHIFT 8 2395 /* the unit of memory self-refresh latency time is 0.5us */ 2396 #define ILK_SRLT_MASK 0x3f 2397 #define ILK_LATENCY(shift) (I915_READ(MLTR_ILK) >> (shift) & ILK_SRLT_MASK) 2398 #define ILK_READ_WM1_LATENCY() ILK_LATENCY(MLTR_WM1_SHIFT) 2399 #define ILK_READ_WM2_LATENCY() ILK_LATENCY(MLTR_WM2_SHIFT) 2400 2401 /* define the fifo size on Ironlake */ 2402 #define ILK_DISPLAY_FIFO 128 2403 #define ILK_DISPLAY_MAXWM 64 2404 #define ILK_DISPLAY_DFTWM 8 2405 #define ILK_CURSOR_FIFO 32 2406 #define ILK_CURSOR_MAXWM 16 2407 #define ILK_CURSOR_DFTWM 8 2408 2409 #define ILK_DISPLAY_SR_FIFO 512 2410 #define ILK_DISPLAY_MAX_SRWM 0x1ff 2411 #define ILK_DISPLAY_DFT_SRWM 0x3f 2412 #define ILK_CURSOR_SR_FIFO 64 2413 #define ILK_CURSOR_MAX_SRWM 0x3f 2414 #define ILK_CURSOR_DFT_SRWM 8 2415 2416 #define ILK_FIFO_LINE_SIZE 64 2417 2418 /* define the WM info on Sandybridge */ 2419 #define SNB_DISPLAY_FIFO 128 2420 #define SNB_DISPLAY_MAXWM 0x7f /* bit 16:22 */ 2421 #define SNB_DISPLAY_DFTWM 8 2422 #define SNB_CURSOR_FIFO 32 2423 #define SNB_CURSOR_MAXWM 0x1f /* bit 4:0 */ 2424 #define SNB_CURSOR_DFTWM 8 2425 2426 #define SNB_DISPLAY_SR_FIFO 512 2427 #define SNB_DISPLAY_MAX_SRWM 0x1ff /* bit 16:8 */ 2428 #define SNB_DISPLAY_DFT_SRWM 0x3f 2429 #define SNB_CURSOR_SR_FIFO 64 2430 #define SNB_CURSOR_MAX_SRWM 0x3f /* bit 5:0 */ 2431 #define SNB_CURSOR_DFT_SRWM 8 2432 2433 #define SNB_FBC_MAX_SRWM 0xf /* bit 23:20 */ 2434 2435 #define SNB_FIFO_LINE_SIZE 64 2436 2437 2438 /* the address where we get all kinds of latency value */ 2439 #define SSKPD 0x5d10 2440 #define SSKPD_WM_MASK 0x3f 2441 #define SSKPD_WM0_SHIFT 0 2442 #define SSKPD_WM1_SHIFT 8 2443 #define SSKPD_WM2_SHIFT 16 2444 #define SSKPD_WM3_SHIFT 24 2445 2446 #define SNB_LATENCY(shift) (I915_READ(MCHBAR_MIRROR_BASE_SNB + SSKPD) >> (shift) & SSKPD_WM_MASK) 2447 #define SNB_READ_WM0_LATENCY() SNB_LATENCY(SSKPD_WM0_SHIFT) 2448 #define SNB_READ_WM1_LATENCY() SNB_LATENCY(SSKPD_WM1_SHIFT) 2449 #define SNB_READ_WM2_LATENCY() SNB_LATENCY(SSKPD_WM2_SHIFT) 2450 #define SNB_READ_WM3_LATENCY() SNB_LATENCY(SSKPD_WM3_SHIFT) 2451 2452 /* 2453 * The two pipe frame counter registers are not synchronized, so 2454 * reading a stable value is somewhat tricky. The following code 2455 * should work: 2456 * 2457 * do { 2458 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 2459 * PIPE_FRAME_HIGH_SHIFT; 2460 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> 2461 * PIPE_FRAME_LOW_SHIFT); 2462 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 2463 * PIPE_FRAME_HIGH_SHIFT); 2464 * } while (high1 != high2); 2465 * frame = (high1 << 8) | low1; 2466 */ 2467 #define PIPEAFRAMEHIGH 0x70040 2468 #define PIPE_FRAME_HIGH_MASK 0x0000ffff 2469 #define PIPE_FRAME_HIGH_SHIFT 0 2470 #define PIPEAFRAMEPIXEL 0x70044 2471 #define PIPE_FRAME_LOW_MASK 0xff000000 2472 #define PIPE_FRAME_LOW_SHIFT 24 2473 #define PIPE_PIXEL_MASK 0x00ffffff 2474 #define PIPE_PIXEL_SHIFT 0 2475 /* GM45+ just has to be different */ 2476 #define PIPEA_FRMCOUNT_GM45 0x70040 2477 #define PIPEA_FLIPCOUNT_GM45 0x70044 2478 2479 /* Cursor A & B regs */ 2480 #define CURACNTR 0x70080 2481 /* Old style CUR*CNTR flags (desktop 8xx) */ 2482 #define CURSOR_ENABLE 0x80000000 2483 #define CURSOR_GAMMA_ENABLE 0x40000000 2484 #define CURSOR_STRIDE_MASK 0x30000000 2485 #define CURSOR_FORMAT_SHIFT 24 2486 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) 2487 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) 2488 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) 2489 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) 2490 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) 2491 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) 2492 /* New style CUR*CNTR flags */ 2493 #define CURSOR_MODE 0x27 2494 #define CURSOR_MODE_DISABLE 0x00 2495 #define CURSOR_MODE_64_32B_AX 0x07 2496 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) 2497 #define MCURSOR_PIPE_SELECT (1 << 28) 2498 #define MCURSOR_PIPE_A 0x00 2499 #define MCURSOR_PIPE_B (1 << 28) 2500 #define MCURSOR_GAMMA_ENABLE (1 << 26) 2501 #define CURABASE 0x70084 2502 #define CURAPOS 0x70088 2503 #define CURSOR_POS_MASK 0x007FF 2504 #define CURSOR_POS_SIGN 0x8000 2505 #define CURSOR_X_SHIFT 0 2506 #define CURSOR_Y_SHIFT 16 2507 #define CURSIZE 0x700a0 2508 #define CURBCNTR 0x700c0 2509 #define CURBBASE 0x700c4 2510 #define CURBPOS 0x700c8 2511 2512 #define CURCNTR(pipe) _PIPE(pipe, CURACNTR, CURBCNTR) 2513 #define CURBASE(pipe) _PIPE(pipe, CURABASE, CURBBASE) 2514 #define CURPOS(pipe) _PIPE(pipe, CURAPOS, CURBPOS) 2515 2516 /* Display A control */ 2517 #define DSPACNTR 0x70180 2518 #define DISPLAY_PLANE_ENABLE (1<<31) 2519 #define DISPLAY_PLANE_DISABLE 0 2520 #define DISPPLANE_GAMMA_ENABLE (1<<30) 2521 #define DISPPLANE_GAMMA_DISABLE 0 2522 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26) 2523 #define DISPPLANE_8BPP (0x2<<26) 2524 #define DISPPLANE_15_16BPP (0x4<<26) 2525 #define DISPPLANE_16BPP (0x5<<26) 2526 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) 2527 #define DISPPLANE_32BPP (0x7<<26) 2528 #define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26) 2529 #define DISPPLANE_STEREO_ENABLE (1<<25) 2530 #define DISPPLANE_STEREO_DISABLE 0 2531 #define DISPPLANE_SEL_PIPE_MASK (1<<24) 2532 #define DISPPLANE_SEL_PIPE_A 0 2533 #define DISPPLANE_SEL_PIPE_B (1<<24) 2534 #define DISPPLANE_SRC_KEY_ENABLE (1<<22) 2535 #define DISPPLANE_SRC_KEY_DISABLE 0 2536 #define DISPPLANE_LINE_DOUBLE (1<<20) 2537 #define DISPPLANE_NO_LINE_DOUBLE 0 2538 #define DISPPLANE_STEREO_POLARITY_FIRST 0 2539 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) 2540 #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ 2541 #define DISPPLANE_TILED (1<<10) 2542 #define DSPAADDR 0x70184 2543 #define DSPASTRIDE 0x70188 2544 #define DSPAPOS 0x7018C /* reserved */ 2545 #define DSPASIZE 0x70190 2546 #define DSPASURF 0x7019C /* 965+ only */ 2547 #define DSPATILEOFF 0x701A4 /* 965+ only */ 2548 2549 #define DSPCNTR(plane) _PIPE(plane, DSPACNTR, DSPBCNTR) 2550 #define DSPADDR(plane) _PIPE(plane, DSPAADDR, DSPBADDR) 2551 #define DSPSTRIDE(plane) _PIPE(plane, DSPASTRIDE, DSPBSTRIDE) 2552 #define DSPPOS(plane) _PIPE(plane, DSPAPOS, DSPBPOS) 2553 #define DSPSIZE(plane) _PIPE(plane, DSPASIZE, DSPBSIZE) 2554 #define DSPSURF(plane) _PIPE(plane, DSPASURF, DSPBSURF) 2555 #define DSPTILEOFF(plane) _PIPE(plane, DSPATILEOFF, DSPBTILEOFF) 2556 2557 /* VBIOS flags */ 2558 #define SWF00 0x71410 2559 #define SWF01 0x71414 2560 #define SWF02 0x71418 2561 #define SWF03 0x7141c 2562 #define SWF04 0x71420 2563 #define SWF05 0x71424 2564 #define SWF06 0x71428 2565 #define SWF10 0x70410 2566 #define SWF11 0x70414 2567 #define SWF14 0x71420 2568 #define SWF30 0x72414 2569 #define SWF31 0x72418 2570 #define SWF32 0x7241c 2571 2572 /* Pipe B */ 2573 #define PIPEBDSL 0x71000 2574 #define PIPEBCONF 0x71008 2575 #define PIPEBSTAT 0x71024 2576 #define PIPEBFRAMEHIGH 0x71040 2577 #define PIPEBFRAMEPIXEL 0x71044 2578 #define PIPEB_FRMCOUNT_GM45 0x71040 2579 #define PIPEB_FLIPCOUNT_GM45 0x71044 2580 2581 2582 /* Display B control */ 2583 #define DSPBCNTR 0x71180 2584 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) 2585 #define DISPPLANE_ALPHA_TRANS_DISABLE 0 2586 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 2587 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 2588 #define DSPBADDR 0x71184 2589 #define DSPBSTRIDE 0x71188 2590 #define DSPBPOS 0x7118C 2591 #define DSPBSIZE 0x71190 2592 #define DSPBSURF 0x7119C 2593 #define DSPBTILEOFF 0x711A4 2594 2595 /* VBIOS regs */ 2596 #define VGACNTRL 0x71400 2597 # define VGA_DISP_DISABLE (1 << 31) 2598 # define VGA_2X_MODE (1 << 30) 2599 # define VGA_PIPE_B_SELECT (1 << 29) 2600 2601 /* Ironlake */ 2602 2603 #define CPU_VGACNTRL 0x41000 2604 2605 #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 2606 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) 2607 #define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2) 2608 #define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2) 2609 #define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2) 2610 #define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2) 2611 #define DIGITAL_PORTA_NO_DETECT (0 << 0) 2612 #define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1) 2613 #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0) 2614 2615 /* refresh rate hardware control */ 2616 #define RR_HW_CTL 0x45300 2617 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff 2618 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 2619 2620 #define FDI_PLL_BIOS_0 0x46000 2621 #define FDI_PLL_FB_CLOCK_MASK 0xff 2622 #define FDI_PLL_BIOS_1 0x46004 2623 #define FDI_PLL_BIOS_2 0x46008 2624 #define DISPLAY_PORT_PLL_BIOS_0 0x4600c 2625 #define DISPLAY_PORT_PLL_BIOS_1 0x46010 2626 #define DISPLAY_PORT_PLL_BIOS_2 0x46014 2627 2628 #define PCH_DSPCLK_GATE_D 0x42020 2629 # define DPFDUNIT_CLOCK_GATE_DISABLE (1 << 7) 2630 # define DPARBUNIT_CLOCK_GATE_DISABLE (1 << 5) 2631 2632 #define PCH_3DCGDIS0 0x46020 2633 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) 2634 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) 2635 2636 #define PCH_3DCGDIS1 0x46024 2637 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) 2638 2639 #define FDI_PLL_FREQ_CTL 0x46030 2640 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) 2641 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 2642 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff 2643 2644 2645 #define PIPEA_DATA_M1 0x60030 2646 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ 2647 #define TU_SIZE_MASK 0x7e000000 2648 #define PIPE_DATA_M1_OFFSET 0 2649 #define PIPEA_DATA_N1 0x60034 2650 #define PIPE_DATA_N1_OFFSET 0 2651 2652 #define PIPEA_DATA_M2 0x60038 2653 #define PIPE_DATA_M2_OFFSET 0 2654 #define PIPEA_DATA_N2 0x6003c 2655 #define PIPE_DATA_N2_OFFSET 0 2656 2657 #define PIPEA_LINK_M1 0x60040 2658 #define PIPE_LINK_M1_OFFSET 0 2659 #define PIPEA_LINK_N1 0x60044 2660 #define PIPE_LINK_N1_OFFSET 0 2661 2662 #define PIPEA_LINK_M2 0x60048 2663 #define PIPE_LINK_M2_OFFSET 0 2664 #define PIPEA_LINK_N2 0x6004c 2665 #define PIPE_LINK_N2_OFFSET 0 2666 2667 /* PIPEB timing regs are same start from 0x61000 */ 2668 2669 #define PIPEB_DATA_M1 0x61030 2670 #define PIPEB_DATA_N1 0x61034 2671 2672 #define PIPEB_DATA_M2 0x61038 2673 #define PIPEB_DATA_N2 0x6103c 2674 2675 #define PIPEB_LINK_M1 0x61040 2676 #define PIPEB_LINK_N1 0x61044 2677 2678 #define PIPEB_LINK_M2 0x61048 2679 #define PIPEB_LINK_N2 0x6104c 2680 2681 #define PIPE_DATA_M1(pipe) _PIPE(pipe, PIPEA_DATA_M1, PIPEB_DATA_M1) 2682 #define PIPE_DATA_N1(pipe) _PIPE(pipe, PIPEA_DATA_N1, PIPEB_DATA_N1) 2683 #define PIPE_DATA_M2(pipe) _PIPE(pipe, PIPEA_DATA_M2, PIPEB_DATA_M2) 2684 #define PIPE_DATA_N2(pipe) _PIPE(pipe, PIPEA_DATA_N2, PIPEB_DATA_N2) 2685 #define PIPE_LINK_M1(pipe) _PIPE(pipe, PIPEA_LINK_M1, PIPEB_LINK_M1) 2686 #define PIPE_LINK_N1(pipe) _PIPE(pipe, PIPEA_LINK_N1, PIPEB_LINK_N1) 2687 #define PIPE_LINK_M2(pipe) _PIPE(pipe, PIPEA_LINK_M2, PIPEB_LINK_M2) 2688 #define PIPE_LINK_N2(pipe) _PIPE(pipe, PIPEA_LINK_N2, PIPEB_LINK_N2) 2689 2690 /* CPU panel fitter */ 2691 #define PFA_CTL_1 0x68080 2692 #define PFB_CTL_1 0x68880 2693 #define PF_ENABLE (1<<31) 2694 #define PF_FILTER_MASK (3<<23) 2695 #define PF_FILTER_PROGRAMMED (0<<23) 2696 #define PF_FILTER_MED_3x3 (1<<23) 2697 #define PF_FILTER_EDGE_ENHANCE (2<<23) 2698 #define PF_FILTER_EDGE_SOFTEN (3<<23) 2699 #define PFA_WIN_SZ 0x68074 2700 #define PFB_WIN_SZ 0x68874 2701 #define PFA_WIN_POS 0x68070 2702 #define PFB_WIN_POS 0x68870 2703 2704 /* legacy palette */ 2705 #define LGC_PALETTE_A 0x4a000 2706 #define LGC_PALETTE_B 0x4a800 2707 2708 /* interrupts */ 2709 #define DE_MASTER_IRQ_CONTROL (1 << 31) 2710 #define DE_SPRITEB_FLIP_DONE (1 << 29) 2711 #define DE_SPRITEA_FLIP_DONE (1 << 28) 2712 #define DE_PLANEB_FLIP_DONE (1 << 27) 2713 #define DE_PLANEA_FLIP_DONE (1 << 26) 2714 #define DE_PCU_EVENT (1 << 25) 2715 #define DE_GTT_FAULT (1 << 24) 2716 #define DE_POISON (1 << 23) 2717 #define DE_PERFORM_COUNTER (1 << 22) 2718 #define DE_PCH_EVENT (1 << 21) 2719 #define DE_AUX_CHANNEL_A (1 << 20) 2720 #define DE_DP_A_HOTPLUG (1 << 19) 2721 #define DE_GSE (1 << 18) 2722 #define DE_PIPEB_VBLANK (1 << 15) 2723 #define DE_PIPEB_EVEN_FIELD (1 << 14) 2724 #define DE_PIPEB_ODD_FIELD (1 << 13) 2725 #define DE_PIPEB_LINE_COMPARE (1 << 12) 2726 #define DE_PIPEB_VSYNC (1 << 11) 2727 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) 2728 #define DE_PIPEA_VBLANK (1 << 7) 2729 #define DE_PIPEA_EVEN_FIELD (1 << 6) 2730 #define DE_PIPEA_ODD_FIELD (1 << 5) 2731 #define DE_PIPEA_LINE_COMPARE (1 << 4) 2732 #define DE_PIPEA_VSYNC (1 << 3) 2733 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) 2734 2735 #define DEISR 0x44000 2736 #define DEIMR 0x44004 2737 #define DEIIR 0x44008 2738 #define DEIER 0x4400c 2739 2740 /* GT interrupt */ 2741 #define GT_PIPE_NOTIFY (1 << 4) 2742 #define GT_SYNC_STATUS (1 << 2) 2743 #define GT_USER_INTERRUPT (1 << 0) 2744 #define GT_BSD_USER_INTERRUPT (1 << 5) 2745 #define GT_GEN6_BSD_USER_INTERRUPT (1 << 12) 2746 #define GT_BLT_USER_INTERRUPT (1 << 22) 2747 2748 #define GTISR 0x44010 2749 #define GTIMR 0x44014 2750 #define GTIIR 0x44018 2751 #define GTIER 0x4401c 2752 2753 #define ILK_DISPLAY_CHICKEN2 0x42004 2754 /* Required on all Ironlake and Sandybridge according to the B-Spec. */ 2755 #define ILK_ELPIN_409_SELECT (1 << 25) 2756 #define ILK_DPARB_GATE (1<<22) 2757 #define ILK_VSDPFD_FULL (1<<21) 2758 #define ILK_DISPLAY_CHICKEN_FUSES 0x42014 2759 #define ILK_INTERNAL_GRAPHICS_DISABLE (1<<31) 2760 #define ILK_INTERNAL_DISPLAY_DISABLE (1<<30) 2761 #define ILK_DISPLAY_DEBUG_DISABLE (1<<29) 2762 #define ILK_HDCP_DISABLE (1<<25) 2763 #define ILK_eDP_A_DISABLE (1<<24) 2764 #define ILK_DESKTOP (1<<23) 2765 #define ILK_DSPCLK_GATE 0x42020 2766 #define ILK_DPARB_CLK_GATE (1<<5) 2767 #define ILK_DPFD_CLK_GATE (1<<7) 2768 2769 /* According to spec this bit 7/8/9 of 0x42020 should be set to enable FBC */ 2770 #define ILK_CLK_FBC (1<<7) 2771 #define ILK_DPFC_DIS1 (1<<8) 2772 #define ILK_DPFC_DIS2 (1<<9) 2773 2774 #define DISP_ARB_CTL 0x45000 2775 #define DISP_TILE_SURFACE_SWIZZLING (1<<13) 2776 #define DISP_FBC_WM_DIS (1<<15) 2777 2778 /* PCH */ 2779 2780 /* south display engine interrupt */ 2781 #define SDE_AUDIO_POWER_D (1 << 27) 2782 #define SDE_AUDIO_POWER_C (1 << 26) 2783 #define SDE_AUDIO_POWER_B (1 << 25) 2784 #define SDE_AUDIO_POWER_SHIFT (25) 2785 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) 2786 #define SDE_GMBUS (1 << 24) 2787 #define SDE_AUDIO_HDCP_TRANSB (1 << 23) 2788 #define SDE_AUDIO_HDCP_TRANSA (1 << 22) 2789 #define SDE_AUDIO_HDCP_MASK (3 << 22) 2790 #define SDE_AUDIO_TRANSB (1 << 21) 2791 #define SDE_AUDIO_TRANSA (1 << 20) 2792 #define SDE_AUDIO_TRANS_MASK (3 << 20) 2793 #define SDE_POISON (1 << 19) 2794 /* 18 reserved */ 2795 #define SDE_FDI_RXB (1 << 17) 2796 #define SDE_FDI_RXA (1 << 16) 2797 #define SDE_FDI_MASK (3 << 16) 2798 #define SDE_AUXD (1 << 15) 2799 #define SDE_AUXC (1 << 14) 2800 #define SDE_AUXB (1 << 13) 2801 #define SDE_AUX_MASK (7 << 13) 2802 /* 12 reserved */ 2803 #define SDE_CRT_HOTPLUG (1 << 11) 2804 #define SDE_PORTD_HOTPLUG (1 << 10) 2805 #define SDE_PORTC_HOTPLUG (1 << 9) 2806 #define SDE_PORTB_HOTPLUG (1 << 8) 2807 #define SDE_SDVOB_HOTPLUG (1 << 6) 2808 #define SDE_HOTPLUG_MASK (0xf << 8) 2809 #define SDE_TRANSB_CRC_DONE (1 << 5) 2810 #define SDE_TRANSB_CRC_ERR (1 << 4) 2811 #define SDE_TRANSB_FIFO_UNDER (1 << 3) 2812 #define SDE_TRANSA_CRC_DONE (1 << 2) 2813 #define SDE_TRANSA_CRC_ERR (1 << 1) 2814 #define SDE_TRANSA_FIFO_UNDER (1 << 0) 2815 #define SDE_TRANS_MASK (0x3f) 2816 /* CPT */ 2817 #define SDE_CRT_HOTPLUG_CPT (1 << 19) 2818 #define SDE_PORTD_HOTPLUG_CPT (1 << 23) 2819 #define SDE_PORTC_HOTPLUG_CPT (1 << 22) 2820 #define SDE_PORTB_HOTPLUG_CPT (1 << 21) 2821 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ 2822 SDE_PORTD_HOTPLUG_CPT | \ 2823 SDE_PORTC_HOTPLUG_CPT | \ 2824 SDE_PORTB_HOTPLUG_CPT) 2825 2826 #define SDEISR 0xc4000 2827 #define SDEIMR 0xc4004 2828 #define SDEIIR 0xc4008 2829 #define SDEIER 0xc400c 2830 2831 /* digital port hotplug */ 2832 #define PCH_PORT_HOTPLUG 0xc4030 2833 #define PORTD_HOTPLUG_ENABLE (1 << 20) 2834 #define PORTD_PULSE_DURATION_2ms (0) 2835 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) 2836 #define PORTD_PULSE_DURATION_6ms (2 << 18) 2837 #define PORTD_PULSE_DURATION_100ms (3 << 18) 2838 #define PORTD_HOTPLUG_NO_DETECT (0) 2839 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) 2840 #define PORTD_HOTPLUG_LONG_DETECT (1 << 17) 2841 #define PORTC_HOTPLUG_ENABLE (1 << 12) 2842 #define PORTC_PULSE_DURATION_2ms (0) 2843 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) 2844 #define PORTC_PULSE_DURATION_6ms (2 << 10) 2845 #define PORTC_PULSE_DURATION_100ms (3 << 10) 2846 #define PORTC_HOTPLUG_NO_DETECT (0) 2847 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) 2848 #define PORTC_HOTPLUG_LONG_DETECT (1 << 9) 2849 #define PORTB_HOTPLUG_ENABLE (1 << 4) 2850 #define PORTB_PULSE_DURATION_2ms (0) 2851 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) 2852 #define PORTB_PULSE_DURATION_6ms (2 << 2) 2853 #define PORTB_PULSE_DURATION_100ms (3 << 2) 2854 #define PORTB_HOTPLUG_NO_DETECT (0) 2855 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) 2856 #define PORTB_HOTPLUG_LONG_DETECT (1 << 1) 2857 2858 #define PCH_GPIOA 0xc5010 2859 #define PCH_GPIOB 0xc5014 2860 #define PCH_GPIOC 0xc5018 2861 #define PCH_GPIOD 0xc501c 2862 #define PCH_GPIOE 0xc5020 2863 #define PCH_GPIOF 0xc5024 2864 2865 #define PCH_GMBUS0 0xc5100 2866 #define PCH_GMBUS1 0xc5104 2867 #define PCH_GMBUS2 0xc5108 2868 #define PCH_GMBUS3 0xc510c 2869 #define PCH_GMBUS4 0xc5110 2870 #define PCH_GMBUS5 0xc5120 2871 2872 #define PCH_DPLL_A 0xc6014 2873 #define PCH_DPLL_B 0xc6018 2874 #define PCH_DPLL(pipe) _PIPE(pipe, PCH_DPLL_A, PCH_DPLL_B) 2875 2876 #define PCH_FPA0 0xc6040 2877 #define FP_CB_TUNE (0x3<<22) 2878 #define PCH_FPA1 0xc6044 2879 #define PCH_FPB0 0xc6048 2880 #define PCH_FPB1 0xc604c 2881 #define PCH_FP0(pipe) _PIPE(pipe, PCH_FPA0, PCH_FPB0) 2882 #define PCH_FP1(pipe) _PIPE(pipe, PCH_FPA1, PCH_FPB1) 2883 2884 #define PCH_DPLL_TEST 0xc606c 2885 2886 #define PCH_DREF_CONTROL 0xC6200 2887 #define DREF_CONTROL_MASK 0x7fc3 2888 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13) 2889 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13) 2890 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13) 2891 #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13) 2892 #define DREF_SSC_SOURCE_DISABLE (0<<11) 2893 #define DREF_SSC_SOURCE_ENABLE (2<<11) 2894 #define DREF_SSC_SOURCE_MASK (3<<11) 2895 #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) 2896 #define DREF_NONSPREAD_CK505_ENABLE (1<<9) 2897 #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) 2898 #define DREF_NONSPREAD_SOURCE_MASK (3<<9) 2899 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) 2900 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) 2901 #define DREF_SSC4_DOWNSPREAD (0<<6) 2902 #define DREF_SSC4_CENTERSPREAD (1<<6) 2903 #define DREF_SSC1_DISABLE (0<<1) 2904 #define DREF_SSC1_ENABLE (1<<1) 2905 #define DREF_SSC4_DISABLE (0) 2906 #define DREF_SSC4_ENABLE (1) 2907 2908 #define PCH_RAWCLK_FREQ 0xc6204 2909 #define FDL_TP1_TIMER_SHIFT 12 2910 #define FDL_TP1_TIMER_MASK (3<<12) 2911 #define FDL_TP2_TIMER_SHIFT 10 2912 #define FDL_TP2_TIMER_MASK (3<<10) 2913 #define RAWCLK_FREQ_MASK 0x3ff 2914 2915 #define PCH_DPLL_TMR_CFG 0xc6208 2916 2917 #define PCH_SSC4_PARMS 0xc6210 2918 #define PCH_SSC4_AUX_PARMS 0xc6214 2919 2920 #define PCH_DPLL_SEL 0xc7000 2921 #define TRANSA_DPLL_ENABLE (1<<3) 2922 #define TRANSA_DPLLB_SEL (1<<0) 2923 #define TRANSA_DPLLA_SEL 0 2924 #define TRANSB_DPLL_ENABLE (1<<7) 2925 #define TRANSB_DPLLB_SEL (1<<4) 2926 #define TRANSB_DPLLA_SEL (0) 2927 #define TRANSC_DPLL_ENABLE (1<<11) 2928 #define TRANSC_DPLLB_SEL (1<<8) 2929 #define TRANSC_DPLLA_SEL (0) 2930 2931 /* transcoder */ 2932 2933 #define TRANS_HTOTAL_A 0xe0000 2934 #define TRANS_HTOTAL_SHIFT 16 2935 #define TRANS_HACTIVE_SHIFT 0 2936 #define TRANS_HBLANK_A 0xe0004 2937 #define TRANS_HBLANK_END_SHIFT 16 2938 #define TRANS_HBLANK_START_SHIFT 0 2939 #define TRANS_HSYNC_A 0xe0008 2940 #define TRANS_HSYNC_END_SHIFT 16 2941 #define TRANS_HSYNC_START_SHIFT 0 2942 #define TRANS_VTOTAL_A 0xe000c 2943 #define TRANS_VTOTAL_SHIFT 16 2944 #define TRANS_VACTIVE_SHIFT 0 2945 #define TRANS_VBLANK_A 0xe0010 2946 #define TRANS_VBLANK_END_SHIFT 16 2947 #define TRANS_VBLANK_START_SHIFT 0 2948 #define TRANS_VSYNC_A 0xe0014 2949 #define TRANS_VSYNC_END_SHIFT 16 2950 #define TRANS_VSYNC_START_SHIFT 0 2951 2952 #define TRANSA_DATA_M1 0xe0030 2953 #define TRANSA_DATA_N1 0xe0034 2954 #define TRANSA_DATA_M2 0xe0038 2955 #define TRANSA_DATA_N2 0xe003c 2956 #define TRANSA_DP_LINK_M1 0xe0040 2957 #define TRANSA_DP_LINK_N1 0xe0044 2958 #define TRANSA_DP_LINK_M2 0xe0048 2959 #define TRANSA_DP_LINK_N2 0xe004c 2960 2961 #define TRANS_HTOTAL_B 0xe1000 2962 #define TRANS_HBLANK_B 0xe1004 2963 #define TRANS_HSYNC_B 0xe1008 2964 #define TRANS_VTOTAL_B 0xe100c 2965 #define TRANS_VBLANK_B 0xe1010 2966 #define TRANS_VSYNC_B 0xe1014 2967 2968 #define TRANS_HTOTAL(pipe) _PIPE(pipe, TRANS_HTOTAL_A, TRANS_HTOTAL_B) 2969 #define TRANS_HBLANK(pipe) _PIPE(pipe, TRANS_HBLANK_A, TRANS_HBLANK_B) 2970 #define TRANS_HSYNC(pipe) _PIPE(pipe, TRANS_HSYNC_A, TRANS_HSYNC_B) 2971 #define TRANS_VTOTAL(pipe) _PIPE(pipe, TRANS_VTOTAL_A, TRANS_VTOTAL_B) 2972 #define TRANS_VBLANK(pipe) _PIPE(pipe, TRANS_VBLANK_A, TRANS_VBLANK_B) 2973 #define TRANS_VSYNC(pipe) _PIPE(pipe, TRANS_VSYNC_A, TRANS_VSYNC_B) 2974 2975 #define TRANSB_DATA_M1 0xe1030 2976 #define TRANSB_DATA_N1 0xe1034 2977 #define TRANSB_DATA_M2 0xe1038 2978 #define TRANSB_DATA_N2 0xe103c 2979 #define TRANSB_DP_LINK_M1 0xe1040 2980 #define TRANSB_DP_LINK_N1 0xe1044 2981 #define TRANSB_DP_LINK_M2 0xe1048 2982 #define TRANSB_DP_LINK_N2 0xe104c 2983 2984 #define TRANSACONF 0xf0008 2985 #define TRANSBCONF 0xf1008 2986 #define TRANSCONF(plane) _PIPE(plane, TRANSACONF, TRANSBCONF) 2987 #define TRANS_DISABLE (0<<31) 2988 #define TRANS_ENABLE (1<<31) 2989 #define TRANS_STATE_MASK (1<<30) 2990 #define TRANS_STATE_DISABLE (0<<30) 2991 #define TRANS_STATE_ENABLE (1<<30) 2992 #define TRANS_FSYNC_DELAY_HB1 (0<<27) 2993 #define TRANS_FSYNC_DELAY_HB2 (1<<27) 2994 #define TRANS_FSYNC_DELAY_HB3 (2<<27) 2995 #define TRANS_FSYNC_DELAY_HB4 (3<<27) 2996 #define TRANS_DP_AUDIO_ONLY (1<<26) 2997 #define TRANS_DP_VIDEO_AUDIO (0<<26) 2998 #define TRANS_PROGRESSIVE (0<<21) 2999 #define TRANS_8BPC (0<<5) 3000 #define TRANS_10BPC (1<<5) 3001 #define TRANS_6BPC (2<<5) 3002 #define TRANS_12BPC (3<<5) 3003 3004 #define FDI_RXA_CHICKEN 0xc200c 3005 #define FDI_RXB_CHICKEN 0xc2010 3006 #define FDI_RX_PHASE_SYNC_POINTER_ENABLE (1) 3007 #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, FDI_RXA_CHICKEN, FDI_RXB_CHICKEN) 3008 3009 #define SOUTH_DSPCLK_GATE_D 0xc2020 3010 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29) 3011 3012 /* CPU: FDI_TX */ 3013 #define FDI_TXA_CTL 0x60100 3014 #define FDI_TXB_CTL 0x61100 3015 #define FDI_TX_CTL(pipe) _PIPE(pipe, FDI_TXA_CTL, FDI_TXB_CTL) 3016 #define FDI_TX_DISABLE (0<<31) 3017 #define FDI_TX_ENABLE (1<<31) 3018 #define FDI_LINK_TRAIN_PATTERN_1 (0<<28) 3019 #define FDI_LINK_TRAIN_PATTERN_2 (1<<28) 3020 #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28) 3021 #define FDI_LINK_TRAIN_NONE (3<<28) 3022 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25) 3023 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25) 3024 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25) 3025 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25) 3026 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22) 3027 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22) 3028 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22) 3029 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22) 3030 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. 3031 SNB has different settings. */ 3032 /* SNB A-stepping */ 3033 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) 3034 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) 3035 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) 3036 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) 3037 /* SNB B-stepping */ 3038 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22) 3039 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22) 3040 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22) 3041 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22) 3042 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22) 3043 #define FDI_DP_PORT_WIDTH_X1 (0<<19) 3044 #define FDI_DP_PORT_WIDTH_X2 (1<<19) 3045 #define FDI_DP_PORT_WIDTH_X3 (2<<19) 3046 #define FDI_DP_PORT_WIDTH_X4 (3<<19) 3047 #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) 3048 /* Ironlake: hardwired to 1 */ 3049 #define FDI_TX_PLL_ENABLE (1<<14) 3050 /* both Tx and Rx */ 3051 #define FDI_SCRAMBLING_ENABLE (0<<7) 3052 #define FDI_SCRAMBLING_DISABLE (1<<7) 3053 3054 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */ 3055 #define FDI_RXA_CTL 0xf000c 3056 #define FDI_RXB_CTL 0xf100c 3057 #define FDI_RX_CTL(pipe) _PIPE(pipe, FDI_RXA_CTL, FDI_RXB_CTL) 3058 #define FDI_RX_ENABLE (1<<31) 3059 /* train, dp width same as FDI_TX */ 3060 #define FDI_DP_PORT_WIDTH_X8 (7<<19) 3061 #define FDI_8BPC (0<<16) 3062 #define FDI_10BPC (1<<16) 3063 #define FDI_6BPC (2<<16) 3064 #define FDI_12BPC (3<<16) 3065 #define FDI_LINK_REVERSE_OVERWRITE (1<<15) 3066 #define FDI_DMI_LINK_REVERSE_MASK (1<<14) 3067 #define FDI_RX_PLL_ENABLE (1<<13) 3068 #define FDI_FS_ERR_CORRECT_ENABLE (1<<11) 3069 #define FDI_FE_ERR_CORRECT_ENABLE (1<<10) 3070 #define FDI_FS_ERR_REPORT_ENABLE (1<<9) 3071 #define FDI_FE_ERR_REPORT_ENABLE (1<<8) 3072 #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) 3073 #define FDI_PCDCLK (1<<4) 3074 /* CPT */ 3075 #define FDI_AUTO_TRAINING (1<<10) 3076 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8) 3077 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8) 3078 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8) 3079 #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8) 3080 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8) 3081 3082 #define FDI_RXA_MISC 0xf0010 3083 #define FDI_RXB_MISC 0xf1010 3084 #define FDI_RXA_TUSIZE1 0xf0030 3085 #define FDI_RXA_TUSIZE2 0xf0038 3086 #define FDI_RXB_TUSIZE1 0xf1030 3087 #define FDI_RXB_TUSIZE2 0xf1038 3088 #define FDI_RX_MISC(pipe) _PIPE(pipe, FDI_RXA_MISC, FDI_RXB_MISC) 3089 #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, FDI_RXA_TUSIZE1, FDI_RXB_TUSIZE1) 3090 #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, FDI_RXA_TUSIZE2, FDI_RXB_TUSIZE2) 3091 3092 /* FDI_RX interrupt register format */ 3093 #define FDI_RX_INTER_LANE_ALIGN (1<<10) 3094 #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */ 3095 #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */ 3096 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7) 3097 #define FDI_RX_FS_CODE_ERR (1<<6) 3098 #define FDI_RX_FE_CODE_ERR (1<<5) 3099 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4) 3100 #define FDI_RX_HDCP_LINK_FAIL (1<<3) 3101 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2) 3102 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) 3103 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) 3104 3105 #define FDI_RXA_IIR 0xf0014 3106 #define FDI_RXA_IMR 0xf0018 3107 #define FDI_RXB_IIR 0xf1014 3108 #define FDI_RXB_IMR 0xf1018 3109 #define FDI_RX_IIR(pipe) _PIPE(pipe, FDI_RXA_IIR, FDI_RXB_IIR) 3110 #define FDI_RX_IMR(pipe) _PIPE(pipe, FDI_RXA_IMR, FDI_RXB_IMR) 3111 3112 #define FDI_PLL_CTL_1 0xfe000 3113 #define FDI_PLL_CTL_2 0xfe004 3114 3115 /* CRT */ 3116 #define PCH_ADPA 0xe1100 3117 #define ADPA_TRANS_SELECT_MASK (1<<30) 3118 #define ADPA_TRANS_A_SELECT 0 3119 #define ADPA_TRANS_B_SELECT (1<<30) 3120 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ 3121 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24) 3122 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24) 3123 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24) 3124 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24) 3125 #define ADPA_CRT_HOTPLUG_ENABLE (1<<23) 3126 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) 3127 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) 3128 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) 3129 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) 3130 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) 3131 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) 3132 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) 3133 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) 3134 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) 3135 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) 3136 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17) 3137 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17) 3138 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16) 3139 3140 /* or SDVOB */ 3141 #define HDMIB 0xe1140 3142 #define PORT_ENABLE (1 << 31) 3143 #define TRANSCODER_A (0) 3144 #define TRANSCODER_B (1 << 30) 3145 #define COLOR_FORMAT_8bpc (0) 3146 #define COLOR_FORMAT_12bpc (3 << 26) 3147 #define SDVOB_HOTPLUG_ENABLE (1 << 23) 3148 #define SDVO_ENCODING (0) 3149 #define TMDS_ENCODING (2 << 10) 3150 #define NULL_PACKET_VSYNC_ENABLE (1 << 9) 3151 /* CPT */ 3152 #define HDMI_MODE_SELECT (1 << 9) 3153 #define DVI_MODE_SELECT (0) 3154 #define SDVOB_BORDER_ENABLE (1 << 7) 3155 #define AUDIO_ENABLE (1 << 6) 3156 #define VSYNC_ACTIVE_HIGH (1 << 4) 3157 #define HSYNC_ACTIVE_HIGH (1 << 3) 3158 #define PORT_DETECTED (1 << 2) 3159 3160 /* PCH SDVOB multiplex with HDMIB */ 3161 #define PCH_SDVOB HDMIB 3162 3163 #define HDMIC 0xe1150 3164 #define HDMID 0xe1160 3165 3166 #define PCH_LVDS 0xe1180 3167 #define LVDS_DETECTED (1 << 1) 3168 3169 #define BLC_PWM_CPU_CTL2 0x48250 3170 #define PWM_ENABLE (1 << 31) 3171 #define PWM_PIPE_A (0 << 29) 3172 #define PWM_PIPE_B (1 << 29) 3173 #define BLC_PWM_CPU_CTL 0x48254 3174 3175 #define BLC_PWM_PCH_CTL1 0xc8250 3176 #define PWM_PCH_ENABLE (1 << 31) 3177 #define PWM_POLARITY_ACTIVE_LOW (1 << 29) 3178 #define PWM_POLARITY_ACTIVE_HIGH (0 << 29) 3179 #define PWM_POLARITY_ACTIVE_LOW2 (1 << 28) 3180 #define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28) 3181 3182 #define BLC_PWM_PCH_CTL2 0xc8254 3183 3184 #define PCH_PP_STATUS 0xc7200 3185 #define PCH_PP_CONTROL 0xc7204 3186 #define PANEL_UNLOCK_REGS (0xabcd << 16) 3187 #define EDP_FORCE_VDD (1 << 3) 3188 #define EDP_BLC_ENABLE (1 << 2) 3189 #define PANEL_POWER_RESET (1 << 1) 3190 #define PANEL_POWER_OFF (0 << 0) 3191 #define PANEL_POWER_ON (1 << 0) 3192 #define PCH_PP_ON_DELAYS 0xc7208 3193 #define EDP_PANEL (1 << 30) 3194 #define PCH_PP_OFF_DELAYS 0xc720c 3195 #define PCH_PP_DIVISOR 0xc7210 3196 3197 #define PCH_DP_B 0xe4100 3198 #define PCH_DPB_AUX_CH_CTL 0xe4110 3199 #define PCH_DPB_AUX_CH_DATA1 0xe4114 3200 #define PCH_DPB_AUX_CH_DATA2 0xe4118 3201 #define PCH_DPB_AUX_CH_DATA3 0xe411c 3202 #define PCH_DPB_AUX_CH_DATA4 0xe4120 3203 #define PCH_DPB_AUX_CH_DATA5 0xe4124 3204 3205 #define PCH_DP_C 0xe4200 3206 #define PCH_DPC_AUX_CH_CTL 0xe4210 3207 #define PCH_DPC_AUX_CH_DATA1 0xe4214 3208 #define PCH_DPC_AUX_CH_DATA2 0xe4218 3209 #define PCH_DPC_AUX_CH_DATA3 0xe421c 3210 #define PCH_DPC_AUX_CH_DATA4 0xe4220 3211 #define PCH_DPC_AUX_CH_DATA5 0xe4224 3212 3213 #define PCH_DP_D 0xe4300 3214 #define PCH_DPD_AUX_CH_CTL 0xe4310 3215 #define PCH_DPD_AUX_CH_DATA1 0xe4314 3216 #define PCH_DPD_AUX_CH_DATA2 0xe4318 3217 #define PCH_DPD_AUX_CH_DATA3 0xe431c 3218 #define PCH_DPD_AUX_CH_DATA4 0xe4320 3219 #define PCH_DPD_AUX_CH_DATA5 0xe4324 3220 3221 /* CPT */ 3222 #define PORT_TRANS_A_SEL_CPT 0 3223 #define PORT_TRANS_B_SEL_CPT (1<<29) 3224 #define PORT_TRANS_C_SEL_CPT (2<<29) 3225 #define PORT_TRANS_SEL_MASK (3<<29) 3226 3227 #define TRANS_DP_CTL_A 0xe0300 3228 #define TRANS_DP_CTL_B 0xe1300 3229 #define TRANS_DP_CTL_C 0xe2300 3230 #define TRANS_DP_CTL(pipe) (TRANS_DP_CTL_A + (pipe) * 0x01000) 3231 #define TRANS_DP_OUTPUT_ENABLE (1<<31) 3232 #define TRANS_DP_PORT_SEL_B (0<<29) 3233 #define TRANS_DP_PORT_SEL_C (1<<29) 3234 #define TRANS_DP_PORT_SEL_D (2<<29) 3235 #define TRANS_DP_PORT_SEL_MASK (3<<29) 3236 #define TRANS_DP_AUDIO_ONLY (1<<26) 3237 #define TRANS_DP_ENH_FRAMING (1<<18) 3238 #define TRANS_DP_8BPC (0<<9) 3239 #define TRANS_DP_10BPC (1<<9) 3240 #define TRANS_DP_6BPC (2<<9) 3241 #define TRANS_DP_12BPC (3<<9) 3242 #define TRANS_DP_BPC_MASK (3<<9) 3243 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4) 3244 #define TRANS_DP_VSYNC_ACTIVE_LOW 0 3245 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3) 3246 #define TRANS_DP_HSYNC_ACTIVE_LOW 0 3247 #define TRANS_DP_SYNC_MASK (3<<3) 3248 3249 /* SNB eDP training params */ 3250 /* SNB A-stepping */ 3251 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) 3252 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) 3253 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) 3254 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) 3255 /* SNB B-stepping */ 3256 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22) 3257 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22) 3258 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22) 3259 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22) 3260 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22) 3261 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22) 3262 3263 #define FORCEWAKE 0xA18C 3264 #define FORCEWAKE_ACK 0x130090 3265 3266 #define GEN6_RPNSWREQ 0xA008 3267 #define GEN6_TURBO_DISABLE (1<<31) 3268 #define GEN6_FREQUENCY(x) ((x)<<25) 3269 #define GEN6_OFFSET(x) ((x)<<19) 3270 #define GEN6_AGGRESSIVE_TURBO (0<<15) 3271 #define GEN6_RC_VIDEO_FREQ 0xA00C 3272 #define GEN6_RC_CONTROL 0xA090 3273 #define GEN6_RC_CTL_RC6pp_ENABLE (1<<16) 3274 #define GEN6_RC_CTL_RC6p_ENABLE (1<<17) 3275 #define GEN6_RC_CTL_RC6_ENABLE (1<<18) 3276 #define GEN6_RC_CTL_RC1e_ENABLE (1<<20) 3277 #define GEN6_RC_CTL_RC7_ENABLE (1<<22) 3278 #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27) 3279 #define GEN6_RC_CTL_HW_ENABLE (1<<31) 3280 #define GEN6_RP_DOWN_TIMEOUT 0xA010 3281 #define GEN6_RP_INTERRUPT_LIMITS 0xA014 3282 #define GEN6_RPSTAT1 0xA01C 3283 #define GEN6_RP_CONTROL 0xA024 3284 #define GEN6_RP_MEDIA_TURBO (1<<11) 3285 #define GEN6_RP_USE_NORMAL_FREQ (1<<9) 3286 #define GEN6_RP_MEDIA_IS_GFX (1<<8) 3287 #define GEN6_RP_ENABLE (1<<7) 3288 #define GEN6_RP_UP_BUSY_MAX (0x2<<3) 3289 #define GEN6_RP_DOWN_BUSY_MIN (0x2<<0) 3290 #define GEN6_RP_UP_THRESHOLD 0xA02C 3291 #define GEN6_RP_DOWN_THRESHOLD 0xA030 3292 #define GEN6_RP_UP_EI 0xA068 3293 #define GEN6_RP_DOWN_EI 0xA06C 3294 #define GEN6_RP_IDLE_HYSTERSIS 0xA070 3295 #define GEN6_RC_STATE 0xA094 3296 #define GEN6_RC1_WAKE_RATE_LIMIT 0xA098 3297 #define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C 3298 #define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0 3299 #define GEN6_RC_EVALUATION_INTERVAL 0xA0A8 3300 #define GEN6_RC_IDLE_HYSTERSIS 0xA0AC 3301 #define GEN6_RC_SLEEP 0xA0B0 3302 #define GEN6_RC1e_THRESHOLD 0xA0B4 3303 #define GEN6_RC6_THRESHOLD 0xA0B8 3304 #define GEN6_RC6p_THRESHOLD 0xA0BC 3305 #define GEN6_RC6pp_THRESHOLD 0xA0C0 3306 #define GEN6_PMINTRMSK 0xA168 3307 3308 #define GEN6_PMISR 0x44020 3309 #define GEN6_PMIMR 0x44024 3310 #define GEN6_PMIIR 0x44028 3311 #define GEN6_PMIER 0x4402C 3312 #define GEN6_PM_MBOX_EVENT (1<<25) 3313 #define GEN6_PM_THERMAL_EVENT (1<<24) 3314 #define GEN6_PM_RP_DOWN_TIMEOUT (1<<6) 3315 #define GEN6_PM_RP_UP_THRESHOLD (1<<5) 3316 #define GEN6_PM_RP_DOWN_THRESHOLD (1<<4) 3317 #define GEN6_PM_RP_UP_EI_EXPIRED (1<<2) 3318 #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1) 3319 3320 #define GEN6_PCODE_MAILBOX 0x138124 3321 #define GEN6_PCODE_READY (1<<31) 3322 #define GEN6_READ_OC_PARAMS 0xc 3323 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x9 3324 #define GEN6_PCODE_DATA 0x138128 3325 3326 #endif /* _I915_REG_H_ */ 3327