xref: /openbmc/linux/drivers/gpu/drm/i915/i915_reg.h (revision 15d90a6a)
1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
2  * All Rights Reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the
6  * "Software"), to deal in the Software without restriction, including
7  * without limitation the rights to use, copy, modify, merge, publish,
8  * distribute, sub license, and/or sell copies of the Software, and to
9  * permit persons to whom the Software is furnished to do so, subject to
10  * the following conditions:
11  *
12  * The above copyright notice and this permission notice (including the
13  * next paragraph) shall be included in all copies or substantial portions
14  * of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23  */
24 
25 #ifndef _I915_REG_H_
26 #define _I915_REG_H_
27 
28 /**
29  * DOC: The i915 register macro definition style guide
30  *
31  * Follow the style described here for new macros, and while changing existing
32  * macros. Do **not** mass change existing definitions just to update the style.
33  *
34  * Layout
35  * ''''''
36  *
37  * Keep helper macros near the top. For example, _PIPE() and friends.
38  *
39  * Prefix macros that generally should not be used outside of this file with
40  * underscore '_'. For example, _PIPE() and friends, single instances of
41  * registers that are defined solely for the use by function-like macros.
42  *
43  * Avoid using the underscore prefixed macros outside of this file. There are
44  * exceptions, but keep them to a minimum.
45  *
46  * There are two basic types of register definitions: Single registers and
47  * register groups. Register groups are registers which have two or more
48  * instances, for example one per pipe, port, transcoder, etc. Register groups
49  * should be defined using function-like macros.
50  *
51  * For single registers, define the register offset first, followed by register
52  * contents.
53  *
54  * For register groups, define the register instance offsets first, prefixed
55  * with underscore, followed by a function-like macro choosing the right
56  * instance based on the parameter, followed by register contents.
57  *
58  * Define the register contents (i.e. bit and bit field macros) from most
59  * significant to least significant bit. Indent the register content macros
60  * using two extra spaces between ``#define`` and the macro name.
61  *
62  * For bit fields, define a ``_MASK`` and a ``_SHIFT`` macro. Define bit field
63  * contents so that they are already shifted in place, and can be directly
64  * OR'd. For convenience, function-like macros may be used to define bit fields,
65  * but do note that the macros may be needed to read as well as write the
66  * register contents.
67  *
68  * Define bits using ``(1 << N)`` instead of ``BIT(N)``. We may change this in
69  * the future, but this is the prevailing style. Do **not** add ``_BIT`` suffix
70  * to the name.
71  *
72  * Group the register and its contents together without blank lines, separate
73  * from other registers and their contents with one blank line.
74  *
75  * Indent macro values from macro names using TABs. Align values vertically. Use
76  * braces in macro values as needed to avoid unintended precedence after macro
77  * substitution. Use spaces in macro values according to kernel coding
78  * style. Use lower case in hexadecimal values.
79  *
80  * Naming
81  * ''''''
82  *
83  * Try to name registers according to the specs. If the register name changes in
84  * the specs from platform to another, stick to the original name.
85  *
86  * Try to re-use existing register macro definitions. Only add new macros for
87  * new register offsets, or when the register contents have changed enough to
88  * warrant a full redefinition.
89  *
90  * When a register macro changes for a new platform, prefix the new macro using
91  * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The
92  * prefix signifies the start platform/generation using the register.
93  *
94  * When a bit (field) macro changes or gets added for a new platform, while
95  * retaining the existing register macro, add a platform acronym or generation
96  * suffix to the name. For example, ``_SKL`` or ``_GEN8``.
97  *
98  * Examples
99  * ''''''''
100  *
101  * (Note that the values in the example are indented using spaces instead of
102  * TABs to avoid misalignment in generated documentation. Use TABs in the
103  * definitions.)::
104  *
105  *  #define _FOO_A                      0xf000
106  *  #define _FOO_B                      0xf001
107  *  #define FOO(pipe)                   _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
108  *  #define   FOO_ENABLE                (1 << 31)
109  *  #define   FOO_MODE_MASK             (0xf << 16)
110  *  #define   FOO_MODE_SHIFT            16
111  *  #define   FOO_MODE_BAR              (0 << 16)
112  *  #define   FOO_MODE_BAZ              (1 << 16)
113  *  #define   FOO_MODE_QUX_SNB          (2 << 16)
114  *
115  *  #define BAR                         _MMIO(0xb000)
116  *  #define GEN8_BAR                    _MMIO(0xb888)
117  */
118 
119 typedef struct {
120 	uint32_t reg;
121 } i915_reg_t;
122 
123 #define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
124 
125 #define INVALID_MMIO_REG _MMIO(0)
126 
127 static inline uint32_t i915_mmio_reg_offset(i915_reg_t reg)
128 {
129 	return reg.reg;
130 }
131 
132 static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
133 {
134 	return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
135 }
136 
137 static inline bool i915_mmio_reg_valid(i915_reg_t reg)
138 {
139 	return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
140 }
141 
142 /*
143  * Given the first two numbers __a and __b of arbitrarily many evenly spaced
144  * numbers, pick the 0-based __index'th value.
145  *
146  * Always prefer this over _PICK() if the numbers are evenly spaced.
147  */
148 #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
149 
150 /*
151  * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
152  *
153  * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced.
154  */
155 #define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
156 
157 /*
158  * Named helper wrappers around _PICK_EVEN() and _PICK().
159  */
160 #define _PIPE(pipe, a, b)		_PICK_EVEN(pipe, a, b)
161 #define _PLANE(plane, a, b)		_PICK_EVEN(plane, a, b)
162 #define _TRANS(tran, a, b)		_PICK_EVEN(tran, a, b)
163 #define _PORT(port, a, b)		_PICK_EVEN(port, a, b)
164 #define _PLL(pll, a, b)			_PICK_EVEN(pll, a, b)
165 
166 #define _MMIO_PIPE(pipe, a, b)		_MMIO(_PIPE(pipe, a, b))
167 #define _MMIO_PLANE(plane, a, b)	_MMIO(_PLANE(plane, a, b))
168 #define _MMIO_TRANS(tran, a, b)		_MMIO(_TRANS(tran, a, b))
169 #define _MMIO_PORT(port, a, b)		_MMIO(_PORT(port, a, b))
170 #define _MMIO_PLL(pll, a, b)		_MMIO(_PLL(pll, a, b))
171 
172 #define _PHY3(phy, ...)			_PICK(phy, __VA_ARGS__)
173 
174 #define _MMIO_PIPE3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
175 #define _MMIO_PORT3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
176 #define _MMIO_PHY3(phy, a, b, c)	_MMIO(_PHY3(phy, a, b, c))
177 
178 /*
179  * Device info offset array based helpers for groups of registers with unevenly
180  * spaced base offsets.
181  */
182 #define _MMIO_PIPE2(pipe, reg)		_MMIO(dev_priv->info.pipe_offsets[pipe] - \
183 					      dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
184 					      dev_priv->info.display_mmio_offset)
185 #define _MMIO_TRANS2(pipe, reg)		_MMIO(dev_priv->info.trans_offsets[(pipe)] - \
186 					      dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
187 					      dev_priv->info.display_mmio_offset)
188 #define _CURSOR2(pipe, reg)		_MMIO(dev_priv->info.cursor_offsets[(pipe)] - \
189 					      dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
190 					      dev_priv->info.display_mmio_offset)
191 
192 #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
193 #define _MASKED_FIELD(mask, value) ({					   \
194 	if (__builtin_constant_p(mask))					   \
195 		BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
196 	if (__builtin_constant_p(value))				   \
197 		BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
198 	if (__builtin_constant_p(mask) && __builtin_constant_p(value))	   \
199 		BUILD_BUG_ON_MSG((value) & ~(mask),			   \
200 				 "Incorrect value for mask");		   \
201 	__MASKED_FIELD(mask, value); })
202 #define _MASKED_BIT_ENABLE(a)	({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
203 #define _MASKED_BIT_DISABLE(a)	(_MASKED_FIELD((a), 0))
204 
205 /* Engine ID */
206 
207 #define RCS_HW		0
208 #define VCS_HW		1
209 #define BCS_HW		2
210 #define VECS_HW		3
211 #define VCS2_HW		4
212 #define VCS3_HW		6
213 #define VCS4_HW		7
214 #define VECS2_HW	12
215 
216 /* Engine class */
217 
218 #define RENDER_CLASS		0
219 #define VIDEO_DECODE_CLASS	1
220 #define VIDEO_ENHANCEMENT_CLASS	2
221 #define COPY_ENGINE_CLASS	3
222 #define OTHER_CLASS		4
223 #define MAX_ENGINE_CLASS	4
224 
225 #define OTHER_GTPM_INSTANCE	1
226 #define MAX_ENGINE_INSTANCE    3
227 
228 /* PCI config space */
229 
230 #define MCHBAR_I915 0x44
231 #define MCHBAR_I965 0x48
232 #define MCHBAR_SIZE (4 * 4096)
233 
234 #define DEVEN 0x54
235 #define   DEVEN_MCHBAR_EN (1 << 28)
236 
237 /* BSM in include/drm/i915_drm.h */
238 
239 #define HPLLCC	0xc0 /* 85x only */
240 #define   GC_CLOCK_CONTROL_MASK		(0x7 << 0)
241 #define   GC_CLOCK_133_200		(0 << 0)
242 #define   GC_CLOCK_100_200		(1 << 0)
243 #define   GC_CLOCK_100_133		(2 << 0)
244 #define   GC_CLOCK_133_266		(3 << 0)
245 #define   GC_CLOCK_133_200_2		(4 << 0)
246 #define   GC_CLOCK_133_266_2		(5 << 0)
247 #define   GC_CLOCK_166_266		(6 << 0)
248 #define   GC_CLOCK_166_250		(7 << 0)
249 
250 #define I915_GDRST 0xc0 /* PCI config register */
251 #define   GRDOM_FULL		(0 << 2)
252 #define   GRDOM_RENDER		(1 << 2)
253 #define   GRDOM_MEDIA		(3 << 2)
254 #define   GRDOM_MASK		(3 << 2)
255 #define   GRDOM_RESET_STATUS	(1 << 1)
256 #define   GRDOM_RESET_ENABLE	(1 << 0)
257 
258 /* BSpec only has register offset, PCI device and bit found empirically */
259 #define I830_CLOCK_GATE	0xc8 /* device 0 */
260 #define   I830_L2_CACHE_CLOCK_GATE_DISABLE	(1 << 2)
261 
262 #define GCDGMBUS 0xcc
263 
264 #define GCFGC2	0xda
265 #define GCFGC	0xf0 /* 915+ only */
266 #define   GC_LOW_FREQUENCY_ENABLE	(1 << 7)
267 #define   GC_DISPLAY_CLOCK_190_200_MHZ	(0 << 4)
268 #define   GC_DISPLAY_CLOCK_333_320_MHZ	(4 << 4)
269 #define   GC_DISPLAY_CLOCK_267_MHZ_PNV	(0 << 4)
270 #define   GC_DISPLAY_CLOCK_333_MHZ_PNV	(1 << 4)
271 #define   GC_DISPLAY_CLOCK_444_MHZ_PNV	(2 << 4)
272 #define   GC_DISPLAY_CLOCK_200_MHZ_PNV	(5 << 4)
273 #define   GC_DISPLAY_CLOCK_133_MHZ_PNV	(6 << 4)
274 #define   GC_DISPLAY_CLOCK_167_MHZ_PNV	(7 << 4)
275 #define   GC_DISPLAY_CLOCK_MASK		(7 << 4)
276 #define   GM45_GC_RENDER_CLOCK_MASK	(0xf << 0)
277 #define   GM45_GC_RENDER_CLOCK_266_MHZ	(8 << 0)
278 #define   GM45_GC_RENDER_CLOCK_320_MHZ	(9 << 0)
279 #define   GM45_GC_RENDER_CLOCK_400_MHZ	(0xb << 0)
280 #define   GM45_GC_RENDER_CLOCK_533_MHZ	(0xc << 0)
281 #define   I965_GC_RENDER_CLOCK_MASK	(0xf << 0)
282 #define   I965_GC_RENDER_CLOCK_267_MHZ	(2 << 0)
283 #define   I965_GC_RENDER_CLOCK_333_MHZ	(3 << 0)
284 #define   I965_GC_RENDER_CLOCK_444_MHZ	(4 << 0)
285 #define   I965_GC_RENDER_CLOCK_533_MHZ	(5 << 0)
286 #define   I945_GC_RENDER_CLOCK_MASK	(7 << 0)
287 #define   I945_GC_RENDER_CLOCK_166_MHZ	(0 << 0)
288 #define   I945_GC_RENDER_CLOCK_200_MHZ	(1 << 0)
289 #define   I945_GC_RENDER_CLOCK_250_MHZ	(3 << 0)
290 #define   I945_GC_RENDER_CLOCK_400_MHZ	(5 << 0)
291 #define   I915_GC_RENDER_CLOCK_MASK	(7 << 0)
292 #define   I915_GC_RENDER_CLOCK_166_MHZ	(0 << 0)
293 #define   I915_GC_RENDER_CLOCK_200_MHZ	(1 << 0)
294 #define   I915_GC_RENDER_CLOCK_333_MHZ	(4 << 0)
295 
296 #define ASLE	0xe4
297 #define ASLS	0xfc
298 
299 #define SWSCI	0xe8
300 #define   SWSCI_SCISEL	(1 << 15)
301 #define   SWSCI_GSSCIE	(1 << 0)
302 
303 #define LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
304 
305 
306 #define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
307 #define  ILK_GRDOM_FULL		(0 << 1)
308 #define  ILK_GRDOM_RENDER	(1 << 1)
309 #define  ILK_GRDOM_MEDIA	(3 << 1)
310 #define  ILK_GRDOM_MASK		(3 << 1)
311 #define  ILK_GRDOM_RESET_ENABLE (1 << 0)
312 
313 #define GEN6_MBCUNIT_SNPCR	_MMIO(0x900c) /* for LLC config */
314 #define   GEN6_MBC_SNPCR_SHIFT	21
315 #define   GEN6_MBC_SNPCR_MASK	(3 << 21)
316 #define   GEN6_MBC_SNPCR_MAX	(0 << 21)
317 #define   GEN6_MBC_SNPCR_MED	(1 << 21)
318 #define   GEN6_MBC_SNPCR_LOW	(2 << 21)
319 #define   GEN6_MBC_SNPCR_MIN	(3 << 21) /* only 1/16th of the cache is shared */
320 
321 #define VLV_G3DCTL		_MMIO(0x9024)
322 #define VLV_GSCKGCTL		_MMIO(0x9028)
323 
324 #define GEN6_MBCTL		_MMIO(0x0907c)
325 #define   GEN6_MBCTL_ENABLE_BOOT_FETCH	(1 << 4)
326 #define   GEN6_MBCTL_CTX_FETCH_NEEDED	(1 << 3)
327 #define   GEN6_MBCTL_BME_UPDATE_ENABLE	(1 << 2)
328 #define   GEN6_MBCTL_MAE_UPDATE_ENABLE	(1 << 1)
329 #define   GEN6_MBCTL_BOOT_FETCH_MECH	(1 << 0)
330 
331 #define GEN6_GDRST	_MMIO(0x941c)
332 #define  GEN6_GRDOM_FULL		(1 << 0)
333 #define  GEN6_GRDOM_RENDER		(1 << 1)
334 #define  GEN6_GRDOM_MEDIA		(1 << 2)
335 #define  GEN6_GRDOM_BLT			(1 << 3)
336 #define  GEN6_GRDOM_VECS		(1 << 4)
337 #define  GEN9_GRDOM_GUC			(1 << 5)
338 #define  GEN8_GRDOM_MEDIA2		(1 << 7)
339 /* GEN11 changed all bit defs except for FULL & RENDER */
340 #define  GEN11_GRDOM_FULL		GEN6_GRDOM_FULL
341 #define  GEN11_GRDOM_RENDER		GEN6_GRDOM_RENDER
342 #define  GEN11_GRDOM_BLT		(1 << 2)
343 #define  GEN11_GRDOM_GUC		(1 << 3)
344 #define  GEN11_GRDOM_MEDIA		(1 << 5)
345 #define  GEN11_GRDOM_MEDIA2		(1 << 6)
346 #define  GEN11_GRDOM_MEDIA3		(1 << 7)
347 #define  GEN11_GRDOM_MEDIA4		(1 << 8)
348 #define  GEN11_GRDOM_VECS		(1 << 13)
349 #define  GEN11_GRDOM_VECS2		(1 << 14)
350 
351 #define RING_PP_DIR_BASE(engine)	_MMIO((engine)->mmio_base + 0x228)
352 #define RING_PP_DIR_BASE_READ(engine)	_MMIO((engine)->mmio_base + 0x518)
353 #define RING_PP_DIR_DCLV(engine)	_MMIO((engine)->mmio_base + 0x220)
354 #define   PP_DIR_DCLV_2G		0xffffffff
355 
356 #define GEN8_RING_PDP_UDW(engine, n)	_MMIO((engine)->mmio_base + 0x270 + (n) * 8 + 4)
357 #define GEN8_RING_PDP_LDW(engine, n)	_MMIO((engine)->mmio_base + 0x270 + (n) * 8)
358 
359 #define GEN8_R_PWR_CLK_STATE		_MMIO(0x20C8)
360 #define   GEN8_RPCS_ENABLE		(1 << 31)
361 #define   GEN8_RPCS_S_CNT_ENABLE	(1 << 18)
362 #define   GEN8_RPCS_S_CNT_SHIFT		15
363 #define   GEN8_RPCS_S_CNT_MASK		(0x7 << GEN8_RPCS_S_CNT_SHIFT)
364 #define   GEN11_RPCS_S_CNT_SHIFT	12
365 #define   GEN11_RPCS_S_CNT_MASK		(0x3f << GEN11_RPCS_S_CNT_SHIFT)
366 #define   GEN8_RPCS_SS_CNT_ENABLE	(1 << 11)
367 #define   GEN8_RPCS_SS_CNT_SHIFT	8
368 #define   GEN8_RPCS_SS_CNT_MASK		(0x7 << GEN8_RPCS_SS_CNT_SHIFT)
369 #define   GEN8_RPCS_EU_MAX_SHIFT	4
370 #define   GEN8_RPCS_EU_MAX_MASK		(0xf << GEN8_RPCS_EU_MAX_SHIFT)
371 #define   GEN8_RPCS_EU_MIN_SHIFT	0
372 #define   GEN8_RPCS_EU_MIN_MASK		(0xf << GEN8_RPCS_EU_MIN_SHIFT)
373 
374 #define WAIT_FOR_RC6_EXIT		_MMIO(0x20CC)
375 /* HSW only */
376 #define   HSW_SELECTIVE_READ_ADDRESSING_SHIFT		2
377 #define   HSW_SELECTIVE_READ_ADDRESSING_MASK		(0x3 << HSW_SLECTIVE_READ_ADDRESSING_SHIFT)
378 #define   HSW_SELECTIVE_WRITE_ADDRESS_SHIFT		4
379 #define   HSW_SELECTIVE_WRITE_ADDRESS_MASK		(0x7 << HSW_SELECTIVE_WRITE_ADDRESS_SHIFT)
380 /* HSW+ */
381 #define   HSW_WAIT_FOR_RC6_EXIT_ENABLE			(1 << 0)
382 #define   HSW_RCS_CONTEXT_ENABLE			(1 << 7)
383 #define   HSW_RCS_INHIBIT				(1 << 8)
384 /* Gen8 */
385 #define   GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT		4
386 #define   GEN8_SELECTIVE_WRITE_ADDRESS_MASK		(0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
387 #define   GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT		4
388 #define   GEN8_SELECTIVE_WRITE_ADDRESS_MASK		(0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
389 #define   GEN8_SELECTIVE_WRITE_ADDRESSING_ENABLE	(1 << 6)
390 #define   GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT	9
391 #define   GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK	(0x3 << GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT)
392 #define   GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT	11
393 #define   GEN8_SELECTIVE_READ_SLICE_SELECT_MASK		(0x3 << GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT)
394 #define   GEN8_SELECTIVE_READ_ADDRESSING_ENABLE         (1 << 13)
395 
396 #define GAM_ECOCHK			_MMIO(0x4090)
397 #define   BDW_DISABLE_HDC_INVALIDATION	(1 << 25)
398 #define   ECOCHK_SNB_BIT		(1 << 10)
399 #define   ECOCHK_DIS_TLB		(1 << 8)
400 #define   HSW_ECOCHK_ARB_PRIO_SOL	(1 << 6)
401 #define   ECOCHK_PPGTT_CACHE64B		(0x3 << 3)
402 #define   ECOCHK_PPGTT_CACHE4B		(0x0 << 3)
403 #define   ECOCHK_PPGTT_GFDT_IVB		(0x1 << 4)
404 #define   ECOCHK_PPGTT_LLC_IVB		(0x1 << 3)
405 #define   ECOCHK_PPGTT_UC_HSW		(0x1 << 3)
406 #define   ECOCHK_PPGTT_WT_HSW		(0x2 << 3)
407 #define   ECOCHK_PPGTT_WB_HSW		(0x3 << 3)
408 
409 #define GAC_ECO_BITS			_MMIO(0x14090)
410 #define   ECOBITS_SNB_BIT		(1 << 13)
411 #define   ECOBITS_PPGTT_CACHE64B	(3 << 8)
412 #define   ECOBITS_PPGTT_CACHE4B		(0 << 8)
413 
414 #define GAB_CTL				_MMIO(0x24000)
415 #define   GAB_CTL_CONT_AFTER_PAGEFAULT	(1 << 8)
416 
417 #define GEN6_STOLEN_RESERVED		_MMIO(0x1082C0)
418 #define GEN6_STOLEN_RESERVED_ADDR_MASK	(0xFFF << 20)
419 #define GEN7_STOLEN_RESERVED_ADDR_MASK	(0x3FFF << 18)
420 #define GEN6_STOLEN_RESERVED_SIZE_MASK	(3 << 4)
421 #define GEN6_STOLEN_RESERVED_1M		(0 << 4)
422 #define GEN6_STOLEN_RESERVED_512K	(1 << 4)
423 #define GEN6_STOLEN_RESERVED_256K	(2 << 4)
424 #define GEN6_STOLEN_RESERVED_128K	(3 << 4)
425 #define GEN7_STOLEN_RESERVED_SIZE_MASK	(1 << 5)
426 #define GEN7_STOLEN_RESERVED_1M		(0 << 5)
427 #define GEN7_STOLEN_RESERVED_256K	(1 << 5)
428 #define GEN8_STOLEN_RESERVED_SIZE_MASK	(3 << 7)
429 #define GEN8_STOLEN_RESERVED_1M		(0 << 7)
430 #define GEN8_STOLEN_RESERVED_2M		(1 << 7)
431 #define GEN8_STOLEN_RESERVED_4M		(2 << 7)
432 #define GEN8_STOLEN_RESERVED_8M		(3 << 7)
433 #define GEN6_STOLEN_RESERVED_ENABLE	(1 << 0)
434 #define GEN11_STOLEN_RESERVED_ADDR_MASK	(0xFFFFFFFFFFFULL << 20)
435 
436 /* VGA stuff */
437 
438 #define VGA_ST01_MDA 0x3ba
439 #define VGA_ST01_CGA 0x3da
440 
441 #define _VGA_MSR_WRITE _MMIO(0x3c2)
442 #define VGA_MSR_WRITE 0x3c2
443 #define VGA_MSR_READ 0x3cc
444 #define   VGA_MSR_MEM_EN (1 << 1)
445 #define   VGA_MSR_CGA_MODE (1 << 0)
446 
447 #define VGA_SR_INDEX 0x3c4
448 #define SR01			1
449 #define VGA_SR_DATA 0x3c5
450 
451 #define VGA_AR_INDEX 0x3c0
452 #define   VGA_AR_VID_EN (1 << 5)
453 #define VGA_AR_DATA_WRITE 0x3c0
454 #define VGA_AR_DATA_READ 0x3c1
455 
456 #define VGA_GR_INDEX 0x3ce
457 #define VGA_GR_DATA 0x3cf
458 /* GR05 */
459 #define   VGA_GR_MEM_READ_MODE_SHIFT 3
460 #define     VGA_GR_MEM_READ_MODE_PLANE 1
461 /* GR06 */
462 #define   VGA_GR_MEM_MODE_MASK 0xc
463 #define   VGA_GR_MEM_MODE_SHIFT 2
464 #define   VGA_GR_MEM_A0000_AFFFF 0
465 #define   VGA_GR_MEM_A0000_BFFFF 1
466 #define   VGA_GR_MEM_B0000_B7FFF 2
467 #define   VGA_GR_MEM_B0000_BFFFF 3
468 
469 #define VGA_DACMASK 0x3c6
470 #define VGA_DACRX 0x3c7
471 #define VGA_DACWX 0x3c8
472 #define VGA_DACDATA 0x3c9
473 
474 #define VGA_CR_INDEX_MDA 0x3b4
475 #define VGA_CR_DATA_MDA 0x3b5
476 #define VGA_CR_INDEX_CGA 0x3d4
477 #define VGA_CR_DATA_CGA 0x3d5
478 
479 #define MI_PREDICATE_SRC0	_MMIO(0x2400)
480 #define MI_PREDICATE_SRC0_UDW	_MMIO(0x2400 + 4)
481 #define MI_PREDICATE_SRC1	_MMIO(0x2408)
482 #define MI_PREDICATE_SRC1_UDW	_MMIO(0x2408 + 4)
483 
484 #define MI_PREDICATE_RESULT_2	_MMIO(0x2214)
485 #define  LOWER_SLICE_ENABLED	(1 << 0)
486 #define  LOWER_SLICE_DISABLED	(0 << 0)
487 
488 /*
489  * Registers used only by the command parser
490  */
491 #define BCS_SWCTRL _MMIO(0x22200)
492 
493 #define GPGPU_THREADS_DISPATCHED        _MMIO(0x2290)
494 #define GPGPU_THREADS_DISPATCHED_UDW	_MMIO(0x2290 + 4)
495 #define HS_INVOCATION_COUNT             _MMIO(0x2300)
496 #define HS_INVOCATION_COUNT_UDW		_MMIO(0x2300 + 4)
497 #define DS_INVOCATION_COUNT             _MMIO(0x2308)
498 #define DS_INVOCATION_COUNT_UDW		_MMIO(0x2308 + 4)
499 #define IA_VERTICES_COUNT               _MMIO(0x2310)
500 #define IA_VERTICES_COUNT_UDW		_MMIO(0x2310 + 4)
501 #define IA_PRIMITIVES_COUNT             _MMIO(0x2318)
502 #define IA_PRIMITIVES_COUNT_UDW		_MMIO(0x2318 + 4)
503 #define VS_INVOCATION_COUNT             _MMIO(0x2320)
504 #define VS_INVOCATION_COUNT_UDW		_MMIO(0x2320 + 4)
505 #define GS_INVOCATION_COUNT             _MMIO(0x2328)
506 #define GS_INVOCATION_COUNT_UDW		_MMIO(0x2328 + 4)
507 #define GS_PRIMITIVES_COUNT             _MMIO(0x2330)
508 #define GS_PRIMITIVES_COUNT_UDW		_MMIO(0x2330 + 4)
509 #define CL_INVOCATION_COUNT             _MMIO(0x2338)
510 #define CL_INVOCATION_COUNT_UDW		_MMIO(0x2338 + 4)
511 #define CL_PRIMITIVES_COUNT             _MMIO(0x2340)
512 #define CL_PRIMITIVES_COUNT_UDW		_MMIO(0x2340 + 4)
513 #define PS_INVOCATION_COUNT             _MMIO(0x2348)
514 #define PS_INVOCATION_COUNT_UDW		_MMIO(0x2348 + 4)
515 #define PS_DEPTH_COUNT                  _MMIO(0x2350)
516 #define PS_DEPTH_COUNT_UDW		_MMIO(0x2350 + 4)
517 
518 /* There are the 4 64-bit counter registers, one for each stream output */
519 #define GEN7_SO_NUM_PRIMS_WRITTEN(n)		_MMIO(0x5200 + (n) * 8)
520 #define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n)	_MMIO(0x5200 + (n) * 8 + 4)
521 
522 #define GEN7_SO_PRIM_STORAGE_NEEDED(n)		_MMIO(0x5240 + (n) * 8)
523 #define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n)	_MMIO(0x5240 + (n) * 8 + 4)
524 
525 #define GEN7_3DPRIM_END_OFFSET          _MMIO(0x2420)
526 #define GEN7_3DPRIM_START_VERTEX        _MMIO(0x2430)
527 #define GEN7_3DPRIM_VERTEX_COUNT        _MMIO(0x2434)
528 #define GEN7_3DPRIM_INSTANCE_COUNT      _MMIO(0x2438)
529 #define GEN7_3DPRIM_START_INSTANCE      _MMIO(0x243C)
530 #define GEN7_3DPRIM_BASE_VERTEX         _MMIO(0x2440)
531 
532 #define GEN7_GPGPU_DISPATCHDIMX         _MMIO(0x2500)
533 #define GEN7_GPGPU_DISPATCHDIMY         _MMIO(0x2504)
534 #define GEN7_GPGPU_DISPATCHDIMZ         _MMIO(0x2508)
535 
536 /* There are the 16 64-bit CS General Purpose Registers */
537 #define HSW_CS_GPR(n)                   _MMIO(0x2600 + (n) * 8)
538 #define HSW_CS_GPR_UDW(n)               _MMIO(0x2600 + (n) * 8 + 4)
539 
540 #define GEN7_OACONTROL _MMIO(0x2360)
541 #define  GEN7_OACONTROL_CTX_MASK	    0xFFFFF000
542 #define  GEN7_OACONTROL_TIMER_PERIOD_MASK   0x3F
543 #define  GEN7_OACONTROL_TIMER_PERIOD_SHIFT  6
544 #define  GEN7_OACONTROL_TIMER_ENABLE	    (1 << 5)
545 #define  GEN7_OACONTROL_FORMAT_A13	    (0 << 2)
546 #define  GEN7_OACONTROL_FORMAT_A29	    (1 << 2)
547 #define  GEN7_OACONTROL_FORMAT_A13_B8_C8    (2 << 2)
548 #define  GEN7_OACONTROL_FORMAT_A29_B8_C8    (3 << 2)
549 #define  GEN7_OACONTROL_FORMAT_B4_C8	    (4 << 2)
550 #define  GEN7_OACONTROL_FORMAT_A45_B8_C8    (5 << 2)
551 #define  GEN7_OACONTROL_FORMAT_B4_C8_A16    (6 << 2)
552 #define  GEN7_OACONTROL_FORMAT_C4_B8	    (7 << 2)
553 #define  GEN7_OACONTROL_FORMAT_SHIFT	    2
554 #define  GEN7_OACONTROL_PER_CTX_ENABLE	    (1 << 1)
555 #define  GEN7_OACONTROL_ENABLE		    (1 << 0)
556 
557 #define GEN8_OACTXID _MMIO(0x2364)
558 
559 #define GEN8_OA_DEBUG _MMIO(0x2B04)
560 #define  GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS    (1 << 5)
561 #define  GEN9_OA_DEBUG_INCLUDE_CLK_RATIO	    (1 << 6)
562 #define  GEN9_OA_DEBUG_DISABLE_GO_1_0_REPORTS	    (1 << 2)
563 #define  GEN9_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS   (1 << 1)
564 
565 #define GEN8_OACONTROL _MMIO(0x2B00)
566 #define  GEN8_OA_REPORT_FORMAT_A12	    (0 << 2)
567 #define  GEN8_OA_REPORT_FORMAT_A12_B8_C8    (2 << 2)
568 #define  GEN8_OA_REPORT_FORMAT_A36_B8_C8    (5 << 2)
569 #define  GEN8_OA_REPORT_FORMAT_C4_B8	    (7 << 2)
570 #define  GEN8_OA_REPORT_FORMAT_SHIFT	    2
571 #define  GEN8_OA_SPECIFIC_CONTEXT_ENABLE    (1 << 1)
572 #define  GEN8_OA_COUNTER_ENABLE             (1 << 0)
573 
574 #define GEN8_OACTXCONTROL _MMIO(0x2360)
575 #define  GEN8_OA_TIMER_PERIOD_MASK	    0x3F
576 #define  GEN8_OA_TIMER_PERIOD_SHIFT	    2
577 #define  GEN8_OA_TIMER_ENABLE		    (1 << 1)
578 #define  GEN8_OA_COUNTER_RESUME		    (1 << 0)
579 
580 #define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */
581 #define  GEN7_OABUFFER_OVERRUN_DISABLE	    (1 << 3)
582 #define  GEN7_OABUFFER_EDGE_TRIGGER	    (1 << 2)
583 #define  GEN7_OABUFFER_STOP_RESUME_ENABLE   (1 << 1)
584 #define  GEN7_OABUFFER_RESUME		    (1 << 0)
585 
586 #define GEN8_OABUFFER_UDW _MMIO(0x23b4)
587 #define GEN8_OABUFFER _MMIO(0x2b14)
588 #define  GEN8_OABUFFER_MEM_SELECT_GGTT      (1 << 0)  /* 0: PPGTT, 1: GGTT */
589 
590 #define GEN7_OASTATUS1 _MMIO(0x2364)
591 #define  GEN7_OASTATUS1_TAIL_MASK	    0xffffffc0
592 #define  GEN7_OASTATUS1_COUNTER_OVERFLOW    (1 << 2)
593 #define  GEN7_OASTATUS1_OABUFFER_OVERFLOW   (1 << 1)
594 #define  GEN7_OASTATUS1_REPORT_LOST	    (1 << 0)
595 
596 #define GEN7_OASTATUS2 _MMIO(0x2368)
597 #define  GEN7_OASTATUS2_HEAD_MASK           0xffffffc0
598 #define  GEN7_OASTATUS2_MEM_SELECT_GGTT     (1 << 0) /* 0: PPGTT, 1: GGTT */
599 
600 #define GEN8_OASTATUS _MMIO(0x2b08)
601 #define  GEN8_OASTATUS_OVERRUN_STATUS	    (1 << 3)
602 #define  GEN8_OASTATUS_COUNTER_OVERFLOW     (1 << 2)
603 #define  GEN8_OASTATUS_OABUFFER_OVERFLOW    (1 << 1)
604 #define  GEN8_OASTATUS_REPORT_LOST	    (1 << 0)
605 
606 #define GEN8_OAHEADPTR _MMIO(0x2B0C)
607 #define GEN8_OAHEADPTR_MASK    0xffffffc0
608 #define GEN8_OATAILPTR _MMIO(0x2B10)
609 #define GEN8_OATAILPTR_MASK    0xffffffc0
610 
611 #define OABUFFER_SIZE_128K  (0 << 3)
612 #define OABUFFER_SIZE_256K  (1 << 3)
613 #define OABUFFER_SIZE_512K  (2 << 3)
614 #define OABUFFER_SIZE_1M    (3 << 3)
615 #define OABUFFER_SIZE_2M    (4 << 3)
616 #define OABUFFER_SIZE_4M    (5 << 3)
617 #define OABUFFER_SIZE_8M    (6 << 3)
618 #define OABUFFER_SIZE_16M   (7 << 3)
619 
620 /*
621  * Flexible, Aggregate EU Counter Registers.
622  * Note: these aren't contiguous
623  */
624 #define EU_PERF_CNTL0	    _MMIO(0xe458)
625 #define EU_PERF_CNTL1	    _MMIO(0xe558)
626 #define EU_PERF_CNTL2	    _MMIO(0xe658)
627 #define EU_PERF_CNTL3	    _MMIO(0xe758)
628 #define EU_PERF_CNTL4	    _MMIO(0xe45c)
629 #define EU_PERF_CNTL5	    _MMIO(0xe55c)
630 #define EU_PERF_CNTL6	    _MMIO(0xe65c)
631 
632 /*
633  * OA Boolean state
634  */
635 
636 #define OASTARTTRIG1 _MMIO(0x2710)
637 #define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
638 #define OASTARTTRIG1_THRESHOLD_MASK	      0xffff
639 
640 #define OASTARTTRIG2 _MMIO(0x2714)
641 #define OASTARTTRIG2_INVERT_A_0 (1 << 0)
642 #define OASTARTTRIG2_INVERT_A_1 (1 << 1)
643 #define OASTARTTRIG2_INVERT_A_2 (1 << 2)
644 #define OASTARTTRIG2_INVERT_A_3 (1 << 3)
645 #define OASTARTTRIG2_INVERT_A_4 (1 << 4)
646 #define OASTARTTRIG2_INVERT_A_5 (1 << 5)
647 #define OASTARTTRIG2_INVERT_A_6 (1 << 6)
648 #define OASTARTTRIG2_INVERT_A_7 (1 << 7)
649 #define OASTARTTRIG2_INVERT_A_8 (1 << 8)
650 #define OASTARTTRIG2_INVERT_A_9 (1 << 9)
651 #define OASTARTTRIG2_INVERT_A_10 (1 << 10)
652 #define OASTARTTRIG2_INVERT_A_11 (1 << 11)
653 #define OASTARTTRIG2_INVERT_A_12 (1 << 12)
654 #define OASTARTTRIG2_INVERT_A_13 (1 << 13)
655 #define OASTARTTRIG2_INVERT_A_14 (1 << 14)
656 #define OASTARTTRIG2_INVERT_A_15 (1 << 15)
657 #define OASTARTTRIG2_INVERT_B_0 (1 << 16)
658 #define OASTARTTRIG2_INVERT_B_1 (1 << 17)
659 #define OASTARTTRIG2_INVERT_B_2 (1 << 18)
660 #define OASTARTTRIG2_INVERT_B_3 (1 << 19)
661 #define OASTARTTRIG2_INVERT_C_0 (1 << 20)
662 #define OASTARTTRIG2_INVERT_C_1 (1 << 21)
663 #define OASTARTTRIG2_INVERT_D_0 (1 << 22)
664 #define OASTARTTRIG2_THRESHOLD_ENABLE	    (1 << 23)
665 #define OASTARTTRIG2_START_TRIG_FLAG_MBZ    (1 << 24)
666 #define OASTARTTRIG2_EVENT_SELECT_0  (1 << 28)
667 #define OASTARTTRIG2_EVENT_SELECT_1  (1 << 29)
668 #define OASTARTTRIG2_EVENT_SELECT_2  (1 << 30)
669 #define OASTARTTRIG2_EVENT_SELECT_3  (1 << 31)
670 
671 #define OASTARTTRIG3 _MMIO(0x2718)
672 #define OASTARTTRIG3_NOA_SELECT_MASK	   0xf
673 #define OASTARTTRIG3_NOA_SELECT_8_SHIFT    0
674 #define OASTARTTRIG3_NOA_SELECT_9_SHIFT    4
675 #define OASTARTTRIG3_NOA_SELECT_10_SHIFT   8
676 #define OASTARTTRIG3_NOA_SELECT_11_SHIFT   12
677 #define OASTARTTRIG3_NOA_SELECT_12_SHIFT   16
678 #define OASTARTTRIG3_NOA_SELECT_13_SHIFT   20
679 #define OASTARTTRIG3_NOA_SELECT_14_SHIFT   24
680 #define OASTARTTRIG3_NOA_SELECT_15_SHIFT   28
681 
682 #define OASTARTTRIG4 _MMIO(0x271c)
683 #define OASTARTTRIG4_NOA_SELECT_MASK	    0xf
684 #define OASTARTTRIG4_NOA_SELECT_0_SHIFT    0
685 #define OASTARTTRIG4_NOA_SELECT_1_SHIFT    4
686 #define OASTARTTRIG4_NOA_SELECT_2_SHIFT    8
687 #define OASTARTTRIG4_NOA_SELECT_3_SHIFT    12
688 #define OASTARTTRIG4_NOA_SELECT_4_SHIFT    16
689 #define OASTARTTRIG4_NOA_SELECT_5_SHIFT    20
690 #define OASTARTTRIG4_NOA_SELECT_6_SHIFT    24
691 #define OASTARTTRIG4_NOA_SELECT_7_SHIFT    28
692 
693 #define OASTARTTRIG5 _MMIO(0x2720)
694 #define OASTARTTRIG5_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
695 #define OASTARTTRIG5_THRESHOLD_MASK	      0xffff
696 
697 #define OASTARTTRIG6 _MMIO(0x2724)
698 #define OASTARTTRIG6_INVERT_A_0 (1 << 0)
699 #define OASTARTTRIG6_INVERT_A_1 (1 << 1)
700 #define OASTARTTRIG6_INVERT_A_2 (1 << 2)
701 #define OASTARTTRIG6_INVERT_A_3 (1 << 3)
702 #define OASTARTTRIG6_INVERT_A_4 (1 << 4)
703 #define OASTARTTRIG6_INVERT_A_5 (1 << 5)
704 #define OASTARTTRIG6_INVERT_A_6 (1 << 6)
705 #define OASTARTTRIG6_INVERT_A_7 (1 << 7)
706 #define OASTARTTRIG6_INVERT_A_8 (1 << 8)
707 #define OASTARTTRIG6_INVERT_A_9 (1 << 9)
708 #define OASTARTTRIG6_INVERT_A_10 (1 << 10)
709 #define OASTARTTRIG6_INVERT_A_11 (1 << 11)
710 #define OASTARTTRIG6_INVERT_A_12 (1 << 12)
711 #define OASTARTTRIG6_INVERT_A_13 (1 << 13)
712 #define OASTARTTRIG6_INVERT_A_14 (1 << 14)
713 #define OASTARTTRIG6_INVERT_A_15 (1 << 15)
714 #define OASTARTTRIG6_INVERT_B_0 (1 << 16)
715 #define OASTARTTRIG6_INVERT_B_1 (1 << 17)
716 #define OASTARTTRIG6_INVERT_B_2 (1 << 18)
717 #define OASTARTTRIG6_INVERT_B_3 (1 << 19)
718 #define OASTARTTRIG6_INVERT_C_0 (1 << 20)
719 #define OASTARTTRIG6_INVERT_C_1 (1 << 21)
720 #define OASTARTTRIG6_INVERT_D_0 (1 << 22)
721 #define OASTARTTRIG6_THRESHOLD_ENABLE	    (1 << 23)
722 #define OASTARTTRIG6_START_TRIG_FLAG_MBZ    (1 << 24)
723 #define OASTARTTRIG6_EVENT_SELECT_4  (1 << 28)
724 #define OASTARTTRIG6_EVENT_SELECT_5  (1 << 29)
725 #define OASTARTTRIG6_EVENT_SELECT_6  (1 << 30)
726 #define OASTARTTRIG6_EVENT_SELECT_7  (1 << 31)
727 
728 #define OASTARTTRIG7 _MMIO(0x2728)
729 #define OASTARTTRIG7_NOA_SELECT_MASK	   0xf
730 #define OASTARTTRIG7_NOA_SELECT_8_SHIFT    0
731 #define OASTARTTRIG7_NOA_SELECT_9_SHIFT    4
732 #define OASTARTTRIG7_NOA_SELECT_10_SHIFT   8
733 #define OASTARTTRIG7_NOA_SELECT_11_SHIFT   12
734 #define OASTARTTRIG7_NOA_SELECT_12_SHIFT   16
735 #define OASTARTTRIG7_NOA_SELECT_13_SHIFT   20
736 #define OASTARTTRIG7_NOA_SELECT_14_SHIFT   24
737 #define OASTARTTRIG7_NOA_SELECT_15_SHIFT   28
738 
739 #define OASTARTTRIG8 _MMIO(0x272c)
740 #define OASTARTTRIG8_NOA_SELECT_MASK	   0xf
741 #define OASTARTTRIG8_NOA_SELECT_0_SHIFT    0
742 #define OASTARTTRIG8_NOA_SELECT_1_SHIFT    4
743 #define OASTARTTRIG8_NOA_SELECT_2_SHIFT    8
744 #define OASTARTTRIG8_NOA_SELECT_3_SHIFT    12
745 #define OASTARTTRIG8_NOA_SELECT_4_SHIFT    16
746 #define OASTARTTRIG8_NOA_SELECT_5_SHIFT    20
747 #define OASTARTTRIG8_NOA_SELECT_6_SHIFT    24
748 #define OASTARTTRIG8_NOA_SELECT_7_SHIFT    28
749 
750 #define OAREPORTTRIG1 _MMIO(0x2740)
751 #define OAREPORTTRIG1_THRESHOLD_MASK 0xffff
752 #define OAREPORTTRIG1_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */
753 
754 #define OAREPORTTRIG2 _MMIO(0x2744)
755 #define OAREPORTTRIG2_INVERT_A_0  (1 << 0)
756 #define OAREPORTTRIG2_INVERT_A_1  (1 << 1)
757 #define OAREPORTTRIG2_INVERT_A_2  (1 << 2)
758 #define OAREPORTTRIG2_INVERT_A_3  (1 << 3)
759 #define OAREPORTTRIG2_INVERT_A_4  (1 << 4)
760 #define OAREPORTTRIG2_INVERT_A_5  (1 << 5)
761 #define OAREPORTTRIG2_INVERT_A_6  (1 << 6)
762 #define OAREPORTTRIG2_INVERT_A_7  (1 << 7)
763 #define OAREPORTTRIG2_INVERT_A_8  (1 << 8)
764 #define OAREPORTTRIG2_INVERT_A_9  (1 << 9)
765 #define OAREPORTTRIG2_INVERT_A_10 (1 << 10)
766 #define OAREPORTTRIG2_INVERT_A_11 (1 << 11)
767 #define OAREPORTTRIG2_INVERT_A_12 (1 << 12)
768 #define OAREPORTTRIG2_INVERT_A_13 (1 << 13)
769 #define OAREPORTTRIG2_INVERT_A_14 (1 << 14)
770 #define OAREPORTTRIG2_INVERT_A_15 (1 << 15)
771 #define OAREPORTTRIG2_INVERT_B_0  (1 << 16)
772 #define OAREPORTTRIG2_INVERT_B_1  (1 << 17)
773 #define OAREPORTTRIG2_INVERT_B_2  (1 << 18)
774 #define OAREPORTTRIG2_INVERT_B_3  (1 << 19)
775 #define OAREPORTTRIG2_INVERT_C_0  (1 << 20)
776 #define OAREPORTTRIG2_INVERT_C_1  (1 << 21)
777 #define OAREPORTTRIG2_INVERT_D_0  (1 << 22)
778 #define OAREPORTTRIG2_THRESHOLD_ENABLE	    (1 << 23)
779 #define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1 << 31)
780 
781 #define OAREPORTTRIG3 _MMIO(0x2748)
782 #define OAREPORTTRIG3_NOA_SELECT_MASK	    0xf
783 #define OAREPORTTRIG3_NOA_SELECT_8_SHIFT    0
784 #define OAREPORTTRIG3_NOA_SELECT_9_SHIFT    4
785 #define OAREPORTTRIG3_NOA_SELECT_10_SHIFT   8
786 #define OAREPORTTRIG3_NOA_SELECT_11_SHIFT   12
787 #define OAREPORTTRIG3_NOA_SELECT_12_SHIFT   16
788 #define OAREPORTTRIG3_NOA_SELECT_13_SHIFT   20
789 #define OAREPORTTRIG3_NOA_SELECT_14_SHIFT   24
790 #define OAREPORTTRIG3_NOA_SELECT_15_SHIFT   28
791 
792 #define OAREPORTTRIG4 _MMIO(0x274c)
793 #define OAREPORTTRIG4_NOA_SELECT_MASK	    0xf
794 #define OAREPORTTRIG4_NOA_SELECT_0_SHIFT    0
795 #define OAREPORTTRIG4_NOA_SELECT_1_SHIFT    4
796 #define OAREPORTTRIG4_NOA_SELECT_2_SHIFT    8
797 #define OAREPORTTRIG4_NOA_SELECT_3_SHIFT    12
798 #define OAREPORTTRIG4_NOA_SELECT_4_SHIFT    16
799 #define OAREPORTTRIG4_NOA_SELECT_5_SHIFT    20
800 #define OAREPORTTRIG4_NOA_SELECT_6_SHIFT    24
801 #define OAREPORTTRIG4_NOA_SELECT_7_SHIFT    28
802 
803 #define OAREPORTTRIG5 _MMIO(0x2750)
804 #define OAREPORTTRIG5_THRESHOLD_MASK 0xffff
805 #define OAREPORTTRIG5_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */
806 
807 #define OAREPORTTRIG6 _MMIO(0x2754)
808 #define OAREPORTTRIG6_INVERT_A_0  (1 << 0)
809 #define OAREPORTTRIG6_INVERT_A_1  (1 << 1)
810 #define OAREPORTTRIG6_INVERT_A_2  (1 << 2)
811 #define OAREPORTTRIG6_INVERT_A_3  (1 << 3)
812 #define OAREPORTTRIG6_INVERT_A_4  (1 << 4)
813 #define OAREPORTTRIG6_INVERT_A_5  (1 << 5)
814 #define OAREPORTTRIG6_INVERT_A_6  (1 << 6)
815 #define OAREPORTTRIG6_INVERT_A_7  (1 << 7)
816 #define OAREPORTTRIG6_INVERT_A_8  (1 << 8)
817 #define OAREPORTTRIG6_INVERT_A_9  (1 << 9)
818 #define OAREPORTTRIG6_INVERT_A_10 (1 << 10)
819 #define OAREPORTTRIG6_INVERT_A_11 (1 << 11)
820 #define OAREPORTTRIG6_INVERT_A_12 (1 << 12)
821 #define OAREPORTTRIG6_INVERT_A_13 (1 << 13)
822 #define OAREPORTTRIG6_INVERT_A_14 (1 << 14)
823 #define OAREPORTTRIG6_INVERT_A_15 (1 << 15)
824 #define OAREPORTTRIG6_INVERT_B_0  (1 << 16)
825 #define OAREPORTTRIG6_INVERT_B_1  (1 << 17)
826 #define OAREPORTTRIG6_INVERT_B_2  (1 << 18)
827 #define OAREPORTTRIG6_INVERT_B_3  (1 << 19)
828 #define OAREPORTTRIG6_INVERT_C_0  (1 << 20)
829 #define OAREPORTTRIG6_INVERT_C_1  (1 << 21)
830 #define OAREPORTTRIG6_INVERT_D_0  (1 << 22)
831 #define OAREPORTTRIG6_THRESHOLD_ENABLE	    (1 << 23)
832 #define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1 << 31)
833 
834 #define OAREPORTTRIG7 _MMIO(0x2758)
835 #define OAREPORTTRIG7_NOA_SELECT_MASK	    0xf
836 #define OAREPORTTRIG7_NOA_SELECT_8_SHIFT    0
837 #define OAREPORTTRIG7_NOA_SELECT_9_SHIFT    4
838 #define OAREPORTTRIG7_NOA_SELECT_10_SHIFT   8
839 #define OAREPORTTRIG7_NOA_SELECT_11_SHIFT   12
840 #define OAREPORTTRIG7_NOA_SELECT_12_SHIFT   16
841 #define OAREPORTTRIG7_NOA_SELECT_13_SHIFT   20
842 #define OAREPORTTRIG7_NOA_SELECT_14_SHIFT   24
843 #define OAREPORTTRIG7_NOA_SELECT_15_SHIFT   28
844 
845 #define OAREPORTTRIG8 _MMIO(0x275c)
846 #define OAREPORTTRIG8_NOA_SELECT_MASK	    0xf
847 #define OAREPORTTRIG8_NOA_SELECT_0_SHIFT    0
848 #define OAREPORTTRIG8_NOA_SELECT_1_SHIFT    4
849 #define OAREPORTTRIG8_NOA_SELECT_2_SHIFT    8
850 #define OAREPORTTRIG8_NOA_SELECT_3_SHIFT    12
851 #define OAREPORTTRIG8_NOA_SELECT_4_SHIFT    16
852 #define OAREPORTTRIG8_NOA_SELECT_5_SHIFT    20
853 #define OAREPORTTRIG8_NOA_SELECT_6_SHIFT    24
854 #define OAREPORTTRIG8_NOA_SELECT_7_SHIFT    28
855 
856 /* CECX_0 */
857 #define OACEC_COMPARE_LESS_OR_EQUAL	6
858 #define OACEC_COMPARE_NOT_EQUAL		5
859 #define OACEC_COMPARE_LESS_THAN		4
860 #define OACEC_COMPARE_GREATER_OR_EQUAL	3
861 #define OACEC_COMPARE_EQUAL		2
862 #define OACEC_COMPARE_GREATER_THAN	1
863 #define OACEC_COMPARE_ANY_EQUAL		0
864 
865 #define OACEC_COMPARE_VALUE_MASK    0xffff
866 #define OACEC_COMPARE_VALUE_SHIFT   3
867 
868 #define OACEC_SELECT_NOA	(0 << 19)
869 #define OACEC_SELECT_PREV	(1 << 19)
870 #define OACEC_SELECT_BOOLEAN	(2 << 19)
871 
872 /* CECX_1 */
873 #define OACEC_MASK_MASK		    0xffff
874 #define OACEC_CONSIDERATIONS_MASK   0xffff
875 #define OACEC_CONSIDERATIONS_SHIFT  16
876 
877 #define OACEC0_0 _MMIO(0x2770)
878 #define OACEC0_1 _MMIO(0x2774)
879 #define OACEC1_0 _MMIO(0x2778)
880 #define OACEC1_1 _MMIO(0x277c)
881 #define OACEC2_0 _MMIO(0x2780)
882 #define OACEC2_1 _MMIO(0x2784)
883 #define OACEC3_0 _MMIO(0x2788)
884 #define OACEC3_1 _MMIO(0x278c)
885 #define OACEC4_0 _MMIO(0x2790)
886 #define OACEC4_1 _MMIO(0x2794)
887 #define OACEC5_0 _MMIO(0x2798)
888 #define OACEC5_1 _MMIO(0x279c)
889 #define OACEC6_0 _MMIO(0x27a0)
890 #define OACEC6_1 _MMIO(0x27a4)
891 #define OACEC7_0 _MMIO(0x27a8)
892 #define OACEC7_1 _MMIO(0x27ac)
893 
894 /* OA perf counters */
895 #define OA_PERFCNT1_LO      _MMIO(0x91B8)
896 #define OA_PERFCNT1_HI      _MMIO(0x91BC)
897 #define OA_PERFCNT2_LO      _MMIO(0x91C0)
898 #define OA_PERFCNT2_HI      _MMIO(0x91C4)
899 #define OA_PERFCNT3_LO      _MMIO(0x91C8)
900 #define OA_PERFCNT3_HI      _MMIO(0x91CC)
901 #define OA_PERFCNT4_LO      _MMIO(0x91D8)
902 #define OA_PERFCNT4_HI      _MMIO(0x91DC)
903 
904 #define OA_PERFMATRIX_LO    _MMIO(0x91C8)
905 #define OA_PERFMATRIX_HI    _MMIO(0x91CC)
906 
907 /* RPM unit config (Gen8+) */
908 #define RPM_CONFIG0	    _MMIO(0x0D00)
909 #define  GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT	3
910 #define  GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK	(1 << GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
911 #define  GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ	0
912 #define  GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ	1
913 #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT	3
914 #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK	(0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
915 #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ	0
916 #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ	1
917 #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ	2
918 #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ	3
919 #define  GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT	1
920 #define  GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK	(0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT)
921 
922 #define RPM_CONFIG1	    _MMIO(0x0D04)
923 #define  GEN10_GT_NOA_ENABLE  (1 << 9)
924 
925 /* GPM unit config (Gen9+) */
926 #define CTC_MODE			_MMIO(0xA26C)
927 #define  CTC_SOURCE_PARAMETER_MASK 1
928 #define  CTC_SOURCE_CRYSTAL_CLOCK	0
929 #define  CTC_SOURCE_DIVIDE_LOGIC	1
930 #define  CTC_SHIFT_PARAMETER_SHIFT	1
931 #define  CTC_SHIFT_PARAMETER_MASK	(0x3 << CTC_SHIFT_PARAMETER_SHIFT)
932 
933 /* RCP unit config (Gen8+) */
934 #define RCP_CONFIG	    _MMIO(0x0D08)
935 
936 /* NOA (HSW) */
937 #define HSW_MBVID2_NOA0		_MMIO(0x9E80)
938 #define HSW_MBVID2_NOA1		_MMIO(0x9E84)
939 #define HSW_MBVID2_NOA2		_MMIO(0x9E88)
940 #define HSW_MBVID2_NOA3		_MMIO(0x9E8C)
941 #define HSW_MBVID2_NOA4		_MMIO(0x9E90)
942 #define HSW_MBVID2_NOA5		_MMIO(0x9E94)
943 #define HSW_MBVID2_NOA6		_MMIO(0x9E98)
944 #define HSW_MBVID2_NOA7		_MMIO(0x9E9C)
945 #define HSW_MBVID2_NOA8		_MMIO(0x9EA0)
946 #define HSW_MBVID2_NOA9		_MMIO(0x9EA4)
947 
948 #define HSW_MBVID2_MISR0	_MMIO(0x9EC0)
949 
950 /* NOA (Gen8+) */
951 #define NOA_CONFIG(i)	    _MMIO(0x0D0C + (i) * 4)
952 
953 #define MICRO_BP0_0	    _MMIO(0x9800)
954 #define MICRO_BP0_2	    _MMIO(0x9804)
955 #define MICRO_BP0_1	    _MMIO(0x9808)
956 
957 #define MICRO_BP1_0	    _MMIO(0x980C)
958 #define MICRO_BP1_2	    _MMIO(0x9810)
959 #define MICRO_BP1_1	    _MMIO(0x9814)
960 
961 #define MICRO_BP2_0	    _MMIO(0x9818)
962 #define MICRO_BP2_2	    _MMIO(0x981C)
963 #define MICRO_BP2_1	    _MMIO(0x9820)
964 
965 #define MICRO_BP3_0	    _MMIO(0x9824)
966 #define MICRO_BP3_2	    _MMIO(0x9828)
967 #define MICRO_BP3_1	    _MMIO(0x982C)
968 
969 #define MICRO_BP_TRIGGER		_MMIO(0x9830)
970 #define MICRO_BP3_COUNT_STATUS01	_MMIO(0x9834)
971 #define MICRO_BP3_COUNT_STATUS23	_MMIO(0x9838)
972 #define MICRO_BP_FIRED_ARMED		_MMIO(0x983C)
973 
974 #define GDT_CHICKEN_BITS    _MMIO(0x9840)
975 #define   GT_NOA_ENABLE	    0x00000080
976 
977 #define NOA_DATA	    _MMIO(0x986C)
978 #define NOA_WRITE	    _MMIO(0x9888)
979 
980 #define _GEN7_PIPEA_DE_LOAD_SL	0x70068
981 #define _GEN7_PIPEB_DE_LOAD_SL	0x71068
982 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
983 
984 /*
985  * Reset registers
986  */
987 #define DEBUG_RESET_I830		_MMIO(0x6070)
988 #define  DEBUG_RESET_FULL		(1 << 7)
989 #define  DEBUG_RESET_RENDER		(1 << 8)
990 #define  DEBUG_RESET_DISPLAY		(1 << 9)
991 
992 /*
993  * IOSF sideband
994  */
995 #define VLV_IOSF_DOORBELL_REQ			_MMIO(VLV_DISPLAY_BASE + 0x2100)
996 #define   IOSF_DEVFN_SHIFT			24
997 #define   IOSF_OPCODE_SHIFT			16
998 #define   IOSF_PORT_SHIFT			8
999 #define   IOSF_BYTE_ENABLES_SHIFT		4
1000 #define   IOSF_BAR_SHIFT			1
1001 #define   IOSF_SB_BUSY				(1 << 0)
1002 #define   IOSF_PORT_BUNIT			0x03
1003 #define   IOSF_PORT_PUNIT			0x04
1004 #define   IOSF_PORT_NC				0x11
1005 #define   IOSF_PORT_DPIO			0x12
1006 #define   IOSF_PORT_GPIO_NC			0x13
1007 #define   IOSF_PORT_CCK				0x14
1008 #define   IOSF_PORT_DPIO_2			0x1a
1009 #define   IOSF_PORT_FLISDSI			0x1b
1010 #define   IOSF_PORT_GPIO_SC			0x48
1011 #define   IOSF_PORT_GPIO_SUS			0xa8
1012 #define   IOSF_PORT_CCU				0xa9
1013 #define   CHV_IOSF_PORT_GPIO_N			0x13
1014 #define   CHV_IOSF_PORT_GPIO_SE			0x48
1015 #define   CHV_IOSF_PORT_GPIO_E			0xa8
1016 #define   CHV_IOSF_PORT_GPIO_SW			0xb2
1017 #define VLV_IOSF_DATA				_MMIO(VLV_DISPLAY_BASE + 0x2104)
1018 #define VLV_IOSF_ADDR				_MMIO(VLV_DISPLAY_BASE + 0x2108)
1019 
1020 /* See configdb bunit SB addr map */
1021 #define BUNIT_REG_BISOC				0x11
1022 
1023 #define PUNIT_REG_DSPFREQ			0x36
1024 #define   DSPFREQSTAT_SHIFT_CHV			24
1025 #define   DSPFREQSTAT_MASK_CHV			(0x1f << DSPFREQSTAT_SHIFT_CHV)
1026 #define   DSPFREQGUAR_SHIFT_CHV			8
1027 #define   DSPFREQGUAR_MASK_CHV			(0x1f << DSPFREQGUAR_SHIFT_CHV)
1028 #define   DSPFREQSTAT_SHIFT			30
1029 #define   DSPFREQSTAT_MASK			(0x3 << DSPFREQSTAT_SHIFT)
1030 #define   DSPFREQGUAR_SHIFT			14
1031 #define   DSPFREQGUAR_MASK			(0x3 << DSPFREQGUAR_SHIFT)
1032 #define   DSP_MAXFIFO_PM5_STATUS		(1 << 22) /* chv */
1033 #define   DSP_AUTO_CDCLK_GATE_DISABLE		(1 << 7) /* chv */
1034 #define   DSP_MAXFIFO_PM5_ENABLE		(1 << 6) /* chv */
1035 #define   _DP_SSC(val, pipe)			((val) << (2 * (pipe)))
1036 #define   DP_SSC_MASK(pipe)			_DP_SSC(0x3, (pipe))
1037 #define   DP_SSC_PWR_ON(pipe)			_DP_SSC(0x0, (pipe))
1038 #define   DP_SSC_CLK_GATE(pipe)			_DP_SSC(0x1, (pipe))
1039 #define   DP_SSC_RESET(pipe)			_DP_SSC(0x2, (pipe))
1040 #define   DP_SSC_PWR_GATE(pipe)			_DP_SSC(0x3, (pipe))
1041 #define   _DP_SSS(val, pipe)			((val) << (2 * (pipe) + 16))
1042 #define   DP_SSS_MASK(pipe)			_DP_SSS(0x3, (pipe))
1043 #define   DP_SSS_PWR_ON(pipe)			_DP_SSS(0x0, (pipe))
1044 #define   DP_SSS_CLK_GATE(pipe)			_DP_SSS(0x1, (pipe))
1045 #define   DP_SSS_RESET(pipe)			_DP_SSS(0x2, (pipe))
1046 #define   DP_SSS_PWR_GATE(pipe)			_DP_SSS(0x3, (pipe))
1047 
1048 /*
1049  * i915_power_well_id:
1050  *
1051  * IDs used to look up power wells. Power wells accessed directly bypassing
1052  * the power domains framework must be assigned a unique ID. The rest of power
1053  * wells must be assigned DISP_PW_ID_NONE.
1054  */
1055 enum i915_power_well_id {
1056 	DISP_PW_ID_NONE,
1057 
1058 	VLV_DISP_PW_DISP2D,
1059 	BXT_DISP_PW_DPIO_CMN_A,
1060 	VLV_DISP_PW_DPIO_CMN_BC,
1061 	GLK_DISP_PW_DPIO_CMN_C,
1062 	CHV_DISP_PW_DPIO_CMN_D,
1063 	HSW_DISP_PW_GLOBAL,
1064 	SKL_DISP_PW_MISC_IO,
1065 	SKL_DISP_PW_1,
1066 	SKL_DISP_PW_2,
1067 };
1068 
1069 #define PUNIT_REG_PWRGT_CTRL			0x60
1070 #define PUNIT_REG_PWRGT_STATUS			0x61
1071 #define   PUNIT_PWRGT_MASK(pw_idx)		(3 << ((pw_idx) * 2))
1072 #define   PUNIT_PWRGT_PWR_ON(pw_idx)		(0 << ((pw_idx) * 2))
1073 #define   PUNIT_PWRGT_CLK_GATE(pw_idx)		(1 << ((pw_idx) * 2))
1074 #define   PUNIT_PWRGT_RESET(pw_idx)		(2 << ((pw_idx) * 2))
1075 #define   PUNIT_PWRGT_PWR_GATE(pw_idx)		(3 << ((pw_idx) * 2))
1076 
1077 #define PUNIT_PWGT_IDX_RENDER			0
1078 #define PUNIT_PWGT_IDX_MEDIA			1
1079 #define PUNIT_PWGT_IDX_DISP2D			3
1080 #define PUNIT_PWGT_IDX_DPIO_CMN_BC		5
1081 #define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01	6
1082 #define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23	7
1083 #define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01	8
1084 #define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23	9
1085 #define PUNIT_PWGT_IDX_DPIO_RX0			10
1086 #define PUNIT_PWGT_IDX_DPIO_RX1			11
1087 #define PUNIT_PWGT_IDX_DPIO_CMN_D		12
1088 
1089 #define PUNIT_REG_GPU_LFM			0xd3
1090 #define PUNIT_REG_GPU_FREQ_REQ			0xd4
1091 #define PUNIT_REG_GPU_FREQ_STS			0xd8
1092 #define   GPLLENABLE				(1 << 4)
1093 #define   GENFREQSTATUS				(1 << 0)
1094 #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ		0xdc
1095 #define PUNIT_REG_CZ_TIMESTAMP			0xce
1096 
1097 #define PUNIT_FUSE_BUS2				0xf6 /* bits 47:40 */
1098 #define PUNIT_FUSE_BUS1				0xf5 /* bits 55:48 */
1099 
1100 #define FB_GFX_FMAX_AT_VMAX_FUSE		0x136
1101 #define FB_GFX_FREQ_FUSE_MASK			0xff
1102 #define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT	24
1103 #define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT	16
1104 #define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT	8
1105 
1106 #define FB_GFX_FMIN_AT_VMIN_FUSE		0x137
1107 #define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT		8
1108 
1109 #define PUNIT_REG_DDR_SETUP2			0x139
1110 #define   FORCE_DDR_FREQ_REQ_ACK		(1 << 8)
1111 #define   FORCE_DDR_LOW_FREQ			(1 << 1)
1112 #define   FORCE_DDR_HIGH_FREQ			(1 << 0)
1113 
1114 #define PUNIT_GPU_STATUS_REG			0xdb
1115 #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT	16
1116 #define PUNIT_GPU_STATUS_MAX_FREQ_MASK		0xff
1117 #define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT	8
1118 #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK	0xff
1119 
1120 #define PUNIT_GPU_DUTYCYCLE_REG		0xdf
1121 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT	8
1122 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK	0xff
1123 
1124 #define IOSF_NC_FB_GFX_FREQ_FUSE		0x1c
1125 #define   FB_GFX_MAX_FREQ_FUSE_SHIFT		3
1126 #define   FB_GFX_MAX_FREQ_FUSE_MASK		0x000007f8
1127 #define   FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT	11
1128 #define   FB_GFX_FGUARANTEED_FREQ_FUSE_MASK	0x0007f800
1129 #define IOSF_NC_FB_GFX_FMAX_FUSE_HI		0x34
1130 #define   FB_FMAX_VMIN_FREQ_HI_MASK		0x00000007
1131 #define IOSF_NC_FB_GFX_FMAX_FUSE_LO		0x30
1132 #define   FB_FMAX_VMIN_FREQ_LO_SHIFT		27
1133 #define   FB_FMAX_VMIN_FREQ_LO_MASK		0xf8000000
1134 
1135 #define VLV_TURBO_SOC_OVERRIDE		0x04
1136 #define   VLV_OVERRIDE_EN		1
1137 #define   VLV_SOC_TDP_EN		(1 << 1)
1138 #define   VLV_BIAS_CPU_125_SOC_875	(6 << 2)
1139 #define   CHV_BIAS_CPU_50_SOC_50	(3 << 2)
1140 
1141 /* vlv2 north clock has */
1142 #define CCK_FUSE_REG				0x8
1143 #define  CCK_FUSE_HPLL_FREQ_MASK		0x3
1144 #define CCK_REG_DSI_PLL_FUSE			0x44
1145 #define CCK_REG_DSI_PLL_CONTROL			0x48
1146 #define  DSI_PLL_VCO_EN				(1 << 31)
1147 #define  DSI_PLL_LDO_GATE			(1 << 30)
1148 #define  DSI_PLL_P1_POST_DIV_SHIFT		17
1149 #define  DSI_PLL_P1_POST_DIV_MASK		(0x1ff << 17)
1150 #define  DSI_PLL_P2_MUX_DSI0_DIV2		(1 << 13)
1151 #define  DSI_PLL_P3_MUX_DSI1_DIV2		(1 << 12)
1152 #define  DSI_PLL_MUX_MASK			(3 << 9)
1153 #define  DSI_PLL_MUX_DSI0_DSIPLL		(0 << 10)
1154 #define  DSI_PLL_MUX_DSI0_CCK			(1 << 10)
1155 #define  DSI_PLL_MUX_DSI1_DSIPLL		(0 << 9)
1156 #define  DSI_PLL_MUX_DSI1_CCK			(1 << 9)
1157 #define  DSI_PLL_CLK_GATE_MASK			(0xf << 5)
1158 #define  DSI_PLL_CLK_GATE_DSI0_DSIPLL		(1 << 8)
1159 #define  DSI_PLL_CLK_GATE_DSI1_DSIPLL		(1 << 7)
1160 #define  DSI_PLL_CLK_GATE_DSI0_CCK		(1 << 6)
1161 #define  DSI_PLL_CLK_GATE_DSI1_CCK		(1 << 5)
1162 #define  DSI_PLL_LOCK				(1 << 0)
1163 #define CCK_REG_DSI_PLL_DIVIDER			0x4c
1164 #define  DSI_PLL_LFSR				(1 << 31)
1165 #define  DSI_PLL_FRACTION_EN			(1 << 30)
1166 #define  DSI_PLL_FRAC_COUNTER_SHIFT		27
1167 #define  DSI_PLL_FRAC_COUNTER_MASK		(7 << 27)
1168 #define  DSI_PLL_USYNC_CNT_SHIFT		18
1169 #define  DSI_PLL_USYNC_CNT_MASK			(0x1ff << 18)
1170 #define  DSI_PLL_N1_DIV_SHIFT			16
1171 #define  DSI_PLL_N1_DIV_MASK			(3 << 16)
1172 #define  DSI_PLL_M1_DIV_SHIFT			0
1173 #define  DSI_PLL_M1_DIV_MASK			(0x1ff << 0)
1174 #define CCK_CZ_CLOCK_CONTROL			0x62
1175 #define CCK_GPLL_CLOCK_CONTROL			0x67
1176 #define CCK_DISPLAY_CLOCK_CONTROL		0x6b
1177 #define CCK_DISPLAY_REF_CLOCK_CONTROL		0x6c
1178 #define  CCK_TRUNK_FORCE_ON			(1 << 17)
1179 #define  CCK_TRUNK_FORCE_OFF			(1 << 16)
1180 #define  CCK_FREQUENCY_STATUS			(0x1f << 8)
1181 #define  CCK_FREQUENCY_STATUS_SHIFT		8
1182 #define  CCK_FREQUENCY_VALUES			(0x1f << 0)
1183 
1184 /* DPIO registers */
1185 #define DPIO_DEVFN			0
1186 
1187 #define DPIO_CTL			_MMIO(VLV_DISPLAY_BASE + 0x2110)
1188 #define  DPIO_MODSEL1			(1 << 3) /* if ref clk b == 27 */
1189 #define  DPIO_MODSEL0			(1 << 2) /* if ref clk a == 27 */
1190 #define  DPIO_SFR_BYPASS		(1 << 1)
1191 #define  DPIO_CMNRST			(1 << 0)
1192 
1193 #define DPIO_PHY(pipe)			((pipe) >> 1)
1194 #define DPIO_PHY_IOSF_PORT(phy)		(dev_priv->dpio_phy_iosf_port[phy])
1195 
1196 /*
1197  * Per pipe/PLL DPIO regs
1198  */
1199 #define _VLV_PLL_DW3_CH0		0x800c
1200 #define   DPIO_POST_DIV_SHIFT		(28) /* 3 bits */
1201 #define   DPIO_POST_DIV_DAC		0
1202 #define   DPIO_POST_DIV_HDMIDP		1 /* DAC 225-400M rate */
1203 #define   DPIO_POST_DIV_LVDS1		2
1204 #define   DPIO_POST_DIV_LVDS2		3
1205 #define   DPIO_K_SHIFT			(24) /* 4 bits */
1206 #define   DPIO_P1_SHIFT			(21) /* 3 bits */
1207 #define   DPIO_P2_SHIFT			(16) /* 5 bits */
1208 #define   DPIO_N_SHIFT			(12) /* 4 bits */
1209 #define   DPIO_ENABLE_CALIBRATION	(1 << 11)
1210 #define   DPIO_M1DIV_SHIFT		(8) /* 3 bits */
1211 #define   DPIO_M2DIV_MASK		0xff
1212 #define _VLV_PLL_DW3_CH1		0x802c
1213 #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
1214 
1215 #define _VLV_PLL_DW5_CH0		0x8014
1216 #define   DPIO_REFSEL_OVERRIDE		27
1217 #define   DPIO_PLL_MODESEL_SHIFT	24 /* 3 bits */
1218 #define   DPIO_BIAS_CURRENT_CTL_SHIFT	21 /* 3 bits, always 0x7 */
1219 #define   DPIO_PLL_REFCLK_SEL_SHIFT	16 /* 2 bits */
1220 #define   DPIO_PLL_REFCLK_SEL_MASK	3
1221 #define   DPIO_DRIVER_CTL_SHIFT		12 /* always set to 0x8 */
1222 #define   DPIO_CLK_BIAS_CTL_SHIFT	8 /* always set to 0x5 */
1223 #define _VLV_PLL_DW5_CH1		0x8034
1224 #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
1225 
1226 #define _VLV_PLL_DW7_CH0		0x801c
1227 #define _VLV_PLL_DW7_CH1		0x803c
1228 #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
1229 
1230 #define _VLV_PLL_DW8_CH0		0x8040
1231 #define _VLV_PLL_DW8_CH1		0x8060
1232 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
1233 
1234 #define VLV_PLL_DW9_BCAST		0xc044
1235 #define _VLV_PLL_DW9_CH0		0x8044
1236 #define _VLV_PLL_DW9_CH1		0x8064
1237 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
1238 
1239 #define _VLV_PLL_DW10_CH0		0x8048
1240 #define _VLV_PLL_DW10_CH1		0x8068
1241 #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
1242 
1243 #define _VLV_PLL_DW11_CH0		0x804c
1244 #define _VLV_PLL_DW11_CH1		0x806c
1245 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
1246 
1247 /* Spec for ref block start counts at DW10 */
1248 #define VLV_REF_DW13			0x80ac
1249 
1250 #define VLV_CMN_DW0			0x8100
1251 
1252 /*
1253  * Per DDI channel DPIO regs
1254  */
1255 
1256 #define _VLV_PCS_DW0_CH0		0x8200
1257 #define _VLV_PCS_DW0_CH1		0x8400
1258 #define   DPIO_PCS_TX_LANE2_RESET	(1 << 16)
1259 #define   DPIO_PCS_TX_LANE1_RESET	(1 << 7)
1260 #define   DPIO_LEFT_TXFIFO_RST_MASTER2	(1 << 4)
1261 #define   DPIO_RIGHT_TXFIFO_RST_MASTER2	(1 << 3)
1262 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
1263 
1264 #define _VLV_PCS01_DW0_CH0		0x200
1265 #define _VLV_PCS23_DW0_CH0		0x400
1266 #define _VLV_PCS01_DW0_CH1		0x2600
1267 #define _VLV_PCS23_DW0_CH1		0x2800
1268 #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
1269 #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
1270 
1271 #define _VLV_PCS_DW1_CH0		0x8204
1272 #define _VLV_PCS_DW1_CH1		0x8404
1273 #define   CHV_PCS_REQ_SOFTRESET_EN	(1 << 23)
1274 #define   DPIO_PCS_CLK_CRI_RXEB_EIOS_EN	(1 << 22)
1275 #define   DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21)
1276 #define   DPIO_PCS_CLK_DATAWIDTH_SHIFT	(6)
1277 #define   DPIO_PCS_CLK_SOFT_RESET	(1 << 5)
1278 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
1279 
1280 #define _VLV_PCS01_DW1_CH0		0x204
1281 #define _VLV_PCS23_DW1_CH0		0x404
1282 #define _VLV_PCS01_DW1_CH1		0x2604
1283 #define _VLV_PCS23_DW1_CH1		0x2804
1284 #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
1285 #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
1286 
1287 #define _VLV_PCS_DW8_CH0		0x8220
1288 #define _VLV_PCS_DW8_CH1		0x8420
1289 #define   CHV_PCS_USEDCLKCHANNEL_OVRRIDE	(1 << 20)
1290 #define   CHV_PCS_USEDCLKCHANNEL		(1 << 21)
1291 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
1292 
1293 #define _VLV_PCS01_DW8_CH0		0x0220
1294 #define _VLV_PCS23_DW8_CH0		0x0420
1295 #define _VLV_PCS01_DW8_CH1		0x2620
1296 #define _VLV_PCS23_DW8_CH1		0x2820
1297 #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
1298 #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
1299 
1300 #define _VLV_PCS_DW9_CH0		0x8224
1301 #define _VLV_PCS_DW9_CH1		0x8424
1302 #define   DPIO_PCS_TX2MARGIN_MASK	(0x7 << 13)
1303 #define   DPIO_PCS_TX2MARGIN_000	(0 << 13)
1304 #define   DPIO_PCS_TX2MARGIN_101	(1 << 13)
1305 #define   DPIO_PCS_TX1MARGIN_MASK	(0x7 << 10)
1306 #define   DPIO_PCS_TX1MARGIN_000	(0 << 10)
1307 #define   DPIO_PCS_TX1MARGIN_101	(1 << 10)
1308 #define	VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
1309 
1310 #define _VLV_PCS01_DW9_CH0		0x224
1311 #define _VLV_PCS23_DW9_CH0		0x424
1312 #define _VLV_PCS01_DW9_CH1		0x2624
1313 #define _VLV_PCS23_DW9_CH1		0x2824
1314 #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
1315 #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
1316 
1317 #define _CHV_PCS_DW10_CH0		0x8228
1318 #define _CHV_PCS_DW10_CH1		0x8428
1319 #define   DPIO_PCS_SWING_CALC_TX0_TX2	(1 << 30)
1320 #define   DPIO_PCS_SWING_CALC_TX1_TX3	(1 << 31)
1321 #define   DPIO_PCS_TX2DEEMP_MASK	(0xf << 24)
1322 #define   DPIO_PCS_TX2DEEMP_9P5		(0 << 24)
1323 #define   DPIO_PCS_TX2DEEMP_6P0		(2 << 24)
1324 #define   DPIO_PCS_TX1DEEMP_MASK	(0xf << 16)
1325 #define   DPIO_PCS_TX1DEEMP_9P5		(0 << 16)
1326 #define   DPIO_PCS_TX1DEEMP_6P0		(2 << 16)
1327 #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
1328 
1329 #define _VLV_PCS01_DW10_CH0		0x0228
1330 #define _VLV_PCS23_DW10_CH0		0x0428
1331 #define _VLV_PCS01_DW10_CH1		0x2628
1332 #define _VLV_PCS23_DW10_CH1		0x2828
1333 #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
1334 #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
1335 
1336 #define _VLV_PCS_DW11_CH0		0x822c
1337 #define _VLV_PCS_DW11_CH1		0x842c
1338 #define   DPIO_TX2_STAGGER_MASK(x)	((x) << 24)
1339 #define   DPIO_LANEDESKEW_STRAP_OVRD	(1 << 3)
1340 #define   DPIO_LEFT_TXFIFO_RST_MASTER	(1 << 1)
1341 #define   DPIO_RIGHT_TXFIFO_RST_MASTER	(1 << 0)
1342 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
1343 
1344 #define _VLV_PCS01_DW11_CH0		0x022c
1345 #define _VLV_PCS23_DW11_CH0		0x042c
1346 #define _VLV_PCS01_DW11_CH1		0x262c
1347 #define _VLV_PCS23_DW11_CH1		0x282c
1348 #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
1349 #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
1350 
1351 #define _VLV_PCS01_DW12_CH0		0x0230
1352 #define _VLV_PCS23_DW12_CH0		0x0430
1353 #define _VLV_PCS01_DW12_CH1		0x2630
1354 #define _VLV_PCS23_DW12_CH1		0x2830
1355 #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
1356 #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
1357 
1358 #define _VLV_PCS_DW12_CH0		0x8230
1359 #define _VLV_PCS_DW12_CH1		0x8430
1360 #define   DPIO_TX2_STAGGER_MULT(x)	((x) << 20)
1361 #define   DPIO_TX1_STAGGER_MULT(x)	((x) << 16)
1362 #define   DPIO_TX1_STAGGER_MASK(x)	((x) << 8)
1363 #define   DPIO_LANESTAGGER_STRAP_OVRD	(1 << 6)
1364 #define   DPIO_LANESTAGGER_STRAP(x)	((x) << 0)
1365 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
1366 
1367 #define _VLV_PCS_DW14_CH0		0x8238
1368 #define _VLV_PCS_DW14_CH1		0x8438
1369 #define	VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
1370 
1371 #define _VLV_PCS_DW23_CH0		0x825c
1372 #define _VLV_PCS_DW23_CH1		0x845c
1373 #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
1374 
1375 #define _VLV_TX_DW2_CH0			0x8288
1376 #define _VLV_TX_DW2_CH1			0x8488
1377 #define   DPIO_SWING_MARGIN000_SHIFT	16
1378 #define   DPIO_SWING_MARGIN000_MASK	(0xff << DPIO_SWING_MARGIN000_SHIFT)
1379 #define   DPIO_UNIQ_TRANS_SCALE_SHIFT	8
1380 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
1381 
1382 #define _VLV_TX_DW3_CH0			0x828c
1383 #define _VLV_TX_DW3_CH1			0x848c
1384 /* The following bit for CHV phy */
1385 #define   DPIO_TX_UNIQ_TRANS_SCALE_EN	(1 << 27)
1386 #define   DPIO_SWING_MARGIN101_SHIFT	16
1387 #define   DPIO_SWING_MARGIN101_MASK	(0xff << DPIO_SWING_MARGIN101_SHIFT)
1388 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
1389 
1390 #define _VLV_TX_DW4_CH0			0x8290
1391 #define _VLV_TX_DW4_CH1			0x8490
1392 #define   DPIO_SWING_DEEMPH9P5_SHIFT	24
1393 #define   DPIO_SWING_DEEMPH9P5_MASK	(0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
1394 #define   DPIO_SWING_DEEMPH6P0_SHIFT	16
1395 #define   DPIO_SWING_DEEMPH6P0_MASK	(0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
1396 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
1397 
1398 #define _VLV_TX3_DW4_CH0		0x690
1399 #define _VLV_TX3_DW4_CH1		0x2a90
1400 #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
1401 
1402 #define _VLV_TX_DW5_CH0			0x8294
1403 #define _VLV_TX_DW5_CH1			0x8494
1404 #define   DPIO_TX_OCALINIT_EN		(1 << 31)
1405 #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
1406 
1407 #define _VLV_TX_DW11_CH0		0x82ac
1408 #define _VLV_TX_DW11_CH1		0x84ac
1409 #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
1410 
1411 #define _VLV_TX_DW14_CH0		0x82b8
1412 #define _VLV_TX_DW14_CH1		0x84b8
1413 #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
1414 
1415 /* CHV dpPhy registers */
1416 #define _CHV_PLL_DW0_CH0		0x8000
1417 #define _CHV_PLL_DW0_CH1		0x8180
1418 #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
1419 
1420 #define _CHV_PLL_DW1_CH0		0x8004
1421 #define _CHV_PLL_DW1_CH1		0x8184
1422 #define   DPIO_CHV_N_DIV_SHIFT		8
1423 #define   DPIO_CHV_M1_DIV_BY_2		(0 << 0)
1424 #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
1425 
1426 #define _CHV_PLL_DW2_CH0		0x8008
1427 #define _CHV_PLL_DW2_CH1		0x8188
1428 #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
1429 
1430 #define _CHV_PLL_DW3_CH0		0x800c
1431 #define _CHV_PLL_DW3_CH1		0x818c
1432 #define  DPIO_CHV_FRAC_DIV_EN		(1 << 16)
1433 #define  DPIO_CHV_FIRST_MOD		(0 << 8)
1434 #define  DPIO_CHV_SECOND_MOD		(1 << 8)
1435 #define  DPIO_CHV_FEEDFWD_GAIN_SHIFT	0
1436 #define  DPIO_CHV_FEEDFWD_GAIN_MASK		(0xF << 0)
1437 #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
1438 
1439 #define _CHV_PLL_DW6_CH0		0x8018
1440 #define _CHV_PLL_DW6_CH1		0x8198
1441 #define   DPIO_CHV_GAIN_CTRL_SHIFT	16
1442 #define	  DPIO_CHV_INT_COEFF_SHIFT	8
1443 #define   DPIO_CHV_PROP_COEFF_SHIFT	0
1444 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
1445 
1446 #define _CHV_PLL_DW8_CH0		0x8020
1447 #define _CHV_PLL_DW8_CH1		0x81A0
1448 #define   DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
1449 #define   DPIO_CHV_TDC_TARGET_CNT_MASK  (0x3FF << 0)
1450 #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
1451 
1452 #define _CHV_PLL_DW9_CH0		0x8024
1453 #define _CHV_PLL_DW9_CH1		0x81A4
1454 #define  DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT		1 /* 3 bits */
1455 #define  DPIO_CHV_INT_LOCK_THRESHOLD_MASK		(7 << 1)
1456 #define  DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE	1 /* 1: coarse & 0 : fine  */
1457 #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
1458 
1459 #define _CHV_CMN_DW0_CH0               0x8100
1460 #define   DPIO_ALLDL_POWERDOWN_SHIFT_CH0	19
1461 #define   DPIO_ANYDL_POWERDOWN_SHIFT_CH0	18
1462 #define   DPIO_ALLDL_POWERDOWN			(1 << 1)
1463 #define   DPIO_ANYDL_POWERDOWN			(1 << 0)
1464 
1465 #define _CHV_CMN_DW5_CH0               0x8114
1466 #define   CHV_BUFRIGHTENA1_DISABLE	(0 << 20)
1467 #define   CHV_BUFRIGHTENA1_NORMAL	(1 << 20)
1468 #define   CHV_BUFRIGHTENA1_FORCE	(3 << 20)
1469 #define   CHV_BUFRIGHTENA1_MASK		(3 << 20)
1470 #define   CHV_BUFLEFTENA1_DISABLE	(0 << 22)
1471 #define   CHV_BUFLEFTENA1_NORMAL	(1 << 22)
1472 #define   CHV_BUFLEFTENA1_FORCE		(3 << 22)
1473 #define   CHV_BUFLEFTENA1_MASK		(3 << 22)
1474 
1475 #define _CHV_CMN_DW13_CH0		0x8134
1476 #define _CHV_CMN_DW0_CH1		0x8080
1477 #define   DPIO_CHV_S1_DIV_SHIFT		21
1478 #define   DPIO_CHV_P1_DIV_SHIFT		13 /* 3 bits */
1479 #define   DPIO_CHV_P2_DIV_SHIFT		8  /* 5 bits */
1480 #define   DPIO_CHV_K_DIV_SHIFT		4
1481 #define   DPIO_PLL_FREQLOCK		(1 << 1)
1482 #define   DPIO_PLL_LOCK			(1 << 0)
1483 #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
1484 
1485 #define _CHV_CMN_DW14_CH0		0x8138
1486 #define _CHV_CMN_DW1_CH1		0x8084
1487 #define   DPIO_AFC_RECAL		(1 << 14)
1488 #define   DPIO_DCLKP_EN			(1 << 13)
1489 #define   CHV_BUFLEFTENA2_DISABLE	(0 << 17) /* CL2 DW1 only */
1490 #define   CHV_BUFLEFTENA2_NORMAL	(1 << 17) /* CL2 DW1 only */
1491 #define   CHV_BUFLEFTENA2_FORCE		(3 << 17) /* CL2 DW1 only */
1492 #define   CHV_BUFLEFTENA2_MASK		(3 << 17) /* CL2 DW1 only */
1493 #define   CHV_BUFRIGHTENA2_DISABLE	(0 << 19) /* CL2 DW1 only */
1494 #define   CHV_BUFRIGHTENA2_NORMAL	(1 << 19) /* CL2 DW1 only */
1495 #define   CHV_BUFRIGHTENA2_FORCE	(3 << 19) /* CL2 DW1 only */
1496 #define   CHV_BUFRIGHTENA2_MASK		(3 << 19) /* CL2 DW1 only */
1497 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
1498 
1499 #define _CHV_CMN_DW19_CH0		0x814c
1500 #define _CHV_CMN_DW6_CH1		0x8098
1501 #define   DPIO_ALLDL_POWERDOWN_SHIFT_CH1	30 /* CL2 DW6 only */
1502 #define   DPIO_ANYDL_POWERDOWN_SHIFT_CH1	29 /* CL2 DW6 only */
1503 #define   DPIO_DYNPWRDOWNEN_CH1		(1 << 28) /* CL2 DW6 only */
1504 #define   CHV_CMN_USEDCLKCHANNEL	(1 << 13)
1505 
1506 #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
1507 
1508 #define CHV_CMN_DW28			0x8170
1509 #define   DPIO_CL1POWERDOWNEN		(1 << 23)
1510 #define   DPIO_DYNPWRDOWNEN_CH0		(1 << 22)
1511 #define   DPIO_SUS_CLK_CONFIG_ON		(0 << 0)
1512 #define   DPIO_SUS_CLK_CONFIG_CLKREQ		(1 << 0)
1513 #define   DPIO_SUS_CLK_CONFIG_GATE		(2 << 0)
1514 #define   DPIO_SUS_CLK_CONFIG_GATE_CLKREQ	(3 << 0)
1515 
1516 #define CHV_CMN_DW30			0x8178
1517 #define   DPIO_CL2_LDOFUSE_PWRENB	(1 << 6)
1518 #define   DPIO_LRC_BYPASS		(1 << 3)
1519 
1520 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
1521 					(lane) * 0x200 + (offset))
1522 
1523 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
1524 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
1525 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
1526 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
1527 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
1528 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
1529 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
1530 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
1531 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
1532 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
1533 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
1534 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
1535 #define   DPIO_FRC_LATENCY_SHFIT	8
1536 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
1537 #define   DPIO_UPAR_SHIFT		30
1538 
1539 /* BXT PHY registers */
1540 #define _BXT_PHY0_BASE			0x6C000
1541 #define _BXT_PHY1_BASE			0x162000
1542 #define _BXT_PHY2_BASE			0x163000
1543 #define BXT_PHY_BASE(phy)		_PHY3((phy), _BXT_PHY0_BASE, \
1544 						     _BXT_PHY1_BASE, \
1545 						     _BXT_PHY2_BASE)
1546 
1547 #define _BXT_PHY(phy, reg)						\
1548 	_MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))
1549 
1550 #define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1)		\
1551 	(BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE,	\
1552 					 (reg_ch1) - _BXT_PHY0_BASE))
1553 #define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1)		\
1554 	_MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1))
1555 
1556 #define BXT_P_CR_GT_DISP_PWRON		_MMIO(0x138090)
1557 #define  MIPIO_RST_CTRL				(1 << 2)
1558 
1559 #define _BXT_PHY_CTL_DDI_A		0x64C00
1560 #define _BXT_PHY_CTL_DDI_B		0x64C10
1561 #define _BXT_PHY_CTL_DDI_C		0x64C20
1562 #define   BXT_PHY_CMNLANE_POWERDOWN_ACK	(1 << 10)
1563 #define   BXT_PHY_LANE_POWERDOWN_ACK	(1 << 9)
1564 #define   BXT_PHY_LANE_ENABLED		(1 << 8)
1565 #define BXT_PHY_CTL(port)		_MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \
1566 							 _BXT_PHY_CTL_DDI_B)
1567 
1568 #define _PHY_CTL_FAMILY_EDP		0x64C80
1569 #define _PHY_CTL_FAMILY_DDI		0x64C90
1570 #define _PHY_CTL_FAMILY_DDI_C		0x64CA0
1571 #define   COMMON_RESET_DIS		(1 << 31)
1572 #define BXT_PHY_CTL_FAMILY(phy)		_MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \
1573 							  _PHY_CTL_FAMILY_EDP, \
1574 							  _PHY_CTL_FAMILY_DDI_C)
1575 
1576 /* BXT PHY PLL registers */
1577 #define _PORT_PLL_A			0x46074
1578 #define _PORT_PLL_B			0x46078
1579 #define _PORT_PLL_C			0x4607c
1580 #define   PORT_PLL_ENABLE		(1 << 31)
1581 #define   PORT_PLL_LOCK			(1 << 30)
1582 #define   PORT_PLL_REF_SEL		(1 << 27)
1583 #define   PORT_PLL_POWER_ENABLE		(1 << 26)
1584 #define   PORT_PLL_POWER_STATE		(1 << 25)
1585 #define BXT_PORT_PLL_ENABLE(port)	_MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
1586 
1587 #define _PORT_PLL_EBB_0_A		0x162034
1588 #define _PORT_PLL_EBB_0_B		0x6C034
1589 #define _PORT_PLL_EBB_0_C		0x6C340
1590 #define   PORT_PLL_P1_SHIFT		13
1591 #define   PORT_PLL_P1_MASK		(0x07 << PORT_PLL_P1_SHIFT)
1592 #define   PORT_PLL_P1(x)		((x)  << PORT_PLL_P1_SHIFT)
1593 #define   PORT_PLL_P2_SHIFT		8
1594 #define   PORT_PLL_P2_MASK		(0x1f << PORT_PLL_P2_SHIFT)
1595 #define   PORT_PLL_P2(x)		((x)  << PORT_PLL_P2_SHIFT)
1596 #define BXT_PORT_PLL_EBB_0(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
1597 							 _PORT_PLL_EBB_0_B, \
1598 							 _PORT_PLL_EBB_0_C)
1599 
1600 #define _PORT_PLL_EBB_4_A		0x162038
1601 #define _PORT_PLL_EBB_4_B		0x6C038
1602 #define _PORT_PLL_EBB_4_C		0x6C344
1603 #define   PORT_PLL_10BIT_CLK_ENABLE	(1 << 13)
1604 #define   PORT_PLL_RECALIBRATE		(1 << 14)
1605 #define BXT_PORT_PLL_EBB_4(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
1606 							 _PORT_PLL_EBB_4_B, \
1607 							 _PORT_PLL_EBB_4_C)
1608 
1609 #define _PORT_PLL_0_A			0x162100
1610 #define _PORT_PLL_0_B			0x6C100
1611 #define _PORT_PLL_0_C			0x6C380
1612 /* PORT_PLL_0_A */
1613 #define   PORT_PLL_M2_MASK		0xFF
1614 /* PORT_PLL_1_A */
1615 #define   PORT_PLL_N_SHIFT		8
1616 #define   PORT_PLL_N_MASK		(0x0F << PORT_PLL_N_SHIFT)
1617 #define   PORT_PLL_N(x)			((x) << PORT_PLL_N_SHIFT)
1618 /* PORT_PLL_2_A */
1619 #define   PORT_PLL_M2_FRAC_MASK		0x3FFFFF
1620 /* PORT_PLL_3_A */
1621 #define   PORT_PLL_M2_FRAC_ENABLE	(1 << 16)
1622 /* PORT_PLL_6_A */
1623 #define   PORT_PLL_PROP_COEFF_MASK	0xF
1624 #define   PORT_PLL_INT_COEFF_MASK	(0x1F << 8)
1625 #define   PORT_PLL_INT_COEFF(x)		((x)  << 8)
1626 #define   PORT_PLL_GAIN_CTL_MASK	(0x07 << 16)
1627 #define   PORT_PLL_GAIN_CTL(x)		((x)  << 16)
1628 /* PORT_PLL_8_A */
1629 #define   PORT_PLL_TARGET_CNT_MASK	0x3FF
1630 /* PORT_PLL_9_A */
1631 #define  PORT_PLL_LOCK_THRESHOLD_SHIFT	1
1632 #define  PORT_PLL_LOCK_THRESHOLD_MASK	(0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT)
1633 /* PORT_PLL_10_A */
1634 #define  PORT_PLL_DCO_AMP_OVR_EN_H	(1 << 27)
1635 #define  PORT_PLL_DCO_AMP_DEFAULT	15
1636 #define  PORT_PLL_DCO_AMP_MASK		0x3c00
1637 #define  PORT_PLL_DCO_AMP(x)		((x) << 10)
1638 #define _PORT_PLL_BASE(phy, ch)		_BXT_PHY_CH(phy, ch, \
1639 						    _PORT_PLL_0_B, \
1640 						    _PORT_PLL_0_C)
1641 #define BXT_PORT_PLL(phy, ch, idx)	_MMIO(_PORT_PLL_BASE(phy, ch) + \
1642 					      (idx) * 4)
1643 
1644 /* BXT PHY common lane registers */
1645 #define _PORT_CL1CM_DW0_A		0x162000
1646 #define _PORT_CL1CM_DW0_BC		0x6C000
1647 #define   PHY_POWER_GOOD		(1 << 16)
1648 #define   PHY_RESERVED			(1 << 7)
1649 #define BXT_PORT_CL1CM_DW0(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
1650 
1651 #define _PORT_CL1CM_DW9_A		0x162024
1652 #define _PORT_CL1CM_DW9_BC		0x6C024
1653 #define   IREF0RC_OFFSET_SHIFT		8
1654 #define   IREF0RC_OFFSET_MASK		(0xFF << IREF0RC_OFFSET_SHIFT)
1655 #define BXT_PORT_CL1CM_DW9(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW9_BC)
1656 
1657 #define _PORT_CL1CM_DW10_A		0x162028
1658 #define _PORT_CL1CM_DW10_BC		0x6C028
1659 #define   IREF1RC_OFFSET_SHIFT		8
1660 #define   IREF1RC_OFFSET_MASK		(0xFF << IREF1RC_OFFSET_SHIFT)
1661 #define BXT_PORT_CL1CM_DW10(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
1662 
1663 #define _PORT_CL1CM_DW28_A		0x162070
1664 #define _PORT_CL1CM_DW28_BC		0x6C070
1665 #define   OCL1_POWER_DOWN_EN		(1 << 23)
1666 #define   DW28_OLDO_DYN_PWR_DOWN_EN	(1 << 22)
1667 #define   SUS_CLK_CONFIG		0x3
1668 #define BXT_PORT_CL1CM_DW28(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW28_BC)
1669 
1670 #define _PORT_CL1CM_DW30_A		0x162078
1671 #define _PORT_CL1CM_DW30_BC		0x6C078
1672 #define   OCL2_LDOFUSE_PWR_DIS		(1 << 6)
1673 #define BXT_PORT_CL1CM_DW30(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
1674 
1675 /*
1676  * CNL/ICL Port/COMBO-PHY Registers
1677  */
1678 #define _ICL_COMBOPHY_A			0x162000
1679 #define _ICL_COMBOPHY_B			0x6C000
1680 #define _ICL_COMBOPHY(port)		_PICK(port, _ICL_COMBOPHY_A, \
1681 					      _ICL_COMBOPHY_B)
1682 
1683 /* CNL/ICL Port CL_DW registers */
1684 #define _ICL_PORT_CL_DW(dw, port)	(_ICL_COMBOPHY(port) + \
1685 					 4 * (dw))
1686 
1687 #define CNL_PORT_CL1CM_DW5		_MMIO(0x162014)
1688 #define ICL_PORT_CL_DW5(port)		_MMIO(_ICL_PORT_CL_DW(5, port))
1689 #define   CL_POWER_DOWN_ENABLE		(1 << 4)
1690 #define   SUS_CLOCK_CONFIG		(3 << 0)
1691 
1692 #define ICL_PORT_CL_DW10(port)		_MMIO(_ICL_PORT_CL_DW(10, port))
1693 #define  PG_SEQ_DELAY_OVERRIDE_MASK	(3 << 25)
1694 #define  PG_SEQ_DELAY_OVERRIDE_SHIFT	25
1695 #define  PG_SEQ_DELAY_OVERRIDE_ENABLE	(1 << 24)
1696 #define  PWR_UP_ALL_LANES		(0x0 << 4)
1697 #define  PWR_DOWN_LN_3_2_1		(0xe << 4)
1698 #define  PWR_DOWN_LN_3_2		(0xc << 4)
1699 #define  PWR_DOWN_LN_3			(0x8 << 4)
1700 #define  PWR_DOWN_LN_2_1_0		(0x7 << 4)
1701 #define  PWR_DOWN_LN_1_0		(0x3 << 4)
1702 #define  PWR_DOWN_LN_1			(0x2 << 4)
1703 #define  PWR_DOWN_LN_3_1		(0xa << 4)
1704 #define  PWR_DOWN_LN_3_1_0		(0xb << 4)
1705 #define  PWR_DOWN_LN_MASK		(0xf << 4)
1706 #define  PWR_DOWN_LN_SHIFT		4
1707 
1708 #define ICL_PORT_CL_DW12(port)		_MMIO(_ICL_PORT_CL_DW(12, port))
1709 #define   ICL_LANE_ENABLE_AUX		(1 << 0)
1710 
1711 /* CNL/ICL Port COMP_DW registers */
1712 #define _ICL_PORT_COMP			0x100
1713 #define _ICL_PORT_COMP_DW(dw, port)	(_ICL_COMBOPHY(port) + \
1714 					 _ICL_PORT_COMP + 4 * (dw))
1715 
1716 #define CNL_PORT_COMP_DW0		_MMIO(0x162100)
1717 #define ICL_PORT_COMP_DW0(port)		_MMIO(_ICL_PORT_COMP_DW(0, port))
1718 #define   COMP_INIT			(1 << 31)
1719 
1720 #define CNL_PORT_COMP_DW1		_MMIO(0x162104)
1721 #define ICL_PORT_COMP_DW1(port)		_MMIO(_ICL_PORT_COMP_DW(1, port))
1722 
1723 #define CNL_PORT_COMP_DW3		_MMIO(0x16210c)
1724 #define ICL_PORT_COMP_DW3(port)		_MMIO(_ICL_PORT_COMP_DW(3, port))
1725 #define   PROCESS_INFO_DOT_0		(0 << 26)
1726 #define   PROCESS_INFO_DOT_1		(1 << 26)
1727 #define   PROCESS_INFO_DOT_4		(2 << 26)
1728 #define   PROCESS_INFO_MASK		(7 << 26)
1729 #define   PROCESS_INFO_SHIFT		26
1730 #define   VOLTAGE_INFO_0_85V		(0 << 24)
1731 #define   VOLTAGE_INFO_0_95V		(1 << 24)
1732 #define   VOLTAGE_INFO_1_05V		(2 << 24)
1733 #define   VOLTAGE_INFO_MASK		(3 << 24)
1734 #define   VOLTAGE_INFO_SHIFT		24
1735 
1736 #define CNL_PORT_COMP_DW9		_MMIO(0x162124)
1737 #define ICL_PORT_COMP_DW9(port)		_MMIO(_ICL_PORT_COMP_DW(9, port))
1738 
1739 #define CNL_PORT_COMP_DW10		_MMIO(0x162128)
1740 #define ICL_PORT_COMP_DW10(port)	_MMIO(_ICL_PORT_COMP_DW(10, port))
1741 
1742 /* CNL/ICL Port PCS registers */
1743 #define _CNL_PORT_PCS_DW1_GRP_AE	0x162304
1744 #define _CNL_PORT_PCS_DW1_GRP_B		0x162384
1745 #define _CNL_PORT_PCS_DW1_GRP_C		0x162B04
1746 #define _CNL_PORT_PCS_DW1_GRP_D		0x162B84
1747 #define _CNL_PORT_PCS_DW1_GRP_F		0x162A04
1748 #define _CNL_PORT_PCS_DW1_LN0_AE	0x162404
1749 #define _CNL_PORT_PCS_DW1_LN0_B		0x162604
1750 #define _CNL_PORT_PCS_DW1_LN0_C		0x162C04
1751 #define _CNL_PORT_PCS_DW1_LN0_D		0x162E04
1752 #define _CNL_PORT_PCS_DW1_LN0_F		0x162804
1753 #define CNL_PORT_PCS_DW1_GRP(port)	_MMIO(_PICK(port, \
1754 						    _CNL_PORT_PCS_DW1_GRP_AE, \
1755 						    _CNL_PORT_PCS_DW1_GRP_B, \
1756 						    _CNL_PORT_PCS_DW1_GRP_C, \
1757 						    _CNL_PORT_PCS_DW1_GRP_D, \
1758 						    _CNL_PORT_PCS_DW1_GRP_AE, \
1759 						    _CNL_PORT_PCS_DW1_GRP_F))
1760 #define CNL_PORT_PCS_DW1_LN0(port)	_MMIO(_PICK(port, \
1761 						    _CNL_PORT_PCS_DW1_LN0_AE, \
1762 						    _CNL_PORT_PCS_DW1_LN0_B, \
1763 						    _CNL_PORT_PCS_DW1_LN0_C, \
1764 						    _CNL_PORT_PCS_DW1_LN0_D, \
1765 						    _CNL_PORT_PCS_DW1_LN0_AE, \
1766 						    _CNL_PORT_PCS_DW1_LN0_F))
1767 
1768 #define _ICL_PORT_PCS_AUX		0x300
1769 #define _ICL_PORT_PCS_GRP		0x600
1770 #define _ICL_PORT_PCS_LN(ln)		(0x800 + (ln) * 0x100)
1771 #define _ICL_PORT_PCS_DW_AUX(dw, port)	(_ICL_COMBOPHY(port) + \
1772 					 _ICL_PORT_PCS_AUX + 4 * (dw))
1773 #define _ICL_PORT_PCS_DW_GRP(dw, port)	(_ICL_COMBOPHY(port) + \
1774 					 _ICL_PORT_PCS_GRP + 4 * (dw))
1775 #define _ICL_PORT_PCS_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \
1776 					  _ICL_PORT_PCS_LN(ln) + 4 * (dw))
1777 #define ICL_PORT_PCS_DW1_AUX(port)	_MMIO(_ICL_PORT_PCS_DW_AUX(1, port))
1778 #define ICL_PORT_PCS_DW1_GRP(port)	_MMIO(_ICL_PORT_PCS_DW_GRP(1, port))
1779 #define ICL_PORT_PCS_DW1_LN0(port)	_MMIO(_ICL_PORT_PCS_DW_LN(1, 0, port))
1780 #define   COMMON_KEEPER_EN		(1 << 26)
1781 
1782 /* CNL/ICL Port TX registers */
1783 #define _CNL_PORT_TX_AE_GRP_OFFSET		0x162340
1784 #define _CNL_PORT_TX_B_GRP_OFFSET		0x1623C0
1785 #define _CNL_PORT_TX_C_GRP_OFFSET		0x162B40
1786 #define _CNL_PORT_TX_D_GRP_OFFSET		0x162BC0
1787 #define _CNL_PORT_TX_F_GRP_OFFSET		0x162A40
1788 #define _CNL_PORT_TX_AE_LN0_OFFSET		0x162440
1789 #define _CNL_PORT_TX_B_LN0_OFFSET		0x162640
1790 #define _CNL_PORT_TX_C_LN0_OFFSET		0x162C40
1791 #define _CNL_PORT_TX_D_LN0_OFFSET		0x162E40
1792 #define _CNL_PORT_TX_F_LN0_OFFSET		0x162840
1793 #define _CNL_PORT_TX_DW_GRP(dw, port)	(_PICK((port), \
1794 					       _CNL_PORT_TX_AE_GRP_OFFSET, \
1795 					       _CNL_PORT_TX_B_GRP_OFFSET, \
1796 					       _CNL_PORT_TX_B_GRP_OFFSET, \
1797 					       _CNL_PORT_TX_D_GRP_OFFSET, \
1798 					       _CNL_PORT_TX_AE_GRP_OFFSET, \
1799 					       _CNL_PORT_TX_F_GRP_OFFSET) + \
1800 					       4 * (dw))
1801 #define _CNL_PORT_TX_DW_LN0(dw, port)	(_PICK((port), \
1802 					       _CNL_PORT_TX_AE_LN0_OFFSET, \
1803 					       _CNL_PORT_TX_B_LN0_OFFSET, \
1804 					       _CNL_PORT_TX_B_LN0_OFFSET, \
1805 					       _CNL_PORT_TX_D_LN0_OFFSET, \
1806 					       _CNL_PORT_TX_AE_LN0_OFFSET, \
1807 					       _CNL_PORT_TX_F_LN0_OFFSET) + \
1808 					       4 * (dw))
1809 
1810 #define _ICL_PORT_TX_AUX		0x380
1811 #define _ICL_PORT_TX_GRP		0x680
1812 #define _ICL_PORT_TX_LN(ln)		(0x880 + (ln) * 0x100)
1813 
1814 #define _ICL_PORT_TX_DW_AUX(dw, port)	(_ICL_COMBOPHY(port) + \
1815 					 _ICL_PORT_TX_AUX + 4 * (dw))
1816 #define _ICL_PORT_TX_DW_GRP(dw, port)	(_ICL_COMBOPHY(port) + \
1817 					 _ICL_PORT_TX_GRP + 4 * (dw))
1818 #define _ICL_PORT_TX_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \
1819 					  _ICL_PORT_TX_LN(ln) + 4 * (dw))
1820 
1821 #define CNL_PORT_TX_DW2_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP(2, port))
1822 #define CNL_PORT_TX_DW2_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0(2, port))
1823 #define ICL_PORT_TX_DW2_AUX(port)	_MMIO(_ICL_PORT_TX_DW_AUX(2, port))
1824 #define ICL_PORT_TX_DW2_GRP(port)	_MMIO(_ICL_PORT_TX_DW_GRP(2, port))
1825 #define ICL_PORT_TX_DW2_LN0(port)	_MMIO(_ICL_PORT_TX_DW_LN(2, 0, port))
1826 #define   SWING_SEL_UPPER(x)		(((x) >> 3) << 15)
1827 #define   SWING_SEL_UPPER_MASK		(1 << 15)
1828 #define   SWING_SEL_LOWER(x)		(((x) & 0x7) << 11)
1829 #define   SWING_SEL_LOWER_MASK		(0x7 << 11)
1830 #define   FRC_LATENCY_OPTIM_MASK	(0x7 << 8)
1831 #define   FRC_LATENCY_OPTIM_VAL(x)	((x) << 8)
1832 #define   RCOMP_SCALAR(x)		((x) << 0)
1833 #define   RCOMP_SCALAR_MASK		(0xFF << 0)
1834 
1835 #define _CNL_PORT_TX_DW4_LN0_AE		0x162450
1836 #define _CNL_PORT_TX_DW4_LN1_AE		0x1624D0
1837 #define CNL_PORT_TX_DW4_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP(4, (port)))
1838 #define CNL_PORT_TX_DW4_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0(4, (port)))
1839 #define CNL_PORT_TX_DW4_LN(port, ln)   _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)) + \
1840 					   ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \
1841 						    _CNL_PORT_TX_DW4_LN0_AE)))
1842 #define ICL_PORT_TX_DW4_AUX(port)	_MMIO(_ICL_PORT_TX_DW_AUX(4, port))
1843 #define ICL_PORT_TX_DW4_GRP(port)	_MMIO(_ICL_PORT_TX_DW_GRP(4, port))
1844 #define ICL_PORT_TX_DW4_LN0(port)	_MMIO(_ICL_PORT_TX_DW_LN(4, 0, port))
1845 #define ICL_PORT_TX_DW4_LN(port, ln)	_MMIO(_ICL_PORT_TX_DW_LN(4, ln, port))
1846 #define   LOADGEN_SELECT		(1 << 31)
1847 #define   POST_CURSOR_1(x)		((x) << 12)
1848 #define   POST_CURSOR_1_MASK		(0x3F << 12)
1849 #define   POST_CURSOR_2(x)		((x) << 6)
1850 #define   POST_CURSOR_2_MASK		(0x3F << 6)
1851 #define   CURSOR_COEFF(x)		((x) << 0)
1852 #define   CURSOR_COEFF_MASK		(0x3F << 0)
1853 
1854 #define CNL_PORT_TX_DW5_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP(5, port))
1855 #define CNL_PORT_TX_DW5_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0(5, port))
1856 #define ICL_PORT_TX_DW5_AUX(port)	_MMIO(_ICL_PORT_TX_DW_AUX(5, port))
1857 #define ICL_PORT_TX_DW5_GRP(port)	_MMIO(_ICL_PORT_TX_DW_GRP(5, port))
1858 #define ICL_PORT_TX_DW5_LN0(port)	_MMIO(_ICL_PORT_TX_DW_LN(5, 0, port))
1859 #define   TX_TRAINING_EN		(1 << 31)
1860 #define   TAP2_DISABLE			(1 << 30)
1861 #define   TAP3_DISABLE			(1 << 29)
1862 #define   SCALING_MODE_SEL(x)		((x) << 18)
1863 #define   SCALING_MODE_SEL_MASK		(0x7 << 18)
1864 #define   RTERM_SELECT(x)		((x) << 3)
1865 #define   RTERM_SELECT_MASK		(0x7 << 3)
1866 
1867 #define CNL_PORT_TX_DW7_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP(7, (port)))
1868 #define CNL_PORT_TX_DW7_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0(7, (port)))
1869 #define ICL_PORT_TX_DW7_AUX(port)	_MMIO(_ICL_PORT_TX_DW_AUX(7, port))
1870 #define ICL_PORT_TX_DW7_GRP(port)	_MMIO(_ICL_PORT_TX_DW_GRP(7, port))
1871 #define ICL_PORT_TX_DW7_LN0(port)	_MMIO(_ICL_PORT_TX_DW_LN(7, 0, port))
1872 #define ICL_PORT_TX_DW7_LN(port, ln)	_MMIO(_ICL_PORT_TX_DW_LN(7, ln, port))
1873 #define   N_SCALAR(x)			((x) << 24)
1874 #define   N_SCALAR_MASK			(0x7F << 24)
1875 
1876 #define MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \
1877 	_MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
1878 
1879 #define MG_TX_LINK_PARAMS_TX1LN0_PORT1		0x16812C
1880 #define MG_TX_LINK_PARAMS_TX1LN1_PORT1		0x16852C
1881 #define MG_TX_LINK_PARAMS_TX1LN0_PORT2		0x16912C
1882 #define MG_TX_LINK_PARAMS_TX1LN1_PORT2		0x16952C
1883 #define MG_TX_LINK_PARAMS_TX1LN0_PORT3		0x16A12C
1884 #define MG_TX_LINK_PARAMS_TX1LN1_PORT3		0x16A52C
1885 #define MG_TX_LINK_PARAMS_TX1LN0_PORT4		0x16B12C
1886 #define MG_TX_LINK_PARAMS_TX1LN1_PORT4		0x16B52C
1887 #define MG_TX1_LINK_PARAMS(port, ln) \
1888 	MG_PHY_PORT_LN(port, ln, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
1889 				 MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
1890 				 MG_TX_LINK_PARAMS_TX1LN1_PORT1)
1891 
1892 #define MG_TX_LINK_PARAMS_TX2LN0_PORT1		0x1680AC
1893 #define MG_TX_LINK_PARAMS_TX2LN1_PORT1		0x1684AC
1894 #define MG_TX_LINK_PARAMS_TX2LN0_PORT2		0x1690AC
1895 #define MG_TX_LINK_PARAMS_TX2LN1_PORT2		0x1694AC
1896 #define MG_TX_LINK_PARAMS_TX2LN0_PORT3		0x16A0AC
1897 #define MG_TX_LINK_PARAMS_TX2LN1_PORT3		0x16A4AC
1898 #define MG_TX_LINK_PARAMS_TX2LN0_PORT4		0x16B0AC
1899 #define MG_TX_LINK_PARAMS_TX2LN1_PORT4		0x16B4AC
1900 #define MG_TX2_LINK_PARAMS(port, ln) \
1901 	MG_PHY_PORT_LN(port, ln, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
1902 				 MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
1903 				 MG_TX_LINK_PARAMS_TX2LN1_PORT1)
1904 #define   CRI_USE_FS32			(1 << 5)
1905 
1906 #define MG_TX_PISO_READLOAD_TX1LN0_PORT1		0x16814C
1907 #define MG_TX_PISO_READLOAD_TX1LN1_PORT1		0x16854C
1908 #define MG_TX_PISO_READLOAD_TX1LN0_PORT2		0x16914C
1909 #define MG_TX_PISO_READLOAD_TX1LN1_PORT2		0x16954C
1910 #define MG_TX_PISO_READLOAD_TX1LN0_PORT3		0x16A14C
1911 #define MG_TX_PISO_READLOAD_TX1LN1_PORT3		0x16A54C
1912 #define MG_TX_PISO_READLOAD_TX1LN0_PORT4		0x16B14C
1913 #define MG_TX_PISO_READLOAD_TX1LN1_PORT4		0x16B54C
1914 #define MG_TX1_PISO_READLOAD(port, ln) \
1915 	MG_PHY_PORT_LN(port, ln, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
1916 				 MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
1917 				 MG_TX_PISO_READLOAD_TX1LN1_PORT1)
1918 
1919 #define MG_TX_PISO_READLOAD_TX2LN0_PORT1		0x1680CC
1920 #define MG_TX_PISO_READLOAD_TX2LN1_PORT1		0x1684CC
1921 #define MG_TX_PISO_READLOAD_TX2LN0_PORT2		0x1690CC
1922 #define MG_TX_PISO_READLOAD_TX2LN1_PORT2		0x1694CC
1923 #define MG_TX_PISO_READLOAD_TX2LN0_PORT3		0x16A0CC
1924 #define MG_TX_PISO_READLOAD_TX2LN1_PORT3		0x16A4CC
1925 #define MG_TX_PISO_READLOAD_TX2LN0_PORT4		0x16B0CC
1926 #define MG_TX_PISO_READLOAD_TX2LN1_PORT4		0x16B4CC
1927 #define MG_TX2_PISO_READLOAD(port, ln) \
1928 	MG_PHY_PORT_LN(port, ln, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
1929 				 MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
1930 				 MG_TX_PISO_READLOAD_TX2LN1_PORT1)
1931 #define   CRI_CALCINIT					(1 << 1)
1932 
1933 #define MG_TX_SWINGCTRL_TX1LN0_PORT1		0x168148
1934 #define MG_TX_SWINGCTRL_TX1LN1_PORT1		0x168548
1935 #define MG_TX_SWINGCTRL_TX1LN0_PORT2		0x169148
1936 #define MG_TX_SWINGCTRL_TX1LN1_PORT2		0x169548
1937 #define MG_TX_SWINGCTRL_TX1LN0_PORT3		0x16A148
1938 #define MG_TX_SWINGCTRL_TX1LN1_PORT3		0x16A548
1939 #define MG_TX_SWINGCTRL_TX1LN0_PORT4		0x16B148
1940 #define MG_TX_SWINGCTRL_TX1LN1_PORT4		0x16B548
1941 #define MG_TX1_SWINGCTRL(port, ln) \
1942 	MG_PHY_PORT_LN(port, ln, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
1943 				 MG_TX_SWINGCTRL_TX1LN0_PORT2, \
1944 				 MG_TX_SWINGCTRL_TX1LN1_PORT1)
1945 
1946 #define MG_TX_SWINGCTRL_TX2LN0_PORT1		0x1680C8
1947 #define MG_TX_SWINGCTRL_TX2LN1_PORT1		0x1684C8
1948 #define MG_TX_SWINGCTRL_TX2LN0_PORT2		0x1690C8
1949 #define MG_TX_SWINGCTRL_TX2LN1_PORT2		0x1694C8
1950 #define MG_TX_SWINGCTRL_TX2LN0_PORT3		0x16A0C8
1951 #define MG_TX_SWINGCTRL_TX2LN1_PORT3		0x16A4C8
1952 #define MG_TX_SWINGCTRL_TX2LN0_PORT4		0x16B0C8
1953 #define MG_TX_SWINGCTRL_TX2LN1_PORT4		0x16B4C8
1954 #define MG_TX2_SWINGCTRL(port, ln) \
1955 	MG_PHY_PORT_LN(port, ln, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
1956 				 MG_TX_SWINGCTRL_TX2LN0_PORT2, \
1957 				 MG_TX_SWINGCTRL_TX2LN1_PORT1)
1958 #define   CRI_TXDEEMPH_OVERRIDE_17_12(x)		((x) << 0)
1959 #define   CRI_TXDEEMPH_OVERRIDE_17_12_MASK		(0x3F << 0)
1960 
1961 #define MG_TX_DRVCTRL_TX1LN0_TXPORT1			0x168144
1962 #define MG_TX_DRVCTRL_TX1LN1_TXPORT1			0x168544
1963 #define MG_TX_DRVCTRL_TX1LN0_TXPORT2			0x169144
1964 #define MG_TX_DRVCTRL_TX1LN1_TXPORT2			0x169544
1965 #define MG_TX_DRVCTRL_TX1LN0_TXPORT3			0x16A144
1966 #define MG_TX_DRVCTRL_TX1LN1_TXPORT3			0x16A544
1967 #define MG_TX_DRVCTRL_TX1LN0_TXPORT4			0x16B144
1968 #define MG_TX_DRVCTRL_TX1LN1_TXPORT4			0x16B544
1969 #define MG_TX1_DRVCTRL(port, ln) \
1970 	MG_PHY_PORT_LN(port, ln, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
1971 				 MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
1972 				 MG_TX_DRVCTRL_TX1LN1_TXPORT1)
1973 
1974 #define MG_TX_DRVCTRL_TX2LN0_PORT1			0x1680C4
1975 #define MG_TX_DRVCTRL_TX2LN1_PORT1			0x1684C4
1976 #define MG_TX_DRVCTRL_TX2LN0_PORT2			0x1690C4
1977 #define MG_TX_DRVCTRL_TX2LN1_PORT2			0x1694C4
1978 #define MG_TX_DRVCTRL_TX2LN0_PORT3			0x16A0C4
1979 #define MG_TX_DRVCTRL_TX2LN1_PORT3			0x16A4C4
1980 #define MG_TX_DRVCTRL_TX2LN0_PORT4			0x16B0C4
1981 #define MG_TX_DRVCTRL_TX2LN1_PORT4			0x16B4C4
1982 #define MG_TX2_DRVCTRL(port, ln) \
1983 	MG_PHY_PORT_LN(port, ln, MG_TX_DRVCTRL_TX2LN0_PORT1, \
1984 				 MG_TX_DRVCTRL_TX2LN0_PORT2, \
1985 				 MG_TX_DRVCTRL_TX2LN1_PORT1)
1986 #define   CRI_TXDEEMPH_OVERRIDE_11_6(x)			((x) << 24)
1987 #define   CRI_TXDEEMPH_OVERRIDE_11_6_MASK		(0x3F << 24)
1988 #define   CRI_TXDEEMPH_OVERRIDE_EN			(1 << 22)
1989 #define   CRI_TXDEEMPH_OVERRIDE_5_0(x)			((x) << 16)
1990 #define   CRI_TXDEEMPH_OVERRIDE_5_0_MASK		(0x3F << 16)
1991 #define   CRI_LOADGEN_SEL(x)				((x) << 12)
1992 #define   CRI_LOADGEN_SEL_MASK				(0x3 << 12)
1993 
1994 #define MG_CLKHUB_LN0_PORT1			0x16839C
1995 #define MG_CLKHUB_LN1_PORT1			0x16879C
1996 #define MG_CLKHUB_LN0_PORT2			0x16939C
1997 #define MG_CLKHUB_LN1_PORT2			0x16979C
1998 #define MG_CLKHUB_LN0_PORT3			0x16A39C
1999 #define MG_CLKHUB_LN1_PORT3			0x16A79C
2000 #define MG_CLKHUB_LN0_PORT4			0x16B39C
2001 #define MG_CLKHUB_LN1_PORT4			0x16B79C
2002 #define MG_CLKHUB(port, ln) \
2003 	MG_PHY_PORT_LN(port, ln, MG_CLKHUB_LN0_PORT1, \
2004 				 MG_CLKHUB_LN0_PORT2, \
2005 				 MG_CLKHUB_LN1_PORT1)
2006 #define   CFG_LOW_RATE_LKREN_EN				(1 << 11)
2007 
2008 #define MG_TX_DCC_TX1LN0_PORT1			0x168110
2009 #define MG_TX_DCC_TX1LN1_PORT1			0x168510
2010 #define MG_TX_DCC_TX1LN0_PORT2			0x169110
2011 #define MG_TX_DCC_TX1LN1_PORT2			0x169510
2012 #define MG_TX_DCC_TX1LN0_PORT3			0x16A110
2013 #define MG_TX_DCC_TX1LN1_PORT3			0x16A510
2014 #define MG_TX_DCC_TX1LN0_PORT4			0x16B110
2015 #define MG_TX_DCC_TX1LN1_PORT4			0x16B510
2016 #define MG_TX1_DCC(port, ln) \
2017 	MG_PHY_PORT_LN(port, ln, MG_TX_DCC_TX1LN0_PORT1, \
2018 				 MG_TX_DCC_TX1LN0_PORT2, \
2019 				 MG_TX_DCC_TX1LN1_PORT1)
2020 #define MG_TX_DCC_TX2LN0_PORT1			0x168090
2021 #define MG_TX_DCC_TX2LN1_PORT1			0x168490
2022 #define MG_TX_DCC_TX2LN0_PORT2			0x169090
2023 #define MG_TX_DCC_TX2LN1_PORT2			0x169490
2024 #define MG_TX_DCC_TX2LN0_PORT3			0x16A090
2025 #define MG_TX_DCC_TX2LN1_PORT3			0x16A490
2026 #define MG_TX_DCC_TX2LN0_PORT4			0x16B090
2027 #define MG_TX_DCC_TX2LN1_PORT4			0x16B490
2028 #define MG_TX2_DCC(port, ln) \
2029 	MG_PHY_PORT_LN(port, ln, MG_TX_DCC_TX2LN0_PORT1, \
2030 				 MG_TX_DCC_TX2LN0_PORT2, \
2031 				 MG_TX_DCC_TX2LN1_PORT1)
2032 #define   CFG_AMI_CK_DIV_OVERRIDE_VAL(x)	((x) << 25)
2033 #define   CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK	(0x3 << 25)
2034 #define   CFG_AMI_CK_DIV_OVERRIDE_EN		(1 << 24)
2035 
2036 #define MG_DP_MODE_LN0_ACU_PORT1			0x1683A0
2037 #define MG_DP_MODE_LN1_ACU_PORT1			0x1687A0
2038 #define MG_DP_MODE_LN0_ACU_PORT2			0x1693A0
2039 #define MG_DP_MODE_LN1_ACU_PORT2			0x1697A0
2040 #define MG_DP_MODE_LN0_ACU_PORT3			0x16A3A0
2041 #define MG_DP_MODE_LN1_ACU_PORT3			0x16A7A0
2042 #define MG_DP_MODE_LN0_ACU_PORT4			0x16B3A0
2043 #define MG_DP_MODE_LN1_ACU_PORT4			0x16B7A0
2044 #define MG_DP_MODE(port, ln)	\
2045 	MG_PHY_PORT_LN(port, ln, MG_DP_MODE_LN0_ACU_PORT1, \
2046 				 MG_DP_MODE_LN0_ACU_PORT2, \
2047 				 MG_DP_MODE_LN1_ACU_PORT1)
2048 #define   MG_DP_MODE_CFG_DP_X2_MODE			(1 << 7)
2049 #define   MG_DP_MODE_CFG_DP_X1_MODE			(1 << 6)
2050 #define   MG_DP_MODE_CFG_TR2PWR_GATING			(1 << 5)
2051 #define   MG_DP_MODE_CFG_TRPWR_GATING			(1 << 4)
2052 #define   MG_DP_MODE_CFG_CLNPWR_GATING			(1 << 3)
2053 #define   MG_DP_MODE_CFG_DIGPWR_GATING			(1 << 2)
2054 #define   MG_DP_MODE_CFG_GAONPWR_GATING			(1 << 1)
2055 
2056 #define MG_MISC_SUS0_PORT1				0x168814
2057 #define MG_MISC_SUS0_PORT2				0x169814
2058 #define MG_MISC_SUS0_PORT3				0x16A814
2059 #define MG_MISC_SUS0_PORT4				0x16B814
2060 #define MG_MISC_SUS0(tc_port) \
2061 	_MMIO(_PORT(tc_port, MG_MISC_SUS0_PORT1, MG_MISC_SUS0_PORT2))
2062 #define   MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK	(3 << 14)
2063 #define   MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(x)	((x) << 14)
2064 #define   MG_MISC_SUS0_CFG_TR2PWR_GATING		(1 << 12)
2065 #define   MG_MISC_SUS0_CFG_CL2PWR_GATING		(1 << 11)
2066 #define   MG_MISC_SUS0_CFG_GAONPWR_GATING		(1 << 10)
2067 #define   MG_MISC_SUS0_CFG_TRPWR_GATING			(1 << 7)
2068 #define   MG_MISC_SUS0_CFG_CL1PWR_GATING		(1 << 6)
2069 #define   MG_MISC_SUS0_CFG_DGPWR_GATING			(1 << 5)
2070 
2071 /* The spec defines this only for BXT PHY0, but lets assume that this
2072  * would exist for PHY1 too if it had a second channel.
2073  */
2074 #define _PORT_CL2CM_DW6_A		0x162358
2075 #define _PORT_CL2CM_DW6_BC		0x6C358
2076 #define BXT_PORT_CL2CM_DW6(phy)		_BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
2077 #define   DW6_OLDO_DYN_PWR_DOWN_EN	(1 << 28)
2078 
2079 #define FIA1_BASE			0x163000
2080 
2081 /* ICL PHY DFLEX registers */
2082 #define PORT_TX_DFLEXDPMLE1		_MMIO(FIA1_BASE + 0x008C0)
2083 #define   DFLEXDPMLE1_DPMLETC_MASK(tc_port)	(0xf << (4 * (tc_port)))
2084 #define   DFLEXDPMLE1_DPMLETC_ML0(tc_port)	(1 << (4 * (tc_port)))
2085 #define   DFLEXDPMLE1_DPMLETC_ML1_0(tc_port)	(3 << (4 * (tc_port)))
2086 #define   DFLEXDPMLE1_DPMLETC_ML3(tc_port)	(8 << (4 * (tc_port)))
2087 #define   DFLEXDPMLE1_DPMLETC_ML3_2(tc_port)	(12 << (4 * (tc_port)))
2088 #define   DFLEXDPMLE1_DPMLETC_ML3_0(tc_port)	(15 << (4 * (tc_port)))
2089 
2090 /* BXT PHY Ref registers */
2091 #define _PORT_REF_DW3_A			0x16218C
2092 #define _PORT_REF_DW3_BC		0x6C18C
2093 #define   GRC_DONE			(1 << 22)
2094 #define BXT_PORT_REF_DW3(phy)		_BXT_PHY((phy), _PORT_REF_DW3_BC)
2095 
2096 #define _PORT_REF_DW6_A			0x162198
2097 #define _PORT_REF_DW6_BC		0x6C198
2098 #define   GRC_CODE_SHIFT		24
2099 #define   GRC_CODE_MASK			(0xFF << GRC_CODE_SHIFT)
2100 #define   GRC_CODE_FAST_SHIFT		16
2101 #define   GRC_CODE_FAST_MASK		(0xFF << GRC_CODE_FAST_SHIFT)
2102 #define   GRC_CODE_SLOW_SHIFT		8
2103 #define   GRC_CODE_SLOW_MASK		(0xFF << GRC_CODE_SLOW_SHIFT)
2104 #define   GRC_CODE_NOM_MASK		0xFF
2105 #define BXT_PORT_REF_DW6(phy)		_BXT_PHY((phy), _PORT_REF_DW6_BC)
2106 
2107 #define _PORT_REF_DW8_A			0x1621A0
2108 #define _PORT_REF_DW8_BC		0x6C1A0
2109 #define   GRC_DIS			(1 << 15)
2110 #define   GRC_RDY_OVRD			(1 << 1)
2111 #define BXT_PORT_REF_DW8(phy)		_BXT_PHY((phy), _PORT_REF_DW8_BC)
2112 
2113 /* BXT PHY PCS registers */
2114 #define _PORT_PCS_DW10_LN01_A		0x162428
2115 #define _PORT_PCS_DW10_LN01_B		0x6C428
2116 #define _PORT_PCS_DW10_LN01_C		0x6C828
2117 #define _PORT_PCS_DW10_GRP_A		0x162C28
2118 #define _PORT_PCS_DW10_GRP_B		0x6CC28
2119 #define _PORT_PCS_DW10_GRP_C		0x6CE28
2120 #define BXT_PORT_PCS_DW10_LN01(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
2121 							 _PORT_PCS_DW10_LN01_B, \
2122 							 _PORT_PCS_DW10_LN01_C)
2123 #define BXT_PORT_PCS_DW10_GRP(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
2124 							 _PORT_PCS_DW10_GRP_B, \
2125 							 _PORT_PCS_DW10_GRP_C)
2126 
2127 #define   TX2_SWING_CALC_INIT		(1 << 31)
2128 #define   TX1_SWING_CALC_INIT		(1 << 30)
2129 
2130 #define _PORT_PCS_DW12_LN01_A		0x162430
2131 #define _PORT_PCS_DW12_LN01_B		0x6C430
2132 #define _PORT_PCS_DW12_LN01_C		0x6C830
2133 #define _PORT_PCS_DW12_LN23_A		0x162630
2134 #define _PORT_PCS_DW12_LN23_B		0x6C630
2135 #define _PORT_PCS_DW12_LN23_C		0x6CA30
2136 #define _PORT_PCS_DW12_GRP_A		0x162c30
2137 #define _PORT_PCS_DW12_GRP_B		0x6CC30
2138 #define _PORT_PCS_DW12_GRP_C		0x6CE30
2139 #define   LANESTAGGER_STRAP_OVRD	(1 << 6)
2140 #define   LANE_STAGGER_MASK		0x1F
2141 #define BXT_PORT_PCS_DW12_LN01(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
2142 							 _PORT_PCS_DW12_LN01_B, \
2143 							 _PORT_PCS_DW12_LN01_C)
2144 #define BXT_PORT_PCS_DW12_LN23(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
2145 							 _PORT_PCS_DW12_LN23_B, \
2146 							 _PORT_PCS_DW12_LN23_C)
2147 #define BXT_PORT_PCS_DW12_GRP(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
2148 							 _PORT_PCS_DW12_GRP_B, \
2149 							 _PORT_PCS_DW12_GRP_C)
2150 
2151 /* BXT PHY TX registers */
2152 #define _BXT_LANE_OFFSET(lane)           (((lane) >> 1) * 0x200 +	\
2153 					  ((lane) & 1) * 0x80)
2154 
2155 #define _PORT_TX_DW2_LN0_A		0x162508
2156 #define _PORT_TX_DW2_LN0_B		0x6C508
2157 #define _PORT_TX_DW2_LN0_C		0x6C908
2158 #define _PORT_TX_DW2_GRP_A		0x162D08
2159 #define _PORT_TX_DW2_GRP_B		0x6CD08
2160 #define _PORT_TX_DW2_GRP_C		0x6CF08
2161 #define BXT_PORT_TX_DW2_LN0(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
2162 							 _PORT_TX_DW2_LN0_B, \
2163 							 _PORT_TX_DW2_LN0_C)
2164 #define BXT_PORT_TX_DW2_GRP(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
2165 							 _PORT_TX_DW2_GRP_B, \
2166 							 _PORT_TX_DW2_GRP_C)
2167 #define   MARGIN_000_SHIFT		16
2168 #define   MARGIN_000			(0xFF << MARGIN_000_SHIFT)
2169 #define   UNIQ_TRANS_SCALE_SHIFT	8
2170 #define   UNIQ_TRANS_SCALE		(0xFF << UNIQ_TRANS_SCALE_SHIFT)
2171 
2172 #define _PORT_TX_DW3_LN0_A		0x16250C
2173 #define _PORT_TX_DW3_LN0_B		0x6C50C
2174 #define _PORT_TX_DW3_LN0_C		0x6C90C
2175 #define _PORT_TX_DW3_GRP_A		0x162D0C
2176 #define _PORT_TX_DW3_GRP_B		0x6CD0C
2177 #define _PORT_TX_DW3_GRP_C		0x6CF0C
2178 #define BXT_PORT_TX_DW3_LN0(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
2179 							 _PORT_TX_DW3_LN0_B, \
2180 							 _PORT_TX_DW3_LN0_C)
2181 #define BXT_PORT_TX_DW3_GRP(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
2182 							 _PORT_TX_DW3_GRP_B, \
2183 							 _PORT_TX_DW3_GRP_C)
2184 #define   SCALE_DCOMP_METHOD		(1 << 26)
2185 #define   UNIQUE_TRANGE_EN_METHOD	(1 << 27)
2186 
2187 #define _PORT_TX_DW4_LN0_A		0x162510
2188 #define _PORT_TX_DW4_LN0_B		0x6C510
2189 #define _PORT_TX_DW4_LN0_C		0x6C910
2190 #define _PORT_TX_DW4_GRP_A		0x162D10
2191 #define _PORT_TX_DW4_GRP_B		0x6CD10
2192 #define _PORT_TX_DW4_GRP_C		0x6CF10
2193 #define BXT_PORT_TX_DW4_LN0(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
2194 							 _PORT_TX_DW4_LN0_B, \
2195 							 _PORT_TX_DW4_LN0_C)
2196 #define BXT_PORT_TX_DW4_GRP(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
2197 							 _PORT_TX_DW4_GRP_B, \
2198 							 _PORT_TX_DW4_GRP_C)
2199 #define   DEEMPH_SHIFT			24
2200 #define   DE_EMPHASIS			(0xFF << DEEMPH_SHIFT)
2201 
2202 #define _PORT_TX_DW5_LN0_A		0x162514
2203 #define _PORT_TX_DW5_LN0_B		0x6C514
2204 #define _PORT_TX_DW5_LN0_C		0x6C914
2205 #define _PORT_TX_DW5_GRP_A		0x162D14
2206 #define _PORT_TX_DW5_GRP_B		0x6CD14
2207 #define _PORT_TX_DW5_GRP_C		0x6CF14
2208 #define BXT_PORT_TX_DW5_LN0(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
2209 							 _PORT_TX_DW5_LN0_B, \
2210 							 _PORT_TX_DW5_LN0_C)
2211 #define BXT_PORT_TX_DW5_GRP(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
2212 							 _PORT_TX_DW5_GRP_B, \
2213 							 _PORT_TX_DW5_GRP_C)
2214 #define   DCC_DELAY_RANGE_1		(1 << 9)
2215 #define   DCC_DELAY_RANGE_2		(1 << 8)
2216 
2217 #define _PORT_TX_DW14_LN0_A		0x162538
2218 #define _PORT_TX_DW14_LN0_B		0x6C538
2219 #define _PORT_TX_DW14_LN0_C		0x6C938
2220 #define   LATENCY_OPTIM_SHIFT		30
2221 #define   LATENCY_OPTIM			(1 << LATENCY_OPTIM_SHIFT)
2222 #define BXT_PORT_TX_DW14_LN(phy, ch, lane)				\
2223 	_MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B,			\
2224 				   _PORT_TX_DW14_LN0_C) +		\
2225 	      _BXT_LANE_OFFSET(lane))
2226 
2227 /* UAIMI scratch pad register 1 */
2228 #define UAIMI_SPR1			_MMIO(0x4F074)
2229 /* SKL VccIO mask */
2230 #define SKL_VCCIO_MASK			0x1
2231 /* SKL balance leg register */
2232 #define DISPIO_CR_TX_BMU_CR0		_MMIO(0x6C00C)
2233 /* I_boost values */
2234 #define BALANCE_LEG_SHIFT(port)		(8 + 3 * (port))
2235 #define BALANCE_LEG_MASK(port)		(7 << (8 + 3 * (port)))
2236 /* Balance leg disable bits */
2237 #define BALANCE_LEG_DISABLE_SHIFT	23
2238 #define BALANCE_LEG_DISABLE(port)	(1 << (23 + (port)))
2239 
2240 /*
2241  * Fence registers
2242  * [0-7]  @ 0x2000 gen2,gen3
2243  * [8-15] @ 0x3000 945,g33,pnv
2244  *
2245  * [0-15] @ 0x3000 gen4,gen5
2246  *
2247  * [0-15] @ 0x100000 gen6,vlv,chv
2248  * [0-31] @ 0x100000 gen7+
2249  */
2250 #define FENCE_REG(i)			_MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
2251 #define   I830_FENCE_START_MASK		0x07f80000
2252 #define   I830_FENCE_TILING_Y_SHIFT	12
2253 #define   I830_FENCE_SIZE_BITS(size)	((ffs((size) >> 19) - 1) << 8)
2254 #define   I830_FENCE_PITCH_SHIFT	4
2255 #define   I830_FENCE_REG_VALID		(1 << 0)
2256 #define   I915_FENCE_MAX_PITCH_VAL	4
2257 #define   I830_FENCE_MAX_PITCH_VAL	6
2258 #define   I830_FENCE_MAX_SIZE_VAL	(1 << 8)
2259 
2260 #define   I915_FENCE_START_MASK		0x0ff00000
2261 #define   I915_FENCE_SIZE_BITS(size)	((ffs((size) >> 20) - 1) << 8)
2262 
2263 #define FENCE_REG_965_LO(i)		_MMIO(0x03000 + (i) * 8)
2264 #define FENCE_REG_965_HI(i)		_MMIO(0x03000 + (i) * 8 + 4)
2265 #define   I965_FENCE_PITCH_SHIFT	2
2266 #define   I965_FENCE_TILING_Y_SHIFT	1
2267 #define   I965_FENCE_REG_VALID		(1 << 0)
2268 #define   I965_FENCE_MAX_PITCH_VAL	0x0400
2269 
2270 #define FENCE_REG_GEN6_LO(i)		_MMIO(0x100000 + (i) * 8)
2271 #define FENCE_REG_GEN6_HI(i)		_MMIO(0x100000 + (i) * 8 + 4)
2272 #define   GEN6_FENCE_PITCH_SHIFT	32
2273 #define   GEN7_FENCE_MAX_PITCH_VAL	0x0800
2274 
2275 
2276 /* control register for cpu gtt access */
2277 #define TILECTL				_MMIO(0x101000)
2278 #define   TILECTL_SWZCTL			(1 << 0)
2279 #define   TILECTL_TLBPF			(1 << 1)
2280 #define   TILECTL_TLB_PREFETCH_DIS	(1 << 2)
2281 #define   TILECTL_BACKSNOOP_DIS		(1 << 3)
2282 
2283 /*
2284  * Instruction and interrupt control regs
2285  */
2286 #define PGTBL_CTL	_MMIO(0x02020)
2287 #define   PGTBL_ADDRESS_LO_MASK	0xfffff000 /* bits [31:12] */
2288 #define   PGTBL_ADDRESS_HI_MASK	0x000000f0 /* bits [35:32] (gen4) */
2289 #define PGTBL_ER	_MMIO(0x02024)
2290 #define PRB0_BASE	(0x2030 - 0x30)
2291 #define PRB1_BASE	(0x2040 - 0x30) /* 830,gen3 */
2292 #define PRB2_BASE	(0x2050 - 0x30) /* gen3 */
2293 #define SRB0_BASE	(0x2100 - 0x30) /* gen2 */
2294 #define SRB1_BASE	(0x2110 - 0x30) /* gen2 */
2295 #define SRB2_BASE	(0x2120 - 0x30) /* 830 */
2296 #define SRB3_BASE	(0x2130 - 0x30) /* 830 */
2297 #define RENDER_RING_BASE	0x02000
2298 #define BSD_RING_BASE		0x04000
2299 #define GEN6_BSD_RING_BASE	0x12000
2300 #define GEN8_BSD2_RING_BASE	0x1c000
2301 #define GEN11_BSD_RING_BASE	0x1c0000
2302 #define GEN11_BSD2_RING_BASE	0x1c4000
2303 #define GEN11_BSD3_RING_BASE	0x1d0000
2304 #define GEN11_BSD4_RING_BASE	0x1d4000
2305 #define VEBOX_RING_BASE		0x1a000
2306 #define GEN11_VEBOX_RING_BASE		0x1c8000
2307 #define GEN11_VEBOX2_RING_BASE		0x1d8000
2308 #define BLT_RING_BASE		0x22000
2309 #define RING_TAIL(base)		_MMIO((base) + 0x30)
2310 #define RING_HEAD(base)		_MMIO((base) + 0x34)
2311 #define RING_START(base)	_MMIO((base) + 0x38)
2312 #define RING_CTL(base)		_MMIO((base) + 0x3c)
2313 #define   RING_CTL_SIZE(size)	((size) - PAGE_SIZE) /* in bytes -> pages */
2314 #define RING_SYNC_0(base)	_MMIO((base) + 0x40)
2315 #define RING_SYNC_1(base)	_MMIO((base) + 0x44)
2316 #define RING_SYNC_2(base)	_MMIO((base) + 0x48)
2317 #define GEN6_RVSYNC	(RING_SYNC_0(RENDER_RING_BASE))
2318 #define GEN6_RBSYNC	(RING_SYNC_1(RENDER_RING_BASE))
2319 #define GEN6_RVESYNC	(RING_SYNC_2(RENDER_RING_BASE))
2320 #define GEN6_VBSYNC	(RING_SYNC_0(GEN6_BSD_RING_BASE))
2321 #define GEN6_VRSYNC	(RING_SYNC_1(GEN6_BSD_RING_BASE))
2322 #define GEN6_VVESYNC	(RING_SYNC_2(GEN6_BSD_RING_BASE))
2323 #define GEN6_BRSYNC	(RING_SYNC_0(BLT_RING_BASE))
2324 #define GEN6_BVSYNC	(RING_SYNC_1(BLT_RING_BASE))
2325 #define GEN6_BVESYNC	(RING_SYNC_2(BLT_RING_BASE))
2326 #define GEN6_VEBSYNC	(RING_SYNC_0(VEBOX_RING_BASE))
2327 #define GEN6_VERSYNC	(RING_SYNC_1(VEBOX_RING_BASE))
2328 #define GEN6_VEVSYNC	(RING_SYNC_2(VEBOX_RING_BASE))
2329 #define GEN6_NOSYNC	INVALID_MMIO_REG
2330 #define RING_PSMI_CTL(base)	_MMIO((base) + 0x50)
2331 #define RING_MAX_IDLE(base)	_MMIO((base) + 0x54)
2332 #define RING_HWS_PGA(base)	_MMIO((base) + 0x80)
2333 #define RING_HWS_PGA_GEN6(base)	_MMIO((base) + 0x2080)
2334 #define RING_RESET_CTL(base)	_MMIO((base) + 0xd0)
2335 #define   RESET_CTL_REQUEST_RESET  (1 << 0)
2336 #define   RESET_CTL_READY_TO_RESET (1 << 1)
2337 #define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c)
2338 
2339 #define HSW_GTT_CACHE_EN	_MMIO(0x4024)
2340 #define   GTT_CACHE_EN_ALL	0xF0007FFF
2341 #define GEN7_WR_WATERMARK	_MMIO(0x4028)
2342 #define GEN7_GFX_PRIO_CTRL	_MMIO(0x402C)
2343 #define ARB_MODE		_MMIO(0x4030)
2344 #define   ARB_MODE_SWIZZLE_SNB	(1 << 4)
2345 #define   ARB_MODE_SWIZZLE_IVB	(1 << 5)
2346 #define GEN7_GFX_PEND_TLB0	_MMIO(0x4034)
2347 #define GEN7_GFX_PEND_TLB1	_MMIO(0x4038)
2348 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
2349 #define GEN7_LRA_LIMITS(i)	_MMIO(0x403C + (i) * 4)
2350 #define GEN7_LRA_LIMITS_REG_NUM	13
2351 #define GEN7_MEDIA_MAX_REQ_COUNT	_MMIO(0x4070)
2352 #define GEN7_GFX_MAX_REQ_COUNT		_MMIO(0x4074)
2353 
2354 #define GAMTARBMODE		_MMIO(0x04a08)
2355 #define   ARB_MODE_BWGTLB_DISABLE (1 << 9)
2356 #define   ARB_MODE_SWIZZLE_BDW	(1 << 1)
2357 #define RENDER_HWS_PGA_GEN7	_MMIO(0x04080)
2358 #define RING_FAULT_REG(engine)	_MMIO(0x4094 + 0x100 * (engine)->hw_id)
2359 #define GEN8_RING_FAULT_REG	_MMIO(0x4094)
2360 #define   GEN8_RING_FAULT_ENGINE_ID(x)	(((x) >> 12) & 0x7)
2361 #define   RING_FAULT_GTTSEL_MASK (1 << 11)
2362 #define   RING_FAULT_SRCID(x)	(((x) >> 3) & 0xff)
2363 #define   RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
2364 #define   RING_FAULT_VALID	(1 << 0)
2365 #define DONE_REG		_MMIO(0x40b0)
2366 #define GEN8_PRIVATE_PAT_LO	_MMIO(0x40e0)
2367 #define GEN8_PRIVATE_PAT_HI	_MMIO(0x40e0 + 4)
2368 #define GEN10_PAT_INDEX(index)	_MMIO(0x40e0 + (index) * 4)
2369 #define BSD_HWS_PGA_GEN7	_MMIO(0x04180)
2370 #define BLT_HWS_PGA_GEN7	_MMIO(0x04280)
2371 #define VEBOX_HWS_PGA_GEN7	_MMIO(0x04380)
2372 #define RING_ACTHD(base)	_MMIO((base) + 0x74)
2373 #define RING_ACTHD_UDW(base)	_MMIO((base) + 0x5c)
2374 #define RING_NOPID(base)	_MMIO((base) + 0x94)
2375 #define RING_IMR(base)		_MMIO((base) + 0xa8)
2376 #define RING_HWSTAM(base)	_MMIO((base) + 0x98)
2377 #define RING_TIMESTAMP(base)		_MMIO((base) + 0x358)
2378 #define RING_TIMESTAMP_UDW(base)	_MMIO((base) + 0x358 + 4)
2379 #define   TAIL_ADDR		0x001FFFF8
2380 #define   HEAD_WRAP_COUNT	0xFFE00000
2381 #define   HEAD_WRAP_ONE		0x00200000
2382 #define   HEAD_ADDR		0x001FFFFC
2383 #define   RING_NR_PAGES		0x001FF000
2384 #define   RING_REPORT_MASK	0x00000006
2385 #define   RING_REPORT_64K	0x00000002
2386 #define   RING_REPORT_128K	0x00000004
2387 #define   RING_NO_REPORT	0x00000000
2388 #define   RING_VALID_MASK	0x00000001
2389 #define   RING_VALID		0x00000001
2390 #define   RING_INVALID		0x00000000
2391 #define   RING_WAIT_I8XX	(1 << 0) /* gen2, PRBx_HEAD */
2392 #define   RING_WAIT		(1 << 11) /* gen3+, PRBx_CTL */
2393 #define   RING_WAIT_SEMAPHORE	(1 << 10) /* gen6+ */
2394 
2395 #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4)
2396 #define   RING_MAX_NONPRIV_SLOTS  12
2397 
2398 #define GEN7_TLB_RD_ADDR	_MMIO(0x4700)
2399 
2400 #define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
2401 #define   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS	(1 << 18)
2402 
2403 #define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080)
2404 #define   GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF
2405 #define   GAMW_ECO_DEV_CTX_RELOAD_DISABLE	(1 << 7)
2406 
2407 #define GAMT_CHKN_BIT_REG	_MMIO(0x4ab8)
2408 #define   GAMT_CHKN_DISABLE_L3_COH_PIPE			(1 << 31)
2409 #define   GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING	(1 << 28)
2410 #define   GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT	(1 << 24)
2411 
2412 #if 0
2413 #define PRB0_TAIL	_MMIO(0x2030)
2414 #define PRB0_HEAD	_MMIO(0x2034)
2415 #define PRB0_START	_MMIO(0x2038)
2416 #define PRB0_CTL	_MMIO(0x203c)
2417 #define PRB1_TAIL	_MMIO(0x2040) /* 915+ only */
2418 #define PRB1_HEAD	_MMIO(0x2044) /* 915+ only */
2419 #define PRB1_START	_MMIO(0x2048) /* 915+ only */
2420 #define PRB1_CTL	_MMIO(0x204c) /* 915+ only */
2421 #endif
2422 #define IPEIR_I965	_MMIO(0x2064)
2423 #define IPEHR_I965	_MMIO(0x2068)
2424 #define GEN7_SC_INSTDONE	_MMIO(0x7100)
2425 #define GEN7_SAMPLER_INSTDONE	_MMIO(0xe160)
2426 #define GEN7_ROW_INSTDONE	_MMIO(0xe164)
2427 #define GEN8_MCR_SELECTOR		_MMIO(0xfdc)
2428 #define   GEN8_MCR_SLICE(slice)		(((slice) & 3) << 26)
2429 #define   GEN8_MCR_SLICE_MASK		GEN8_MCR_SLICE(3)
2430 #define   GEN8_MCR_SUBSLICE(subslice)	(((subslice) & 3) << 24)
2431 #define   GEN8_MCR_SUBSLICE_MASK	GEN8_MCR_SUBSLICE(3)
2432 #define   GEN11_MCR_SLICE(slice)	(((slice) & 0xf) << 27)
2433 #define   GEN11_MCR_SLICE_MASK		GEN11_MCR_SLICE(0xf)
2434 #define   GEN11_MCR_SUBSLICE(subslice)	(((subslice) & 0x7) << 24)
2435 #define   GEN11_MCR_SUBSLICE_MASK	GEN11_MCR_SUBSLICE(0x7)
2436 #define RING_IPEIR(base)	_MMIO((base) + 0x64)
2437 #define RING_IPEHR(base)	_MMIO((base) + 0x68)
2438 /*
2439  * On GEN4, only the render ring INSTDONE exists and has a different
2440  * layout than the GEN7+ version.
2441  * The GEN2 counterpart of this register is GEN2_INSTDONE.
2442  */
2443 #define RING_INSTDONE(base)	_MMIO((base) + 0x6c)
2444 #define RING_INSTPS(base)	_MMIO((base) + 0x70)
2445 #define RING_DMA_FADD(base)	_MMIO((base) + 0x78)
2446 #define RING_DMA_FADD_UDW(base)	_MMIO((base) + 0x60) /* gen8+ */
2447 #define RING_INSTPM(base)	_MMIO((base) + 0xc0)
2448 #define RING_MI_MODE(base)	_MMIO((base) + 0x9c)
2449 #define INSTPS		_MMIO(0x2070) /* 965+ only */
2450 #define GEN4_INSTDONE1	_MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */
2451 #define ACTHD_I965	_MMIO(0x2074)
2452 #define HWS_PGA		_MMIO(0x2080)
2453 #define HWS_ADDRESS_MASK	0xfffff000
2454 #define HWS_START_ADDRESS_SHIFT	4
2455 #define PWRCTXA		_MMIO(0x2088) /* 965GM+ only */
2456 #define   PWRCTX_EN	(1 << 0)
2457 #define IPEIR		_MMIO(0x2088)
2458 #define IPEHR		_MMIO(0x208c)
2459 #define GEN2_INSTDONE	_MMIO(0x2090)
2460 #define NOPID		_MMIO(0x2094)
2461 #define HWSTAM		_MMIO(0x2098)
2462 #define DMA_FADD_I8XX	_MMIO(0x20d0)
2463 #define RING_BBSTATE(base)	_MMIO((base) + 0x110)
2464 #define   RING_BB_PPGTT		(1 << 5)
2465 #define RING_SBBADDR(base)	_MMIO((base) + 0x114) /* hsw+ */
2466 #define RING_SBBSTATE(base)	_MMIO((base) + 0x118) /* hsw+ */
2467 #define RING_SBBADDR_UDW(base)	_MMIO((base) + 0x11c) /* gen8+ */
2468 #define RING_BBADDR(base)	_MMIO((base) + 0x140)
2469 #define RING_BBADDR_UDW(base)	_MMIO((base) + 0x168) /* gen8+ */
2470 #define RING_BB_PER_CTX_PTR(base)	_MMIO((base) + 0x1c0) /* gen8+ */
2471 #define RING_INDIRECT_CTX(base)		_MMIO((base) + 0x1c4) /* gen8+ */
2472 #define RING_INDIRECT_CTX_OFFSET(base)	_MMIO((base) + 0x1c8) /* gen8+ */
2473 #define RING_CTX_TIMESTAMP(base)	_MMIO((base) + 0x3a8) /* gen8+ */
2474 
2475 #define ERROR_GEN6	_MMIO(0x40a0)
2476 #define GEN7_ERR_INT	_MMIO(0x44040)
2477 #define   ERR_INT_POISON		(1 << 31)
2478 #define   ERR_INT_MMIO_UNCLAIMED	(1 << 13)
2479 #define   ERR_INT_PIPE_CRC_DONE_C	(1 << 8)
2480 #define   ERR_INT_FIFO_UNDERRUN_C	(1 << 6)
2481 #define   ERR_INT_PIPE_CRC_DONE_B	(1 << 5)
2482 #define   ERR_INT_FIFO_UNDERRUN_B	(1 << 3)
2483 #define   ERR_INT_PIPE_CRC_DONE_A	(1 << 2)
2484 #define   ERR_INT_PIPE_CRC_DONE(pipe)	(1 << (2 + (pipe) * 3))
2485 #define   ERR_INT_FIFO_UNDERRUN_A	(1 << 0)
2486 #define   ERR_INT_FIFO_UNDERRUN(pipe)	(1 << ((pipe) * 3))
2487 
2488 #define GEN8_FAULT_TLB_DATA0		_MMIO(0x4b10)
2489 #define GEN8_FAULT_TLB_DATA1		_MMIO(0x4b14)
2490 #define   FAULT_VA_HIGH_BITS		(0xf << 0)
2491 #define   FAULT_GTT_SEL			(1 << 4)
2492 
2493 #define FPGA_DBG		_MMIO(0x42300)
2494 #define   FPGA_DBG_RM_NOCLAIM	(1 << 31)
2495 
2496 #define CLAIM_ER		_MMIO(VLV_DISPLAY_BASE + 0x2028)
2497 #define   CLAIM_ER_CLR		(1 << 31)
2498 #define   CLAIM_ER_OVERFLOW	(1 << 16)
2499 #define   CLAIM_ER_CTR_MASK	0xffff
2500 
2501 #define DERRMR		_MMIO(0x44050)
2502 /* Note that HBLANK events are reserved on bdw+ */
2503 #define   DERRMR_PIPEA_SCANLINE		(1 << 0)
2504 #define   DERRMR_PIPEA_PRI_FLIP_DONE	(1 << 1)
2505 #define   DERRMR_PIPEA_SPR_FLIP_DONE	(1 << 2)
2506 #define   DERRMR_PIPEA_VBLANK		(1 << 3)
2507 #define   DERRMR_PIPEA_HBLANK		(1 << 5)
2508 #define   DERRMR_PIPEB_SCANLINE		(1 << 8)
2509 #define   DERRMR_PIPEB_PRI_FLIP_DONE	(1 << 9)
2510 #define   DERRMR_PIPEB_SPR_FLIP_DONE	(1 << 10)
2511 #define   DERRMR_PIPEB_VBLANK		(1 << 11)
2512 #define   DERRMR_PIPEB_HBLANK		(1 << 13)
2513 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
2514 #define   DERRMR_PIPEC_SCANLINE		(1 << 14)
2515 #define   DERRMR_PIPEC_PRI_FLIP_DONE	(1 << 15)
2516 #define   DERRMR_PIPEC_SPR_FLIP_DONE	(1 << 20)
2517 #define   DERRMR_PIPEC_VBLANK		(1 << 21)
2518 #define   DERRMR_PIPEC_HBLANK		(1 << 22)
2519 
2520 
2521 /* GM45+ chicken bits -- debug workaround bits that may be required
2522  * for various sorts of correct behavior.  The top 16 bits of each are
2523  * the enables for writing to the corresponding low bit.
2524  */
2525 #define _3D_CHICKEN	_MMIO(0x2084)
2526 #define  _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB	(1 << 10)
2527 #define _3D_CHICKEN2	_MMIO(0x208c)
2528 
2529 #define FF_SLICE_CHICKEN	_MMIO(0x2088)
2530 #define  FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX	(1 << 1)
2531 
2532 /* Disables pipelining of read flushes past the SF-WIZ interface.
2533  * Required on all Ironlake steppings according to the B-Spec, but the
2534  * particular danger of not doing so is not specified.
2535  */
2536 # define _3D_CHICKEN2_WM_READ_PIPELINED			(1 << 14)
2537 #define _3D_CHICKEN3	_MMIO(0x2090)
2538 #define  _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX		(1 << 12)
2539 #define  _3D_CHICKEN_SF_DISABLE_OBJEND_CULL		(1 << 10)
2540 #define  _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE	(1 << 5)
2541 #define  _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL		(1 << 5)
2542 #define  _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x)	((x) << 1) /* gen8+ */
2543 #define  _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH	(1 << 1) /* gen6 */
2544 
2545 #define MI_MODE		_MMIO(0x209c)
2546 # define VS_TIMER_DISPATCH				(1 << 6)
2547 # define MI_FLUSH_ENABLE				(1 << 12)
2548 # define ASYNC_FLIP_PERF_DISABLE			(1 << 14)
2549 # define MODE_IDLE					(1 << 9)
2550 # define STOP_RING					(1 << 8)
2551 
2552 #define GEN6_GT_MODE	_MMIO(0x20d0)
2553 #define GEN7_GT_MODE	_MMIO(0x7008)
2554 #define   GEN6_WIZ_HASHING(hi, lo)			(((hi) << 9) | ((lo) << 7))
2555 #define   GEN6_WIZ_HASHING_8x8				GEN6_WIZ_HASHING(0, 0)
2556 #define   GEN6_WIZ_HASHING_8x4				GEN6_WIZ_HASHING(0, 1)
2557 #define   GEN6_WIZ_HASHING_16x4				GEN6_WIZ_HASHING(1, 0)
2558 #define   GEN6_WIZ_HASHING_MASK				GEN6_WIZ_HASHING(1, 1)
2559 #define   GEN6_TD_FOUR_ROW_DISPATCH_DISABLE		(1 << 5)
2560 #define   GEN9_IZ_HASHING_MASK(slice)			(0x3 << ((slice) * 2))
2561 #define   GEN9_IZ_HASHING(slice, val)			((val) << ((slice) * 2))
2562 
2563 /* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */
2564 #define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)
2565 #define   GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
2566 #define   GEN11_ENABLE_32_PLANE_MODE (1 << 7)
2567 
2568 /* WaClearTdlStateAckDirtyBits */
2569 #define GEN8_STATE_ACK		_MMIO(0x20F0)
2570 #define GEN9_STATE_ACK_SLICE1	_MMIO(0x20F8)
2571 #define GEN9_STATE_ACK_SLICE2	_MMIO(0x2100)
2572 #define   GEN9_STATE_ACK_TDL0 (1 << 12)
2573 #define   GEN9_STATE_ACK_TDL1 (1 << 13)
2574 #define   GEN9_STATE_ACK_TDL2 (1 << 14)
2575 #define   GEN9_STATE_ACK_TDL3 (1 << 15)
2576 #define   GEN9_SUBSLICE_TDL_ACK_BITS \
2577 	(GEN9_STATE_ACK_TDL3 | GEN9_STATE_ACK_TDL2 | \
2578 	 GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0)
2579 
2580 #define GFX_MODE	_MMIO(0x2520)
2581 #define GFX_MODE_GEN7	_MMIO(0x229c)
2582 #define RING_MODE_GEN7(engine)	_MMIO((engine)->mmio_base + 0x29c)
2583 #define   GFX_RUN_LIST_ENABLE		(1 << 15)
2584 #define   GFX_INTERRUPT_STEERING	(1 << 14)
2585 #define   GFX_TLB_INVALIDATE_EXPLICIT	(1 << 13)
2586 #define   GFX_SURFACE_FAULT_ENABLE	(1 << 12)
2587 #define   GFX_REPLAY_MODE		(1 << 11)
2588 #define   GFX_PSMI_GRANULARITY		(1 << 10)
2589 #define   GFX_PPGTT_ENABLE		(1 << 9)
2590 #define   GEN8_GFX_PPGTT_48B		(1 << 7)
2591 
2592 #define   GFX_FORWARD_VBLANK_MASK	(3 << 5)
2593 #define   GFX_FORWARD_VBLANK_NEVER	(0 << 5)
2594 #define   GFX_FORWARD_VBLANK_ALWAYS	(1 << 5)
2595 #define   GFX_FORWARD_VBLANK_COND	(2 << 5)
2596 
2597 #define   GEN11_GFX_DISABLE_LEGACY_MODE	(1 << 3)
2598 
2599 #define VLV_DISPLAY_BASE 0x180000
2600 #define VLV_MIPI_BASE VLV_DISPLAY_BASE
2601 #define BXT_MIPI_BASE 0x60000
2602 
2603 #define VLV_GU_CTL0	_MMIO(VLV_DISPLAY_BASE + 0x2030)
2604 #define VLV_GU_CTL1	_MMIO(VLV_DISPLAY_BASE + 0x2034)
2605 #define SCPD0		_MMIO(0x209c) /* 915+ only */
2606 #define IER		_MMIO(0x20a0)
2607 #define IIR		_MMIO(0x20a4)
2608 #define IMR		_MMIO(0x20a8)
2609 #define ISR		_MMIO(0x20ac)
2610 #define VLV_GUNIT_CLOCK_GATE	_MMIO(VLV_DISPLAY_BASE + 0x2060)
2611 #define   GINT_DIS		(1 << 22)
2612 #define   GCFG_DIS		(1 << 8)
2613 #define VLV_GUNIT_CLOCK_GATE2	_MMIO(VLV_DISPLAY_BASE + 0x2064)
2614 #define VLV_IIR_RW	_MMIO(VLV_DISPLAY_BASE + 0x2084)
2615 #define VLV_IER		_MMIO(VLV_DISPLAY_BASE + 0x20a0)
2616 #define VLV_IIR		_MMIO(VLV_DISPLAY_BASE + 0x20a4)
2617 #define VLV_IMR		_MMIO(VLV_DISPLAY_BASE + 0x20a8)
2618 #define VLV_ISR		_MMIO(VLV_DISPLAY_BASE + 0x20ac)
2619 #define VLV_PCBR	_MMIO(VLV_DISPLAY_BASE + 0x2120)
2620 #define VLV_PCBR_ADDR_SHIFT	12
2621 
2622 #define   DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */
2623 #define EIR		_MMIO(0x20b0)
2624 #define EMR		_MMIO(0x20b4)
2625 #define ESR		_MMIO(0x20b8)
2626 #define   GM45_ERROR_PAGE_TABLE				(1 << 5)
2627 #define   GM45_ERROR_MEM_PRIV				(1 << 4)
2628 #define   I915_ERROR_PAGE_TABLE				(1 << 4)
2629 #define   GM45_ERROR_CP_PRIV				(1 << 3)
2630 #define   I915_ERROR_MEMORY_REFRESH			(1 << 1)
2631 #define   I915_ERROR_INSTRUCTION			(1 << 0)
2632 #define INSTPM	        _MMIO(0x20c0)
2633 #define   INSTPM_SELF_EN (1 << 12) /* 915GM only */
2634 #define   INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
2635 					will not assert AGPBUSY# and will only
2636 					be delivered when out of C3. */
2637 #define   INSTPM_FORCE_ORDERING				(1 << 7) /* GEN6+ */
2638 #define   INSTPM_TLB_INVALIDATE	(1 << 9)
2639 #define   INSTPM_SYNC_FLUSH	(1 << 5)
2640 #define ACTHD	        _MMIO(0x20c8)
2641 #define MEM_MODE	_MMIO(0x20cc)
2642 #define   MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
2643 #define   MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
2644 #define   MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */
2645 #define FW_BLC		_MMIO(0x20d8)
2646 #define FW_BLC2		_MMIO(0x20dc)
2647 #define FW_BLC_SELF	_MMIO(0x20e0) /* 915+ only */
2648 #define   FW_BLC_SELF_EN_MASK      (1 << 31)
2649 #define   FW_BLC_SELF_FIFO_MASK    (1 << 16) /* 945 only */
2650 #define   FW_BLC_SELF_EN           (1 << 15) /* 945 only */
2651 #define MM_BURST_LENGTH     0x00700000
2652 #define MM_FIFO_WATERMARK   0x0001F000
2653 #define LM_BURST_LENGTH     0x00000700
2654 #define LM_FIFO_WATERMARK   0x0000001F
2655 #define MI_ARB_STATE	_MMIO(0x20e4) /* 915+ only */
2656 
2657 #define MBUS_ABOX_CTL			_MMIO(0x45038)
2658 #define MBUS_ABOX_BW_CREDIT_MASK	(3 << 20)
2659 #define MBUS_ABOX_BW_CREDIT(x)		((x) << 20)
2660 #define MBUS_ABOX_B_CREDIT_MASK		(0xF << 16)
2661 #define MBUS_ABOX_B_CREDIT(x)		((x) << 16)
2662 #define MBUS_ABOX_BT_CREDIT_POOL2_MASK	(0x1F << 8)
2663 #define MBUS_ABOX_BT_CREDIT_POOL2(x)	((x) << 8)
2664 #define MBUS_ABOX_BT_CREDIT_POOL1_MASK	(0x1F << 0)
2665 #define MBUS_ABOX_BT_CREDIT_POOL1(x)	((x) << 0)
2666 
2667 #define _PIPEA_MBUS_DBOX_CTL		0x7003C
2668 #define _PIPEB_MBUS_DBOX_CTL		0x7103C
2669 #define PIPE_MBUS_DBOX_CTL(pipe)	_MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \
2670 						   _PIPEB_MBUS_DBOX_CTL)
2671 #define MBUS_DBOX_BW_CREDIT_MASK	(3 << 14)
2672 #define MBUS_DBOX_BW_CREDIT(x)		((x) << 14)
2673 #define MBUS_DBOX_B_CREDIT_MASK		(0x1F << 8)
2674 #define MBUS_DBOX_B_CREDIT(x)		((x) << 8)
2675 #define MBUS_DBOX_A_CREDIT_MASK		(0xF << 0)
2676 #define MBUS_DBOX_A_CREDIT(x)		((x) << 0)
2677 
2678 #define MBUS_UBOX_CTL			_MMIO(0x4503C)
2679 #define MBUS_BBOX_CTL_S1		_MMIO(0x45040)
2680 #define MBUS_BBOX_CTL_S2		_MMIO(0x45044)
2681 
2682 /* Make render/texture TLB fetches lower priorty than associated data
2683  *   fetches. This is not turned on by default
2684  */
2685 #define   MI_ARB_RENDER_TLB_LOW_PRIORITY	(1 << 15)
2686 
2687 /* Isoch request wait on GTT enable (Display A/B/C streams).
2688  * Make isoch requests stall on the TLB update. May cause
2689  * display underruns (test mode only)
2690  */
2691 #define   MI_ARB_ISOCH_WAIT_GTT			(1 << 14)
2692 
2693 /* Block grant count for isoch requests when block count is
2694  * set to a finite value.
2695  */
2696 #define   MI_ARB_BLOCK_GRANT_MASK		(3 << 12)
2697 #define   MI_ARB_BLOCK_GRANT_8			(0 << 12)	/* for 3 display planes */
2698 #define   MI_ARB_BLOCK_GRANT_4			(1 << 12)	/* for 2 display planes */
2699 #define   MI_ARB_BLOCK_GRANT_2			(2 << 12)	/* for 1 display plane */
2700 #define   MI_ARB_BLOCK_GRANT_0			(3 << 12)	/* don't use */
2701 
2702 /* Enable render writes to complete in C2/C3/C4 power states.
2703  * If this isn't enabled, render writes are prevented in low
2704  * power states. That seems bad to me.
2705  */
2706 #define   MI_ARB_C3_LP_WRITE_ENABLE		(1 << 11)
2707 
2708 /* This acknowledges an async flip immediately instead
2709  * of waiting for 2TLB fetches.
2710  */
2711 #define   MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE	(1 << 10)
2712 
2713 /* Enables non-sequential data reads through arbiter
2714  */
2715 #define   MI_ARB_DUAL_DATA_PHASE_DISABLE	(1 << 9)
2716 
2717 /* Disable FSB snooping of cacheable write cycles from binner/render
2718  * command stream
2719  */
2720 #define   MI_ARB_CACHE_SNOOP_DISABLE		(1 << 8)
2721 
2722 /* Arbiter time slice for non-isoch streams */
2723 #define   MI_ARB_TIME_SLICE_MASK		(7 << 5)
2724 #define   MI_ARB_TIME_SLICE_1			(0 << 5)
2725 #define   MI_ARB_TIME_SLICE_2			(1 << 5)
2726 #define   MI_ARB_TIME_SLICE_4			(2 << 5)
2727 #define   MI_ARB_TIME_SLICE_6			(3 << 5)
2728 #define   MI_ARB_TIME_SLICE_8			(4 << 5)
2729 #define   MI_ARB_TIME_SLICE_10			(5 << 5)
2730 #define   MI_ARB_TIME_SLICE_14			(6 << 5)
2731 #define   MI_ARB_TIME_SLICE_16			(7 << 5)
2732 
2733 /* Low priority grace period page size */
2734 #define   MI_ARB_LOW_PRIORITY_GRACE_4KB		(0 << 4)	/* default */
2735 #define   MI_ARB_LOW_PRIORITY_GRACE_8KB		(1 << 4)
2736 
2737 /* Disable display A/B trickle feed */
2738 #define   MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE	(1 << 2)
2739 
2740 /* Set display plane priority */
2741 #define   MI_ARB_DISPLAY_PRIORITY_A_B		(0 << 0)	/* display A > display B */
2742 #define   MI_ARB_DISPLAY_PRIORITY_B_A		(1 << 0)	/* display B > display A */
2743 
2744 #define MI_STATE	_MMIO(0x20e4) /* gen2 only */
2745 #define   MI_AGPBUSY_INT_EN			(1 << 1) /* 85x only */
2746 #define   MI_AGPBUSY_830_MODE			(1 << 0) /* 85x only */
2747 
2748 #define CACHE_MODE_0	_MMIO(0x2120) /* 915+ only */
2749 #define   CM0_PIPELINED_RENDER_FLUSH_DISABLE (1 << 8)
2750 #define   CM0_IZ_OPT_DISABLE      (1 << 6)
2751 #define   CM0_ZR_OPT_DISABLE      (1 << 5)
2752 #define	  CM0_STC_EVICT_DISABLE_LRA_SNB	(1 << 5)
2753 #define   CM0_DEPTH_EVICT_DISABLE (1 << 4)
2754 #define   CM0_COLOR_EVICT_DISABLE (1 << 3)
2755 #define   CM0_DEPTH_WRITE_DISABLE (1 << 1)
2756 #define   CM0_RC_OP_FLUSH_DISABLE (1 << 0)
2757 #define GFX_FLSH_CNTL	_MMIO(0x2170) /* 915+ only */
2758 #define GFX_FLSH_CNTL_GEN6	_MMIO(0x101008)
2759 #define   GFX_FLSH_CNTL_EN	(1 << 0)
2760 #define ECOSKPD		_MMIO(0x21d0)
2761 #define   ECO_GATING_CX_ONLY	(1 << 3)
2762 #define   ECO_FLIP_DONE		(1 << 0)
2763 
2764 #define CACHE_MODE_0_GEN7	_MMIO(0x7000) /* IVB+ */
2765 #define RC_OP_FLUSH_ENABLE (1 << 0)
2766 #define   HIZ_RAW_STALL_OPT_DISABLE (1 << 2)
2767 #define CACHE_MODE_1		_MMIO(0x7004) /* IVB+ */
2768 #define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE	(1 << 6)
2769 #define   GEN8_4x4_STC_OPTIMIZATION_DISABLE	(1 << 6)
2770 #define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE	(1 << 1)
2771 
2772 #define GEN6_BLITTER_ECOSKPD	_MMIO(0x221d0)
2773 #define   GEN6_BLITTER_LOCK_SHIFT			16
2774 #define   GEN6_BLITTER_FBC_NOTIFY			(1 << 3)
2775 
2776 #define GEN6_RC_SLEEP_PSMI_CONTROL	_MMIO(0x2050)
2777 #define   GEN6_PSMI_SLEEP_MSG_DISABLE	(1 << 0)
2778 #define   GEN8_RC_SEMA_IDLE_MSG_DISABLE	(1 << 12)
2779 #define   GEN8_FF_DOP_CLOCK_GATE_DISABLE	(1 << 10)
2780 
2781 #define GEN6_RCS_PWR_FSM _MMIO(0x22ac)
2782 #define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
2783 
2784 /* Fuse readout registers for GT */
2785 #define HSW_PAVP_FUSE1			_MMIO(0x911C)
2786 #define   HSW_F1_EU_DIS_SHIFT		16
2787 #define   HSW_F1_EU_DIS_MASK		(0x3 << HSW_F1_EU_DIS_SHIFT)
2788 #define   HSW_F1_EU_DIS_10EUS		0
2789 #define   HSW_F1_EU_DIS_8EUS		1
2790 #define   HSW_F1_EU_DIS_6EUS		2
2791 
2792 #define CHV_FUSE_GT			_MMIO(VLV_DISPLAY_BASE + 0x2168)
2793 #define   CHV_FGT_DISABLE_SS0		(1 << 10)
2794 #define   CHV_FGT_DISABLE_SS1		(1 << 11)
2795 #define   CHV_FGT_EU_DIS_SS0_R0_SHIFT	16
2796 #define   CHV_FGT_EU_DIS_SS0_R0_MASK	(0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
2797 #define   CHV_FGT_EU_DIS_SS0_R1_SHIFT	20
2798 #define   CHV_FGT_EU_DIS_SS0_R1_MASK	(0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
2799 #define   CHV_FGT_EU_DIS_SS1_R0_SHIFT	24
2800 #define   CHV_FGT_EU_DIS_SS1_R0_MASK	(0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
2801 #define   CHV_FGT_EU_DIS_SS1_R1_SHIFT	28
2802 #define   CHV_FGT_EU_DIS_SS1_R1_MASK	(0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
2803 
2804 #define GEN8_FUSE2			_MMIO(0x9120)
2805 #define   GEN8_F2_SS_DIS_SHIFT		21
2806 #define   GEN8_F2_SS_DIS_MASK		(0x7 << GEN8_F2_SS_DIS_SHIFT)
2807 #define   GEN8_F2_S_ENA_SHIFT		25
2808 #define   GEN8_F2_S_ENA_MASK		(0x7 << GEN8_F2_S_ENA_SHIFT)
2809 
2810 #define   GEN9_F2_SS_DIS_SHIFT		20
2811 #define   GEN9_F2_SS_DIS_MASK		(0xf << GEN9_F2_SS_DIS_SHIFT)
2812 
2813 #define   GEN10_F2_S_ENA_SHIFT		22
2814 #define   GEN10_F2_S_ENA_MASK		(0x3f << GEN10_F2_S_ENA_SHIFT)
2815 #define   GEN10_F2_SS_DIS_SHIFT		18
2816 #define   GEN10_F2_SS_DIS_MASK		(0xf << GEN10_F2_SS_DIS_SHIFT)
2817 
2818 #define	GEN10_MIRROR_FUSE3		_MMIO(0x9118)
2819 #define GEN10_L3BANK_PAIR_COUNT     4
2820 #define GEN10_L3BANK_MASK   0x0F
2821 
2822 #define GEN8_EU_DISABLE0		_MMIO(0x9134)
2823 #define   GEN8_EU_DIS0_S0_MASK		0xffffff
2824 #define   GEN8_EU_DIS0_S1_SHIFT		24
2825 #define   GEN8_EU_DIS0_S1_MASK		(0xff << GEN8_EU_DIS0_S1_SHIFT)
2826 
2827 #define GEN8_EU_DISABLE1		_MMIO(0x9138)
2828 #define   GEN8_EU_DIS1_S1_MASK		0xffff
2829 #define   GEN8_EU_DIS1_S2_SHIFT		16
2830 #define   GEN8_EU_DIS1_S2_MASK		(0xffff << GEN8_EU_DIS1_S2_SHIFT)
2831 
2832 #define GEN8_EU_DISABLE2		_MMIO(0x913c)
2833 #define   GEN8_EU_DIS2_S2_MASK		0xff
2834 
2835 #define GEN9_EU_DISABLE(slice)		_MMIO(0x9134 + (slice) * 0x4)
2836 
2837 #define GEN10_EU_DISABLE3		_MMIO(0x9140)
2838 #define   GEN10_EU_DIS_SS_MASK		0xff
2839 
2840 #define GEN11_GT_VEBOX_VDBOX_DISABLE	_MMIO(0x9140)
2841 #define   GEN11_GT_VDBOX_DISABLE_MASK	0xff
2842 #define   GEN11_GT_VEBOX_DISABLE_SHIFT	16
2843 #define   GEN11_GT_VEBOX_DISABLE_MASK	(0xff << GEN11_GT_VEBOX_DISABLE_SHIFT)
2844 
2845 #define GEN11_EU_DISABLE _MMIO(0x9134)
2846 #define GEN11_EU_DIS_MASK 0xFF
2847 
2848 #define GEN11_GT_SLICE_ENABLE _MMIO(0x9138)
2849 #define GEN11_GT_S_ENA_MASK 0xFF
2850 
2851 #define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C)
2852 
2853 #define GEN6_BSD_SLEEP_PSMI_CONTROL	_MMIO(0x12050)
2854 #define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)
2855 #define   GEN6_BSD_SLEEP_FLUSH_DISABLE	(1 << 2)
2856 #define   GEN6_BSD_SLEEP_INDICATOR	(1 << 3)
2857 #define   GEN6_BSD_GO_INDICATOR		(1 << 4)
2858 
2859 /* On modern GEN architectures interrupt control consists of two sets
2860  * of registers. The first set pertains to the ring generating the
2861  * interrupt. The second control is for the functional block generating the
2862  * interrupt. These are PM, GT, DE, etc.
2863  *
2864  * Luckily *knocks on wood* all the ring interrupt bits match up with the
2865  * GT interrupt bits, so we don't need to duplicate the defines.
2866  *
2867  * These defines should cover us well from SNB->HSW with minor exceptions
2868  * it can also work on ILK.
2869  */
2870 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT		(1 << 26)
2871 #define GT_BLT_CS_ERROR_INTERRUPT		(1 << 25)
2872 #define GT_BLT_USER_INTERRUPT			(1 << 22)
2873 #define GT_BSD_CS_ERROR_INTERRUPT		(1 << 15)
2874 #define GT_BSD_USER_INTERRUPT			(1 << 12)
2875 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1	(1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
2876 #define GT_CONTEXT_SWITCH_INTERRUPT		(1 <<  8)
2877 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT	(1 <<  5) /* !snb */
2878 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT	(1 <<  4)
2879 #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT	(1 <<  3)
2880 #define GT_RENDER_SYNC_STATUS_INTERRUPT		(1 <<  2)
2881 #define GT_RENDER_DEBUG_INTERRUPT		(1 <<  1)
2882 #define GT_RENDER_USER_INTERRUPT		(1 <<  0)
2883 
2884 #define PM_VEBOX_CS_ERROR_INTERRUPT		(1 << 12) /* hsw+ */
2885 #define PM_VEBOX_USER_INTERRUPT			(1 << 10) /* hsw+ */
2886 
2887 #define GT_PARITY_ERROR(dev_priv) \
2888 	(GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
2889 	 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
2890 
2891 /* These are all the "old" interrupts */
2892 #define ILK_BSD_USER_INTERRUPT				(1 << 5)
2893 
2894 #define I915_PM_INTERRUPT				(1 << 31)
2895 #define I915_ISP_INTERRUPT				(1 << 22)
2896 #define I915_LPE_PIPE_B_INTERRUPT			(1 << 21)
2897 #define I915_LPE_PIPE_A_INTERRUPT			(1 << 20)
2898 #define I915_MIPIC_INTERRUPT				(1 << 19)
2899 #define I915_MIPIA_INTERRUPT				(1 << 18)
2900 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT		(1 << 18)
2901 #define I915_DISPLAY_PORT_INTERRUPT			(1 << 17)
2902 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT		(1 << 16)
2903 #define I915_MASTER_ERROR_INTERRUPT			(1 << 15)
2904 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT		(1 << 14)
2905 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT	(1 << 14) /* p-state */
2906 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT		(1 << 13)
2907 #define I915_HWB_OOM_INTERRUPT				(1 << 13)
2908 #define I915_LPE_PIPE_C_INTERRUPT			(1 << 12)
2909 #define I915_SYNC_STATUS_INTERRUPT			(1 << 12)
2910 #define I915_MISC_INTERRUPT				(1 << 11)
2911 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT	(1 << 11)
2912 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT		(1 << 10)
2913 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT	(1 << 10)
2914 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT		(1 << 9)
2915 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT	(1 << 9)
2916 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT		(1 << 8)
2917 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT	(1 << 8)
2918 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT		(1 << 7)
2919 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT		(1 << 6)
2920 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT		(1 << 5)
2921 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT		(1 << 4)
2922 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT		(1 << 3)
2923 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT		(1 << 2)
2924 #define I915_DEBUG_INTERRUPT				(1 << 2)
2925 #define I915_WINVALID_INTERRUPT				(1 << 1)
2926 #define I915_USER_INTERRUPT				(1 << 1)
2927 #define I915_ASLE_INTERRUPT				(1 << 0)
2928 #define I915_BSD_USER_INTERRUPT				(1 << 25)
2929 
2930 #define I915_HDMI_LPE_AUDIO_BASE	(VLV_DISPLAY_BASE + 0x65000)
2931 #define I915_HDMI_LPE_AUDIO_SIZE	0x1000
2932 
2933 /* DisplayPort Audio w/ LPE */
2934 #define VLV_AUD_CHICKEN_BIT_REG		_MMIO(VLV_DISPLAY_BASE + 0x62F38)
2935 #define VLV_CHICKEN_BIT_DBG_ENABLE	(1 << 0)
2936 
2937 #define _VLV_AUD_PORT_EN_B_DBG		(VLV_DISPLAY_BASE + 0x62F20)
2938 #define _VLV_AUD_PORT_EN_C_DBG		(VLV_DISPLAY_BASE + 0x62F30)
2939 #define _VLV_AUD_PORT_EN_D_DBG		(VLV_DISPLAY_BASE + 0x62F34)
2940 #define VLV_AUD_PORT_EN_DBG(port)	_MMIO_PORT3((port) - PORT_B,	   \
2941 						    _VLV_AUD_PORT_EN_B_DBG, \
2942 						    _VLV_AUD_PORT_EN_C_DBG, \
2943 						    _VLV_AUD_PORT_EN_D_DBG)
2944 #define VLV_AMP_MUTE		        (1 << 1)
2945 
2946 #define GEN6_BSD_RNCID			_MMIO(0x12198)
2947 
2948 #define GEN7_FF_THREAD_MODE		_MMIO(0x20a0)
2949 #define   GEN7_FF_SCHED_MASK		0x0077070
2950 #define   GEN8_FF_DS_REF_CNT_FFME	(1 << 19)
2951 #define   GEN7_FF_TS_SCHED_HS1		(0x5 << 16)
2952 #define   GEN7_FF_TS_SCHED_HS0		(0x3 << 16)
2953 #define   GEN7_FF_TS_SCHED_LOAD_BALANCE	(0x1 << 16)
2954 #define   GEN7_FF_TS_SCHED_HW		(0x0 << 16) /* Default */
2955 #define   GEN7_FF_VS_REF_CNT_FFME	(1 << 15)
2956 #define   GEN7_FF_VS_SCHED_HS1		(0x5 << 12)
2957 #define   GEN7_FF_VS_SCHED_HS0		(0x3 << 12)
2958 #define   GEN7_FF_VS_SCHED_LOAD_BALANCE	(0x1 << 12) /* Default */
2959 #define   GEN7_FF_VS_SCHED_HW		(0x0 << 12)
2960 #define   GEN7_FF_DS_SCHED_HS1		(0x5 << 4)
2961 #define   GEN7_FF_DS_SCHED_HS0		(0x3 << 4)
2962 #define   GEN7_FF_DS_SCHED_LOAD_BALANCE	(0x1 << 4)  /* Default */
2963 #define   GEN7_FF_DS_SCHED_HW		(0x0 << 4)
2964 
2965 /*
2966  * Framebuffer compression (915+ only)
2967  */
2968 
2969 #define FBC_CFB_BASE		_MMIO(0x3200) /* 4k page aligned */
2970 #define FBC_LL_BASE		_MMIO(0x3204) /* 4k page aligned */
2971 #define FBC_CONTROL		_MMIO(0x3208)
2972 #define   FBC_CTL_EN		(1 << 31)
2973 #define   FBC_CTL_PERIODIC	(1 << 30)
2974 #define   FBC_CTL_INTERVAL_SHIFT (16)
2975 #define   FBC_CTL_UNCOMPRESSIBLE (1 << 14)
2976 #define   FBC_CTL_C3_IDLE	(1 << 13)
2977 #define   FBC_CTL_STRIDE_SHIFT	(5)
2978 #define   FBC_CTL_FENCENO_SHIFT	(0)
2979 #define FBC_COMMAND		_MMIO(0x320c)
2980 #define   FBC_CMD_COMPRESS	(1 << 0)
2981 #define FBC_STATUS		_MMIO(0x3210)
2982 #define   FBC_STAT_COMPRESSING	(1 << 31)
2983 #define   FBC_STAT_COMPRESSED	(1 << 30)
2984 #define   FBC_STAT_MODIFIED	(1 << 29)
2985 #define   FBC_STAT_CURRENT_LINE_SHIFT	(0)
2986 #define FBC_CONTROL2		_MMIO(0x3214)
2987 #define   FBC_CTL_FENCE_DBL	(0 << 4)
2988 #define   FBC_CTL_IDLE_IMM	(0 << 2)
2989 #define   FBC_CTL_IDLE_FULL	(1 << 2)
2990 #define   FBC_CTL_IDLE_LINE	(2 << 2)
2991 #define   FBC_CTL_IDLE_DEBUG	(3 << 2)
2992 #define   FBC_CTL_CPU_FENCE	(1 << 1)
2993 #define   FBC_CTL_PLANE(plane)	((plane) << 0)
2994 #define FBC_FENCE_OFF		_MMIO(0x3218) /* BSpec typo has 321Bh */
2995 #define FBC_TAG(i)		_MMIO(0x3300 + (i) * 4)
2996 
2997 #define FBC_LL_SIZE		(1536)
2998 
2999 #define FBC_LLC_READ_CTRL	_MMIO(0x9044)
3000 #define   FBC_LLC_FULLY_OPEN	(1 << 30)
3001 
3002 /* Framebuffer compression for GM45+ */
3003 #define DPFC_CB_BASE		_MMIO(0x3200)
3004 #define DPFC_CONTROL		_MMIO(0x3208)
3005 #define   DPFC_CTL_EN		(1 << 31)
3006 #define   DPFC_CTL_PLANE(plane)	((plane) << 30)
3007 #define   IVB_DPFC_CTL_PLANE(plane)	((plane) << 29)
3008 #define   DPFC_CTL_FENCE_EN	(1 << 29)
3009 #define   IVB_DPFC_CTL_FENCE_EN	(1 << 28)
3010 #define   DPFC_CTL_PERSISTENT_MODE	(1 << 25)
3011 #define   DPFC_SR_EN		(1 << 10)
3012 #define   DPFC_CTL_LIMIT_1X	(0 << 6)
3013 #define   DPFC_CTL_LIMIT_2X	(1 << 6)
3014 #define   DPFC_CTL_LIMIT_4X	(2 << 6)
3015 #define DPFC_RECOMP_CTL		_MMIO(0x320c)
3016 #define   DPFC_RECOMP_STALL_EN	(1 << 27)
3017 #define   DPFC_RECOMP_STALL_WM_SHIFT (16)
3018 #define   DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
3019 #define   DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
3020 #define   DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
3021 #define DPFC_STATUS		_MMIO(0x3210)
3022 #define   DPFC_INVAL_SEG_SHIFT  (16)
3023 #define   DPFC_INVAL_SEG_MASK	(0x07ff0000)
3024 #define   DPFC_COMP_SEG_SHIFT	(0)
3025 #define   DPFC_COMP_SEG_MASK	(0x000007ff)
3026 #define DPFC_STATUS2		_MMIO(0x3214)
3027 #define DPFC_FENCE_YOFF		_MMIO(0x3218)
3028 #define DPFC_CHICKEN		_MMIO(0x3224)
3029 #define   DPFC_HT_MODIFY	(1 << 31)
3030 
3031 /* Framebuffer compression for Ironlake */
3032 #define ILK_DPFC_CB_BASE	_MMIO(0x43200)
3033 #define ILK_DPFC_CONTROL	_MMIO(0x43208)
3034 #define   FBC_CTL_FALSE_COLOR	(1 << 10)
3035 /* The bit 28-8 is reserved */
3036 #define   DPFC_RESERVED		(0x1FFFFF00)
3037 #define ILK_DPFC_RECOMP_CTL	_MMIO(0x4320c)
3038 #define ILK_DPFC_STATUS		_MMIO(0x43210)
3039 #define  ILK_DPFC_COMP_SEG_MASK	0x7ff
3040 #define IVB_FBC_STATUS2		_MMIO(0x43214)
3041 #define  IVB_FBC_COMP_SEG_MASK	0x7ff
3042 #define  BDW_FBC_COMP_SEG_MASK	0xfff
3043 #define ILK_DPFC_FENCE_YOFF	_MMIO(0x43218)
3044 #define ILK_DPFC_CHICKEN	_MMIO(0x43224)
3045 #define   ILK_DPFC_DISABLE_DUMMY0 (1 << 8)
3046 #define   ILK_DPFC_NUKE_ON_ANY_MODIFICATION	(1 << 23)
3047 #define ILK_FBC_RT_BASE		_MMIO(0x2128)
3048 #define   ILK_FBC_RT_VALID	(1 << 0)
3049 #define   SNB_FBC_FRONT_BUFFER	(1 << 1)
3050 
3051 #define ILK_DISPLAY_CHICKEN1	_MMIO(0x42000)
3052 #define   ILK_FBCQ_DIS		(1 << 22)
3053 #define	  ILK_PABSTRETCH_DIS	(1 << 21)
3054 
3055 
3056 /*
3057  * Framebuffer compression for Sandybridge
3058  *
3059  * The following two registers are of type GTTMMADR
3060  */
3061 #define SNB_DPFC_CTL_SA		_MMIO(0x100100)
3062 #define   SNB_CPU_FENCE_ENABLE	(1 << 29)
3063 #define DPFC_CPU_FENCE_OFFSET	_MMIO(0x100104)
3064 
3065 /* Framebuffer compression for Ivybridge */
3066 #define IVB_FBC_RT_BASE			_MMIO(0x7020)
3067 
3068 #define IPS_CTL		_MMIO(0x43408)
3069 #define   IPS_ENABLE	(1 << 31)
3070 
3071 #define MSG_FBC_REND_STATE	_MMIO(0x50380)
3072 #define   FBC_REND_NUKE		(1 << 2)
3073 #define   FBC_REND_CACHE_CLEAN	(1 << 1)
3074 
3075 /*
3076  * GPIO regs
3077  */
3078 #define GPIO(gpio)		_MMIO(dev_priv->gpio_mmio_base + 0x5010 + \
3079 				      4 * (gpio))
3080 
3081 # define GPIO_CLOCK_DIR_MASK		(1 << 0)
3082 # define GPIO_CLOCK_DIR_IN		(0 << 1)
3083 # define GPIO_CLOCK_DIR_OUT		(1 << 1)
3084 # define GPIO_CLOCK_VAL_MASK		(1 << 2)
3085 # define GPIO_CLOCK_VAL_OUT		(1 << 3)
3086 # define GPIO_CLOCK_VAL_IN		(1 << 4)
3087 # define GPIO_CLOCK_PULLUP_DISABLE	(1 << 5)
3088 # define GPIO_DATA_DIR_MASK		(1 << 8)
3089 # define GPIO_DATA_DIR_IN		(0 << 9)
3090 # define GPIO_DATA_DIR_OUT		(1 << 9)
3091 # define GPIO_DATA_VAL_MASK		(1 << 10)
3092 # define GPIO_DATA_VAL_OUT		(1 << 11)
3093 # define GPIO_DATA_VAL_IN		(1 << 12)
3094 # define GPIO_DATA_PULLUP_DISABLE	(1 << 13)
3095 
3096 #define GMBUS0			_MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
3097 #define   GMBUS_AKSV_SELECT	(1 << 11)
3098 #define   GMBUS_RATE_100KHZ	(0 << 8)
3099 #define   GMBUS_RATE_50KHZ	(1 << 8)
3100 #define   GMBUS_RATE_400KHZ	(2 << 8) /* reserved on Pineview */
3101 #define   GMBUS_RATE_1MHZ	(3 << 8) /* reserved on Pineview */
3102 #define   GMBUS_HOLD_EXT	(1 << 7) /* 300ns hold time, rsvd on Pineview */
3103 #define   GMBUS_BYTE_CNT_OVERRIDE (1 << 6)
3104 #define   GMBUS_PIN_DISABLED	0
3105 #define   GMBUS_PIN_SSC		1
3106 #define   GMBUS_PIN_VGADDC	2
3107 #define   GMBUS_PIN_PANEL	3
3108 #define   GMBUS_PIN_DPD_CHV	3 /* HDMID_CHV */
3109 #define   GMBUS_PIN_DPC		4 /* HDMIC */
3110 #define   GMBUS_PIN_DPB		5 /* SDVO, HDMIB */
3111 #define   GMBUS_PIN_DPD		6 /* HDMID */
3112 #define   GMBUS_PIN_RESERVED	7 /* 7 reserved */
3113 #define   GMBUS_PIN_1_BXT	1 /* BXT+ (atom) and CNP+ (big core) */
3114 #define   GMBUS_PIN_2_BXT	2
3115 #define   GMBUS_PIN_3_BXT	3
3116 #define   GMBUS_PIN_4_CNP	4
3117 #define   GMBUS_PIN_9_TC1_ICP	9
3118 #define   GMBUS_PIN_10_TC2_ICP	10
3119 #define   GMBUS_PIN_11_TC3_ICP	11
3120 #define   GMBUS_PIN_12_TC4_ICP	12
3121 
3122 #define   GMBUS_NUM_PINS	13 /* including 0 */
3123 #define GMBUS1			_MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
3124 #define   GMBUS_SW_CLR_INT	(1 << 31)
3125 #define   GMBUS_SW_RDY		(1 << 30)
3126 #define   GMBUS_ENT		(1 << 29) /* enable timeout */
3127 #define   GMBUS_CYCLE_NONE	(0 << 25)
3128 #define   GMBUS_CYCLE_WAIT	(1 << 25)
3129 #define   GMBUS_CYCLE_INDEX	(2 << 25)
3130 #define   GMBUS_CYCLE_STOP	(4 << 25)
3131 #define   GMBUS_BYTE_COUNT_SHIFT 16
3132 #define   GMBUS_BYTE_COUNT_MAX   256U
3133 #define   GEN9_GMBUS_BYTE_COUNT_MAX 511U
3134 #define   GMBUS_SLAVE_INDEX_SHIFT 8
3135 #define   GMBUS_SLAVE_ADDR_SHIFT 1
3136 #define   GMBUS_SLAVE_READ	(1 << 0)
3137 #define   GMBUS_SLAVE_WRITE	(0 << 0)
3138 #define GMBUS2			_MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */
3139 #define   GMBUS_INUSE		(1 << 15)
3140 #define   GMBUS_HW_WAIT_PHASE	(1 << 14)
3141 #define   GMBUS_STALL_TIMEOUT	(1 << 13)
3142 #define   GMBUS_INT		(1 << 12)
3143 #define   GMBUS_HW_RDY		(1 << 11)
3144 #define   GMBUS_SATOER		(1 << 10)
3145 #define   GMBUS_ACTIVE		(1 << 9)
3146 #define GMBUS3			_MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
3147 #define GMBUS4			_MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
3148 #define   GMBUS_SLAVE_TIMEOUT_EN (1 << 4)
3149 #define   GMBUS_NAK_EN		(1 << 3)
3150 #define   GMBUS_IDLE_EN		(1 << 2)
3151 #define   GMBUS_HW_WAIT_EN	(1 << 1)
3152 #define   GMBUS_HW_RDY_EN	(1 << 0)
3153 #define GMBUS5			_MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
3154 #define   GMBUS_2BYTE_INDEX_EN	(1 << 31)
3155 
3156 /*
3157  * Clock control & power management
3158  */
3159 #define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
3160 #define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
3161 #define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030)
3162 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
3163 
3164 #define VGA0	_MMIO(0x6000)
3165 #define VGA1	_MMIO(0x6004)
3166 #define VGA_PD	_MMIO(0x6010)
3167 #define   VGA0_PD_P2_DIV_4	(1 << 7)
3168 #define   VGA0_PD_P1_DIV_2	(1 << 5)
3169 #define   VGA0_PD_P1_SHIFT	0
3170 #define   VGA0_PD_P1_MASK	(0x1f << 0)
3171 #define   VGA1_PD_P2_DIV_4	(1 << 15)
3172 #define   VGA1_PD_P1_DIV_2	(1 << 13)
3173 #define   VGA1_PD_P1_SHIFT	8
3174 #define   VGA1_PD_P1_MASK	(0x1f << 8)
3175 #define   DPLL_VCO_ENABLE		(1 << 31)
3176 #define   DPLL_SDVO_HIGH_SPEED		(1 << 30)
3177 #define   DPLL_DVO_2X_MODE		(1 << 30)
3178 #define   DPLL_EXT_BUFFER_ENABLE_VLV	(1 << 30)
3179 #define   DPLL_SYNCLOCK_ENABLE		(1 << 29)
3180 #define   DPLL_REF_CLK_ENABLE_VLV	(1 << 29)
3181 #define   DPLL_VGA_MODE_DIS		(1 << 28)
3182 #define   DPLLB_MODE_DAC_SERIAL		(1 << 26) /* i915 */
3183 #define   DPLLB_MODE_LVDS		(2 << 26) /* i915 */
3184 #define   DPLL_MODE_MASK		(3 << 26)
3185 #define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
3186 #define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
3187 #define   DPLLB_LVDS_P2_CLOCK_DIV_14	(0 << 24) /* i915 */
3188 #define   DPLLB_LVDS_P2_CLOCK_DIV_7	(1 << 24) /* i915 */
3189 #define   DPLL_P2_CLOCK_DIV_MASK	0x03000000 /* i915 */
3190 #define   DPLL_FPA01_P1_POST_DIV_MASK	0x00ff0000 /* i915 */
3191 #define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW	0x00ff8000 /* Pineview */
3192 #define   DPLL_LOCK_VLV			(1 << 15)
3193 #define   DPLL_INTEGRATED_CRI_CLK_VLV	(1 << 14)
3194 #define   DPLL_INTEGRATED_REF_CLK_VLV	(1 << 13)
3195 #define   DPLL_SSC_REF_CLK_CHV		(1 << 13)
3196 #define   DPLL_PORTC_READY_MASK		(0xf << 4)
3197 #define   DPLL_PORTB_READY_MASK		(0xf)
3198 
3199 #define   DPLL_FPA01_P1_POST_DIV_MASK_I830	0x001f0000
3200 
3201 /* Additional CHV pll/phy registers */
3202 #define DPIO_PHY_STATUS			_MMIO(VLV_DISPLAY_BASE + 0x6240)
3203 #define   DPLL_PORTD_READY_MASK		(0xf)
3204 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
3205 #define   PHY_CH_POWER_DOWN_OVRD_EN(phy, ch)	(1 << (2 * (phy) + (ch) + 27))
3206 #define   PHY_LDO_DELAY_0NS			0x0
3207 #define   PHY_LDO_DELAY_200NS			0x1
3208 #define   PHY_LDO_DELAY_600NS			0x2
3209 #define   PHY_LDO_SEQ_DELAY(delay, phy)		((delay) << (2 * (phy) + 23))
3210 #define   PHY_CH_POWER_DOWN_OVRD(mask, phy, ch)	((mask) << (8 * (phy) + 4 * (ch) + 11))
3211 #define   PHY_CH_SU_PSR				0x1
3212 #define   PHY_CH_DEEP_PSR			0x7
3213 #define   PHY_CH_POWER_MODE(mode, phy, ch)	((mode) << (6 * (phy) + 3 * (ch) + 2))
3214 #define   PHY_COM_LANE_RESET_DEASSERT(phy)	(1 << (phy))
3215 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
3216 #define   PHY_POWERGOOD(phy)	(((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30))
3217 #define   PHY_STATUS_CMN_LDO(phy, ch)                   (1 << (6 - (6 * (phy) + 3 * (ch))))
3218 #define   PHY_STATUS_SPLINE_LDO(phy, ch, spline)        (1 << (8 - (6 * (phy) + 3 * (ch) + (spline))))
3219 
3220 /*
3221  * The i830 generation, in LVDS mode, defines P1 as the bit number set within
3222  * this field (only one bit may be set).
3223  */
3224 #define   DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS	0x003f0000
3225 #define   DPLL_FPA01_P1_POST_DIV_SHIFT	16
3226 #define   DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
3227 /* i830, required in DVO non-gang */
3228 #define   PLL_P2_DIVIDE_BY_4		(1 << 23)
3229 #define   PLL_P1_DIVIDE_BY_TWO		(1 << 21) /* i830 */
3230 #define   PLL_REF_INPUT_DREFCLK		(0 << 13)
3231 #define   PLL_REF_INPUT_TVCLKINA	(1 << 13) /* i830 */
3232 #define   PLL_REF_INPUT_TVCLKINBC	(2 << 13) /* SDVO TVCLKIN */
3233 #define   PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
3234 #define   PLL_REF_INPUT_MASK		(3 << 13)
3235 #define   PLL_LOAD_PULSE_PHASE_SHIFT		9
3236 /* Ironlake */
3237 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT     9
3238 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK      (7 << 9)
3239 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x)	(((x) - 1) << 9)
3240 # define DPLL_FPA1_P1_POST_DIV_SHIFT            0
3241 # define DPLL_FPA1_P1_POST_DIV_MASK             0xff
3242 
3243 /*
3244  * Parallel to Serial Load Pulse phase selection.
3245  * Selects the phase for the 10X DPLL clock for the PCIe
3246  * digital display port. The range is 4 to 13; 10 or more
3247  * is just a flip delay. The default is 6
3248  */
3249 #define   PLL_LOAD_PULSE_PHASE_MASK		(0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
3250 #define   DISPLAY_RATE_SELECT_FPA1		(1 << 8)
3251 /*
3252  * SDVO multiplier for 945G/GM. Not used on 965.
3253  */
3254 #define   SDVO_MULTIPLIER_MASK			0x000000ff
3255 #define   SDVO_MULTIPLIER_SHIFT_HIRES		4
3256 #define   SDVO_MULTIPLIER_SHIFT_VGA		0
3257 
3258 #define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
3259 #define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
3260 #define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c)
3261 #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
3262 
3263 /*
3264  * UDI pixel divider, controlling how many pixels are stuffed into a packet.
3265  *
3266  * Value is pixels minus 1.  Must be set to 1 pixel for SDVO.
3267  */
3268 #define   DPLL_MD_UDI_DIVIDER_MASK		0x3f000000
3269 #define   DPLL_MD_UDI_DIVIDER_SHIFT		24
3270 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
3271 #define   DPLL_MD_VGA_UDI_DIVIDER_MASK		0x003f0000
3272 #define   DPLL_MD_VGA_UDI_DIVIDER_SHIFT		16
3273 /*
3274  * SDVO/UDI pixel multiplier.
3275  *
3276  * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
3277  * clock rate is 10 times the DPLL clock.  At low resolution/refresh rate
3278  * modes, the bus rate would be below the limits, so SDVO allows for stuffing
3279  * dummy bytes in the datastream at an increased clock rate, with both sides of
3280  * the link knowing how many bytes are fill.
3281  *
3282  * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
3283  * rate to 130Mhz to get a bus rate of 1.30Ghz.  The DPLL clock rate would be
3284  * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
3285  * through an SDVO command.
3286  *
3287  * This register field has values of multiplication factor minus 1, with
3288  * a maximum multiplier of 5 for SDVO.
3289  */
3290 #define   DPLL_MD_UDI_MULTIPLIER_MASK		0x00003f00
3291 #define   DPLL_MD_UDI_MULTIPLIER_SHIFT		8
3292 /*
3293  * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
3294  * This best be set to the default value (3) or the CRT won't work. No,
3295  * I don't entirely understand what this does...
3296  */
3297 #define   DPLL_MD_VGA_UDI_MULTIPLIER_MASK	0x0000003f
3298 #define   DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT	0
3299 
3300 #define RAWCLK_FREQ_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6024)
3301 
3302 #define _FPA0	0x6040
3303 #define _FPA1	0x6044
3304 #define _FPB0	0x6048
3305 #define _FPB1	0x604c
3306 #define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0)
3307 #define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1)
3308 #define   FP_N_DIV_MASK		0x003f0000
3309 #define   FP_N_PINEVIEW_DIV_MASK	0x00ff0000
3310 #define   FP_N_DIV_SHIFT		16
3311 #define   FP_M1_DIV_MASK	0x00003f00
3312 #define   FP_M1_DIV_SHIFT		 8
3313 #define   FP_M2_DIV_MASK	0x0000003f
3314 #define   FP_M2_PINEVIEW_DIV_MASK	0x000000ff
3315 #define   FP_M2_DIV_SHIFT		 0
3316 #define DPLL_TEST	_MMIO(0x606c)
3317 #define   DPLLB_TEST_SDVO_DIV_1		(0 << 22)
3318 #define   DPLLB_TEST_SDVO_DIV_2		(1 << 22)
3319 #define   DPLLB_TEST_SDVO_DIV_4		(2 << 22)
3320 #define   DPLLB_TEST_SDVO_DIV_MASK	(3 << 22)
3321 #define   DPLLB_TEST_N_BYPASS		(1 << 19)
3322 #define   DPLLB_TEST_M_BYPASS		(1 << 18)
3323 #define   DPLLB_INPUT_BUFFER_ENABLE	(1 << 16)
3324 #define   DPLLA_TEST_N_BYPASS		(1 << 3)
3325 #define   DPLLA_TEST_M_BYPASS		(1 << 2)
3326 #define   DPLLA_INPUT_BUFFER_ENABLE	(1 << 0)
3327 #define D_STATE		_MMIO(0x6104)
3328 #define  DSTATE_GFX_RESET_I830			(1 << 6)
3329 #define  DSTATE_PLL_D3_OFF			(1 << 3)
3330 #define  DSTATE_GFX_CLOCK_GATING		(1 << 1)
3331 #define  DSTATE_DOT_CLOCK_GATING		(1 << 0)
3332 #define DSPCLK_GATE_D	_MMIO(dev_priv->info.display_mmio_offset + 0x6200)
3333 # define DPUNIT_B_CLOCK_GATE_DISABLE		(1 << 30) /* 965 */
3334 # define VSUNIT_CLOCK_GATE_DISABLE		(1 << 29) /* 965 */
3335 # define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* 965 */
3336 # define VRDUNIT_CLOCK_GATE_DISABLE		(1 << 27) /* 965 */
3337 # define AUDUNIT_CLOCK_GATE_DISABLE		(1 << 26) /* 965 */
3338 # define DPUNIT_A_CLOCK_GATE_DISABLE		(1 << 25) /* 965 */
3339 # define DPCUNIT_CLOCK_GATE_DISABLE		(1 << 24) /* 965 */
3340 # define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE	(1 << 24) /* pnv */
3341 # define TVRUNIT_CLOCK_GATE_DISABLE		(1 << 23) /* 915-945 */
3342 # define TVCUNIT_CLOCK_GATE_DISABLE		(1 << 22) /* 915-945 */
3343 # define TVFUNIT_CLOCK_GATE_DISABLE		(1 << 21) /* 915-945 */
3344 # define TVEUNIT_CLOCK_GATE_DISABLE		(1 << 20) /* 915-945 */
3345 # define DVSUNIT_CLOCK_GATE_DISABLE		(1 << 19) /* 915-945 */
3346 # define DSSUNIT_CLOCK_GATE_DISABLE		(1 << 18) /* 915-945 */
3347 # define DDBUNIT_CLOCK_GATE_DISABLE		(1 << 17) /* 915-945 */
3348 # define DPRUNIT_CLOCK_GATE_DISABLE		(1 << 16) /* 915-945 */
3349 # define DPFUNIT_CLOCK_GATE_DISABLE		(1 << 15) /* 915-945 */
3350 # define DPBMUNIT_CLOCK_GATE_DISABLE		(1 << 14) /* 915-945 */
3351 # define DPLSUNIT_CLOCK_GATE_DISABLE		(1 << 13) /* 915-945 */
3352 # define DPLUNIT_CLOCK_GATE_DISABLE		(1 << 12) /* 915-945 */
3353 # define DPOUNIT_CLOCK_GATE_DISABLE		(1 << 11)
3354 # define DPBUNIT_CLOCK_GATE_DISABLE		(1 << 10)
3355 # define DCUNIT_CLOCK_GATE_DISABLE		(1 << 9)
3356 # define DPUNIT_CLOCK_GATE_DISABLE		(1 << 8)
3357 # define VRUNIT_CLOCK_GATE_DISABLE		(1 << 7) /* 915+: reserved */
3358 # define OVHUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 830-865 */
3359 # define DPIOUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 915-945 */
3360 # define OVFUNIT_CLOCK_GATE_DISABLE		(1 << 5)
3361 # define OVBUNIT_CLOCK_GATE_DISABLE		(1 << 4)
3362 /*
3363  * This bit must be set on the 830 to prevent hangs when turning off the
3364  * overlay scaler.
3365  */
3366 # define OVRUNIT_CLOCK_GATE_DISABLE		(1 << 3)
3367 # define OVCUNIT_CLOCK_GATE_DISABLE		(1 << 2)
3368 # define OVUUNIT_CLOCK_GATE_DISABLE		(1 << 1)
3369 # define ZVUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 830 */
3370 # define OVLUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 845,865 */
3371 
3372 #define RENCLK_GATE_D1		_MMIO(0x6204)
3373 # define BLITTER_CLOCK_GATE_DISABLE		(1 << 13) /* 945GM only */
3374 # define MPEG_CLOCK_GATE_DISABLE		(1 << 12) /* 945GM only */
3375 # define PC_FE_CLOCK_GATE_DISABLE		(1 << 11)
3376 # define PC_BE_CLOCK_GATE_DISABLE		(1 << 10)
3377 # define WINDOWER_CLOCK_GATE_DISABLE		(1 << 9)
3378 # define INTERPOLATOR_CLOCK_GATE_DISABLE	(1 << 8)
3379 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE	(1 << 7)
3380 # define MOTION_COMP_CLOCK_GATE_DISABLE		(1 << 6)
3381 # define MAG_CLOCK_GATE_DISABLE			(1 << 5)
3382 /* This bit must be unset on 855,865 */
3383 # define MECI_CLOCK_GATE_DISABLE		(1 << 4)
3384 # define DCMP_CLOCK_GATE_DISABLE		(1 << 3)
3385 # define MEC_CLOCK_GATE_DISABLE			(1 << 2)
3386 # define MECO_CLOCK_GATE_DISABLE		(1 << 1)
3387 /* This bit must be set on 855,865. */
3388 # define SV_CLOCK_GATE_DISABLE			(1 << 0)
3389 # define I915_MPEG_CLOCK_GATE_DISABLE		(1 << 16)
3390 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE	(1 << 15)
3391 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE	(1 << 14)
3392 # define I915_BD_BF_CLOCK_GATE_DISABLE		(1 << 13)
3393 # define I915_SF_SE_CLOCK_GATE_DISABLE		(1 << 12)
3394 # define I915_WM_CLOCK_GATE_DISABLE		(1 << 11)
3395 # define I915_IZ_CLOCK_GATE_DISABLE		(1 << 10)
3396 # define I915_PI_CLOCK_GATE_DISABLE		(1 << 9)
3397 # define I915_DI_CLOCK_GATE_DISABLE		(1 << 8)
3398 # define I915_SH_SV_CLOCK_GATE_DISABLE		(1 << 7)
3399 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE	(1 << 6)
3400 # define I915_SC_CLOCK_GATE_DISABLE		(1 << 5)
3401 # define I915_FL_CLOCK_GATE_DISABLE		(1 << 4)
3402 # define I915_DM_CLOCK_GATE_DISABLE		(1 << 3)
3403 # define I915_PS_CLOCK_GATE_DISABLE		(1 << 2)
3404 # define I915_CC_CLOCK_GATE_DISABLE		(1 << 1)
3405 # define I915_BY_CLOCK_GATE_DISABLE		(1 << 0)
3406 
3407 # define I965_RCZ_CLOCK_GATE_DISABLE		(1 << 30)
3408 /* This bit must always be set on 965G/965GM */
3409 # define I965_RCC_CLOCK_GATE_DISABLE		(1 << 29)
3410 # define I965_RCPB_CLOCK_GATE_DISABLE		(1 << 28)
3411 # define I965_DAP_CLOCK_GATE_DISABLE		(1 << 27)
3412 # define I965_ROC_CLOCK_GATE_DISABLE		(1 << 26)
3413 # define I965_GW_CLOCK_GATE_DISABLE		(1 << 25)
3414 # define I965_TD_CLOCK_GATE_DISABLE		(1 << 24)
3415 /* This bit must always be set on 965G */
3416 # define I965_ISC_CLOCK_GATE_DISABLE		(1 << 23)
3417 # define I965_IC_CLOCK_GATE_DISABLE		(1 << 22)
3418 # define I965_EU_CLOCK_GATE_DISABLE		(1 << 21)
3419 # define I965_IF_CLOCK_GATE_DISABLE		(1 << 20)
3420 # define I965_TC_CLOCK_GATE_DISABLE		(1 << 19)
3421 # define I965_SO_CLOCK_GATE_DISABLE		(1 << 17)
3422 # define I965_FBC_CLOCK_GATE_DISABLE		(1 << 16)
3423 # define I965_MARI_CLOCK_GATE_DISABLE		(1 << 15)
3424 # define I965_MASF_CLOCK_GATE_DISABLE		(1 << 14)
3425 # define I965_MAWB_CLOCK_GATE_DISABLE		(1 << 13)
3426 # define I965_EM_CLOCK_GATE_DISABLE		(1 << 12)
3427 # define I965_UC_CLOCK_GATE_DISABLE		(1 << 11)
3428 # define I965_SI_CLOCK_GATE_DISABLE		(1 << 6)
3429 # define I965_MT_CLOCK_GATE_DISABLE		(1 << 5)
3430 # define I965_PL_CLOCK_GATE_DISABLE		(1 << 4)
3431 # define I965_DG_CLOCK_GATE_DISABLE		(1 << 3)
3432 # define I965_QC_CLOCK_GATE_DISABLE		(1 << 2)
3433 # define I965_FT_CLOCK_GATE_DISABLE		(1 << 1)
3434 # define I965_DM_CLOCK_GATE_DISABLE		(1 << 0)
3435 
3436 #define RENCLK_GATE_D2		_MMIO(0x6208)
3437 #define VF_UNIT_CLOCK_GATE_DISABLE		(1 << 9)
3438 #define GS_UNIT_CLOCK_GATE_DISABLE		(1 << 7)
3439 #define CL_UNIT_CLOCK_GATE_DISABLE		(1 << 6)
3440 
3441 #define VDECCLK_GATE_D		_MMIO(0x620C)		/* g4x only */
3442 #define  VCP_UNIT_CLOCK_GATE_DISABLE		(1 << 4)
3443 
3444 #define RAMCLK_GATE_D		_MMIO(0x6210)		/* CRL only */
3445 #define DEUC			_MMIO(0x6214)          /* CRL only */
3446 
3447 #define FW_BLC_SELF_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6500)
3448 #define  FW_CSPWRDWNEN		(1 << 15)
3449 
3450 #define MI_ARB_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6504)
3451 
3452 #define CZCLK_CDCLK_FREQ_RATIO	_MMIO(VLV_DISPLAY_BASE + 0x6508)
3453 #define   CDCLK_FREQ_SHIFT	4
3454 #define   CDCLK_FREQ_MASK	(0x1f << CDCLK_FREQ_SHIFT)
3455 #define   CZCLK_FREQ_MASK	0xf
3456 
3457 #define GCI_CONTROL		_MMIO(VLV_DISPLAY_BASE + 0x650C)
3458 #define   PFI_CREDIT_63		(9 << 28)		/* chv only */
3459 #define   PFI_CREDIT_31		(8 << 28)		/* chv only */
3460 #define   PFI_CREDIT(x)		(((x) - 8) << 28)	/* 8-15 */
3461 #define   PFI_CREDIT_RESEND	(1 << 27)
3462 #define   VGA_FAST_MODE_DISABLE	(1 << 14)
3463 
3464 #define GMBUSFREQ_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6510)
3465 
3466 /*
3467  * Palette regs
3468  */
3469 #define _PALETTE_A		0xa000
3470 #define _PALETTE_B		0xa800
3471 #define _CHV_PALETTE_C		0xc000
3472 #define PALETTE(pipe, i)	_MMIO(dev_priv->info.display_mmio_offset + \
3473 				      _PICK((pipe), _PALETTE_A,		\
3474 					    _PALETTE_B, _CHV_PALETTE_C) + \
3475 				      (i) * 4)
3476 
3477 /* MCH MMIO space */
3478 
3479 /*
3480  * MCHBAR mirror.
3481  *
3482  * This mirrors the MCHBAR MMIO space whose location is determined by
3483  * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
3484  * every way.  It is not accessible from the CP register read instructions.
3485  *
3486  * Starting from Haswell, you can't write registers using the MCHBAR mirror,
3487  * just read.
3488  */
3489 #define MCHBAR_MIRROR_BASE	0x10000
3490 
3491 #define MCHBAR_MIRROR_BASE_SNB	0x140000
3492 
3493 #define CTG_STOLEN_RESERVED		_MMIO(MCHBAR_MIRROR_BASE + 0x34)
3494 #define ELK_STOLEN_RESERVED		_MMIO(MCHBAR_MIRROR_BASE + 0x48)
3495 #define G4X_STOLEN_RESERVED_ADDR1_MASK	(0xFFFF << 16)
3496 #define G4X_STOLEN_RESERVED_ADDR2_MASK	(0xFFF << 4)
3497 #define G4X_STOLEN_RESERVED_ENABLE	(1 << 0)
3498 
3499 /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
3500 #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)
3501 
3502 /* 915-945 and GM965 MCH register controlling DRAM channel access */
3503 #define DCC			_MMIO(MCHBAR_MIRROR_BASE + 0x200)
3504 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL		(0 << 0)
3505 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC	(1 << 0)
3506 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED	(2 << 0)
3507 #define DCC_ADDRESSING_MODE_MASK			(3 << 0)
3508 #define DCC_CHANNEL_XOR_DISABLE				(1 << 10)
3509 #define DCC_CHANNEL_XOR_BIT_17				(1 << 9)
3510 #define DCC2			_MMIO(MCHBAR_MIRROR_BASE + 0x204)
3511 #define DCC2_MODIFIED_ENHANCED_DISABLE			(1 << 20)
3512 
3513 /* Pineview MCH register contains DDR3 setting */
3514 #define CSHRDDR3CTL            _MMIO(MCHBAR_MIRROR_BASE + 0x1a8)
3515 #define CSHRDDR3CTL_DDR3       (1 << 2)
3516 
3517 /* 965 MCH register controlling DRAM channel configuration */
3518 #define C0DRB3			_MMIO(MCHBAR_MIRROR_BASE + 0x206)
3519 #define C1DRB3			_MMIO(MCHBAR_MIRROR_BASE + 0x606)
3520 
3521 /* snb MCH registers for reading the DRAM channel configuration */
3522 #define MAD_DIMM_C0			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
3523 #define MAD_DIMM_C1			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
3524 #define MAD_DIMM_C2			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
3525 #define   MAD_DIMM_ECC_MASK		(0x3 << 24)
3526 #define   MAD_DIMM_ECC_OFF		(0x0 << 24)
3527 #define   MAD_DIMM_ECC_IO_ON_LOGIC_OFF	(0x1 << 24)
3528 #define   MAD_DIMM_ECC_IO_OFF_LOGIC_ON	(0x2 << 24)
3529 #define   MAD_DIMM_ECC_ON		(0x3 << 24)
3530 #define   MAD_DIMM_ENH_INTERLEAVE	(0x1 << 22)
3531 #define   MAD_DIMM_RANK_INTERLEAVE	(0x1 << 21)
3532 #define   MAD_DIMM_B_WIDTH_X16		(0x1 << 20) /* X8 chips if unset */
3533 #define   MAD_DIMM_A_WIDTH_X16		(0x1 << 19) /* X8 chips if unset */
3534 #define   MAD_DIMM_B_DUAL_RANK		(0x1 << 18)
3535 #define   MAD_DIMM_A_DUAL_RANK		(0x1 << 17)
3536 #define   MAD_DIMM_A_SELECT		(0x1 << 16)
3537 /* DIMM sizes are in multiples of 256mb. */
3538 #define   MAD_DIMM_B_SIZE_SHIFT		8
3539 #define   MAD_DIMM_B_SIZE_MASK		(0xff << MAD_DIMM_B_SIZE_SHIFT)
3540 #define   MAD_DIMM_A_SIZE_SHIFT		0
3541 #define   MAD_DIMM_A_SIZE_MASK		(0xff << MAD_DIMM_A_SIZE_SHIFT)
3542 
3543 /* snb MCH registers for priority tuning */
3544 #define MCH_SSKPD			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
3545 #define   MCH_SSKPD_WM0_MASK		0x3f
3546 #define   MCH_SSKPD_WM0_VAL		0xc
3547 
3548 #define MCH_SECP_NRG_STTS		_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x592c)
3549 
3550 /* Clocking configuration register */
3551 #define CLKCFG			_MMIO(MCHBAR_MIRROR_BASE + 0xc00)
3552 #define CLKCFG_FSB_400					(5 << 0)	/* hrawclk 100 */
3553 #define CLKCFG_FSB_533					(1 << 0)	/* hrawclk 133 */
3554 #define CLKCFG_FSB_667					(3 << 0)	/* hrawclk 166 */
3555 #define CLKCFG_FSB_800					(2 << 0)	/* hrawclk 200 */
3556 #define CLKCFG_FSB_1067					(6 << 0)	/* hrawclk 266 */
3557 #define CLKCFG_FSB_1067_ALT				(0 << 0)	/* hrawclk 266 */
3558 #define CLKCFG_FSB_1333					(7 << 0)	/* hrawclk 333 */
3559 /*
3560  * Note that on at least on ELK the below value is reported for both
3561  * 333 and 400 MHz BIOS FSB setting, but given that the gmch datasheet
3562  * lists only 200/266/333 MHz FSB as supported let's decode it as 333 MHz.
3563  */
3564 #define CLKCFG_FSB_1333_ALT				(4 << 0)	/* hrawclk 333 */
3565 #define CLKCFG_FSB_MASK					(7 << 0)
3566 #define CLKCFG_MEM_533					(1 << 4)
3567 #define CLKCFG_MEM_667					(2 << 4)
3568 #define CLKCFG_MEM_800					(3 << 4)
3569 #define CLKCFG_MEM_MASK					(7 << 4)
3570 
3571 #define HPLLVCO                 _MMIO(MCHBAR_MIRROR_BASE + 0xc38)
3572 #define HPLLVCO_MOBILE          _MMIO(MCHBAR_MIRROR_BASE + 0xc0f)
3573 
3574 #define TSC1			_MMIO(0x11001)
3575 #define   TSE			(1 << 0)
3576 #define TR1			_MMIO(0x11006)
3577 #define TSFS			_MMIO(0x11020)
3578 #define   TSFS_SLOPE_MASK	0x0000ff00
3579 #define   TSFS_SLOPE_SHIFT	8
3580 #define   TSFS_INTR_MASK	0x000000ff
3581 
3582 #define CRSTANDVID		_MMIO(0x11100)
3583 #define PXVFREQ(fstart)		_MMIO(0x11110 + (fstart) * 4)  /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
3584 #define   PXVFREQ_PX_MASK	0x7f000000
3585 #define   PXVFREQ_PX_SHIFT	24
3586 #define VIDFREQ_BASE		_MMIO(0x11110)
3587 #define VIDFREQ1		_MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */
3588 #define VIDFREQ2		_MMIO(0x11114)
3589 #define VIDFREQ3		_MMIO(0x11118)
3590 #define VIDFREQ4		_MMIO(0x1111c)
3591 #define   VIDFREQ_P0_MASK	0x1f000000
3592 #define   VIDFREQ_P0_SHIFT	24
3593 #define   VIDFREQ_P0_CSCLK_MASK	0x00f00000
3594 #define   VIDFREQ_P0_CSCLK_SHIFT 20
3595 #define   VIDFREQ_P0_CRCLK_MASK	0x000f0000
3596 #define   VIDFREQ_P0_CRCLK_SHIFT 16
3597 #define   VIDFREQ_P1_MASK	0x00001f00
3598 #define   VIDFREQ_P1_SHIFT	8
3599 #define   VIDFREQ_P1_CSCLK_MASK	0x000000f0
3600 #define   VIDFREQ_P1_CSCLK_SHIFT 4
3601 #define   VIDFREQ_P1_CRCLK_MASK	0x0000000f
3602 #define INTTOEXT_BASE_ILK	_MMIO(0x11300)
3603 #define INTTOEXT_BASE		_MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */
3604 #define   INTTOEXT_MAP3_SHIFT	24
3605 #define   INTTOEXT_MAP3_MASK	(0x1f << INTTOEXT_MAP3_SHIFT)
3606 #define   INTTOEXT_MAP2_SHIFT	16
3607 #define   INTTOEXT_MAP2_MASK	(0x1f << INTTOEXT_MAP2_SHIFT)
3608 #define   INTTOEXT_MAP1_SHIFT	8
3609 #define   INTTOEXT_MAP1_MASK	(0x1f << INTTOEXT_MAP1_SHIFT)
3610 #define   INTTOEXT_MAP0_SHIFT	0
3611 #define   INTTOEXT_MAP0_MASK	(0x1f << INTTOEXT_MAP0_SHIFT)
3612 #define MEMSWCTL		_MMIO(0x11170) /* Ironlake only */
3613 #define   MEMCTL_CMD_MASK	0xe000
3614 #define   MEMCTL_CMD_SHIFT	13
3615 #define   MEMCTL_CMD_RCLK_OFF	0
3616 #define   MEMCTL_CMD_RCLK_ON	1
3617 #define   MEMCTL_CMD_CHFREQ	2
3618 #define   MEMCTL_CMD_CHVID	3
3619 #define   MEMCTL_CMD_VMMOFF	4
3620 #define   MEMCTL_CMD_VMMON	5
3621 #define   MEMCTL_CMD_STS	(1 << 12) /* write 1 triggers command, clears
3622 					   when command complete */
3623 #define   MEMCTL_FREQ_MASK	0x0f00 /* jitter, from 0-15 */
3624 #define   MEMCTL_FREQ_SHIFT	8
3625 #define   MEMCTL_SFCAVM		(1 << 7)
3626 #define   MEMCTL_TGT_VID_MASK	0x007f
3627 #define MEMIHYST		_MMIO(0x1117c)
3628 #define MEMINTREN		_MMIO(0x11180) /* 16 bits */
3629 #define   MEMINT_RSEXIT_EN	(1 << 8)
3630 #define   MEMINT_CX_SUPR_EN	(1 << 7)
3631 #define   MEMINT_CONT_BUSY_EN	(1 << 6)
3632 #define   MEMINT_AVG_BUSY_EN	(1 << 5)
3633 #define   MEMINT_EVAL_CHG_EN	(1 << 4)
3634 #define   MEMINT_MON_IDLE_EN	(1 << 3)
3635 #define   MEMINT_UP_EVAL_EN	(1 << 2)
3636 #define   MEMINT_DOWN_EVAL_EN	(1 << 1)
3637 #define   MEMINT_SW_CMD_EN	(1 << 0)
3638 #define MEMINTRSTR		_MMIO(0x11182) /* 16 bits */
3639 #define   MEM_RSEXIT_MASK	0xc000
3640 #define   MEM_RSEXIT_SHIFT	14
3641 #define   MEM_CONT_BUSY_MASK	0x3000
3642 #define   MEM_CONT_BUSY_SHIFT	12
3643 #define   MEM_AVG_BUSY_MASK	0x0c00
3644 #define   MEM_AVG_BUSY_SHIFT	10
3645 #define   MEM_EVAL_CHG_MASK	0x0300
3646 #define   MEM_EVAL_BUSY_SHIFT	8
3647 #define   MEM_MON_IDLE_MASK	0x00c0
3648 #define   MEM_MON_IDLE_SHIFT	6
3649 #define   MEM_UP_EVAL_MASK	0x0030
3650 #define   MEM_UP_EVAL_SHIFT	4
3651 #define   MEM_DOWN_EVAL_MASK	0x000c
3652 #define   MEM_DOWN_EVAL_SHIFT	2
3653 #define   MEM_SW_CMD_MASK	0x0003
3654 #define   MEM_INT_STEER_GFX	0
3655 #define   MEM_INT_STEER_CMR	1
3656 #define   MEM_INT_STEER_SMI	2
3657 #define   MEM_INT_STEER_SCI	3
3658 #define MEMINTRSTS		_MMIO(0x11184)
3659 #define   MEMINT_RSEXIT		(1 << 7)
3660 #define   MEMINT_CONT_BUSY	(1 << 6)
3661 #define   MEMINT_AVG_BUSY	(1 << 5)
3662 #define   MEMINT_EVAL_CHG	(1 << 4)
3663 #define   MEMINT_MON_IDLE	(1 << 3)
3664 #define   MEMINT_UP_EVAL	(1 << 2)
3665 #define   MEMINT_DOWN_EVAL	(1 << 1)
3666 #define   MEMINT_SW_CMD		(1 << 0)
3667 #define MEMMODECTL		_MMIO(0x11190)
3668 #define   MEMMODE_BOOST_EN	(1 << 31)
3669 #define   MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
3670 #define   MEMMODE_BOOST_FREQ_SHIFT 24
3671 #define   MEMMODE_IDLE_MODE_MASK 0x00030000
3672 #define   MEMMODE_IDLE_MODE_SHIFT 16
3673 #define   MEMMODE_IDLE_MODE_EVAL 0
3674 #define   MEMMODE_IDLE_MODE_CONT 1
3675 #define   MEMMODE_HWIDLE_EN	(1 << 15)
3676 #define   MEMMODE_SWMODE_EN	(1 << 14)
3677 #define   MEMMODE_RCLK_GATE	(1 << 13)
3678 #define   MEMMODE_HW_UPDATE	(1 << 12)
3679 #define   MEMMODE_FSTART_MASK	0x00000f00 /* starting jitter, 0-15 */
3680 #define   MEMMODE_FSTART_SHIFT	8
3681 #define   MEMMODE_FMAX_MASK	0x000000f0 /* max jitter, 0-15 */
3682 #define   MEMMODE_FMAX_SHIFT	4
3683 #define   MEMMODE_FMIN_MASK	0x0000000f /* min jitter, 0-15 */
3684 #define RCBMAXAVG		_MMIO(0x1119c)
3685 #define MEMSWCTL2		_MMIO(0x1119e) /* Cantiga only */
3686 #define   SWMEMCMD_RENDER_OFF	(0 << 13)
3687 #define   SWMEMCMD_RENDER_ON	(1 << 13)
3688 #define   SWMEMCMD_SWFREQ	(2 << 13)
3689 #define   SWMEMCMD_TARVID	(3 << 13)
3690 #define   SWMEMCMD_VRM_OFF	(4 << 13)
3691 #define   SWMEMCMD_VRM_ON	(5 << 13)
3692 #define   CMDSTS		(1 << 12)
3693 #define   SFCAVM		(1 << 11)
3694 #define   SWFREQ_MASK		0x0380 /* P0-7 */
3695 #define   SWFREQ_SHIFT		7
3696 #define   TARVID_MASK		0x001f
3697 #define MEMSTAT_CTG		_MMIO(0x111a0)
3698 #define RCBMINAVG		_MMIO(0x111a0)
3699 #define RCUPEI			_MMIO(0x111b0)
3700 #define RCDNEI			_MMIO(0x111b4)
3701 #define RSTDBYCTL		_MMIO(0x111b8)
3702 #define   RS1EN			(1 << 31)
3703 #define   RS2EN			(1 << 30)
3704 #define   RS3EN			(1 << 29)
3705 #define   D3RS3EN		(1 << 28) /* Display D3 imlies RS3 */
3706 #define   SWPROMORSX		(1 << 27) /* RSx promotion timers ignored */
3707 #define   RCWAKERW		(1 << 26) /* Resetwarn from PCH causes wakeup */
3708 #define   DPRSLPVREN		(1 << 25) /* Fast voltage ramp enable */
3709 #define   GFXTGHYST		(1 << 24) /* Hysteresis to allow trunk gating */
3710 #define   RCX_SW_EXIT		(1 << 23) /* Leave RSx and prevent re-entry */
3711 #define   RSX_STATUS_MASK	(7 << 20)
3712 #define   RSX_STATUS_ON		(0 << 20)
3713 #define   RSX_STATUS_RC1	(1 << 20)
3714 #define   RSX_STATUS_RC1E	(2 << 20)
3715 #define   RSX_STATUS_RS1	(3 << 20)
3716 #define   RSX_STATUS_RS2	(4 << 20) /* aka rc6 */
3717 #define   RSX_STATUS_RSVD	(5 << 20) /* deep rc6 unsupported on ilk */
3718 #define   RSX_STATUS_RS3	(6 << 20) /* rs3 unsupported on ilk */
3719 #define   RSX_STATUS_RSVD2	(7 << 20)
3720 #define   UWRCRSXE		(1 << 19) /* wake counter limit prevents rsx */
3721 #define   RSCRP			(1 << 18) /* rs requests control on rs1/2 reqs */
3722 #define   JRSC			(1 << 17) /* rsx coupled to cpu c-state */
3723 #define   RS2INC0		(1 << 16) /* allow rs2 in cpu c0 */
3724 #define   RS1CONTSAV_MASK	(3 << 14)
3725 #define   RS1CONTSAV_NO_RS1	(0 << 14) /* rs1 doesn't save/restore context */
3726 #define   RS1CONTSAV_RSVD	(1 << 14)
3727 #define   RS1CONTSAV_SAVE_RS1	(2 << 14) /* rs1 saves context */
3728 #define   RS1CONTSAV_FULL_RS1	(3 << 14) /* rs1 saves and restores context */
3729 #define   NORMSLEXLAT_MASK	(3 << 12)
3730 #define   SLOW_RS123		(0 << 12)
3731 #define   SLOW_RS23		(1 << 12)
3732 #define   SLOW_RS3		(2 << 12)
3733 #define   NORMAL_RS123		(3 << 12)
3734 #define   RCMODE_TIMEOUT	(1 << 11) /* 0 is eval interval method */
3735 #define   IMPROMOEN		(1 << 10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
3736 #define   RCENTSYNC		(1 << 9) /* rs coupled to cpu c-state (3/6/7) */
3737 #define   STATELOCK		(1 << 7) /* locked to rs_cstate if 0 */
3738 #define   RS_CSTATE_MASK	(3 << 4)
3739 #define   RS_CSTATE_C367_RS1	(0 << 4)
3740 #define   RS_CSTATE_C36_RS1_C7_RS2 (1 << 4)
3741 #define   RS_CSTATE_RSVD	(2 << 4)
3742 #define   RS_CSTATE_C367_RS2	(3 << 4)
3743 #define   REDSAVES		(1 << 3) /* no context save if was idle during rs0 */
3744 #define   REDRESTORES		(1 << 2) /* no restore if was idle during rs0 */
3745 #define VIDCTL			_MMIO(0x111c0)
3746 #define VIDSTS			_MMIO(0x111c8)
3747 #define VIDSTART		_MMIO(0x111cc) /* 8 bits */
3748 #define MEMSTAT_ILK		_MMIO(0x111f8)
3749 #define   MEMSTAT_VID_MASK	0x7f00
3750 #define   MEMSTAT_VID_SHIFT	8
3751 #define   MEMSTAT_PSTATE_MASK	0x00f8
3752 #define   MEMSTAT_PSTATE_SHIFT  3
3753 #define   MEMSTAT_MON_ACTV	(1 << 2)
3754 #define   MEMSTAT_SRC_CTL_MASK	0x0003
3755 #define   MEMSTAT_SRC_CTL_CORE	0
3756 #define   MEMSTAT_SRC_CTL_TRB	1
3757 #define   MEMSTAT_SRC_CTL_THM	2
3758 #define   MEMSTAT_SRC_CTL_STDBY 3
3759 #define RCPREVBSYTUPAVG		_MMIO(0x113b8)
3760 #define RCPREVBSYTDNAVG		_MMIO(0x113bc)
3761 #define PMMISC			_MMIO(0x11214)
3762 #define   MCPPCE_EN		(1 << 0) /* enable PM_MSG from PCH->MPC */
3763 #define SDEW			_MMIO(0x1124c)
3764 #define CSIEW0			_MMIO(0x11250)
3765 #define CSIEW1			_MMIO(0x11254)
3766 #define CSIEW2			_MMIO(0x11258)
3767 #define PEW(i)			_MMIO(0x1125c + (i) * 4) /* 5 registers */
3768 #define DEW(i)			_MMIO(0x11270 + (i) * 4) /* 3 registers */
3769 #define MCHAFE			_MMIO(0x112c0)
3770 #define CSIEC			_MMIO(0x112e0)
3771 #define DMIEC			_MMIO(0x112e4)
3772 #define DDREC			_MMIO(0x112e8)
3773 #define PEG0EC			_MMIO(0x112ec)
3774 #define PEG1EC			_MMIO(0x112f0)
3775 #define GFXEC			_MMIO(0x112f4)
3776 #define RPPREVBSYTUPAVG		_MMIO(0x113b8)
3777 #define RPPREVBSYTDNAVG		_MMIO(0x113bc)
3778 #define ECR			_MMIO(0x11600)
3779 #define   ECR_GPFE		(1 << 31)
3780 #define   ECR_IMONE		(1 << 30)
3781 #define   ECR_CAP_MASK		0x0000001f /* Event range, 0-31 */
3782 #define OGW0			_MMIO(0x11608)
3783 #define OGW1			_MMIO(0x1160c)
3784 #define EG0			_MMIO(0x11610)
3785 #define EG1			_MMIO(0x11614)
3786 #define EG2			_MMIO(0x11618)
3787 #define EG3			_MMIO(0x1161c)
3788 #define EG4			_MMIO(0x11620)
3789 #define EG5			_MMIO(0x11624)
3790 #define EG6			_MMIO(0x11628)
3791 #define EG7			_MMIO(0x1162c)
3792 #define PXW(i)			_MMIO(0x11664 + (i) * 4) /* 4 registers */
3793 #define PXWL(i)			_MMIO(0x11680 + (i) * 8) /* 8 registers */
3794 #define LCFUSE02		_MMIO(0x116c0)
3795 #define   LCFUSE_HIV_MASK	0x000000ff
3796 #define CSIPLL0			_MMIO(0x12c10)
3797 #define DDRMPLL1		_MMIO(0X12c20)
3798 #define PEG_BAND_GAP_DATA	_MMIO(0x14d68)
3799 
3800 #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
3801 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
3802 
3803 #define GEN6_GT_PERF_STATUS	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
3804 #define BXT_GT_PERF_STATUS      _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)
3805 #define GEN6_RP_STATE_LIMITS	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
3806 #define GEN6_RP_STATE_CAP	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
3807 #define BXT_RP_STATE_CAP        _MMIO(0x138170)
3808 
3809 /*
3810  * Make these a multiple of magic 25 to avoid SNB (eg. Dell XPS
3811  * 8300) freezing up around GPU hangs. Looks as if even
3812  * scheduling/timer interrupts start misbehaving if the RPS
3813  * EI/thresholds are "bad", leading to a very sluggish or even
3814  * frozen machine.
3815  */
3816 #define INTERVAL_1_28_US(us)	roundup(((us) * 100) >> 7, 25)
3817 #define INTERVAL_1_33_US(us)	(((us) * 3)   >> 2)
3818 #define INTERVAL_0_833_US(us)	(((us) * 6) / 5)
3819 #define GT_INTERVAL_FROM_US(dev_priv, us) (INTEL_GEN(dev_priv) >= 9 ? \
3820 				(IS_GEN9_LP(dev_priv) ? \
3821 				INTERVAL_0_833_US(us) : \
3822 				INTERVAL_1_33_US(us)) : \
3823 				INTERVAL_1_28_US(us))
3824 
3825 #define INTERVAL_1_28_TO_US(interval)  (((interval) << 7) / 100)
3826 #define INTERVAL_1_33_TO_US(interval)  (((interval) << 2) / 3)
3827 #define INTERVAL_0_833_TO_US(interval) (((interval) * 5)  / 6)
3828 #define GT_PM_INTERVAL_TO_US(dev_priv, interval) (INTEL_GEN(dev_priv) >= 9 ? \
3829                            (IS_GEN9_LP(dev_priv) ? \
3830                            INTERVAL_0_833_TO_US(interval) : \
3831                            INTERVAL_1_33_TO_US(interval)) : \
3832                            INTERVAL_1_28_TO_US(interval))
3833 
3834 /*
3835  * Logical Context regs
3836  */
3837 #define CCID				_MMIO(0x2180)
3838 #define   CCID_EN			BIT(0)
3839 #define   CCID_EXTENDED_STATE_RESTORE	BIT(2)
3840 #define   CCID_EXTENDED_STATE_SAVE	BIT(3)
3841 /*
3842  * Notes on SNB/IVB/VLV context size:
3843  * - Power context is saved elsewhere (LLC or stolen)
3844  * - Ring/execlist context is saved on SNB, not on IVB
3845  * - Extended context size already includes render context size
3846  * - We always need to follow the extended context size.
3847  *   SNB BSpec has comments indicating that we should use the
3848  *   render context size instead if execlists are disabled, but
3849  *   based on empirical testing that's just nonsense.
3850  * - Pipelined/VF state is saved on SNB/IVB respectively
3851  * - GT1 size just indicates how much of render context
3852  *   doesn't need saving on GT1
3853  */
3854 #define CXT_SIZE		_MMIO(0x21a0)
3855 #define GEN6_CXT_POWER_SIZE(cxt_reg)	(((cxt_reg) >> 24) & 0x3f)
3856 #define GEN6_CXT_RING_SIZE(cxt_reg)	(((cxt_reg) >> 18) & 0x3f)
3857 #define GEN6_CXT_RENDER_SIZE(cxt_reg)	(((cxt_reg) >> 12) & 0x3f)
3858 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg)	(((cxt_reg) >> 6) & 0x3f)
3859 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg)	(((cxt_reg) >> 0) & 0x3f)
3860 #define GEN6_CXT_TOTAL_SIZE(cxt_reg)	(GEN6_CXT_RING_SIZE(cxt_reg) + \
3861 					GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
3862 					GEN6_CXT_PIPELINE_SIZE(cxt_reg))
3863 #define GEN7_CXT_SIZE		_MMIO(0x21a8)
3864 #define GEN7_CXT_POWER_SIZE(ctx_reg)	(((ctx_reg) >> 25) & 0x7f)
3865 #define GEN7_CXT_RING_SIZE(ctx_reg)	(((ctx_reg) >> 22) & 0x7)
3866 #define GEN7_CXT_RENDER_SIZE(ctx_reg)	(((ctx_reg) >> 16) & 0x3f)
3867 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg)	(((ctx_reg) >> 9) & 0x7f)
3868 #define GEN7_CXT_GT1_SIZE(ctx_reg)	(((ctx_reg) >> 6) & 0x7)
3869 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg)	(((ctx_reg) >> 0) & 0x3f)
3870 #define GEN7_CXT_TOTAL_SIZE(ctx_reg)	(GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
3871 					 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
3872 
3873 enum {
3874 	INTEL_ADVANCED_CONTEXT = 0,
3875 	INTEL_LEGACY_32B_CONTEXT,
3876 	INTEL_ADVANCED_AD_CONTEXT,
3877 	INTEL_LEGACY_64B_CONTEXT
3878 };
3879 
3880 enum {
3881 	FAULT_AND_HANG = 0,
3882 	FAULT_AND_HALT, /* Debug only */
3883 	FAULT_AND_STREAM,
3884 	FAULT_AND_CONTINUE /* Unsupported */
3885 };
3886 
3887 #define GEN8_CTX_VALID (1 << 0)
3888 #define GEN8_CTX_FORCE_PD_RESTORE (1 << 1)
3889 #define GEN8_CTX_FORCE_RESTORE (1 << 2)
3890 #define GEN8_CTX_L3LLC_COHERENT (1 << 5)
3891 #define GEN8_CTX_PRIVILEGE (1 << 8)
3892 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
3893 
3894 #define GEN8_CTX_ID_SHIFT 32
3895 #define GEN8_CTX_ID_WIDTH 21
3896 #define GEN11_SW_CTX_ID_SHIFT 37
3897 #define GEN11_SW_CTX_ID_WIDTH 11
3898 #define GEN11_ENGINE_CLASS_SHIFT 61
3899 #define GEN11_ENGINE_CLASS_WIDTH 3
3900 #define GEN11_ENGINE_INSTANCE_SHIFT 48
3901 #define GEN11_ENGINE_INSTANCE_WIDTH 6
3902 
3903 #define CHV_CLK_CTL1			_MMIO(0x101100)
3904 #define VLV_CLK_CTL2			_MMIO(0x101104)
3905 #define   CLK_CTL2_CZCOUNT_30NS_SHIFT	28
3906 
3907 /*
3908  * Overlay regs
3909  */
3910 
3911 #define OVADD			_MMIO(0x30000)
3912 #define DOVSTA			_MMIO(0x30008)
3913 #define OC_BUF			(0x3 << 20)
3914 #define OGAMC5			_MMIO(0x30010)
3915 #define OGAMC4			_MMIO(0x30014)
3916 #define OGAMC3			_MMIO(0x30018)
3917 #define OGAMC2			_MMIO(0x3001c)
3918 #define OGAMC1			_MMIO(0x30020)
3919 #define OGAMC0			_MMIO(0x30024)
3920 
3921 /*
3922  * GEN9 clock gating regs
3923  */
3924 #define GEN9_CLKGATE_DIS_0		_MMIO(0x46530)
3925 #define   DARBF_GATING_DIS		(1 << 27)
3926 #define   PWM2_GATING_DIS		(1 << 14)
3927 #define   PWM1_GATING_DIS		(1 << 13)
3928 
3929 #define GEN9_CLKGATE_DIS_4		_MMIO(0x4653C)
3930 #define   BXT_GMBUS_GATING_DIS		(1 << 14)
3931 
3932 #define _CLKGATE_DIS_PSL_A		0x46520
3933 #define _CLKGATE_DIS_PSL_B		0x46524
3934 #define _CLKGATE_DIS_PSL_C		0x46528
3935 #define   DUPS1_GATING_DIS		(1 << 15)
3936 #define   DUPS2_GATING_DIS		(1 << 19)
3937 #define   DUPS3_GATING_DIS		(1 << 23)
3938 #define   DPF_GATING_DIS		(1 << 10)
3939 #define   DPF_RAM_GATING_DIS		(1 << 9)
3940 #define   DPFR_GATING_DIS		(1 << 8)
3941 
3942 #define CLKGATE_DIS_PSL(pipe) \
3943 	_MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)
3944 
3945 /*
3946  * GEN10 clock gating regs
3947  */
3948 #define SLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x94d4)
3949 #define  SARBUNIT_CLKGATE_DIS		(1 << 5)
3950 #define  RCCUNIT_CLKGATE_DIS		(1 << 7)
3951 #define  MSCUNIT_CLKGATE_DIS		(1 << 10)
3952 
3953 #define SUBSLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x9524)
3954 #define  GWUNIT_CLKGATE_DIS		(1 << 16)
3955 
3956 #define UNSLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x9434)
3957 #define  VFUNIT_CLKGATE_DIS		(1 << 20)
3958 
3959 #define INF_UNIT_LEVEL_CLKGATE		_MMIO(0x9560)
3960 #define   CGPSF_CLKGATE_DIS		(1 << 3)
3961 
3962 /*
3963  * Display engine regs
3964  */
3965 
3966 /* Pipe A CRC regs */
3967 #define _PIPE_CRC_CTL_A			0x60050
3968 #define   PIPE_CRC_ENABLE		(1 << 31)
3969 /* ivb+ source selection */
3970 #define   PIPE_CRC_SOURCE_PRIMARY_IVB	(0 << 29)
3971 #define   PIPE_CRC_SOURCE_SPRITE_IVB	(1 << 29)
3972 #define   PIPE_CRC_SOURCE_PF_IVB	(2 << 29)
3973 /* ilk+ source selection */
3974 #define   PIPE_CRC_SOURCE_PRIMARY_ILK	(0 << 28)
3975 #define   PIPE_CRC_SOURCE_SPRITE_ILK	(1 << 28)
3976 #define   PIPE_CRC_SOURCE_PIPE_ILK	(2 << 28)
3977 /* embedded DP port on the north display block, reserved on ivb */
3978 #define   PIPE_CRC_SOURCE_PORT_A_ILK	(4 << 28)
3979 #define   PIPE_CRC_SOURCE_FDI_ILK	(5 << 28) /* reserved on ivb */
3980 /* vlv source selection */
3981 #define   PIPE_CRC_SOURCE_PIPE_VLV	(0 << 27)
3982 #define   PIPE_CRC_SOURCE_HDMIB_VLV	(1 << 27)
3983 #define   PIPE_CRC_SOURCE_HDMIC_VLV	(2 << 27)
3984 /* with DP port the pipe source is invalid */
3985 #define   PIPE_CRC_SOURCE_DP_D_VLV	(3 << 27)
3986 #define   PIPE_CRC_SOURCE_DP_B_VLV	(6 << 27)
3987 #define   PIPE_CRC_SOURCE_DP_C_VLV	(7 << 27)
3988 /* gen3+ source selection */
3989 #define   PIPE_CRC_SOURCE_PIPE_I9XX	(0 << 28)
3990 #define   PIPE_CRC_SOURCE_SDVOB_I9XX	(1 << 28)
3991 #define   PIPE_CRC_SOURCE_SDVOC_I9XX	(2 << 28)
3992 /* with DP/TV port the pipe source is invalid */
3993 #define   PIPE_CRC_SOURCE_DP_D_G4X	(3 << 28)
3994 #define   PIPE_CRC_SOURCE_TV_PRE	(4 << 28)
3995 #define   PIPE_CRC_SOURCE_TV_POST	(5 << 28)
3996 #define   PIPE_CRC_SOURCE_DP_B_G4X	(6 << 28)
3997 #define   PIPE_CRC_SOURCE_DP_C_G4X	(7 << 28)
3998 /* gen2 doesn't have source selection bits */
3999 #define   PIPE_CRC_INCLUDE_BORDER_I8XX	(1 << 30)
4000 
4001 #define _PIPE_CRC_RES_1_A_IVB		0x60064
4002 #define _PIPE_CRC_RES_2_A_IVB		0x60068
4003 #define _PIPE_CRC_RES_3_A_IVB		0x6006c
4004 #define _PIPE_CRC_RES_4_A_IVB		0x60070
4005 #define _PIPE_CRC_RES_5_A_IVB		0x60074
4006 
4007 #define _PIPE_CRC_RES_RED_A		0x60060
4008 #define _PIPE_CRC_RES_GREEN_A		0x60064
4009 #define _PIPE_CRC_RES_BLUE_A		0x60068
4010 #define _PIPE_CRC_RES_RES1_A_I915	0x6006c
4011 #define _PIPE_CRC_RES_RES2_A_G4X	0x60080
4012 
4013 /* Pipe B CRC regs */
4014 #define _PIPE_CRC_RES_1_B_IVB		0x61064
4015 #define _PIPE_CRC_RES_2_B_IVB		0x61068
4016 #define _PIPE_CRC_RES_3_B_IVB		0x6106c
4017 #define _PIPE_CRC_RES_4_B_IVB		0x61070
4018 #define _PIPE_CRC_RES_5_B_IVB		0x61074
4019 
4020 #define PIPE_CRC_CTL(pipe)		_MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A)
4021 #define PIPE_CRC_RES_1_IVB(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB)
4022 #define PIPE_CRC_RES_2_IVB(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB)
4023 #define PIPE_CRC_RES_3_IVB(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB)
4024 #define PIPE_CRC_RES_4_IVB(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB)
4025 #define PIPE_CRC_RES_5_IVB(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB)
4026 
4027 #define PIPE_CRC_RES_RED(pipe)		_MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A)
4028 #define PIPE_CRC_RES_GREEN(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A)
4029 #define PIPE_CRC_RES_BLUE(pipe)		_MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A)
4030 #define PIPE_CRC_RES_RES1_I915(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915)
4031 #define PIPE_CRC_RES_RES2_G4X(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
4032 
4033 /* Pipe A timing regs */
4034 #define _HTOTAL_A	0x60000
4035 #define _HBLANK_A	0x60004
4036 #define _HSYNC_A	0x60008
4037 #define _VTOTAL_A	0x6000c
4038 #define _VBLANK_A	0x60010
4039 #define _VSYNC_A	0x60014
4040 #define _PIPEASRC	0x6001c
4041 #define _BCLRPAT_A	0x60020
4042 #define _VSYNCSHIFT_A	0x60028
4043 #define _PIPE_MULT_A	0x6002c
4044 
4045 /* Pipe B timing regs */
4046 #define _HTOTAL_B	0x61000
4047 #define _HBLANK_B	0x61004
4048 #define _HSYNC_B	0x61008
4049 #define _VTOTAL_B	0x6100c
4050 #define _VBLANK_B	0x61010
4051 #define _VSYNC_B	0x61014
4052 #define _PIPEBSRC	0x6101c
4053 #define _BCLRPAT_B	0x61020
4054 #define _VSYNCSHIFT_B	0x61028
4055 #define _PIPE_MULT_B	0x6102c
4056 
4057 /* DSI 0 timing regs */
4058 #define _HTOTAL_DSI0		0x6b000
4059 #define _HSYNC_DSI0		0x6b008
4060 #define _VTOTAL_DSI0		0x6b00c
4061 #define _VSYNC_DSI0		0x6b014
4062 #define _VSYNCSHIFT_DSI0	0x6b028
4063 
4064 /* DSI 1 timing regs */
4065 #define _HTOTAL_DSI1		0x6b800
4066 #define _HSYNC_DSI1		0x6b808
4067 #define _VTOTAL_DSI1		0x6b80c
4068 #define _VSYNC_DSI1		0x6b814
4069 #define _VSYNCSHIFT_DSI1	0x6b828
4070 
4071 #define TRANSCODER_A_OFFSET 0x60000
4072 #define TRANSCODER_B_OFFSET 0x61000
4073 #define TRANSCODER_C_OFFSET 0x62000
4074 #define CHV_TRANSCODER_C_OFFSET 0x63000
4075 #define TRANSCODER_EDP_OFFSET 0x6f000
4076 #define TRANSCODER_DSI0_OFFSET	0x6b000
4077 #define TRANSCODER_DSI1_OFFSET	0x6b800
4078 
4079 #define HTOTAL(trans)		_MMIO_TRANS2(trans, _HTOTAL_A)
4080 #define HBLANK(trans)		_MMIO_TRANS2(trans, _HBLANK_A)
4081 #define HSYNC(trans)		_MMIO_TRANS2(trans, _HSYNC_A)
4082 #define VTOTAL(trans)		_MMIO_TRANS2(trans, _VTOTAL_A)
4083 #define VBLANK(trans)		_MMIO_TRANS2(trans, _VBLANK_A)
4084 #define VSYNC(trans)		_MMIO_TRANS2(trans, _VSYNC_A)
4085 #define BCLRPAT(trans)		_MMIO_TRANS2(trans, _BCLRPAT_A)
4086 #define VSYNCSHIFT(trans)	_MMIO_TRANS2(trans, _VSYNCSHIFT_A)
4087 #define PIPESRC(trans)		_MMIO_TRANS2(trans, _PIPEASRC)
4088 #define PIPE_MULT(trans)	_MMIO_TRANS2(trans, _PIPE_MULT_A)
4089 
4090 /* VLV eDP PSR registers */
4091 #define _PSRCTLA				(VLV_DISPLAY_BASE + 0x60090)
4092 #define _PSRCTLB				(VLV_DISPLAY_BASE + 0x61090)
4093 #define  VLV_EDP_PSR_ENABLE			(1 << 0)
4094 #define  VLV_EDP_PSR_RESET			(1 << 1)
4095 #define  VLV_EDP_PSR_MODE_MASK			(7 << 2)
4096 #define  VLV_EDP_PSR_MODE_HW_TIMER		(1 << 3)
4097 #define  VLV_EDP_PSR_MODE_SW_TIMER		(1 << 2)
4098 #define  VLV_EDP_PSR_SINGLE_FRAME_UPDATE	(1 << 7)
4099 #define  VLV_EDP_PSR_ACTIVE_ENTRY		(1 << 8)
4100 #define  VLV_EDP_PSR_SRC_TRANSMITTER_STATE	(1 << 9)
4101 #define  VLV_EDP_PSR_DBL_FRAME			(1 << 10)
4102 #define  VLV_EDP_PSR_FRAME_COUNT_MASK		(0xff << 16)
4103 #define  VLV_EDP_PSR_IDLE_FRAME_SHIFT		16
4104 #define VLV_PSRCTL(pipe)	_MMIO_PIPE(pipe, _PSRCTLA, _PSRCTLB)
4105 
4106 #define _VSCSDPA			(VLV_DISPLAY_BASE + 0x600a0)
4107 #define _VSCSDPB			(VLV_DISPLAY_BASE + 0x610a0)
4108 #define  VLV_EDP_PSR_SDP_FREQ_MASK	(3 << 30)
4109 #define  VLV_EDP_PSR_SDP_FREQ_ONCE	(1 << 31)
4110 #define  VLV_EDP_PSR_SDP_FREQ_EVFRAME	(1 << 30)
4111 #define VLV_VSCSDP(pipe)	_MMIO_PIPE(pipe, _VSCSDPA, _VSCSDPB)
4112 
4113 #define _PSRSTATA			(VLV_DISPLAY_BASE + 0x60094)
4114 #define _PSRSTATB			(VLV_DISPLAY_BASE + 0x61094)
4115 #define  VLV_EDP_PSR_LAST_STATE_MASK	(7 << 3)
4116 #define  VLV_EDP_PSR_CURR_STATE_MASK	7
4117 #define  VLV_EDP_PSR_DISABLED		(0 << 0)
4118 #define  VLV_EDP_PSR_INACTIVE		(1 << 0)
4119 #define  VLV_EDP_PSR_IN_TRANS_TO_ACTIVE	(2 << 0)
4120 #define  VLV_EDP_PSR_ACTIVE_NORFB_UP	(3 << 0)
4121 #define  VLV_EDP_PSR_ACTIVE_SF_UPDATE	(4 << 0)
4122 #define  VLV_EDP_PSR_EXIT		(5 << 0)
4123 #define  VLV_EDP_PSR_IN_TRANS		(1 << 7)
4124 #define VLV_PSRSTAT(pipe)	_MMIO_PIPE(pipe, _PSRSTATA, _PSRSTATB)
4125 
4126 /* HSW+ eDP PSR registers */
4127 #define HSW_EDP_PSR_BASE	0x64800
4128 #define BDW_EDP_PSR_BASE	0x6f800
4129 #define EDP_PSR_CTL				_MMIO(dev_priv->psr_mmio_base + 0)
4130 #define   EDP_PSR_ENABLE			(1 << 31)
4131 #define   BDW_PSR_SINGLE_FRAME			(1 << 30)
4132 #define   EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK	(1 << 29) /* SW can't modify */
4133 #define   EDP_PSR_LINK_STANDBY			(1 << 27)
4134 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_MASK	(3 << 25)
4135 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES	(0 << 25)
4136 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES	(1 << 25)
4137 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES	(2 << 25)
4138 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES	(3 << 25)
4139 #define   EDP_PSR_MAX_SLEEP_TIME_SHIFT		20
4140 #define   EDP_PSR_SKIP_AUX_EXIT			(1 << 12)
4141 #define   EDP_PSR_TP1_TP2_SEL			(0 << 11)
4142 #define   EDP_PSR_TP1_TP3_SEL			(1 << 11)
4143 #define   EDP_PSR_CRC_ENABLE			(1 << 10) /* BDW+ */
4144 #define   EDP_PSR_TP2_TP3_TIME_500us		(0 << 8)
4145 #define   EDP_PSR_TP2_TP3_TIME_100us		(1 << 8)
4146 #define   EDP_PSR_TP2_TP3_TIME_2500us		(2 << 8)
4147 #define   EDP_PSR_TP2_TP3_TIME_0us		(3 << 8)
4148 #define   EDP_PSR_TP1_TIME_500us		(0 << 4)
4149 #define   EDP_PSR_TP1_TIME_100us		(1 << 4)
4150 #define   EDP_PSR_TP1_TIME_2500us		(2 << 4)
4151 #define   EDP_PSR_TP1_TIME_0us			(3 << 4)
4152 #define   EDP_PSR_IDLE_FRAME_SHIFT		0
4153 
4154 /* Bspec claims those aren't shifted but stay at 0x64800 */
4155 #define EDP_PSR_IMR				_MMIO(0x64834)
4156 #define EDP_PSR_IIR				_MMIO(0x64838)
4157 #define   EDP_PSR_ERROR(shift)			(1 << ((shift) + 2))
4158 #define   EDP_PSR_POST_EXIT(shift)		(1 << ((shift) + 1))
4159 #define   EDP_PSR_PRE_ENTRY(shift)		(1 << (shift))
4160 #define   EDP_PSR_TRANSCODER_C_SHIFT		24
4161 #define   EDP_PSR_TRANSCODER_B_SHIFT		16
4162 #define   EDP_PSR_TRANSCODER_A_SHIFT		8
4163 #define   EDP_PSR_TRANSCODER_EDP_SHIFT		0
4164 
4165 #define EDP_PSR_AUX_CTL				_MMIO(dev_priv->psr_mmio_base + 0x10)
4166 #define   EDP_PSR_AUX_CTL_TIME_OUT_MASK		(3 << 26)
4167 #define   EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK	(0x1f << 20)
4168 #define   EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK	(0xf << 16)
4169 #define   EDP_PSR_AUX_CTL_ERROR_INTERRUPT	(1 << 11)
4170 #define   EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK	(0x7ff)
4171 
4172 #define EDP_PSR_AUX_DATA(i)			_MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */
4173 
4174 #define EDP_PSR_STATUS				_MMIO(dev_priv->psr_mmio_base + 0x40)
4175 #define   EDP_PSR_STATUS_STATE_MASK		(7 << 29)
4176 #define   EDP_PSR_STATUS_STATE_SHIFT		29
4177 #define   EDP_PSR_STATUS_STATE_IDLE		(0 << 29)
4178 #define   EDP_PSR_STATUS_STATE_SRDONACK		(1 << 29)
4179 #define   EDP_PSR_STATUS_STATE_SRDENT		(2 << 29)
4180 #define   EDP_PSR_STATUS_STATE_BUFOFF		(3 << 29)
4181 #define   EDP_PSR_STATUS_STATE_BUFON		(4 << 29)
4182 #define   EDP_PSR_STATUS_STATE_AUXACK		(5 << 29)
4183 #define   EDP_PSR_STATUS_STATE_SRDOFFACK	(6 << 29)
4184 #define   EDP_PSR_STATUS_LINK_MASK		(3 << 26)
4185 #define   EDP_PSR_STATUS_LINK_FULL_OFF		(0 << 26)
4186 #define   EDP_PSR_STATUS_LINK_FULL_ON		(1 << 26)
4187 #define   EDP_PSR_STATUS_LINK_STANDBY		(2 << 26)
4188 #define   EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT	20
4189 #define   EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK	0x1f
4190 #define   EDP_PSR_STATUS_COUNT_SHIFT		16
4191 #define   EDP_PSR_STATUS_COUNT_MASK		0xf
4192 #define   EDP_PSR_STATUS_AUX_ERROR		(1 << 15)
4193 #define   EDP_PSR_STATUS_AUX_SENDING		(1 << 12)
4194 #define   EDP_PSR_STATUS_SENDING_IDLE		(1 << 9)
4195 #define   EDP_PSR_STATUS_SENDING_TP2_TP3	(1 << 8)
4196 #define   EDP_PSR_STATUS_SENDING_TP1		(1 << 4)
4197 #define   EDP_PSR_STATUS_IDLE_MASK		0xf
4198 
4199 #define EDP_PSR_PERF_CNT		_MMIO(dev_priv->psr_mmio_base + 0x44)
4200 #define   EDP_PSR_PERF_CNT_MASK		0xffffff
4201 
4202 #define EDP_PSR_DEBUG				_MMIO(dev_priv->psr_mmio_base + 0x60) /* PSR_MASK on SKL+ */
4203 #define   EDP_PSR_DEBUG_MASK_MAX_SLEEP         (1 << 28)
4204 #define   EDP_PSR_DEBUG_MASK_LPSP              (1 << 27)
4205 #define   EDP_PSR_DEBUG_MASK_MEMUP             (1 << 26)
4206 #define   EDP_PSR_DEBUG_MASK_HPD               (1 << 25)
4207 #define   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE    (1 << 16) /* Reserved in ICL+ */
4208 #define   EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */
4209 
4210 #define EDP_PSR2_CTL			_MMIO(0x6f900)
4211 #define   EDP_PSR2_ENABLE		(1 << 31)
4212 #define   EDP_SU_TRACK_ENABLE		(1 << 30)
4213 #define   EDP_Y_COORDINATE_VALID	(1 << 26) /* GLK and CNL+ */
4214 #define   EDP_Y_COORDINATE_ENABLE	(1 << 25) /* GLK and CNL+ */
4215 #define   EDP_MAX_SU_DISABLE_TIME(t)	((t) << 20)
4216 #define   EDP_MAX_SU_DISABLE_TIME_MASK	(0x1f << 20)
4217 #define   EDP_PSR2_TP2_TIME_500us	(0 << 8)
4218 #define   EDP_PSR2_TP2_TIME_100us	(1 << 8)
4219 #define   EDP_PSR2_TP2_TIME_2500us	(2 << 8)
4220 #define   EDP_PSR2_TP2_TIME_50us	(3 << 8)
4221 #define   EDP_PSR2_TP2_TIME_MASK	(3 << 8)
4222 #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
4223 #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf << 4)
4224 #define   EDP_PSR2_FRAME_BEFORE_SU(a)	((a) << 4)
4225 #define   EDP_PSR2_IDLE_FRAME_MASK	0xf
4226 #define   EDP_PSR2_IDLE_FRAME_SHIFT	0
4227 
4228 #define _PSR_EVENT_TRANS_A			0x60848
4229 #define _PSR_EVENT_TRANS_B			0x61848
4230 #define _PSR_EVENT_TRANS_C			0x62848
4231 #define _PSR_EVENT_TRANS_D			0x63848
4232 #define _PSR_EVENT_TRANS_EDP			0x6F848
4233 #define PSR_EVENT(trans)			_MMIO_TRANS2(trans, _PSR_EVENT_TRANS_A)
4234 #define  PSR_EVENT_PSR2_WD_TIMER_EXPIRE		(1 << 17)
4235 #define  PSR_EVENT_PSR2_DISABLED		(1 << 16)
4236 #define  PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN	(1 << 15)
4237 #define  PSR_EVENT_SU_CRC_FIFO_UNDERRUN		(1 << 14)
4238 #define  PSR_EVENT_GRAPHICS_RESET		(1 << 12)
4239 #define  PSR_EVENT_PCH_INTERRUPT		(1 << 11)
4240 #define  PSR_EVENT_MEMORY_UP			(1 << 10)
4241 #define  PSR_EVENT_FRONT_BUFFER_MODIFY		(1 << 9)
4242 #define  PSR_EVENT_WD_TIMER_EXPIRE		(1 << 8)
4243 #define  PSR_EVENT_PIPE_REGISTERS_UPDATE	(1 << 6)
4244 #define  PSR_EVENT_REGISTER_UPDATE		(1 << 5) /* Reserved in ICL+ */
4245 #define  PSR_EVENT_HDCP_ENABLE			(1 << 4)
4246 #define  PSR_EVENT_KVMR_SESSION_ENABLE		(1 << 3)
4247 #define  PSR_EVENT_VBI_ENABLE			(1 << 2)
4248 #define  PSR_EVENT_LPSP_MODE_EXIT		(1 << 1)
4249 #define  PSR_EVENT_PSR_DISABLE			(1 << 0)
4250 
4251 #define EDP_PSR2_STATUS			_MMIO(0x6f940)
4252 #define EDP_PSR2_STATUS_STATE_MASK     (0xf << 28)
4253 #define EDP_PSR2_STATUS_STATE_SHIFT    28
4254 
4255 /* VGA port control */
4256 #define ADPA			_MMIO(0x61100)
4257 #define PCH_ADPA                _MMIO(0xe1100)
4258 #define VLV_ADPA		_MMIO(VLV_DISPLAY_BASE + 0x61100)
4259 
4260 #define   ADPA_DAC_ENABLE	(1 << 31)
4261 #define   ADPA_DAC_DISABLE	0
4262 #define   ADPA_PIPE_SEL_SHIFT		30
4263 #define   ADPA_PIPE_SEL_MASK		(1 << 30)
4264 #define   ADPA_PIPE_SEL(pipe)		((pipe) << 30)
4265 #define   ADPA_PIPE_SEL_SHIFT_CPT	29
4266 #define   ADPA_PIPE_SEL_MASK_CPT	(3 << 29)
4267 #define   ADPA_PIPE_SEL_CPT(pipe)	((pipe) << 29)
4268 #define   ADPA_CRT_HOTPLUG_MASK  0x03ff0000 /* bit 25-16 */
4269 #define   ADPA_CRT_HOTPLUG_MONITOR_NONE  (0 << 24)
4270 #define   ADPA_CRT_HOTPLUG_MONITOR_MASK  (3 << 24)
4271 #define   ADPA_CRT_HOTPLUG_MONITOR_COLOR (3 << 24)
4272 #define   ADPA_CRT_HOTPLUG_MONITOR_MONO  (2 << 24)
4273 #define   ADPA_CRT_HOTPLUG_ENABLE        (1 << 23)
4274 #define   ADPA_CRT_HOTPLUG_PERIOD_64     (0 << 22)
4275 #define   ADPA_CRT_HOTPLUG_PERIOD_128    (1 << 22)
4276 #define   ADPA_CRT_HOTPLUG_WARMUP_5MS    (0 << 21)
4277 #define   ADPA_CRT_HOTPLUG_WARMUP_10MS   (1 << 21)
4278 #define   ADPA_CRT_HOTPLUG_SAMPLE_2S     (0 << 20)
4279 #define   ADPA_CRT_HOTPLUG_SAMPLE_4S     (1 << 20)
4280 #define   ADPA_CRT_HOTPLUG_VOLTAGE_40    (0 << 18)
4281 #define   ADPA_CRT_HOTPLUG_VOLTAGE_50    (1 << 18)
4282 #define   ADPA_CRT_HOTPLUG_VOLTAGE_60    (2 << 18)
4283 #define   ADPA_CRT_HOTPLUG_VOLTAGE_70    (3 << 18)
4284 #define   ADPA_CRT_HOTPLUG_VOLREF_325MV  (0 << 17)
4285 #define   ADPA_CRT_HOTPLUG_VOLREF_475MV  (1 << 17)
4286 #define   ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1 << 16)
4287 #define   ADPA_USE_VGA_HVPOLARITY (1 << 15)
4288 #define   ADPA_SETS_HVPOLARITY	0
4289 #define   ADPA_VSYNC_CNTL_DISABLE (1 << 10)
4290 #define   ADPA_VSYNC_CNTL_ENABLE 0
4291 #define   ADPA_HSYNC_CNTL_DISABLE (1 << 11)
4292 #define   ADPA_HSYNC_CNTL_ENABLE 0
4293 #define   ADPA_VSYNC_ACTIVE_HIGH (1 << 4)
4294 #define   ADPA_VSYNC_ACTIVE_LOW	0
4295 #define   ADPA_HSYNC_ACTIVE_HIGH (1 << 3)
4296 #define   ADPA_HSYNC_ACTIVE_LOW	0
4297 #define   ADPA_DPMS_MASK	(~(3 << 10))
4298 #define   ADPA_DPMS_ON		(0 << 10)
4299 #define   ADPA_DPMS_SUSPEND	(1 << 10)
4300 #define   ADPA_DPMS_STANDBY	(2 << 10)
4301 #define   ADPA_DPMS_OFF		(3 << 10)
4302 
4303 
4304 /* Hotplug control (945+ only) */
4305 #define PORT_HOTPLUG_EN		_MMIO(dev_priv->info.display_mmio_offset + 0x61110)
4306 #define   PORTB_HOTPLUG_INT_EN			(1 << 29)
4307 #define   PORTC_HOTPLUG_INT_EN			(1 << 28)
4308 #define   PORTD_HOTPLUG_INT_EN			(1 << 27)
4309 #define   SDVOB_HOTPLUG_INT_EN			(1 << 26)
4310 #define   SDVOC_HOTPLUG_INT_EN			(1 << 25)
4311 #define   TV_HOTPLUG_INT_EN			(1 << 18)
4312 #define   CRT_HOTPLUG_INT_EN			(1 << 9)
4313 #define HOTPLUG_INT_EN_MASK			(PORTB_HOTPLUG_INT_EN | \
4314 						 PORTC_HOTPLUG_INT_EN | \
4315 						 PORTD_HOTPLUG_INT_EN | \
4316 						 SDVOC_HOTPLUG_INT_EN | \
4317 						 SDVOB_HOTPLUG_INT_EN | \
4318 						 CRT_HOTPLUG_INT_EN)
4319 #define   CRT_HOTPLUG_FORCE_DETECT		(1 << 3)
4320 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32	(0 << 8)
4321 /* must use period 64 on GM45 according to docs */
4322 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64	(1 << 8)
4323 #define CRT_HOTPLUG_DAC_ON_TIME_2M		(0 << 7)
4324 #define CRT_HOTPLUG_DAC_ON_TIME_4M		(1 << 7)
4325 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40		(0 << 5)
4326 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50		(1 << 5)
4327 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60		(2 << 5)
4328 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70		(3 << 5)
4329 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK	(3 << 5)
4330 #define CRT_HOTPLUG_DETECT_DELAY_1G		(0 << 4)
4331 #define CRT_HOTPLUG_DETECT_DELAY_2G		(1 << 4)
4332 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV	(0 << 2)
4333 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV	(1 << 2)
4334 
4335 #define PORT_HOTPLUG_STAT	_MMIO(dev_priv->info.display_mmio_offset + 0x61114)
4336 /*
4337  * HDMI/DP bits are g4x+
4338  *
4339  * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
4340  * Please check the detailed lore in the commit message for for experimental
4341  * evidence.
4342  */
4343 /* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */
4344 #define   PORTD_HOTPLUG_LIVE_STATUS_GM45	(1 << 29)
4345 #define   PORTC_HOTPLUG_LIVE_STATUS_GM45	(1 << 28)
4346 #define   PORTB_HOTPLUG_LIVE_STATUS_GM45	(1 << 27)
4347 /* G4X/VLV/CHV DP/HDMI bits again match Bspec */
4348 #define   PORTD_HOTPLUG_LIVE_STATUS_G4X		(1 << 27)
4349 #define   PORTC_HOTPLUG_LIVE_STATUS_G4X		(1 << 28)
4350 #define   PORTB_HOTPLUG_LIVE_STATUS_G4X		(1 << 29)
4351 #define   PORTD_HOTPLUG_INT_STATUS		(3 << 21)
4352 #define   PORTD_HOTPLUG_INT_LONG_PULSE		(2 << 21)
4353 #define   PORTD_HOTPLUG_INT_SHORT_PULSE		(1 << 21)
4354 #define   PORTC_HOTPLUG_INT_STATUS		(3 << 19)
4355 #define   PORTC_HOTPLUG_INT_LONG_PULSE		(2 << 19)
4356 #define   PORTC_HOTPLUG_INT_SHORT_PULSE		(1 << 19)
4357 #define   PORTB_HOTPLUG_INT_STATUS		(3 << 17)
4358 #define   PORTB_HOTPLUG_INT_LONG_PULSE		(2 << 17)
4359 #define   PORTB_HOTPLUG_INT_SHORT_PLUSE		(1 << 17)
4360 /* CRT/TV common between gen3+ */
4361 #define   CRT_HOTPLUG_INT_STATUS		(1 << 11)
4362 #define   TV_HOTPLUG_INT_STATUS			(1 << 10)
4363 #define   CRT_HOTPLUG_MONITOR_MASK		(3 << 8)
4364 #define   CRT_HOTPLUG_MONITOR_COLOR		(3 << 8)
4365 #define   CRT_HOTPLUG_MONITOR_MONO		(2 << 8)
4366 #define   CRT_HOTPLUG_MONITOR_NONE		(0 << 8)
4367 #define   DP_AUX_CHANNEL_D_INT_STATUS_G4X	(1 << 6)
4368 #define   DP_AUX_CHANNEL_C_INT_STATUS_G4X	(1 << 5)
4369 #define   DP_AUX_CHANNEL_B_INT_STATUS_G4X	(1 << 4)
4370 #define   DP_AUX_CHANNEL_MASK_INT_STATUS_G4X	(7 << 4)
4371 
4372 /* SDVO is different across gen3/4 */
4373 #define   SDVOC_HOTPLUG_INT_STATUS_G4X		(1 << 3)
4374 #define   SDVOB_HOTPLUG_INT_STATUS_G4X		(1 << 2)
4375 /*
4376  * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
4377  * since reality corrobates that they're the same as on gen3. But keep these
4378  * bits here (and the comment!) to help any other lost wanderers back onto the
4379  * right tracks.
4380  */
4381 #define   SDVOC_HOTPLUG_INT_STATUS_I965		(3 << 4)
4382 #define   SDVOB_HOTPLUG_INT_STATUS_I965		(3 << 2)
4383 #define   SDVOC_HOTPLUG_INT_STATUS_I915		(1 << 7)
4384 #define   SDVOB_HOTPLUG_INT_STATUS_I915		(1 << 6)
4385 #define   HOTPLUG_INT_STATUS_G4X		(CRT_HOTPLUG_INT_STATUS | \
4386 						 SDVOB_HOTPLUG_INT_STATUS_G4X | \
4387 						 SDVOC_HOTPLUG_INT_STATUS_G4X | \
4388 						 PORTB_HOTPLUG_INT_STATUS | \
4389 						 PORTC_HOTPLUG_INT_STATUS | \
4390 						 PORTD_HOTPLUG_INT_STATUS)
4391 
4392 #define HOTPLUG_INT_STATUS_I915			(CRT_HOTPLUG_INT_STATUS | \
4393 						 SDVOB_HOTPLUG_INT_STATUS_I915 | \
4394 						 SDVOC_HOTPLUG_INT_STATUS_I915 | \
4395 						 PORTB_HOTPLUG_INT_STATUS | \
4396 						 PORTC_HOTPLUG_INT_STATUS | \
4397 						 PORTD_HOTPLUG_INT_STATUS)
4398 
4399 /* SDVO and HDMI port control.
4400  * The same register may be used for SDVO or HDMI */
4401 #define _GEN3_SDVOB	0x61140
4402 #define _GEN3_SDVOC	0x61160
4403 #define GEN3_SDVOB	_MMIO(_GEN3_SDVOB)
4404 #define GEN3_SDVOC	_MMIO(_GEN3_SDVOC)
4405 #define GEN4_HDMIB	GEN3_SDVOB
4406 #define GEN4_HDMIC	GEN3_SDVOC
4407 #define VLV_HDMIB	_MMIO(VLV_DISPLAY_BASE + 0x61140)
4408 #define VLV_HDMIC	_MMIO(VLV_DISPLAY_BASE + 0x61160)
4409 #define CHV_HDMID	_MMIO(VLV_DISPLAY_BASE + 0x6116C)
4410 #define PCH_SDVOB	_MMIO(0xe1140)
4411 #define PCH_HDMIB	PCH_SDVOB
4412 #define PCH_HDMIC	_MMIO(0xe1150)
4413 #define PCH_HDMID	_MMIO(0xe1160)
4414 
4415 #define PORT_DFT_I9XX				_MMIO(0x61150)
4416 #define   DC_BALANCE_RESET			(1 << 25)
4417 #define PORT_DFT2_G4X		_MMIO(dev_priv->info.display_mmio_offset + 0x61154)
4418 #define   DC_BALANCE_RESET_VLV			(1 << 31)
4419 #define   PIPE_SCRAMBLE_RESET_MASK		((1 << 14) | (0x3 << 0))
4420 #define   PIPE_C_SCRAMBLE_RESET			(1 << 14) /* chv */
4421 #define   PIPE_B_SCRAMBLE_RESET			(1 << 1)
4422 #define   PIPE_A_SCRAMBLE_RESET			(1 << 0)
4423 
4424 /* Gen 3 SDVO bits: */
4425 #define   SDVO_ENABLE				(1 << 31)
4426 #define   SDVO_PIPE_SEL_SHIFT			30
4427 #define   SDVO_PIPE_SEL_MASK			(1 << 30)
4428 #define   SDVO_PIPE_SEL(pipe)			((pipe) << 30)
4429 #define   SDVO_STALL_SELECT			(1 << 29)
4430 #define   SDVO_INTERRUPT_ENABLE			(1 << 26)
4431 /*
4432  * 915G/GM SDVO pixel multiplier.
4433  * Programmed value is multiplier - 1, up to 5x.
4434  * \sa DPLL_MD_UDI_MULTIPLIER_MASK
4435  */
4436 #define   SDVO_PORT_MULTIPLY_MASK		(7 << 23)
4437 #define   SDVO_PORT_MULTIPLY_SHIFT		23
4438 #define   SDVO_PHASE_SELECT_MASK		(15 << 19)
4439 #define   SDVO_PHASE_SELECT_DEFAULT		(6 << 19)
4440 #define   SDVO_CLOCK_OUTPUT_INVERT		(1 << 18)
4441 #define   SDVOC_GANG_MODE			(1 << 16) /* Port C only */
4442 #define   SDVO_BORDER_ENABLE			(1 << 7) /* SDVO only */
4443 #define   SDVOB_PCIE_CONCURRENCY		(1 << 3) /* Port B only */
4444 #define   SDVO_DETECTED				(1 << 2)
4445 /* Bits to be preserved when writing */
4446 #define   SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
4447 			       SDVO_INTERRUPT_ENABLE)
4448 #define   SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
4449 
4450 /* Gen 4 SDVO/HDMI bits: */
4451 #define   SDVO_COLOR_FORMAT_8bpc		(0 << 26)
4452 #define   SDVO_COLOR_FORMAT_MASK		(7 << 26)
4453 #define   SDVO_ENCODING_SDVO			(0 << 10)
4454 #define   SDVO_ENCODING_HDMI			(2 << 10)
4455 #define   HDMI_MODE_SELECT_HDMI			(1 << 9) /* HDMI only */
4456 #define   HDMI_MODE_SELECT_DVI			(0 << 9) /* HDMI only */
4457 #define   HDMI_COLOR_RANGE_16_235		(1 << 8) /* HDMI only */
4458 #define   SDVO_AUDIO_ENABLE			(1 << 6)
4459 /* VSYNC/HSYNC bits new with 965, default is to be set */
4460 #define   SDVO_VSYNC_ACTIVE_HIGH		(1 << 4)
4461 #define   SDVO_HSYNC_ACTIVE_HIGH		(1 << 3)
4462 
4463 /* Gen 5 (IBX) SDVO/HDMI bits: */
4464 #define   HDMI_COLOR_FORMAT_12bpc		(3 << 26) /* HDMI only */
4465 #define   SDVOB_HOTPLUG_ENABLE			(1 << 23) /* SDVO only */
4466 
4467 /* Gen 6 (CPT) SDVO/HDMI bits: */
4468 #define   SDVO_PIPE_SEL_SHIFT_CPT		29
4469 #define   SDVO_PIPE_SEL_MASK_CPT		(3 << 29)
4470 #define   SDVO_PIPE_SEL_CPT(pipe)		((pipe) << 29)
4471 
4472 /* CHV SDVO/HDMI bits: */
4473 #define   SDVO_PIPE_SEL_SHIFT_CHV		24
4474 #define   SDVO_PIPE_SEL_MASK_CHV		(3 << 24)
4475 #define   SDVO_PIPE_SEL_CHV(pipe)		((pipe) << 24)
4476 
4477 
4478 /* DVO port control */
4479 #define _DVOA			0x61120
4480 #define DVOA			_MMIO(_DVOA)
4481 #define _DVOB			0x61140
4482 #define DVOB			_MMIO(_DVOB)
4483 #define _DVOC			0x61160
4484 #define DVOC			_MMIO(_DVOC)
4485 #define   DVO_ENABLE			(1 << 31)
4486 #define   DVO_PIPE_SEL_SHIFT		30
4487 #define   DVO_PIPE_SEL_MASK		(1 << 30)
4488 #define   DVO_PIPE_SEL(pipe)		((pipe) << 30)
4489 #define   DVO_PIPE_STALL_UNUSED		(0 << 28)
4490 #define   DVO_PIPE_STALL		(1 << 28)
4491 #define   DVO_PIPE_STALL_TV		(2 << 28)
4492 #define   DVO_PIPE_STALL_MASK		(3 << 28)
4493 #define   DVO_USE_VGA_SYNC		(1 << 15)
4494 #define   DVO_DATA_ORDER_I740		(0 << 14)
4495 #define   DVO_DATA_ORDER_FP		(1 << 14)
4496 #define   DVO_VSYNC_DISABLE		(1 << 11)
4497 #define   DVO_HSYNC_DISABLE		(1 << 10)
4498 #define   DVO_VSYNC_TRISTATE		(1 << 9)
4499 #define   DVO_HSYNC_TRISTATE		(1 << 8)
4500 #define   DVO_BORDER_ENABLE		(1 << 7)
4501 #define   DVO_DATA_ORDER_GBRG		(1 << 6)
4502 #define   DVO_DATA_ORDER_RGGB		(0 << 6)
4503 #define   DVO_DATA_ORDER_GBRG_ERRATA	(0 << 6)
4504 #define   DVO_DATA_ORDER_RGGB_ERRATA	(1 << 6)
4505 #define   DVO_VSYNC_ACTIVE_HIGH		(1 << 4)
4506 #define   DVO_HSYNC_ACTIVE_HIGH		(1 << 3)
4507 #define   DVO_BLANK_ACTIVE_HIGH		(1 << 2)
4508 #define   DVO_OUTPUT_CSTATE_PIXELS	(1 << 1)	/* SDG only */
4509 #define   DVO_OUTPUT_SOURCE_SIZE_PIXELS	(1 << 0)	/* SDG only */
4510 #define   DVO_PRESERVE_MASK		(0x7 << 24)
4511 #define DVOA_SRCDIM		_MMIO(0x61124)
4512 #define DVOB_SRCDIM		_MMIO(0x61144)
4513 #define DVOC_SRCDIM		_MMIO(0x61164)
4514 #define   DVO_SRCDIM_HORIZONTAL_SHIFT	12
4515 #define   DVO_SRCDIM_VERTICAL_SHIFT	0
4516 
4517 /* LVDS port control */
4518 #define LVDS			_MMIO(0x61180)
4519 /*
4520  * Enables the LVDS port.  This bit must be set before DPLLs are enabled, as
4521  * the DPLL semantics change when the LVDS is assigned to that pipe.
4522  */
4523 #define   LVDS_PORT_EN			(1 << 31)
4524 /* Selects pipe B for LVDS data.  Must be set on pre-965. */
4525 #define   LVDS_PIPE_SEL_SHIFT		30
4526 #define   LVDS_PIPE_SEL_MASK		(1 << 30)
4527 #define   LVDS_PIPE_SEL(pipe)		((pipe) << 30)
4528 #define   LVDS_PIPE_SEL_SHIFT_CPT	29
4529 #define   LVDS_PIPE_SEL_MASK_CPT	(3 << 29)
4530 #define   LVDS_PIPE_SEL_CPT(pipe)	((pipe) << 29)
4531 /* LVDS dithering flag on 965/g4x platform */
4532 #define   LVDS_ENABLE_DITHER		(1 << 25)
4533 /* LVDS sync polarity flags. Set to invert (i.e. negative) */
4534 #define   LVDS_VSYNC_POLARITY		(1 << 21)
4535 #define   LVDS_HSYNC_POLARITY		(1 << 20)
4536 
4537 /* Enable border for unscaled (or aspect-scaled) display */
4538 #define   LVDS_BORDER_ENABLE		(1 << 15)
4539 /*
4540  * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
4541  * pixel.
4542  */
4543 #define   LVDS_A0A2_CLKA_POWER_MASK	(3 << 8)
4544 #define   LVDS_A0A2_CLKA_POWER_DOWN	(0 << 8)
4545 #define   LVDS_A0A2_CLKA_POWER_UP	(3 << 8)
4546 /*
4547  * Controls the A3 data pair, which contains the additional LSBs for 24 bit
4548  * mode.  Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
4549  * on.
4550  */
4551 #define   LVDS_A3_POWER_MASK		(3 << 6)
4552 #define   LVDS_A3_POWER_DOWN		(0 << 6)
4553 #define   LVDS_A3_POWER_UP		(3 << 6)
4554 /*
4555  * Controls the CLKB pair.  This should only be set when LVDS_B0B3_POWER_UP
4556  * is set.
4557  */
4558 #define   LVDS_CLKB_POWER_MASK		(3 << 4)
4559 #define   LVDS_CLKB_POWER_DOWN		(0 << 4)
4560 #define   LVDS_CLKB_POWER_UP		(3 << 4)
4561 /*
4562  * Controls the B0-B3 data pairs.  This must be set to match the DPLL p2
4563  * setting for whether we are in dual-channel mode.  The B3 pair will
4564  * additionally only be powered up when LVDS_A3_POWER_UP is set.
4565  */
4566 #define   LVDS_B0B3_POWER_MASK		(3 << 2)
4567 #define   LVDS_B0B3_POWER_DOWN		(0 << 2)
4568 #define   LVDS_B0B3_POWER_UP		(3 << 2)
4569 
4570 /* Video Data Island Packet control */
4571 #define VIDEO_DIP_DATA		_MMIO(0x61178)
4572 /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
4573  * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
4574  * of the infoframe structure specified by CEA-861. */
4575 #define   VIDEO_DIP_DATA_SIZE	32
4576 #define   VIDEO_DIP_VSC_DATA_SIZE	36
4577 #define   VIDEO_DIP_PPS_DATA_SIZE	132
4578 #define VIDEO_DIP_CTL		_MMIO(0x61170)
4579 /* Pre HSW: */
4580 #define   VIDEO_DIP_ENABLE		(1 << 31)
4581 #define   VIDEO_DIP_PORT(port)		((port) << 29)
4582 #define   VIDEO_DIP_PORT_MASK		(3 << 29)
4583 #define   VIDEO_DIP_ENABLE_GCP		(1 << 25)
4584 #define   VIDEO_DIP_ENABLE_AVI		(1 << 21)
4585 #define   VIDEO_DIP_ENABLE_VENDOR	(2 << 21)
4586 #define   VIDEO_DIP_ENABLE_GAMUT	(4 << 21)
4587 #define   VIDEO_DIP_ENABLE_SPD		(8 << 21)
4588 #define   VIDEO_DIP_SELECT_AVI		(0 << 19)
4589 #define   VIDEO_DIP_SELECT_VENDOR	(1 << 19)
4590 #define   VIDEO_DIP_SELECT_SPD		(3 << 19)
4591 #define   VIDEO_DIP_SELECT_MASK		(3 << 19)
4592 #define   VIDEO_DIP_FREQ_ONCE		(0 << 16)
4593 #define   VIDEO_DIP_FREQ_VSYNC		(1 << 16)
4594 #define   VIDEO_DIP_FREQ_2VSYNC		(2 << 16)
4595 #define   VIDEO_DIP_FREQ_MASK		(3 << 16)
4596 /* HSW and later: */
4597 #define   DRM_DIP_ENABLE		(1 << 28)
4598 #define   PSR_VSC_BIT_7_SET		(1 << 27)
4599 #define   VSC_SELECT_MASK		(0x3 << 25)
4600 #define   VSC_SELECT_SHIFT		25
4601 #define   VSC_DIP_HW_HEA_DATA		(0 << 25)
4602 #define   VSC_DIP_HW_HEA_SW_DATA	(1 << 25)
4603 #define   VSC_DIP_HW_DATA_SW_HEA	(2 << 25)
4604 #define   VSC_DIP_SW_HEA_DATA		(3 << 25)
4605 #define   VDIP_ENABLE_PPS		(1 << 24)
4606 #define   VIDEO_DIP_ENABLE_VSC_HSW	(1 << 20)
4607 #define   VIDEO_DIP_ENABLE_GCP_HSW	(1 << 16)
4608 #define   VIDEO_DIP_ENABLE_AVI_HSW	(1 << 12)
4609 #define   VIDEO_DIP_ENABLE_VS_HSW	(1 << 8)
4610 #define   VIDEO_DIP_ENABLE_GMP_HSW	(1 << 4)
4611 #define   VIDEO_DIP_ENABLE_SPD_HSW	(1 << 0)
4612 
4613 /* Panel power sequencing */
4614 #define PPS_BASE			0x61200
4615 #define VLV_PPS_BASE			(VLV_DISPLAY_BASE + PPS_BASE)
4616 #define PCH_PPS_BASE			0xC7200
4617 
4618 #define _MMIO_PPS(pps_idx, reg)		_MMIO(dev_priv->pps_mmio_base -	\
4619 					      PPS_BASE + (reg) +	\
4620 					      (pps_idx) * 0x100)
4621 
4622 #define _PP_STATUS			0x61200
4623 #define PP_STATUS(pps_idx)		_MMIO_PPS(pps_idx, _PP_STATUS)
4624 #define   PP_ON				(1 << 31)
4625 
4626 #define _PP_CONTROL_1			0xc7204
4627 #define _PP_CONTROL_2			0xc7304
4628 #define ICP_PP_CONTROL(x)		_MMIO(((x) == 1) ? _PP_CONTROL_1 : \
4629 					      _PP_CONTROL_2)
4630 #define  POWER_CYCLE_DELAY_MASK	(0x1f << 4)
4631 #define  POWER_CYCLE_DELAY_SHIFT	4
4632 #define  VDD_OVERRIDE_FORCE		(1 << 3)
4633 #define  BACKLIGHT_ENABLE		(1 << 2)
4634 #define  PWR_DOWN_ON_RESET		(1 << 1)
4635 #define  PWR_STATE_TARGET		(1 << 0)
4636 /*
4637  * Indicates that all dependencies of the panel are on:
4638  *
4639  * - PLL enabled
4640  * - pipe enabled
4641  * - LVDS/DVOB/DVOC on
4642  */
4643 #define   PP_READY			(1 << 30)
4644 #define   PP_SEQUENCE_NONE		(0 << 28)
4645 #define   PP_SEQUENCE_POWER_UP		(1 << 28)
4646 #define   PP_SEQUENCE_POWER_DOWN	(2 << 28)
4647 #define   PP_SEQUENCE_MASK		(3 << 28)
4648 #define   PP_SEQUENCE_SHIFT		28
4649 #define   PP_CYCLE_DELAY_ACTIVE		(1 << 27)
4650 #define   PP_SEQUENCE_STATE_MASK	0x0000000f
4651 #define   PP_SEQUENCE_STATE_OFF_IDLE	(0x0 << 0)
4652 #define   PP_SEQUENCE_STATE_OFF_S0_1	(0x1 << 0)
4653 #define   PP_SEQUENCE_STATE_OFF_S0_2	(0x2 << 0)
4654 #define   PP_SEQUENCE_STATE_OFF_S0_3	(0x3 << 0)
4655 #define   PP_SEQUENCE_STATE_ON_IDLE	(0x8 << 0)
4656 #define   PP_SEQUENCE_STATE_ON_S1_0	(0x9 << 0)
4657 #define   PP_SEQUENCE_STATE_ON_S1_2	(0xa << 0)
4658 #define   PP_SEQUENCE_STATE_ON_S1_3	(0xb << 0)
4659 #define   PP_SEQUENCE_STATE_RESET	(0xf << 0)
4660 
4661 #define _PP_CONTROL			0x61204
4662 #define PP_CONTROL(pps_idx)		_MMIO_PPS(pps_idx, _PP_CONTROL)
4663 #define  PANEL_UNLOCK_REGS		(0xabcd << 16)
4664 #define  PANEL_UNLOCK_MASK		(0xffff << 16)
4665 #define  BXT_POWER_CYCLE_DELAY_MASK	0x1f0
4666 #define  BXT_POWER_CYCLE_DELAY_SHIFT	4
4667 #define  EDP_FORCE_VDD			(1 << 3)
4668 #define  EDP_BLC_ENABLE			(1 << 2)
4669 #define  PANEL_POWER_RESET		(1 << 1)
4670 #define  PANEL_POWER_OFF		(0 << 0)
4671 #define  PANEL_POWER_ON			(1 << 0)
4672 
4673 #define _PP_ON_DELAYS			0x61208
4674 #define PP_ON_DELAYS(pps_idx)		_MMIO_PPS(pps_idx, _PP_ON_DELAYS)
4675 #define  PANEL_PORT_SELECT_SHIFT	30
4676 #define  PANEL_PORT_SELECT_MASK		(3 << 30)
4677 #define  PANEL_PORT_SELECT_LVDS		(0 << 30)
4678 #define  PANEL_PORT_SELECT_DPA		(1 << 30)
4679 #define  PANEL_PORT_SELECT_DPC		(2 << 30)
4680 #define  PANEL_PORT_SELECT_DPD		(3 << 30)
4681 #define  PANEL_PORT_SELECT_VLV(port)	((port) << 30)
4682 #define  PANEL_POWER_UP_DELAY_MASK	0x1fff0000
4683 #define  PANEL_POWER_UP_DELAY_SHIFT	16
4684 #define  PANEL_LIGHT_ON_DELAY_MASK	0x1fff
4685 #define  PANEL_LIGHT_ON_DELAY_SHIFT	0
4686 
4687 #define _PP_OFF_DELAYS			0x6120C
4688 #define PP_OFF_DELAYS(pps_idx)		_MMIO_PPS(pps_idx, _PP_OFF_DELAYS)
4689 #define  PANEL_POWER_DOWN_DELAY_MASK	0x1fff0000
4690 #define  PANEL_POWER_DOWN_DELAY_SHIFT	16
4691 #define  PANEL_LIGHT_OFF_DELAY_MASK	0x1fff
4692 #define  PANEL_LIGHT_OFF_DELAY_SHIFT	0
4693 
4694 #define _PP_DIVISOR			0x61210
4695 #define PP_DIVISOR(pps_idx)		_MMIO_PPS(pps_idx, _PP_DIVISOR)
4696 #define  PP_REFERENCE_DIVIDER_MASK	0xffffff00
4697 #define  PP_REFERENCE_DIVIDER_SHIFT	8
4698 #define  PANEL_POWER_CYCLE_DELAY_MASK	0x1f
4699 #define  PANEL_POWER_CYCLE_DELAY_SHIFT	0
4700 
4701 /* Panel fitting */
4702 #define PFIT_CONTROL	_MMIO(dev_priv->info.display_mmio_offset + 0x61230)
4703 #define   PFIT_ENABLE		(1 << 31)
4704 #define   PFIT_PIPE_MASK	(3 << 29)
4705 #define   PFIT_PIPE_SHIFT	29
4706 #define   VERT_INTERP_DISABLE	(0 << 10)
4707 #define   VERT_INTERP_BILINEAR	(1 << 10)
4708 #define   VERT_INTERP_MASK	(3 << 10)
4709 #define   VERT_AUTO_SCALE	(1 << 9)
4710 #define   HORIZ_INTERP_DISABLE	(0 << 6)
4711 #define   HORIZ_INTERP_BILINEAR	(1 << 6)
4712 #define   HORIZ_INTERP_MASK	(3 << 6)
4713 #define   HORIZ_AUTO_SCALE	(1 << 5)
4714 #define   PANEL_8TO6_DITHER_ENABLE (1 << 3)
4715 #define   PFIT_FILTER_FUZZY	(0 << 24)
4716 #define   PFIT_SCALING_AUTO	(0 << 26)
4717 #define   PFIT_SCALING_PROGRAMMED (1 << 26)
4718 #define   PFIT_SCALING_PILLAR	(2 << 26)
4719 #define   PFIT_SCALING_LETTER	(3 << 26)
4720 #define PFIT_PGM_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61234)
4721 /* Pre-965 */
4722 #define		PFIT_VERT_SCALE_SHIFT		20
4723 #define		PFIT_VERT_SCALE_MASK		0xfff00000
4724 #define		PFIT_HORIZ_SCALE_SHIFT		4
4725 #define		PFIT_HORIZ_SCALE_MASK		0x0000fff0
4726 /* 965+ */
4727 #define		PFIT_VERT_SCALE_SHIFT_965	16
4728 #define		PFIT_VERT_SCALE_MASK_965	0x1fff0000
4729 #define		PFIT_HORIZ_SCALE_SHIFT_965	0
4730 #define		PFIT_HORIZ_SCALE_MASK_965	0x00001fff
4731 
4732 #define PFIT_AUTO_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61238)
4733 
4734 #define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
4735 #define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
4736 #define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
4737 					 _VLV_BLC_PWM_CTL2_B)
4738 
4739 #define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
4740 #define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
4741 #define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
4742 					_VLV_BLC_PWM_CTL_B)
4743 
4744 #define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
4745 #define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
4746 #define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
4747 					 _VLV_BLC_HIST_CTL_B)
4748 
4749 /* Backlight control */
4750 #define BLC_PWM_CTL2	_MMIO(dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
4751 #define   BLM_PWM_ENABLE		(1 << 31)
4752 #define   BLM_COMBINATION_MODE		(1 << 30) /* gen4 only */
4753 #define   BLM_PIPE_SELECT		(1 << 29)
4754 #define   BLM_PIPE_SELECT_IVB		(3 << 29)
4755 #define   BLM_PIPE_A			(0 << 29)
4756 #define   BLM_PIPE_B			(1 << 29)
4757 #define   BLM_PIPE_C			(2 << 29) /* ivb + */
4758 #define   BLM_TRANSCODER_A		BLM_PIPE_A /* hsw */
4759 #define   BLM_TRANSCODER_B		BLM_PIPE_B
4760 #define   BLM_TRANSCODER_C		BLM_PIPE_C
4761 #define   BLM_TRANSCODER_EDP		(3 << 29)
4762 #define   BLM_PIPE(pipe)		((pipe) << 29)
4763 #define   BLM_POLARITY_I965		(1 << 28) /* gen4 only */
4764 #define   BLM_PHASE_IN_INTERUPT_STATUS	(1 << 26)
4765 #define   BLM_PHASE_IN_ENABLE		(1 << 25)
4766 #define   BLM_PHASE_IN_INTERUPT_ENABL	(1 << 24)
4767 #define   BLM_PHASE_IN_TIME_BASE_SHIFT	(16)
4768 #define   BLM_PHASE_IN_TIME_BASE_MASK	(0xff << 16)
4769 #define   BLM_PHASE_IN_COUNT_SHIFT	(8)
4770 #define   BLM_PHASE_IN_COUNT_MASK	(0xff << 8)
4771 #define   BLM_PHASE_IN_INCR_SHIFT	(0)
4772 #define   BLM_PHASE_IN_INCR_MASK	(0xff << 0)
4773 #define BLC_PWM_CTL	_MMIO(dev_priv->info.display_mmio_offset + 0x61254)
4774 /*
4775  * This is the most significant 15 bits of the number of backlight cycles in a
4776  * complete cycle of the modulated backlight control.
4777  *
4778  * The actual value is this field multiplied by two.
4779  */
4780 #define   BACKLIGHT_MODULATION_FREQ_SHIFT	(17)
4781 #define   BACKLIGHT_MODULATION_FREQ_MASK	(0x7fff << 17)
4782 #define   BLM_LEGACY_MODE			(1 << 16) /* gen2 only */
4783 /*
4784  * This is the number of cycles out of the backlight modulation cycle for which
4785  * the backlight is on.
4786  *
4787  * This field must be no greater than the number of cycles in the complete
4788  * backlight modulation cycle.
4789  */
4790 #define   BACKLIGHT_DUTY_CYCLE_SHIFT		(0)
4791 #define   BACKLIGHT_DUTY_CYCLE_MASK		(0xffff)
4792 #define   BACKLIGHT_DUTY_CYCLE_MASK_PNV		(0xfffe)
4793 #define   BLM_POLARITY_PNV			(1 << 0) /* pnv only */
4794 
4795 #define BLC_HIST_CTL	_MMIO(dev_priv->info.display_mmio_offset + 0x61260)
4796 #define  BLM_HISTOGRAM_ENABLE			(1 << 31)
4797 
4798 /* New registers for PCH-split platforms. Safe where new bits show up, the
4799  * register layout machtes with gen4 BLC_PWM_CTL[12]. */
4800 #define BLC_PWM_CPU_CTL2	_MMIO(0x48250)
4801 #define BLC_PWM_CPU_CTL		_MMIO(0x48254)
4802 
4803 #define HSW_BLC_PWM2_CTL	_MMIO(0x48350)
4804 
4805 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
4806  * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
4807 #define BLC_PWM_PCH_CTL1	_MMIO(0xc8250)
4808 #define   BLM_PCH_PWM_ENABLE			(1 << 31)
4809 #define   BLM_PCH_OVERRIDE_ENABLE		(1 << 30)
4810 #define   BLM_PCH_POLARITY			(1 << 29)
4811 #define BLC_PWM_PCH_CTL2	_MMIO(0xc8254)
4812 
4813 #define UTIL_PIN_CTL		_MMIO(0x48400)
4814 #define   UTIL_PIN_ENABLE	(1 << 31)
4815 
4816 #define   UTIL_PIN_PIPE(x)     ((x) << 29)
4817 #define   UTIL_PIN_PIPE_MASK   (3 << 29)
4818 #define   UTIL_PIN_MODE_PWM    (1 << 24)
4819 #define   UTIL_PIN_MODE_MASK   (0xf << 24)
4820 #define   UTIL_PIN_POLARITY    (1 << 22)
4821 
4822 /* BXT backlight register definition. */
4823 #define _BXT_BLC_PWM_CTL1			0xC8250
4824 #define   BXT_BLC_PWM_ENABLE			(1 << 31)
4825 #define   BXT_BLC_PWM_POLARITY			(1 << 29)
4826 #define _BXT_BLC_PWM_FREQ1			0xC8254
4827 #define _BXT_BLC_PWM_DUTY1			0xC8258
4828 
4829 #define _BXT_BLC_PWM_CTL2			0xC8350
4830 #define _BXT_BLC_PWM_FREQ2			0xC8354
4831 #define _BXT_BLC_PWM_DUTY2			0xC8358
4832 
4833 #define BXT_BLC_PWM_CTL(controller)    _MMIO_PIPE(controller,		\
4834 					_BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
4835 #define BXT_BLC_PWM_FREQ(controller)   _MMIO_PIPE(controller, \
4836 					_BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
4837 #define BXT_BLC_PWM_DUTY(controller)   _MMIO_PIPE(controller, \
4838 					_BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
4839 
4840 #define PCH_GTC_CTL		_MMIO(0xe7000)
4841 #define   PCH_GTC_ENABLE	(1 << 31)
4842 
4843 /* TV port control */
4844 #define TV_CTL			_MMIO(0x68000)
4845 /* Enables the TV encoder */
4846 # define TV_ENC_ENABLE			(1 << 31)
4847 /* Sources the TV encoder input from pipe B instead of A. */
4848 # define TV_ENC_PIPE_SEL_SHIFT		30
4849 # define TV_ENC_PIPE_SEL_MASK		(1 << 30)
4850 # define TV_ENC_PIPE_SEL(pipe)		((pipe) << 30)
4851 /* Outputs composite video (DAC A only) */
4852 # define TV_ENC_OUTPUT_COMPOSITE	(0 << 28)
4853 /* Outputs SVideo video (DAC B/C) */
4854 # define TV_ENC_OUTPUT_SVIDEO		(1 << 28)
4855 /* Outputs Component video (DAC A/B/C) */
4856 # define TV_ENC_OUTPUT_COMPONENT	(2 << 28)
4857 /* Outputs Composite and SVideo (DAC A/B/C) */
4858 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE	(3 << 28)
4859 # define TV_TRILEVEL_SYNC		(1 << 21)
4860 /* Enables slow sync generation (945GM only) */
4861 # define TV_SLOW_SYNC			(1 << 20)
4862 /* Selects 4x oversampling for 480i and 576p */
4863 # define TV_OVERSAMPLE_4X		(0 << 18)
4864 /* Selects 2x oversampling for 720p and 1080i */
4865 # define TV_OVERSAMPLE_2X		(1 << 18)
4866 /* Selects no oversampling for 1080p */
4867 # define TV_OVERSAMPLE_NONE		(2 << 18)
4868 /* Selects 8x oversampling */
4869 # define TV_OVERSAMPLE_8X		(3 << 18)
4870 /* Selects progressive mode rather than interlaced */
4871 # define TV_PROGRESSIVE			(1 << 17)
4872 /* Sets the colorburst to PAL mode.  Required for non-M PAL modes. */
4873 # define TV_PAL_BURST			(1 << 16)
4874 /* Field for setting delay of Y compared to C */
4875 # define TV_YC_SKEW_MASK		(7 << 12)
4876 /* Enables a fix for 480p/576p standard definition modes on the 915GM only */
4877 # define TV_ENC_SDP_FIX			(1 << 11)
4878 /*
4879  * Enables a fix for the 915GM only.
4880  *
4881  * Not sure what it does.
4882  */
4883 # define TV_ENC_C0_FIX			(1 << 10)
4884 /* Bits that must be preserved by software */
4885 # define TV_CTL_SAVE			((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
4886 # define TV_FUSE_STATE_MASK		(3 << 4)
4887 /* Read-only state that reports all features enabled */
4888 # define TV_FUSE_STATE_ENABLED		(0 << 4)
4889 /* Read-only state that reports that Macrovision is disabled in hardware*/
4890 # define TV_FUSE_STATE_NO_MACROVISION	(1 << 4)
4891 /* Read-only state that reports that TV-out is disabled in hardware. */
4892 # define TV_FUSE_STATE_DISABLED		(2 << 4)
4893 /* Normal operation */
4894 # define TV_TEST_MODE_NORMAL		(0 << 0)
4895 /* Encoder test pattern 1 - combo pattern */
4896 # define TV_TEST_MODE_PATTERN_1		(1 << 0)
4897 /* Encoder test pattern 2 - full screen vertical 75% color bars */
4898 # define TV_TEST_MODE_PATTERN_2		(2 << 0)
4899 /* Encoder test pattern 3 - full screen horizontal 75% color bars */
4900 # define TV_TEST_MODE_PATTERN_3		(3 << 0)
4901 /* Encoder test pattern 4 - random noise */
4902 # define TV_TEST_MODE_PATTERN_4		(4 << 0)
4903 /* Encoder test pattern 5 - linear color ramps */
4904 # define TV_TEST_MODE_PATTERN_5		(5 << 0)
4905 /*
4906  * This test mode forces the DACs to 50% of full output.
4907  *
4908  * This is used for load detection in combination with TVDAC_SENSE_MASK
4909  */
4910 # define TV_TEST_MODE_MONITOR_DETECT	(7 << 0)
4911 # define TV_TEST_MODE_MASK		(7 << 0)
4912 
4913 #define TV_DAC			_MMIO(0x68004)
4914 # define TV_DAC_SAVE		0x00ffff00
4915 /*
4916  * Reports that DAC state change logic has reported change (RO).
4917  *
4918  * This gets cleared when TV_DAC_STATE_EN is cleared
4919 */
4920 # define TVDAC_STATE_CHG		(1 << 31)
4921 # define TVDAC_SENSE_MASK		(7 << 28)
4922 /* Reports that DAC A voltage is above the detect threshold */
4923 # define TVDAC_A_SENSE			(1 << 30)
4924 /* Reports that DAC B voltage is above the detect threshold */
4925 # define TVDAC_B_SENSE			(1 << 29)
4926 /* Reports that DAC C voltage is above the detect threshold */
4927 # define TVDAC_C_SENSE			(1 << 28)
4928 /*
4929  * Enables DAC state detection logic, for load-based TV detection.
4930  *
4931  * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
4932  * to off, for load detection to work.
4933  */
4934 # define TVDAC_STATE_CHG_EN		(1 << 27)
4935 /* Sets the DAC A sense value to high */
4936 # define TVDAC_A_SENSE_CTL		(1 << 26)
4937 /* Sets the DAC B sense value to high */
4938 # define TVDAC_B_SENSE_CTL		(1 << 25)
4939 /* Sets the DAC C sense value to high */
4940 # define TVDAC_C_SENSE_CTL		(1 << 24)
4941 /* Overrides the ENC_ENABLE and DAC voltage levels */
4942 # define DAC_CTL_OVERRIDE		(1 << 7)
4943 /* Sets the slew rate.  Must be preserved in software */
4944 # define ENC_TVDAC_SLEW_FAST		(1 << 6)
4945 # define DAC_A_1_3_V			(0 << 4)
4946 # define DAC_A_1_1_V			(1 << 4)
4947 # define DAC_A_0_7_V			(2 << 4)
4948 # define DAC_A_MASK			(3 << 4)
4949 # define DAC_B_1_3_V			(0 << 2)
4950 # define DAC_B_1_1_V			(1 << 2)
4951 # define DAC_B_0_7_V			(2 << 2)
4952 # define DAC_B_MASK			(3 << 2)
4953 # define DAC_C_1_3_V			(0 << 0)
4954 # define DAC_C_1_1_V			(1 << 0)
4955 # define DAC_C_0_7_V			(2 << 0)
4956 # define DAC_C_MASK			(3 << 0)
4957 
4958 /*
4959  * CSC coefficients are stored in a floating point format with 9 bits of
4960  * mantissa and 2 or 3 bits of exponent.  The exponent is represented as 2**-n,
4961  * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
4962  * -1 (0x3) being the only legal negative value.
4963  */
4964 #define TV_CSC_Y		_MMIO(0x68010)
4965 # define TV_RY_MASK			0x07ff0000
4966 # define TV_RY_SHIFT			16
4967 # define TV_GY_MASK			0x00000fff
4968 # define TV_GY_SHIFT			0
4969 
4970 #define TV_CSC_Y2		_MMIO(0x68014)
4971 # define TV_BY_MASK			0x07ff0000
4972 # define TV_BY_SHIFT			16
4973 /*
4974  * Y attenuation for component video.
4975  *
4976  * Stored in 1.9 fixed point.
4977  */
4978 # define TV_AY_MASK			0x000003ff
4979 # define TV_AY_SHIFT			0
4980 
4981 #define TV_CSC_U		_MMIO(0x68018)
4982 # define TV_RU_MASK			0x07ff0000
4983 # define TV_RU_SHIFT			16
4984 # define TV_GU_MASK			0x000007ff
4985 # define TV_GU_SHIFT			0
4986 
4987 #define TV_CSC_U2		_MMIO(0x6801c)
4988 # define TV_BU_MASK			0x07ff0000
4989 # define TV_BU_SHIFT			16
4990 /*
4991  * U attenuation for component video.
4992  *
4993  * Stored in 1.9 fixed point.
4994  */
4995 # define TV_AU_MASK			0x000003ff
4996 # define TV_AU_SHIFT			0
4997 
4998 #define TV_CSC_V		_MMIO(0x68020)
4999 # define TV_RV_MASK			0x0fff0000
5000 # define TV_RV_SHIFT			16
5001 # define TV_GV_MASK			0x000007ff
5002 # define TV_GV_SHIFT			0
5003 
5004 #define TV_CSC_V2		_MMIO(0x68024)
5005 # define TV_BV_MASK			0x07ff0000
5006 # define TV_BV_SHIFT			16
5007 /*
5008  * V attenuation for component video.
5009  *
5010  * Stored in 1.9 fixed point.
5011  */
5012 # define TV_AV_MASK			0x000007ff
5013 # define TV_AV_SHIFT			0
5014 
5015 #define TV_CLR_KNOBS		_MMIO(0x68028)
5016 /* 2s-complement brightness adjustment */
5017 # define TV_BRIGHTNESS_MASK		0xff000000
5018 # define TV_BRIGHTNESS_SHIFT		24
5019 /* Contrast adjustment, as a 2.6 unsigned floating point number */
5020 # define TV_CONTRAST_MASK		0x00ff0000
5021 # define TV_CONTRAST_SHIFT		16
5022 /* Saturation adjustment, as a 2.6 unsigned floating point number */
5023 # define TV_SATURATION_MASK		0x0000ff00
5024 # define TV_SATURATION_SHIFT		8
5025 /* Hue adjustment, as an integer phase angle in degrees */
5026 # define TV_HUE_MASK			0x000000ff
5027 # define TV_HUE_SHIFT			0
5028 
5029 #define TV_CLR_LEVEL		_MMIO(0x6802c)
5030 /* Controls the DAC level for black */
5031 # define TV_BLACK_LEVEL_MASK		0x01ff0000
5032 # define TV_BLACK_LEVEL_SHIFT		16
5033 /* Controls the DAC level for blanking */
5034 # define TV_BLANK_LEVEL_MASK		0x000001ff
5035 # define TV_BLANK_LEVEL_SHIFT		0
5036 
5037 #define TV_H_CTL_1		_MMIO(0x68030)
5038 /* Number of pixels in the hsync. */
5039 # define TV_HSYNC_END_MASK		0x1fff0000
5040 # define TV_HSYNC_END_SHIFT		16
5041 /* Total number of pixels minus one in the line (display and blanking). */
5042 # define TV_HTOTAL_MASK			0x00001fff
5043 # define TV_HTOTAL_SHIFT		0
5044 
5045 #define TV_H_CTL_2		_MMIO(0x68034)
5046 /* Enables the colorburst (needed for non-component color) */
5047 # define TV_BURST_ENA			(1 << 31)
5048 /* Offset of the colorburst from the start of hsync, in pixels minus one. */
5049 # define TV_HBURST_START_SHIFT		16
5050 # define TV_HBURST_START_MASK		0x1fff0000
5051 /* Length of the colorburst */
5052 # define TV_HBURST_LEN_SHIFT		0
5053 # define TV_HBURST_LEN_MASK		0x0001fff
5054 
5055 #define TV_H_CTL_3		_MMIO(0x68038)
5056 /* End of hblank, measured in pixels minus one from start of hsync */
5057 # define TV_HBLANK_END_SHIFT		16
5058 # define TV_HBLANK_END_MASK		0x1fff0000
5059 /* Start of hblank, measured in pixels minus one from start of hsync */
5060 # define TV_HBLANK_START_SHIFT		0
5061 # define TV_HBLANK_START_MASK		0x0001fff
5062 
5063 #define TV_V_CTL_1		_MMIO(0x6803c)
5064 /* XXX */
5065 # define TV_NBR_END_SHIFT		16
5066 # define TV_NBR_END_MASK		0x07ff0000
5067 /* XXX */
5068 # define TV_VI_END_F1_SHIFT		8
5069 # define TV_VI_END_F1_MASK		0x00003f00
5070 /* XXX */
5071 # define TV_VI_END_F2_SHIFT		0
5072 # define TV_VI_END_F2_MASK		0x0000003f
5073 
5074 #define TV_V_CTL_2		_MMIO(0x68040)
5075 /* Length of vsync, in half lines */
5076 # define TV_VSYNC_LEN_MASK		0x07ff0000
5077 # define TV_VSYNC_LEN_SHIFT		16
5078 /* Offset of the start of vsync in field 1, measured in one less than the
5079  * number of half lines.
5080  */
5081 # define TV_VSYNC_START_F1_MASK		0x00007f00
5082 # define TV_VSYNC_START_F1_SHIFT	8
5083 /*
5084  * Offset of the start of vsync in field 2, measured in one less than the
5085  * number of half lines.
5086  */
5087 # define TV_VSYNC_START_F2_MASK		0x0000007f
5088 # define TV_VSYNC_START_F2_SHIFT	0
5089 
5090 #define TV_V_CTL_3		_MMIO(0x68044)
5091 /* Enables generation of the equalization signal */
5092 # define TV_EQUAL_ENA			(1 << 31)
5093 /* Length of vsync, in half lines */
5094 # define TV_VEQ_LEN_MASK		0x007f0000
5095 # define TV_VEQ_LEN_SHIFT		16
5096 /* Offset of the start of equalization in field 1, measured in one less than
5097  * the number of half lines.
5098  */
5099 # define TV_VEQ_START_F1_MASK		0x0007f00
5100 # define TV_VEQ_START_F1_SHIFT		8
5101 /*
5102  * Offset of the start of equalization in field 2, measured in one less than
5103  * the number of half lines.
5104  */
5105 # define TV_VEQ_START_F2_MASK		0x000007f
5106 # define TV_VEQ_START_F2_SHIFT		0
5107 
5108 #define TV_V_CTL_4		_MMIO(0x68048)
5109 /*
5110  * Offset to start of vertical colorburst, measured in one less than the
5111  * number of lines from vertical start.
5112  */
5113 # define TV_VBURST_START_F1_MASK	0x003f0000
5114 # define TV_VBURST_START_F1_SHIFT	16
5115 /*
5116  * Offset to the end of vertical colorburst, measured in one less than the
5117  * number of lines from the start of NBR.
5118  */
5119 # define TV_VBURST_END_F1_MASK		0x000000ff
5120 # define TV_VBURST_END_F1_SHIFT		0
5121 
5122 #define TV_V_CTL_5		_MMIO(0x6804c)
5123 /*
5124  * Offset to start of vertical colorburst, measured in one less than the
5125  * number of lines from vertical start.
5126  */
5127 # define TV_VBURST_START_F2_MASK	0x003f0000
5128 # define TV_VBURST_START_F2_SHIFT	16
5129 /*
5130  * Offset to the end of vertical colorburst, measured in one less than the
5131  * number of lines from the start of NBR.
5132  */
5133 # define TV_VBURST_END_F2_MASK		0x000000ff
5134 # define TV_VBURST_END_F2_SHIFT		0
5135 
5136 #define TV_V_CTL_6		_MMIO(0x68050)
5137 /*
5138  * Offset to start of vertical colorburst, measured in one less than the
5139  * number of lines from vertical start.
5140  */
5141 # define TV_VBURST_START_F3_MASK	0x003f0000
5142 # define TV_VBURST_START_F3_SHIFT	16
5143 /*
5144  * Offset to the end of vertical colorburst, measured in one less than the
5145  * number of lines from the start of NBR.
5146  */
5147 # define TV_VBURST_END_F3_MASK		0x000000ff
5148 # define TV_VBURST_END_F3_SHIFT		0
5149 
5150 #define TV_V_CTL_7		_MMIO(0x68054)
5151 /*
5152  * Offset to start of vertical colorburst, measured in one less than the
5153  * number of lines from vertical start.
5154  */
5155 # define TV_VBURST_START_F4_MASK	0x003f0000
5156 # define TV_VBURST_START_F4_SHIFT	16
5157 /*
5158  * Offset to the end of vertical colorburst, measured in one less than the
5159  * number of lines from the start of NBR.
5160  */
5161 # define TV_VBURST_END_F4_MASK		0x000000ff
5162 # define TV_VBURST_END_F4_SHIFT		0
5163 
5164 #define TV_SC_CTL_1		_MMIO(0x68060)
5165 /* Turns on the first subcarrier phase generation DDA */
5166 # define TV_SC_DDA1_EN			(1 << 31)
5167 /* Turns on the first subcarrier phase generation DDA */
5168 # define TV_SC_DDA2_EN			(1 << 30)
5169 /* Turns on the first subcarrier phase generation DDA */
5170 # define TV_SC_DDA3_EN			(1 << 29)
5171 /* Sets the subcarrier DDA to reset frequency every other field */
5172 # define TV_SC_RESET_EVERY_2		(0 << 24)
5173 /* Sets the subcarrier DDA to reset frequency every fourth field */
5174 # define TV_SC_RESET_EVERY_4		(1 << 24)
5175 /* Sets the subcarrier DDA to reset frequency every eighth field */
5176 # define TV_SC_RESET_EVERY_8		(2 << 24)
5177 /* Sets the subcarrier DDA to never reset the frequency */
5178 # define TV_SC_RESET_NEVER		(3 << 24)
5179 /* Sets the peak amplitude of the colorburst.*/
5180 # define TV_BURST_LEVEL_MASK		0x00ff0000
5181 # define TV_BURST_LEVEL_SHIFT		16
5182 /* Sets the increment of the first subcarrier phase generation DDA */
5183 # define TV_SCDDA1_INC_MASK		0x00000fff
5184 # define TV_SCDDA1_INC_SHIFT		0
5185 
5186 #define TV_SC_CTL_2		_MMIO(0x68064)
5187 /* Sets the rollover for the second subcarrier phase generation DDA */
5188 # define TV_SCDDA2_SIZE_MASK		0x7fff0000
5189 # define TV_SCDDA2_SIZE_SHIFT		16
5190 /* Sets the increent of the second subcarrier phase generation DDA */
5191 # define TV_SCDDA2_INC_MASK		0x00007fff
5192 # define TV_SCDDA2_INC_SHIFT		0
5193 
5194 #define TV_SC_CTL_3		_MMIO(0x68068)
5195 /* Sets the rollover for the third subcarrier phase generation DDA */
5196 # define TV_SCDDA3_SIZE_MASK		0x7fff0000
5197 # define TV_SCDDA3_SIZE_SHIFT		16
5198 /* Sets the increent of the third subcarrier phase generation DDA */
5199 # define TV_SCDDA3_INC_MASK		0x00007fff
5200 # define TV_SCDDA3_INC_SHIFT		0
5201 
5202 #define TV_WIN_POS		_MMIO(0x68070)
5203 /* X coordinate of the display from the start of horizontal active */
5204 # define TV_XPOS_MASK			0x1fff0000
5205 # define TV_XPOS_SHIFT			16
5206 /* Y coordinate of the display from the start of vertical active (NBR) */
5207 # define TV_YPOS_MASK			0x00000fff
5208 # define TV_YPOS_SHIFT			0
5209 
5210 #define TV_WIN_SIZE		_MMIO(0x68074)
5211 /* Horizontal size of the display window, measured in pixels*/
5212 # define TV_XSIZE_MASK			0x1fff0000
5213 # define TV_XSIZE_SHIFT			16
5214 /*
5215  * Vertical size of the display window, measured in pixels.
5216  *
5217  * Must be even for interlaced modes.
5218  */
5219 # define TV_YSIZE_MASK			0x00000fff
5220 # define TV_YSIZE_SHIFT			0
5221 
5222 #define TV_FILTER_CTL_1		_MMIO(0x68080)
5223 /*
5224  * Enables automatic scaling calculation.
5225  *
5226  * If set, the rest of the registers are ignored, and the calculated values can
5227  * be read back from the register.
5228  */
5229 # define TV_AUTO_SCALE			(1 << 31)
5230 /*
5231  * Disables the vertical filter.
5232  *
5233  * This is required on modes more than 1024 pixels wide */
5234 # define TV_V_FILTER_BYPASS		(1 << 29)
5235 /* Enables adaptive vertical filtering */
5236 # define TV_VADAPT			(1 << 28)
5237 # define TV_VADAPT_MODE_MASK		(3 << 26)
5238 /* Selects the least adaptive vertical filtering mode */
5239 # define TV_VADAPT_MODE_LEAST		(0 << 26)
5240 /* Selects the moderately adaptive vertical filtering mode */
5241 # define TV_VADAPT_MODE_MODERATE	(1 << 26)
5242 /* Selects the most adaptive vertical filtering mode */
5243 # define TV_VADAPT_MODE_MOST		(3 << 26)
5244 /*
5245  * Sets the horizontal scaling factor.
5246  *
5247  * This should be the fractional part of the horizontal scaling factor divided
5248  * by the oversampling rate.  TV_HSCALE should be less than 1, and set to:
5249  *
5250  * (src width - 1) / ((oversample * dest width) - 1)
5251  */
5252 # define TV_HSCALE_FRAC_MASK		0x00003fff
5253 # define TV_HSCALE_FRAC_SHIFT		0
5254 
5255 #define TV_FILTER_CTL_2		_MMIO(0x68084)
5256 /*
5257  * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
5258  *
5259  * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
5260  */
5261 # define TV_VSCALE_INT_MASK		0x00038000
5262 # define TV_VSCALE_INT_SHIFT		15
5263 /*
5264  * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
5265  *
5266  * \sa TV_VSCALE_INT_MASK
5267  */
5268 # define TV_VSCALE_FRAC_MASK		0x00007fff
5269 # define TV_VSCALE_FRAC_SHIFT		0
5270 
5271 #define TV_FILTER_CTL_3		_MMIO(0x68088)
5272 /*
5273  * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
5274  *
5275  * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
5276  *
5277  * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
5278  */
5279 # define TV_VSCALE_IP_INT_MASK		0x00038000
5280 # define TV_VSCALE_IP_INT_SHIFT		15
5281 /*
5282  * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
5283  *
5284  * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
5285  *
5286  * \sa TV_VSCALE_IP_INT_MASK
5287  */
5288 # define TV_VSCALE_IP_FRAC_MASK		0x00007fff
5289 # define TV_VSCALE_IP_FRAC_SHIFT		0
5290 
5291 #define TV_CC_CONTROL		_MMIO(0x68090)
5292 # define TV_CC_ENABLE			(1 << 31)
5293 /*
5294  * Specifies which field to send the CC data in.
5295  *
5296  * CC data is usually sent in field 0.
5297  */
5298 # define TV_CC_FID_MASK			(1 << 27)
5299 # define TV_CC_FID_SHIFT		27
5300 /* Sets the horizontal position of the CC data.  Usually 135. */
5301 # define TV_CC_HOFF_MASK		0x03ff0000
5302 # define TV_CC_HOFF_SHIFT		16
5303 /* Sets the vertical position of the CC data.  Usually 21 */
5304 # define TV_CC_LINE_MASK		0x0000003f
5305 # define TV_CC_LINE_SHIFT		0
5306 
5307 #define TV_CC_DATA		_MMIO(0x68094)
5308 # define TV_CC_RDY			(1 << 31)
5309 /* Second word of CC data to be transmitted. */
5310 # define TV_CC_DATA_2_MASK		0x007f0000
5311 # define TV_CC_DATA_2_SHIFT		16
5312 /* First word of CC data to be transmitted. */
5313 # define TV_CC_DATA_1_MASK		0x0000007f
5314 # define TV_CC_DATA_1_SHIFT		0
5315 
5316 #define TV_H_LUMA(i)		_MMIO(0x68100 + (i) * 4) /* 60 registers */
5317 #define TV_H_CHROMA(i)		_MMIO(0x68200 + (i) * 4) /* 60 registers */
5318 #define TV_V_LUMA(i)		_MMIO(0x68300 + (i) * 4) /* 43 registers */
5319 #define TV_V_CHROMA(i)		_MMIO(0x68400 + (i) * 4) /* 43 registers */
5320 
5321 /* Display Port */
5322 #define DP_A			_MMIO(0x64000) /* eDP */
5323 #define DP_B			_MMIO(0x64100)
5324 #define DP_C			_MMIO(0x64200)
5325 #define DP_D			_MMIO(0x64300)
5326 
5327 #define VLV_DP_B		_MMIO(VLV_DISPLAY_BASE + 0x64100)
5328 #define VLV_DP_C		_MMIO(VLV_DISPLAY_BASE + 0x64200)
5329 #define CHV_DP_D		_MMIO(VLV_DISPLAY_BASE + 0x64300)
5330 
5331 #define   DP_PORT_EN			(1 << 31)
5332 #define   DP_PIPE_SEL_SHIFT		30
5333 #define   DP_PIPE_SEL_MASK		(1 << 30)
5334 #define   DP_PIPE_SEL(pipe)		((pipe) << 30)
5335 #define   DP_PIPE_SEL_SHIFT_IVB		29
5336 #define   DP_PIPE_SEL_MASK_IVB		(3 << 29)
5337 #define   DP_PIPE_SEL_IVB(pipe)		((pipe) << 29)
5338 #define   DP_PIPE_SEL_SHIFT_CHV		16
5339 #define   DP_PIPE_SEL_MASK_CHV		(3 << 16)
5340 #define   DP_PIPE_SEL_CHV(pipe)		((pipe) << 16)
5341 
5342 /* Link training mode - select a suitable mode for each stage */
5343 #define   DP_LINK_TRAIN_PAT_1		(0 << 28)
5344 #define   DP_LINK_TRAIN_PAT_2		(1 << 28)
5345 #define   DP_LINK_TRAIN_PAT_IDLE	(2 << 28)
5346 #define   DP_LINK_TRAIN_OFF		(3 << 28)
5347 #define   DP_LINK_TRAIN_MASK		(3 << 28)
5348 #define   DP_LINK_TRAIN_SHIFT		28
5349 
5350 /* CPT Link training mode */
5351 #define   DP_LINK_TRAIN_PAT_1_CPT	(0 << 8)
5352 #define   DP_LINK_TRAIN_PAT_2_CPT	(1 << 8)
5353 #define   DP_LINK_TRAIN_PAT_IDLE_CPT	(2 << 8)
5354 #define   DP_LINK_TRAIN_OFF_CPT		(3 << 8)
5355 #define   DP_LINK_TRAIN_MASK_CPT	(7 << 8)
5356 #define   DP_LINK_TRAIN_SHIFT_CPT	8
5357 
5358 /* Signal voltages. These are mostly controlled by the other end */
5359 #define   DP_VOLTAGE_0_4		(0 << 25)
5360 #define   DP_VOLTAGE_0_6		(1 << 25)
5361 #define   DP_VOLTAGE_0_8		(2 << 25)
5362 #define   DP_VOLTAGE_1_2		(3 << 25)
5363 #define   DP_VOLTAGE_MASK		(7 << 25)
5364 #define   DP_VOLTAGE_SHIFT		25
5365 
5366 /* Signal pre-emphasis levels, like voltages, the other end tells us what
5367  * they want
5368  */
5369 #define   DP_PRE_EMPHASIS_0		(0 << 22)
5370 #define   DP_PRE_EMPHASIS_3_5		(1 << 22)
5371 #define   DP_PRE_EMPHASIS_6		(2 << 22)
5372 #define   DP_PRE_EMPHASIS_9_5		(3 << 22)
5373 #define   DP_PRE_EMPHASIS_MASK		(7 << 22)
5374 #define   DP_PRE_EMPHASIS_SHIFT		22
5375 
5376 /* How many wires to use. I guess 3 was too hard */
5377 #define   DP_PORT_WIDTH(width)		(((width) - 1) << 19)
5378 #define   DP_PORT_WIDTH_MASK		(7 << 19)
5379 #define   DP_PORT_WIDTH_SHIFT		19
5380 
5381 /* Mystic DPCD version 1.1 special mode */
5382 #define   DP_ENHANCED_FRAMING		(1 << 18)
5383 
5384 /* eDP */
5385 #define   DP_PLL_FREQ_270MHZ		(0 << 16)
5386 #define   DP_PLL_FREQ_162MHZ		(1 << 16)
5387 #define   DP_PLL_FREQ_MASK		(3 << 16)
5388 
5389 /* locked once port is enabled */
5390 #define   DP_PORT_REVERSAL		(1 << 15)
5391 
5392 /* eDP */
5393 #define   DP_PLL_ENABLE			(1 << 14)
5394 
5395 /* sends the clock on lane 15 of the PEG for debug */
5396 #define   DP_CLOCK_OUTPUT_ENABLE	(1 << 13)
5397 
5398 #define   DP_SCRAMBLING_DISABLE		(1 << 12)
5399 #define   DP_SCRAMBLING_DISABLE_IRONLAKE	(1 << 7)
5400 
5401 /* limit RGB values to avoid confusing TVs */
5402 #define   DP_COLOR_RANGE_16_235		(1 << 8)
5403 
5404 /* Turn on the audio link */
5405 #define   DP_AUDIO_OUTPUT_ENABLE	(1 << 6)
5406 
5407 /* vs and hs sync polarity */
5408 #define   DP_SYNC_VS_HIGH		(1 << 4)
5409 #define   DP_SYNC_HS_HIGH		(1 << 3)
5410 
5411 /* A fantasy */
5412 #define   DP_DETECTED			(1 << 2)
5413 
5414 /* The aux channel provides a way to talk to the
5415  * signal sink for DDC etc. Max packet size supported
5416  * is 20 bytes in each direction, hence the 5 fixed
5417  * data registers
5418  */
5419 #define _DPA_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64010)
5420 #define _DPA_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64014)
5421 #define _DPA_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64018)
5422 #define _DPA_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6401c)
5423 #define _DPA_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64020)
5424 #define _DPA_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64024)
5425 
5426 #define _DPB_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64110)
5427 #define _DPB_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64114)
5428 #define _DPB_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64118)
5429 #define _DPB_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6411c)
5430 #define _DPB_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64120)
5431 #define _DPB_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64124)
5432 
5433 #define _DPC_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64210)
5434 #define _DPC_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64214)
5435 #define _DPC_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64218)
5436 #define _DPC_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6421c)
5437 #define _DPC_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64220)
5438 #define _DPC_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64224)
5439 
5440 #define _DPD_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64310)
5441 #define _DPD_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64314)
5442 #define _DPD_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64318)
5443 #define _DPD_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6431c)
5444 #define _DPD_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64320)
5445 #define _DPD_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64324)
5446 
5447 #define _DPE_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64410)
5448 #define _DPE_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64414)
5449 #define _DPE_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64418)
5450 #define _DPE_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6441c)
5451 #define _DPE_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64420)
5452 #define _DPE_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64424)
5453 
5454 #define _DPF_AUX_CH_CTL		(dev_priv->info.display_mmio_offset + 0x64510)
5455 #define _DPF_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset + 0x64514)
5456 #define _DPF_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset + 0x64518)
5457 #define _DPF_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset + 0x6451c)
5458 #define _DPF_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset + 0x64520)
5459 #define _DPF_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset + 0x64524)
5460 
5461 #define DP_AUX_CH_CTL(aux_ch)	_MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
5462 #define DP_AUX_CH_DATA(aux_ch, i)	_MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
5463 
5464 #define   DP_AUX_CH_CTL_SEND_BUSY	    (1 << 31)
5465 #define   DP_AUX_CH_CTL_DONE		    (1 << 30)
5466 #define   DP_AUX_CH_CTL_INTERRUPT	    (1 << 29)
5467 #define   DP_AUX_CH_CTL_TIME_OUT_ERROR	    (1 << 28)
5468 #define   DP_AUX_CH_CTL_TIME_OUT_400us	    (0 << 26)
5469 #define   DP_AUX_CH_CTL_TIME_OUT_600us	    (1 << 26)
5470 #define   DP_AUX_CH_CTL_TIME_OUT_800us	    (2 << 26)
5471 #define   DP_AUX_CH_CTL_TIME_OUT_MAX	    (3 << 26) /* Varies per platform */
5472 #define   DP_AUX_CH_CTL_TIME_OUT_MASK	    (3 << 26)
5473 #define   DP_AUX_CH_CTL_RECEIVE_ERROR	    (1 << 25)
5474 #define   DP_AUX_CH_CTL_MESSAGE_SIZE_MASK    (0x1f << 20)
5475 #define   DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT   20
5476 #define   DP_AUX_CH_CTL_PRECHARGE_2US_MASK   (0xf << 16)
5477 #define   DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT  16
5478 #define   DP_AUX_CH_CTL_AUX_AKSV_SELECT	    (1 << 15)
5479 #define   DP_AUX_CH_CTL_MANCHESTER_TEST	    (1 << 14)
5480 #define   DP_AUX_CH_CTL_SYNC_TEST	    (1 << 13)
5481 #define   DP_AUX_CH_CTL_DEGLITCH_TEST	    (1 << 12)
5482 #define   DP_AUX_CH_CTL_PRECHARGE_TEST	    (1 << 11)
5483 #define   DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK    (0x7ff)
5484 #define   DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT   0
5485 #define   DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL	(1 << 14)
5486 #define   DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL	(1 << 13)
5487 #define   DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL	(1 << 12)
5488 #define   DP_AUX_CH_CTL_TBT_IO			(1 << 11)
5489 #define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
5490 #define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
5491 #define   DP_AUX_CH_CTL_SYNC_PULSE_SKL(c)   ((c) - 1)
5492 
5493 /*
5494  * Computing GMCH M and N values for the Display Port link
5495  *
5496  * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
5497  *
5498  * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
5499  *
5500  * The GMCH value is used internally
5501  *
5502  * bytes_per_pixel is the number of bytes coming out of the plane,
5503  * which is after the LUTs, so we want the bytes for our color format.
5504  * For our current usage, this is always 3, one byte for R, G and B.
5505  */
5506 #define _PIPEA_DATA_M_G4X	0x70050
5507 #define _PIPEB_DATA_M_G4X	0x71050
5508 
5509 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
5510 #define  TU_SIZE(x)             (((x) - 1) << 25) /* default size 64 */
5511 #define  TU_SIZE_SHIFT		25
5512 #define  TU_SIZE_MASK           (0x3f << 25)
5513 
5514 #define  DATA_LINK_M_N_MASK	(0xffffff)
5515 #define  DATA_LINK_N_MAX	(0x800000)
5516 
5517 #define _PIPEA_DATA_N_G4X	0x70054
5518 #define _PIPEB_DATA_N_G4X	0x71054
5519 #define   PIPE_GMCH_DATA_N_MASK			(0xffffff)
5520 
5521 /*
5522  * Computing Link M and N values for the Display Port link
5523  *
5524  * Link M / N = pixel_clock / ls_clk
5525  *
5526  * (the DP spec calls pixel_clock the 'strm_clk')
5527  *
5528  * The Link value is transmitted in the Main Stream
5529  * Attributes and VB-ID.
5530  */
5531 
5532 #define _PIPEA_LINK_M_G4X	0x70060
5533 #define _PIPEB_LINK_M_G4X	0x71060
5534 #define   PIPEA_DP_LINK_M_MASK			(0xffffff)
5535 
5536 #define _PIPEA_LINK_N_G4X	0x70064
5537 #define _PIPEB_LINK_N_G4X	0x71064
5538 #define   PIPEA_DP_LINK_N_MASK			(0xffffff)
5539 
5540 #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
5541 #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
5542 #define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
5543 #define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
5544 
5545 /* Display & cursor control */
5546 
5547 /* Pipe A */
5548 #define _PIPEADSL		0x70000
5549 #define   DSL_LINEMASK_GEN2	0x00000fff
5550 #define   DSL_LINEMASK_GEN3	0x00001fff
5551 #define _PIPEACONF		0x70008
5552 #define   PIPECONF_ENABLE	(1 << 31)
5553 #define   PIPECONF_DISABLE	0
5554 #define   PIPECONF_DOUBLE_WIDE	(1 << 30)
5555 #define   I965_PIPECONF_ACTIVE	(1 << 30)
5556 #define   PIPECONF_DSI_PLL_LOCKED	(1 << 29) /* vlv & pipe A only */
5557 #define   PIPECONF_FRAME_START_DELAY_MASK (3 << 27)
5558 #define   PIPECONF_SINGLE_WIDE	0
5559 #define   PIPECONF_PIPE_UNLOCKED 0
5560 #define   PIPECONF_PIPE_LOCKED	(1 << 25)
5561 #define   PIPECONF_PALETTE	0
5562 #define   PIPECONF_GAMMA		(1 << 24)
5563 #define   PIPECONF_FORCE_BORDER	(1 << 25)
5564 #define   PIPECONF_INTERLACE_MASK	(7 << 21)
5565 #define   PIPECONF_INTERLACE_MASK_HSW	(3 << 21)
5566 /* Note that pre-gen3 does not support interlaced display directly. Panel
5567  * fitting must be disabled on pre-ilk for interlaced. */
5568 #define   PIPECONF_PROGRESSIVE			(0 << 21)
5569 #define   PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL	(4 << 21) /* gen4 only */
5570 #define   PIPECONF_INTERLACE_W_SYNC_SHIFT	(5 << 21) /* gen4 only */
5571 #define   PIPECONF_INTERLACE_W_FIELD_INDICATION	(6 << 21)
5572 #define   PIPECONF_INTERLACE_FIELD_0_ONLY	(7 << 21) /* gen3 only */
5573 /* Ironlake and later have a complete new set of values for interlaced. PFIT
5574  * means panel fitter required, PF means progressive fetch, DBL means power
5575  * saving pixel doubling. */
5576 #define   PIPECONF_PFIT_PF_INTERLACED_ILK	(1 << 21)
5577 #define   PIPECONF_INTERLACED_ILK		(3 << 21)
5578 #define   PIPECONF_INTERLACED_DBL_ILK		(4 << 21) /* ilk/snb only */
5579 #define   PIPECONF_PFIT_PF_INTERLACED_DBL_ILK	(5 << 21) /* ilk/snb only */
5580 #define   PIPECONF_INTERLACE_MODE_MASK		(7 << 21)
5581 #define   PIPECONF_EDP_RR_MODE_SWITCH		(1 << 20)
5582 #define   PIPECONF_CXSR_DOWNCLOCK	(1 << 16)
5583 #define   PIPECONF_EDP_RR_MODE_SWITCH_VLV	(1 << 14)
5584 #define   PIPECONF_COLOR_RANGE_SELECT	(1 << 13)
5585 #define   PIPECONF_BPC_MASK	(0x7 << 5)
5586 #define   PIPECONF_8BPC		(0 << 5)
5587 #define   PIPECONF_10BPC	(1 << 5)
5588 #define   PIPECONF_6BPC		(2 << 5)
5589 #define   PIPECONF_12BPC	(3 << 5)
5590 #define   PIPECONF_DITHER_EN	(1 << 4)
5591 #define   PIPECONF_DITHER_TYPE_MASK (0x0000000c)
5592 #define   PIPECONF_DITHER_TYPE_SP (0 << 2)
5593 #define   PIPECONF_DITHER_TYPE_ST1 (1 << 2)
5594 #define   PIPECONF_DITHER_TYPE_ST2 (2 << 2)
5595 #define   PIPECONF_DITHER_TYPE_TEMP (3 << 2)
5596 #define _PIPEASTAT		0x70024
5597 #define   PIPE_FIFO_UNDERRUN_STATUS		(1UL << 31)
5598 #define   SPRITE1_FLIP_DONE_INT_EN_VLV		(1UL << 30)
5599 #define   PIPE_CRC_ERROR_ENABLE			(1UL << 29)
5600 #define   PIPE_CRC_DONE_ENABLE			(1UL << 28)
5601 #define   PERF_COUNTER2_INTERRUPT_EN		(1UL << 27)
5602 #define   PIPE_GMBUS_EVENT_ENABLE		(1UL << 27)
5603 #define   PLANE_FLIP_DONE_INT_EN_VLV		(1UL << 26)
5604 #define   PIPE_HOTPLUG_INTERRUPT_ENABLE		(1UL << 26)
5605 #define   PIPE_VSYNC_INTERRUPT_ENABLE		(1UL << 25)
5606 #define   PIPE_DISPLAY_LINE_COMPARE_ENABLE	(1UL << 24)
5607 #define   PIPE_DPST_EVENT_ENABLE		(1UL << 23)
5608 #define   SPRITE0_FLIP_DONE_INT_EN_VLV		(1UL << 22)
5609 #define   PIPE_LEGACY_BLC_EVENT_ENABLE		(1UL << 22)
5610 #define   PIPE_ODD_FIELD_INTERRUPT_ENABLE	(1UL << 21)
5611 #define   PIPE_EVEN_FIELD_INTERRUPT_ENABLE	(1UL << 20)
5612 #define   PIPE_B_PSR_INTERRUPT_ENABLE_VLV	(1UL << 19)
5613 #define   PERF_COUNTER_INTERRUPT_EN		(1UL << 19)
5614 #define   PIPE_HOTPLUG_TV_INTERRUPT_ENABLE	(1UL << 18) /* pre-965 */
5615 #define   PIPE_START_VBLANK_INTERRUPT_ENABLE	(1UL << 18) /* 965 or later */
5616 #define   PIPE_FRAMESTART_INTERRUPT_ENABLE	(1UL << 17)
5617 #define   PIPE_VBLANK_INTERRUPT_ENABLE		(1UL << 17)
5618 #define   PIPEA_HBLANK_INT_EN_VLV		(1UL << 16)
5619 #define   PIPE_OVERLAY_UPDATED_ENABLE		(1UL << 16)
5620 #define   SPRITE1_FLIP_DONE_INT_STATUS_VLV	(1UL << 15)
5621 #define   SPRITE0_FLIP_DONE_INT_STATUS_VLV	(1UL << 14)
5622 #define   PIPE_CRC_ERROR_INTERRUPT_STATUS	(1UL << 13)
5623 #define   PIPE_CRC_DONE_INTERRUPT_STATUS	(1UL << 12)
5624 #define   PERF_COUNTER2_INTERRUPT_STATUS	(1UL << 11)
5625 #define   PIPE_GMBUS_INTERRUPT_STATUS		(1UL << 11)
5626 #define   PLANE_FLIP_DONE_INT_STATUS_VLV	(1UL << 10)
5627 #define   PIPE_HOTPLUG_INTERRUPT_STATUS		(1UL << 10)
5628 #define   PIPE_VSYNC_INTERRUPT_STATUS		(1UL << 9)
5629 #define   PIPE_DISPLAY_LINE_COMPARE_STATUS	(1UL << 8)
5630 #define   PIPE_DPST_EVENT_STATUS		(1UL << 7)
5631 #define   PIPE_A_PSR_STATUS_VLV			(1UL << 6)
5632 #define   PIPE_LEGACY_BLC_EVENT_STATUS		(1UL << 6)
5633 #define   PIPE_ODD_FIELD_INTERRUPT_STATUS	(1UL << 5)
5634 #define   PIPE_EVEN_FIELD_INTERRUPT_STATUS	(1UL << 4)
5635 #define   PIPE_B_PSR_STATUS_VLV			(1UL << 3)
5636 #define   PERF_COUNTER_INTERRUPT_STATUS		(1UL << 3)
5637 #define   PIPE_HOTPLUG_TV_INTERRUPT_STATUS	(1UL << 2) /* pre-965 */
5638 #define   PIPE_START_VBLANK_INTERRUPT_STATUS	(1UL << 2) /* 965 or later */
5639 #define   PIPE_FRAMESTART_INTERRUPT_STATUS	(1UL << 1)
5640 #define   PIPE_VBLANK_INTERRUPT_STATUS		(1UL << 1)
5641 #define   PIPE_HBLANK_INT_STATUS		(1UL << 0)
5642 #define   PIPE_OVERLAY_UPDATED_STATUS		(1UL << 0)
5643 
5644 #define PIPESTAT_INT_ENABLE_MASK		0x7fff0000
5645 #define PIPESTAT_INT_STATUS_MASK		0x0000ffff
5646 
5647 #define PIPE_A_OFFSET		0x70000
5648 #define PIPE_B_OFFSET		0x71000
5649 #define PIPE_C_OFFSET		0x72000
5650 #define CHV_PIPE_C_OFFSET	0x74000
5651 /*
5652  * There's actually no pipe EDP. Some pipe registers have
5653  * simply shifted from the pipe to the transcoder, while
5654  * keeping their original offset. Thus we need PIPE_EDP_OFFSET
5655  * to access such registers in transcoder EDP.
5656  */
5657 #define PIPE_EDP_OFFSET	0x7f000
5658 
5659 /* ICL DSI 0 and 1 */
5660 #define PIPE_DSI0_OFFSET	0x7b000
5661 #define PIPE_DSI1_OFFSET	0x7b800
5662 
5663 #define PIPECONF(pipe)		_MMIO_PIPE2(pipe, _PIPEACONF)
5664 #define PIPEDSL(pipe)		_MMIO_PIPE2(pipe, _PIPEADSL)
5665 #define PIPEFRAME(pipe)		_MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
5666 #define PIPEFRAMEPIXEL(pipe)	_MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL)
5667 #define PIPESTAT(pipe)		_MMIO_PIPE2(pipe, _PIPEASTAT)
5668 
5669 #define _PIPE_MISC_A			0x70030
5670 #define _PIPE_MISC_B			0x71030
5671 #define   PIPEMISC_YUV420_ENABLE	(1 << 27)
5672 #define   PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26)
5673 #define   PIPEMISC_OUTPUT_COLORSPACE_YUV  (1 << 11)
5674 #define   PIPEMISC_DITHER_BPC_MASK	(7 << 5)
5675 #define   PIPEMISC_DITHER_8_BPC		(0 << 5)
5676 #define   PIPEMISC_DITHER_10_BPC	(1 << 5)
5677 #define   PIPEMISC_DITHER_6_BPC		(2 << 5)
5678 #define   PIPEMISC_DITHER_12_BPC	(3 << 5)
5679 #define   PIPEMISC_DITHER_ENABLE	(1 << 4)
5680 #define   PIPEMISC_DITHER_TYPE_MASK	(3 << 2)
5681 #define   PIPEMISC_DITHER_TYPE_SP	(0 << 2)
5682 #define PIPEMISC(pipe)			_MMIO_PIPE2(pipe, _PIPE_MISC_A)
5683 
5684 #define VLV_DPFLIPSTAT				_MMIO(VLV_DISPLAY_BASE + 0x70028)
5685 #define   PIPEB_LINE_COMPARE_INT_EN		(1 << 29)
5686 #define   PIPEB_HLINE_INT_EN			(1 << 28)
5687 #define   PIPEB_VBLANK_INT_EN			(1 << 27)
5688 #define   SPRITED_FLIP_DONE_INT_EN		(1 << 26)
5689 #define   SPRITEC_FLIP_DONE_INT_EN		(1 << 25)
5690 #define   PLANEB_FLIP_DONE_INT_EN		(1 << 24)
5691 #define   PIPE_PSR_INT_EN			(1 << 22)
5692 #define   PIPEA_LINE_COMPARE_INT_EN		(1 << 21)
5693 #define   PIPEA_HLINE_INT_EN			(1 << 20)
5694 #define   PIPEA_VBLANK_INT_EN			(1 << 19)
5695 #define   SPRITEB_FLIP_DONE_INT_EN		(1 << 18)
5696 #define   SPRITEA_FLIP_DONE_INT_EN		(1 << 17)
5697 #define   PLANEA_FLIPDONE_INT_EN		(1 << 16)
5698 #define   PIPEC_LINE_COMPARE_INT_EN		(1 << 13)
5699 #define   PIPEC_HLINE_INT_EN			(1 << 12)
5700 #define   PIPEC_VBLANK_INT_EN			(1 << 11)
5701 #define   SPRITEF_FLIPDONE_INT_EN		(1 << 10)
5702 #define   SPRITEE_FLIPDONE_INT_EN		(1 << 9)
5703 #define   PLANEC_FLIPDONE_INT_EN		(1 << 8)
5704 
5705 #define DPINVGTT				_MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
5706 #define   SPRITEF_INVALID_GTT_INT_EN		(1 << 27)
5707 #define   SPRITEE_INVALID_GTT_INT_EN		(1 << 26)
5708 #define   PLANEC_INVALID_GTT_INT_EN		(1 << 25)
5709 #define   CURSORC_INVALID_GTT_INT_EN		(1 << 24)
5710 #define   CURSORB_INVALID_GTT_INT_EN		(1 << 23)
5711 #define   CURSORA_INVALID_GTT_INT_EN		(1 << 22)
5712 #define   SPRITED_INVALID_GTT_INT_EN		(1 << 21)
5713 #define   SPRITEC_INVALID_GTT_INT_EN		(1 << 20)
5714 #define   PLANEB_INVALID_GTT_INT_EN		(1 << 19)
5715 #define   SPRITEB_INVALID_GTT_INT_EN		(1 << 18)
5716 #define   SPRITEA_INVALID_GTT_INT_EN		(1 << 17)
5717 #define   PLANEA_INVALID_GTT_INT_EN		(1 << 16)
5718 #define   DPINVGTT_EN_MASK			0xff0000
5719 #define   DPINVGTT_EN_MASK_CHV			0xfff0000
5720 #define   SPRITEF_INVALID_GTT_STATUS		(1 << 11)
5721 #define   SPRITEE_INVALID_GTT_STATUS		(1 << 10)
5722 #define   PLANEC_INVALID_GTT_STATUS		(1 << 9)
5723 #define   CURSORC_INVALID_GTT_STATUS		(1 << 8)
5724 #define   CURSORB_INVALID_GTT_STATUS		(1 << 7)
5725 #define   CURSORA_INVALID_GTT_STATUS		(1 << 6)
5726 #define   SPRITED_INVALID_GTT_STATUS		(1 << 5)
5727 #define   SPRITEC_INVALID_GTT_STATUS		(1 << 4)
5728 #define   PLANEB_INVALID_GTT_STATUS		(1 << 3)
5729 #define   SPRITEB_INVALID_GTT_STATUS		(1 << 2)
5730 #define   SPRITEA_INVALID_GTT_STATUS		(1 << 1)
5731 #define   PLANEA_INVALID_GTT_STATUS		(1 << 0)
5732 #define   DPINVGTT_STATUS_MASK			0xff
5733 #define   DPINVGTT_STATUS_MASK_CHV		0xfff
5734 
5735 #define DSPARB			_MMIO(dev_priv->info.display_mmio_offset + 0x70030)
5736 #define   DSPARB_CSTART_MASK	(0x7f << 7)
5737 #define   DSPARB_CSTART_SHIFT	7
5738 #define   DSPARB_BSTART_MASK	(0x7f)
5739 #define   DSPARB_BSTART_SHIFT	0
5740 #define   DSPARB_BEND_SHIFT	9 /* on 855 */
5741 #define   DSPARB_AEND_SHIFT	0
5742 #define   DSPARB_SPRITEA_SHIFT_VLV	0
5743 #define   DSPARB_SPRITEA_MASK_VLV	(0xff << 0)
5744 #define   DSPARB_SPRITEB_SHIFT_VLV	8
5745 #define   DSPARB_SPRITEB_MASK_VLV	(0xff << 8)
5746 #define   DSPARB_SPRITEC_SHIFT_VLV	16
5747 #define   DSPARB_SPRITEC_MASK_VLV	(0xff << 16)
5748 #define   DSPARB_SPRITED_SHIFT_VLV	24
5749 #define   DSPARB_SPRITED_MASK_VLV	(0xff << 24)
5750 #define DSPARB2				_MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
5751 #define   DSPARB_SPRITEA_HI_SHIFT_VLV	0
5752 #define   DSPARB_SPRITEA_HI_MASK_VLV	(0x1 << 0)
5753 #define   DSPARB_SPRITEB_HI_SHIFT_VLV	4
5754 #define   DSPARB_SPRITEB_HI_MASK_VLV	(0x1 << 4)
5755 #define   DSPARB_SPRITEC_HI_SHIFT_VLV	8
5756 #define   DSPARB_SPRITEC_HI_MASK_VLV	(0x1 << 8)
5757 #define   DSPARB_SPRITED_HI_SHIFT_VLV	12
5758 #define   DSPARB_SPRITED_HI_MASK_VLV	(0x1 << 12)
5759 #define   DSPARB_SPRITEE_HI_SHIFT_VLV	16
5760 #define   DSPARB_SPRITEE_HI_MASK_VLV	(0x1 << 16)
5761 #define   DSPARB_SPRITEF_HI_SHIFT_VLV	20
5762 #define   DSPARB_SPRITEF_HI_MASK_VLV	(0x1 << 20)
5763 #define DSPARB3				_MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
5764 #define   DSPARB_SPRITEE_SHIFT_VLV	0
5765 #define   DSPARB_SPRITEE_MASK_VLV	(0xff << 0)
5766 #define   DSPARB_SPRITEF_SHIFT_VLV	8
5767 #define   DSPARB_SPRITEF_MASK_VLV	(0xff << 8)
5768 
5769 /* pnv/gen4/g4x/vlv/chv */
5770 #define DSPFW1		_MMIO(dev_priv->info.display_mmio_offset + 0x70034)
5771 #define   DSPFW_SR_SHIFT		23
5772 #define   DSPFW_SR_MASK			(0x1ff << 23)
5773 #define   DSPFW_CURSORB_SHIFT		16
5774 #define   DSPFW_CURSORB_MASK		(0x3f << 16)
5775 #define   DSPFW_PLANEB_SHIFT		8
5776 #define   DSPFW_PLANEB_MASK		(0x7f << 8)
5777 #define   DSPFW_PLANEB_MASK_VLV		(0xff << 8) /* vlv/chv */
5778 #define   DSPFW_PLANEA_SHIFT		0
5779 #define   DSPFW_PLANEA_MASK		(0x7f << 0)
5780 #define   DSPFW_PLANEA_MASK_VLV		(0xff << 0) /* vlv/chv */
5781 #define DSPFW2		_MMIO(dev_priv->info.display_mmio_offset + 0x70038)
5782 #define   DSPFW_FBC_SR_EN		(1 << 31)	  /* g4x */
5783 #define   DSPFW_FBC_SR_SHIFT		28
5784 #define   DSPFW_FBC_SR_MASK		(0x7 << 28) /* g4x */
5785 #define   DSPFW_FBC_HPLL_SR_SHIFT	24
5786 #define   DSPFW_FBC_HPLL_SR_MASK	(0xf << 24) /* g4x */
5787 #define   DSPFW_SPRITEB_SHIFT		(16)
5788 #define   DSPFW_SPRITEB_MASK		(0x7f << 16) /* g4x */
5789 #define   DSPFW_SPRITEB_MASK_VLV	(0xff << 16) /* vlv/chv */
5790 #define   DSPFW_CURSORA_SHIFT		8
5791 #define   DSPFW_CURSORA_MASK		(0x3f << 8)
5792 #define   DSPFW_PLANEC_OLD_SHIFT	0
5793 #define   DSPFW_PLANEC_OLD_MASK		(0x7f << 0) /* pre-gen4 sprite C */
5794 #define   DSPFW_SPRITEA_SHIFT		0
5795 #define   DSPFW_SPRITEA_MASK		(0x7f << 0) /* g4x */
5796 #define   DSPFW_SPRITEA_MASK_VLV	(0xff << 0) /* vlv/chv */
5797 #define DSPFW3		_MMIO(dev_priv->info.display_mmio_offset + 0x7003c)
5798 #define   DSPFW_HPLL_SR_EN		(1 << 31)
5799 #define   PINEVIEW_SELF_REFRESH_EN	(1 << 30)
5800 #define   DSPFW_CURSOR_SR_SHIFT		24
5801 #define   DSPFW_CURSOR_SR_MASK		(0x3f << 24)
5802 #define   DSPFW_HPLL_CURSOR_SHIFT	16
5803 #define   DSPFW_HPLL_CURSOR_MASK	(0x3f << 16)
5804 #define   DSPFW_HPLL_SR_SHIFT		0
5805 #define   DSPFW_HPLL_SR_MASK		(0x1ff << 0)
5806 
5807 /* vlv/chv */
5808 #define DSPFW4		_MMIO(VLV_DISPLAY_BASE + 0x70070)
5809 #define   DSPFW_SPRITEB_WM1_SHIFT	16
5810 #define   DSPFW_SPRITEB_WM1_MASK	(0xff << 16)
5811 #define   DSPFW_CURSORA_WM1_SHIFT	8
5812 #define   DSPFW_CURSORA_WM1_MASK	(0x3f << 8)
5813 #define   DSPFW_SPRITEA_WM1_SHIFT	0
5814 #define   DSPFW_SPRITEA_WM1_MASK	(0xff << 0)
5815 #define DSPFW5		_MMIO(VLV_DISPLAY_BASE + 0x70074)
5816 #define   DSPFW_PLANEB_WM1_SHIFT	24
5817 #define   DSPFW_PLANEB_WM1_MASK		(0xff << 24)
5818 #define   DSPFW_PLANEA_WM1_SHIFT	16
5819 #define   DSPFW_PLANEA_WM1_MASK		(0xff << 16)
5820 #define   DSPFW_CURSORB_WM1_SHIFT	8
5821 #define   DSPFW_CURSORB_WM1_MASK	(0x3f << 8)
5822 #define   DSPFW_CURSOR_SR_WM1_SHIFT	0
5823 #define   DSPFW_CURSOR_SR_WM1_MASK	(0x3f << 0)
5824 #define DSPFW6		_MMIO(VLV_DISPLAY_BASE + 0x70078)
5825 #define   DSPFW_SR_WM1_SHIFT		0
5826 #define   DSPFW_SR_WM1_MASK		(0x1ff << 0)
5827 #define DSPFW7		_MMIO(VLV_DISPLAY_BASE + 0x7007c)
5828 #define DSPFW7_CHV	_MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
5829 #define   DSPFW_SPRITED_WM1_SHIFT	24
5830 #define   DSPFW_SPRITED_WM1_MASK	(0xff << 24)
5831 #define   DSPFW_SPRITED_SHIFT		16
5832 #define   DSPFW_SPRITED_MASK_VLV	(0xff << 16)
5833 #define   DSPFW_SPRITEC_WM1_SHIFT	8
5834 #define   DSPFW_SPRITEC_WM1_MASK	(0xff << 8)
5835 #define   DSPFW_SPRITEC_SHIFT		0
5836 #define   DSPFW_SPRITEC_MASK_VLV	(0xff << 0)
5837 #define DSPFW8_CHV	_MMIO(VLV_DISPLAY_BASE + 0x700b8)
5838 #define   DSPFW_SPRITEF_WM1_SHIFT	24
5839 #define   DSPFW_SPRITEF_WM1_MASK	(0xff << 24)
5840 #define   DSPFW_SPRITEF_SHIFT		16
5841 #define   DSPFW_SPRITEF_MASK_VLV	(0xff << 16)
5842 #define   DSPFW_SPRITEE_WM1_SHIFT	8
5843 #define   DSPFW_SPRITEE_WM1_MASK	(0xff << 8)
5844 #define   DSPFW_SPRITEE_SHIFT		0
5845 #define   DSPFW_SPRITEE_MASK_VLV	(0xff << 0)
5846 #define DSPFW9_CHV	_MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
5847 #define   DSPFW_PLANEC_WM1_SHIFT	24
5848 #define   DSPFW_PLANEC_WM1_MASK		(0xff << 24)
5849 #define   DSPFW_PLANEC_SHIFT		16
5850 #define   DSPFW_PLANEC_MASK_VLV		(0xff << 16)
5851 #define   DSPFW_CURSORC_WM1_SHIFT	8
5852 #define   DSPFW_CURSORC_WM1_MASK	(0x3f << 16)
5853 #define   DSPFW_CURSORC_SHIFT		0
5854 #define   DSPFW_CURSORC_MASK		(0x3f << 0)
5855 
5856 /* vlv/chv high order bits */
5857 #define DSPHOWM		_MMIO(VLV_DISPLAY_BASE + 0x70064)
5858 #define   DSPFW_SR_HI_SHIFT		24
5859 #define   DSPFW_SR_HI_MASK		(3 << 24) /* 2 bits for chv, 1 for vlv */
5860 #define   DSPFW_SPRITEF_HI_SHIFT	23
5861 #define   DSPFW_SPRITEF_HI_MASK		(1 << 23)
5862 #define   DSPFW_SPRITEE_HI_SHIFT	22
5863 #define   DSPFW_SPRITEE_HI_MASK		(1 << 22)
5864 #define   DSPFW_PLANEC_HI_SHIFT		21
5865 #define   DSPFW_PLANEC_HI_MASK		(1 << 21)
5866 #define   DSPFW_SPRITED_HI_SHIFT	20
5867 #define   DSPFW_SPRITED_HI_MASK		(1 << 20)
5868 #define   DSPFW_SPRITEC_HI_SHIFT	16
5869 #define   DSPFW_SPRITEC_HI_MASK		(1 << 16)
5870 #define   DSPFW_PLANEB_HI_SHIFT		12
5871 #define   DSPFW_PLANEB_HI_MASK		(1 << 12)
5872 #define   DSPFW_SPRITEB_HI_SHIFT	8
5873 #define   DSPFW_SPRITEB_HI_MASK		(1 << 8)
5874 #define   DSPFW_SPRITEA_HI_SHIFT	4
5875 #define   DSPFW_SPRITEA_HI_MASK		(1 << 4)
5876 #define   DSPFW_PLANEA_HI_SHIFT		0
5877 #define   DSPFW_PLANEA_HI_MASK		(1 << 0)
5878 #define DSPHOWM1	_MMIO(VLV_DISPLAY_BASE + 0x70068)
5879 #define   DSPFW_SR_WM1_HI_SHIFT		24
5880 #define   DSPFW_SR_WM1_HI_MASK		(3 << 24) /* 2 bits for chv, 1 for vlv */
5881 #define   DSPFW_SPRITEF_WM1_HI_SHIFT	23
5882 #define   DSPFW_SPRITEF_WM1_HI_MASK	(1 << 23)
5883 #define   DSPFW_SPRITEE_WM1_HI_SHIFT	22
5884 #define   DSPFW_SPRITEE_WM1_HI_MASK	(1 << 22)
5885 #define   DSPFW_PLANEC_WM1_HI_SHIFT	21
5886 #define   DSPFW_PLANEC_WM1_HI_MASK	(1 << 21)
5887 #define   DSPFW_SPRITED_WM1_HI_SHIFT	20
5888 #define   DSPFW_SPRITED_WM1_HI_MASK	(1 << 20)
5889 #define   DSPFW_SPRITEC_WM1_HI_SHIFT	16
5890 #define   DSPFW_SPRITEC_WM1_HI_MASK	(1 << 16)
5891 #define   DSPFW_PLANEB_WM1_HI_SHIFT	12
5892 #define   DSPFW_PLANEB_WM1_HI_MASK	(1 << 12)
5893 #define   DSPFW_SPRITEB_WM1_HI_SHIFT	8
5894 #define   DSPFW_SPRITEB_WM1_HI_MASK	(1 << 8)
5895 #define   DSPFW_SPRITEA_WM1_HI_SHIFT	4
5896 #define   DSPFW_SPRITEA_WM1_HI_MASK	(1 << 4)
5897 #define   DSPFW_PLANEA_WM1_HI_SHIFT	0
5898 #define   DSPFW_PLANEA_WM1_HI_MASK	(1 << 0)
5899 
5900 /* drain latency register values*/
5901 #define VLV_DDL(pipe)			_MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
5902 #define DDL_CURSOR_SHIFT		24
5903 #define DDL_SPRITE_SHIFT(sprite)	(8 + 8 * (sprite))
5904 #define DDL_PLANE_SHIFT			0
5905 #define DDL_PRECISION_HIGH		(1 << 7)
5906 #define DDL_PRECISION_LOW		(0 << 7)
5907 #define DRAIN_LATENCY_MASK		0x7f
5908 
5909 #define CBR1_VLV			_MMIO(VLV_DISPLAY_BASE + 0x70400)
5910 #define  CBR_PND_DEADLINE_DISABLE	(1 << 31)
5911 #define  CBR_PWM_CLOCK_MUX_SELECT	(1 << 30)
5912 
5913 #define CBR4_VLV			_MMIO(VLV_DISPLAY_BASE + 0x70450)
5914 #define  CBR_DPLLBMD_PIPE(pipe)		(1 << (7 + (pipe) * 11)) /* pipes B and C */
5915 
5916 /* FIFO watermark sizes etc */
5917 #define G4X_FIFO_LINE_SIZE	64
5918 #define I915_FIFO_LINE_SIZE	64
5919 #define I830_FIFO_LINE_SIZE	32
5920 
5921 #define VALLEYVIEW_FIFO_SIZE	255
5922 #define G4X_FIFO_SIZE		127
5923 #define I965_FIFO_SIZE		512
5924 #define I945_FIFO_SIZE		127
5925 #define I915_FIFO_SIZE		95
5926 #define I855GM_FIFO_SIZE	127 /* In cachelines */
5927 #define I830_FIFO_SIZE		95
5928 
5929 #define VALLEYVIEW_MAX_WM	0xff
5930 #define G4X_MAX_WM		0x3f
5931 #define I915_MAX_WM		0x3f
5932 
5933 #define PINEVIEW_DISPLAY_FIFO	512 /* in 64byte unit */
5934 #define PINEVIEW_FIFO_LINE_SIZE	64
5935 #define PINEVIEW_MAX_WM		0x1ff
5936 #define PINEVIEW_DFT_WM		0x3f
5937 #define PINEVIEW_DFT_HPLLOFF_WM	0
5938 #define PINEVIEW_GUARD_WM		10
5939 #define PINEVIEW_CURSOR_FIFO		64
5940 #define PINEVIEW_CURSOR_MAX_WM	0x3f
5941 #define PINEVIEW_CURSOR_DFT_WM	0
5942 #define PINEVIEW_CURSOR_GUARD_WM	5
5943 
5944 #define VALLEYVIEW_CURSOR_MAX_WM 64
5945 #define I965_CURSOR_FIFO	64
5946 #define I965_CURSOR_MAX_WM	32
5947 #define I965_CURSOR_DFT_WM	8
5948 
5949 /* Watermark register definitions for SKL */
5950 #define _CUR_WM_A_0		0x70140
5951 #define _CUR_WM_B_0		0x71140
5952 #define _PLANE_WM_1_A_0		0x70240
5953 #define _PLANE_WM_1_B_0		0x71240
5954 #define _PLANE_WM_2_A_0		0x70340
5955 #define _PLANE_WM_2_B_0		0x71340
5956 #define _PLANE_WM_TRANS_1_A_0	0x70268
5957 #define _PLANE_WM_TRANS_1_B_0	0x71268
5958 #define _PLANE_WM_TRANS_2_A_0	0x70368
5959 #define _PLANE_WM_TRANS_2_B_0	0x71368
5960 #define _CUR_WM_TRANS_A_0	0x70168
5961 #define _CUR_WM_TRANS_B_0	0x71168
5962 #define   PLANE_WM_EN		(1 << 31)
5963 #define   PLANE_WM_LINES_SHIFT	14
5964 #define   PLANE_WM_LINES_MASK	0x1f
5965 #define   PLANE_WM_BLOCKS_MASK	0x3ff
5966 
5967 #define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
5968 #define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
5969 #define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0)
5970 
5971 #define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
5972 #define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
5973 #define _PLANE_WM_BASE(pipe, plane)	\
5974 			_PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
5975 #define PLANE_WM(pipe, plane, level)	\
5976 			_MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
5977 #define _PLANE_WM_TRANS_1(pipe)	\
5978 			_PIPE(pipe, _PLANE_WM_TRANS_1_A_0, _PLANE_WM_TRANS_1_B_0)
5979 #define _PLANE_WM_TRANS_2(pipe)	\
5980 			_PIPE(pipe, _PLANE_WM_TRANS_2_A_0, _PLANE_WM_TRANS_2_B_0)
5981 #define PLANE_WM_TRANS(pipe, plane)	\
5982 	_MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
5983 
5984 /* define the Watermark register on Ironlake */
5985 #define WM0_PIPEA_ILK		_MMIO(0x45100)
5986 #define  WM0_PIPE_PLANE_MASK	(0xffff << 16)
5987 #define  WM0_PIPE_PLANE_SHIFT	16
5988 #define  WM0_PIPE_SPRITE_MASK	(0xff << 8)
5989 #define  WM0_PIPE_SPRITE_SHIFT	8
5990 #define  WM0_PIPE_CURSOR_MASK	(0xff)
5991 
5992 #define WM0_PIPEB_ILK		_MMIO(0x45104)
5993 #define WM0_PIPEC_IVB		_MMIO(0x45200)
5994 #define WM1_LP_ILK		_MMIO(0x45108)
5995 #define  WM1_LP_SR_EN		(1 << 31)
5996 #define  WM1_LP_LATENCY_SHIFT	24
5997 #define  WM1_LP_LATENCY_MASK	(0x7f << 24)
5998 #define  WM1_LP_FBC_MASK	(0xf << 20)
5999 #define  WM1_LP_FBC_SHIFT	20
6000 #define  WM1_LP_FBC_SHIFT_BDW	19
6001 #define  WM1_LP_SR_MASK		(0x7ff << 8)
6002 #define  WM1_LP_SR_SHIFT	8
6003 #define  WM1_LP_CURSOR_MASK	(0xff)
6004 #define WM2_LP_ILK		_MMIO(0x4510c)
6005 #define  WM2_LP_EN		(1 << 31)
6006 #define WM3_LP_ILK		_MMIO(0x45110)
6007 #define  WM3_LP_EN		(1 << 31)
6008 #define WM1S_LP_ILK		_MMIO(0x45120)
6009 #define WM2S_LP_IVB		_MMIO(0x45124)
6010 #define WM3S_LP_IVB		_MMIO(0x45128)
6011 #define  WM1S_LP_EN		(1 << 31)
6012 
6013 #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
6014 	(WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
6015 	 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
6016 
6017 /* Memory latency timer register */
6018 #define MLTR_ILK		_MMIO(0x11222)
6019 #define  MLTR_WM1_SHIFT		0
6020 #define  MLTR_WM2_SHIFT		8
6021 /* the unit of memory self-refresh latency time is 0.5us */
6022 #define  ILK_SRLT_MASK		0x3f
6023 
6024 
6025 /* the address where we get all kinds of latency value */
6026 #define SSKPD			_MMIO(0x5d10)
6027 #define SSKPD_WM_MASK		0x3f
6028 #define SSKPD_WM0_SHIFT		0
6029 #define SSKPD_WM1_SHIFT		8
6030 #define SSKPD_WM2_SHIFT		16
6031 #define SSKPD_WM3_SHIFT		24
6032 
6033 /*
6034  * The two pipe frame counter registers are not synchronized, so
6035  * reading a stable value is somewhat tricky. The following code
6036  * should work:
6037  *
6038  *  do {
6039  *    high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
6040  *             PIPE_FRAME_HIGH_SHIFT;
6041  *    low1 =  ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
6042  *             PIPE_FRAME_LOW_SHIFT);
6043  *    high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
6044  *             PIPE_FRAME_HIGH_SHIFT);
6045  *  } while (high1 != high2);
6046  *  frame = (high1 << 8) | low1;
6047  */
6048 #define _PIPEAFRAMEHIGH          0x70040
6049 #define   PIPE_FRAME_HIGH_MASK    0x0000ffff
6050 #define   PIPE_FRAME_HIGH_SHIFT   0
6051 #define _PIPEAFRAMEPIXEL         0x70044
6052 #define   PIPE_FRAME_LOW_MASK     0xff000000
6053 #define   PIPE_FRAME_LOW_SHIFT    24
6054 #define   PIPE_PIXEL_MASK         0x00ffffff
6055 #define   PIPE_PIXEL_SHIFT        0
6056 /* GM45+ just has to be different */
6057 #define _PIPEA_FRMCOUNT_G4X	0x70040
6058 #define _PIPEA_FLIPCOUNT_G4X	0x70044
6059 #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)
6060 #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)
6061 
6062 /* Cursor A & B regs */
6063 #define _CURACNTR		0x70080
6064 /* Old style CUR*CNTR flags (desktop 8xx) */
6065 #define   CURSOR_ENABLE		0x80000000
6066 #define   CURSOR_GAMMA_ENABLE	0x40000000
6067 #define   CURSOR_STRIDE_SHIFT	28
6068 #define   CURSOR_STRIDE(x)	((ffs(x) - 9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */
6069 #define   CURSOR_FORMAT_SHIFT	24
6070 #define   CURSOR_FORMAT_MASK	(0x07 << CURSOR_FORMAT_SHIFT)
6071 #define   CURSOR_FORMAT_2C	(0x00 << CURSOR_FORMAT_SHIFT)
6072 #define   CURSOR_FORMAT_3C	(0x01 << CURSOR_FORMAT_SHIFT)
6073 #define   CURSOR_FORMAT_4C	(0x02 << CURSOR_FORMAT_SHIFT)
6074 #define   CURSOR_FORMAT_ARGB	(0x04 << CURSOR_FORMAT_SHIFT)
6075 #define   CURSOR_FORMAT_XRGB	(0x05 << CURSOR_FORMAT_SHIFT)
6076 /* New style CUR*CNTR flags */
6077 #define   MCURSOR_MODE		0x27
6078 #define   MCURSOR_MODE_DISABLE   0x00
6079 #define   MCURSOR_MODE_128_32B_AX 0x02
6080 #define   MCURSOR_MODE_256_32B_AX 0x03
6081 #define   MCURSOR_MODE_64_32B_AX 0x07
6082 #define   MCURSOR_MODE_128_ARGB_AX ((1 << 5) | MCURSOR_MODE_128_32B_AX)
6083 #define   MCURSOR_MODE_256_ARGB_AX ((1 << 5) | MCURSOR_MODE_256_32B_AX)
6084 #define   MCURSOR_MODE_64_ARGB_AX ((1 << 5) | MCURSOR_MODE_64_32B_AX)
6085 #define   MCURSOR_PIPE_SELECT_MASK	(0x3 << 28)
6086 #define   MCURSOR_PIPE_SELECT_SHIFT	28
6087 #define   MCURSOR_PIPE_SELECT(pipe)	((pipe) << 28)
6088 #define   MCURSOR_GAMMA_ENABLE  (1 << 26)
6089 #define   MCURSOR_PIPE_CSC_ENABLE (1 << 24)
6090 #define   MCURSOR_ROTATE_180	(1 << 15)
6091 #define   MCURSOR_TRICKLE_FEED_DISABLE	(1 << 14)
6092 #define _CURABASE		0x70084
6093 #define _CURAPOS		0x70088
6094 #define   CURSOR_POS_MASK       0x007FF
6095 #define   CURSOR_POS_SIGN       0x8000
6096 #define   CURSOR_X_SHIFT        0
6097 #define   CURSOR_Y_SHIFT        16
6098 #define CURSIZE			_MMIO(0x700a0) /* 845/865 */
6099 #define _CUR_FBC_CTL_A		0x700a0 /* ivb+ */
6100 #define   CUR_FBC_CTL_EN	(1 << 31)
6101 #define _CURASURFLIVE		0x700ac /* g4x+ */
6102 #define _CURBCNTR		0x700c0
6103 #define _CURBBASE		0x700c4
6104 #define _CURBPOS		0x700c8
6105 
6106 #define _CURBCNTR_IVB		0x71080
6107 #define _CURBBASE_IVB		0x71084
6108 #define _CURBPOS_IVB		0x71088
6109 
6110 #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
6111 #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
6112 #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
6113 #define CUR_FBC_CTL(pipe) _CURSOR2(pipe, _CUR_FBC_CTL_A)
6114 #define CURSURFLIVE(pipe) _CURSOR2(pipe, _CURASURFLIVE)
6115 
6116 #define CURSOR_A_OFFSET 0x70080
6117 #define CURSOR_B_OFFSET 0x700c0
6118 #define CHV_CURSOR_C_OFFSET 0x700e0
6119 #define IVB_CURSOR_B_OFFSET 0x71080
6120 #define IVB_CURSOR_C_OFFSET 0x72080
6121 
6122 /* Display A control */
6123 #define _DSPACNTR				0x70180
6124 #define   DISPLAY_PLANE_ENABLE			(1 << 31)
6125 #define   DISPLAY_PLANE_DISABLE			0
6126 #define   DISPPLANE_GAMMA_ENABLE		(1 << 30)
6127 #define   DISPPLANE_GAMMA_DISABLE		0
6128 #define   DISPPLANE_PIXFORMAT_MASK		(0xf << 26)
6129 #define   DISPPLANE_YUV422			(0x0 << 26)
6130 #define   DISPPLANE_8BPP			(0x2 << 26)
6131 #define   DISPPLANE_BGRA555			(0x3 << 26)
6132 #define   DISPPLANE_BGRX555			(0x4 << 26)
6133 #define   DISPPLANE_BGRX565			(0x5 << 26)
6134 #define   DISPPLANE_BGRX888			(0x6 << 26)
6135 #define   DISPPLANE_BGRA888			(0x7 << 26)
6136 #define   DISPPLANE_RGBX101010			(0x8 << 26)
6137 #define   DISPPLANE_RGBA101010			(0x9 << 26)
6138 #define   DISPPLANE_BGRX101010			(0xa << 26)
6139 #define   DISPPLANE_RGBX161616			(0xc << 26)
6140 #define   DISPPLANE_RGBX888			(0xe << 26)
6141 #define   DISPPLANE_RGBA888			(0xf << 26)
6142 #define   DISPPLANE_STEREO_ENABLE		(1 << 25)
6143 #define   DISPPLANE_STEREO_DISABLE		0
6144 #define   DISPPLANE_PIPE_CSC_ENABLE		(1 << 24)
6145 #define   DISPPLANE_SEL_PIPE_SHIFT		24
6146 #define   DISPPLANE_SEL_PIPE_MASK		(3 << DISPPLANE_SEL_PIPE_SHIFT)
6147 #define   DISPPLANE_SEL_PIPE(pipe)		((pipe) << DISPPLANE_SEL_PIPE_SHIFT)
6148 #define   DISPPLANE_SRC_KEY_ENABLE		(1 << 22)
6149 #define   DISPPLANE_SRC_KEY_DISABLE		0
6150 #define   DISPPLANE_LINE_DOUBLE			(1 << 20)
6151 #define   DISPPLANE_NO_LINE_DOUBLE		0
6152 #define   DISPPLANE_STEREO_POLARITY_FIRST	0
6153 #define   DISPPLANE_STEREO_POLARITY_SECOND	(1 << 18)
6154 #define   DISPPLANE_ALPHA_PREMULTIPLY		(1 << 16) /* CHV pipe B */
6155 #define   DISPPLANE_ROTATE_180			(1 << 15)
6156 #define   DISPPLANE_TRICKLE_FEED_DISABLE	(1 << 14) /* Ironlake */
6157 #define   DISPPLANE_TILED			(1 << 10)
6158 #define   DISPPLANE_MIRROR			(1 << 8) /* CHV pipe B */
6159 #define _DSPAADDR				0x70184
6160 #define _DSPASTRIDE				0x70188
6161 #define _DSPAPOS				0x7018C /* reserved */
6162 #define _DSPASIZE				0x70190
6163 #define _DSPASURF				0x7019C /* 965+ only */
6164 #define _DSPATILEOFF				0x701A4 /* 965+ only */
6165 #define _DSPAOFFSET				0x701A4 /* HSW */
6166 #define _DSPASURFLIVE				0x701AC
6167 
6168 #define DSPCNTR(plane)		_MMIO_PIPE2(plane, _DSPACNTR)
6169 #define DSPADDR(plane)		_MMIO_PIPE2(plane, _DSPAADDR)
6170 #define DSPSTRIDE(plane)	_MMIO_PIPE2(plane, _DSPASTRIDE)
6171 #define DSPPOS(plane)		_MMIO_PIPE2(plane, _DSPAPOS)
6172 #define DSPSIZE(plane)		_MMIO_PIPE2(plane, _DSPASIZE)
6173 #define DSPSURF(plane)		_MMIO_PIPE2(plane, _DSPASURF)
6174 #define DSPTILEOFF(plane)	_MMIO_PIPE2(plane, _DSPATILEOFF)
6175 #define DSPLINOFF(plane)	DSPADDR(plane)
6176 #define DSPOFFSET(plane)	_MMIO_PIPE2(plane, _DSPAOFFSET)
6177 #define DSPSURFLIVE(plane)	_MMIO_PIPE2(plane, _DSPASURFLIVE)
6178 
6179 /* CHV pipe B blender and primary plane */
6180 #define _CHV_BLEND_A		0x60a00
6181 #define   CHV_BLEND_LEGACY		(0 << 30)
6182 #define   CHV_BLEND_ANDROID		(1 << 30)
6183 #define   CHV_BLEND_MPO			(2 << 30)
6184 #define   CHV_BLEND_MASK		(3 << 30)
6185 #define _CHV_CANVAS_A		0x60a04
6186 #define _PRIMPOS_A		0x60a08
6187 #define _PRIMSIZE_A		0x60a0c
6188 #define _PRIMCNSTALPHA_A	0x60a10
6189 #define   PRIM_CONST_ALPHA_ENABLE	(1 << 31)
6190 
6191 #define CHV_BLEND(pipe)		_MMIO_TRANS2(pipe, _CHV_BLEND_A)
6192 #define CHV_CANVAS(pipe)	_MMIO_TRANS2(pipe, _CHV_CANVAS_A)
6193 #define PRIMPOS(plane)		_MMIO_TRANS2(plane, _PRIMPOS_A)
6194 #define PRIMSIZE(plane)		_MMIO_TRANS2(plane, _PRIMSIZE_A)
6195 #define PRIMCNSTALPHA(plane)	_MMIO_TRANS2(plane, _PRIMCNSTALPHA_A)
6196 
6197 /* Display/Sprite base address macros */
6198 #define DISP_BASEADDR_MASK	(0xfffff000)
6199 #define I915_LO_DISPBASE(val)	((val) & ~DISP_BASEADDR_MASK)
6200 #define I915_HI_DISPBASE(val)	((val) & DISP_BASEADDR_MASK)
6201 
6202 /*
6203  * VBIOS flags
6204  * gen2:
6205  * [00:06] alm,mgm
6206  * [10:16] all
6207  * [30:32] alm,mgm
6208  * gen3+:
6209  * [00:0f] all
6210  * [10:1f] all
6211  * [30:32] all
6212  */
6213 #define SWF0(i)	_MMIO(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4)
6214 #define SWF1(i)	_MMIO(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
6215 #define SWF3(i)	_MMIO(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
6216 #define SWF_ILK(i)	_MMIO(0x4F000 + (i) * 4)
6217 
6218 /* Pipe B */
6219 #define _PIPEBDSL		(dev_priv->info.display_mmio_offset + 0x71000)
6220 #define _PIPEBCONF		(dev_priv->info.display_mmio_offset + 0x71008)
6221 #define _PIPEBSTAT		(dev_priv->info.display_mmio_offset + 0x71024)
6222 #define _PIPEBFRAMEHIGH		0x71040
6223 #define _PIPEBFRAMEPIXEL	0x71044
6224 #define _PIPEB_FRMCOUNT_G4X	(dev_priv->info.display_mmio_offset + 0x71040)
6225 #define _PIPEB_FLIPCOUNT_G4X	(dev_priv->info.display_mmio_offset + 0x71044)
6226 
6227 
6228 /* Display B control */
6229 #define _DSPBCNTR		(dev_priv->info.display_mmio_offset + 0x71180)
6230 #define   DISPPLANE_ALPHA_TRANS_ENABLE		(1 << 15)
6231 #define   DISPPLANE_ALPHA_TRANS_DISABLE		0
6232 #define   DISPPLANE_SPRITE_ABOVE_DISPLAY	0
6233 #define   DISPPLANE_SPRITE_ABOVE_OVERLAY	(1)
6234 #define _DSPBADDR		(dev_priv->info.display_mmio_offset + 0x71184)
6235 #define _DSPBSTRIDE		(dev_priv->info.display_mmio_offset + 0x71188)
6236 #define _DSPBPOS		(dev_priv->info.display_mmio_offset + 0x7118C)
6237 #define _DSPBSIZE		(dev_priv->info.display_mmio_offset + 0x71190)
6238 #define _DSPBSURF		(dev_priv->info.display_mmio_offset + 0x7119C)
6239 #define _DSPBTILEOFF		(dev_priv->info.display_mmio_offset + 0x711A4)
6240 #define _DSPBOFFSET		(dev_priv->info.display_mmio_offset + 0x711A4)
6241 #define _DSPBSURFLIVE		(dev_priv->info.display_mmio_offset + 0x711AC)
6242 
6243 /* ICL DSI 0 and 1 */
6244 #define _PIPEDSI0CONF		0x7b008
6245 #define _PIPEDSI1CONF		0x7b808
6246 
6247 /* Sprite A control */
6248 #define _DVSACNTR		0x72180
6249 #define   DVS_ENABLE		(1 << 31)
6250 #define   DVS_GAMMA_ENABLE	(1 << 30)
6251 #define   DVS_YUV_RANGE_CORRECTION_DISABLE	(1 << 27)
6252 #define   DVS_PIXFORMAT_MASK	(3 << 25)
6253 #define   DVS_FORMAT_YUV422	(0 << 25)
6254 #define   DVS_FORMAT_RGBX101010	(1 << 25)
6255 #define   DVS_FORMAT_RGBX888	(2 << 25)
6256 #define   DVS_FORMAT_RGBX161616	(3 << 25)
6257 #define   DVS_PIPE_CSC_ENABLE   (1 << 24)
6258 #define   DVS_SOURCE_KEY	(1 << 22)
6259 #define   DVS_RGB_ORDER_XBGR	(1 << 20)
6260 #define   DVS_YUV_FORMAT_BT709	(1 << 18)
6261 #define   DVS_YUV_BYTE_ORDER_MASK (3 << 16)
6262 #define   DVS_YUV_ORDER_YUYV	(0 << 16)
6263 #define   DVS_YUV_ORDER_UYVY	(1 << 16)
6264 #define   DVS_YUV_ORDER_YVYU	(2 << 16)
6265 #define   DVS_YUV_ORDER_VYUY	(3 << 16)
6266 #define   DVS_ROTATE_180	(1 << 15)
6267 #define   DVS_DEST_KEY		(1 << 2)
6268 #define   DVS_TRICKLE_FEED_DISABLE (1 << 14)
6269 #define   DVS_TILED		(1 << 10)
6270 #define _DVSALINOFF		0x72184
6271 #define _DVSASTRIDE		0x72188
6272 #define _DVSAPOS		0x7218c
6273 #define _DVSASIZE		0x72190
6274 #define _DVSAKEYVAL		0x72194
6275 #define _DVSAKEYMSK		0x72198
6276 #define _DVSASURF		0x7219c
6277 #define _DVSAKEYMAXVAL		0x721a0
6278 #define _DVSATILEOFF		0x721a4
6279 #define _DVSASURFLIVE		0x721ac
6280 #define _DVSASCALE		0x72204
6281 #define   DVS_SCALE_ENABLE	(1 << 31)
6282 #define   DVS_FILTER_MASK	(3 << 29)
6283 #define   DVS_FILTER_MEDIUM	(0 << 29)
6284 #define   DVS_FILTER_ENHANCING	(1 << 29)
6285 #define   DVS_FILTER_SOFTENING	(2 << 29)
6286 #define   DVS_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */
6287 #define   DVS_VERTICAL_OFFSET_ENABLE (1 << 27)
6288 #define _DVSAGAMC		0x72300
6289 
6290 #define _DVSBCNTR		0x73180
6291 #define _DVSBLINOFF		0x73184
6292 #define _DVSBSTRIDE		0x73188
6293 #define _DVSBPOS		0x7318c
6294 #define _DVSBSIZE		0x73190
6295 #define _DVSBKEYVAL		0x73194
6296 #define _DVSBKEYMSK		0x73198
6297 #define _DVSBSURF		0x7319c
6298 #define _DVSBKEYMAXVAL		0x731a0
6299 #define _DVSBTILEOFF		0x731a4
6300 #define _DVSBSURFLIVE		0x731ac
6301 #define _DVSBSCALE		0x73204
6302 #define _DVSBGAMC		0x73300
6303 
6304 #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
6305 #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
6306 #define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
6307 #define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
6308 #define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
6309 #define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
6310 #define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
6311 #define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
6312 #define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
6313 #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
6314 #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
6315 #define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
6316 
6317 #define _SPRA_CTL		0x70280
6318 #define   SPRITE_ENABLE			(1 << 31)
6319 #define   SPRITE_GAMMA_ENABLE		(1 << 30)
6320 #define   SPRITE_YUV_RANGE_CORRECTION_DISABLE	(1 << 28)
6321 #define   SPRITE_PIXFORMAT_MASK		(7 << 25)
6322 #define   SPRITE_FORMAT_YUV422		(0 << 25)
6323 #define   SPRITE_FORMAT_RGBX101010	(1 << 25)
6324 #define   SPRITE_FORMAT_RGBX888		(2 << 25)
6325 #define   SPRITE_FORMAT_RGBX161616	(3 << 25)
6326 #define   SPRITE_FORMAT_YUV444		(4 << 25)
6327 #define   SPRITE_FORMAT_XR_BGR101010	(5 << 25) /* Extended range */
6328 #define   SPRITE_PIPE_CSC_ENABLE	(1 << 24)
6329 #define   SPRITE_SOURCE_KEY		(1 << 22)
6330 #define   SPRITE_RGB_ORDER_RGBX		(1 << 20) /* only for 888 and 161616 */
6331 #define   SPRITE_YUV_TO_RGB_CSC_DISABLE	(1 << 19)
6332 #define   SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709	(1 << 18) /* 0 is BT601 */
6333 #define   SPRITE_YUV_BYTE_ORDER_MASK	(3 << 16)
6334 #define   SPRITE_YUV_ORDER_YUYV		(0 << 16)
6335 #define   SPRITE_YUV_ORDER_UYVY		(1 << 16)
6336 #define   SPRITE_YUV_ORDER_YVYU		(2 << 16)
6337 #define   SPRITE_YUV_ORDER_VYUY		(3 << 16)
6338 #define   SPRITE_ROTATE_180		(1 << 15)
6339 #define   SPRITE_TRICKLE_FEED_DISABLE	(1 << 14)
6340 #define   SPRITE_INT_GAMMA_ENABLE	(1 << 13)
6341 #define   SPRITE_TILED			(1 << 10)
6342 #define   SPRITE_DEST_KEY		(1 << 2)
6343 #define _SPRA_LINOFF		0x70284
6344 #define _SPRA_STRIDE		0x70288
6345 #define _SPRA_POS		0x7028c
6346 #define _SPRA_SIZE		0x70290
6347 #define _SPRA_KEYVAL		0x70294
6348 #define _SPRA_KEYMSK		0x70298
6349 #define _SPRA_SURF		0x7029c
6350 #define _SPRA_KEYMAX		0x702a0
6351 #define _SPRA_TILEOFF		0x702a4
6352 #define _SPRA_OFFSET		0x702a4
6353 #define _SPRA_SURFLIVE		0x702ac
6354 #define _SPRA_SCALE		0x70304
6355 #define   SPRITE_SCALE_ENABLE	(1 << 31)
6356 #define   SPRITE_FILTER_MASK	(3 << 29)
6357 #define   SPRITE_FILTER_MEDIUM	(0 << 29)
6358 #define   SPRITE_FILTER_ENHANCING	(1 << 29)
6359 #define   SPRITE_FILTER_SOFTENING	(2 << 29)
6360 #define   SPRITE_VERTICAL_OFFSET_HALF	(1 << 28) /* must be enabled below */
6361 #define   SPRITE_VERTICAL_OFFSET_ENABLE	(1 << 27)
6362 #define _SPRA_GAMC		0x70400
6363 
6364 #define _SPRB_CTL		0x71280
6365 #define _SPRB_LINOFF		0x71284
6366 #define _SPRB_STRIDE		0x71288
6367 #define _SPRB_POS		0x7128c
6368 #define _SPRB_SIZE		0x71290
6369 #define _SPRB_KEYVAL		0x71294
6370 #define _SPRB_KEYMSK		0x71298
6371 #define _SPRB_SURF		0x7129c
6372 #define _SPRB_KEYMAX		0x712a0
6373 #define _SPRB_TILEOFF		0x712a4
6374 #define _SPRB_OFFSET		0x712a4
6375 #define _SPRB_SURFLIVE		0x712ac
6376 #define _SPRB_SCALE		0x71304
6377 #define _SPRB_GAMC		0x71400
6378 
6379 #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
6380 #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
6381 #define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
6382 #define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
6383 #define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
6384 #define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
6385 #define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
6386 #define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
6387 #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
6388 #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
6389 #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
6390 #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
6391 #define SPRGAMC(pipe) _MMIO_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
6392 #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
6393 
6394 #define _SPACNTR		(VLV_DISPLAY_BASE + 0x72180)
6395 #define   SP_ENABLE			(1 << 31)
6396 #define   SP_GAMMA_ENABLE		(1 << 30)
6397 #define   SP_PIXFORMAT_MASK		(0xf << 26)
6398 #define   SP_FORMAT_YUV422		(0 << 26)
6399 #define   SP_FORMAT_BGR565		(5 << 26)
6400 #define   SP_FORMAT_BGRX8888		(6 << 26)
6401 #define   SP_FORMAT_BGRA8888		(7 << 26)
6402 #define   SP_FORMAT_RGBX1010102		(8 << 26)
6403 #define   SP_FORMAT_RGBA1010102		(9 << 26)
6404 #define   SP_FORMAT_RGBX8888		(0xe << 26)
6405 #define   SP_FORMAT_RGBA8888		(0xf << 26)
6406 #define   SP_ALPHA_PREMULTIPLY		(1 << 23) /* CHV pipe B */
6407 #define   SP_SOURCE_KEY			(1 << 22)
6408 #define   SP_YUV_FORMAT_BT709		(1 << 18)
6409 #define   SP_YUV_BYTE_ORDER_MASK	(3 << 16)
6410 #define   SP_YUV_ORDER_YUYV		(0 << 16)
6411 #define   SP_YUV_ORDER_UYVY		(1 << 16)
6412 #define   SP_YUV_ORDER_YVYU		(2 << 16)
6413 #define   SP_YUV_ORDER_VYUY		(3 << 16)
6414 #define   SP_ROTATE_180			(1 << 15)
6415 #define   SP_TILED			(1 << 10)
6416 #define   SP_MIRROR			(1 << 8) /* CHV pipe B */
6417 #define _SPALINOFF		(VLV_DISPLAY_BASE + 0x72184)
6418 #define _SPASTRIDE		(VLV_DISPLAY_BASE + 0x72188)
6419 #define _SPAPOS			(VLV_DISPLAY_BASE + 0x7218c)
6420 #define _SPASIZE		(VLV_DISPLAY_BASE + 0x72190)
6421 #define _SPAKEYMINVAL		(VLV_DISPLAY_BASE + 0x72194)
6422 #define _SPAKEYMSK		(VLV_DISPLAY_BASE + 0x72198)
6423 #define _SPASURF		(VLV_DISPLAY_BASE + 0x7219c)
6424 #define _SPAKEYMAXVAL		(VLV_DISPLAY_BASE + 0x721a0)
6425 #define _SPATILEOFF		(VLV_DISPLAY_BASE + 0x721a4)
6426 #define _SPACONSTALPHA		(VLV_DISPLAY_BASE + 0x721a8)
6427 #define   SP_CONST_ALPHA_ENABLE		(1 << 31)
6428 #define _SPACLRC0		(VLV_DISPLAY_BASE + 0x721d0)
6429 #define   SP_CONTRAST(x)		((x) << 18) /* u3.6 */
6430 #define   SP_BRIGHTNESS(x)		((x) & 0xff) /* s8 */
6431 #define _SPACLRC1		(VLV_DISPLAY_BASE + 0x721d4)
6432 #define   SP_SH_SIN(x)			(((x) & 0x7ff) << 16) /* s4.7 */
6433 #define   SP_SH_COS(x)			(x) /* u3.7 */
6434 #define _SPAGAMC		(VLV_DISPLAY_BASE + 0x721f4)
6435 
6436 #define _SPBCNTR		(VLV_DISPLAY_BASE + 0x72280)
6437 #define _SPBLINOFF		(VLV_DISPLAY_BASE + 0x72284)
6438 #define _SPBSTRIDE		(VLV_DISPLAY_BASE + 0x72288)
6439 #define _SPBPOS			(VLV_DISPLAY_BASE + 0x7228c)
6440 #define _SPBSIZE		(VLV_DISPLAY_BASE + 0x72290)
6441 #define _SPBKEYMINVAL		(VLV_DISPLAY_BASE + 0x72294)
6442 #define _SPBKEYMSK		(VLV_DISPLAY_BASE + 0x72298)
6443 #define _SPBSURF		(VLV_DISPLAY_BASE + 0x7229c)
6444 #define _SPBKEYMAXVAL		(VLV_DISPLAY_BASE + 0x722a0)
6445 #define _SPBTILEOFF		(VLV_DISPLAY_BASE + 0x722a4)
6446 #define _SPBCONSTALPHA		(VLV_DISPLAY_BASE + 0x722a8)
6447 #define _SPBCLRC0		(VLV_DISPLAY_BASE + 0x722d0)
6448 #define _SPBCLRC1		(VLV_DISPLAY_BASE + 0x722d4)
6449 #define _SPBGAMC		(VLV_DISPLAY_BASE + 0x722f4)
6450 
6451 #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
6452 	_MMIO_PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
6453 
6454 #define SPCNTR(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
6455 #define SPLINOFF(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
6456 #define SPSTRIDE(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)
6457 #define SPPOS(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)
6458 #define SPSIZE(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)
6459 #define SPKEYMINVAL(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
6460 #define SPKEYMSK(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)
6461 #define SPSURF(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)
6462 #define SPKEYMAXVAL(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
6463 #define SPTILEOFF(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)
6464 #define SPCONSTALPHA(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
6465 #define SPCLRC0(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)
6466 #define SPCLRC1(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)
6467 #define SPGAMC(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC)
6468 
6469 /*
6470  * CHV pipe B sprite CSC
6471  *
6472  * |cr|   |c0 c1 c2|   |cr + cr_ioff|   |cr_ooff|
6473  * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
6474  * |cb|   |c6 c7 c8|   |cb + cr_ioff|   |cb_ooff|
6475  */
6476 #define _MMIO_CHV_SPCSC(plane_id, reg) \
6477 	_MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
6478 
6479 #define SPCSCYGOFF(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d900)
6480 #define SPCSCCBOFF(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d904)
6481 #define SPCSCCROFF(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d908)
6482 #define  SPCSC_OOFF(x)		(((x) & 0x7ff) << 16) /* s11 */
6483 #define  SPCSC_IOFF(x)		(((x) & 0x7ff) << 0) /* s11 */
6484 
6485 #define SPCSCC01(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d90c)
6486 #define SPCSCC23(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d910)
6487 #define SPCSCC45(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d914)
6488 #define SPCSCC67(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d918)
6489 #define SPCSCC8(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d91c)
6490 #define  SPCSC_C1(x)		(((x) & 0x7fff) << 16) /* s3.12 */
6491 #define  SPCSC_C0(x)		(((x) & 0x7fff) << 0) /* s3.12 */
6492 
6493 #define SPCSCYGICLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d920)
6494 #define SPCSCCBICLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d924)
6495 #define SPCSCCRICLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d928)
6496 #define  SPCSC_IMAX(x)		(((x) & 0x7ff) << 16) /* s11 */
6497 #define  SPCSC_IMIN(x)		(((x) & 0x7ff) << 0) /* s11 */
6498 
6499 #define SPCSCYGOCLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d92c)
6500 #define SPCSCCBOCLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d930)
6501 #define SPCSCCROCLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d934)
6502 #define  SPCSC_OMAX(x)		((x) << 16) /* u10 */
6503 #define  SPCSC_OMIN(x)		((x) << 0) /* u10 */
6504 
6505 /* Skylake plane registers */
6506 
6507 #define _PLANE_CTL_1_A				0x70180
6508 #define _PLANE_CTL_2_A				0x70280
6509 #define _PLANE_CTL_3_A				0x70380
6510 #define   PLANE_CTL_ENABLE			(1 << 31)
6511 #define   PLANE_CTL_PIPE_GAMMA_ENABLE		(1 << 30)   /* Pre-GLK */
6512 #define   PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE	(1 << 28)
6513 /*
6514  * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
6515  * expanded to include bit 23 as well. However, the shift-24 based values
6516  * correctly map to the same formats in ICL, as long as bit 23 is set to 0
6517  */
6518 #define   PLANE_CTL_FORMAT_MASK			(0xf << 24)
6519 #define   PLANE_CTL_FORMAT_YUV422		(0 << 24)
6520 #define   PLANE_CTL_FORMAT_NV12			(1 << 24)
6521 #define   PLANE_CTL_FORMAT_XRGB_2101010		(2 << 24)
6522 #define   PLANE_CTL_FORMAT_XRGB_8888		(4 << 24)
6523 #define   PLANE_CTL_FORMAT_XRGB_16161616F	(6 << 24)
6524 #define   PLANE_CTL_FORMAT_AYUV			(8 << 24)
6525 #define   PLANE_CTL_FORMAT_INDEXED		(12 << 24)
6526 #define   PLANE_CTL_FORMAT_RGB_565		(14 << 24)
6527 #define   ICL_PLANE_CTL_FORMAT_MASK		(0x1f << 23)
6528 #define   PLANE_CTL_PIPE_CSC_ENABLE		(1 << 23) /* Pre-GLK */
6529 #define   PLANE_CTL_KEY_ENABLE_MASK		(0x3 << 21)
6530 #define   PLANE_CTL_KEY_ENABLE_SOURCE		(1 << 21)
6531 #define   PLANE_CTL_KEY_ENABLE_DESTINATION	(2 << 21)
6532 #define   PLANE_CTL_ORDER_BGRX			(0 << 20)
6533 #define   PLANE_CTL_ORDER_RGBX			(1 << 20)
6534 #define   PLANE_CTL_YUV420_Y_PLANE		(1 << 19)
6535 #define   PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709	(1 << 18)
6536 #define   PLANE_CTL_YUV422_ORDER_MASK		(0x3 << 16)
6537 #define   PLANE_CTL_YUV422_YUYV			(0 << 16)
6538 #define   PLANE_CTL_YUV422_UYVY			(1 << 16)
6539 #define   PLANE_CTL_YUV422_YVYU			(2 << 16)
6540 #define   PLANE_CTL_YUV422_VYUY			(3 << 16)
6541 #define   PLANE_CTL_RENDER_DECOMPRESSION_ENABLE	(1 << 15)
6542 #define   PLANE_CTL_TRICKLE_FEED_DISABLE	(1 << 14)
6543 #define   PLANE_CTL_PLANE_GAMMA_DISABLE		(1 << 13) /* Pre-GLK */
6544 #define   PLANE_CTL_TILED_MASK			(0x7 << 10)
6545 #define   PLANE_CTL_TILED_LINEAR		(0 << 10)
6546 #define   PLANE_CTL_TILED_X			(1 << 10)
6547 #define   PLANE_CTL_TILED_Y			(4 << 10)
6548 #define   PLANE_CTL_TILED_YF			(5 << 10)
6549 #define   PLANE_CTL_FLIP_HORIZONTAL		(1 << 8)
6550 #define   PLANE_CTL_ALPHA_MASK			(0x3 << 4) /* Pre-GLK */
6551 #define   PLANE_CTL_ALPHA_DISABLE		(0 << 4)
6552 #define   PLANE_CTL_ALPHA_SW_PREMULTIPLY	(2 << 4)
6553 #define   PLANE_CTL_ALPHA_HW_PREMULTIPLY	(3 << 4)
6554 #define   PLANE_CTL_ROTATE_MASK			0x3
6555 #define   PLANE_CTL_ROTATE_0			0x0
6556 #define   PLANE_CTL_ROTATE_90			0x1
6557 #define   PLANE_CTL_ROTATE_180			0x2
6558 #define   PLANE_CTL_ROTATE_270			0x3
6559 #define _PLANE_STRIDE_1_A			0x70188
6560 #define _PLANE_STRIDE_2_A			0x70288
6561 #define _PLANE_STRIDE_3_A			0x70388
6562 #define _PLANE_POS_1_A				0x7018c
6563 #define _PLANE_POS_2_A				0x7028c
6564 #define _PLANE_POS_3_A				0x7038c
6565 #define _PLANE_SIZE_1_A				0x70190
6566 #define _PLANE_SIZE_2_A				0x70290
6567 #define _PLANE_SIZE_3_A				0x70390
6568 #define _PLANE_SURF_1_A				0x7019c
6569 #define _PLANE_SURF_2_A				0x7029c
6570 #define _PLANE_SURF_3_A				0x7039c
6571 #define _PLANE_OFFSET_1_A			0x701a4
6572 #define _PLANE_OFFSET_2_A			0x702a4
6573 #define _PLANE_OFFSET_3_A			0x703a4
6574 #define _PLANE_KEYVAL_1_A			0x70194
6575 #define _PLANE_KEYVAL_2_A			0x70294
6576 #define _PLANE_KEYMSK_1_A			0x70198
6577 #define _PLANE_KEYMSK_2_A			0x70298
6578 #define  PLANE_KEYMSK_ALPHA_ENABLE		(1 << 31)
6579 #define _PLANE_KEYMAX_1_A			0x701a0
6580 #define _PLANE_KEYMAX_2_A			0x702a0
6581 #define  PLANE_KEYMAX_ALPHA(a)			((a) << 24)
6582 #define _PLANE_AUX_DIST_1_A			0x701c0
6583 #define _PLANE_AUX_DIST_2_A			0x702c0
6584 #define _PLANE_AUX_OFFSET_1_A			0x701c4
6585 #define _PLANE_AUX_OFFSET_2_A			0x702c4
6586 #define _PLANE_CUS_CTL_1_A			0x701c8
6587 #define _PLANE_CUS_CTL_2_A			0x702c8
6588 #define  PLANE_CUS_ENABLE			(1 << 31)
6589 #define  PLANE_CUS_PLANE_6			(0 << 30)
6590 #define  PLANE_CUS_PLANE_7			(1 << 30)
6591 #define  PLANE_CUS_HPHASE_SIGN_NEGATIVE		(1 << 19)
6592 #define  PLANE_CUS_HPHASE_0			(0 << 16)
6593 #define  PLANE_CUS_HPHASE_0_25			(1 << 16)
6594 #define  PLANE_CUS_HPHASE_0_5			(2 << 16)
6595 #define  PLANE_CUS_VPHASE_SIGN_NEGATIVE		(1 << 15)
6596 #define  PLANE_CUS_VPHASE_0			(0 << 12)
6597 #define  PLANE_CUS_VPHASE_0_25			(1 << 12)
6598 #define  PLANE_CUS_VPHASE_0_5			(2 << 12)
6599 #define _PLANE_COLOR_CTL_1_A			0x701CC /* GLK+ */
6600 #define _PLANE_COLOR_CTL_2_A			0x702CC /* GLK+ */
6601 #define _PLANE_COLOR_CTL_3_A			0x703CC /* GLK+ */
6602 #define   PLANE_COLOR_PIPE_GAMMA_ENABLE		(1 << 30) /* Pre-ICL */
6603 #define   PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE	(1 << 28)
6604 #define   PLANE_COLOR_INPUT_CSC_ENABLE		(1 << 20) /* ICL+ */
6605 #define   PLANE_COLOR_PIPE_CSC_ENABLE		(1 << 23) /* Pre-ICL */
6606 #define   PLANE_COLOR_CSC_MODE_BYPASS			(0 << 17)
6607 #define   PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709		(1 << 17)
6608 #define   PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709		(2 << 17)
6609 #define   PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020	(3 << 17)
6610 #define   PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020	(4 << 17)
6611 #define   PLANE_COLOR_PLANE_GAMMA_DISABLE	(1 << 13)
6612 #define   PLANE_COLOR_ALPHA_MASK		(0x3 << 4)
6613 #define   PLANE_COLOR_ALPHA_DISABLE		(0 << 4)
6614 #define   PLANE_COLOR_ALPHA_SW_PREMULTIPLY	(2 << 4)
6615 #define   PLANE_COLOR_ALPHA_HW_PREMULTIPLY	(3 << 4)
6616 #define _PLANE_BUF_CFG_1_A			0x7027c
6617 #define _PLANE_BUF_CFG_2_A			0x7037c
6618 #define _PLANE_NV12_BUF_CFG_1_A		0x70278
6619 #define _PLANE_NV12_BUF_CFG_2_A		0x70378
6620 
6621 /* Input CSC Register Definitions */
6622 #define _PLANE_INPUT_CSC_RY_GY_1_A	0x701E0
6623 #define _PLANE_INPUT_CSC_RY_GY_2_A	0x702E0
6624 
6625 #define _PLANE_INPUT_CSC_RY_GY_1_B	0x711E0
6626 #define _PLANE_INPUT_CSC_RY_GY_2_B	0x712E0
6627 
6628 #define _PLANE_INPUT_CSC_RY_GY_1(pipe)	\
6629 	_PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \
6630 	     _PLANE_INPUT_CSC_RY_GY_1_B)
6631 #define _PLANE_INPUT_CSC_RY_GY_2(pipe)	\
6632 	_PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
6633 	     _PLANE_INPUT_CSC_RY_GY_2_B)
6634 
6635 #define PLANE_INPUT_CSC_COEFF(pipe, plane, index)	\
6636 	_MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) +  (index) * 4, \
6637 		    _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
6638 
6639 #define _PLANE_INPUT_CSC_PREOFF_HI_1_A		0x701F8
6640 #define _PLANE_INPUT_CSC_PREOFF_HI_2_A		0x702F8
6641 
6642 #define _PLANE_INPUT_CSC_PREOFF_HI_1_B		0x711F8
6643 #define _PLANE_INPUT_CSC_PREOFF_HI_2_B		0x712F8
6644 
6645 #define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe)	\
6646 	_PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \
6647 	     _PLANE_INPUT_CSC_PREOFF_HI_1_B)
6648 #define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe)	\
6649 	_PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \
6650 	     _PLANE_INPUT_CSC_PREOFF_HI_2_B)
6651 #define PLANE_INPUT_CSC_PREOFF(pipe, plane, index)	\
6652 	_MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
6653 		    _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
6654 
6655 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_A		0x70204
6656 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_A		0x70304
6657 
6658 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_B		0x71204
6659 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_B		0x71304
6660 
6661 #define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe)	\
6662 	_PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \
6663 	     _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
6664 #define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe)	\
6665 	_PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \
6666 	     _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
6667 #define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index)	\
6668 	_MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
6669 		    _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
6670 
6671 #define _PLANE_CTL_1_B				0x71180
6672 #define _PLANE_CTL_2_B				0x71280
6673 #define _PLANE_CTL_3_B				0x71380
6674 #define _PLANE_CTL_1(pipe)	_PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
6675 #define _PLANE_CTL_2(pipe)	_PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
6676 #define _PLANE_CTL_3(pipe)	_PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
6677 #define PLANE_CTL(pipe, plane)	\
6678 	_MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
6679 
6680 #define _PLANE_STRIDE_1_B			0x71188
6681 #define _PLANE_STRIDE_2_B			0x71288
6682 #define _PLANE_STRIDE_3_B			0x71388
6683 #define _PLANE_STRIDE_1(pipe)	\
6684 	_PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
6685 #define _PLANE_STRIDE_2(pipe)	\
6686 	_PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
6687 #define _PLANE_STRIDE_3(pipe)	\
6688 	_PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
6689 #define PLANE_STRIDE(pipe, plane)	\
6690 	_MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
6691 
6692 #define _PLANE_POS_1_B				0x7118c
6693 #define _PLANE_POS_2_B				0x7128c
6694 #define _PLANE_POS_3_B				0x7138c
6695 #define _PLANE_POS_1(pipe)	_PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
6696 #define _PLANE_POS_2(pipe)	_PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
6697 #define _PLANE_POS_3(pipe)	_PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
6698 #define PLANE_POS(pipe, plane)	\
6699 	_MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
6700 
6701 #define _PLANE_SIZE_1_B				0x71190
6702 #define _PLANE_SIZE_2_B				0x71290
6703 #define _PLANE_SIZE_3_B				0x71390
6704 #define _PLANE_SIZE_1(pipe)	_PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
6705 #define _PLANE_SIZE_2(pipe)	_PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
6706 #define _PLANE_SIZE_3(pipe)	_PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
6707 #define PLANE_SIZE(pipe, plane)	\
6708 	_MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
6709 
6710 #define _PLANE_SURF_1_B				0x7119c
6711 #define _PLANE_SURF_2_B				0x7129c
6712 #define _PLANE_SURF_3_B				0x7139c
6713 #define _PLANE_SURF_1(pipe)	_PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
6714 #define _PLANE_SURF_2(pipe)	_PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
6715 #define _PLANE_SURF_3(pipe)	_PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
6716 #define PLANE_SURF(pipe, plane)	\
6717 	_MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
6718 
6719 #define _PLANE_OFFSET_1_B			0x711a4
6720 #define _PLANE_OFFSET_2_B			0x712a4
6721 #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
6722 #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
6723 #define PLANE_OFFSET(pipe, plane)	\
6724 	_MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
6725 
6726 #define _PLANE_KEYVAL_1_B			0x71194
6727 #define _PLANE_KEYVAL_2_B			0x71294
6728 #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
6729 #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
6730 #define PLANE_KEYVAL(pipe, plane)	\
6731 	_MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
6732 
6733 #define _PLANE_KEYMSK_1_B			0x71198
6734 #define _PLANE_KEYMSK_2_B			0x71298
6735 #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
6736 #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
6737 #define PLANE_KEYMSK(pipe, plane)	\
6738 	_MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
6739 
6740 #define _PLANE_KEYMAX_1_B			0x711a0
6741 #define _PLANE_KEYMAX_2_B			0x712a0
6742 #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
6743 #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
6744 #define PLANE_KEYMAX(pipe, plane)	\
6745 	_MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
6746 
6747 #define _PLANE_BUF_CFG_1_B			0x7127c
6748 #define _PLANE_BUF_CFG_2_B			0x7137c
6749 #define  SKL_DDB_ENTRY_MASK			0x3FF
6750 #define  ICL_DDB_ENTRY_MASK			0x7FF
6751 #define  DDB_ENTRY_END_SHIFT			16
6752 #define _PLANE_BUF_CFG_1(pipe)	\
6753 	_PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
6754 #define _PLANE_BUF_CFG_2(pipe)	\
6755 	_PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
6756 #define PLANE_BUF_CFG(pipe, plane)	\
6757 	_MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
6758 
6759 #define _PLANE_NV12_BUF_CFG_1_B		0x71278
6760 #define _PLANE_NV12_BUF_CFG_2_B		0x71378
6761 #define _PLANE_NV12_BUF_CFG_1(pipe)	\
6762 	_PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
6763 #define _PLANE_NV12_BUF_CFG_2(pipe)	\
6764 	_PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
6765 #define PLANE_NV12_BUF_CFG(pipe, plane)	\
6766 	_MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
6767 
6768 #define _PLANE_AUX_DIST_1_B		0x711c0
6769 #define _PLANE_AUX_DIST_2_B		0x712c0
6770 #define _PLANE_AUX_DIST_1(pipe) \
6771 			_PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B)
6772 #define _PLANE_AUX_DIST_2(pipe) \
6773 			_PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
6774 #define PLANE_AUX_DIST(pipe, plane)     \
6775 	_MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
6776 
6777 #define _PLANE_AUX_OFFSET_1_B		0x711c4
6778 #define _PLANE_AUX_OFFSET_2_B		0x712c4
6779 #define _PLANE_AUX_OFFSET_1(pipe)       \
6780 		_PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B)
6781 #define _PLANE_AUX_OFFSET_2(pipe)       \
6782 		_PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
6783 #define PLANE_AUX_OFFSET(pipe, plane)   \
6784 	_MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
6785 
6786 #define _PLANE_CUS_CTL_1_B		0x711c8
6787 #define _PLANE_CUS_CTL_2_B		0x712c8
6788 #define _PLANE_CUS_CTL_1(pipe)       \
6789 		_PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B)
6790 #define _PLANE_CUS_CTL_2(pipe)       \
6791 		_PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
6792 #define PLANE_CUS_CTL(pipe, plane)   \
6793 	_MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
6794 
6795 #define _PLANE_COLOR_CTL_1_B			0x711CC
6796 #define _PLANE_COLOR_CTL_2_B			0x712CC
6797 #define _PLANE_COLOR_CTL_3_B			0x713CC
6798 #define _PLANE_COLOR_CTL_1(pipe)	\
6799 	_PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
6800 #define _PLANE_COLOR_CTL_2(pipe)	\
6801 	_PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
6802 #define PLANE_COLOR_CTL(pipe, plane)	\
6803 	_MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
6804 
6805 #/* SKL new cursor registers */
6806 #define _CUR_BUF_CFG_A				0x7017c
6807 #define _CUR_BUF_CFG_B				0x7117c
6808 #define CUR_BUF_CFG(pipe)	_MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
6809 
6810 /* VBIOS regs */
6811 #define VGACNTRL		_MMIO(0x71400)
6812 # define VGA_DISP_DISABLE			(1 << 31)
6813 # define VGA_2X_MODE				(1 << 30)
6814 # define VGA_PIPE_B_SELECT			(1 << 29)
6815 
6816 #define VLV_VGACNTRL		_MMIO(VLV_DISPLAY_BASE + 0x71400)
6817 
6818 /* Ironlake */
6819 
6820 #define CPU_VGACNTRL	_MMIO(0x41000)
6821 
6822 #define DIGITAL_PORT_HOTPLUG_CNTRL	_MMIO(0x44030)
6823 #define  DIGITAL_PORTA_HOTPLUG_ENABLE		(1 << 4)
6824 #define  DIGITAL_PORTA_PULSE_DURATION_2ms	(0 << 2) /* pre-HSW */
6825 #define  DIGITAL_PORTA_PULSE_DURATION_4_5ms	(1 << 2) /* pre-HSW */
6826 #define  DIGITAL_PORTA_PULSE_DURATION_6ms	(2 << 2) /* pre-HSW */
6827 #define  DIGITAL_PORTA_PULSE_DURATION_100ms	(3 << 2) /* pre-HSW */
6828 #define  DIGITAL_PORTA_PULSE_DURATION_MASK	(3 << 2) /* pre-HSW */
6829 #define  DIGITAL_PORTA_HOTPLUG_STATUS_MASK	(3 << 0)
6830 #define  DIGITAL_PORTA_HOTPLUG_NO_DETECT	(0 << 0)
6831 #define  DIGITAL_PORTA_HOTPLUG_SHORT_DETECT	(1 << 0)
6832 #define  DIGITAL_PORTA_HOTPLUG_LONG_DETECT	(2 << 0)
6833 
6834 /* refresh rate hardware control */
6835 #define RR_HW_CTL       _MMIO(0x45300)
6836 #define  RR_HW_LOW_POWER_FRAMES_MASK    0xff
6837 #define  RR_HW_HIGH_POWER_FRAMES_MASK   0xff00
6838 
6839 #define FDI_PLL_BIOS_0  _MMIO(0x46000)
6840 #define  FDI_PLL_FB_CLOCK_MASK  0xff
6841 #define FDI_PLL_BIOS_1  _MMIO(0x46004)
6842 #define FDI_PLL_BIOS_2  _MMIO(0x46008)
6843 #define DISPLAY_PORT_PLL_BIOS_0         _MMIO(0x4600c)
6844 #define DISPLAY_PORT_PLL_BIOS_1         _MMIO(0x46010)
6845 #define DISPLAY_PORT_PLL_BIOS_2         _MMIO(0x46014)
6846 
6847 #define PCH_3DCGDIS0		_MMIO(0x46020)
6848 # define MARIUNIT_CLOCK_GATE_DISABLE		(1 << 18)
6849 # define SVSMUNIT_CLOCK_GATE_DISABLE		(1 << 1)
6850 
6851 #define PCH_3DCGDIS1		_MMIO(0x46024)
6852 # define VFMUNIT_CLOCK_GATE_DISABLE		(1 << 11)
6853 
6854 #define FDI_PLL_FREQ_CTL        _MMIO(0x46030)
6855 #define  FDI_PLL_FREQ_CHANGE_REQUEST    (1 << 24)
6856 #define  FDI_PLL_FREQ_LOCK_LIMIT_MASK   0xfff00
6857 #define  FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK  0xff
6858 
6859 
6860 #define _PIPEA_DATA_M1		0x60030
6861 #define  PIPE_DATA_M1_OFFSET    0
6862 #define _PIPEA_DATA_N1		0x60034
6863 #define  PIPE_DATA_N1_OFFSET    0
6864 
6865 #define _PIPEA_DATA_M2		0x60038
6866 #define  PIPE_DATA_M2_OFFSET    0
6867 #define _PIPEA_DATA_N2		0x6003c
6868 #define  PIPE_DATA_N2_OFFSET    0
6869 
6870 #define _PIPEA_LINK_M1		0x60040
6871 #define  PIPE_LINK_M1_OFFSET    0
6872 #define _PIPEA_LINK_N1		0x60044
6873 #define  PIPE_LINK_N1_OFFSET    0
6874 
6875 #define _PIPEA_LINK_M2		0x60048
6876 #define  PIPE_LINK_M2_OFFSET    0
6877 #define _PIPEA_LINK_N2		0x6004c
6878 #define  PIPE_LINK_N2_OFFSET    0
6879 
6880 /* PIPEB timing regs are same start from 0x61000 */
6881 
6882 #define _PIPEB_DATA_M1		0x61030
6883 #define _PIPEB_DATA_N1		0x61034
6884 #define _PIPEB_DATA_M2		0x61038
6885 #define _PIPEB_DATA_N2		0x6103c
6886 #define _PIPEB_LINK_M1		0x61040
6887 #define _PIPEB_LINK_N1		0x61044
6888 #define _PIPEB_LINK_M2		0x61048
6889 #define _PIPEB_LINK_N2		0x6104c
6890 
6891 #define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1)
6892 #define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1)
6893 #define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2)
6894 #define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2)
6895 #define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1)
6896 #define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1)
6897 #define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2)
6898 #define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2)
6899 
6900 /* CPU panel fitter */
6901 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
6902 #define _PFA_CTL_1               0x68080
6903 #define _PFB_CTL_1               0x68880
6904 #define  PF_ENABLE              (1 << 31)
6905 #define  PF_PIPE_SEL_MASK_IVB	(3 << 29)
6906 #define  PF_PIPE_SEL_IVB(pipe)	((pipe) << 29)
6907 #define  PF_FILTER_MASK		(3 << 23)
6908 #define  PF_FILTER_PROGRAMMED	(0 << 23)
6909 #define  PF_FILTER_MED_3x3	(1 << 23)
6910 #define  PF_FILTER_EDGE_ENHANCE	(2 << 23)
6911 #define  PF_FILTER_EDGE_SOFTEN	(3 << 23)
6912 #define _PFA_WIN_SZ		0x68074
6913 #define _PFB_WIN_SZ		0x68874
6914 #define _PFA_WIN_POS		0x68070
6915 #define _PFB_WIN_POS		0x68870
6916 #define _PFA_VSCALE		0x68084
6917 #define _PFB_VSCALE		0x68884
6918 #define _PFA_HSCALE		0x68090
6919 #define _PFB_HSCALE		0x68890
6920 
6921 #define PF_CTL(pipe)		_MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
6922 #define PF_WIN_SZ(pipe)		_MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
6923 #define PF_WIN_POS(pipe)	_MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
6924 #define PF_VSCALE(pipe)		_MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
6925 #define PF_HSCALE(pipe)		_MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
6926 
6927 #define _PSA_CTL		0x68180
6928 #define _PSB_CTL		0x68980
6929 #define PS_ENABLE		(1 << 31)
6930 #define _PSA_WIN_SZ		0x68174
6931 #define _PSB_WIN_SZ		0x68974
6932 #define _PSA_WIN_POS		0x68170
6933 #define _PSB_WIN_POS		0x68970
6934 
6935 #define PS_CTL(pipe)		_MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL)
6936 #define PS_WIN_SZ(pipe)		_MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
6937 #define PS_WIN_POS(pipe)	_MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
6938 
6939 /*
6940  * Skylake scalers
6941  */
6942 #define _PS_1A_CTRL      0x68180
6943 #define _PS_2A_CTRL      0x68280
6944 #define _PS_1B_CTRL      0x68980
6945 #define _PS_2B_CTRL      0x68A80
6946 #define _PS_1C_CTRL      0x69180
6947 #define PS_SCALER_EN        (1 << 31)
6948 #define SKL_PS_SCALER_MODE_MASK (3 << 28)
6949 #define SKL_PS_SCALER_MODE_DYN  (0 << 28)
6950 #define SKL_PS_SCALER_MODE_HQ  (1 << 28)
6951 #define SKL_PS_SCALER_MODE_NV12 (2 << 28)
6952 #define PS_SCALER_MODE_PLANAR (1 << 29)
6953 #define PS_SCALER_MODE_NORMAL (0 << 29)
6954 #define PS_PLANE_SEL_MASK  (7 << 25)
6955 #define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
6956 #define PS_FILTER_MASK         (3 << 23)
6957 #define PS_FILTER_MEDIUM       (0 << 23)
6958 #define PS_FILTER_EDGE_ENHANCE (2 << 23)
6959 #define PS_FILTER_BILINEAR     (3 << 23)
6960 #define PS_VERT3TAP            (1 << 21)
6961 #define PS_VERT_INT_INVERT_FIELD1 (0 << 20)
6962 #define PS_VERT_INT_INVERT_FIELD0 (1 << 20)
6963 #define PS_PWRUP_PROGRESS         (1 << 17)
6964 #define PS_V_FILTER_BYPASS        (1 << 8)
6965 #define PS_VADAPT_EN              (1 << 7)
6966 #define PS_VADAPT_MODE_MASK        (3 << 5)
6967 #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
6968 #define PS_VADAPT_MODE_MOD_ADAPT   (1 << 5)
6969 #define PS_VADAPT_MODE_MOST_ADAPT  (3 << 5)
6970 #define PS_PLANE_Y_SEL_MASK  (7 << 5)
6971 #define PS_PLANE_Y_SEL(plane) (((plane) + 1) << 5)
6972 
6973 #define _PS_PWR_GATE_1A     0x68160
6974 #define _PS_PWR_GATE_2A     0x68260
6975 #define _PS_PWR_GATE_1B     0x68960
6976 #define _PS_PWR_GATE_2B     0x68A60
6977 #define _PS_PWR_GATE_1C     0x69160
6978 #define PS_PWR_GATE_DIS_OVERRIDE       (1 << 31)
6979 #define PS_PWR_GATE_SETTLING_TIME_32   (0 << 3)
6980 #define PS_PWR_GATE_SETTLING_TIME_64   (1 << 3)
6981 #define PS_PWR_GATE_SETTLING_TIME_96   (2 << 3)
6982 #define PS_PWR_GATE_SETTLING_TIME_128  (3 << 3)
6983 #define PS_PWR_GATE_SLPEN_8             0
6984 #define PS_PWR_GATE_SLPEN_16            1
6985 #define PS_PWR_GATE_SLPEN_24            2
6986 #define PS_PWR_GATE_SLPEN_32            3
6987 
6988 #define _PS_WIN_POS_1A      0x68170
6989 #define _PS_WIN_POS_2A      0x68270
6990 #define _PS_WIN_POS_1B      0x68970
6991 #define _PS_WIN_POS_2B      0x68A70
6992 #define _PS_WIN_POS_1C      0x69170
6993 
6994 #define _PS_WIN_SZ_1A       0x68174
6995 #define _PS_WIN_SZ_2A       0x68274
6996 #define _PS_WIN_SZ_1B       0x68974
6997 #define _PS_WIN_SZ_2B       0x68A74
6998 #define _PS_WIN_SZ_1C       0x69174
6999 
7000 #define _PS_VSCALE_1A       0x68184
7001 #define _PS_VSCALE_2A       0x68284
7002 #define _PS_VSCALE_1B       0x68984
7003 #define _PS_VSCALE_2B       0x68A84
7004 #define _PS_VSCALE_1C       0x69184
7005 
7006 #define _PS_HSCALE_1A       0x68190
7007 #define _PS_HSCALE_2A       0x68290
7008 #define _PS_HSCALE_1B       0x68990
7009 #define _PS_HSCALE_2B       0x68A90
7010 #define _PS_HSCALE_1C       0x69190
7011 
7012 #define _PS_VPHASE_1A       0x68188
7013 #define _PS_VPHASE_2A       0x68288
7014 #define _PS_VPHASE_1B       0x68988
7015 #define _PS_VPHASE_2B       0x68A88
7016 #define _PS_VPHASE_1C       0x69188
7017 #define  PS_Y_PHASE(x)		((x) << 16)
7018 #define  PS_UV_RGB_PHASE(x)	((x) << 0)
7019 #define   PS_PHASE_MASK	(0x7fff << 1) /* u2.13 */
7020 #define   PS_PHASE_TRIP	(1 << 0)
7021 
7022 #define _PS_HPHASE_1A       0x68194
7023 #define _PS_HPHASE_2A       0x68294
7024 #define _PS_HPHASE_1B       0x68994
7025 #define _PS_HPHASE_2B       0x68A94
7026 #define _PS_HPHASE_1C       0x69194
7027 
7028 #define _PS_ECC_STAT_1A     0x681D0
7029 #define _PS_ECC_STAT_2A     0x682D0
7030 #define _PS_ECC_STAT_1B     0x689D0
7031 #define _PS_ECC_STAT_2B     0x68AD0
7032 #define _PS_ECC_STAT_1C     0x691D0
7033 
7034 #define _ID(id, a, b) _PICK_EVEN(id, a, b)
7035 #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe,        \
7036 			_ID(id, _PS_1A_CTRL, _PS_2A_CTRL),       \
7037 			_ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
7038 #define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe,    \
7039 			_ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
7040 			_ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
7041 #define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe,     \
7042 			_ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
7043 			_ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
7044 #define SKL_PS_WIN_SZ(pipe, id)  _MMIO_PIPE(pipe,     \
7045 			_ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A),   \
7046 			_ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
7047 #define SKL_PS_VSCALE(pipe, id)  _MMIO_PIPE(pipe,     \
7048 			_ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A),   \
7049 			_ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
7050 #define SKL_PS_HSCALE(pipe, id)  _MMIO_PIPE(pipe,     \
7051 			_ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A),   \
7052 			_ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
7053 #define SKL_PS_VPHASE(pipe, id)  _MMIO_PIPE(pipe,     \
7054 			_ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A),   \
7055 			_ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
7056 #define SKL_PS_HPHASE(pipe, id)  _MMIO_PIPE(pipe,     \
7057 			_ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A),   \
7058 			_ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
7059 #define SKL_PS_ECC_STAT(pipe, id)  _MMIO_PIPE(pipe,     \
7060 			_ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A),   \
7061 			_ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
7062 
7063 /* legacy palette */
7064 #define _LGC_PALETTE_A           0x4a000
7065 #define _LGC_PALETTE_B           0x4a800
7066 #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
7067 
7068 #define _GAMMA_MODE_A		0x4a480
7069 #define _GAMMA_MODE_B		0x4ac80
7070 #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
7071 #define GAMMA_MODE_MODE_MASK	(3 << 0)
7072 #define GAMMA_MODE_MODE_8BIT	(0 << 0)
7073 #define GAMMA_MODE_MODE_10BIT	(1 << 0)
7074 #define GAMMA_MODE_MODE_12BIT	(2 << 0)
7075 #define GAMMA_MODE_MODE_SPLIT	(3 << 0)
7076 
7077 /* DMC/CSR */
7078 #define CSR_PROGRAM(i)		_MMIO(0x80000 + (i) * 4)
7079 #define CSR_SSP_BASE_ADDR_GEN9	0x00002FC0
7080 #define CSR_HTP_ADDR_SKL	0x00500034
7081 #define CSR_SSP_BASE		_MMIO(0x8F074)
7082 #define CSR_HTP_SKL		_MMIO(0x8F004)
7083 #define CSR_LAST_WRITE		_MMIO(0x8F034)
7084 #define CSR_LAST_WRITE_VALUE	0xc003b400
7085 /* MMIO address range for CSR program (0x80000 - 0x82FFF) */
7086 #define CSR_MMIO_START_RANGE	0x80000
7087 #define CSR_MMIO_END_RANGE	0x8FFFF
7088 #define SKL_CSR_DC3_DC5_COUNT	_MMIO(0x80030)
7089 #define SKL_CSR_DC5_DC6_COUNT	_MMIO(0x8002C)
7090 #define BXT_CSR_DC3_DC5_COUNT	_MMIO(0x80038)
7091 
7092 /* interrupts */
7093 #define DE_MASTER_IRQ_CONTROL   (1 << 31)
7094 #define DE_SPRITEB_FLIP_DONE    (1 << 29)
7095 #define DE_SPRITEA_FLIP_DONE    (1 << 28)
7096 #define DE_PLANEB_FLIP_DONE     (1 << 27)
7097 #define DE_PLANEA_FLIP_DONE     (1 << 26)
7098 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
7099 #define DE_PCU_EVENT            (1 << 25)
7100 #define DE_GTT_FAULT            (1 << 24)
7101 #define DE_POISON               (1 << 23)
7102 #define DE_PERFORM_COUNTER      (1 << 22)
7103 #define DE_PCH_EVENT            (1 << 21)
7104 #define DE_AUX_CHANNEL_A        (1 << 20)
7105 #define DE_DP_A_HOTPLUG         (1 << 19)
7106 #define DE_GSE                  (1 << 18)
7107 #define DE_PIPEB_VBLANK         (1 << 15)
7108 #define DE_PIPEB_EVEN_FIELD     (1 << 14)
7109 #define DE_PIPEB_ODD_FIELD      (1 << 13)
7110 #define DE_PIPEB_LINE_COMPARE   (1 << 12)
7111 #define DE_PIPEB_VSYNC          (1 << 11)
7112 #define DE_PIPEB_CRC_DONE	(1 << 10)
7113 #define DE_PIPEB_FIFO_UNDERRUN  (1 << 8)
7114 #define DE_PIPEA_VBLANK         (1 << 7)
7115 #define DE_PIPE_VBLANK(pipe)    (1 << (7 + 8 * (pipe)))
7116 #define DE_PIPEA_EVEN_FIELD     (1 << 6)
7117 #define DE_PIPEA_ODD_FIELD      (1 << 5)
7118 #define DE_PIPEA_LINE_COMPARE   (1 << 4)
7119 #define DE_PIPEA_VSYNC          (1 << 3)
7120 #define DE_PIPEA_CRC_DONE	(1 << 2)
7121 #define DE_PIPE_CRC_DONE(pipe)	(1 << (2 + 8 * (pipe)))
7122 #define DE_PIPEA_FIFO_UNDERRUN  (1 << 0)
7123 #define DE_PIPE_FIFO_UNDERRUN(pipe)  (1 << (8 * (pipe)))
7124 
7125 /* More Ivybridge lolz */
7126 #define DE_ERR_INT_IVB			(1 << 30)
7127 #define DE_GSE_IVB			(1 << 29)
7128 #define DE_PCH_EVENT_IVB		(1 << 28)
7129 #define DE_DP_A_HOTPLUG_IVB		(1 << 27)
7130 #define DE_AUX_CHANNEL_A_IVB		(1 << 26)
7131 #define DE_EDP_PSR_INT_HSW		(1 << 19)
7132 #define DE_SPRITEC_FLIP_DONE_IVB	(1 << 14)
7133 #define DE_PLANEC_FLIP_DONE_IVB		(1 << 13)
7134 #define DE_PIPEC_VBLANK_IVB		(1 << 10)
7135 #define DE_SPRITEB_FLIP_DONE_IVB	(1 << 9)
7136 #define DE_PLANEB_FLIP_DONE_IVB		(1 << 8)
7137 #define DE_PIPEB_VBLANK_IVB		(1 << 5)
7138 #define DE_SPRITEA_FLIP_DONE_IVB	(1 << 4)
7139 #define DE_PLANEA_FLIP_DONE_IVB		(1 << 3)
7140 #define DE_PLANE_FLIP_DONE_IVB(plane)	(1 << (3 + 5 * (plane)))
7141 #define DE_PIPEA_VBLANK_IVB		(1 << 0)
7142 #define DE_PIPE_VBLANK_IVB(pipe)	(1 << ((pipe) * 5))
7143 
7144 #define VLV_MASTER_IER			_MMIO(0x4400c) /* Gunit master IER */
7145 #define   MASTER_INTERRUPT_ENABLE	(1 << 31)
7146 
7147 #define DEISR   _MMIO(0x44000)
7148 #define DEIMR   _MMIO(0x44004)
7149 #define DEIIR   _MMIO(0x44008)
7150 #define DEIER   _MMIO(0x4400c)
7151 
7152 #define GTISR   _MMIO(0x44010)
7153 #define GTIMR   _MMIO(0x44014)
7154 #define GTIIR   _MMIO(0x44018)
7155 #define GTIER   _MMIO(0x4401c)
7156 
7157 #define GEN8_MASTER_IRQ			_MMIO(0x44200)
7158 #define  GEN8_MASTER_IRQ_CONTROL	(1 << 31)
7159 #define  GEN8_PCU_IRQ			(1 << 30)
7160 #define  GEN8_DE_PCH_IRQ		(1 << 23)
7161 #define  GEN8_DE_MISC_IRQ		(1 << 22)
7162 #define  GEN8_DE_PORT_IRQ		(1 << 20)
7163 #define  GEN8_DE_PIPE_C_IRQ		(1 << 18)
7164 #define  GEN8_DE_PIPE_B_IRQ		(1 << 17)
7165 #define  GEN8_DE_PIPE_A_IRQ		(1 << 16)
7166 #define  GEN8_DE_PIPE_IRQ(pipe)		(1 << (16 + (pipe)))
7167 #define  GEN8_GT_VECS_IRQ		(1 << 6)
7168 #define  GEN8_GT_GUC_IRQ		(1 << 5)
7169 #define  GEN8_GT_PM_IRQ			(1 << 4)
7170 #define  GEN8_GT_VCS2_IRQ		(1 << 3)
7171 #define  GEN8_GT_VCS1_IRQ		(1 << 2)
7172 #define  GEN8_GT_BCS_IRQ		(1 << 1)
7173 #define  GEN8_GT_RCS_IRQ		(1 << 0)
7174 
7175 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
7176 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
7177 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
7178 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
7179 
7180 #define GEN9_GUC_TO_HOST_INT_EVENT	(1 << 31)
7181 #define GEN9_GUC_EXEC_ERROR_EVENT	(1 << 30)
7182 #define GEN9_GUC_DISPLAY_EVENT		(1 << 29)
7183 #define GEN9_GUC_SEMA_SIGNAL_EVENT	(1 << 28)
7184 #define GEN9_GUC_IOMMU_MSG_EVENT	(1 << 27)
7185 #define GEN9_GUC_DB_RING_EVENT		(1 << 26)
7186 #define GEN9_GUC_DMA_DONE_EVENT		(1 << 25)
7187 #define GEN9_GUC_FATAL_ERROR_EVENT	(1 << 24)
7188 #define GEN9_GUC_NOTIFICATION_EVENT	(1 << 23)
7189 
7190 #define GEN8_RCS_IRQ_SHIFT 0
7191 #define GEN8_BCS_IRQ_SHIFT 16
7192 #define GEN8_VCS1_IRQ_SHIFT 0
7193 #define GEN8_VCS2_IRQ_SHIFT 16
7194 #define GEN8_VECS_IRQ_SHIFT 0
7195 #define GEN8_WD_IRQ_SHIFT 16
7196 
7197 #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
7198 #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
7199 #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
7200 #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
7201 #define  GEN8_PIPE_FIFO_UNDERRUN	(1 << 31)
7202 #define  GEN8_PIPE_CDCLK_CRC_ERROR	(1 << 29)
7203 #define  GEN8_PIPE_CDCLK_CRC_DONE	(1 << 28)
7204 #define  GEN8_PIPE_CURSOR_FAULT		(1 << 10)
7205 #define  GEN8_PIPE_SPRITE_FAULT		(1 << 9)
7206 #define  GEN8_PIPE_PRIMARY_FAULT	(1 << 8)
7207 #define  GEN8_PIPE_SPRITE_FLIP_DONE	(1 << 5)
7208 #define  GEN8_PIPE_PRIMARY_FLIP_DONE	(1 << 4)
7209 #define  GEN8_PIPE_SCAN_LINE_EVENT	(1 << 2)
7210 #define  GEN8_PIPE_VSYNC		(1 << 1)
7211 #define  GEN8_PIPE_VBLANK		(1 << 0)
7212 #define  GEN9_PIPE_CURSOR_FAULT		(1 << 11)
7213 #define  GEN9_PIPE_PLANE4_FAULT		(1 << 10)
7214 #define  GEN9_PIPE_PLANE3_FAULT		(1 << 9)
7215 #define  GEN9_PIPE_PLANE2_FAULT		(1 << 8)
7216 #define  GEN9_PIPE_PLANE1_FAULT		(1 << 7)
7217 #define  GEN9_PIPE_PLANE4_FLIP_DONE	(1 << 6)
7218 #define  GEN9_PIPE_PLANE3_FLIP_DONE	(1 << 5)
7219 #define  GEN9_PIPE_PLANE2_FLIP_DONE	(1 << 4)
7220 #define  GEN9_PIPE_PLANE1_FLIP_DONE	(1 << 3)
7221 #define  GEN9_PIPE_PLANE_FLIP_DONE(p)	(1 << (3 + (p)))
7222 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
7223 	(GEN8_PIPE_CURSOR_FAULT | \
7224 	 GEN8_PIPE_SPRITE_FAULT | \
7225 	 GEN8_PIPE_PRIMARY_FAULT)
7226 #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \
7227 	(GEN9_PIPE_CURSOR_FAULT | \
7228 	 GEN9_PIPE_PLANE4_FAULT | \
7229 	 GEN9_PIPE_PLANE3_FAULT | \
7230 	 GEN9_PIPE_PLANE2_FAULT | \
7231 	 GEN9_PIPE_PLANE1_FAULT)
7232 
7233 #define GEN8_DE_PORT_ISR _MMIO(0x44440)
7234 #define GEN8_DE_PORT_IMR _MMIO(0x44444)
7235 #define GEN8_DE_PORT_IIR _MMIO(0x44448)
7236 #define GEN8_DE_PORT_IER _MMIO(0x4444c)
7237 #define  ICL_AUX_CHANNEL_E		(1 << 29)
7238 #define  CNL_AUX_CHANNEL_F		(1 << 28)
7239 #define  GEN9_AUX_CHANNEL_D		(1 << 27)
7240 #define  GEN9_AUX_CHANNEL_C		(1 << 26)
7241 #define  GEN9_AUX_CHANNEL_B		(1 << 25)
7242 #define  BXT_DE_PORT_HP_DDIC		(1 << 5)
7243 #define  BXT_DE_PORT_HP_DDIB		(1 << 4)
7244 #define  BXT_DE_PORT_HP_DDIA		(1 << 3)
7245 #define  BXT_DE_PORT_HOTPLUG_MASK	(BXT_DE_PORT_HP_DDIA | \
7246 					 BXT_DE_PORT_HP_DDIB | \
7247 					 BXT_DE_PORT_HP_DDIC)
7248 #define  GEN8_PORT_DP_A_HOTPLUG		(1 << 3)
7249 #define  BXT_DE_PORT_GMBUS		(1 << 1)
7250 #define  GEN8_AUX_CHANNEL_A		(1 << 0)
7251 
7252 #define GEN8_DE_MISC_ISR _MMIO(0x44460)
7253 #define GEN8_DE_MISC_IMR _MMIO(0x44464)
7254 #define GEN8_DE_MISC_IIR _MMIO(0x44468)
7255 #define GEN8_DE_MISC_IER _MMIO(0x4446c)
7256 #define  GEN8_DE_MISC_GSE		(1 << 27)
7257 #define  GEN8_DE_EDP_PSR		(1 << 19)
7258 
7259 #define GEN8_PCU_ISR _MMIO(0x444e0)
7260 #define GEN8_PCU_IMR _MMIO(0x444e4)
7261 #define GEN8_PCU_IIR _MMIO(0x444e8)
7262 #define GEN8_PCU_IER _MMIO(0x444ec)
7263 
7264 #define GEN11_GU_MISC_ISR	_MMIO(0x444f0)
7265 #define GEN11_GU_MISC_IMR	_MMIO(0x444f4)
7266 #define GEN11_GU_MISC_IIR	_MMIO(0x444f8)
7267 #define GEN11_GU_MISC_IER	_MMIO(0x444fc)
7268 #define  GEN11_GU_MISC_GSE	(1 << 27)
7269 
7270 #define GEN11_GFX_MSTR_IRQ		_MMIO(0x190010)
7271 #define  GEN11_MASTER_IRQ		(1 << 31)
7272 #define  GEN11_PCU_IRQ			(1 << 30)
7273 #define  GEN11_GU_MISC_IRQ		(1 << 29)
7274 #define  GEN11_DISPLAY_IRQ		(1 << 16)
7275 #define  GEN11_GT_DW_IRQ(x)		(1 << (x))
7276 #define  GEN11_GT_DW1_IRQ		(1 << 1)
7277 #define  GEN11_GT_DW0_IRQ		(1 << 0)
7278 
7279 #define GEN11_DISPLAY_INT_CTL		_MMIO(0x44200)
7280 #define  GEN11_DISPLAY_IRQ_ENABLE	(1 << 31)
7281 #define  GEN11_AUDIO_CODEC_IRQ		(1 << 24)
7282 #define  GEN11_DE_PCH_IRQ		(1 << 23)
7283 #define  GEN11_DE_MISC_IRQ		(1 << 22)
7284 #define  GEN11_DE_HPD_IRQ		(1 << 21)
7285 #define  GEN11_DE_PORT_IRQ		(1 << 20)
7286 #define  GEN11_DE_PIPE_C		(1 << 18)
7287 #define  GEN11_DE_PIPE_B		(1 << 17)
7288 #define  GEN11_DE_PIPE_A		(1 << 16)
7289 
7290 #define GEN11_DE_HPD_ISR		_MMIO(0x44470)
7291 #define GEN11_DE_HPD_IMR		_MMIO(0x44474)
7292 #define GEN11_DE_HPD_IIR		_MMIO(0x44478)
7293 #define GEN11_DE_HPD_IER		_MMIO(0x4447c)
7294 #define  GEN11_TC4_HOTPLUG			(1 << 19)
7295 #define  GEN11_TC3_HOTPLUG			(1 << 18)
7296 #define  GEN11_TC2_HOTPLUG			(1 << 17)
7297 #define  GEN11_TC1_HOTPLUG			(1 << 16)
7298 #define  GEN11_TC_HOTPLUG(tc_port)		(1 << ((tc_port) + 16))
7299 #define  GEN11_DE_TC_HOTPLUG_MASK		(GEN11_TC4_HOTPLUG | \
7300 						 GEN11_TC3_HOTPLUG | \
7301 						 GEN11_TC2_HOTPLUG | \
7302 						 GEN11_TC1_HOTPLUG)
7303 #define  GEN11_TBT4_HOTPLUG			(1 << 3)
7304 #define  GEN11_TBT3_HOTPLUG			(1 << 2)
7305 #define  GEN11_TBT2_HOTPLUG			(1 << 1)
7306 #define  GEN11_TBT1_HOTPLUG			(1 << 0)
7307 #define  GEN11_TBT_HOTPLUG(tc_port)		(1 << (tc_port))
7308 #define  GEN11_DE_TBT_HOTPLUG_MASK		(GEN11_TBT4_HOTPLUG | \
7309 						 GEN11_TBT3_HOTPLUG | \
7310 						 GEN11_TBT2_HOTPLUG | \
7311 						 GEN11_TBT1_HOTPLUG)
7312 
7313 #define GEN11_TBT_HOTPLUG_CTL				_MMIO(0x44030)
7314 #define GEN11_TC_HOTPLUG_CTL				_MMIO(0x44038)
7315 #define  GEN11_HOTPLUG_CTL_ENABLE(tc_port)		(8 << (tc_port) * 4)
7316 #define  GEN11_HOTPLUG_CTL_LONG_DETECT(tc_port)		(2 << (tc_port) * 4)
7317 #define  GEN11_HOTPLUG_CTL_SHORT_DETECT(tc_port)	(1 << (tc_port) * 4)
7318 #define  GEN11_HOTPLUG_CTL_NO_DETECT(tc_port)		(0 << (tc_port) * 4)
7319 
7320 #define GEN11_GT_INTR_DW0		_MMIO(0x190018)
7321 #define  GEN11_CSME			(31)
7322 #define  GEN11_GUNIT			(28)
7323 #define  GEN11_GUC			(25)
7324 #define  GEN11_WDPERF			(20)
7325 #define  GEN11_KCR			(19)
7326 #define  GEN11_GTPM			(16)
7327 #define  GEN11_BCS			(15)
7328 #define  GEN11_RCS0			(0)
7329 
7330 #define GEN11_GT_INTR_DW1		_MMIO(0x19001c)
7331 #define  GEN11_VECS(x)			(31 - (x))
7332 #define  GEN11_VCS(x)			(x)
7333 
7334 #define GEN11_GT_INTR_DW(x)		_MMIO(0x190018 + ((x) * 4))
7335 
7336 #define GEN11_INTR_IDENTITY_REG0	_MMIO(0x190060)
7337 #define GEN11_INTR_IDENTITY_REG1	_MMIO(0x190064)
7338 #define  GEN11_INTR_DATA_VALID		(1 << 31)
7339 #define  GEN11_INTR_ENGINE_CLASS(x)	(((x) & GENMASK(18, 16)) >> 16)
7340 #define  GEN11_INTR_ENGINE_INSTANCE(x)	(((x) & GENMASK(25, 20)) >> 20)
7341 #define  GEN11_INTR_ENGINE_INTR(x)	((x) & 0xffff)
7342 
7343 #define GEN11_INTR_IDENTITY_REG(x)	_MMIO(0x190060 + ((x) * 4))
7344 
7345 #define GEN11_IIR_REG0_SELECTOR		_MMIO(0x190070)
7346 #define GEN11_IIR_REG1_SELECTOR		_MMIO(0x190074)
7347 
7348 #define GEN11_IIR_REG_SELECTOR(x)	_MMIO(0x190070 + ((x) * 4))
7349 
7350 #define GEN11_RENDER_COPY_INTR_ENABLE	_MMIO(0x190030)
7351 #define GEN11_VCS_VECS_INTR_ENABLE	_MMIO(0x190034)
7352 #define GEN11_GUC_SG_INTR_ENABLE	_MMIO(0x190038)
7353 #define GEN11_GPM_WGBOXPERF_INTR_ENABLE	_MMIO(0x19003c)
7354 #define GEN11_CRYPTO_RSVD_INTR_ENABLE	_MMIO(0x190040)
7355 #define GEN11_GUNIT_CSME_INTR_ENABLE	_MMIO(0x190044)
7356 
7357 #define GEN11_RCS0_RSVD_INTR_MASK	_MMIO(0x190090)
7358 #define GEN11_BCS_RSVD_INTR_MASK	_MMIO(0x1900a0)
7359 #define GEN11_VCS0_VCS1_INTR_MASK	_MMIO(0x1900a8)
7360 #define GEN11_VCS2_VCS3_INTR_MASK	_MMIO(0x1900ac)
7361 #define GEN11_VECS0_VECS1_INTR_MASK	_MMIO(0x1900d0)
7362 #define GEN11_GUC_SG_INTR_MASK		_MMIO(0x1900e8)
7363 #define GEN11_GPM_WGBOXPERF_INTR_MASK	_MMIO(0x1900ec)
7364 #define GEN11_CRYPTO_RSVD_INTR_MASK	_MMIO(0x1900f0)
7365 #define GEN11_GUNIT_CSME_INTR_MASK	_MMIO(0x1900f4)
7366 
7367 #define ILK_DISPLAY_CHICKEN2	_MMIO(0x42004)
7368 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
7369 #define  ILK_ELPIN_409_SELECT	(1 << 25)
7370 #define  ILK_DPARB_GATE	(1 << 22)
7371 #define  ILK_VSDPFD_FULL	(1 << 21)
7372 #define FUSE_STRAP			_MMIO(0x42014)
7373 #define  ILK_INTERNAL_GRAPHICS_DISABLE	(1 << 31)
7374 #define  ILK_INTERNAL_DISPLAY_DISABLE	(1 << 30)
7375 #define  ILK_DISPLAY_DEBUG_DISABLE	(1 << 29)
7376 #define  IVB_PIPE_C_DISABLE		(1 << 28)
7377 #define  ILK_HDCP_DISABLE		(1 << 25)
7378 #define  ILK_eDP_A_DISABLE		(1 << 24)
7379 #define  HSW_CDCLK_LIMIT		(1 << 24)
7380 #define  ILK_DESKTOP			(1 << 23)
7381 
7382 #define ILK_DSPCLK_GATE_D			_MMIO(0x42020)
7383 #define   ILK_VRHUNIT_CLOCK_GATE_DISABLE	(1 << 28)
7384 #define   ILK_DPFCUNIT_CLOCK_GATE_DISABLE	(1 << 9)
7385 #define   ILK_DPFCRUNIT_CLOCK_GATE_DISABLE	(1 << 8)
7386 #define   ILK_DPFDUNIT_CLOCK_GATE_ENABLE	(1 << 7)
7387 #define   ILK_DPARBUNIT_CLOCK_GATE_ENABLE	(1 << 5)
7388 
7389 #define IVB_CHICKEN3	_MMIO(0x4200c)
7390 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE	(1 << 5)
7391 # define CHICKEN3_DGMG_DONE_FIX_DISABLE		(1 << 2)
7392 
7393 #define CHICKEN_PAR1_1		_MMIO(0x42080)
7394 #define  SKL_DE_COMPRESSED_HASH_MODE	(1 << 15)
7395 #define  DPA_MASK_VBLANK_SRD	(1 << 15)
7396 #define  FORCE_ARB_IDLE_PLANES	(1 << 14)
7397 #define  SKL_EDP_PSR_FIX_RDWRAP	(1 << 3)
7398 
7399 #define CHICKEN_PAR2_1		_MMIO(0x42090)
7400 #define  KVM_CONFIG_CHANGE_NOTIFICATION_SELECT	(1 << 14)
7401 
7402 #define CHICKEN_MISC_2		_MMIO(0x42084)
7403 #define  CNL_COMP_PWR_DOWN	(1 << 23)
7404 #define  GLK_CL2_PWR_DOWN	(1 << 12)
7405 #define  GLK_CL1_PWR_DOWN	(1 << 11)
7406 #define  GLK_CL0_PWR_DOWN	(1 << 10)
7407 
7408 #define CHICKEN_MISC_4		_MMIO(0x4208c)
7409 #define   FBC_STRIDE_OVERRIDE	(1 << 13)
7410 #define   FBC_STRIDE_MASK	0x1FFF
7411 
7412 #define _CHICKEN_PIPESL_1_A	0x420b0
7413 #define _CHICKEN_PIPESL_1_B	0x420b4
7414 #define  HSW_FBCQ_DIS			(1 << 22)
7415 #define  BDW_DPRS_MASK_VBLANK_SRD	(1 << 0)
7416 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
7417 
7418 #define CHICKEN_TRANS_A		_MMIO(0x420c0)
7419 #define CHICKEN_TRANS_B		_MMIO(0x420c4)
7420 #define CHICKEN_TRANS_C		_MMIO(0x420c8)
7421 #define CHICKEN_TRANS_EDP	_MMIO(0x420cc)
7422 #define  VSC_DATA_SEL_SOFTWARE_CONTROL	(1 << 25) /* GLK and CNL+ */
7423 #define  DDI_TRAINING_OVERRIDE_ENABLE	(1 << 19)
7424 #define  DDI_TRAINING_OVERRIDE_VALUE	(1 << 18)
7425 #define  DDIE_TRAINING_OVERRIDE_ENABLE	(1 << 17) /* CHICKEN_TRANS_A only */
7426 #define  DDIE_TRAINING_OVERRIDE_VALUE	(1 << 16) /* CHICKEN_TRANS_A only */
7427 #define  PSR2_ADD_VERTICAL_LINE_COUNT   (1 << 15)
7428 #define  PSR2_VSC_ENABLE_PROG_HEADER    (1 << 12)
7429 
7430 #define DISP_ARB_CTL	_MMIO(0x45000)
7431 #define  DISP_FBC_MEMORY_WAKE		(1 << 31)
7432 #define  DISP_TILE_SURFACE_SWIZZLING	(1 << 13)
7433 #define  DISP_FBC_WM_DIS		(1 << 15)
7434 #define DISP_ARB_CTL2	_MMIO(0x45004)
7435 #define  DISP_DATA_PARTITION_5_6	(1 << 6)
7436 #define  DISP_IPC_ENABLE		(1 << 3)
7437 #define DBUF_CTL	_MMIO(0x45008)
7438 #define DBUF_CTL_S1	_MMIO(0x45008)
7439 #define DBUF_CTL_S2	_MMIO(0x44FE8)
7440 #define  DBUF_POWER_REQUEST		(1 << 31)
7441 #define  DBUF_POWER_STATE		(1 << 30)
7442 #define GEN7_MSG_CTL	_MMIO(0x45010)
7443 #define  WAIT_FOR_PCH_RESET_ACK		(1 << 1)
7444 #define  WAIT_FOR_PCH_FLR_ACK		(1 << 0)
7445 #define HSW_NDE_RSTWRN_OPT	_MMIO(0x46408)
7446 #define  RESET_PCH_HANDSHAKE_ENABLE	(1 << 4)
7447 
7448 #define GEN8_CHICKEN_DCPR_1		_MMIO(0x46430)
7449 #define   SKL_SELECT_ALTERNATE_DC_EXIT	(1 << 30)
7450 #define   MASK_WAKEMEM			(1 << 13)
7451 #define   CNL_DDI_CLOCK_REG_ACCESS_ON	(1 << 7)
7452 
7453 #define SKL_DFSM			_MMIO(0x51000)
7454 #define SKL_DFSM_CDCLK_LIMIT_MASK	(3 << 23)
7455 #define SKL_DFSM_CDCLK_LIMIT_675	(0 << 23)
7456 #define SKL_DFSM_CDCLK_LIMIT_540	(1 << 23)
7457 #define SKL_DFSM_CDCLK_LIMIT_450	(2 << 23)
7458 #define SKL_DFSM_CDCLK_LIMIT_337_5	(3 << 23)
7459 #define SKL_DFSM_PIPE_A_DISABLE		(1 << 30)
7460 #define SKL_DFSM_PIPE_B_DISABLE		(1 << 21)
7461 #define SKL_DFSM_PIPE_C_DISABLE		(1 << 28)
7462 
7463 #define SKL_DSSM				_MMIO(0x51004)
7464 #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz		(1 << 31)
7465 #define ICL_DSSM_CDCLK_PLL_REFCLK_MASK		(7 << 29)
7466 #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz		(0 << 29)
7467 #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz	(1 << 29)
7468 #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz	(2 << 29)
7469 
7470 #define GEN7_FF_SLICE_CS_CHICKEN1	_MMIO(0x20e0)
7471 #define   GEN9_FFSC_PERCTX_PREEMPT_CTRL	(1 << 14)
7472 
7473 #define FF_SLICE_CS_CHICKEN2			_MMIO(0x20e4)
7474 #define  GEN9_TSG_BARRIER_ACK_DISABLE		(1 << 8)
7475 #define  GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE  (1 << 10)
7476 
7477 #define GEN9_CS_DEBUG_MODE1		_MMIO(0x20ec)
7478 #define GEN9_CTX_PREEMPT_REG		_MMIO(0x2248)
7479 #define GEN8_CS_CHICKEN1		_MMIO(0x2580)
7480 #define GEN9_PREEMPT_3D_OBJECT_LEVEL		(1 << 0)
7481 #define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo)	(((hi) << 2) | ((lo) << 1))
7482 #define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL	GEN9_PREEMPT_GPGPU_LEVEL(0, 0)
7483 #define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL	GEN9_PREEMPT_GPGPU_LEVEL(0, 1)
7484 #define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL	GEN9_PREEMPT_GPGPU_LEVEL(1, 0)
7485 #define GEN9_PREEMPT_GPGPU_LEVEL_MASK		GEN9_PREEMPT_GPGPU_LEVEL(1, 1)
7486 
7487 /* GEN7 chicken */
7488 #define GEN7_COMMON_SLICE_CHICKEN1		_MMIO(0x7010)
7489   #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC	((1 << 10) | (1 << 26))
7490   #define GEN9_RHWO_OPTIMIZATION_DISABLE	(1 << 14)
7491 
7492 #define COMMON_SLICE_CHICKEN2					_MMIO(0x7014)
7493   #define GEN9_PBE_COMPRESSED_HASH_SELECTION			(1 << 13)
7494   #define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE	(1 << 12)
7495   #define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION		(1 << 8)
7496   #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE			(1 << 0)
7497 
7498 #define GEN11_COMMON_SLICE_CHICKEN3		_MMIO(0x7304)
7499   #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC	(1 << 11)
7500 
7501 #define HIZ_CHICKEN					_MMIO(0x7018)
7502 # define CHV_HZ_8X8_MODE_IN_1X				(1 << 15)
7503 # define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE	(1 << 3)
7504 
7505 #define GEN9_SLICE_COMMON_ECO_CHICKEN0		_MMIO(0x7308)
7506 #define  DISABLE_PIXEL_MASK_CAMMING		(1 << 14)
7507 
7508 #define GEN9_SLICE_COMMON_ECO_CHICKEN1		_MMIO(0x731c)
7509 #define   GEN11_STATE_CACHE_REDIRECT_TO_CS	(1 << 11)
7510 
7511 #define GEN7_SARCHKMD				_MMIO(0xB000)
7512 #define GEN7_DISABLE_DEMAND_PREFETCH		(1 << 31)
7513 #define GEN7_DISABLE_SAMPLER_PREFETCH           (1 << 30)
7514 
7515 #define GEN7_L3SQCREG1				_MMIO(0xB010)
7516 #define  VLV_B0_WA_L3SQCREG1_VALUE		0x00D30000
7517 
7518 #define GEN8_L3SQCREG1				_MMIO(0xB100)
7519 /*
7520  * Note that on CHV the following has an off-by-one error wrt. to BSpec.
7521  * Using the formula in BSpec leads to a hang, while the formula here works
7522  * fine and matches the formulas for all other platforms. A BSpec change
7523  * request has been filed to clarify this.
7524  */
7525 #define  L3_GENERAL_PRIO_CREDITS(x)		(((x) >> 1) << 19)
7526 #define  L3_HIGH_PRIO_CREDITS(x)		(((x) >> 1) << 14)
7527 #define  L3_PRIO_CREDITS_MASK			((0x1f << 19) | (0x1f << 14))
7528 
7529 #define GEN7_L3CNTLREG1				_MMIO(0xB01C)
7530 #define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C47FF8C
7531 #define  GEN7_L3AGDIS				(1 << 19)
7532 #define GEN7_L3CNTLREG2				_MMIO(0xB020)
7533 #define GEN7_L3CNTLREG3				_MMIO(0xB024)
7534 
7535 #define GEN7_L3_CHICKEN_MODE_REGISTER		_MMIO(0xB030)
7536 #define   GEN7_WA_L3_CHICKEN_MODE		0x20000000
7537 #define GEN10_L3_CHICKEN_MODE_REGISTER		_MMIO(0xB114)
7538 #define   GEN11_I2M_WRITE_DISABLE		(1 << 28)
7539 
7540 #define GEN7_L3SQCREG4				_MMIO(0xb034)
7541 #define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1 << 27)
7542 
7543 #define GEN8_L3SQCREG4				_MMIO(0xb118)
7544 #define  GEN11_LQSC_CLEAN_EVICT_DISABLE		(1 << 6)
7545 #define  GEN8_LQSC_RO_PERF_DIS			(1 << 27)
7546 #define  GEN8_LQSC_FLUSH_COHERENT_LINES		(1 << 21)
7547 
7548 /* GEN8 chicken */
7549 #define HDC_CHICKEN0				_MMIO(0x7300)
7550 #define CNL_HDC_CHICKEN0			_MMIO(0xE5F0)
7551 #define ICL_HDC_MODE				_MMIO(0xE5F4)
7552 #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE	(1 << 15)
7553 #define  HDC_FENCE_DEST_SLM_DISABLE		(1 << 14)
7554 #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1 << 11)
7555 #define  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT	(1 << 5)
7556 #define  HDC_FORCE_NON_COHERENT			(1 << 4)
7557 #define  HDC_BARRIER_PERFORMANCE_DISABLE	(1 << 10)
7558 
7559 #define GEN8_HDC_CHICKEN1			_MMIO(0x7304)
7560 
7561 /* GEN9 chicken */
7562 #define SLICE_ECO_CHICKEN0			_MMIO(0x7308)
7563 #define   PIXEL_MASK_CAMMING_DISABLE		(1 << 14)
7564 
7565 #define GEN9_WM_CHICKEN3			_MMIO(0x5588)
7566 #define   GEN9_FACTOR_IN_CLR_VAL_HIZ		(1 << 9)
7567 
7568 /* WaCatErrorRejectionIssue */
7569 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		_MMIO(0x9030)
7570 #define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1 << 11)
7571 
7572 #define HSW_SCRATCH1				_MMIO(0xb038)
7573 #define  HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE	(1 << 27)
7574 
7575 #define BDW_SCRATCH1					_MMIO(0xb11c)
7576 #define  GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE	(1 << 2)
7577 
7578 /*GEN11 chicken */
7579 #define _PIPEA_CHICKEN			0x70038
7580 #define _PIPEB_CHICKEN			0x71038
7581 #define _PIPEC_CHICKEN			0x72038
7582 #define  PER_PIXEL_ALPHA_BYPASS_EN	(1 << 7)
7583 #define PIPE_CHICKEN(pipe)		_MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
7584 						   _PIPEB_CHICKEN)
7585 
7586 /* PCH */
7587 
7588 #define PCH_DISPLAY_BASE	0xc0000u
7589 
7590 /* south display engine interrupt: IBX */
7591 #define SDE_AUDIO_POWER_D	(1 << 27)
7592 #define SDE_AUDIO_POWER_C	(1 << 26)
7593 #define SDE_AUDIO_POWER_B	(1 << 25)
7594 #define SDE_AUDIO_POWER_SHIFT	(25)
7595 #define SDE_AUDIO_POWER_MASK	(7 << SDE_AUDIO_POWER_SHIFT)
7596 #define SDE_GMBUS		(1 << 24)
7597 #define SDE_AUDIO_HDCP_TRANSB	(1 << 23)
7598 #define SDE_AUDIO_HDCP_TRANSA	(1 << 22)
7599 #define SDE_AUDIO_HDCP_MASK	(3 << 22)
7600 #define SDE_AUDIO_TRANSB	(1 << 21)
7601 #define SDE_AUDIO_TRANSA	(1 << 20)
7602 #define SDE_AUDIO_TRANS_MASK	(3 << 20)
7603 #define SDE_POISON		(1 << 19)
7604 /* 18 reserved */
7605 #define SDE_FDI_RXB		(1 << 17)
7606 #define SDE_FDI_RXA		(1 << 16)
7607 #define SDE_FDI_MASK		(3 << 16)
7608 #define SDE_AUXD		(1 << 15)
7609 #define SDE_AUXC		(1 << 14)
7610 #define SDE_AUXB		(1 << 13)
7611 #define SDE_AUX_MASK		(7 << 13)
7612 /* 12 reserved */
7613 #define SDE_CRT_HOTPLUG         (1 << 11)
7614 #define SDE_PORTD_HOTPLUG       (1 << 10)
7615 #define SDE_PORTC_HOTPLUG       (1 << 9)
7616 #define SDE_PORTB_HOTPLUG       (1 << 8)
7617 #define SDE_SDVOB_HOTPLUG       (1 << 6)
7618 #define SDE_HOTPLUG_MASK        (SDE_CRT_HOTPLUG | \
7619 				 SDE_SDVOB_HOTPLUG |	\
7620 				 SDE_PORTB_HOTPLUG |	\
7621 				 SDE_PORTC_HOTPLUG |	\
7622 				 SDE_PORTD_HOTPLUG)
7623 #define SDE_TRANSB_CRC_DONE	(1 << 5)
7624 #define SDE_TRANSB_CRC_ERR	(1 << 4)
7625 #define SDE_TRANSB_FIFO_UNDER	(1 << 3)
7626 #define SDE_TRANSA_CRC_DONE	(1 << 2)
7627 #define SDE_TRANSA_CRC_ERR	(1 << 1)
7628 #define SDE_TRANSA_FIFO_UNDER	(1 << 0)
7629 #define SDE_TRANS_MASK		(0x3f)
7630 
7631 /* south display engine interrupt: CPT - CNP */
7632 #define SDE_AUDIO_POWER_D_CPT	(1 << 31)
7633 #define SDE_AUDIO_POWER_C_CPT	(1 << 30)
7634 #define SDE_AUDIO_POWER_B_CPT	(1 << 29)
7635 #define SDE_AUDIO_POWER_SHIFT_CPT   29
7636 #define SDE_AUDIO_POWER_MASK_CPT    (7 << 29)
7637 #define SDE_AUXD_CPT		(1 << 27)
7638 #define SDE_AUXC_CPT		(1 << 26)
7639 #define SDE_AUXB_CPT		(1 << 25)
7640 #define SDE_AUX_MASK_CPT	(7 << 25)
7641 #define SDE_PORTE_HOTPLUG_SPT	(1 << 25)
7642 #define SDE_PORTA_HOTPLUG_SPT	(1 << 24)
7643 #define SDE_PORTD_HOTPLUG_CPT	(1 << 23)
7644 #define SDE_PORTC_HOTPLUG_CPT	(1 << 22)
7645 #define SDE_PORTB_HOTPLUG_CPT	(1 << 21)
7646 #define SDE_CRT_HOTPLUG_CPT	(1 << 19)
7647 #define SDE_SDVOB_HOTPLUG_CPT	(1 << 18)
7648 #define SDE_HOTPLUG_MASK_CPT	(SDE_CRT_HOTPLUG_CPT |		\
7649 				 SDE_SDVOB_HOTPLUG_CPT |	\
7650 				 SDE_PORTD_HOTPLUG_CPT |	\
7651 				 SDE_PORTC_HOTPLUG_CPT |	\
7652 				 SDE_PORTB_HOTPLUG_CPT)
7653 #define SDE_HOTPLUG_MASK_SPT	(SDE_PORTE_HOTPLUG_SPT |	\
7654 				 SDE_PORTD_HOTPLUG_CPT |	\
7655 				 SDE_PORTC_HOTPLUG_CPT |	\
7656 				 SDE_PORTB_HOTPLUG_CPT |	\
7657 				 SDE_PORTA_HOTPLUG_SPT)
7658 #define SDE_GMBUS_CPT		(1 << 17)
7659 #define SDE_ERROR_CPT		(1 << 16)
7660 #define SDE_AUDIO_CP_REQ_C_CPT	(1 << 10)
7661 #define SDE_AUDIO_CP_CHG_C_CPT	(1 << 9)
7662 #define SDE_FDI_RXC_CPT		(1 << 8)
7663 #define SDE_AUDIO_CP_REQ_B_CPT	(1 << 6)
7664 #define SDE_AUDIO_CP_CHG_B_CPT	(1 << 5)
7665 #define SDE_FDI_RXB_CPT		(1 << 4)
7666 #define SDE_AUDIO_CP_REQ_A_CPT	(1 << 2)
7667 #define SDE_AUDIO_CP_CHG_A_CPT	(1 << 1)
7668 #define SDE_FDI_RXA_CPT		(1 << 0)
7669 #define SDE_AUDIO_CP_REQ_CPT	(SDE_AUDIO_CP_REQ_C_CPT | \
7670 				 SDE_AUDIO_CP_REQ_B_CPT | \
7671 				 SDE_AUDIO_CP_REQ_A_CPT)
7672 #define SDE_AUDIO_CP_CHG_CPT	(SDE_AUDIO_CP_CHG_C_CPT | \
7673 				 SDE_AUDIO_CP_CHG_B_CPT | \
7674 				 SDE_AUDIO_CP_CHG_A_CPT)
7675 #define SDE_FDI_MASK_CPT	(SDE_FDI_RXC_CPT | \
7676 				 SDE_FDI_RXB_CPT | \
7677 				 SDE_FDI_RXA_CPT)
7678 
7679 /* south display engine interrupt: ICP */
7680 #define SDE_TC4_HOTPLUG_ICP		(1 << 27)
7681 #define SDE_TC3_HOTPLUG_ICP		(1 << 26)
7682 #define SDE_TC2_HOTPLUG_ICP		(1 << 25)
7683 #define SDE_TC1_HOTPLUG_ICP		(1 << 24)
7684 #define SDE_GMBUS_ICP			(1 << 23)
7685 #define SDE_DDIB_HOTPLUG_ICP		(1 << 17)
7686 #define SDE_DDIA_HOTPLUG_ICP		(1 << 16)
7687 #define SDE_TC_HOTPLUG_ICP(tc_port)	(1 << ((tc_port) + 24))
7688 #define SDE_DDI_HOTPLUG_ICP(port)	(1 << ((port) + 16))
7689 #define SDE_DDI_MASK_ICP		(SDE_DDIB_HOTPLUG_ICP |	\
7690 					 SDE_DDIA_HOTPLUG_ICP)
7691 #define SDE_TC_MASK_ICP			(SDE_TC4_HOTPLUG_ICP |	\
7692 					 SDE_TC3_HOTPLUG_ICP |	\
7693 					 SDE_TC2_HOTPLUG_ICP |	\
7694 					 SDE_TC1_HOTPLUG_ICP)
7695 
7696 #define SDEISR  _MMIO(0xc4000)
7697 #define SDEIMR  _MMIO(0xc4004)
7698 #define SDEIIR  _MMIO(0xc4008)
7699 #define SDEIER  _MMIO(0xc400c)
7700 
7701 #define SERR_INT			_MMIO(0xc4040)
7702 #define  SERR_INT_POISON		(1 << 31)
7703 #define  SERR_INT_TRANS_FIFO_UNDERRUN(pipe)	(1 << ((pipe) * 3))
7704 
7705 /* digital port hotplug */
7706 #define PCH_PORT_HOTPLUG		_MMIO(0xc4030)	/* SHOTPLUG_CTL */
7707 #define  PORTA_HOTPLUG_ENABLE		(1 << 28) /* LPT:LP+ & BXT */
7708 #define  BXT_DDIA_HPD_INVERT            (1 << 27)
7709 #define  PORTA_HOTPLUG_STATUS_MASK	(3 << 24) /* SPT+ & BXT */
7710 #define  PORTA_HOTPLUG_NO_DETECT	(0 << 24) /* SPT+ & BXT */
7711 #define  PORTA_HOTPLUG_SHORT_DETECT	(1 << 24) /* SPT+ & BXT */
7712 #define  PORTA_HOTPLUG_LONG_DETECT	(2 << 24) /* SPT+ & BXT */
7713 #define  PORTD_HOTPLUG_ENABLE		(1 << 20)
7714 #define  PORTD_PULSE_DURATION_2ms	(0 << 18) /* pre-LPT */
7715 #define  PORTD_PULSE_DURATION_4_5ms	(1 << 18) /* pre-LPT */
7716 #define  PORTD_PULSE_DURATION_6ms	(2 << 18) /* pre-LPT */
7717 #define  PORTD_PULSE_DURATION_100ms	(3 << 18) /* pre-LPT */
7718 #define  PORTD_PULSE_DURATION_MASK	(3 << 18) /* pre-LPT */
7719 #define  PORTD_HOTPLUG_STATUS_MASK	(3 << 16)
7720 #define  PORTD_HOTPLUG_NO_DETECT	(0 << 16)
7721 #define  PORTD_HOTPLUG_SHORT_DETECT	(1 << 16)
7722 #define  PORTD_HOTPLUG_LONG_DETECT	(2 << 16)
7723 #define  PORTC_HOTPLUG_ENABLE		(1 << 12)
7724 #define  BXT_DDIC_HPD_INVERT            (1 << 11)
7725 #define  PORTC_PULSE_DURATION_2ms	(0 << 10) /* pre-LPT */
7726 #define  PORTC_PULSE_DURATION_4_5ms	(1 << 10) /* pre-LPT */
7727 #define  PORTC_PULSE_DURATION_6ms	(2 << 10) /* pre-LPT */
7728 #define  PORTC_PULSE_DURATION_100ms	(3 << 10) /* pre-LPT */
7729 #define  PORTC_PULSE_DURATION_MASK	(3 << 10) /* pre-LPT */
7730 #define  PORTC_HOTPLUG_STATUS_MASK	(3 << 8)
7731 #define  PORTC_HOTPLUG_NO_DETECT	(0 << 8)
7732 #define  PORTC_HOTPLUG_SHORT_DETECT	(1 << 8)
7733 #define  PORTC_HOTPLUG_LONG_DETECT	(2 << 8)
7734 #define  PORTB_HOTPLUG_ENABLE		(1 << 4)
7735 #define  BXT_DDIB_HPD_INVERT            (1 << 3)
7736 #define  PORTB_PULSE_DURATION_2ms	(0 << 2) /* pre-LPT */
7737 #define  PORTB_PULSE_DURATION_4_5ms	(1 << 2) /* pre-LPT */
7738 #define  PORTB_PULSE_DURATION_6ms	(2 << 2) /* pre-LPT */
7739 #define  PORTB_PULSE_DURATION_100ms	(3 << 2) /* pre-LPT */
7740 #define  PORTB_PULSE_DURATION_MASK	(3 << 2) /* pre-LPT */
7741 #define  PORTB_HOTPLUG_STATUS_MASK	(3 << 0)
7742 #define  PORTB_HOTPLUG_NO_DETECT	(0 << 0)
7743 #define  PORTB_HOTPLUG_SHORT_DETECT	(1 << 0)
7744 #define  PORTB_HOTPLUG_LONG_DETECT	(2 << 0)
7745 #define  BXT_DDI_HPD_INVERT_MASK	(BXT_DDIA_HPD_INVERT | \
7746 					BXT_DDIB_HPD_INVERT | \
7747 					BXT_DDIC_HPD_INVERT)
7748 
7749 #define PCH_PORT_HOTPLUG2		_MMIO(0xc403C)	/* SHOTPLUG_CTL2 SPT+ */
7750 #define  PORTE_HOTPLUG_ENABLE		(1 << 4)
7751 #define  PORTE_HOTPLUG_STATUS_MASK	(3 << 0)
7752 #define  PORTE_HOTPLUG_NO_DETECT	(0 << 0)
7753 #define  PORTE_HOTPLUG_SHORT_DETECT	(1 << 0)
7754 #define  PORTE_HOTPLUG_LONG_DETECT	(2 << 0)
7755 
7756 /* This register is a reuse of PCH_PORT_HOTPLUG register. The
7757  * functionality covered in PCH_PORT_HOTPLUG is split into
7758  * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
7759  */
7760 
7761 #define SHOTPLUG_CTL_DDI			_MMIO(0xc4030)
7762 #define   ICP_DDIB_HPD_ENABLE			(1 << 7)
7763 #define   ICP_DDIB_HPD_STATUS_MASK		(3 << 4)
7764 #define   ICP_DDIB_HPD_NO_DETECT		(0 << 4)
7765 #define   ICP_DDIB_HPD_SHORT_DETECT		(1 << 4)
7766 #define   ICP_DDIB_HPD_LONG_DETECT		(2 << 4)
7767 #define   ICP_DDIB_HPD_SHORT_LONG_DETECT	(3 << 4)
7768 #define   ICP_DDIA_HPD_ENABLE			(1 << 3)
7769 #define   ICP_DDIA_HPD_OP_DRIVE_1		(1 << 2)
7770 #define   ICP_DDIA_HPD_STATUS_MASK		(3 << 0)
7771 #define   ICP_DDIA_HPD_NO_DETECT		(0 << 0)
7772 #define   ICP_DDIA_HPD_SHORT_DETECT		(1 << 0)
7773 #define   ICP_DDIA_HPD_LONG_DETECT		(2 << 0)
7774 #define   ICP_DDIA_HPD_SHORT_LONG_DETECT	(3 << 0)
7775 
7776 #define SHOTPLUG_CTL_TC				_MMIO(0xc4034)
7777 #define   ICP_TC_HPD_ENABLE(tc_port)		(8 << (tc_port) * 4)
7778 /* Icelake DSC Rate Control Range Parameter Registers */
7779 #define DSCA_RC_RANGE_PARAMETERS_0		_MMIO(0x6B240)
7780 #define DSCA_RC_RANGE_PARAMETERS_0_UDW		_MMIO(0x6B240 + 4)
7781 #define DSCC_RC_RANGE_PARAMETERS_0		_MMIO(0x6BA40)
7782 #define DSCC_RC_RANGE_PARAMETERS_0_UDW		_MMIO(0x6BA40 + 4)
7783 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB	(0x78208)
7784 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB	(0x78208 + 4)
7785 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB	(0x78308)
7786 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB	(0x78308 + 4)
7787 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC	(0x78408)
7788 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC	(0x78408 + 4)
7789 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC	(0x78508)
7790 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC	(0x78508 + 4)
7791 #define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
7792 							_ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
7793 							_ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
7794 #define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
7795 							_ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
7796 							_ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
7797 #define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
7798 							_ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
7799 							_ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
7800 #define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
7801 							_ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
7802 							_ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
7803 #define RC_BPG_OFFSET_SHIFT			10
7804 #define RC_MAX_QP_SHIFT				5
7805 #define RC_MIN_QP_SHIFT				0
7806 
7807 #define DSCA_RC_RANGE_PARAMETERS_1		_MMIO(0x6B248)
7808 #define DSCA_RC_RANGE_PARAMETERS_1_UDW		_MMIO(0x6B248 + 4)
7809 #define DSCC_RC_RANGE_PARAMETERS_1		_MMIO(0x6BA48)
7810 #define DSCC_RC_RANGE_PARAMETERS_1_UDW		_MMIO(0x6BA48 + 4)
7811 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB	(0x78210)
7812 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB	(0x78210 + 4)
7813 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB	(0x78310)
7814 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB	(0x78310 + 4)
7815 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC	(0x78410)
7816 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC	(0x78410 + 4)
7817 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC	(0x78510)
7818 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC	(0x78510 + 4)
7819 #define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
7820 							_ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
7821 							_ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
7822 #define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
7823 							_ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
7824 							_ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
7825 #define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
7826 							_ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
7827 							_ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
7828 #define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
7829 							_ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
7830 							_ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
7831 
7832 #define DSCA_RC_RANGE_PARAMETERS_2		_MMIO(0x6B250)
7833 #define DSCA_RC_RANGE_PARAMETERS_2_UDW		_MMIO(0x6B250 + 4)
7834 #define DSCC_RC_RANGE_PARAMETERS_2		_MMIO(0x6BA50)
7835 #define DSCC_RC_RANGE_PARAMETERS_2_UDW		_MMIO(0x6BA50 + 4)
7836 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB	(0x78218)
7837 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB	(0x78218 + 4)
7838 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB	(0x78318)
7839 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB	(0x78318 + 4)
7840 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC	(0x78418)
7841 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC	(0x78418 + 4)
7842 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC	(0x78518)
7843 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC	(0x78518 + 4)
7844 #define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
7845 							_ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
7846 							_ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
7847 #define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
7848 							_ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
7849 							_ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
7850 #define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
7851 							_ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
7852 							_ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
7853 #define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
7854 							_ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
7855 							_ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
7856 
7857 #define DSCA_RC_RANGE_PARAMETERS_3		_MMIO(0x6B258)
7858 #define DSCA_RC_RANGE_PARAMETERS_3_UDW		_MMIO(0x6B258 + 4)
7859 #define DSCC_RC_RANGE_PARAMETERS_3		_MMIO(0x6BA58)
7860 #define DSCC_RC_RANGE_PARAMETERS_3_UDW		_MMIO(0x6BA58 + 4)
7861 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB	(0x78220)
7862 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB	(0x78220 + 4)
7863 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB	(0x78320)
7864 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB	(0x78320 + 4)
7865 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC	(0x78420)
7866 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC	(0x78420 + 4)
7867 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC	(0x78520)
7868 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC	(0x78520 + 4)
7869 #define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
7870 							_ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
7871 							_ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
7872 #define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
7873 							_ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
7874 							_ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
7875 #define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
7876 							_ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
7877 							_ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
7878 #define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
7879 							_ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
7880 							_ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
7881 
7882 #define   ICP_TC_HPD_LONG_DETECT(tc_port)	(2 << (tc_port) * 4)
7883 #define   ICP_TC_HPD_SHORT_DETECT(tc_port)	(1 << (tc_port) * 4)
7884 
7885 #define _PCH_DPLL_A              0xc6014
7886 #define _PCH_DPLL_B              0xc6018
7887 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
7888 
7889 #define _PCH_FPA0                0xc6040
7890 #define  FP_CB_TUNE		(0x3 << 22)
7891 #define _PCH_FPA1                0xc6044
7892 #define _PCH_FPB0                0xc6048
7893 #define _PCH_FPB1                0xc604c
7894 #define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0)
7895 #define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1)
7896 
7897 #define PCH_DPLL_TEST           _MMIO(0xc606c)
7898 
7899 #define PCH_DREF_CONTROL        _MMIO(0xC6200)
7900 #define  DREF_CONTROL_MASK      0x7fc3
7901 #define  DREF_CPU_SOURCE_OUTPUT_DISABLE         (0 << 13)
7902 #define  DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD      (2 << 13)
7903 #define  DREF_CPU_SOURCE_OUTPUT_NONSPREAD       (3 << 13)
7904 #define  DREF_CPU_SOURCE_OUTPUT_MASK		(3 << 13)
7905 #define  DREF_SSC_SOURCE_DISABLE                (0 << 11)
7906 #define  DREF_SSC_SOURCE_ENABLE                 (2 << 11)
7907 #define  DREF_SSC_SOURCE_MASK			(3 << 11)
7908 #define  DREF_NONSPREAD_SOURCE_DISABLE          (0 << 9)
7909 #define  DREF_NONSPREAD_CK505_ENABLE		(1 << 9)
7910 #define  DREF_NONSPREAD_SOURCE_ENABLE           (2 << 9)
7911 #define  DREF_NONSPREAD_SOURCE_MASK		(3 << 9)
7912 #define  DREF_SUPERSPREAD_SOURCE_DISABLE        (0 << 7)
7913 #define  DREF_SUPERSPREAD_SOURCE_ENABLE         (2 << 7)
7914 #define  DREF_SUPERSPREAD_SOURCE_MASK		(3 << 7)
7915 #define  DREF_SSC4_DOWNSPREAD                   (0 << 6)
7916 #define  DREF_SSC4_CENTERSPREAD                 (1 << 6)
7917 #define  DREF_SSC1_DISABLE                      (0 << 1)
7918 #define  DREF_SSC1_ENABLE                       (1 << 1)
7919 #define  DREF_SSC4_DISABLE                      (0)
7920 #define  DREF_SSC4_ENABLE                       (1)
7921 
7922 #define PCH_RAWCLK_FREQ         _MMIO(0xc6204)
7923 #define  FDL_TP1_TIMER_SHIFT    12
7924 #define  FDL_TP1_TIMER_MASK     (3 << 12)
7925 #define  FDL_TP2_TIMER_SHIFT    10
7926 #define  FDL_TP2_TIMER_MASK     (3 << 10)
7927 #define  RAWCLK_FREQ_MASK       0x3ff
7928 #define  CNP_RAWCLK_DIV_MASK	(0x3ff << 16)
7929 #define  CNP_RAWCLK_DIV(div)	((div) << 16)
7930 #define  CNP_RAWCLK_FRAC_MASK	(0xf << 26)
7931 #define  CNP_RAWCLK_DEN(den)	((den) << 26)
7932 #define  ICP_RAWCLK_NUM(num)	((num) << 11)
7933 
7934 #define PCH_DPLL_TMR_CFG        _MMIO(0xc6208)
7935 
7936 #define PCH_SSC4_PARMS          _MMIO(0xc6210)
7937 #define PCH_SSC4_AUX_PARMS      _MMIO(0xc6214)
7938 
7939 #define PCH_DPLL_SEL		_MMIO(0xc7000)
7940 #define	 TRANS_DPLLB_SEL(pipe)		(1 << ((pipe) * 4))
7941 #define	 TRANS_DPLLA_SEL(pipe)		0
7942 #define  TRANS_DPLL_ENABLE(pipe)	(1 << ((pipe) * 4 + 3))
7943 
7944 /* transcoder */
7945 
7946 #define _PCH_TRANS_HTOTAL_A		0xe0000
7947 #define  TRANS_HTOTAL_SHIFT		16
7948 #define  TRANS_HACTIVE_SHIFT		0
7949 #define _PCH_TRANS_HBLANK_A		0xe0004
7950 #define  TRANS_HBLANK_END_SHIFT		16
7951 #define  TRANS_HBLANK_START_SHIFT	0
7952 #define _PCH_TRANS_HSYNC_A		0xe0008
7953 #define  TRANS_HSYNC_END_SHIFT		16
7954 #define  TRANS_HSYNC_START_SHIFT	0
7955 #define _PCH_TRANS_VTOTAL_A		0xe000c
7956 #define  TRANS_VTOTAL_SHIFT		16
7957 #define  TRANS_VACTIVE_SHIFT		0
7958 #define _PCH_TRANS_VBLANK_A		0xe0010
7959 #define  TRANS_VBLANK_END_SHIFT		16
7960 #define  TRANS_VBLANK_START_SHIFT	0
7961 #define _PCH_TRANS_VSYNC_A		0xe0014
7962 #define  TRANS_VSYNC_END_SHIFT		16
7963 #define  TRANS_VSYNC_START_SHIFT	0
7964 #define _PCH_TRANS_VSYNCSHIFT_A		0xe0028
7965 
7966 #define _PCH_TRANSA_DATA_M1	0xe0030
7967 #define _PCH_TRANSA_DATA_N1	0xe0034
7968 #define _PCH_TRANSA_DATA_M2	0xe0038
7969 #define _PCH_TRANSA_DATA_N2	0xe003c
7970 #define _PCH_TRANSA_LINK_M1	0xe0040
7971 #define _PCH_TRANSA_LINK_N1	0xe0044
7972 #define _PCH_TRANSA_LINK_M2	0xe0048
7973 #define _PCH_TRANSA_LINK_N2	0xe004c
7974 
7975 /* Per-transcoder DIP controls (PCH) */
7976 #define _VIDEO_DIP_CTL_A         0xe0200
7977 #define _VIDEO_DIP_DATA_A        0xe0208
7978 #define _VIDEO_DIP_GCP_A         0xe0210
7979 #define  GCP_COLOR_INDICATION		(1 << 2)
7980 #define  GCP_DEFAULT_PHASE_ENABLE	(1 << 1)
7981 #define  GCP_AV_MUTE			(1 << 0)
7982 
7983 #define _VIDEO_DIP_CTL_B         0xe1200
7984 #define _VIDEO_DIP_DATA_B        0xe1208
7985 #define _VIDEO_DIP_GCP_B         0xe1210
7986 
7987 #define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
7988 #define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
7989 #define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
7990 
7991 /* Per-transcoder DIP controls (VLV) */
7992 #define _VLV_VIDEO_DIP_CTL_A		(VLV_DISPLAY_BASE + 0x60200)
7993 #define _VLV_VIDEO_DIP_DATA_A		(VLV_DISPLAY_BASE + 0x60208)
7994 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A	(VLV_DISPLAY_BASE + 0x60210)
7995 
7996 #define _VLV_VIDEO_DIP_CTL_B		(VLV_DISPLAY_BASE + 0x61170)
7997 #define _VLV_VIDEO_DIP_DATA_B		(VLV_DISPLAY_BASE + 0x61174)
7998 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B	(VLV_DISPLAY_BASE + 0x61178)
7999 
8000 #define _CHV_VIDEO_DIP_CTL_C		(VLV_DISPLAY_BASE + 0x611f0)
8001 #define _CHV_VIDEO_DIP_DATA_C		(VLV_DISPLAY_BASE + 0x611f4)
8002 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C	(VLV_DISPLAY_BASE + 0x611f8)
8003 
8004 #define VLV_TVIDEO_DIP_CTL(pipe) \
8005 	_MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \
8006 	       _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C)
8007 #define VLV_TVIDEO_DIP_DATA(pipe) \
8008 	_MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \
8009 	       _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C)
8010 #define VLV_TVIDEO_DIP_GCP(pipe) \
8011 	_MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
8012 		_VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
8013 
8014 /* Haswell DIP controls */
8015 
8016 #define _HSW_VIDEO_DIP_CTL_A		0x60200
8017 #define _HSW_VIDEO_DIP_AVI_DATA_A	0x60220
8018 #define _HSW_VIDEO_DIP_VS_DATA_A	0x60260
8019 #define _HSW_VIDEO_DIP_SPD_DATA_A	0x602A0
8020 #define _HSW_VIDEO_DIP_GMP_DATA_A	0x602E0
8021 #define _HSW_VIDEO_DIP_VSC_DATA_A	0x60320
8022 #define _HSW_VIDEO_DIP_AVI_ECC_A	0x60240
8023 #define _HSW_VIDEO_DIP_VS_ECC_A		0x60280
8024 #define _HSW_VIDEO_DIP_SPD_ECC_A	0x602C0
8025 #define _HSW_VIDEO_DIP_GMP_ECC_A	0x60300
8026 #define _HSW_VIDEO_DIP_VSC_ECC_A	0x60344
8027 #define _HSW_VIDEO_DIP_GCP_A		0x60210
8028 
8029 #define _HSW_VIDEO_DIP_CTL_B		0x61200
8030 #define _HSW_VIDEO_DIP_AVI_DATA_B	0x61220
8031 #define _HSW_VIDEO_DIP_VS_DATA_B	0x61260
8032 #define _HSW_VIDEO_DIP_SPD_DATA_B	0x612A0
8033 #define _HSW_VIDEO_DIP_GMP_DATA_B	0x612E0
8034 #define _HSW_VIDEO_DIP_VSC_DATA_B	0x61320
8035 #define _HSW_VIDEO_DIP_BVI_ECC_B	0x61240
8036 #define _HSW_VIDEO_DIP_VS_ECC_B		0x61280
8037 #define _HSW_VIDEO_DIP_SPD_ECC_B	0x612C0
8038 #define _HSW_VIDEO_DIP_GMP_ECC_B	0x61300
8039 #define _HSW_VIDEO_DIP_VSC_ECC_B	0x61344
8040 #define _HSW_VIDEO_DIP_GCP_B		0x61210
8041 
8042 /* Icelake PPS_DATA and _ECC DIP Registers.
8043  * These are available for transcoders B,C and eDP.
8044  * Adding the _A so as to reuse the _MMIO_TRANS2
8045  * definition, with which it offsets to the right location.
8046  */
8047 
8048 #define _ICL_VIDEO_DIP_PPS_DATA_A	0x60350
8049 #define _ICL_VIDEO_DIP_PPS_DATA_B	0x61350
8050 #define _ICL_VIDEO_DIP_PPS_ECC_A	0x603D4
8051 #define _ICL_VIDEO_DIP_PPS_ECC_B	0x613D4
8052 
8053 #define HSW_TVIDEO_DIP_CTL(trans)		_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A)
8054 #define HSW_TVIDEO_DIP_AVI_DATA(trans, i)	_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
8055 #define HSW_TVIDEO_DIP_VS_DATA(trans, i)	_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
8056 #define HSW_TVIDEO_DIP_SPD_DATA(trans, i)	_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
8057 #define HSW_TVIDEO_DIP_GCP(trans)		_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A)
8058 #define HSW_TVIDEO_DIP_VSC_DATA(trans, i)	_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
8059 #define ICL_VIDEO_DIP_PPS_DATA(trans, i)	_MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
8060 #define ICL_VIDEO_DIP_PPS_ECC(trans, i)		_MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
8061 
8062 #define _HSW_STEREO_3D_CTL_A		0x70020
8063 #define   S3D_ENABLE			(1 << 31)
8064 #define _HSW_STEREO_3D_CTL_B		0x71020
8065 
8066 #define HSW_STEREO_3D_CTL(trans)	_MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A)
8067 
8068 #define _PCH_TRANS_HTOTAL_B          0xe1000
8069 #define _PCH_TRANS_HBLANK_B          0xe1004
8070 #define _PCH_TRANS_HSYNC_B           0xe1008
8071 #define _PCH_TRANS_VTOTAL_B          0xe100c
8072 #define _PCH_TRANS_VBLANK_B          0xe1010
8073 #define _PCH_TRANS_VSYNC_B           0xe1014
8074 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
8075 
8076 #define PCH_TRANS_HTOTAL(pipe)		_MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
8077 #define PCH_TRANS_HBLANK(pipe)		_MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
8078 #define PCH_TRANS_HSYNC(pipe)		_MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
8079 #define PCH_TRANS_VTOTAL(pipe)		_MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
8080 #define PCH_TRANS_VBLANK(pipe)		_MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
8081 #define PCH_TRANS_VSYNC(pipe)		_MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
8082 #define PCH_TRANS_VSYNCSHIFT(pipe)	_MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
8083 
8084 #define _PCH_TRANSB_DATA_M1	0xe1030
8085 #define _PCH_TRANSB_DATA_N1	0xe1034
8086 #define _PCH_TRANSB_DATA_M2	0xe1038
8087 #define _PCH_TRANSB_DATA_N2	0xe103c
8088 #define _PCH_TRANSB_LINK_M1	0xe1040
8089 #define _PCH_TRANSB_LINK_N1	0xe1044
8090 #define _PCH_TRANSB_LINK_M2	0xe1048
8091 #define _PCH_TRANSB_LINK_N2	0xe104c
8092 
8093 #define PCH_TRANS_DATA_M1(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
8094 #define PCH_TRANS_DATA_N1(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
8095 #define PCH_TRANS_DATA_M2(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
8096 #define PCH_TRANS_DATA_N2(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
8097 #define PCH_TRANS_LINK_M1(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
8098 #define PCH_TRANS_LINK_N1(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
8099 #define PCH_TRANS_LINK_M2(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
8100 #define PCH_TRANS_LINK_N2(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
8101 
8102 #define _PCH_TRANSACONF              0xf0008
8103 #define _PCH_TRANSBCONF              0xf1008
8104 #define PCH_TRANSCONF(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
8105 #define LPT_TRANSCONF		PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
8106 #define  TRANS_DISABLE          (0 << 31)
8107 #define  TRANS_ENABLE           (1 << 31)
8108 #define  TRANS_STATE_MASK       (1 << 30)
8109 #define  TRANS_STATE_DISABLE    (0 << 30)
8110 #define  TRANS_STATE_ENABLE     (1 << 30)
8111 #define  TRANS_FSYNC_DELAY_HB1  (0 << 27)
8112 #define  TRANS_FSYNC_DELAY_HB2  (1 << 27)
8113 #define  TRANS_FSYNC_DELAY_HB3  (2 << 27)
8114 #define  TRANS_FSYNC_DELAY_HB4  (3 << 27)
8115 #define  TRANS_INTERLACE_MASK   (7 << 21)
8116 #define  TRANS_PROGRESSIVE      (0 << 21)
8117 #define  TRANS_INTERLACED       (3 << 21)
8118 #define  TRANS_LEGACY_INTERLACED_ILK (2 << 21)
8119 #define  TRANS_8BPC             (0 << 5)
8120 #define  TRANS_10BPC            (1 << 5)
8121 #define  TRANS_6BPC             (2 << 5)
8122 #define  TRANS_12BPC            (3 << 5)
8123 
8124 #define _TRANSA_CHICKEN1	 0xf0060
8125 #define _TRANSB_CHICKEN1	 0xf1060
8126 #define TRANS_CHICKEN1(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
8127 #define  TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE	(1 << 10)
8128 #define  TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	(1 << 4)
8129 #define _TRANSA_CHICKEN2	 0xf0064
8130 #define _TRANSB_CHICKEN2	 0xf1064
8131 #define TRANS_CHICKEN2(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
8132 #define  TRANS_CHICKEN2_TIMING_OVERRIDE			(1 << 31)
8133 #define  TRANS_CHICKEN2_FDI_POLARITY_REVERSED		(1 << 29)
8134 #define  TRANS_CHICKEN2_FRAME_START_DELAY_MASK		(3 << 27)
8135 #define  TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER	(1 << 26)
8136 #define  TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH	(1 << 25)
8137 
8138 #define SOUTH_CHICKEN1		_MMIO(0xc2000)
8139 #define  FDIA_PHASE_SYNC_SHIFT_OVR	19
8140 #define  FDIA_PHASE_SYNC_SHIFT_EN	18
8141 #define  FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
8142 #define  FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
8143 #define  FDI_BC_BIFURCATION_SELECT	(1 << 12)
8144 #define  CHASSIS_CLK_REQ_DURATION_MASK	(0xf << 8)
8145 #define  CHASSIS_CLK_REQ_DURATION(x)	((x) << 8)
8146 #define  SPT_PWM_GRANULARITY		(1 << 0)
8147 #define SOUTH_CHICKEN2		_MMIO(0xc2004)
8148 #define  FDI_MPHY_IOSFSB_RESET_STATUS	(1 << 13)
8149 #define  FDI_MPHY_IOSFSB_RESET_CTL	(1 << 12)
8150 #define  LPT_PWM_GRANULARITY		(1 << 5)
8151 #define  DPLS_EDP_PPS_FIX_DIS		(1 << 0)
8152 
8153 #define _FDI_RXA_CHICKEN        0xc200c
8154 #define _FDI_RXB_CHICKEN        0xc2010
8155 #define  FDI_RX_PHASE_SYNC_POINTER_OVR	(1 << 1)
8156 #define  FDI_RX_PHASE_SYNC_POINTER_EN	(1 << 0)
8157 #define FDI_RX_CHICKEN(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
8158 
8159 #define SOUTH_DSPCLK_GATE_D	_MMIO(0xc2020)
8160 #define  PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
8161 #define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
8162 #define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
8163 #define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
8164 #define  CNP_PWM_CGE_GATING_DISABLE (1 << 13)
8165 #define  PCH_LP_PARTITION_LEVEL_DISABLE  (1 << 12)
8166 
8167 /* CPU: FDI_TX */
8168 #define _FDI_TXA_CTL            0x60100
8169 #define _FDI_TXB_CTL            0x61100
8170 #define FDI_TX_CTL(pipe)	_MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
8171 #define  FDI_TX_DISABLE         (0 << 31)
8172 #define  FDI_TX_ENABLE          (1 << 31)
8173 #define  FDI_LINK_TRAIN_PATTERN_1       (0 << 28)
8174 #define  FDI_LINK_TRAIN_PATTERN_2       (1 << 28)
8175 #define  FDI_LINK_TRAIN_PATTERN_IDLE    (2 << 28)
8176 #define  FDI_LINK_TRAIN_NONE            (3 << 28)
8177 #define  FDI_LINK_TRAIN_VOLTAGE_0_4V    (0 << 25)
8178 #define  FDI_LINK_TRAIN_VOLTAGE_0_6V    (1 << 25)
8179 #define  FDI_LINK_TRAIN_VOLTAGE_0_8V    (2 << 25)
8180 #define  FDI_LINK_TRAIN_VOLTAGE_1_2V    (3 << 25)
8181 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22)
8182 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22)
8183 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_2X   (2 << 22)
8184 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_3X   (3 << 22)
8185 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
8186    SNB has different settings. */
8187 /* SNB A-stepping */
8188 #define  FDI_LINK_TRAIN_400MV_0DB_SNB_A		(0x38 << 22)
8189 #define  FDI_LINK_TRAIN_400MV_6DB_SNB_A		(0x02 << 22)
8190 #define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_A	(0x01 << 22)
8191 #define  FDI_LINK_TRAIN_800MV_0DB_SNB_A		(0x0 << 22)
8192 /* SNB B-stepping */
8193 #define  FDI_LINK_TRAIN_400MV_0DB_SNB_B		(0x0 << 22)
8194 #define  FDI_LINK_TRAIN_400MV_6DB_SNB_B		(0x3a << 22)
8195 #define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_B	(0x39 << 22)
8196 #define  FDI_LINK_TRAIN_800MV_0DB_SNB_B		(0x38 << 22)
8197 #define  FDI_LINK_TRAIN_VOL_EMP_MASK		(0x3f << 22)
8198 #define  FDI_DP_PORT_WIDTH_SHIFT		19
8199 #define  FDI_DP_PORT_WIDTH_MASK			(7 << FDI_DP_PORT_WIDTH_SHIFT)
8200 #define  FDI_DP_PORT_WIDTH(width)           (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
8201 #define  FDI_TX_ENHANCE_FRAME_ENABLE    (1 << 18)
8202 /* Ironlake: hardwired to 1 */
8203 #define  FDI_TX_PLL_ENABLE              (1 << 14)
8204 
8205 /* Ivybridge has different bits for lolz */
8206 #define  FDI_LINK_TRAIN_PATTERN_1_IVB       (0 << 8)
8207 #define  FDI_LINK_TRAIN_PATTERN_2_IVB       (1 << 8)
8208 #define  FDI_LINK_TRAIN_PATTERN_IDLE_IVB    (2 << 8)
8209 #define  FDI_LINK_TRAIN_NONE_IVB            (3 << 8)
8210 
8211 /* both Tx and Rx */
8212 #define  FDI_COMPOSITE_SYNC		(1 << 11)
8213 #define  FDI_LINK_TRAIN_AUTO		(1 << 10)
8214 #define  FDI_SCRAMBLING_ENABLE          (0 << 7)
8215 #define  FDI_SCRAMBLING_DISABLE         (1 << 7)
8216 
8217 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
8218 #define _FDI_RXA_CTL             0xf000c
8219 #define _FDI_RXB_CTL             0xf100c
8220 #define FDI_RX_CTL(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
8221 #define  FDI_RX_ENABLE          (1 << 31)
8222 /* train, dp width same as FDI_TX */
8223 #define  FDI_FS_ERRC_ENABLE		(1 << 27)
8224 #define  FDI_FE_ERRC_ENABLE		(1 << 26)
8225 #define  FDI_RX_POLARITY_REVERSED_LPT	(1 << 16)
8226 #define  FDI_8BPC                       (0 << 16)
8227 #define  FDI_10BPC                      (1 << 16)
8228 #define  FDI_6BPC                       (2 << 16)
8229 #define  FDI_12BPC                      (3 << 16)
8230 #define  FDI_RX_LINK_REVERSAL_OVERRIDE  (1 << 15)
8231 #define  FDI_DMI_LINK_REVERSE_MASK      (1 << 14)
8232 #define  FDI_RX_PLL_ENABLE              (1 << 13)
8233 #define  FDI_FS_ERR_CORRECT_ENABLE      (1 << 11)
8234 #define  FDI_FE_ERR_CORRECT_ENABLE      (1 << 10)
8235 #define  FDI_FS_ERR_REPORT_ENABLE       (1 << 9)
8236 #define  FDI_FE_ERR_REPORT_ENABLE       (1 << 8)
8237 #define  FDI_RX_ENHANCE_FRAME_ENABLE    (1 << 6)
8238 #define  FDI_PCDCLK	                (1 << 4)
8239 /* CPT */
8240 #define  FDI_AUTO_TRAINING			(1 << 10)
8241 #define  FDI_LINK_TRAIN_PATTERN_1_CPT		(0 << 8)
8242 #define  FDI_LINK_TRAIN_PATTERN_2_CPT		(1 << 8)
8243 #define  FDI_LINK_TRAIN_PATTERN_IDLE_CPT	(2 << 8)
8244 #define  FDI_LINK_TRAIN_NORMAL_CPT		(3 << 8)
8245 #define  FDI_LINK_TRAIN_PATTERN_MASK_CPT	(3 << 8)
8246 
8247 #define _FDI_RXA_MISC			0xf0010
8248 #define _FDI_RXB_MISC			0xf1010
8249 #define  FDI_RX_PWRDN_LANE1_MASK	(3 << 26)
8250 #define  FDI_RX_PWRDN_LANE1_VAL(x)	((x) << 26)
8251 #define  FDI_RX_PWRDN_LANE0_MASK	(3 << 24)
8252 #define  FDI_RX_PWRDN_LANE0_VAL(x)	((x) << 24)
8253 #define  FDI_RX_TP1_TO_TP2_48		(2 << 20)
8254 #define  FDI_RX_TP1_TO_TP2_64		(3 << 20)
8255 #define  FDI_RX_FDI_DELAY_90		(0x90 << 0)
8256 #define FDI_RX_MISC(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
8257 
8258 #define _FDI_RXA_TUSIZE1        0xf0030
8259 #define _FDI_RXA_TUSIZE2        0xf0038
8260 #define _FDI_RXB_TUSIZE1        0xf1030
8261 #define _FDI_RXB_TUSIZE2        0xf1038
8262 #define FDI_RX_TUSIZE1(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
8263 #define FDI_RX_TUSIZE2(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
8264 
8265 /* FDI_RX interrupt register format */
8266 #define FDI_RX_INTER_LANE_ALIGN         (1 << 10)
8267 #define FDI_RX_SYMBOL_LOCK              (1 << 9) /* train 2 */
8268 #define FDI_RX_BIT_LOCK                 (1 << 8) /* train 1 */
8269 #define FDI_RX_TRAIN_PATTERN_2_FAIL     (1 << 7)
8270 #define FDI_RX_FS_CODE_ERR              (1 << 6)
8271 #define FDI_RX_FE_CODE_ERR              (1 << 5)
8272 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE    (1 << 4)
8273 #define FDI_RX_HDCP_LINK_FAIL           (1 << 3)
8274 #define FDI_RX_PIXEL_FIFO_OVERFLOW      (1 << 2)
8275 #define FDI_RX_CROSS_CLOCK_OVERFLOW     (1 << 1)
8276 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW    (1 << 0)
8277 
8278 #define _FDI_RXA_IIR            0xf0014
8279 #define _FDI_RXA_IMR            0xf0018
8280 #define _FDI_RXB_IIR            0xf1014
8281 #define _FDI_RXB_IMR            0xf1018
8282 #define FDI_RX_IIR(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
8283 #define FDI_RX_IMR(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
8284 
8285 #define FDI_PLL_CTL_1           _MMIO(0xfe000)
8286 #define FDI_PLL_CTL_2           _MMIO(0xfe004)
8287 
8288 #define PCH_LVDS	_MMIO(0xe1180)
8289 #define  LVDS_DETECTED	(1 << 1)
8290 
8291 #define _PCH_DP_B		0xe4100
8292 #define PCH_DP_B		_MMIO(_PCH_DP_B)
8293 #define _PCH_DPB_AUX_CH_CTL	0xe4110
8294 #define _PCH_DPB_AUX_CH_DATA1	0xe4114
8295 #define _PCH_DPB_AUX_CH_DATA2	0xe4118
8296 #define _PCH_DPB_AUX_CH_DATA3	0xe411c
8297 #define _PCH_DPB_AUX_CH_DATA4	0xe4120
8298 #define _PCH_DPB_AUX_CH_DATA5	0xe4124
8299 
8300 #define _PCH_DP_C		0xe4200
8301 #define PCH_DP_C		_MMIO(_PCH_DP_C)
8302 #define _PCH_DPC_AUX_CH_CTL	0xe4210
8303 #define _PCH_DPC_AUX_CH_DATA1	0xe4214
8304 #define _PCH_DPC_AUX_CH_DATA2	0xe4218
8305 #define _PCH_DPC_AUX_CH_DATA3	0xe421c
8306 #define _PCH_DPC_AUX_CH_DATA4	0xe4220
8307 #define _PCH_DPC_AUX_CH_DATA5	0xe4224
8308 
8309 #define _PCH_DP_D		0xe4300
8310 #define PCH_DP_D		_MMIO(_PCH_DP_D)
8311 #define _PCH_DPD_AUX_CH_CTL	0xe4310
8312 #define _PCH_DPD_AUX_CH_DATA1	0xe4314
8313 #define _PCH_DPD_AUX_CH_DATA2	0xe4318
8314 #define _PCH_DPD_AUX_CH_DATA3	0xe431c
8315 #define _PCH_DPD_AUX_CH_DATA4	0xe4320
8316 #define _PCH_DPD_AUX_CH_DATA5	0xe4324
8317 
8318 #define PCH_DP_AUX_CH_CTL(aux_ch)		_MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
8319 #define PCH_DP_AUX_CH_DATA(aux_ch, i)	_MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
8320 
8321 /* CPT */
8322 #define _TRANS_DP_CTL_A		0xe0300
8323 #define _TRANS_DP_CTL_B		0xe1300
8324 #define _TRANS_DP_CTL_C		0xe2300
8325 #define TRANS_DP_CTL(pipe)	_MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
8326 #define  TRANS_DP_OUTPUT_ENABLE	(1 << 31)
8327 #define  TRANS_DP_PORT_SEL_MASK		(3 << 29)
8328 #define  TRANS_DP_PORT_SEL_NONE		(3 << 29)
8329 #define  TRANS_DP_PORT_SEL(port)	(((port) - PORT_B) << 29)
8330 #define  TRANS_DP_AUDIO_ONLY	(1 << 26)
8331 #define  TRANS_DP_ENH_FRAMING	(1 << 18)
8332 #define  TRANS_DP_8BPC		(0 << 9)
8333 #define  TRANS_DP_10BPC		(1 << 9)
8334 #define  TRANS_DP_6BPC		(2 << 9)
8335 #define  TRANS_DP_12BPC		(3 << 9)
8336 #define  TRANS_DP_BPC_MASK	(3 << 9)
8337 #define  TRANS_DP_VSYNC_ACTIVE_HIGH	(1 << 4)
8338 #define  TRANS_DP_VSYNC_ACTIVE_LOW	0
8339 #define  TRANS_DP_HSYNC_ACTIVE_HIGH	(1 << 3)
8340 #define  TRANS_DP_HSYNC_ACTIVE_LOW	0
8341 #define  TRANS_DP_SYNC_MASK	(3 << 3)
8342 
8343 /* SNB eDP training params */
8344 /* SNB A-stepping */
8345 #define  EDP_LINK_TRAIN_400MV_0DB_SNB_A		(0x38 << 22)
8346 #define  EDP_LINK_TRAIN_400MV_6DB_SNB_A		(0x02 << 22)
8347 #define  EDP_LINK_TRAIN_600MV_3_5DB_SNB_A	(0x01 << 22)
8348 #define  EDP_LINK_TRAIN_800MV_0DB_SNB_A		(0x0 << 22)
8349 /* SNB B-stepping */
8350 #define  EDP_LINK_TRAIN_400_600MV_0DB_SNB_B	(0x0 << 22)
8351 #define  EDP_LINK_TRAIN_400MV_3_5DB_SNB_B	(0x1 << 22)
8352 #define  EDP_LINK_TRAIN_400_600MV_6DB_SNB_B	(0x3a << 22)
8353 #define  EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B	(0x39 << 22)
8354 #define  EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B	(0x38 << 22)
8355 #define  EDP_LINK_TRAIN_VOL_EMP_MASK_SNB	(0x3f << 22)
8356 
8357 /* IVB */
8358 #define EDP_LINK_TRAIN_400MV_0DB_IVB		(0x24 << 22)
8359 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB		(0x2a << 22)
8360 #define EDP_LINK_TRAIN_400MV_6DB_IVB		(0x2f << 22)
8361 #define EDP_LINK_TRAIN_600MV_0DB_IVB		(0x30 << 22)
8362 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB		(0x36 << 22)
8363 #define EDP_LINK_TRAIN_800MV_0DB_IVB		(0x38 << 22)
8364 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB		(0x3e << 22)
8365 
8366 /* legacy values */
8367 #define EDP_LINK_TRAIN_500MV_0DB_IVB		(0x00 << 22)
8368 #define EDP_LINK_TRAIN_1000MV_0DB_IVB		(0x20 << 22)
8369 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB		(0x02 << 22)
8370 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB		(0x22 << 22)
8371 #define EDP_LINK_TRAIN_1000MV_6DB_IVB		(0x23 << 22)
8372 
8373 #define  EDP_LINK_TRAIN_VOL_EMP_MASK_IVB	(0x3f << 22)
8374 
8375 #define  VLV_PMWGICZ				_MMIO(0x1300a4)
8376 
8377 #define  RC6_LOCATION				_MMIO(0xD40)
8378 #define	   RC6_CTX_IN_DRAM			(1 << 0)
8379 #define  RC6_CTX_BASE				_MMIO(0xD48)
8380 #define    RC6_CTX_BASE_MASK			0xFFFFFFF0
8381 #define  PWRCTX_MAXCNT_RCSUNIT			_MMIO(0x2054)
8382 #define  PWRCTX_MAXCNT_VCSUNIT0			_MMIO(0x12054)
8383 #define  PWRCTX_MAXCNT_BCSUNIT			_MMIO(0x22054)
8384 #define  PWRCTX_MAXCNT_VECSUNIT			_MMIO(0x1A054)
8385 #define  PWRCTX_MAXCNT_VCSUNIT1			_MMIO(0x1C054)
8386 #define    IDLE_TIME_MASK			0xFFFFF
8387 #define  FORCEWAKE				_MMIO(0xA18C)
8388 #define  FORCEWAKE_VLV				_MMIO(0x1300b0)
8389 #define  FORCEWAKE_ACK_VLV			_MMIO(0x1300b4)
8390 #define  FORCEWAKE_MEDIA_VLV			_MMIO(0x1300b8)
8391 #define  FORCEWAKE_ACK_MEDIA_VLV		_MMIO(0x1300bc)
8392 #define  FORCEWAKE_ACK_HSW			_MMIO(0x130044)
8393 #define  FORCEWAKE_ACK				_MMIO(0x130090)
8394 #define  VLV_GTLC_WAKE_CTRL			_MMIO(0x130090)
8395 #define   VLV_GTLC_RENDER_CTX_EXISTS		(1 << 25)
8396 #define   VLV_GTLC_MEDIA_CTX_EXISTS		(1 << 24)
8397 #define   VLV_GTLC_ALLOWWAKEREQ			(1 << 0)
8398 
8399 #define  VLV_GTLC_PW_STATUS			_MMIO(0x130094)
8400 #define   VLV_GTLC_ALLOWWAKEACK			(1 << 0)
8401 #define   VLV_GTLC_ALLOWWAKEERR			(1 << 1)
8402 #define   VLV_GTLC_PW_MEDIA_STATUS_MASK		(1 << 5)
8403 #define   VLV_GTLC_PW_RENDER_STATUS_MASK	(1 << 7)
8404 #define  FORCEWAKE_MT				_MMIO(0xa188) /* multi-threaded */
8405 #define  FORCEWAKE_MEDIA_GEN9			_MMIO(0xa270)
8406 #define  FORCEWAKE_MEDIA_VDBOX_GEN11(n)		_MMIO(0xa540 + (n) * 4)
8407 #define  FORCEWAKE_MEDIA_VEBOX_GEN11(n)		_MMIO(0xa560 + (n) * 4)
8408 #define  FORCEWAKE_RENDER_GEN9			_MMIO(0xa278)
8409 #define  FORCEWAKE_BLITTER_GEN9			_MMIO(0xa188)
8410 #define  FORCEWAKE_ACK_MEDIA_GEN9		_MMIO(0x0D88)
8411 #define  FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n)	_MMIO(0x0D50 + (n) * 4)
8412 #define  FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n)	_MMIO(0x0D70 + (n) * 4)
8413 #define  FORCEWAKE_ACK_RENDER_GEN9		_MMIO(0x0D84)
8414 #define  FORCEWAKE_ACK_BLITTER_GEN9		_MMIO(0x130044)
8415 #define   FORCEWAKE_KERNEL			BIT(0)
8416 #define   FORCEWAKE_USER			BIT(1)
8417 #define   FORCEWAKE_KERNEL_FALLBACK		BIT(15)
8418 #define  FORCEWAKE_MT_ACK			_MMIO(0x130040)
8419 #define  ECOBUS					_MMIO(0xa180)
8420 #define    FORCEWAKE_MT_ENABLE			(1 << 5)
8421 #define  VLV_SPAREG2H				_MMIO(0xA194)
8422 #define  GEN9_PWRGT_DOMAIN_STATUS		_MMIO(0xA2A0)
8423 #define   GEN9_PWRGT_MEDIA_STATUS_MASK		(1 << 0)
8424 #define   GEN9_PWRGT_RENDER_STATUS_MASK		(1 << 1)
8425 
8426 #define  GTFIFODBG				_MMIO(0x120000)
8427 #define    GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV	(0x1f << 20)
8428 #define    GT_FIFO_FREE_ENTRIES_CHV		(0x7f << 13)
8429 #define    GT_FIFO_SBDROPERR			(1 << 6)
8430 #define    GT_FIFO_BLOBDROPERR			(1 << 5)
8431 #define    GT_FIFO_SB_READ_ABORTERR		(1 << 4)
8432 #define    GT_FIFO_DROPERR			(1 << 3)
8433 #define    GT_FIFO_OVFERR			(1 << 2)
8434 #define    GT_FIFO_IAWRERR			(1 << 1)
8435 #define    GT_FIFO_IARDERR			(1 << 0)
8436 
8437 #define  GTFIFOCTL				_MMIO(0x120008)
8438 #define    GT_FIFO_FREE_ENTRIES_MASK		0x7f
8439 #define    GT_FIFO_NUM_RESERVED_ENTRIES		20
8440 #define    GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL	(1 << 12)
8441 #define    GT_FIFO_CTL_RC6_POLICY_STALL		(1 << 11)
8442 
8443 #define  HSW_IDICR				_MMIO(0x9008)
8444 #define    IDIHASHMSK(x)			(((x) & 0x3f) << 16)
8445 #define  HSW_EDRAM_CAP				_MMIO(0x120010)
8446 #define    EDRAM_ENABLED			0x1
8447 #define    EDRAM_NUM_BANKS(cap)			(((cap) >> 1) & 0xf)
8448 #define    EDRAM_WAYS_IDX(cap)			(((cap) >> 5) & 0x7)
8449 #define    EDRAM_SETS_IDX(cap)			(((cap) >> 8) & 0x3)
8450 
8451 #define GEN6_UCGCTL1				_MMIO(0x9400)
8452 # define GEN6_GAMUNIT_CLOCK_GATE_DISABLE		(1 << 22)
8453 # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE		(1 << 16)
8454 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE		(1 << 5)
8455 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE			(1 << 7)
8456 
8457 #define GEN6_UCGCTL2				_MMIO(0x9404)
8458 # define GEN6_VFUNIT_CLOCK_GATE_DISABLE			(1 << 31)
8459 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE		(1 << 30)
8460 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE		(1 << 22)
8461 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE		(1 << 13)
8462 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE		(1 << 12)
8463 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE		(1 << 11)
8464 
8465 #define GEN6_UCGCTL3				_MMIO(0x9408)
8466 # define GEN6_OACSUNIT_CLOCK_GATE_DISABLE		(1 << 20)
8467 
8468 #define GEN7_UCGCTL4				_MMIO(0x940c)
8469 #define  GEN7_L3BANK2X_CLOCK_GATE_DISABLE	(1 << 25)
8470 #define  GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE	(1 << 14)
8471 
8472 #define GEN6_RCGCTL1				_MMIO(0x9410)
8473 #define GEN6_RCGCTL2				_MMIO(0x9414)
8474 #define GEN6_RSTCTL				_MMIO(0x9420)
8475 
8476 #define GEN8_UCGCTL6				_MMIO(0x9430)
8477 #define   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE	(1 << 24)
8478 #define   GEN8_SDEUNIT_CLOCK_GATE_DISABLE	(1 << 14)
8479 #define   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1 << 28)
8480 
8481 #define GEN6_GFXPAUSE				_MMIO(0xA000)
8482 #define GEN6_RPNSWREQ				_MMIO(0xA008)
8483 #define   GEN6_TURBO_DISABLE			(1 << 31)
8484 #define   GEN6_FREQUENCY(x)			((x) << 25)
8485 #define   HSW_FREQUENCY(x)			((x) << 24)
8486 #define   GEN9_FREQUENCY(x)			((x) << 23)
8487 #define   GEN6_OFFSET(x)			((x) << 19)
8488 #define   GEN6_AGGRESSIVE_TURBO			(0 << 15)
8489 #define GEN6_RC_VIDEO_FREQ			_MMIO(0xA00C)
8490 #define GEN6_RC_CONTROL				_MMIO(0xA090)
8491 #define   GEN6_RC_CTL_RC6pp_ENABLE		(1 << 16)
8492 #define   GEN6_RC_CTL_RC6p_ENABLE		(1 << 17)
8493 #define   GEN6_RC_CTL_RC6_ENABLE		(1 << 18)
8494 #define   GEN6_RC_CTL_RC1e_ENABLE		(1 << 20)
8495 #define   GEN6_RC_CTL_RC7_ENABLE		(1 << 22)
8496 #define   VLV_RC_CTL_CTX_RST_PARALLEL		(1 << 24)
8497 #define   GEN7_RC_CTL_TO_MODE			(1 << 28)
8498 #define   GEN6_RC_CTL_EI_MODE(x)		((x) << 27)
8499 #define   GEN6_RC_CTL_HW_ENABLE			(1 << 31)
8500 #define GEN6_RP_DOWN_TIMEOUT			_MMIO(0xA010)
8501 #define GEN6_RP_INTERRUPT_LIMITS		_MMIO(0xA014)
8502 #define GEN6_RPSTAT1				_MMIO(0xA01C)
8503 #define   GEN6_CAGF_SHIFT			8
8504 #define   HSW_CAGF_SHIFT			7
8505 #define   GEN9_CAGF_SHIFT			23
8506 #define   GEN6_CAGF_MASK			(0x7f << GEN6_CAGF_SHIFT)
8507 #define   HSW_CAGF_MASK				(0x7f << HSW_CAGF_SHIFT)
8508 #define   GEN9_CAGF_MASK			(0x1ff << GEN9_CAGF_SHIFT)
8509 #define GEN6_RP_CONTROL				_MMIO(0xA024)
8510 #define   GEN6_RP_MEDIA_TURBO			(1 << 11)
8511 #define   GEN6_RP_MEDIA_MODE_MASK		(3 << 9)
8512 #define   GEN6_RP_MEDIA_HW_TURBO_MODE		(3 << 9)
8513 #define   GEN6_RP_MEDIA_HW_NORMAL_MODE		(2 << 9)
8514 #define   GEN6_RP_MEDIA_HW_MODE			(1 << 9)
8515 #define   GEN6_RP_MEDIA_SW_MODE			(0 << 9)
8516 #define   GEN6_RP_MEDIA_IS_GFX			(1 << 8)
8517 #define   GEN6_RP_ENABLE			(1 << 7)
8518 #define   GEN6_RP_UP_IDLE_MIN			(0x1 << 3)
8519 #define   GEN6_RP_UP_BUSY_AVG			(0x2 << 3)
8520 #define   GEN6_RP_UP_BUSY_CONT			(0x4 << 3)
8521 #define   GEN6_RP_DOWN_IDLE_AVG			(0x2 << 0)
8522 #define   GEN6_RP_DOWN_IDLE_CONT		(0x1 << 0)
8523 #define GEN6_RP_UP_THRESHOLD			_MMIO(0xA02C)
8524 #define GEN6_RP_DOWN_THRESHOLD			_MMIO(0xA030)
8525 #define GEN6_RP_CUR_UP_EI			_MMIO(0xA050)
8526 #define   GEN6_RP_EI_MASK			0xffffff
8527 #define   GEN6_CURICONT_MASK			GEN6_RP_EI_MASK
8528 #define GEN6_RP_CUR_UP				_MMIO(0xA054)
8529 #define   GEN6_CURBSYTAVG_MASK			GEN6_RP_EI_MASK
8530 #define GEN6_RP_PREV_UP				_MMIO(0xA058)
8531 #define GEN6_RP_CUR_DOWN_EI			_MMIO(0xA05C)
8532 #define   GEN6_CURIAVG_MASK			GEN6_RP_EI_MASK
8533 #define GEN6_RP_CUR_DOWN			_MMIO(0xA060)
8534 #define GEN6_RP_PREV_DOWN			_MMIO(0xA064)
8535 #define GEN6_RP_UP_EI				_MMIO(0xA068)
8536 #define GEN6_RP_DOWN_EI				_MMIO(0xA06C)
8537 #define GEN6_RP_IDLE_HYSTERSIS			_MMIO(0xA070)
8538 #define GEN6_RPDEUHWTC				_MMIO(0xA080)
8539 #define GEN6_RPDEUC				_MMIO(0xA084)
8540 #define GEN6_RPDEUCSW				_MMIO(0xA088)
8541 #define GEN6_RC_STATE				_MMIO(0xA094)
8542 #define   RC_SW_TARGET_STATE_SHIFT		16
8543 #define   RC_SW_TARGET_STATE_MASK		(7 << RC_SW_TARGET_STATE_SHIFT)
8544 #define GEN6_RC1_WAKE_RATE_LIMIT		_MMIO(0xA098)
8545 #define GEN6_RC6_WAKE_RATE_LIMIT		_MMIO(0xA09C)
8546 #define GEN6_RC6pp_WAKE_RATE_LIMIT		_MMIO(0xA0A0)
8547 #define GEN10_MEDIA_WAKE_RATE_LIMIT		_MMIO(0xA0A0)
8548 #define GEN6_RC_EVALUATION_INTERVAL		_MMIO(0xA0A8)
8549 #define GEN6_RC_IDLE_HYSTERSIS			_MMIO(0xA0AC)
8550 #define GEN6_RC_SLEEP				_MMIO(0xA0B0)
8551 #define GEN6_RCUBMABDTMR			_MMIO(0xA0B0)
8552 #define GEN6_RC1e_THRESHOLD			_MMIO(0xA0B4)
8553 #define GEN6_RC6_THRESHOLD			_MMIO(0xA0B8)
8554 #define GEN6_RC6p_THRESHOLD			_MMIO(0xA0BC)
8555 #define VLV_RCEDATA				_MMIO(0xA0BC)
8556 #define GEN6_RC6pp_THRESHOLD			_MMIO(0xA0C0)
8557 #define GEN6_PMINTRMSK				_MMIO(0xA168)
8558 #define   GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC	(1 << 31)
8559 #define   ARAT_EXPIRED_INTRMSK			(1 << 9)
8560 #define GEN8_MISC_CTRL0				_MMIO(0xA180)
8561 #define VLV_PWRDWNUPCTL				_MMIO(0xA294)
8562 #define GEN9_MEDIA_PG_IDLE_HYSTERESIS		_MMIO(0xA0C4)
8563 #define GEN9_RENDER_PG_IDLE_HYSTERESIS		_MMIO(0xA0C8)
8564 #define GEN9_PG_ENABLE				_MMIO(0xA210)
8565 #define GEN9_RENDER_PG_ENABLE			(1 << 0)
8566 #define GEN9_MEDIA_PG_ENABLE			(1 << 1)
8567 #define GEN8_PUSHBUS_CONTROL			_MMIO(0xA248)
8568 #define GEN8_PUSHBUS_ENABLE			_MMIO(0xA250)
8569 #define GEN8_PUSHBUS_SHIFT			_MMIO(0xA25C)
8570 
8571 #define VLV_CHICKEN_3				_MMIO(VLV_DISPLAY_BASE + 0x7040C)
8572 #define  PIXEL_OVERLAP_CNT_MASK			(3 << 30)
8573 #define  PIXEL_OVERLAP_CNT_SHIFT		30
8574 
8575 #define GEN6_PMISR				_MMIO(0x44020)
8576 #define GEN6_PMIMR				_MMIO(0x44024) /* rps_lock */
8577 #define GEN6_PMIIR				_MMIO(0x44028)
8578 #define GEN6_PMIER				_MMIO(0x4402C)
8579 #define  GEN6_PM_MBOX_EVENT			(1 << 25)
8580 #define  GEN6_PM_THERMAL_EVENT			(1 << 24)
8581 #define  GEN6_PM_RP_DOWN_TIMEOUT		(1 << 6)
8582 #define  GEN6_PM_RP_UP_THRESHOLD		(1 << 5)
8583 #define  GEN6_PM_RP_DOWN_THRESHOLD		(1 << 4)
8584 #define  GEN6_PM_RP_UP_EI_EXPIRED		(1 << 2)
8585 #define  GEN6_PM_RP_DOWN_EI_EXPIRED		(1 << 1)
8586 #define  GEN6_PM_RPS_EVENTS			(GEN6_PM_RP_UP_EI_EXPIRED   | \
8587 						 GEN6_PM_RP_UP_THRESHOLD    | \
8588 						 GEN6_PM_RP_DOWN_EI_EXPIRED | \
8589 						 GEN6_PM_RP_DOWN_THRESHOLD  | \
8590 						 GEN6_PM_RP_DOWN_TIMEOUT)
8591 
8592 #define GEN7_GT_SCRATCH(i)			_MMIO(0x4F100 + (i) * 4)
8593 #define GEN7_GT_SCRATCH_REG_NUM			8
8594 
8595 #define VLV_GTLC_SURVIVABILITY_REG              _MMIO(0x130098)
8596 #define VLV_GFX_CLK_STATUS_BIT			(1 << 3)
8597 #define VLV_GFX_CLK_FORCE_ON_BIT		(1 << 2)
8598 
8599 #define GEN6_GT_GFX_RC6_LOCKED			_MMIO(0x138104)
8600 #define VLV_COUNTER_CONTROL			_MMIO(0x138104)
8601 #define   VLV_COUNT_RANGE_HIGH			(1 << 15)
8602 #define   VLV_MEDIA_RC0_COUNT_EN		(1 << 5)
8603 #define   VLV_RENDER_RC0_COUNT_EN		(1 << 4)
8604 #define   VLV_MEDIA_RC6_COUNT_EN		(1 << 1)
8605 #define   VLV_RENDER_RC6_COUNT_EN		(1 << 0)
8606 #define GEN6_GT_GFX_RC6				_MMIO(0x138108)
8607 #define VLV_GT_RENDER_RC6			_MMIO(0x138108)
8608 #define VLV_GT_MEDIA_RC6			_MMIO(0x13810C)
8609 
8610 #define GEN6_GT_GFX_RC6p			_MMIO(0x13810C)
8611 #define GEN6_GT_GFX_RC6pp			_MMIO(0x138110)
8612 #define VLV_RENDER_C0_COUNT			_MMIO(0x138118)
8613 #define VLV_MEDIA_C0_COUNT			_MMIO(0x13811C)
8614 
8615 #define GEN6_PCODE_MAILBOX			_MMIO(0x138124)
8616 #define   GEN6_PCODE_READY			(1 << 31)
8617 #define   GEN6_PCODE_ERROR_MASK			0xFF
8618 #define     GEN6_PCODE_SUCCESS			0x0
8619 #define     GEN6_PCODE_ILLEGAL_CMD		0x1
8620 #define     GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
8621 #define     GEN6_PCODE_TIMEOUT			0x3
8622 #define     GEN6_PCODE_UNIMPLEMENTED_CMD	0xFF
8623 #define     GEN7_PCODE_TIMEOUT			0x2
8624 #define     GEN7_PCODE_ILLEGAL_DATA		0x3
8625 #define     GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
8626 #define   GEN6_PCODE_WRITE_RC6VIDS		0x4
8627 #define   GEN6_PCODE_READ_RC6VIDS		0x5
8628 #define     GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)
8629 #define     GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)
8630 #define   BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ	0x18
8631 #define   GEN9_PCODE_READ_MEM_LATENCY		0x6
8632 #define     GEN9_MEM_LATENCY_LEVEL_MASK		0xFF
8633 #define     GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT	8
8634 #define     GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT	16
8635 #define     GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT	24
8636 #define   SKL_PCODE_LOAD_HDCP_KEYS		0x5
8637 #define   SKL_PCODE_CDCLK_CONTROL		0x7
8638 #define     SKL_CDCLK_PREPARE_FOR_CHANGE	0x3
8639 #define     SKL_CDCLK_READY_FOR_CHANGE		0x1
8640 #define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE	0x8
8641 #define   GEN6_PCODE_READ_MIN_FREQ_TABLE	0x9
8642 #define   GEN6_READ_OC_PARAMS			0xc
8643 #define   GEN6_PCODE_READ_D_COMP		0x10
8644 #define   GEN6_PCODE_WRITE_D_COMP		0x11
8645 #define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
8646 #define   DISPLAY_IPS_CONTROL			0x19
8647             /* See also IPS_CTL */
8648 #define     IPS_PCODE_CONTROL			(1 << 30)
8649 #define   HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A
8650 #define   GEN9_PCODE_SAGV_CONTROL		0x21
8651 #define     GEN9_SAGV_DISABLE			0x0
8652 #define     GEN9_SAGV_IS_DISABLED		0x1
8653 #define     GEN9_SAGV_ENABLE			0x3
8654 #define GEN6_PCODE_DATA				_MMIO(0x138128)
8655 #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
8656 #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16
8657 #define GEN6_PCODE_DATA1			_MMIO(0x13812C)
8658 
8659 #define GEN6_GT_CORE_STATUS		_MMIO(0x138060)
8660 #define   GEN6_CORE_CPD_STATE_MASK	(7 << 4)
8661 #define   GEN6_RCn_MASK			7
8662 #define   GEN6_RC0			0
8663 #define   GEN6_RC3			2
8664 #define   GEN6_RC6			3
8665 #define   GEN6_RC7			4
8666 
8667 #define GEN8_GT_SLICE_INFO		_MMIO(0x138064)
8668 #define   GEN8_LSLICESTAT_MASK		0x7
8669 
8670 #define CHV_POWER_SS0_SIG1		_MMIO(0xa720)
8671 #define CHV_POWER_SS1_SIG1		_MMIO(0xa728)
8672 #define   CHV_SS_PG_ENABLE		(1 << 1)
8673 #define   CHV_EU08_PG_ENABLE		(1 << 9)
8674 #define   CHV_EU19_PG_ENABLE		(1 << 17)
8675 #define   CHV_EU210_PG_ENABLE		(1 << 25)
8676 
8677 #define CHV_POWER_SS0_SIG2		_MMIO(0xa724)
8678 #define CHV_POWER_SS1_SIG2		_MMIO(0xa72c)
8679 #define   CHV_EU311_PG_ENABLE		(1 << 1)
8680 
8681 #define GEN9_SLICE_PGCTL_ACK(slice)	_MMIO(0x804c + (slice) * 0x4)
8682 #define GEN10_SLICE_PGCTL_ACK(slice)	_MMIO(0x804c + ((slice) / 3) * 0x34 + \
8683 					      ((slice) % 3) * 0x4)
8684 #define   GEN9_PGCTL_SLICE_ACK		(1 << 0)
8685 #define   GEN9_PGCTL_SS_ACK(subslice)	(1 << (2 + (subslice) * 2))
8686 #define   GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
8687 
8688 #define GEN9_SS01_EU_PGCTL_ACK(slice)	_MMIO(0x805c + (slice) * 0x8)
8689 #define GEN10_SS01_EU_PGCTL_ACK(slice)	_MMIO(0x805c + ((slice) / 3) * 0x30 + \
8690 					      ((slice) % 3) * 0x8)
8691 #define GEN9_SS23_EU_PGCTL_ACK(slice)	_MMIO(0x8060 + (slice) * 0x8)
8692 #define GEN10_SS23_EU_PGCTL_ACK(slice)	_MMIO(0x8060 + ((slice) / 3) * 0x30 + \
8693 					      ((slice) % 3) * 0x8)
8694 #define   GEN9_PGCTL_SSA_EU08_ACK	(1 << 0)
8695 #define   GEN9_PGCTL_SSA_EU19_ACK	(1 << 2)
8696 #define   GEN9_PGCTL_SSA_EU210_ACK	(1 << 4)
8697 #define   GEN9_PGCTL_SSA_EU311_ACK	(1 << 6)
8698 #define   GEN9_PGCTL_SSB_EU08_ACK	(1 << 8)
8699 #define   GEN9_PGCTL_SSB_EU19_ACK	(1 << 10)
8700 #define   GEN9_PGCTL_SSB_EU210_ACK	(1 << 12)
8701 #define   GEN9_PGCTL_SSB_EU311_ACK	(1 << 14)
8702 
8703 #define GEN7_MISCCPCTL				_MMIO(0x9424)
8704 #define   GEN7_DOP_CLOCK_GATE_ENABLE		(1 << 0)
8705 #define   GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE	(1 << 2)
8706 #define   GEN8_DOP_CLOCK_GATE_GUC_ENABLE	(1 << 4)
8707 #define   GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE     (1 << 6)
8708 
8709 #define GEN8_GARBCNTL				_MMIO(0xB004)
8710 #define   GEN9_GAPS_TSV_CREDIT_DISABLE		(1 << 7)
8711 #define   GEN11_ARBITRATION_PRIO_ORDER_MASK	(0x3f << 22)
8712 #define   GEN11_HASH_CTRL_EXCL_MASK		(0x7f << 0)
8713 #define   GEN11_HASH_CTRL_EXCL_BIT0		(1 << 0)
8714 
8715 #define GEN11_GLBLINVL				_MMIO(0xB404)
8716 #define   GEN11_BANK_HASH_ADDR_EXCL_MASK	(0x7f << 5)
8717 #define   GEN11_BANK_HASH_ADDR_EXCL_BIT0	(1 << 5)
8718 
8719 #define GEN10_DFR_RATIO_EN_AND_CHICKEN	_MMIO(0x9550)
8720 #define   DFR_DISABLE			(1 << 9)
8721 
8722 #define GEN11_GACB_PERF_CTRL			_MMIO(0x4B80)
8723 #define   GEN11_HASH_CTRL_MASK			(0x3 << 12 | 0xf << 0)
8724 #define   GEN11_HASH_CTRL_BIT0			(1 << 0)
8725 #define   GEN11_HASH_CTRL_BIT4			(1 << 12)
8726 
8727 #define GEN11_LSN_UNSLCVC				_MMIO(0xB43C)
8728 #define   GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC	(1 << 9)
8729 #define   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC	(1 << 7)
8730 
8731 #define GEN10_SAMPLER_MODE		_MMIO(0xE18C)
8732 
8733 /* IVYBRIDGE DPF */
8734 #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
8735 #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff << 14)
8736 #define   GEN7_PARITY_ERROR_VALID	(1 << 13)
8737 #define   GEN7_L3CDERRST1_BANK_MASK	(3 << 11)
8738 #define   GEN7_L3CDERRST1_SUBBANK_MASK	(7 << 8)
8739 #define GEN7_PARITY_ERROR_ROW(reg) \
8740 		(((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14)
8741 #define GEN7_PARITY_ERROR_BANK(reg) \
8742 		(((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11)
8743 #define GEN7_PARITY_ERROR_SUBBANK(reg) \
8744 		(((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
8745 #define   GEN7_L3CDERRST1_ENABLE	(1 << 7)
8746 
8747 #define GEN7_L3LOG(slice, i)		_MMIO(0xB070 + (slice) * 0x200 + (i) * 4)
8748 #define GEN7_L3LOG_SIZE			0x80
8749 
8750 #define GEN7_HALF_SLICE_CHICKEN1	_MMIO(0xe100) /* IVB GT1 + VLV */
8751 #define GEN7_HALF_SLICE_CHICKEN1_GT2	_MMIO(0xf100)
8752 #define   GEN7_MAX_PS_THREAD_DEP		(8 << 12)
8753 #define   GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE	(1 << 10)
8754 #define   GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE	(1 << 4)
8755 #define   GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE	(1 << 3)
8756 
8757 #define GEN9_HALF_SLICE_CHICKEN5	_MMIO(0xe188)
8758 #define   GEN9_DG_MIRROR_FIX_ENABLE	(1 << 5)
8759 #define   GEN9_CCS_TLB_PREFETCH_ENABLE	(1 << 3)
8760 
8761 #define GEN8_ROW_CHICKEN		_MMIO(0xe4f0)
8762 #define   FLOW_CONTROL_ENABLE		(1 << 15)
8763 #define   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE	(1 << 8)
8764 #define   STALL_DOP_GATING_DISABLE		(1 << 5)
8765 #define   THROTTLE_12_5				(7 << 2)
8766 #define   DISABLE_EARLY_EOT			(1 << 1)
8767 
8768 #define GEN7_ROW_CHICKEN2		_MMIO(0xe4f4)
8769 #define GEN7_ROW_CHICKEN2_GT2		_MMIO(0xf4f4)
8770 #define   DOP_CLOCK_GATING_DISABLE	(1 << 0)
8771 #define   PUSH_CONSTANT_DEREF_DISABLE	(1 << 8)
8772 #define   GEN11_TDL_CLOCK_GATING_FIX_DISABLE	(1 << 1)
8773 
8774 #define HSW_ROW_CHICKEN3		_MMIO(0xe49c)
8775 #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)
8776 
8777 #define HALF_SLICE_CHICKEN2		_MMIO(0xe180)
8778 #define   GEN8_ST_PO_DISABLE		(1 << 13)
8779 
8780 #define HALF_SLICE_CHICKEN3		_MMIO(0xe184)
8781 #define   HSW_SAMPLE_C_PERFORMANCE	(1 << 9)
8782 #define   GEN8_CENTROID_PIXEL_OPT_DIS	(1 << 8)
8783 #define   GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC	(1 << 5)
8784 #define   CNL_FAST_ANISO_L1_BANKING_FIX	(1 << 4)
8785 #define   GEN8_SAMPLER_POWER_BYPASS_DIS	(1 << 1)
8786 
8787 #define GEN9_HALF_SLICE_CHICKEN7	_MMIO(0xe194)
8788 #define   GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR	(1 << 8)
8789 #define   GEN9_ENABLE_YV12_BUGFIX	(1 << 4)
8790 #define   GEN9_ENABLE_GPGPU_PREEMPTION	(1 << 2)
8791 
8792 /* Audio */
8793 #define G4X_AUD_VID_DID			_MMIO(dev_priv->info.display_mmio_offset + 0x62020)
8794 #define   INTEL_AUDIO_DEVCL		0x808629FB
8795 #define   INTEL_AUDIO_DEVBLC		0x80862801
8796 #define   INTEL_AUDIO_DEVCTG		0x80862802
8797 
8798 #define G4X_AUD_CNTL_ST			_MMIO(0x620B4)
8799 #define   G4X_ELDV_DEVCL_DEVBLC		(1 << 13)
8800 #define   G4X_ELDV_DEVCTG		(1 << 14)
8801 #define   G4X_ELD_ADDR_MASK		(0xf << 5)
8802 #define   G4X_ELD_ACK			(1 << 4)
8803 #define G4X_HDMIW_HDMIEDID		_MMIO(0x6210C)
8804 
8805 #define _IBX_HDMIW_HDMIEDID_A		0xE2050
8806 #define _IBX_HDMIW_HDMIEDID_B		0xE2150
8807 #define IBX_HDMIW_HDMIEDID(pipe)	_MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \
8808 						  _IBX_HDMIW_HDMIEDID_B)
8809 #define _IBX_AUD_CNTL_ST_A		0xE20B4
8810 #define _IBX_AUD_CNTL_ST_B		0xE21B4
8811 #define IBX_AUD_CNTL_ST(pipe)		_MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \
8812 						  _IBX_AUD_CNTL_ST_B)
8813 #define   IBX_ELD_BUFFER_SIZE_MASK	(0x1f << 10)
8814 #define   IBX_ELD_ADDRESS_MASK		(0x1f << 5)
8815 #define   IBX_ELD_ACK			(1 << 4)
8816 #define IBX_AUD_CNTL_ST2		_MMIO(0xE20C0)
8817 #define   IBX_CP_READY(port)		((1 << 1) << (((port) - 1) * 4))
8818 #define   IBX_ELD_VALID(port)		((1 << 0) << (((port) - 1) * 4))
8819 
8820 #define _CPT_HDMIW_HDMIEDID_A		0xE5050
8821 #define _CPT_HDMIW_HDMIEDID_B		0xE5150
8822 #define CPT_HDMIW_HDMIEDID(pipe)	_MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B)
8823 #define _CPT_AUD_CNTL_ST_A		0xE50B4
8824 #define _CPT_AUD_CNTL_ST_B		0xE51B4
8825 #define CPT_AUD_CNTL_ST(pipe)		_MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B)
8826 #define CPT_AUD_CNTRL_ST2		_MMIO(0xE50C0)
8827 
8828 #define _VLV_HDMIW_HDMIEDID_A		(VLV_DISPLAY_BASE + 0x62050)
8829 #define _VLV_HDMIW_HDMIEDID_B		(VLV_DISPLAY_BASE + 0x62150)
8830 #define VLV_HDMIW_HDMIEDID(pipe)	_MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B)
8831 #define _VLV_AUD_CNTL_ST_A		(VLV_DISPLAY_BASE + 0x620B4)
8832 #define _VLV_AUD_CNTL_ST_B		(VLV_DISPLAY_BASE + 0x621B4)
8833 #define VLV_AUD_CNTL_ST(pipe)		_MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B)
8834 #define VLV_AUD_CNTL_ST2		_MMIO(VLV_DISPLAY_BASE + 0x620C0)
8835 
8836 /* These are the 4 32-bit write offset registers for each stream
8837  * output buffer.  It determines the offset from the
8838  * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
8839  */
8840 #define GEN7_SO_WRITE_OFFSET(n)		_MMIO(0x5280 + (n) * 4)
8841 
8842 #define _IBX_AUD_CONFIG_A		0xe2000
8843 #define _IBX_AUD_CONFIG_B		0xe2100
8844 #define IBX_AUD_CFG(pipe)		_MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B)
8845 #define _CPT_AUD_CONFIG_A		0xe5000
8846 #define _CPT_AUD_CONFIG_B		0xe5100
8847 #define CPT_AUD_CFG(pipe)		_MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B)
8848 #define _VLV_AUD_CONFIG_A		(VLV_DISPLAY_BASE + 0x62000)
8849 #define _VLV_AUD_CONFIG_B		(VLV_DISPLAY_BASE + 0x62100)
8850 #define VLV_AUD_CFG(pipe)		_MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B)
8851 
8852 #define   AUD_CONFIG_N_VALUE_INDEX		(1 << 29)
8853 #define   AUD_CONFIG_N_PROG_ENABLE		(1 << 28)
8854 #define   AUD_CONFIG_UPPER_N_SHIFT		20
8855 #define   AUD_CONFIG_UPPER_N_MASK		(0xff << 20)
8856 #define   AUD_CONFIG_LOWER_N_SHIFT		4
8857 #define   AUD_CONFIG_LOWER_N_MASK		(0xfff << 4)
8858 #define   AUD_CONFIG_N_MASK			(AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK)
8859 #define   AUD_CONFIG_N(n) \
8860 	(((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) |	\
8861 	 (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT))
8862 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT	16
8863 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK	(0xf << 16)
8864 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_25175	(0 << 16)
8865 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_25200	(1 << 16)
8866 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_27000	(2 << 16)
8867 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_27027	(3 << 16)
8868 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_54000	(4 << 16)
8869 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_54054	(5 << 16)
8870 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_74176	(6 << 16)
8871 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_74250	(7 << 16)
8872 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_148352	(8 << 16)
8873 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_148500	(9 << 16)
8874 #define   AUD_CONFIG_DISABLE_NCTS		(1 << 3)
8875 
8876 /* HSW Audio */
8877 #define _HSW_AUD_CONFIG_A		0x65000
8878 #define _HSW_AUD_CONFIG_B		0x65100
8879 #define HSW_AUD_CFG(pipe)		_MMIO_PIPE(pipe, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
8880 
8881 #define _HSW_AUD_MISC_CTRL_A		0x65010
8882 #define _HSW_AUD_MISC_CTRL_B		0x65110
8883 #define HSW_AUD_MISC_CTRL(pipe)		_MMIO_PIPE(pipe, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
8884 
8885 #define _HSW_AUD_M_CTS_ENABLE_A		0x65028
8886 #define _HSW_AUD_M_CTS_ENABLE_B		0x65128
8887 #define HSW_AUD_M_CTS_ENABLE(pipe)	_MMIO_PIPE(pipe, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
8888 #define   AUD_M_CTS_M_VALUE_INDEX	(1 << 21)
8889 #define   AUD_M_CTS_M_PROG_ENABLE	(1 << 20)
8890 #define   AUD_CONFIG_M_MASK		0xfffff
8891 
8892 #define _HSW_AUD_DIP_ELD_CTRL_ST_A	0x650b4
8893 #define _HSW_AUD_DIP_ELD_CTRL_ST_B	0x651b4
8894 #define HSW_AUD_DIP_ELD_CTRL(pipe)	_MMIO_PIPE(pipe, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
8895 
8896 /* Audio Digital Converter */
8897 #define _HSW_AUD_DIG_CNVT_1		0x65080
8898 #define _HSW_AUD_DIG_CNVT_2		0x65180
8899 #define AUD_DIG_CNVT(pipe)		_MMIO_PIPE(pipe, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2)
8900 #define DIP_PORT_SEL_MASK		0x3
8901 
8902 #define _HSW_AUD_EDID_DATA_A		0x65050
8903 #define _HSW_AUD_EDID_DATA_B		0x65150
8904 #define HSW_AUD_EDID_DATA(pipe)		_MMIO_PIPE(pipe, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
8905 
8906 #define HSW_AUD_PIPE_CONV_CFG		_MMIO(0x6507c)
8907 #define HSW_AUD_PIN_ELD_CP_VLD		_MMIO(0x650c0)
8908 #define   AUDIO_INACTIVE(trans)		((1 << 3) << ((trans) * 4))
8909 #define   AUDIO_OUTPUT_ENABLE(trans)	((1 << 2) << ((trans) * 4))
8910 #define   AUDIO_CP_READY(trans)		((1 << 1) << ((trans) * 4))
8911 #define   AUDIO_ELD_VALID(trans)	((1 << 0) << ((trans) * 4))
8912 
8913 #define HSW_AUD_CHICKENBIT			_MMIO(0x65f10)
8914 #define   SKL_AUD_CODEC_WAKE_SIGNAL		(1 << 15)
8915 
8916 /*
8917  * HSW - ICL power wells
8918  *
8919  * Platforms have up to 3 power well control register sets, each set
8920  * controlling up to 16 power wells via a request/status HW flag tuple:
8921  * - main (HSW_PWR_WELL_CTL[1-4])
8922  * - AUX  (ICL_PWR_WELL_CTL_AUX[1-4])
8923  * - DDI  (ICL_PWR_WELL_CTL_DDI[1-4])
8924  * Each control register set consists of up to 4 registers used by different
8925  * sources that can request a power well to be enabled:
8926  * - BIOS   (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1)
8927  * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2)
8928  * - KVMR   (HSW_PWR_WELL_CTL3)   (only in the main register set)
8929  * - DEBUG  (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4)
8930  */
8931 #define HSW_PWR_WELL_CTL1			_MMIO(0x45400)
8932 #define HSW_PWR_WELL_CTL2			_MMIO(0x45404)
8933 #define HSW_PWR_WELL_CTL3			_MMIO(0x45408)
8934 #define HSW_PWR_WELL_CTL4			_MMIO(0x4540C)
8935 #define   HSW_PWR_WELL_CTL_REQ(pw_idx)		(0x2 << ((pw_idx) * 2))
8936 #define   HSW_PWR_WELL_CTL_STATE(pw_idx)	(0x1 << ((pw_idx) * 2))
8937 
8938 /* HSW/BDW power well */
8939 #define   HSW_PW_CTL_IDX_GLOBAL			15
8940 
8941 /* SKL/BXT/GLK/CNL power wells */
8942 #define   SKL_PW_CTL_IDX_PW_2			15
8943 #define   SKL_PW_CTL_IDX_PW_1			14
8944 #define   CNL_PW_CTL_IDX_AUX_F			12
8945 #define   CNL_PW_CTL_IDX_AUX_D			11
8946 #define   GLK_PW_CTL_IDX_AUX_C			10
8947 #define   GLK_PW_CTL_IDX_AUX_B			9
8948 #define   GLK_PW_CTL_IDX_AUX_A			8
8949 #define   CNL_PW_CTL_IDX_DDI_F			6
8950 #define   SKL_PW_CTL_IDX_DDI_D			4
8951 #define   SKL_PW_CTL_IDX_DDI_C			3
8952 #define   SKL_PW_CTL_IDX_DDI_B			2
8953 #define   SKL_PW_CTL_IDX_DDI_A_E		1
8954 #define   GLK_PW_CTL_IDX_DDI_A			1
8955 #define   SKL_PW_CTL_IDX_MISC_IO		0
8956 
8957 /* ICL - power wells */
8958 #define   ICL_PW_CTL_IDX_PW_4			3
8959 #define   ICL_PW_CTL_IDX_PW_3			2
8960 #define   ICL_PW_CTL_IDX_PW_2			1
8961 #define   ICL_PW_CTL_IDX_PW_1			0
8962 
8963 #define ICL_PWR_WELL_CTL_AUX1			_MMIO(0x45440)
8964 #define ICL_PWR_WELL_CTL_AUX2			_MMIO(0x45444)
8965 #define ICL_PWR_WELL_CTL_AUX4			_MMIO(0x4544C)
8966 #define   ICL_PW_CTL_IDX_AUX_TBT4		11
8967 #define   ICL_PW_CTL_IDX_AUX_TBT3		10
8968 #define   ICL_PW_CTL_IDX_AUX_TBT2		9
8969 #define   ICL_PW_CTL_IDX_AUX_TBT1		8
8970 #define   ICL_PW_CTL_IDX_AUX_F			5
8971 #define   ICL_PW_CTL_IDX_AUX_E			4
8972 #define   ICL_PW_CTL_IDX_AUX_D			3
8973 #define   ICL_PW_CTL_IDX_AUX_C			2
8974 #define   ICL_PW_CTL_IDX_AUX_B			1
8975 #define   ICL_PW_CTL_IDX_AUX_A			0
8976 
8977 #define ICL_PWR_WELL_CTL_DDI1			_MMIO(0x45450)
8978 #define ICL_PWR_WELL_CTL_DDI2			_MMIO(0x45454)
8979 #define ICL_PWR_WELL_CTL_DDI4			_MMIO(0x4545C)
8980 #define   ICL_PW_CTL_IDX_DDI_F			5
8981 #define   ICL_PW_CTL_IDX_DDI_E			4
8982 #define   ICL_PW_CTL_IDX_DDI_D			3
8983 #define   ICL_PW_CTL_IDX_DDI_C			2
8984 #define   ICL_PW_CTL_IDX_DDI_B			1
8985 #define   ICL_PW_CTL_IDX_DDI_A			0
8986 
8987 /* HSW - power well misc debug registers */
8988 #define HSW_PWR_WELL_CTL5			_MMIO(0x45410)
8989 #define   HSW_PWR_WELL_ENABLE_SINGLE_STEP	(1 << 31)
8990 #define   HSW_PWR_WELL_PWR_GATE_OVERRIDE	(1 << 20)
8991 #define   HSW_PWR_WELL_FORCE_ON			(1 << 19)
8992 #define HSW_PWR_WELL_CTL6			_MMIO(0x45414)
8993 
8994 /* SKL Fuse Status */
8995 enum skl_power_gate {
8996 	SKL_PG0,
8997 	SKL_PG1,
8998 	SKL_PG2,
8999 	ICL_PG3,
9000 	ICL_PG4,
9001 };
9002 
9003 #define SKL_FUSE_STATUS				_MMIO(0x42000)
9004 #define  SKL_FUSE_DOWNLOAD_STATUS		(1 << 31)
9005 /*
9006  * PG0 is HW controlled, so doesn't have a corresponding power well control knob
9007  * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2
9008  */
9009 #define  SKL_PW_CTL_IDX_TO_PG(pw_idx)		\
9010 	((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1)
9011 /*
9012  * PG0 is HW controlled, so doesn't have a corresponding power well control knob
9013  * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4
9014  */
9015 #define  ICL_PW_CTL_IDX_TO_PG(pw_idx)		\
9016 	((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
9017 #define  SKL_FUSE_PG_DIST_STATUS(pg)		(1 << (27 - (pg)))
9018 
9019 #define _CNL_AUX_REG_IDX(pw_idx)	((pw_idx) - GLK_PW_CTL_IDX_AUX_B)
9020 #define _CNL_AUX_ANAOVRD1_B		0x162250
9021 #define _CNL_AUX_ANAOVRD1_C		0x162210
9022 #define _CNL_AUX_ANAOVRD1_D		0x1622D0
9023 #define _CNL_AUX_ANAOVRD1_F		0x162A90
9024 #define CNL_AUX_ANAOVRD1(pw_idx)	_MMIO(_PICK(_CNL_AUX_REG_IDX(pw_idx), \
9025 						    _CNL_AUX_ANAOVRD1_B, \
9026 						    _CNL_AUX_ANAOVRD1_C, \
9027 						    _CNL_AUX_ANAOVRD1_D, \
9028 						    _CNL_AUX_ANAOVRD1_F))
9029 #define   CNL_AUX_ANAOVRD1_ENABLE	(1 << 16)
9030 #define   CNL_AUX_ANAOVRD1_LDO_BYPASS	(1 << 23)
9031 
9032 #define _ICL_AUX_REG_IDX(pw_idx)	((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
9033 #define _ICL_AUX_ANAOVRD1_A		0x162398
9034 #define _ICL_AUX_ANAOVRD1_B		0x6C398
9035 #define ICL_AUX_ANAOVRD1(pw_idx)	_MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \
9036 						    _ICL_AUX_ANAOVRD1_A, \
9037 						    _ICL_AUX_ANAOVRD1_B))
9038 #define   ICL_AUX_ANAOVRD1_LDO_BYPASS	(1 << 7)
9039 #define   ICL_AUX_ANAOVRD1_ENABLE	(1 << 0)
9040 
9041 /* HDCP Key Registers */
9042 #define HDCP_KEY_CONF			_MMIO(0x66c00)
9043 #define  HDCP_AKSV_SEND_TRIGGER		BIT(31)
9044 #define  HDCP_CLEAR_KEYS_TRIGGER	BIT(30)
9045 #define  HDCP_KEY_LOAD_TRIGGER		BIT(8)
9046 #define HDCP_KEY_STATUS			_MMIO(0x66c04)
9047 #define  HDCP_FUSE_IN_PROGRESS		BIT(7)
9048 #define  HDCP_FUSE_ERROR		BIT(6)
9049 #define  HDCP_FUSE_DONE			BIT(5)
9050 #define  HDCP_KEY_LOAD_STATUS		BIT(1)
9051 #define  HDCP_KEY_LOAD_DONE		BIT(0)
9052 #define HDCP_AKSV_LO			_MMIO(0x66c10)
9053 #define HDCP_AKSV_HI			_MMIO(0x66c14)
9054 
9055 /* HDCP Repeater Registers */
9056 #define HDCP_REP_CTL			_MMIO(0x66d00)
9057 #define  HDCP_DDIB_REP_PRESENT		BIT(30)
9058 #define  HDCP_DDIA_REP_PRESENT		BIT(29)
9059 #define  HDCP_DDIC_REP_PRESENT		BIT(28)
9060 #define  HDCP_DDID_REP_PRESENT		BIT(27)
9061 #define  HDCP_DDIF_REP_PRESENT		BIT(26)
9062 #define  HDCP_DDIE_REP_PRESENT		BIT(25)
9063 #define  HDCP_DDIB_SHA1_M0		(1 << 20)
9064 #define  HDCP_DDIA_SHA1_M0		(2 << 20)
9065 #define  HDCP_DDIC_SHA1_M0		(3 << 20)
9066 #define  HDCP_DDID_SHA1_M0		(4 << 20)
9067 #define  HDCP_DDIF_SHA1_M0		(5 << 20)
9068 #define  HDCP_DDIE_SHA1_M0		(6 << 20) /* Bspec says 5? */
9069 #define  HDCP_SHA1_BUSY			BIT(16)
9070 #define  HDCP_SHA1_READY		BIT(17)
9071 #define  HDCP_SHA1_COMPLETE		BIT(18)
9072 #define  HDCP_SHA1_V_MATCH		BIT(19)
9073 #define  HDCP_SHA1_TEXT_32		(1 << 1)
9074 #define  HDCP_SHA1_COMPLETE_HASH	(2 << 1)
9075 #define  HDCP_SHA1_TEXT_24		(4 << 1)
9076 #define  HDCP_SHA1_TEXT_16		(5 << 1)
9077 #define  HDCP_SHA1_TEXT_8		(6 << 1)
9078 #define  HDCP_SHA1_TEXT_0		(7 << 1)
9079 #define HDCP_SHA_V_PRIME_H0		_MMIO(0x66d04)
9080 #define HDCP_SHA_V_PRIME_H1		_MMIO(0x66d08)
9081 #define HDCP_SHA_V_PRIME_H2		_MMIO(0x66d0C)
9082 #define HDCP_SHA_V_PRIME_H3		_MMIO(0x66d10)
9083 #define HDCP_SHA_V_PRIME_H4		_MMIO(0x66d14)
9084 #define HDCP_SHA_V_PRIME(h)		_MMIO((0x66d04 + (h) * 4))
9085 #define HDCP_SHA_TEXT			_MMIO(0x66d18)
9086 
9087 /* HDCP Auth Registers */
9088 #define _PORTA_HDCP_AUTHENC		0x66800
9089 #define _PORTB_HDCP_AUTHENC		0x66500
9090 #define _PORTC_HDCP_AUTHENC		0x66600
9091 #define _PORTD_HDCP_AUTHENC		0x66700
9092 #define _PORTE_HDCP_AUTHENC		0x66A00
9093 #define _PORTF_HDCP_AUTHENC		0x66900
9094 #define _PORT_HDCP_AUTHENC(port, x)	_MMIO(_PICK(port, \
9095 					  _PORTA_HDCP_AUTHENC, \
9096 					  _PORTB_HDCP_AUTHENC, \
9097 					  _PORTC_HDCP_AUTHENC, \
9098 					  _PORTD_HDCP_AUTHENC, \
9099 					  _PORTE_HDCP_AUTHENC, \
9100 					  _PORTF_HDCP_AUTHENC) + (x))
9101 #define PORT_HDCP_CONF(port)		_PORT_HDCP_AUTHENC(port, 0x0)
9102 #define  HDCP_CONF_CAPTURE_AN		BIT(0)
9103 #define  HDCP_CONF_AUTH_AND_ENC		(BIT(1) | BIT(0))
9104 #define PORT_HDCP_ANINIT(port)		_PORT_HDCP_AUTHENC(port, 0x4)
9105 #define PORT_HDCP_ANLO(port)		_PORT_HDCP_AUTHENC(port, 0x8)
9106 #define PORT_HDCP_ANHI(port)		_PORT_HDCP_AUTHENC(port, 0xC)
9107 #define PORT_HDCP_BKSVLO(port)		_PORT_HDCP_AUTHENC(port, 0x10)
9108 #define PORT_HDCP_BKSVHI(port)		_PORT_HDCP_AUTHENC(port, 0x14)
9109 #define PORT_HDCP_RPRIME(port)		_PORT_HDCP_AUTHENC(port, 0x18)
9110 #define PORT_HDCP_STATUS(port)		_PORT_HDCP_AUTHENC(port, 0x1C)
9111 #define  HDCP_STATUS_STREAM_A_ENC	BIT(31)
9112 #define  HDCP_STATUS_STREAM_B_ENC	BIT(30)
9113 #define  HDCP_STATUS_STREAM_C_ENC	BIT(29)
9114 #define  HDCP_STATUS_STREAM_D_ENC	BIT(28)
9115 #define  HDCP_STATUS_AUTH		BIT(21)
9116 #define  HDCP_STATUS_ENC		BIT(20)
9117 #define  HDCP_STATUS_RI_MATCH		BIT(19)
9118 #define  HDCP_STATUS_R0_READY		BIT(18)
9119 #define  HDCP_STATUS_AN_READY		BIT(17)
9120 #define  HDCP_STATUS_CIPHER		BIT(16)
9121 #define  HDCP_STATUS_FRAME_CNT(x)	(((x) >> 8) & 0xff)
9122 
9123 /* HDCP2.2 Registers */
9124 #define _PORTA_HDCP2_BASE		0x66800
9125 #define _PORTB_HDCP2_BASE		0x66500
9126 #define _PORTC_HDCP2_BASE		0x66600
9127 #define _PORTD_HDCP2_BASE		0x66700
9128 #define _PORTE_HDCP2_BASE		0x66A00
9129 #define _PORTF_HDCP2_BASE		0x66900
9130 #define _PORT_HDCP2_BASE(port, x)	_MMIO(_PICK((port), \
9131 					  _PORTA_HDCP2_BASE, \
9132 					  _PORTB_HDCP2_BASE, \
9133 					  _PORTC_HDCP2_BASE, \
9134 					  _PORTD_HDCP2_BASE, \
9135 					  _PORTE_HDCP2_BASE, \
9136 					  _PORTF_HDCP2_BASE) + (x))
9137 
9138 #define HDCP2_AUTH_DDI(port)		_PORT_HDCP2_BASE(port, 0x98)
9139 #define   AUTH_LINK_AUTHENTICATED	BIT(31)
9140 #define   AUTH_LINK_TYPE		BIT(30)
9141 #define   AUTH_FORCE_CLR_INPUTCTR	BIT(19)
9142 #define   AUTH_CLR_KEYS			BIT(18)
9143 
9144 #define HDCP2_CTL_DDI(port)		_PORT_HDCP2_BASE(port, 0xB0)
9145 #define   CTL_LINK_ENCRYPTION_REQ	BIT(31)
9146 
9147 #define HDCP2_STATUS_DDI(port)		_PORT_HDCP2_BASE(port, 0xB4)
9148 #define   STREAM_ENCRYPTION_STATUS_A	BIT(31)
9149 #define   STREAM_ENCRYPTION_STATUS_B	BIT(30)
9150 #define   STREAM_ENCRYPTION_STATUS_C	BIT(29)
9151 #define   LINK_TYPE_STATUS		BIT(22)
9152 #define   LINK_AUTH_STATUS		BIT(21)
9153 #define   LINK_ENCRYPTION_STATUS	BIT(20)
9154 
9155 /* Per-pipe DDI Function Control */
9156 #define _TRANS_DDI_FUNC_CTL_A		0x60400
9157 #define _TRANS_DDI_FUNC_CTL_B		0x61400
9158 #define _TRANS_DDI_FUNC_CTL_C		0x62400
9159 #define _TRANS_DDI_FUNC_CTL_EDP		0x6F400
9160 #define _TRANS_DDI_FUNC_CTL_DSI0	0x6b400
9161 #define _TRANS_DDI_FUNC_CTL_DSI1	0x6bc00
9162 #define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A)
9163 
9164 #define  TRANS_DDI_FUNC_ENABLE		(1 << 31)
9165 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
9166 #define  TRANS_DDI_PORT_MASK		(7 << 28)
9167 #define  TRANS_DDI_PORT_SHIFT		28
9168 #define  TRANS_DDI_SELECT_PORT(x)	((x) << 28)
9169 #define  TRANS_DDI_PORT_NONE		(0 << 28)
9170 #define  TRANS_DDI_MODE_SELECT_MASK	(7 << 24)
9171 #define  TRANS_DDI_MODE_SELECT_HDMI	(0 << 24)
9172 #define  TRANS_DDI_MODE_SELECT_DVI	(1 << 24)
9173 #define  TRANS_DDI_MODE_SELECT_DP_SST	(2 << 24)
9174 #define  TRANS_DDI_MODE_SELECT_DP_MST	(3 << 24)
9175 #define  TRANS_DDI_MODE_SELECT_FDI	(4 << 24)
9176 #define  TRANS_DDI_BPC_MASK		(7 << 20)
9177 #define  TRANS_DDI_BPC_8		(0 << 20)
9178 #define  TRANS_DDI_BPC_10		(1 << 20)
9179 #define  TRANS_DDI_BPC_6		(2 << 20)
9180 #define  TRANS_DDI_BPC_12		(3 << 20)
9181 #define  TRANS_DDI_PVSYNC		(1 << 17)
9182 #define  TRANS_DDI_PHSYNC		(1 << 16)
9183 #define  TRANS_DDI_EDP_INPUT_MASK	(7 << 12)
9184 #define  TRANS_DDI_EDP_INPUT_A_ON	(0 << 12)
9185 #define  TRANS_DDI_EDP_INPUT_A_ONOFF	(4 << 12)
9186 #define  TRANS_DDI_EDP_INPUT_B_ONOFF	(5 << 12)
9187 #define  TRANS_DDI_EDP_INPUT_C_ONOFF	(6 << 12)
9188 #define  TRANS_DDI_HDCP_SIGNALLING	(1 << 9)
9189 #define  TRANS_DDI_DP_VC_PAYLOAD_ALLOC	(1 << 8)
9190 #define  TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
9191 #define  TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6)
9192 #define  TRANS_DDI_BFI_ENABLE		(1 << 4)
9193 #define  TRANS_DDI_HIGH_TMDS_CHAR_RATE	(1 << 4)
9194 #define  TRANS_DDI_HDMI_SCRAMBLING	(1 << 0)
9195 #define  TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \
9196 					| TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \
9197 					| TRANS_DDI_HDMI_SCRAMBLING)
9198 
9199 #define _TRANS_DDI_FUNC_CTL2_A		0x60404
9200 #define _TRANS_DDI_FUNC_CTL2_B		0x61404
9201 #define _TRANS_DDI_FUNC_CTL2_C		0x62404
9202 #define _TRANS_DDI_FUNC_CTL2_EDP	0x6f404
9203 #define _TRANS_DDI_FUNC_CTL2_DSI0	0x6b404
9204 #define _TRANS_DDI_FUNC_CTL2_DSI1	0x6bc04
9205 #define TRANS_DDI_FUNC_CTL2(tran)	_MMIO_TRANS2(tran, \
9206 						     _TRANS_DDI_FUNC_CTL2_A)
9207 #define  PORT_SYNC_MODE_ENABLE			(1 << 4)
9208 #define  PORT_SYNC_MODE_MASTER_SELECT(x)	((x) < 0)
9209 #define  PORT_SYNC_MODE_MASTER_SELECT_MASK	(0x7 << 0)
9210 #define  PORT_SYNC_MODE_MASTER_SELECT_SHIFT	0
9211 
9212 /* DisplayPort Transport Control */
9213 #define _DP_TP_CTL_A			0x64040
9214 #define _DP_TP_CTL_B			0x64140
9215 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
9216 #define  DP_TP_CTL_ENABLE			(1 << 31)
9217 #define  DP_TP_CTL_FEC_ENABLE			(1 << 30)
9218 #define  DP_TP_CTL_MODE_SST			(0 << 27)
9219 #define  DP_TP_CTL_MODE_MST			(1 << 27)
9220 #define  DP_TP_CTL_FORCE_ACT			(1 << 25)
9221 #define  DP_TP_CTL_ENHANCED_FRAME_ENABLE	(1 << 18)
9222 #define  DP_TP_CTL_FDI_AUTOTRAIN		(1 << 15)
9223 #define  DP_TP_CTL_LINK_TRAIN_MASK		(7 << 8)
9224 #define  DP_TP_CTL_LINK_TRAIN_PAT1		(0 << 8)
9225 #define  DP_TP_CTL_LINK_TRAIN_PAT2		(1 << 8)
9226 #define  DP_TP_CTL_LINK_TRAIN_PAT3		(4 << 8)
9227 #define  DP_TP_CTL_LINK_TRAIN_PAT4		(5 << 8)
9228 #define  DP_TP_CTL_LINK_TRAIN_IDLE		(2 << 8)
9229 #define  DP_TP_CTL_LINK_TRAIN_NORMAL		(3 << 8)
9230 #define  DP_TP_CTL_SCRAMBLE_DISABLE		(1 << 7)
9231 
9232 /* DisplayPort Transport Status */
9233 #define _DP_TP_STATUS_A			0x64044
9234 #define _DP_TP_STATUS_B			0x64144
9235 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
9236 #define  DP_TP_STATUS_FEC_ENABLE_LIVE		(1 << 28)
9237 #define  DP_TP_STATUS_IDLE_DONE			(1 << 25)
9238 #define  DP_TP_STATUS_ACT_SENT			(1 << 24)
9239 #define  DP_TP_STATUS_MODE_STATUS_MST		(1 << 23)
9240 #define  DP_TP_STATUS_AUTOTRAIN_DONE		(1 << 12)
9241 #define  DP_TP_STATUS_PAYLOAD_MAPPING_VC2	(3 << 8)
9242 #define  DP_TP_STATUS_PAYLOAD_MAPPING_VC1	(3 << 4)
9243 #define  DP_TP_STATUS_PAYLOAD_MAPPING_VC0	(3 << 0)
9244 
9245 /* DDI Buffer Control */
9246 #define _DDI_BUF_CTL_A				0x64000
9247 #define _DDI_BUF_CTL_B				0x64100
9248 #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
9249 #define  DDI_BUF_CTL_ENABLE			(1 << 31)
9250 #define  DDI_BUF_TRANS_SELECT(n)	((n) << 24)
9251 #define  DDI_BUF_EMP_MASK			(0xf << 24)
9252 #define  DDI_BUF_PORT_REVERSAL			(1 << 16)
9253 #define  DDI_BUF_IS_IDLE			(1 << 7)
9254 #define  DDI_A_4_LANES				(1 << 4)
9255 #define  DDI_PORT_WIDTH(width)			(((width) - 1) << 1)
9256 #define  DDI_PORT_WIDTH_MASK			(7 << 1)
9257 #define  DDI_PORT_WIDTH_SHIFT			1
9258 #define  DDI_INIT_DISPLAY_DETECTED		(1 << 0)
9259 
9260 /* DDI Buffer Translations */
9261 #define _DDI_BUF_TRANS_A		0x64E00
9262 #define _DDI_BUF_TRANS_B		0x64E60
9263 #define DDI_BUF_TRANS_LO(port, i)	_MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
9264 #define  DDI_BUF_BALANCE_LEG_ENABLE	(1 << 31)
9265 #define DDI_BUF_TRANS_HI(port, i)	_MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
9266 
9267 /* Sideband Interface (SBI) is programmed indirectly, via
9268  * SBI_ADDR, which contains the register offset; and SBI_DATA,
9269  * which contains the payload */
9270 #define SBI_ADDR			_MMIO(0xC6000)
9271 #define SBI_DATA			_MMIO(0xC6004)
9272 #define SBI_CTL_STAT			_MMIO(0xC6008)
9273 #define  SBI_CTL_DEST_ICLK		(0x0 << 16)
9274 #define  SBI_CTL_DEST_MPHY		(0x1 << 16)
9275 #define  SBI_CTL_OP_IORD		(0x2 << 8)
9276 #define  SBI_CTL_OP_IOWR		(0x3 << 8)
9277 #define  SBI_CTL_OP_CRRD		(0x6 << 8)
9278 #define  SBI_CTL_OP_CRWR		(0x7 << 8)
9279 #define  SBI_RESPONSE_FAIL		(0x1 << 1)
9280 #define  SBI_RESPONSE_SUCCESS		(0x0 << 1)
9281 #define  SBI_BUSY			(0x1 << 0)
9282 #define  SBI_READY			(0x0 << 0)
9283 
9284 /* SBI offsets */
9285 #define  SBI_SSCDIVINTPHASE			0x0200
9286 #define  SBI_SSCDIVINTPHASE6			0x0600
9287 #define   SBI_SSCDIVINTPHASE_DIVSEL_SHIFT	1
9288 #define   SBI_SSCDIVINTPHASE_DIVSEL_MASK	(0x7f << 1)
9289 #define   SBI_SSCDIVINTPHASE_DIVSEL(x)		((x) << 1)
9290 #define   SBI_SSCDIVINTPHASE_INCVAL_SHIFT	8
9291 #define   SBI_SSCDIVINTPHASE_INCVAL_MASK	(0x7f << 8)
9292 #define   SBI_SSCDIVINTPHASE_INCVAL(x)		((x) << 8)
9293 #define   SBI_SSCDIVINTPHASE_DIR(x)		((x) << 15)
9294 #define   SBI_SSCDIVINTPHASE_PROPAGATE		(1 << 0)
9295 #define  SBI_SSCDITHPHASE			0x0204
9296 #define  SBI_SSCCTL				0x020c
9297 #define  SBI_SSCCTL6				0x060C
9298 #define   SBI_SSCCTL_PATHALT			(1 << 3)
9299 #define   SBI_SSCCTL_DISABLE			(1 << 0)
9300 #define  SBI_SSCAUXDIV6				0x0610
9301 #define   SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT	4
9302 #define   SBI_SSCAUXDIV_FINALDIV2SEL_MASK	(1 << 4)
9303 #define   SBI_SSCAUXDIV_FINALDIV2SEL(x)		((x) << 4)
9304 #define  SBI_DBUFF0				0x2a00
9305 #define  SBI_GEN0				0x1f00
9306 #define   SBI_GEN0_CFG_BUFFENABLE_DISABLE	(1 << 0)
9307 
9308 /* LPT PIXCLK_GATE */
9309 #define PIXCLK_GATE			_MMIO(0xC6020)
9310 #define  PIXCLK_GATE_UNGATE		(1 << 0)
9311 #define  PIXCLK_GATE_GATE		(0 << 0)
9312 
9313 /* SPLL */
9314 #define SPLL_CTL			_MMIO(0x46020)
9315 #define  SPLL_PLL_ENABLE		(1 << 31)
9316 #define  SPLL_PLL_SSC			(1 << 28)
9317 #define  SPLL_PLL_NON_SSC		(2 << 28)
9318 #define  SPLL_PLL_LCPLL			(3 << 28)
9319 #define  SPLL_PLL_REF_MASK		(3 << 28)
9320 #define  SPLL_PLL_FREQ_810MHz		(0 << 26)
9321 #define  SPLL_PLL_FREQ_1350MHz		(1 << 26)
9322 #define  SPLL_PLL_FREQ_2700MHz		(2 << 26)
9323 #define  SPLL_PLL_FREQ_MASK		(3 << 26)
9324 
9325 /* WRPLL */
9326 #define _WRPLL_CTL1			0x46040
9327 #define _WRPLL_CTL2			0x46060
9328 #define WRPLL_CTL(pll)			_MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)
9329 #define  WRPLL_PLL_ENABLE		(1 << 31)
9330 #define  WRPLL_PLL_SSC			(1 << 28)
9331 #define  WRPLL_PLL_NON_SSC		(2 << 28)
9332 #define  WRPLL_PLL_LCPLL		(3 << 28)
9333 #define  WRPLL_PLL_REF_MASK		(3 << 28)
9334 /* WRPLL divider programming */
9335 #define  WRPLL_DIVIDER_REFERENCE(x)	((x) << 0)
9336 #define  WRPLL_DIVIDER_REF_MASK		(0xff)
9337 #define  WRPLL_DIVIDER_POST(x)		((x) << 8)
9338 #define  WRPLL_DIVIDER_POST_MASK	(0x3f << 8)
9339 #define  WRPLL_DIVIDER_POST_SHIFT	8
9340 #define  WRPLL_DIVIDER_FEEDBACK(x)	((x) << 16)
9341 #define  WRPLL_DIVIDER_FB_SHIFT		16
9342 #define  WRPLL_DIVIDER_FB_MASK		(0xff << 16)
9343 
9344 /* Port clock selection */
9345 #define _PORT_CLK_SEL_A			0x46100
9346 #define _PORT_CLK_SEL_B			0x46104
9347 #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)
9348 #define  PORT_CLK_SEL_LCPLL_2700	(0 << 29)
9349 #define  PORT_CLK_SEL_LCPLL_1350	(1 << 29)
9350 #define  PORT_CLK_SEL_LCPLL_810		(2 << 29)
9351 #define  PORT_CLK_SEL_SPLL		(3 << 29)
9352 #define  PORT_CLK_SEL_WRPLL(pll)	(((pll) + 4) << 29)
9353 #define  PORT_CLK_SEL_WRPLL1		(4 << 29)
9354 #define  PORT_CLK_SEL_WRPLL2		(5 << 29)
9355 #define  PORT_CLK_SEL_NONE		(7 << 29)
9356 #define  PORT_CLK_SEL_MASK		(7 << 29)
9357 
9358 /* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */
9359 #define DDI_CLK_SEL(port)		PORT_CLK_SEL(port)
9360 #define  DDI_CLK_SEL_NONE		(0x0 << 28)
9361 #define  DDI_CLK_SEL_MG			(0x8 << 28)
9362 #define  DDI_CLK_SEL_TBT_162		(0xC << 28)
9363 #define  DDI_CLK_SEL_TBT_270		(0xD << 28)
9364 #define  DDI_CLK_SEL_TBT_540		(0xE << 28)
9365 #define  DDI_CLK_SEL_TBT_810		(0xF << 28)
9366 #define  DDI_CLK_SEL_MASK		(0xF << 28)
9367 
9368 /* Transcoder clock selection */
9369 #define _TRANS_CLK_SEL_A		0x46140
9370 #define _TRANS_CLK_SEL_B		0x46144
9371 #define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B)
9372 /* For each transcoder, we need to select the corresponding port clock */
9373 #define  TRANS_CLK_SEL_DISABLED		(0x0 << 29)
9374 #define  TRANS_CLK_SEL_PORT(x)		(((x) + 1) << 29)
9375 
9376 #define CDCLK_FREQ			_MMIO(0x46200)
9377 
9378 #define _TRANSA_MSA_MISC		0x60410
9379 #define _TRANSB_MSA_MISC		0x61410
9380 #define _TRANSC_MSA_MISC		0x62410
9381 #define _TRANS_EDP_MSA_MISC		0x6f410
9382 #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)
9383 
9384 #define  TRANS_MSA_SYNC_CLK		(1 << 0)
9385 #define  TRANS_MSA_SAMPLING_444		(2 << 1)
9386 #define  TRANS_MSA_CLRSP_YCBCR		(2 << 3)
9387 #define  TRANS_MSA_6_BPC		(0 << 5)
9388 #define  TRANS_MSA_8_BPC		(1 << 5)
9389 #define  TRANS_MSA_10_BPC		(2 << 5)
9390 #define  TRANS_MSA_12_BPC		(3 << 5)
9391 #define  TRANS_MSA_16_BPC		(4 << 5)
9392 #define  TRANS_MSA_CEA_RANGE		(1 << 3)
9393 
9394 /* LCPLL Control */
9395 #define LCPLL_CTL			_MMIO(0x130040)
9396 #define  LCPLL_PLL_DISABLE		(1 << 31)
9397 #define  LCPLL_PLL_LOCK			(1 << 30)
9398 #define  LCPLL_CLK_FREQ_MASK		(3 << 26)
9399 #define  LCPLL_CLK_FREQ_450		(0 << 26)
9400 #define  LCPLL_CLK_FREQ_54O_BDW		(1 << 26)
9401 #define  LCPLL_CLK_FREQ_337_5_BDW	(2 << 26)
9402 #define  LCPLL_CLK_FREQ_675_BDW		(3 << 26)
9403 #define  LCPLL_CD_CLOCK_DISABLE		(1 << 25)
9404 #define  LCPLL_ROOT_CD_CLOCK_DISABLE	(1 << 24)
9405 #define  LCPLL_CD2X_CLOCK_DISABLE	(1 << 23)
9406 #define  LCPLL_POWER_DOWN_ALLOW		(1 << 22)
9407 #define  LCPLL_CD_SOURCE_FCLK		(1 << 21)
9408 #define  LCPLL_CD_SOURCE_FCLK_DONE	(1 << 19)
9409 
9410 /*
9411  * SKL Clocks
9412  */
9413 
9414 /* CDCLK_CTL */
9415 #define CDCLK_CTL			_MMIO(0x46000)
9416 #define  CDCLK_FREQ_SEL_MASK		(3 << 26)
9417 #define  CDCLK_FREQ_450_432		(0 << 26)
9418 #define  CDCLK_FREQ_540			(1 << 26)
9419 #define  CDCLK_FREQ_337_308		(2 << 26)
9420 #define  CDCLK_FREQ_675_617		(3 << 26)
9421 #define  BXT_CDCLK_CD2X_DIV_SEL_MASK	(3 << 22)
9422 #define  BXT_CDCLK_CD2X_DIV_SEL_1	(0 << 22)
9423 #define  BXT_CDCLK_CD2X_DIV_SEL_1_5	(1 << 22)
9424 #define  BXT_CDCLK_CD2X_DIV_SEL_2	(2 << 22)
9425 #define  BXT_CDCLK_CD2X_DIV_SEL_4	(3 << 22)
9426 #define  BXT_CDCLK_CD2X_PIPE(pipe)	((pipe) << 20)
9427 #define  CDCLK_DIVMUX_CD_OVERRIDE	(1 << 19)
9428 #define  BXT_CDCLK_CD2X_PIPE_NONE	BXT_CDCLK_CD2X_PIPE(3)
9429 #define  ICL_CDCLK_CD2X_PIPE_NONE	(7 << 19)
9430 #define  BXT_CDCLK_SSA_PRECHARGE_ENABLE	(1 << 16)
9431 #define  CDCLK_FREQ_DECIMAL_MASK	(0x7ff)
9432 
9433 /* LCPLL_CTL */
9434 #define LCPLL1_CTL		_MMIO(0x46010)
9435 #define LCPLL2_CTL		_MMIO(0x46014)
9436 #define  LCPLL_PLL_ENABLE	(1 << 31)
9437 
9438 /* DPLL control1 */
9439 #define DPLL_CTRL1		_MMIO(0x6C058)
9440 #define  DPLL_CTRL1_HDMI_MODE(id)		(1 << ((id) * 6 + 5))
9441 #define  DPLL_CTRL1_SSC(id)			(1 << ((id) * 6 + 4))
9442 #define  DPLL_CTRL1_LINK_RATE_MASK(id)		(7 << ((id) * 6 + 1))
9443 #define  DPLL_CTRL1_LINK_RATE_SHIFT(id)		((id) * 6 + 1)
9444 #define  DPLL_CTRL1_LINK_RATE(linkrate, id)	((linkrate) << ((id) * 6 + 1))
9445 #define  DPLL_CTRL1_OVERRIDE(id)		(1 << ((id) * 6))
9446 #define  DPLL_CTRL1_LINK_RATE_2700		0
9447 #define  DPLL_CTRL1_LINK_RATE_1350		1
9448 #define  DPLL_CTRL1_LINK_RATE_810		2
9449 #define  DPLL_CTRL1_LINK_RATE_1620		3
9450 #define  DPLL_CTRL1_LINK_RATE_1080		4
9451 #define  DPLL_CTRL1_LINK_RATE_2160		5
9452 
9453 /* DPLL control2 */
9454 #define DPLL_CTRL2				_MMIO(0x6C05C)
9455 #define  DPLL_CTRL2_DDI_CLK_OFF(port)		(1 << ((port) + 15))
9456 #define  DPLL_CTRL2_DDI_CLK_SEL_MASK(port)	(3 << ((port) * 3 + 1))
9457 #define  DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port)    ((port) * 3 + 1)
9458 #define  DPLL_CTRL2_DDI_CLK_SEL(clk, port)	((clk) << ((port) * 3 + 1))
9459 #define  DPLL_CTRL2_DDI_SEL_OVERRIDE(port)     (1 << ((port) * 3))
9460 
9461 /* DPLL Status */
9462 #define DPLL_STATUS	_MMIO(0x6C060)
9463 #define  DPLL_LOCK(id) (1 << ((id) * 8))
9464 
9465 /* DPLL cfg */
9466 #define _DPLL1_CFGCR1	0x6C040
9467 #define _DPLL2_CFGCR1	0x6C048
9468 #define _DPLL3_CFGCR1	0x6C050
9469 #define  DPLL_CFGCR1_FREQ_ENABLE	(1 << 31)
9470 #define  DPLL_CFGCR1_DCO_FRACTION_MASK	(0x7fff << 9)
9471 #define  DPLL_CFGCR1_DCO_FRACTION(x)	((x) << 9)
9472 #define  DPLL_CFGCR1_DCO_INTEGER_MASK	(0x1ff)
9473 
9474 #define _DPLL1_CFGCR2	0x6C044
9475 #define _DPLL2_CFGCR2	0x6C04C
9476 #define _DPLL3_CFGCR2	0x6C054
9477 #define  DPLL_CFGCR2_QDIV_RATIO_MASK	(0xff << 8)
9478 #define  DPLL_CFGCR2_QDIV_RATIO(x)	((x) << 8)
9479 #define  DPLL_CFGCR2_QDIV_MODE(x)	((x) << 7)
9480 #define  DPLL_CFGCR2_KDIV_MASK		(3 << 5)
9481 #define  DPLL_CFGCR2_KDIV(x)		((x) << 5)
9482 #define  DPLL_CFGCR2_KDIV_5 (0 << 5)
9483 #define  DPLL_CFGCR2_KDIV_2 (1 << 5)
9484 #define  DPLL_CFGCR2_KDIV_3 (2 << 5)
9485 #define  DPLL_CFGCR2_KDIV_1 (3 << 5)
9486 #define  DPLL_CFGCR2_PDIV_MASK		(7 << 2)
9487 #define  DPLL_CFGCR2_PDIV(x)		((x) << 2)
9488 #define  DPLL_CFGCR2_PDIV_1 (0 << 2)
9489 #define  DPLL_CFGCR2_PDIV_2 (1 << 2)
9490 #define  DPLL_CFGCR2_PDIV_3 (2 << 2)
9491 #define  DPLL_CFGCR2_PDIV_7 (4 << 2)
9492 #define  DPLL_CFGCR2_CENTRAL_FREQ_MASK	(3)
9493 
9494 #define DPLL_CFGCR1(id)	_MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
9495 #define DPLL_CFGCR2(id)	_MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
9496 
9497 /*
9498  * CNL Clocks
9499  */
9500 #define DPCLKA_CFGCR0				_MMIO(0x6C200)
9501 #define DPCLKA_CFGCR0_ICL			_MMIO(0x164280)
9502 #define  DPCLKA_CFGCR0_DDI_CLK_OFF(port)	(1 << ((port) ==  PORT_F ? 23 : \
9503 						      (port) + 10))
9504 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port)   (1 << ((port) + 10))
9505 #define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \
9506 						      21 : (tc_port) + 12))
9507 #define  DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)	((port) == PORT_F ? 21 : \
9508 						(port) * 2)
9509 #define  DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port)	(3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
9510 #define  DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port)	((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
9511 
9512 /* CNL PLL */
9513 #define DPLL0_ENABLE		0x46010
9514 #define DPLL1_ENABLE		0x46014
9515 #define  PLL_ENABLE		(1 << 31)
9516 #define  PLL_LOCK		(1 << 30)
9517 #define  PLL_POWER_ENABLE	(1 << 27)
9518 #define  PLL_POWER_STATE	(1 << 26)
9519 #define CNL_DPLL_ENABLE(pll)	_MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE)
9520 
9521 #define TBT_PLL_ENABLE		_MMIO(0x46020)
9522 
9523 #define _MG_PLL1_ENABLE		0x46030
9524 #define _MG_PLL2_ENABLE		0x46034
9525 #define _MG_PLL3_ENABLE		0x46038
9526 #define _MG_PLL4_ENABLE		0x4603C
9527 /* Bits are the same as DPLL0_ENABLE */
9528 #define MG_PLL_ENABLE(port)	_MMIO_PORT((port) - PORT_C, _MG_PLL1_ENABLE, \
9529 					   _MG_PLL2_ENABLE)
9530 
9531 #define _MG_REFCLKIN_CTL_PORT1				0x16892C
9532 #define _MG_REFCLKIN_CTL_PORT2				0x16992C
9533 #define _MG_REFCLKIN_CTL_PORT3				0x16A92C
9534 #define _MG_REFCLKIN_CTL_PORT4				0x16B92C
9535 #define   MG_REFCLKIN_CTL_OD_2_MUX(x)			((x) << 8)
9536 #define   MG_REFCLKIN_CTL_OD_2_MUX_MASK			(0x7 << 8)
9537 #define MG_REFCLKIN_CTL(port) _MMIO_PORT((port) - PORT_C, \
9538 					 _MG_REFCLKIN_CTL_PORT1, \
9539 					 _MG_REFCLKIN_CTL_PORT2)
9540 
9541 #define _MG_CLKTOP2_CORECLKCTL1_PORT1			0x1688D8
9542 #define _MG_CLKTOP2_CORECLKCTL1_PORT2			0x1698D8
9543 #define _MG_CLKTOP2_CORECLKCTL1_PORT3			0x16A8D8
9544 #define _MG_CLKTOP2_CORECLKCTL1_PORT4			0x16B8D8
9545 #define   MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x)		((x) << 16)
9546 #define   MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK	(0xff << 16)
9547 #define   MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x)		((x) << 8)
9548 #define   MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK	(0xff << 8)
9549 #define MG_CLKTOP2_CORECLKCTL1(port) _MMIO_PORT((port) - PORT_C, \
9550 						_MG_CLKTOP2_CORECLKCTL1_PORT1, \
9551 						_MG_CLKTOP2_CORECLKCTL1_PORT2)
9552 
9553 #define _MG_CLKTOP2_HSCLKCTL_PORT1			0x1688D4
9554 #define _MG_CLKTOP2_HSCLKCTL_PORT2			0x1698D4
9555 #define _MG_CLKTOP2_HSCLKCTL_PORT3			0x16A8D4
9556 #define _MG_CLKTOP2_HSCLKCTL_PORT4			0x16B8D4
9557 #define   MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x)		((x) << 16)
9558 #define   MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK	(0x1 << 16)
9559 #define   MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x)	((x) << 14)
9560 #define   MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK	(0x3 << 14)
9561 #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK		(0x3 << 12)
9562 #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2		(0 << 12)
9563 #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3		(1 << 12)
9564 #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5		(2 << 12)
9565 #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7		(3 << 12)
9566 #define   MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x)		((x) << 8)
9567 #define   MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT		8
9568 #define   MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK		(0xf << 8)
9569 #define MG_CLKTOP2_HSCLKCTL(port) _MMIO_PORT((port) - PORT_C, \
9570 					     _MG_CLKTOP2_HSCLKCTL_PORT1, \
9571 					     _MG_CLKTOP2_HSCLKCTL_PORT2)
9572 
9573 #define _MG_PLL_DIV0_PORT1				0x168A00
9574 #define _MG_PLL_DIV0_PORT2				0x169A00
9575 #define _MG_PLL_DIV0_PORT3				0x16AA00
9576 #define _MG_PLL_DIV0_PORT4				0x16BA00
9577 #define   MG_PLL_DIV0_FRACNEN_H				(1 << 30)
9578 #define   MG_PLL_DIV0_FBDIV_FRAC_MASK			(0x3fffff << 8)
9579 #define   MG_PLL_DIV0_FBDIV_FRAC_SHIFT			8
9580 #define   MG_PLL_DIV0_FBDIV_FRAC(x)			((x) << 8)
9581 #define   MG_PLL_DIV0_FBDIV_INT_MASK			(0xff << 0)
9582 #define   MG_PLL_DIV0_FBDIV_INT(x)			((x) << 0)
9583 #define MG_PLL_DIV0(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_DIV0_PORT1, \
9584 				     _MG_PLL_DIV0_PORT2)
9585 
9586 #define _MG_PLL_DIV1_PORT1				0x168A04
9587 #define _MG_PLL_DIV1_PORT2				0x169A04
9588 #define _MG_PLL_DIV1_PORT3				0x16AA04
9589 #define _MG_PLL_DIV1_PORT4				0x16BA04
9590 #define   MG_PLL_DIV1_IREF_NDIVRATIO(x)			((x) << 16)
9591 #define   MG_PLL_DIV1_DITHER_DIV_1			(0 << 12)
9592 #define   MG_PLL_DIV1_DITHER_DIV_2			(1 << 12)
9593 #define   MG_PLL_DIV1_DITHER_DIV_4			(2 << 12)
9594 #define   MG_PLL_DIV1_DITHER_DIV_8			(3 << 12)
9595 #define   MG_PLL_DIV1_NDIVRATIO(x)			((x) << 4)
9596 #define   MG_PLL_DIV1_FBPREDIV_MASK			(0xf << 0)
9597 #define   MG_PLL_DIV1_FBPREDIV(x)			((x) << 0)
9598 #define MG_PLL_DIV1(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_DIV1_PORT1, \
9599 				     _MG_PLL_DIV1_PORT2)
9600 
9601 #define _MG_PLL_LF_PORT1				0x168A08
9602 #define _MG_PLL_LF_PORT2				0x169A08
9603 #define _MG_PLL_LF_PORT3				0x16AA08
9604 #define _MG_PLL_LF_PORT4				0x16BA08
9605 #define   MG_PLL_LF_TDCTARGETCNT(x)			((x) << 24)
9606 #define   MG_PLL_LF_AFCCNTSEL_256			(0 << 20)
9607 #define   MG_PLL_LF_AFCCNTSEL_512			(1 << 20)
9608 #define   MG_PLL_LF_GAINCTRL(x)				((x) << 16)
9609 #define   MG_PLL_LF_INT_COEFF(x)			((x) << 8)
9610 #define   MG_PLL_LF_PROP_COEFF(x)			((x) << 0)
9611 #define MG_PLL_LF(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_LF_PORT1, \
9612 				   _MG_PLL_LF_PORT2)
9613 
9614 #define _MG_PLL_FRAC_LOCK_PORT1				0x168A0C
9615 #define _MG_PLL_FRAC_LOCK_PORT2				0x169A0C
9616 #define _MG_PLL_FRAC_LOCK_PORT3				0x16AA0C
9617 #define _MG_PLL_FRAC_LOCK_PORT4				0x16BA0C
9618 #define   MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32		(1 << 18)
9619 #define   MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32		(1 << 16)
9620 #define   MG_PLL_FRAC_LOCK_LOCKTHRESH(x)		((x) << 11)
9621 #define   MG_PLL_FRAC_LOCK_DCODITHEREN			(1 << 10)
9622 #define   MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN		(1 << 8)
9623 #define   MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(x)		((x) << 0)
9624 #define MG_PLL_FRAC_LOCK(port) _MMIO_PORT((port) - PORT_C, \
9625 					  _MG_PLL_FRAC_LOCK_PORT1, \
9626 					  _MG_PLL_FRAC_LOCK_PORT2)
9627 
9628 #define _MG_PLL_SSC_PORT1				0x168A10
9629 #define _MG_PLL_SSC_PORT2				0x169A10
9630 #define _MG_PLL_SSC_PORT3				0x16AA10
9631 #define _MG_PLL_SSC_PORT4				0x16BA10
9632 #define   MG_PLL_SSC_EN					(1 << 28)
9633 #define   MG_PLL_SSC_TYPE(x)				((x) << 26)
9634 #define   MG_PLL_SSC_STEPLENGTH(x)			((x) << 16)
9635 #define   MG_PLL_SSC_STEPNUM(x)				((x) << 10)
9636 #define   MG_PLL_SSC_FLLEN				(1 << 9)
9637 #define   MG_PLL_SSC_STEPSIZE(x)			((x) << 0)
9638 #define MG_PLL_SSC(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_SSC_PORT1, \
9639 				    _MG_PLL_SSC_PORT2)
9640 
9641 #define _MG_PLL_BIAS_PORT1				0x168A14
9642 #define _MG_PLL_BIAS_PORT2				0x169A14
9643 #define _MG_PLL_BIAS_PORT3				0x16AA14
9644 #define _MG_PLL_BIAS_PORT4				0x16BA14
9645 #define   MG_PLL_BIAS_BIAS_GB_SEL(x)			((x) << 30)
9646 #define   MG_PLL_BIAS_BIAS_GB_SEL_MASK			(0x3 << 30)
9647 #define   MG_PLL_BIAS_INIT_DCOAMP(x)			((x) << 24)
9648 #define   MG_PLL_BIAS_INIT_DCOAMP_MASK			(0x3f << 24)
9649 #define   MG_PLL_BIAS_BIAS_BONUS(x)			((x) << 16)
9650 #define   MG_PLL_BIAS_BIAS_BONUS_MASK			(0xff << 16)
9651 #define   MG_PLL_BIAS_BIASCAL_EN			(1 << 15)
9652 #define   MG_PLL_BIAS_CTRIM(x)				((x) << 8)
9653 #define   MG_PLL_BIAS_CTRIM_MASK			(0x1f << 8)
9654 #define   MG_PLL_BIAS_VREF_RDAC(x)			((x) << 5)
9655 #define   MG_PLL_BIAS_VREF_RDAC_MASK			(0x7 << 5)
9656 #define   MG_PLL_BIAS_IREFTRIM(x)			((x) << 0)
9657 #define   MG_PLL_BIAS_IREFTRIM_MASK			(0x1f << 0)
9658 #define MG_PLL_BIAS(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_BIAS_PORT1, \
9659 				     _MG_PLL_BIAS_PORT2)
9660 
9661 #define _MG_PLL_TDC_COLDST_BIAS_PORT1			0x168A18
9662 #define _MG_PLL_TDC_COLDST_BIAS_PORT2			0x169A18
9663 #define _MG_PLL_TDC_COLDST_BIAS_PORT3			0x16AA18
9664 #define _MG_PLL_TDC_COLDST_BIAS_PORT4			0x16BA18
9665 #define   MG_PLL_TDC_COLDST_IREFINT_EN			(1 << 27)
9666 #define   MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(x)	((x) << 17)
9667 #define   MG_PLL_TDC_COLDST_COLDSTART			(1 << 16)
9668 #define   MG_PLL_TDC_TDCOVCCORR_EN			(1 << 2)
9669 #define   MG_PLL_TDC_TDCSEL(x)				((x) << 0)
9670 #define MG_PLL_TDC_COLDST_BIAS(port) _MMIO_PORT((port) - PORT_C, \
9671 						_MG_PLL_TDC_COLDST_BIAS_PORT1, \
9672 						_MG_PLL_TDC_COLDST_BIAS_PORT2)
9673 
9674 #define _CNL_DPLL0_CFGCR0		0x6C000
9675 #define _CNL_DPLL1_CFGCR0		0x6C080
9676 #define  DPLL_CFGCR0_HDMI_MODE		(1 << 30)
9677 #define  DPLL_CFGCR0_SSC_ENABLE		(1 << 29)
9678 #define  DPLL_CFGCR0_SSC_ENABLE_ICL	(1 << 25)
9679 #define  DPLL_CFGCR0_LINK_RATE_MASK	(0xf << 25)
9680 #define  DPLL_CFGCR0_LINK_RATE_2700	(0 << 25)
9681 #define  DPLL_CFGCR0_LINK_RATE_1350	(1 << 25)
9682 #define  DPLL_CFGCR0_LINK_RATE_810	(2 << 25)
9683 #define  DPLL_CFGCR0_LINK_RATE_1620	(3 << 25)
9684 #define  DPLL_CFGCR0_LINK_RATE_1080	(4 << 25)
9685 #define  DPLL_CFGCR0_LINK_RATE_2160	(5 << 25)
9686 #define  DPLL_CFGCR0_LINK_RATE_3240	(6 << 25)
9687 #define  DPLL_CFGCR0_LINK_RATE_4050	(7 << 25)
9688 #define  DPLL_CFGCR0_DCO_FRACTION_MASK	(0x7fff << 10)
9689 #define  DPLL_CFGCR0_DCO_FRACTION_SHIFT	(10)
9690 #define  DPLL_CFGCR0_DCO_FRACTION(x)	((x) << 10)
9691 #define  DPLL_CFGCR0_DCO_INTEGER_MASK	(0x3ff)
9692 #define CNL_DPLL_CFGCR0(pll)		_MMIO_PLL(pll, _CNL_DPLL0_CFGCR0, _CNL_DPLL1_CFGCR0)
9693 
9694 #define _CNL_DPLL0_CFGCR1		0x6C004
9695 #define _CNL_DPLL1_CFGCR1		0x6C084
9696 #define  DPLL_CFGCR1_QDIV_RATIO_MASK	(0xff << 10)
9697 #define  DPLL_CFGCR1_QDIV_RATIO_SHIFT	(10)
9698 #define  DPLL_CFGCR1_QDIV_RATIO(x)	((x) << 10)
9699 #define  DPLL_CFGCR1_QDIV_MODE_SHIFT	(9)
9700 #define  DPLL_CFGCR1_QDIV_MODE(x)	((x) << 9)
9701 #define  DPLL_CFGCR1_KDIV_MASK		(7 << 6)
9702 #define  DPLL_CFGCR1_KDIV_SHIFT		(6)
9703 #define  DPLL_CFGCR1_KDIV(x)		((x) << 6)
9704 #define  DPLL_CFGCR1_KDIV_1		(1 << 6)
9705 #define  DPLL_CFGCR1_KDIV_2		(2 << 6)
9706 #define  DPLL_CFGCR1_KDIV_4		(4 << 6)
9707 #define  DPLL_CFGCR1_PDIV_MASK		(0xf << 2)
9708 #define  DPLL_CFGCR1_PDIV_SHIFT		(2)
9709 #define  DPLL_CFGCR1_PDIV(x)		((x) << 2)
9710 #define  DPLL_CFGCR1_PDIV_2		(1 << 2)
9711 #define  DPLL_CFGCR1_PDIV_3		(2 << 2)
9712 #define  DPLL_CFGCR1_PDIV_5		(4 << 2)
9713 #define  DPLL_CFGCR1_PDIV_7		(8 << 2)
9714 #define  DPLL_CFGCR1_CENTRAL_FREQ	(3 << 0)
9715 #define  DPLL_CFGCR1_CENTRAL_FREQ_8400	(3 << 0)
9716 #define CNL_DPLL_CFGCR1(pll)		_MMIO_PLL(pll, _CNL_DPLL0_CFGCR1, _CNL_DPLL1_CFGCR1)
9717 
9718 #define _ICL_DPLL0_CFGCR0		0x164000
9719 #define _ICL_DPLL1_CFGCR0		0x164080
9720 #define ICL_DPLL_CFGCR0(pll)		_MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \
9721 						  _ICL_DPLL1_CFGCR0)
9722 
9723 #define _ICL_DPLL0_CFGCR1		0x164004
9724 #define _ICL_DPLL1_CFGCR1		0x164084
9725 #define ICL_DPLL_CFGCR1(pll)		_MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
9726 						  _ICL_DPLL1_CFGCR1)
9727 
9728 /* BXT display engine PLL */
9729 #define BXT_DE_PLL_CTL			_MMIO(0x6d000)
9730 #define   BXT_DE_PLL_RATIO(x)		(x)	/* {60,65,100} * 19.2MHz */
9731 #define   BXT_DE_PLL_RATIO_MASK		0xff
9732 
9733 #define BXT_DE_PLL_ENABLE		_MMIO(0x46070)
9734 #define   BXT_DE_PLL_PLL_ENABLE		(1 << 31)
9735 #define   BXT_DE_PLL_LOCK		(1 << 30)
9736 #define   CNL_CDCLK_PLL_RATIO(x)	(x)
9737 #define   CNL_CDCLK_PLL_RATIO_MASK	0xff
9738 
9739 /* GEN9 DC */
9740 #define DC_STATE_EN			_MMIO(0x45504)
9741 #define  DC_STATE_DISABLE		0
9742 #define  DC_STATE_EN_UPTO_DC5		(1 << 0)
9743 #define  DC_STATE_EN_DC9		(1 << 3)
9744 #define  DC_STATE_EN_UPTO_DC6		(2 << 0)
9745 #define  DC_STATE_EN_UPTO_DC5_DC6_MASK   0x3
9746 
9747 #define  DC_STATE_DEBUG                  _MMIO(0x45520)
9748 #define  DC_STATE_DEBUG_MASK_CORES	(1 << 0)
9749 #define  DC_STATE_DEBUG_MASK_MEMORY_UP	(1 << 1)
9750 
9751 #define BXT_P_CR_MC_BIOS_REQ_0_0_0	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7114)
9752 #define  BXT_REQ_DATA_MASK			0x3F
9753 #define  BXT_DRAM_CHANNEL_ACTIVE_SHIFT		12
9754 #define  BXT_DRAM_CHANNEL_ACTIVE_MASK		(0xF << 12)
9755 #define  BXT_MEMORY_FREQ_MULTIPLIER_HZ		133333333
9756 
9757 #define BXT_D_CR_DRP0_DUNIT8			0x1000
9758 #define BXT_D_CR_DRP0_DUNIT9			0x1200
9759 #define  BXT_D_CR_DRP0_DUNIT_START		8
9760 #define  BXT_D_CR_DRP0_DUNIT_END		11
9761 #define BXT_D_CR_DRP0_DUNIT(x)	_MMIO(MCHBAR_MIRROR_BASE_SNB + \
9762 				      _PICK_EVEN((x) - 8, BXT_D_CR_DRP0_DUNIT8,\
9763 						 BXT_D_CR_DRP0_DUNIT9))
9764 #define  BXT_DRAM_RANK_MASK			0x3
9765 #define  BXT_DRAM_RANK_SINGLE			0x1
9766 #define  BXT_DRAM_RANK_DUAL			0x3
9767 #define  BXT_DRAM_WIDTH_MASK			(0x3 << 4)
9768 #define  BXT_DRAM_WIDTH_SHIFT			4
9769 #define  BXT_DRAM_WIDTH_X8			(0x0 << 4)
9770 #define  BXT_DRAM_WIDTH_X16			(0x1 << 4)
9771 #define  BXT_DRAM_WIDTH_X32			(0x2 << 4)
9772 #define  BXT_DRAM_WIDTH_X64			(0x3 << 4)
9773 #define  BXT_DRAM_SIZE_MASK			(0x7 << 6)
9774 #define  BXT_DRAM_SIZE_SHIFT			6
9775 #define  BXT_DRAM_SIZE_4GB			(0x0 << 6)
9776 #define  BXT_DRAM_SIZE_6GB			(0x1 << 6)
9777 #define  BXT_DRAM_SIZE_8GB			(0x2 << 6)
9778 #define  BXT_DRAM_SIZE_12GB			(0x3 << 6)
9779 #define  BXT_DRAM_SIZE_16GB			(0x4 << 6)
9780 
9781 #define SKL_MEMORY_FREQ_MULTIPLIER_HZ		266666666
9782 #define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5E04)
9783 #define  SKL_REQ_DATA_MASK			(0xF << 0)
9784 
9785 #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
9786 #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
9787 #define  SKL_DRAM_S_SHIFT			16
9788 #define  SKL_DRAM_SIZE_MASK			0x3F
9789 #define  SKL_DRAM_WIDTH_MASK			(0x3 << 8)
9790 #define  SKL_DRAM_WIDTH_SHIFT			8
9791 #define  SKL_DRAM_WIDTH_X8			(0x0 << 8)
9792 #define  SKL_DRAM_WIDTH_X16			(0x1 << 8)
9793 #define  SKL_DRAM_WIDTH_X32			(0x2 << 8)
9794 #define  SKL_DRAM_RANK_MASK			(0x1 << 10)
9795 #define  SKL_DRAM_RANK_SHIFT			10
9796 #define  SKL_DRAM_RANK_SINGLE			(0x0 << 10)
9797 #define  SKL_DRAM_RANK_DUAL			(0x1 << 10)
9798 
9799 /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
9800  * since on HSW we can't write to it using I915_WRITE. */
9801 #define D_COMP_HSW			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
9802 #define D_COMP_BDW			_MMIO(0x138144)
9803 #define  D_COMP_RCOMP_IN_PROGRESS	(1 << 9)
9804 #define  D_COMP_COMP_FORCE		(1 << 8)
9805 #define  D_COMP_COMP_DISABLE		(1 << 0)
9806 
9807 /* Pipe WM_LINETIME - watermark line time */
9808 #define _PIPE_WM_LINETIME_A		0x45270
9809 #define _PIPE_WM_LINETIME_B		0x45274
9810 #define PIPE_WM_LINETIME(pipe) _MMIO_PIPE(pipe, _PIPE_WM_LINETIME_A, _PIPE_WM_LINETIME_B)
9811 #define   PIPE_WM_LINETIME_MASK			(0x1ff)
9812 #define   PIPE_WM_LINETIME_TIME(x)		((x))
9813 #define   PIPE_WM_LINETIME_IPS_LINETIME_MASK	(0x1ff << 16)
9814 #define   PIPE_WM_LINETIME_IPS_LINETIME(x)	((x) << 16)
9815 
9816 /* SFUSE_STRAP */
9817 #define SFUSE_STRAP			_MMIO(0xc2014)
9818 #define  SFUSE_STRAP_FUSE_LOCK		(1 << 13)
9819 #define  SFUSE_STRAP_RAW_FREQUENCY	(1 << 8)
9820 #define  SFUSE_STRAP_DISPLAY_DISABLED	(1 << 7)
9821 #define  SFUSE_STRAP_CRT_DISABLED	(1 << 6)
9822 #define  SFUSE_STRAP_DDIF_DETECTED	(1 << 3)
9823 #define  SFUSE_STRAP_DDIB_DETECTED	(1 << 2)
9824 #define  SFUSE_STRAP_DDIC_DETECTED	(1 << 1)
9825 #define  SFUSE_STRAP_DDID_DETECTED	(1 << 0)
9826 
9827 #define WM_MISC				_MMIO(0x45260)
9828 #define  WM_MISC_DATA_PARTITION_5_6	(1 << 0)
9829 
9830 #define WM_DBG				_MMIO(0x45280)
9831 #define  WM_DBG_DISALLOW_MULTIPLE_LP	(1 << 0)
9832 #define  WM_DBG_DISALLOW_MAXFIFO	(1 << 1)
9833 #define  WM_DBG_DISALLOW_SPRITE		(1 << 2)
9834 
9835 /* pipe CSC */
9836 #define _PIPE_A_CSC_COEFF_RY_GY	0x49010
9837 #define _PIPE_A_CSC_COEFF_BY	0x49014
9838 #define _PIPE_A_CSC_COEFF_RU_GU	0x49018
9839 #define _PIPE_A_CSC_COEFF_BU	0x4901c
9840 #define _PIPE_A_CSC_COEFF_RV_GV	0x49020
9841 #define _PIPE_A_CSC_COEFF_BV	0x49024
9842 #define _PIPE_A_CSC_MODE	0x49028
9843 #define   CSC_BLACK_SCREEN_OFFSET	(1 << 2)
9844 #define   CSC_POSITION_BEFORE_GAMMA	(1 << 1)
9845 #define   CSC_MODE_YUV_TO_RGB		(1 << 0)
9846 #define _PIPE_A_CSC_PREOFF_HI	0x49030
9847 #define _PIPE_A_CSC_PREOFF_ME	0x49034
9848 #define _PIPE_A_CSC_PREOFF_LO	0x49038
9849 #define _PIPE_A_CSC_POSTOFF_HI	0x49040
9850 #define _PIPE_A_CSC_POSTOFF_ME	0x49044
9851 #define _PIPE_A_CSC_POSTOFF_LO	0x49048
9852 
9853 #define _PIPE_B_CSC_COEFF_RY_GY	0x49110
9854 #define _PIPE_B_CSC_COEFF_BY	0x49114
9855 #define _PIPE_B_CSC_COEFF_RU_GU	0x49118
9856 #define _PIPE_B_CSC_COEFF_BU	0x4911c
9857 #define _PIPE_B_CSC_COEFF_RV_GV	0x49120
9858 #define _PIPE_B_CSC_COEFF_BV	0x49124
9859 #define _PIPE_B_CSC_MODE	0x49128
9860 #define _PIPE_B_CSC_PREOFF_HI	0x49130
9861 #define _PIPE_B_CSC_PREOFF_ME	0x49134
9862 #define _PIPE_B_CSC_PREOFF_LO	0x49138
9863 #define _PIPE_B_CSC_POSTOFF_HI	0x49140
9864 #define _PIPE_B_CSC_POSTOFF_ME	0x49144
9865 #define _PIPE_B_CSC_POSTOFF_LO	0x49148
9866 
9867 #define PIPE_CSC_COEFF_RY_GY(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
9868 #define PIPE_CSC_COEFF_BY(pipe)		_MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
9869 #define PIPE_CSC_COEFF_RU_GU(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
9870 #define PIPE_CSC_COEFF_BU(pipe)		_MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
9871 #define PIPE_CSC_COEFF_RV_GV(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
9872 #define PIPE_CSC_COEFF_BV(pipe)		_MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
9873 #define PIPE_CSC_MODE(pipe)		_MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
9874 #define PIPE_CSC_PREOFF_HI(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
9875 #define PIPE_CSC_PREOFF_ME(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
9876 #define PIPE_CSC_PREOFF_LO(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
9877 #define PIPE_CSC_POSTOFF_HI(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
9878 #define PIPE_CSC_POSTOFF_ME(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
9879 #define PIPE_CSC_POSTOFF_LO(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
9880 
9881 /* pipe degamma/gamma LUTs on IVB+ */
9882 #define _PAL_PREC_INDEX_A	0x4A400
9883 #define _PAL_PREC_INDEX_B	0x4AC00
9884 #define _PAL_PREC_INDEX_C	0x4B400
9885 #define   PAL_PREC_10_12_BIT		(0 << 31)
9886 #define   PAL_PREC_SPLIT_MODE		(1 << 31)
9887 #define   PAL_PREC_AUTO_INCREMENT	(1 << 15)
9888 #define   PAL_PREC_INDEX_VALUE_MASK	(0x3ff << 0)
9889 #define _PAL_PREC_DATA_A	0x4A404
9890 #define _PAL_PREC_DATA_B	0x4AC04
9891 #define _PAL_PREC_DATA_C	0x4B404
9892 #define _PAL_PREC_GC_MAX_A	0x4A410
9893 #define _PAL_PREC_GC_MAX_B	0x4AC10
9894 #define _PAL_PREC_GC_MAX_C	0x4B410
9895 #define _PAL_PREC_EXT_GC_MAX_A	0x4A420
9896 #define _PAL_PREC_EXT_GC_MAX_B	0x4AC20
9897 #define _PAL_PREC_EXT_GC_MAX_C	0x4B420
9898 #define _PAL_PREC_EXT2_GC_MAX_A	0x4A430
9899 #define _PAL_PREC_EXT2_GC_MAX_B	0x4AC30
9900 #define _PAL_PREC_EXT2_GC_MAX_C	0x4B430
9901 
9902 #define PREC_PAL_INDEX(pipe)		_MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B)
9903 #define PREC_PAL_DATA(pipe)		_MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
9904 #define PREC_PAL_GC_MAX(pipe, i)	_MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)
9905 #define PREC_PAL_EXT_GC_MAX(pipe, i)	_MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
9906 
9907 #define _PRE_CSC_GAMC_INDEX_A	0x4A484
9908 #define _PRE_CSC_GAMC_INDEX_B	0x4AC84
9909 #define _PRE_CSC_GAMC_INDEX_C	0x4B484
9910 #define   PRE_CSC_GAMC_AUTO_INCREMENT	(1 << 10)
9911 #define _PRE_CSC_GAMC_DATA_A	0x4A488
9912 #define _PRE_CSC_GAMC_DATA_B	0x4AC88
9913 #define _PRE_CSC_GAMC_DATA_C	0x4B488
9914 
9915 #define PRE_CSC_GAMC_INDEX(pipe)	_MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B)
9916 #define PRE_CSC_GAMC_DATA(pipe)		_MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
9917 
9918 /* pipe CSC & degamma/gamma LUTs on CHV */
9919 #define _CGM_PIPE_A_CSC_COEFF01	(VLV_DISPLAY_BASE + 0x67900)
9920 #define _CGM_PIPE_A_CSC_COEFF23	(VLV_DISPLAY_BASE + 0x67904)
9921 #define _CGM_PIPE_A_CSC_COEFF45	(VLV_DISPLAY_BASE + 0x67908)
9922 #define _CGM_PIPE_A_CSC_COEFF67	(VLV_DISPLAY_BASE + 0x6790C)
9923 #define _CGM_PIPE_A_CSC_COEFF8	(VLV_DISPLAY_BASE + 0x67910)
9924 #define _CGM_PIPE_A_DEGAMMA	(VLV_DISPLAY_BASE + 0x66000)
9925 #define _CGM_PIPE_A_GAMMA	(VLV_DISPLAY_BASE + 0x67000)
9926 #define _CGM_PIPE_A_MODE	(VLV_DISPLAY_BASE + 0x67A00)
9927 #define   CGM_PIPE_MODE_GAMMA	(1 << 2)
9928 #define   CGM_PIPE_MODE_CSC	(1 << 1)
9929 #define   CGM_PIPE_MODE_DEGAMMA	(1 << 0)
9930 
9931 #define _CGM_PIPE_B_CSC_COEFF01	(VLV_DISPLAY_BASE + 0x69900)
9932 #define _CGM_PIPE_B_CSC_COEFF23	(VLV_DISPLAY_BASE + 0x69904)
9933 #define _CGM_PIPE_B_CSC_COEFF45	(VLV_DISPLAY_BASE + 0x69908)
9934 #define _CGM_PIPE_B_CSC_COEFF67	(VLV_DISPLAY_BASE + 0x6990C)
9935 #define _CGM_PIPE_B_CSC_COEFF8	(VLV_DISPLAY_BASE + 0x69910)
9936 #define _CGM_PIPE_B_DEGAMMA	(VLV_DISPLAY_BASE + 0x68000)
9937 #define _CGM_PIPE_B_GAMMA	(VLV_DISPLAY_BASE + 0x69000)
9938 #define _CGM_PIPE_B_MODE	(VLV_DISPLAY_BASE + 0x69A00)
9939 
9940 #define CGM_PIPE_CSC_COEFF01(pipe)	_MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01)
9941 #define CGM_PIPE_CSC_COEFF23(pipe)	_MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23)
9942 #define CGM_PIPE_CSC_COEFF45(pipe)	_MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45)
9943 #define CGM_PIPE_CSC_COEFF67(pipe)	_MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67)
9944 #define CGM_PIPE_CSC_COEFF8(pipe)	_MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8)
9945 #define CGM_PIPE_DEGAMMA(pipe, i, w)	_MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4)
9946 #define CGM_PIPE_GAMMA(pipe, i, w)	_MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4)
9947 #define CGM_PIPE_MODE(pipe)		_MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE)
9948 
9949 /* MIPI DSI registers */
9950 
9951 #define _MIPI_PORT(port, a, c)	(((port) == PORT_A) ? a : c)	/* ports A and C only */
9952 #define _MMIO_MIPI(port, a, c)	_MMIO(_MIPI_PORT(port, a, c))
9953 
9954 /* Gen11 DSI */
9955 #define _MMIO_DSI(tc, dsi0, dsi1)	_MMIO_TRANS((tc) - TRANSCODER_DSI_0, \
9956 						    dsi0, dsi1)
9957 
9958 #define MIPIO_TXESC_CLK_DIV1			_MMIO(0x160004)
9959 #define  GLK_TX_ESC_CLK_DIV1_MASK			0x3FF
9960 #define MIPIO_TXESC_CLK_DIV2			_MMIO(0x160008)
9961 #define  GLK_TX_ESC_CLK_DIV2_MASK			0x3FF
9962 
9963 #define _ICL_DSI_ESC_CLK_DIV0		0x6b090
9964 #define _ICL_DSI_ESC_CLK_DIV1		0x6b890
9965 #define ICL_DSI_ESC_CLK_DIV(port)	_MMIO_PORT((port),	\
9966 							_ICL_DSI_ESC_CLK_DIV0, \
9967 							_ICL_DSI_ESC_CLK_DIV1)
9968 #define _ICL_DPHY_ESC_CLK_DIV0		0x162190
9969 #define _ICL_DPHY_ESC_CLK_DIV1		0x6C190
9970 #define ICL_DPHY_ESC_CLK_DIV(port)	_MMIO_PORT((port),	\
9971 						_ICL_DPHY_ESC_CLK_DIV0, \
9972 						_ICL_DPHY_ESC_CLK_DIV1)
9973 #define  ICL_BYTE_CLK_PER_ESC_CLK_MASK		(0x1f << 16)
9974 #define  ICL_BYTE_CLK_PER_ESC_CLK_SHIFT	16
9975 #define  ICL_ESC_CLK_DIV_MASK			0x1ff
9976 #define  ICL_ESC_CLK_DIV_SHIFT			0
9977 #define DSI_MAX_ESC_CLK			20000		/* in KHz */
9978 
9979 /* Gen4+ Timestamp and Pipe Frame time stamp registers */
9980 #define GEN4_TIMESTAMP		_MMIO(0x2358)
9981 #define ILK_TIMESTAMP_HI	_MMIO(0x70070)
9982 #define IVB_TIMESTAMP_CTR	_MMIO(0x44070)
9983 
9984 #define GEN9_TIMESTAMP_OVERRIDE				_MMIO(0x44074)
9985 #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT	0
9986 #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK	0x3ff
9987 #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT	12
9988 #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK	(0xf << 12)
9989 
9990 #define _PIPE_FRMTMSTMP_A		0x70048
9991 #define PIPE_FRMTMSTMP(pipe)		\
9992 			_MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A)
9993 
9994 /* BXT MIPI clock controls */
9995 #define BXT_MAX_VAR_OUTPUT_KHZ			39500
9996 
9997 #define BXT_MIPI_CLOCK_CTL			_MMIO(0x46090)
9998 #define  BXT_MIPI1_DIV_SHIFT			26
9999 #define  BXT_MIPI2_DIV_SHIFT			10
10000 #define  BXT_MIPI_DIV_SHIFT(port)		\
10001 			_MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
10002 					BXT_MIPI2_DIV_SHIFT)
10003 
10004 /* TX control divider to select actual TX clock output from (8x/var) */
10005 #define  BXT_MIPI1_TX_ESCLK_SHIFT		26
10006 #define  BXT_MIPI2_TX_ESCLK_SHIFT		10
10007 #define  BXT_MIPI_TX_ESCLK_SHIFT(port)		\
10008 			_MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
10009 					BXT_MIPI2_TX_ESCLK_SHIFT)
10010 #define  BXT_MIPI1_TX_ESCLK_FIXDIV_MASK		(0x3F << 26)
10011 #define  BXT_MIPI2_TX_ESCLK_FIXDIV_MASK		(0x3F << 10)
10012 #define  BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)	\
10013 			_MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
10014 					BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
10015 #define  BXT_MIPI_TX_ESCLK_DIVIDER(port, val)	\
10016 		(((val) & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port))
10017 /* RX upper control divider to select actual RX clock output from 8x */
10018 #define  BXT_MIPI1_RX_ESCLK_UPPER_SHIFT		21
10019 #define  BXT_MIPI2_RX_ESCLK_UPPER_SHIFT		5
10020 #define  BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port)		\
10021 			_MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \
10022 					BXT_MIPI2_RX_ESCLK_UPPER_SHIFT)
10023 #define  BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK		(3 << 21)
10024 #define  BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK		(3 << 5)
10025 #define  BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port)	\
10026 			_MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK, \
10027 					BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK)
10028 #define  BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val)	\
10029 		(((val) & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port))
10030 /* 8/3X divider to select the actual 8/3X clock output from 8x */
10031 #define  BXT_MIPI1_8X_BY3_SHIFT                19
10032 #define  BXT_MIPI2_8X_BY3_SHIFT                3
10033 #define  BXT_MIPI_8X_BY3_SHIFT(port)          \
10034 			_MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \
10035 					BXT_MIPI2_8X_BY3_SHIFT)
10036 #define  BXT_MIPI1_8X_BY3_DIVIDER_MASK         (3 << 19)
10037 #define  BXT_MIPI2_8X_BY3_DIVIDER_MASK         (3 << 3)
10038 #define  BXT_MIPI_8X_BY3_DIVIDER_MASK(port)    \
10039 			_MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \
10040 						BXT_MIPI2_8X_BY3_DIVIDER_MASK)
10041 #define  BXT_MIPI_8X_BY3_DIVIDER(port, val)    \
10042 			(((val) & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
10043 /* RX lower control divider to select actual RX clock output from 8x */
10044 #define  BXT_MIPI1_RX_ESCLK_LOWER_SHIFT		16
10045 #define  BXT_MIPI2_RX_ESCLK_LOWER_SHIFT		0
10046 #define  BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port)		\
10047 			_MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \
10048 					BXT_MIPI2_RX_ESCLK_LOWER_SHIFT)
10049 #define  BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK		(3 << 16)
10050 #define  BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK		(3 << 0)
10051 #define  BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port)	\
10052 			_MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \
10053 					BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK)
10054 #define  BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val)	\
10055 		(((val) & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port))
10056 
10057 #define RX_DIVIDER_BIT_1_2                     0x3
10058 #define RX_DIVIDER_BIT_3_4                     0xC
10059 
10060 /* BXT MIPI mode configure */
10061 #define  _BXT_MIPIA_TRANS_HACTIVE			0x6B0F8
10062 #define  _BXT_MIPIC_TRANS_HACTIVE			0x6B8F8
10063 #define  BXT_MIPI_TRANS_HACTIVE(tc)	_MMIO_MIPI(tc, \
10064 		_BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)
10065 
10066 #define  _BXT_MIPIA_TRANS_VACTIVE			0x6B0FC
10067 #define  _BXT_MIPIC_TRANS_VACTIVE			0x6B8FC
10068 #define  BXT_MIPI_TRANS_VACTIVE(tc)	_MMIO_MIPI(tc, \
10069 		_BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)
10070 
10071 #define  _BXT_MIPIA_TRANS_VTOTAL			0x6B100
10072 #define  _BXT_MIPIC_TRANS_VTOTAL			0x6B900
10073 #define  BXT_MIPI_TRANS_VTOTAL(tc)	_MMIO_MIPI(tc, \
10074 		_BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)
10075 
10076 #define BXT_DSI_PLL_CTL			_MMIO(0x161000)
10077 #define  BXT_DSI_PLL_PVD_RATIO_SHIFT	16
10078 #define  BXT_DSI_PLL_PVD_RATIO_MASK	(3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
10079 #define  BXT_DSI_PLL_PVD_RATIO_1	(1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
10080 #define  BXT_DSIC_16X_BY1		(0 << 10)
10081 #define  BXT_DSIC_16X_BY2		(1 << 10)
10082 #define  BXT_DSIC_16X_BY3		(2 << 10)
10083 #define  BXT_DSIC_16X_BY4		(3 << 10)
10084 #define  BXT_DSIC_16X_MASK		(3 << 10)
10085 #define  BXT_DSIA_16X_BY1		(0 << 8)
10086 #define  BXT_DSIA_16X_BY2		(1 << 8)
10087 #define  BXT_DSIA_16X_BY3		(2 << 8)
10088 #define  BXT_DSIA_16X_BY4		(3 << 8)
10089 #define  BXT_DSIA_16X_MASK		(3 << 8)
10090 #define  BXT_DSI_FREQ_SEL_SHIFT		8
10091 #define  BXT_DSI_FREQ_SEL_MASK		(0xF << BXT_DSI_FREQ_SEL_SHIFT)
10092 
10093 #define BXT_DSI_PLL_RATIO_MAX		0x7D
10094 #define BXT_DSI_PLL_RATIO_MIN		0x22
10095 #define GLK_DSI_PLL_RATIO_MAX		0x6F
10096 #define GLK_DSI_PLL_RATIO_MIN		0x22
10097 #define BXT_DSI_PLL_RATIO_MASK		0xFF
10098 #define BXT_REF_CLOCK_KHZ		19200
10099 
10100 #define BXT_DSI_PLL_ENABLE		_MMIO(0x46080)
10101 #define  BXT_DSI_PLL_DO_ENABLE		(1 << 31)
10102 #define  BXT_DSI_PLL_LOCKED		(1 << 30)
10103 
10104 #define _MIPIA_PORT_CTRL			(VLV_DISPLAY_BASE + 0x61190)
10105 #define _MIPIC_PORT_CTRL			(VLV_DISPLAY_BASE + 0x61700)
10106 #define MIPI_PORT_CTRL(port)	_MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
10107 
10108  /* BXT port control */
10109 #define _BXT_MIPIA_PORT_CTRL				0x6B0C0
10110 #define _BXT_MIPIC_PORT_CTRL				0x6B8C0
10111 #define BXT_MIPI_PORT_CTRL(tc)	_MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL)
10112 
10113 /* ICL DSI MODE control */
10114 #define _ICL_DSI_IO_MODECTL_0				0x6B094
10115 #define _ICL_DSI_IO_MODECTL_1				0x6B894
10116 #define ICL_DSI_IO_MODECTL(port)	_MMIO_PORT(port,	\
10117 						    _ICL_DSI_IO_MODECTL_0, \
10118 						    _ICL_DSI_IO_MODECTL_1)
10119 #define  COMBO_PHY_MODE_DSI				(1 << 0)
10120 
10121 /* Display Stream Splitter Control */
10122 #define DSS_CTL1				_MMIO(0x67400)
10123 #define  SPLITTER_ENABLE			(1 << 31)
10124 #define  JOINER_ENABLE				(1 << 30)
10125 #define  DUAL_LINK_MODE_INTERLEAVE		(1 << 24)
10126 #define  DUAL_LINK_MODE_FRONTBACK		(0 << 24)
10127 #define  OVERLAP_PIXELS_MASK			(0xf << 16)
10128 #define  OVERLAP_PIXELS(pixels)			((pixels) << 16)
10129 #define  LEFT_DL_BUF_TARGET_DEPTH_MASK		(0xfff << 0)
10130 #define  LEFT_DL_BUF_TARGET_DEPTH(pixels)	((pixels) << 0)
10131 #define  MAX_DL_BUFFER_TARGET_DEPTH		0x5a0
10132 
10133 #define DSS_CTL2				_MMIO(0x67404)
10134 #define  LEFT_BRANCH_VDSC_ENABLE		(1 << 31)
10135 #define  RIGHT_BRANCH_VDSC_ENABLE		(1 << 15)
10136 #define  RIGHT_DL_BUF_TARGET_DEPTH_MASK		(0xfff << 0)
10137 #define  RIGHT_DL_BUF_TARGET_DEPTH(pixels)	((pixels) << 0)
10138 
10139 #define _ICL_PIPE_DSS_CTL1_PB			0x78200
10140 #define _ICL_PIPE_DSS_CTL1_PC			0x78400
10141 #define ICL_PIPE_DSS_CTL1(pipe)			_MMIO_PIPE((pipe) - PIPE_B, \
10142 							   _ICL_PIPE_DSS_CTL1_PB, \
10143 							   _ICL_PIPE_DSS_CTL1_PC)
10144 #define  BIG_JOINER_ENABLE			(1 << 29)
10145 #define  MASTER_BIG_JOINER_ENABLE		(1 << 28)
10146 #define  VGA_CENTERING_ENABLE			(1 << 27)
10147 
10148 #define _ICL_PIPE_DSS_CTL2_PB			0x78204
10149 #define _ICL_PIPE_DSS_CTL2_PC			0x78404
10150 #define ICL_PIPE_DSS_CTL2(pipe)			_MMIO_PIPE((pipe) - PIPE_B, \
10151 							   _ICL_PIPE_DSS_CTL2_PB, \
10152 							   _ICL_PIPE_DSS_CTL2_PC)
10153 
10154 #define BXT_P_DSI_REGULATOR_CFG			_MMIO(0x160020)
10155 #define  STAP_SELECT					(1 << 0)
10156 
10157 #define BXT_P_DSI_REGULATOR_TX_CTRL		_MMIO(0x160054)
10158 #define  HS_IO_CTRL_SELECT				(1 << 0)
10159 
10160 #define  DPI_ENABLE					(1 << 31) /* A + C */
10161 #define  MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT		27
10162 #define  MIPIA_MIPI4DPHY_DELAY_COUNT_MASK		(0xf << 27)
10163 #define  DUAL_LINK_MODE_SHIFT				26
10164 #define  DUAL_LINK_MODE_MASK				(1 << 26)
10165 #define  DUAL_LINK_MODE_FRONT_BACK			(0 << 26)
10166 #define  DUAL_LINK_MODE_PIXEL_ALTERNATIVE		(1 << 26)
10167 #define  DITHERING_ENABLE				(1 << 25) /* A + C */
10168 #define  FLOPPED_HSTX					(1 << 23)
10169 #define  DE_INVERT					(1 << 19) /* XXX */
10170 #define  MIPIA_FLISDSI_DELAY_COUNT_SHIFT		18
10171 #define  MIPIA_FLISDSI_DELAY_COUNT_MASK			(0xf << 18)
10172 #define  AFE_LATCHOUT					(1 << 17)
10173 #define  LP_OUTPUT_HOLD					(1 << 16)
10174 #define  MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT		15
10175 #define  MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK		(1 << 15)
10176 #define  MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT		11
10177 #define  MIPIC_MIPI4DPHY_DELAY_COUNT_MASK		(0xf << 11)
10178 #define  CSB_SHIFT					9
10179 #define  CSB_MASK					(3 << 9)
10180 #define  CSB_20MHZ					(0 << 9)
10181 #define  CSB_10MHZ					(1 << 9)
10182 #define  CSB_40MHZ					(2 << 9)
10183 #define  BANDGAP_MASK					(1 << 8)
10184 #define  BANDGAP_PNW_CIRCUIT				(0 << 8)
10185 #define  BANDGAP_LNC_CIRCUIT				(1 << 8)
10186 #define  MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT		5
10187 #define  MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK		(7 << 5)
10188 #define  TEARING_EFFECT_DELAY				(1 << 4) /* A + C */
10189 #define  TEARING_EFFECT_SHIFT				2 /* A + C */
10190 #define  TEARING_EFFECT_MASK				(3 << 2)
10191 #define  TEARING_EFFECT_OFF				(0 << 2)
10192 #define  TEARING_EFFECT_DSI				(1 << 2)
10193 #define  TEARING_EFFECT_GPIO				(2 << 2)
10194 #define  LANE_CONFIGURATION_SHIFT			0
10195 #define  LANE_CONFIGURATION_MASK			(3 << 0)
10196 #define  LANE_CONFIGURATION_4LANE			(0 << 0)
10197 #define  LANE_CONFIGURATION_DUAL_LINK_A			(1 << 0)
10198 #define  LANE_CONFIGURATION_DUAL_LINK_B			(2 << 0)
10199 
10200 #define _MIPIA_TEARING_CTRL			(VLV_DISPLAY_BASE + 0x61194)
10201 #define _MIPIC_TEARING_CTRL			(VLV_DISPLAY_BASE + 0x61704)
10202 #define MIPI_TEARING_CTRL(port)			_MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
10203 #define  TEARING_EFFECT_DELAY_SHIFT			0
10204 #define  TEARING_EFFECT_DELAY_MASK			(0xffff << 0)
10205 
10206 /* XXX: all bits reserved */
10207 #define _MIPIA_AUTOPWG			(VLV_DISPLAY_BASE + 0x611a0)
10208 
10209 /* MIPI DSI Controller and D-PHY registers */
10210 
10211 #define _MIPIA_DEVICE_READY		(dev_priv->mipi_mmio_base + 0xb000)
10212 #define _MIPIC_DEVICE_READY		(dev_priv->mipi_mmio_base + 0xb800)
10213 #define MIPI_DEVICE_READY(port)		_MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY)
10214 #define  BUS_POSSESSION					(1 << 3) /* set to give bus to receiver */
10215 #define  ULPS_STATE_MASK				(3 << 1)
10216 #define  ULPS_STATE_ENTER				(2 << 1)
10217 #define  ULPS_STATE_EXIT				(1 << 1)
10218 #define  ULPS_STATE_NORMAL_OPERATION			(0 << 1)
10219 #define  DEVICE_READY					(1 << 0)
10220 
10221 #define _MIPIA_INTR_STAT		(dev_priv->mipi_mmio_base + 0xb004)
10222 #define _MIPIC_INTR_STAT		(dev_priv->mipi_mmio_base + 0xb804)
10223 #define MIPI_INTR_STAT(port)		_MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT)
10224 #define _MIPIA_INTR_EN			(dev_priv->mipi_mmio_base + 0xb008)
10225 #define _MIPIC_INTR_EN			(dev_priv->mipi_mmio_base + 0xb808)
10226 #define MIPI_INTR_EN(port)		_MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN)
10227 #define  TEARING_EFFECT					(1 << 31)
10228 #define  SPL_PKT_SENT_INTERRUPT				(1 << 30)
10229 #define  GEN_READ_DATA_AVAIL				(1 << 29)
10230 #define  LP_GENERIC_WR_FIFO_FULL			(1 << 28)
10231 #define  HS_GENERIC_WR_FIFO_FULL			(1 << 27)
10232 #define  RX_PROT_VIOLATION				(1 << 26)
10233 #define  RX_INVALID_TX_LENGTH				(1 << 25)
10234 #define  ACK_WITH_NO_ERROR				(1 << 24)
10235 #define  TURN_AROUND_ACK_TIMEOUT			(1 << 23)
10236 #define  LP_RX_TIMEOUT					(1 << 22)
10237 #define  HS_TX_TIMEOUT					(1 << 21)
10238 #define  DPI_FIFO_UNDERRUN				(1 << 20)
10239 #define  LOW_CONTENTION					(1 << 19)
10240 #define  HIGH_CONTENTION				(1 << 18)
10241 #define  TXDSI_VC_ID_INVALID				(1 << 17)
10242 #define  TXDSI_DATA_TYPE_NOT_RECOGNISED			(1 << 16)
10243 #define  TXCHECKSUM_ERROR				(1 << 15)
10244 #define  TXECC_MULTIBIT_ERROR				(1 << 14)
10245 #define  TXECC_SINGLE_BIT_ERROR				(1 << 13)
10246 #define  TXFALSE_CONTROL_ERROR				(1 << 12)
10247 #define  RXDSI_VC_ID_INVALID				(1 << 11)
10248 #define  RXDSI_DATA_TYPE_NOT_REGOGNISED			(1 << 10)
10249 #define  RXCHECKSUM_ERROR				(1 << 9)
10250 #define  RXECC_MULTIBIT_ERROR				(1 << 8)
10251 #define  RXECC_SINGLE_BIT_ERROR				(1 << 7)
10252 #define  RXFALSE_CONTROL_ERROR				(1 << 6)
10253 #define  RXHS_RECEIVE_TIMEOUT_ERROR			(1 << 5)
10254 #define  RX_LP_TX_SYNC_ERROR				(1 << 4)
10255 #define  RXEXCAPE_MODE_ENTRY_ERROR			(1 << 3)
10256 #define  RXEOT_SYNC_ERROR				(1 << 2)
10257 #define  RXSOT_SYNC_ERROR				(1 << 1)
10258 #define  RXSOT_ERROR					(1 << 0)
10259 
10260 #define _MIPIA_DSI_FUNC_PRG		(dev_priv->mipi_mmio_base + 0xb00c)
10261 #define _MIPIC_DSI_FUNC_PRG		(dev_priv->mipi_mmio_base + 0xb80c)
10262 #define MIPI_DSI_FUNC_PRG(port)		_MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG)
10263 #define  CMD_MODE_DATA_WIDTH_MASK			(7 << 13)
10264 #define  CMD_MODE_NOT_SUPPORTED				(0 << 13)
10265 #define  CMD_MODE_DATA_WIDTH_16_BIT			(1 << 13)
10266 #define  CMD_MODE_DATA_WIDTH_9_BIT			(2 << 13)
10267 #define  CMD_MODE_DATA_WIDTH_8_BIT			(3 << 13)
10268 #define  CMD_MODE_DATA_WIDTH_OPTION1			(4 << 13)
10269 #define  CMD_MODE_DATA_WIDTH_OPTION2			(5 << 13)
10270 #define  VID_MODE_FORMAT_MASK				(0xf << 7)
10271 #define  VID_MODE_NOT_SUPPORTED				(0 << 7)
10272 #define  VID_MODE_FORMAT_RGB565				(1 << 7)
10273 #define  VID_MODE_FORMAT_RGB666_PACKED			(2 << 7)
10274 #define  VID_MODE_FORMAT_RGB666				(3 << 7)
10275 #define  VID_MODE_FORMAT_RGB888				(4 << 7)
10276 #define  CMD_MODE_CHANNEL_NUMBER_SHIFT			5
10277 #define  CMD_MODE_CHANNEL_NUMBER_MASK			(3 << 5)
10278 #define  VID_MODE_CHANNEL_NUMBER_SHIFT			3
10279 #define  VID_MODE_CHANNEL_NUMBER_MASK			(3 << 3)
10280 #define  DATA_LANES_PRG_REG_SHIFT			0
10281 #define  DATA_LANES_PRG_REG_MASK			(7 << 0)
10282 
10283 #define _MIPIA_HS_TX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb010)
10284 #define _MIPIC_HS_TX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb810)
10285 #define MIPI_HS_TX_TIMEOUT(port)	_MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT)
10286 #define  HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK		0xffffff
10287 
10288 #define _MIPIA_LP_RX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb014)
10289 #define _MIPIC_LP_RX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb814)
10290 #define MIPI_LP_RX_TIMEOUT(port)	_MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT)
10291 #define  LOW_POWER_RX_TIMEOUT_COUNTER_MASK		0xffffff
10292 
10293 #define _MIPIA_TURN_AROUND_TIMEOUT	(dev_priv->mipi_mmio_base + 0xb018)
10294 #define _MIPIC_TURN_AROUND_TIMEOUT	(dev_priv->mipi_mmio_base + 0xb818)
10295 #define MIPI_TURN_AROUND_TIMEOUT(port)	_MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
10296 #define  TURN_AROUND_TIMEOUT_MASK			0x3f
10297 
10298 #define _MIPIA_DEVICE_RESET_TIMER	(dev_priv->mipi_mmio_base + 0xb01c)
10299 #define _MIPIC_DEVICE_RESET_TIMER	(dev_priv->mipi_mmio_base + 0xb81c)
10300 #define MIPI_DEVICE_RESET_TIMER(port)	_MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
10301 #define  DEVICE_RESET_TIMER_MASK			0xffff
10302 
10303 #define _MIPIA_DPI_RESOLUTION		(dev_priv->mipi_mmio_base + 0xb020)
10304 #define _MIPIC_DPI_RESOLUTION		(dev_priv->mipi_mmio_base + 0xb820)
10305 #define MIPI_DPI_RESOLUTION(port)	_MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION)
10306 #define  VERTICAL_ADDRESS_SHIFT				16
10307 #define  VERTICAL_ADDRESS_MASK				(0xffff << 16)
10308 #define  HORIZONTAL_ADDRESS_SHIFT			0
10309 #define  HORIZONTAL_ADDRESS_MASK			0xffff
10310 
10311 #define _MIPIA_DBI_FIFO_THROTTLE	(dev_priv->mipi_mmio_base + 0xb024)
10312 #define _MIPIC_DBI_FIFO_THROTTLE	(dev_priv->mipi_mmio_base + 0xb824)
10313 #define MIPI_DBI_FIFO_THROTTLE(port)	_MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
10314 #define  DBI_FIFO_EMPTY_HALF				(0 << 0)
10315 #define  DBI_FIFO_EMPTY_QUARTER				(1 << 0)
10316 #define  DBI_FIFO_EMPTY_7_LOCATIONS			(2 << 0)
10317 
10318 /* regs below are bits 15:0 */
10319 #define _MIPIA_HSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb028)
10320 #define _MIPIC_HSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb828)
10321 #define MIPI_HSYNC_PADDING_COUNT(port)	_MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
10322 
10323 #define _MIPIA_HBP_COUNT		(dev_priv->mipi_mmio_base + 0xb02c)
10324 #define _MIPIC_HBP_COUNT		(dev_priv->mipi_mmio_base + 0xb82c)
10325 #define MIPI_HBP_COUNT(port)		_MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT)
10326 
10327 #define _MIPIA_HFP_COUNT		(dev_priv->mipi_mmio_base + 0xb030)
10328 #define _MIPIC_HFP_COUNT		(dev_priv->mipi_mmio_base + 0xb830)
10329 #define MIPI_HFP_COUNT(port)		_MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT)
10330 
10331 #define _MIPIA_HACTIVE_AREA_COUNT	(dev_priv->mipi_mmio_base + 0xb034)
10332 #define _MIPIC_HACTIVE_AREA_COUNT	(dev_priv->mipi_mmio_base + 0xb834)
10333 #define MIPI_HACTIVE_AREA_COUNT(port)	_MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
10334 
10335 #define _MIPIA_VSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb038)
10336 #define _MIPIC_VSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb838)
10337 #define MIPI_VSYNC_PADDING_COUNT(port)	_MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
10338 
10339 #define _MIPIA_VBP_COUNT		(dev_priv->mipi_mmio_base + 0xb03c)
10340 #define _MIPIC_VBP_COUNT		(dev_priv->mipi_mmio_base + 0xb83c)
10341 #define MIPI_VBP_COUNT(port)		_MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT)
10342 
10343 #define _MIPIA_VFP_COUNT		(dev_priv->mipi_mmio_base + 0xb040)
10344 #define _MIPIC_VFP_COUNT		(dev_priv->mipi_mmio_base + 0xb840)
10345 #define MIPI_VFP_COUNT(port)		_MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT)
10346 
10347 #define _MIPIA_HIGH_LOW_SWITCH_COUNT	(dev_priv->mipi_mmio_base + 0xb044)
10348 #define _MIPIC_HIGH_LOW_SWITCH_COUNT	(dev_priv->mipi_mmio_base + 0xb844)
10349 #define MIPI_HIGH_LOW_SWITCH_COUNT(port)	_MMIO_MIPI(port,	_MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
10350 
10351 /* regs above are bits 15:0 */
10352 
10353 #define _MIPIA_DPI_CONTROL		(dev_priv->mipi_mmio_base + 0xb048)
10354 #define _MIPIC_DPI_CONTROL		(dev_priv->mipi_mmio_base + 0xb848)
10355 #define MIPI_DPI_CONTROL(port)		_MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL)
10356 #define  DPI_LP_MODE					(1 << 6)
10357 #define  BACKLIGHT_OFF					(1 << 5)
10358 #define  BACKLIGHT_ON					(1 << 4)
10359 #define  COLOR_MODE_OFF					(1 << 3)
10360 #define  COLOR_MODE_ON					(1 << 2)
10361 #define  TURN_ON					(1 << 1)
10362 #define  SHUTDOWN					(1 << 0)
10363 
10364 #define _MIPIA_DPI_DATA			(dev_priv->mipi_mmio_base + 0xb04c)
10365 #define _MIPIC_DPI_DATA			(dev_priv->mipi_mmio_base + 0xb84c)
10366 #define MIPI_DPI_DATA(port)		_MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA)
10367 #define  COMMAND_BYTE_SHIFT				0
10368 #define  COMMAND_BYTE_MASK				(0x3f << 0)
10369 
10370 #define _MIPIA_INIT_COUNT		(dev_priv->mipi_mmio_base + 0xb050)
10371 #define _MIPIC_INIT_COUNT		(dev_priv->mipi_mmio_base + 0xb850)
10372 #define MIPI_INIT_COUNT(port)		_MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT)
10373 #define  MASTER_INIT_TIMER_SHIFT			0
10374 #define  MASTER_INIT_TIMER_MASK				(0xffff << 0)
10375 
10376 #define _MIPIA_MAX_RETURN_PKT_SIZE	(dev_priv->mipi_mmio_base + 0xb054)
10377 #define _MIPIC_MAX_RETURN_PKT_SIZE	(dev_priv->mipi_mmio_base + 0xb854)
10378 #define MIPI_MAX_RETURN_PKT_SIZE(port)	_MMIO_MIPI(port, \
10379 			_MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)
10380 #define  MAX_RETURN_PKT_SIZE_SHIFT			0
10381 #define  MAX_RETURN_PKT_SIZE_MASK			(0x3ff << 0)
10382 
10383 #define _MIPIA_VIDEO_MODE_FORMAT	(dev_priv->mipi_mmio_base + 0xb058)
10384 #define _MIPIC_VIDEO_MODE_FORMAT	(dev_priv->mipi_mmio_base + 0xb858)
10385 #define MIPI_VIDEO_MODE_FORMAT(port)	_MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
10386 #define  RANDOM_DPI_DISPLAY_RESOLUTION			(1 << 4)
10387 #define  DISABLE_VIDEO_BTA				(1 << 3)
10388 #define  IP_TG_CONFIG					(1 << 2)
10389 #define  VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE		(1 << 0)
10390 #define  VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS		(2 << 0)
10391 #define  VIDEO_MODE_BURST				(3 << 0)
10392 
10393 #define _MIPIA_EOT_DISABLE		(dev_priv->mipi_mmio_base + 0xb05c)
10394 #define _MIPIC_EOT_DISABLE		(dev_priv->mipi_mmio_base + 0xb85c)
10395 #define MIPI_EOT_DISABLE(port)		_MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)
10396 #define  BXT_DEFEATURE_DPI_FIFO_CTR			(1 << 9)
10397 #define  BXT_DPHY_DEFEATURE_EN				(1 << 8)
10398 #define  LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE		(1 << 7)
10399 #define  HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE		(1 << 6)
10400 #define  LOW_CONTENTION_RECOVERY_DISABLE		(1 << 5)
10401 #define  HIGH_CONTENTION_RECOVERY_DISABLE		(1 << 4)
10402 #define  TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
10403 #define  TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE		(1 << 2)
10404 #define  CLOCKSTOP					(1 << 1)
10405 #define  EOT_DISABLE					(1 << 0)
10406 
10407 #define _MIPIA_LP_BYTECLK		(dev_priv->mipi_mmio_base + 0xb060)
10408 #define _MIPIC_LP_BYTECLK		(dev_priv->mipi_mmio_base + 0xb860)
10409 #define MIPI_LP_BYTECLK(port)		_MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK)
10410 #define  LP_BYTECLK_SHIFT				0
10411 #define  LP_BYTECLK_MASK				(0xffff << 0)
10412 
10413 #define _MIPIA_TLPX_TIME_COUNT		(dev_priv->mipi_mmio_base + 0xb0a4)
10414 #define _MIPIC_TLPX_TIME_COUNT		(dev_priv->mipi_mmio_base + 0xb8a4)
10415 #define MIPI_TLPX_TIME_COUNT(port)	 _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
10416 
10417 #define _MIPIA_CLK_LANE_TIMING		(dev_priv->mipi_mmio_base + 0xb098)
10418 #define _MIPIC_CLK_LANE_TIMING		(dev_priv->mipi_mmio_base + 0xb898)
10419 #define MIPI_CLK_LANE_TIMING(port)	 _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
10420 
10421 /* bits 31:0 */
10422 #define _MIPIA_LP_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb064)
10423 #define _MIPIC_LP_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb864)
10424 #define MIPI_LP_GEN_DATA(port)		_MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA)
10425 
10426 /* bits 31:0 */
10427 #define _MIPIA_HS_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb068)
10428 #define _MIPIC_HS_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb868)
10429 #define MIPI_HS_GEN_DATA(port)		_MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA)
10430 
10431 #define _MIPIA_LP_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb06c)
10432 #define _MIPIC_LP_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb86c)
10433 #define MIPI_LP_GEN_CTRL(port)		_MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL)
10434 #define _MIPIA_HS_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb070)
10435 #define _MIPIC_HS_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb870)
10436 #define MIPI_HS_GEN_CTRL(port)		_MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL)
10437 #define  LONG_PACKET_WORD_COUNT_SHIFT			8
10438 #define  LONG_PACKET_WORD_COUNT_MASK			(0xffff << 8)
10439 #define  SHORT_PACKET_PARAM_SHIFT			8
10440 #define  SHORT_PACKET_PARAM_MASK			(0xffff << 8)
10441 #define  VIRTUAL_CHANNEL_SHIFT				6
10442 #define  VIRTUAL_CHANNEL_MASK				(3 << 6)
10443 #define  DATA_TYPE_SHIFT				0
10444 #define  DATA_TYPE_MASK					(0x3f << 0)
10445 /* data type values, see include/video/mipi_display.h */
10446 
10447 #define _MIPIA_GEN_FIFO_STAT		(dev_priv->mipi_mmio_base + 0xb074)
10448 #define _MIPIC_GEN_FIFO_STAT		(dev_priv->mipi_mmio_base + 0xb874)
10449 #define MIPI_GEN_FIFO_STAT(port)	_MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT)
10450 #define  DPI_FIFO_EMPTY					(1 << 28)
10451 #define  DBI_FIFO_EMPTY					(1 << 27)
10452 #define  LP_CTRL_FIFO_EMPTY				(1 << 26)
10453 #define  LP_CTRL_FIFO_HALF_EMPTY			(1 << 25)
10454 #define  LP_CTRL_FIFO_FULL				(1 << 24)
10455 #define  HS_CTRL_FIFO_EMPTY				(1 << 18)
10456 #define  HS_CTRL_FIFO_HALF_EMPTY			(1 << 17)
10457 #define  HS_CTRL_FIFO_FULL				(1 << 16)
10458 #define  LP_DATA_FIFO_EMPTY				(1 << 10)
10459 #define  LP_DATA_FIFO_HALF_EMPTY			(1 << 9)
10460 #define  LP_DATA_FIFO_FULL				(1 << 8)
10461 #define  HS_DATA_FIFO_EMPTY				(1 << 2)
10462 #define  HS_DATA_FIFO_HALF_EMPTY			(1 << 1)
10463 #define  HS_DATA_FIFO_FULL				(1 << 0)
10464 
10465 #define _MIPIA_HS_LS_DBI_ENABLE		(dev_priv->mipi_mmio_base + 0xb078)
10466 #define _MIPIC_HS_LS_DBI_ENABLE		(dev_priv->mipi_mmio_base + 0xb878)
10467 #define MIPI_HS_LP_DBI_ENABLE(port)	_MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
10468 #define  DBI_HS_LP_MODE_MASK				(1 << 0)
10469 #define  DBI_LP_MODE					(1 << 0)
10470 #define  DBI_HS_MODE					(0 << 0)
10471 
10472 #define _MIPIA_DPHY_PARAM		(dev_priv->mipi_mmio_base + 0xb080)
10473 #define _MIPIC_DPHY_PARAM		(dev_priv->mipi_mmio_base + 0xb880)
10474 #define MIPI_DPHY_PARAM(port)		_MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM)
10475 #define  EXIT_ZERO_COUNT_SHIFT				24
10476 #define  EXIT_ZERO_COUNT_MASK				(0x3f << 24)
10477 #define  TRAIL_COUNT_SHIFT				16
10478 #define  TRAIL_COUNT_MASK				(0x1f << 16)
10479 #define  CLK_ZERO_COUNT_SHIFT				8
10480 #define  CLK_ZERO_COUNT_MASK				(0xff << 8)
10481 #define  PREPARE_COUNT_SHIFT				0
10482 #define  PREPARE_COUNT_MASK				(0x3f << 0)
10483 
10484 #define _ICL_DSI_T_INIT_MASTER_0	0x6b088
10485 #define _ICL_DSI_T_INIT_MASTER_1	0x6b888
10486 #define ICL_DSI_T_INIT_MASTER(port)	_MMIO_PORT(port,	\
10487 						   _ICL_DSI_T_INIT_MASTER_0,\
10488 						   _ICL_DSI_T_INIT_MASTER_1)
10489 
10490 #define _DPHY_CLK_TIMING_PARAM_0	0x162180
10491 #define _DPHY_CLK_TIMING_PARAM_1	0x6c180
10492 #define DPHY_CLK_TIMING_PARAM(port)	_MMIO_PORT(port,	\
10493 						   _DPHY_CLK_TIMING_PARAM_0,\
10494 						   _DPHY_CLK_TIMING_PARAM_1)
10495 #define _DSI_CLK_TIMING_PARAM_0		0x6b080
10496 #define _DSI_CLK_TIMING_PARAM_1		0x6b880
10497 #define DSI_CLK_TIMING_PARAM(port)	_MMIO_PORT(port,	\
10498 						   _DSI_CLK_TIMING_PARAM_0,\
10499 						   _DSI_CLK_TIMING_PARAM_1)
10500 #define  CLK_PREPARE_OVERRIDE		(1 << 31)
10501 #define  CLK_PREPARE(x)		((x) << 28)
10502 #define  CLK_PREPARE_MASK		(0x7 << 28)
10503 #define  CLK_PREPARE_SHIFT		28
10504 #define  CLK_ZERO_OVERRIDE		(1 << 27)
10505 #define  CLK_ZERO(x)			((x) << 20)
10506 #define  CLK_ZERO_MASK			(0xf << 20)
10507 #define  CLK_ZERO_SHIFT		20
10508 #define  CLK_PRE_OVERRIDE		(1 << 19)
10509 #define  CLK_PRE(x)			((x) << 16)
10510 #define  CLK_PRE_MASK			(0x3 << 16)
10511 #define  CLK_PRE_SHIFT			16
10512 #define  CLK_POST_OVERRIDE		(1 << 15)
10513 #define  CLK_POST(x)			((x) << 8)
10514 #define  CLK_POST_MASK			(0x7 << 8)
10515 #define  CLK_POST_SHIFT		8
10516 #define  CLK_TRAIL_OVERRIDE		(1 << 7)
10517 #define  CLK_TRAIL(x)			((x) << 0)
10518 #define  CLK_TRAIL_MASK		(0xf << 0)
10519 #define  CLK_TRAIL_SHIFT		0
10520 
10521 #define _DPHY_DATA_TIMING_PARAM_0	0x162184
10522 #define _DPHY_DATA_TIMING_PARAM_1	0x6c184
10523 #define DPHY_DATA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
10524 						   _DPHY_DATA_TIMING_PARAM_0,\
10525 						   _DPHY_DATA_TIMING_PARAM_1)
10526 #define _DSI_DATA_TIMING_PARAM_0	0x6B084
10527 #define _DSI_DATA_TIMING_PARAM_1	0x6B884
10528 #define DSI_DATA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
10529 						   _DSI_DATA_TIMING_PARAM_0,\
10530 						   _DSI_DATA_TIMING_PARAM_1)
10531 #define  HS_PREPARE_OVERRIDE		(1 << 31)
10532 #define  HS_PREPARE(x)			((x) << 24)
10533 #define  HS_PREPARE_MASK		(0x7 << 24)
10534 #define  HS_PREPARE_SHIFT		24
10535 #define  HS_ZERO_OVERRIDE		(1 << 23)
10536 #define  HS_ZERO(x)			((x) << 16)
10537 #define  HS_ZERO_MASK			(0xf << 16)
10538 #define  HS_ZERO_SHIFT			16
10539 #define  HS_TRAIL_OVERRIDE		(1 << 15)
10540 #define  HS_TRAIL(x)			((x) << 8)
10541 #define  HS_TRAIL_MASK			(0x7 << 8)
10542 #define  HS_TRAIL_SHIFT		8
10543 #define  HS_EXIT_OVERRIDE		(1 << 7)
10544 #define  HS_EXIT(x)			((x) << 0)
10545 #define  HS_EXIT_MASK			(0x7 << 0)
10546 #define  HS_EXIT_SHIFT			0
10547 
10548 #define _DPHY_TA_TIMING_PARAM_0		0x162188
10549 #define _DPHY_TA_TIMING_PARAM_1		0x6c188
10550 #define DPHY_TA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
10551 						   _DPHY_TA_TIMING_PARAM_0,\
10552 						   _DPHY_TA_TIMING_PARAM_1)
10553 #define _DSI_TA_TIMING_PARAM_0		0x6b098
10554 #define _DSI_TA_TIMING_PARAM_1		0x6b898
10555 #define DSI_TA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
10556 						   _DSI_TA_TIMING_PARAM_0,\
10557 						   _DSI_TA_TIMING_PARAM_1)
10558 #define  TA_SURE_OVERRIDE		(1 << 31)
10559 #define  TA_SURE(x)			((x) << 16)
10560 #define  TA_SURE_MASK			(0x1f << 16)
10561 #define  TA_SURE_SHIFT			16
10562 #define  TA_GO_OVERRIDE		(1 << 15)
10563 #define  TA_GO(x)			((x) << 8)
10564 #define  TA_GO_MASK			(0xf << 8)
10565 #define  TA_GO_SHIFT			8
10566 #define  TA_GET_OVERRIDE		(1 << 7)
10567 #define  TA_GET(x)			((x) << 0)
10568 #define  TA_GET_MASK			(0xf << 0)
10569 #define  TA_GET_SHIFT			0
10570 
10571 /* DSI transcoder configuration */
10572 #define _DSI_TRANS_FUNC_CONF_0		0x6b030
10573 #define _DSI_TRANS_FUNC_CONF_1		0x6b830
10574 #define DSI_TRANS_FUNC_CONF(tc)		_MMIO_DSI(tc,	\
10575 						  _DSI_TRANS_FUNC_CONF_0,\
10576 						  _DSI_TRANS_FUNC_CONF_1)
10577 #define  OP_MODE_MASK			(0x3 << 28)
10578 #define  OP_MODE_SHIFT			28
10579 #define  CMD_MODE_NO_GATE		(0x0 << 28)
10580 #define  CMD_MODE_TE_GATE		(0x1 << 28)
10581 #define  VIDEO_MODE_SYNC_EVENT		(0x2 << 28)
10582 #define  VIDEO_MODE_SYNC_PULSE		(0x3 << 28)
10583 #define  LINK_READY			(1 << 20)
10584 #define  PIX_FMT_MASK			(0x3 << 16)
10585 #define  PIX_FMT_SHIFT			16
10586 #define  PIX_FMT_RGB565			(0x0 << 16)
10587 #define  PIX_FMT_RGB666_PACKED		(0x1 << 16)
10588 #define  PIX_FMT_RGB666_LOOSE		(0x2 << 16)
10589 #define  PIX_FMT_RGB888			(0x3 << 16)
10590 #define  PIX_FMT_RGB101010		(0x4 << 16)
10591 #define  PIX_FMT_RGB121212		(0x5 << 16)
10592 #define  PIX_FMT_COMPRESSED		(0x6 << 16)
10593 #define  BGR_TRANSMISSION		(1 << 15)
10594 #define  PIX_VIRT_CHAN(x)		((x) << 12)
10595 #define  PIX_VIRT_CHAN_MASK		(0x3 << 12)
10596 #define  PIX_VIRT_CHAN_SHIFT		12
10597 #define  PIX_BUF_THRESHOLD_MASK		(0x3 << 10)
10598 #define  PIX_BUF_THRESHOLD_SHIFT	10
10599 #define  PIX_BUF_THRESHOLD_1_4		(0x0 << 10)
10600 #define  PIX_BUF_THRESHOLD_1_2		(0x1 << 10)
10601 #define  PIX_BUF_THRESHOLD_3_4		(0x2 << 10)
10602 #define  PIX_BUF_THRESHOLD_FULL		(0x3 << 10)
10603 #define  CONTINUOUS_CLK_MASK		(0x3 << 8)
10604 #define  CONTINUOUS_CLK_SHIFT		8
10605 #define  CLK_ENTER_LP_AFTER_DATA	(0x0 << 8)
10606 #define  CLK_HS_OR_LP			(0x2 << 8)
10607 #define  CLK_HS_CONTINUOUS		(0x3 << 8)
10608 #define  LINK_CALIBRATION_MASK		(0x3 << 4)
10609 #define  LINK_CALIBRATION_SHIFT		4
10610 #define  CALIBRATION_DISABLED		(0x0 << 4)
10611 #define  CALIBRATION_ENABLED_INITIAL_ONLY	(0x2 << 4)
10612 #define  CALIBRATION_ENABLED_INITIAL_PERIODIC	(0x3 << 4)
10613 #define  S3D_ORIENTATION_LANDSCAPE	(1 << 1)
10614 #define  EOTP_DISABLED			(1 << 0)
10615 
10616 #define _DSI_CMD_RXCTL_0		0x6b0d4
10617 #define _DSI_CMD_RXCTL_1		0x6b8d4
10618 #define DSI_CMD_RXCTL(tc)		_MMIO_DSI(tc,	\
10619 						  _DSI_CMD_RXCTL_0,\
10620 						  _DSI_CMD_RXCTL_1)
10621 #define  READ_UNLOADS_DW		(1 << 16)
10622 #define  RECEIVED_UNASSIGNED_TRIGGER	(1 << 15)
10623 #define  RECEIVED_ACKNOWLEDGE_TRIGGER	(1 << 14)
10624 #define  RECEIVED_TEAR_EFFECT_TRIGGER	(1 << 13)
10625 #define  RECEIVED_RESET_TRIGGER		(1 << 12)
10626 #define  RECEIVED_PAYLOAD_WAS_LOST	(1 << 11)
10627 #define  RECEIVED_CRC_WAS_LOST		(1 << 10)
10628 #define  NUMBER_RX_PLOAD_DW_MASK	(0xff << 0)
10629 #define  NUMBER_RX_PLOAD_DW_SHIFT	0
10630 
10631 #define _DSI_CMD_TXCTL_0		0x6b0d0
10632 #define _DSI_CMD_TXCTL_1		0x6b8d0
10633 #define DSI_CMD_TXCTL(tc)		_MMIO_DSI(tc,	\
10634 						  _DSI_CMD_TXCTL_0,\
10635 						  _DSI_CMD_TXCTL_1)
10636 #define  KEEP_LINK_IN_HS		(1 << 24)
10637 #define  FREE_HEADER_CREDIT_MASK	(0x1f << 8)
10638 #define  FREE_HEADER_CREDIT_SHIFT	0x8
10639 #define  FREE_PLOAD_CREDIT_MASK		(0xff << 0)
10640 #define  FREE_PLOAD_CREDIT_SHIFT	0
10641 #define  MAX_HEADER_CREDIT		0x10
10642 #define  MAX_PLOAD_CREDIT		0x40
10643 
10644 #define _DSI_CMD_TXHDR_0		0x6b100
10645 #define _DSI_CMD_TXHDR_1		0x6b900
10646 #define DSI_CMD_TXHDR(tc)		_MMIO_DSI(tc,	\
10647 						  _DSI_CMD_TXHDR_0,\
10648 						  _DSI_CMD_TXHDR_1)
10649 #define  PAYLOAD_PRESENT		(1 << 31)
10650 #define  LP_DATA_TRANSFER		(1 << 30)
10651 #define  VBLANK_FENCE			(1 << 29)
10652 #define  PARAM_WC_MASK			(0xffff << 8)
10653 #define  PARAM_WC_LOWER_SHIFT		8
10654 #define  PARAM_WC_UPPER_SHIFT		16
10655 #define  VC_MASK			(0x3 << 6)
10656 #define  VC_SHIFT			6
10657 #define  DT_MASK			(0x3f << 0)
10658 #define  DT_SHIFT			0
10659 
10660 #define _DSI_CMD_TXPYLD_0		0x6b104
10661 #define _DSI_CMD_TXPYLD_1		0x6b904
10662 #define DSI_CMD_TXPYLD(tc)		_MMIO_DSI(tc,	\
10663 						  _DSI_CMD_TXPYLD_0,\
10664 						  _DSI_CMD_TXPYLD_1)
10665 
10666 #define _DSI_LP_MSG_0			0x6b0d8
10667 #define _DSI_LP_MSG_1			0x6b8d8
10668 #define DSI_LP_MSG(tc)			_MMIO_DSI(tc,	\
10669 						  _DSI_LP_MSG_0,\
10670 						  _DSI_LP_MSG_1)
10671 #define  LPTX_IN_PROGRESS		(1 << 17)
10672 #define  LINK_IN_ULPS			(1 << 16)
10673 #define  LINK_ULPS_TYPE_LP11		(1 << 8)
10674 #define  LINK_ENTER_ULPS		(1 << 0)
10675 
10676 /* DSI timeout registers */
10677 #define _DSI_HSTX_TO_0			0x6b044
10678 #define _DSI_HSTX_TO_1			0x6b844
10679 #define DSI_HSTX_TO(tc)			_MMIO_DSI(tc,	\
10680 						  _DSI_HSTX_TO_0,\
10681 						  _DSI_HSTX_TO_1)
10682 #define  HSTX_TIMEOUT_VALUE_MASK	(0xffff << 16)
10683 #define  HSTX_TIMEOUT_VALUE_SHIFT	16
10684 #define  HSTX_TIMEOUT_VALUE(x)		((x) << 16)
10685 #define  HSTX_TIMED_OUT			(1 << 0)
10686 
10687 #define _DSI_LPRX_HOST_TO_0		0x6b048
10688 #define _DSI_LPRX_HOST_TO_1		0x6b848
10689 #define DSI_LPRX_HOST_TO(tc)		_MMIO_DSI(tc,	\
10690 						  _DSI_LPRX_HOST_TO_0,\
10691 						  _DSI_LPRX_HOST_TO_1)
10692 #define  LPRX_TIMED_OUT			(1 << 16)
10693 #define  LPRX_TIMEOUT_VALUE_MASK	(0xffff << 0)
10694 #define  LPRX_TIMEOUT_VALUE_SHIFT	0
10695 #define  LPRX_TIMEOUT_VALUE(x)		((x) << 0)
10696 
10697 #define _DSI_PWAIT_TO_0			0x6b040
10698 #define _DSI_PWAIT_TO_1			0x6b840
10699 #define DSI_PWAIT_TO(tc)		_MMIO_DSI(tc,	\
10700 						  _DSI_PWAIT_TO_0,\
10701 						  _DSI_PWAIT_TO_1)
10702 #define  PRESET_TIMEOUT_VALUE_MASK	(0xffff << 16)
10703 #define  PRESET_TIMEOUT_VALUE_SHIFT	16
10704 #define  PRESET_TIMEOUT_VALUE(x)	((x) << 16)
10705 #define  PRESPONSE_TIMEOUT_VALUE_MASK	(0xffff << 0)
10706 #define  PRESPONSE_TIMEOUT_VALUE_SHIFT	0
10707 #define  PRESPONSE_TIMEOUT_VALUE(x)	((x) << 0)
10708 
10709 #define _DSI_TA_TO_0			0x6b04c
10710 #define _DSI_TA_TO_1			0x6b84c
10711 #define DSI_TA_TO(tc)			_MMIO_DSI(tc,	\
10712 						  _DSI_TA_TO_0,\
10713 						  _DSI_TA_TO_1)
10714 #define  TA_TIMED_OUT			(1 << 16)
10715 #define  TA_TIMEOUT_VALUE_MASK		(0xffff << 0)
10716 #define  TA_TIMEOUT_VALUE_SHIFT		0
10717 #define  TA_TIMEOUT_VALUE(x)		((x) << 0)
10718 
10719 /* bits 31:0 */
10720 #define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)
10721 #define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)
10722 #define MIPI_DBI_BW_CTRL(port)		_MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL)
10723 
10724 #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT		(dev_priv->mipi_mmio_base + 0xb088)
10725 #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT		(dev_priv->mipi_mmio_base + 0xb888)
10726 #define MIPI_CLK_LANE_SWITCH_TIME_CNT(port)	_MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
10727 #define  LP_HS_SSW_CNT_SHIFT				16
10728 #define  LP_HS_SSW_CNT_MASK				(0xffff << 16)
10729 #define  HS_LP_PWR_SW_CNT_SHIFT				0
10730 #define  HS_LP_PWR_SW_CNT_MASK				(0xffff << 0)
10731 
10732 #define _MIPIA_STOP_STATE_STALL		(dev_priv->mipi_mmio_base + 0xb08c)
10733 #define _MIPIC_STOP_STATE_STALL		(dev_priv->mipi_mmio_base + 0xb88c)
10734 #define MIPI_STOP_STATE_STALL(port)	_MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
10735 #define  STOP_STATE_STALL_COUNTER_SHIFT			0
10736 #define  STOP_STATE_STALL_COUNTER_MASK			(0xff << 0)
10737 
10738 #define _MIPIA_INTR_STAT_REG_1		(dev_priv->mipi_mmio_base + 0xb090)
10739 #define _MIPIC_INTR_STAT_REG_1		(dev_priv->mipi_mmio_base + 0xb890)
10740 #define MIPI_INTR_STAT_REG_1(port)	_MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
10741 #define _MIPIA_INTR_EN_REG_1		(dev_priv->mipi_mmio_base + 0xb094)
10742 #define _MIPIC_INTR_EN_REG_1		(dev_priv->mipi_mmio_base + 0xb894)
10743 #define MIPI_INTR_EN_REG_1(port)	_MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1)
10744 #define  RX_CONTENTION_DETECTED				(1 << 0)
10745 
10746 /* XXX: only pipe A ?!? */
10747 #define MIPIA_DBI_TYPEC_CTRL		(dev_priv->mipi_mmio_base + 0xb100)
10748 #define  DBI_TYPEC_ENABLE				(1 << 31)
10749 #define  DBI_TYPEC_WIP					(1 << 30)
10750 #define  DBI_TYPEC_OPTION_SHIFT				28
10751 #define  DBI_TYPEC_OPTION_MASK				(3 << 28)
10752 #define  DBI_TYPEC_FREQ_SHIFT				24
10753 #define  DBI_TYPEC_FREQ_MASK				(0xf << 24)
10754 #define  DBI_TYPEC_OVERRIDE				(1 << 8)
10755 #define  DBI_TYPEC_OVERRIDE_COUNTER_SHIFT		0
10756 #define  DBI_TYPEC_OVERRIDE_COUNTER_MASK		(0xff << 0)
10757 
10758 
10759 /* MIPI adapter registers */
10760 
10761 #define _MIPIA_CTRL			(dev_priv->mipi_mmio_base + 0xb104)
10762 #define _MIPIC_CTRL			(dev_priv->mipi_mmio_base + 0xb904)
10763 #define MIPI_CTRL(port)			_MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL)
10764 #define  ESCAPE_CLOCK_DIVIDER_SHIFT			5 /* A only */
10765 #define  ESCAPE_CLOCK_DIVIDER_MASK			(3 << 5)
10766 #define  ESCAPE_CLOCK_DIVIDER_1				(0 << 5)
10767 #define  ESCAPE_CLOCK_DIVIDER_2				(1 << 5)
10768 #define  ESCAPE_CLOCK_DIVIDER_4				(2 << 5)
10769 #define  READ_REQUEST_PRIORITY_SHIFT			3
10770 #define  READ_REQUEST_PRIORITY_MASK			(3 << 3)
10771 #define  READ_REQUEST_PRIORITY_LOW			(0 << 3)
10772 #define  READ_REQUEST_PRIORITY_HIGH			(3 << 3)
10773 #define  RGB_FLIP_TO_BGR				(1 << 2)
10774 
10775 #define  BXT_PIPE_SELECT_SHIFT				7
10776 #define  BXT_PIPE_SELECT_MASK				(7 << 7)
10777 #define  BXT_PIPE_SELECT(pipe)				((pipe) << 7)
10778 #define  GLK_PHY_STATUS_PORT_READY			(1 << 31) /* RO */
10779 #define  GLK_ULPS_NOT_ACTIVE				(1 << 30) /* RO */
10780 #define  GLK_MIPIIO_RESET_RELEASED			(1 << 28)
10781 #define  GLK_CLOCK_LANE_STOP_STATE			(1 << 27) /* RO */
10782 #define  GLK_DATA_LANE_STOP_STATE			(1 << 26) /* RO */
10783 #define  GLK_LP_WAKE					(1 << 22)
10784 #define  GLK_LP11_LOW_PWR_MODE				(1 << 21)
10785 #define  GLK_LP00_LOW_PWR_MODE				(1 << 20)
10786 #define  GLK_FIREWALL_ENABLE				(1 << 16)
10787 #define  BXT_PIXEL_OVERLAP_CNT_MASK			(0xf << 10)
10788 #define  BXT_PIXEL_OVERLAP_CNT_SHIFT			10
10789 #define  BXT_DSC_ENABLE					(1 << 3)
10790 #define  BXT_RGB_FLIP					(1 << 2)
10791 #define  GLK_MIPIIO_PORT_POWERED			(1 << 1) /* RO */
10792 #define  GLK_MIPIIO_ENABLE				(1 << 0)
10793 
10794 #define _MIPIA_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb108)
10795 #define _MIPIC_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb908)
10796 #define MIPI_DATA_ADDRESS(port)		_MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS)
10797 #define  DATA_MEM_ADDRESS_SHIFT				5
10798 #define  DATA_MEM_ADDRESS_MASK				(0x7ffffff << 5)
10799 #define  DATA_VALID					(1 << 0)
10800 
10801 #define _MIPIA_DATA_LENGTH		(dev_priv->mipi_mmio_base + 0xb10c)
10802 #define _MIPIC_DATA_LENGTH		(dev_priv->mipi_mmio_base + 0xb90c)
10803 #define MIPI_DATA_LENGTH(port)		_MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH)
10804 #define  DATA_LENGTH_SHIFT				0
10805 #define  DATA_LENGTH_MASK				(0xfffff << 0)
10806 
10807 #define _MIPIA_COMMAND_ADDRESS		(dev_priv->mipi_mmio_base + 0xb110)
10808 #define _MIPIC_COMMAND_ADDRESS		(dev_priv->mipi_mmio_base + 0xb910)
10809 #define MIPI_COMMAND_ADDRESS(port)	_MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
10810 #define  COMMAND_MEM_ADDRESS_SHIFT			5
10811 #define  COMMAND_MEM_ADDRESS_MASK			(0x7ffffff << 5)
10812 #define  AUTO_PWG_ENABLE				(1 << 2)
10813 #define  MEMORY_WRITE_DATA_FROM_PIPE_RENDERING		(1 << 1)
10814 #define  COMMAND_VALID					(1 << 0)
10815 
10816 #define _MIPIA_COMMAND_LENGTH		(dev_priv->mipi_mmio_base + 0xb114)
10817 #define _MIPIC_COMMAND_LENGTH		(dev_priv->mipi_mmio_base + 0xb914)
10818 #define MIPI_COMMAND_LENGTH(port)	_MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH)
10819 #define  COMMAND_LENGTH_SHIFT(n)			(8 * (n)) /* n: 0...3 */
10820 #define  COMMAND_LENGTH_MASK(n)				(0xff << (8 * (n)))
10821 
10822 #define _MIPIA_READ_DATA_RETURN0	(dev_priv->mipi_mmio_base + 0xb118)
10823 #define _MIPIC_READ_DATA_RETURN0	(dev_priv->mipi_mmio_base + 0xb918)
10824 #define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
10825 
10826 #define _MIPIA_READ_DATA_VALID		(dev_priv->mipi_mmio_base + 0xb138)
10827 #define _MIPIC_READ_DATA_VALID		(dev_priv->mipi_mmio_base + 0xb938)
10828 #define MIPI_READ_DATA_VALID(port)	_MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
10829 #define  READ_DATA_VALID(n)				(1 << (n))
10830 
10831 /* MOCS (Memory Object Control State) registers */
10832 #define GEN9_LNCFCMOCS(i)	_MMIO(0xb020 + (i) * 4)	/* L3 Cache Control */
10833 
10834 #define GEN9_GFX_MOCS(i)	_MMIO(0xc800 + (i) * 4)	/* Graphics MOCS registers */
10835 #define GEN9_MFX0_MOCS(i)	_MMIO(0xc900 + (i) * 4)	/* Media 0 MOCS registers */
10836 #define GEN9_MFX1_MOCS(i)	_MMIO(0xca00 + (i) * 4)	/* Media 1 MOCS registers */
10837 #define GEN9_VEBOX_MOCS(i)	_MMIO(0xcb00 + (i) * 4)	/* Video MOCS registers */
10838 #define GEN9_BLT_MOCS(i)	_MMIO(0xcc00 + (i) * 4)	/* Blitter MOCS registers */
10839 /* Media decoder 2 MOCS registers */
10840 #define GEN11_MFX2_MOCS(i)	_MMIO(0x10000 + (i) * 4)
10841 
10842 #define GEN10_SCRATCH_LNCF2		_MMIO(0xb0a0)
10843 #define   PMFLUSHDONE_LNICRSDROP	(1 << 20)
10844 #define   PMFLUSH_GAPL3UNBLOCK		(1 << 21)
10845 #define   PMFLUSHDONE_LNEBLK		(1 << 22)
10846 
10847 /* gamt regs */
10848 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
10849 #define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW  0x67F1427F /* max/min for LRA1/2 */
10850 #define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV  0x5FF101FF /* max/min for LRA1/2 */
10851 #define   GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL  0x67F1427F /*    "        " */
10852 #define   GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT  0x5FF101FF /*    "        " */
10853 
10854 #define MMCD_MISC_CTRL		_MMIO(0x4ddc) /* skl+ */
10855 #define  MMCD_PCLA		(1 << 31)
10856 #define  MMCD_HOTSPOT_EN	(1 << 27)
10857 
10858 #define _ICL_PHY_MISC_A		0x64C00
10859 #define _ICL_PHY_MISC_B		0x64C04
10860 #define ICL_PHY_MISC(port)	_MMIO_PORT(port, _ICL_PHY_MISC_A, \
10861 						 _ICL_PHY_MISC_B)
10862 #define  ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN	(1 << 23)
10863 
10864 /* Icelake Display Stream Compression Registers */
10865 #define DSCA_PICTURE_PARAMETER_SET_0		_MMIO(0x6B200)
10866 #define DSCC_PICTURE_PARAMETER_SET_0		_MMIO(0x6BA00)
10867 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB	0x78270
10868 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB	0x78370
10869 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC	0x78470
10870 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC	0x78570
10871 #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
10872 							   _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
10873 							   _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
10874 #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
10875 							   _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
10876 							   _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
10877 #define  DSC_VBR_ENABLE			(1 << 19)
10878 #define  DSC_422_ENABLE			(1 << 18)
10879 #define  DSC_COLOR_SPACE_CONVERSION	(1 << 17)
10880 #define  DSC_BLOCK_PREDICTION		(1 << 16)
10881 #define  DSC_LINE_BUF_DEPTH_SHIFT	12
10882 #define  DSC_BPC_SHIFT			8
10883 #define  DSC_VER_MIN_SHIFT		4
10884 #define  DSC_VER_MAJ			(0x1 << 0)
10885 
10886 #define DSCA_PICTURE_PARAMETER_SET_1		_MMIO(0x6B204)
10887 #define DSCC_PICTURE_PARAMETER_SET_1		_MMIO(0x6BA04)
10888 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB	0x78274
10889 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB	0x78374
10890 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC	0x78474
10891 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC	0x78574
10892 #define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
10893 							   _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \
10894 							   _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC)
10895 #define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
10896 							   _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \
10897 							   _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC)
10898 #define  DSC_BPP(bpp)				((bpp) << 0)
10899 
10900 #define DSCA_PICTURE_PARAMETER_SET_2		_MMIO(0x6B208)
10901 #define DSCC_PICTURE_PARAMETER_SET_2		_MMIO(0x6BA08)
10902 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB	0x78278
10903 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB	0x78378
10904 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC	0x78478
10905 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC	0x78578
10906 #define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
10907 							   _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \
10908 							   _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC)
10909 #define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
10910 					    _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \
10911 					    _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC)
10912 #define  DSC_PIC_WIDTH(pic_width)	((pic_width) << 16)
10913 #define  DSC_PIC_HEIGHT(pic_height)	((pic_height) << 0)
10914 
10915 #define DSCA_PICTURE_PARAMETER_SET_3		_MMIO(0x6B20C)
10916 #define DSCC_PICTURE_PARAMETER_SET_3		_MMIO(0x6BA0C)
10917 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB	0x7827C
10918 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB	0x7837C
10919 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC	0x7847C
10920 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC	0x7857C
10921 #define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
10922 							   _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \
10923 							   _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC)
10924 #define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
10925 							   _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \
10926 							   _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC)
10927 #define  DSC_SLICE_WIDTH(slice_width)   ((slice_width) << 16)
10928 #define  DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
10929 
10930 #define DSCA_PICTURE_PARAMETER_SET_4		_MMIO(0x6B210)
10931 #define DSCC_PICTURE_PARAMETER_SET_4		_MMIO(0x6BA10)
10932 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB	0x78280
10933 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB	0x78380
10934 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC	0x78480
10935 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC	0x78580
10936 #define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
10937 							   _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
10938 							   _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC)
10939 #define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
10940 							   _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \
10941 							   _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC)
10942 #define  DSC_INITIAL_DEC_DELAY(dec_delay)       ((dec_delay) << 16)
10943 #define  DSC_INITIAL_XMIT_DELAY(xmit_delay)     ((xmit_delay) << 0)
10944 
10945 #define DSCA_PICTURE_PARAMETER_SET_5		_MMIO(0x6B214)
10946 #define DSCC_PICTURE_PARAMETER_SET_5		_MMIO(0x6BA14)
10947 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB	0x78284
10948 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB	0x78384
10949 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC	0x78484
10950 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC	0x78584
10951 #define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
10952 							   _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \
10953 							   _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC)
10954 #define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
10955 							   _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \
10956 							   _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
10957 #define  DSC_SCALE_DEC_INT(scale_dec)	((scale_dec) << 16)
10958 #define  DSC_SCALE_INC_INT(scale_inc)		((scale_inc) << 0)
10959 
10960 #define DSCA_PICTURE_PARAMETER_SET_6		_MMIO(0x6B218)
10961 #define DSCC_PICTURE_PARAMETER_SET_6		_MMIO(0x6BA18)
10962 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB	0x78288
10963 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB	0x78388
10964 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC	0x78488
10965 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC	0x78588
10966 #define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
10967 							   _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \
10968 							   _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC)
10969 #define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
10970 							   _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \
10971 							   _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC)
10972 #define  DSC_FLATNESS_MAX_QP(max_qp)		((max_qp) << 24)
10973 #define  DSC_FLATNESS_MIN_QP(min_qp)		((min_qp) << 16)
10974 #define  DSC_FIRST_LINE_BPG_OFFSET(offset)	((offset) << 8)
10975 #define  DSC_INITIAL_SCALE_VALUE(value)		((value) << 0)
10976 
10977 #define DSCA_PICTURE_PARAMETER_SET_7		_MMIO(0x6B21C)
10978 #define DSCC_PICTURE_PARAMETER_SET_7		_MMIO(0x6BA1C)
10979 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB	0x7828C
10980 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB	0x7838C
10981 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC	0x7848C
10982 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC	0x7858C
10983 #define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
10984 							    _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \
10985 							    _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC)
10986 #define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
10987 							    _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \
10988 							    _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC)
10989 #define  DSC_NFL_BPG_OFFSET(bpg_offset)		((bpg_offset) << 16)
10990 #define  DSC_SLICE_BPG_OFFSET(bpg_offset)	((bpg_offset) << 0)
10991 
10992 #define DSCA_PICTURE_PARAMETER_SET_8		_MMIO(0x6B220)
10993 #define DSCC_PICTURE_PARAMETER_SET_8		_MMIO(0x6BA20)
10994 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB	0x78290
10995 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB	0x78390
10996 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC	0x78490
10997 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC	0x78590
10998 #define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
10999 							   _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \
11000 							   _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC)
11001 #define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11002 							   _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \
11003 							   _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC)
11004 #define  DSC_INITIAL_OFFSET(initial_offset)		((initial_offset) << 16)
11005 #define  DSC_FINAL_OFFSET(final_offset)			((final_offset) << 0)
11006 
11007 #define DSCA_PICTURE_PARAMETER_SET_9		_MMIO(0x6B224)
11008 #define DSCC_PICTURE_PARAMETER_SET_9		_MMIO(0x6BA24)
11009 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB	0x78294
11010 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB	0x78394
11011 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC	0x78494
11012 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC	0x78594
11013 #define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11014 							   _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \
11015 							   _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC)
11016 #define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11017 							   _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \
11018 							   _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC)
11019 #define  DSC_RC_EDGE_FACTOR(rc_edge_fact)	((rc_edge_fact) << 16)
11020 #define  DSC_RC_MODEL_SIZE(rc_model_size)	((rc_model_size) << 0)
11021 
11022 #define DSCA_PICTURE_PARAMETER_SET_10		_MMIO(0x6B228)
11023 #define DSCC_PICTURE_PARAMETER_SET_10		_MMIO(0x6BA28)
11024 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB	0x78298
11025 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB	0x78398
11026 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC	0x78498
11027 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC	0x78598
11028 #define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11029 							   _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \
11030 							   _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC)
11031 #define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11032 							   _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \
11033 							   _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC)
11034 #define  DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low)		((rc_tgt_off_low) << 20)
11035 #define  DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high)	((rc_tgt_off_high) << 16)
11036 #define  DSC_RC_QUANT_INC_LIMIT1(lim)			((lim) << 8)
11037 #define  DSC_RC_QUANT_INC_LIMIT0(lim)			((lim) << 0)
11038 
11039 #define DSCA_PICTURE_PARAMETER_SET_11		_MMIO(0x6B22C)
11040 #define DSCC_PICTURE_PARAMETER_SET_11		_MMIO(0x6BA2C)
11041 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB	0x7829C
11042 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB	0x7839C
11043 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC	0x7849C
11044 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC	0x7859C
11045 #define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11046 							   _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \
11047 							   _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC)
11048 #define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11049 							   _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \
11050 							   _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC)
11051 
11052 #define DSCA_PICTURE_PARAMETER_SET_12		_MMIO(0x6B260)
11053 #define DSCC_PICTURE_PARAMETER_SET_12		_MMIO(0x6BA60)
11054 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB	0x782A0
11055 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB	0x783A0
11056 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC	0x784A0
11057 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC	0x785A0
11058 #define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11059 							   _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \
11060 							   _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC)
11061 #define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11062 							   _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \
11063 							   _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC)
11064 
11065 #define DSCA_PICTURE_PARAMETER_SET_13		_MMIO(0x6B264)
11066 #define DSCC_PICTURE_PARAMETER_SET_13		_MMIO(0x6BA64)
11067 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB	0x782A4
11068 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB	0x783A4
11069 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC	0x784A4
11070 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC	0x785A4
11071 #define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11072 							   _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \
11073 							   _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC)
11074 #define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11075 							   _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \
11076 							   _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC)
11077 
11078 #define DSCA_PICTURE_PARAMETER_SET_14		_MMIO(0x6B268)
11079 #define DSCC_PICTURE_PARAMETER_SET_14		_MMIO(0x6BA68)
11080 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB	0x782A8
11081 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB	0x783A8
11082 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC	0x784A8
11083 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC	0x785A8
11084 #define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11085 							   _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \
11086 							   _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC)
11087 #define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11088 							   _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \
11089 							   _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC)
11090 
11091 #define DSCA_PICTURE_PARAMETER_SET_15		_MMIO(0x6B26C)
11092 #define DSCC_PICTURE_PARAMETER_SET_15		_MMIO(0x6BA6C)
11093 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB	0x782AC
11094 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB	0x783AC
11095 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC	0x784AC
11096 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC	0x785AC
11097 #define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11098 							   _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \
11099 							   _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC)
11100 #define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11101 							   _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \
11102 							   _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC)
11103 
11104 #define DSCA_PICTURE_PARAMETER_SET_16		_MMIO(0x6B270)
11105 #define DSCC_PICTURE_PARAMETER_SET_16		_MMIO(0x6BA70)
11106 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB	0x782B0
11107 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB	0x783B0
11108 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC	0x784B0
11109 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC	0x785B0
11110 #define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11111 							   _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \
11112 							   _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC)
11113 #define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11114 							   _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
11115 							   _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
11116 #define  DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame)	((slice_row_per_frame) << 20)
11117 #define  DSC_SLICE_PER_LINE(slice_per_line)		((slice_per_line) << 16)
11118 #define  DSC_SLICE_CHUNK_SIZE(slice_chunk_size)		((slice_chunk_size) << 0)
11119 
11120 /* Icelake Rate Control Buffer Threshold Registers */
11121 #define DSCA_RC_BUF_THRESH_0			_MMIO(0x6B230)
11122 #define DSCA_RC_BUF_THRESH_0_UDW		_MMIO(0x6B230 + 4)
11123 #define DSCC_RC_BUF_THRESH_0			_MMIO(0x6BA30)
11124 #define DSCC_RC_BUF_THRESH_0_UDW		_MMIO(0x6BA30 + 4)
11125 #define _ICL_DSC0_RC_BUF_THRESH_0_PB		(0x78254)
11126 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB	(0x78254 + 4)
11127 #define _ICL_DSC1_RC_BUF_THRESH_0_PB		(0x78354)
11128 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB	(0x78354 + 4)
11129 #define _ICL_DSC0_RC_BUF_THRESH_0_PC		(0x78454)
11130 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC	(0x78454 + 4)
11131 #define _ICL_DSC1_RC_BUF_THRESH_0_PC		(0x78554)
11132 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC	(0x78554 + 4)
11133 #define ICL_DSC0_RC_BUF_THRESH_0(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
11134 						_ICL_DSC0_RC_BUF_THRESH_0_PB, \
11135 						_ICL_DSC0_RC_BUF_THRESH_0_PC)
11136 #define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11137 						_ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \
11138 						_ICL_DSC0_RC_BUF_THRESH_0_UDW_PC)
11139 #define ICL_DSC1_RC_BUF_THRESH_0(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
11140 						_ICL_DSC1_RC_BUF_THRESH_0_PB, \
11141 						_ICL_DSC1_RC_BUF_THRESH_0_PC)
11142 #define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11143 						_ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \
11144 						_ICL_DSC1_RC_BUF_THRESH_0_UDW_PC)
11145 
11146 #define DSCA_RC_BUF_THRESH_1			_MMIO(0x6B238)
11147 #define DSCA_RC_BUF_THRESH_1_UDW		_MMIO(0x6B238 + 4)
11148 #define DSCC_RC_BUF_THRESH_1			_MMIO(0x6BA38)
11149 #define DSCC_RC_BUF_THRESH_1_UDW		_MMIO(0x6BA38 + 4)
11150 #define _ICL_DSC0_RC_BUF_THRESH_1_PB		(0x7825C)
11151 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB	(0x7825C + 4)
11152 #define _ICL_DSC1_RC_BUF_THRESH_1_PB		(0x7835C)
11153 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB	(0x7835C + 4)
11154 #define _ICL_DSC0_RC_BUF_THRESH_1_PC		(0x7845C)
11155 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC	(0x7845C + 4)
11156 #define _ICL_DSC1_RC_BUF_THRESH_1_PC		(0x7855C)
11157 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC	(0x7855C + 4)
11158 #define ICL_DSC0_RC_BUF_THRESH_1(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
11159 						_ICL_DSC0_RC_BUF_THRESH_1_PB, \
11160 						_ICL_DSC0_RC_BUF_THRESH_1_PC)
11161 #define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11162 						_ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \
11163 						_ICL_DSC0_RC_BUF_THRESH_1_UDW_PC)
11164 #define ICL_DSC1_RC_BUF_THRESH_1(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
11165 						_ICL_DSC1_RC_BUF_THRESH_1_PB, \
11166 						_ICL_DSC1_RC_BUF_THRESH_1_PC)
11167 #define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11168 						_ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
11169 						_ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
11170 
11171 #define PORT_TX_DFLEXDPSP			_MMIO(FIA1_BASE + 0x008A0)
11172 #define   TC_LIVE_STATE_TBT(tc_port)		(1 << ((tc_port) * 8 + 6))
11173 #define   TC_LIVE_STATE_TC(tc_port)		(1 << ((tc_port) * 8 + 5))
11174 #define   DP_LANE_ASSIGNMENT_SHIFT(tc_port)	((tc_port) * 8)
11175 #define   DP_LANE_ASSIGNMENT_MASK(tc_port)	(0xf << ((tc_port) * 8))
11176 #define   DP_LANE_ASSIGNMENT(tc_port, x)	((x) << ((tc_port) * 8))
11177 
11178 #define PORT_TX_DFLEXDPPMS				_MMIO(FIA1_BASE + 0x00890)
11179 #define   DP_PHY_MODE_STATUS_COMPLETED(tc_port)		(1 << (tc_port))
11180 
11181 #define PORT_TX_DFLEXDPCSSS			_MMIO(FIA1_BASE + 0x00894)
11182 #define   DP_PHY_MODE_STATUS_NOT_SAFE(tc_port)		(1 << (tc_port))
11183 
11184 #endif /* _I915_REG_H_ */
11185