1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 2 * All Rights Reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef _I915_REG_H_ 26 #define _I915_REG_H_ 27 28 #include <linux/bitfield.h> 29 #include <linux/bits.h> 30 31 /** 32 * DOC: The i915 register macro definition style guide 33 * 34 * Follow the style described here for new macros, and while changing existing 35 * macros. Do **not** mass change existing definitions just to update the style. 36 * 37 * Layout 38 * '''''' 39 * 40 * Keep helper macros near the top. For example, _PIPE() and friends. 41 * 42 * Prefix macros that generally should not be used outside of this file with 43 * underscore '_'. For example, _PIPE() and friends, single instances of 44 * registers that are defined solely for the use by function-like macros. 45 * 46 * Avoid using the underscore prefixed macros outside of this file. There are 47 * exceptions, but keep them to a minimum. 48 * 49 * There are two basic types of register definitions: Single registers and 50 * register groups. Register groups are registers which have two or more 51 * instances, for example one per pipe, port, transcoder, etc. Register groups 52 * should be defined using function-like macros. 53 * 54 * For single registers, define the register offset first, followed by register 55 * contents. 56 * 57 * For register groups, define the register instance offsets first, prefixed 58 * with underscore, followed by a function-like macro choosing the right 59 * instance based on the parameter, followed by register contents. 60 * 61 * Define the register contents (i.e. bit and bit field macros) from most 62 * significant to least significant bit. Indent the register content macros 63 * using two extra spaces between ``#define`` and the macro name. 64 * 65 * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents 66 * using ``REG_FIELD_PREP(mask, value)``. This will define the values already 67 * shifted in place, so they can be directly OR'd together. For convenience, 68 * function-like macros may be used to define bit fields, but do note that the 69 * macros may be needed to read as well as write the register contents. 70 * 71 * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name. 72 * 73 * Group the register and its contents together without blank lines, separate 74 * from other registers and their contents with one blank line. 75 * 76 * Indent macro values from macro names using TABs. Align values vertically. Use 77 * braces in macro values as needed to avoid unintended precedence after macro 78 * substitution. Use spaces in macro values according to kernel coding 79 * style. Use lower case in hexadecimal values. 80 * 81 * Naming 82 * '''''' 83 * 84 * Try to name registers according to the specs. If the register name changes in 85 * the specs from platform to another, stick to the original name. 86 * 87 * Try to re-use existing register macro definitions. Only add new macros for 88 * new register offsets, or when the register contents have changed enough to 89 * warrant a full redefinition. 90 * 91 * When a register macro changes for a new platform, prefix the new macro using 92 * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The 93 * prefix signifies the start platform/generation using the register. 94 * 95 * When a bit (field) macro changes or gets added for a new platform, while 96 * retaining the existing register macro, add a platform acronym or generation 97 * suffix to the name. For example, ``_SKL`` or ``_GEN8``. 98 * 99 * Examples 100 * '''''''' 101 * 102 * (Note that the values in the example are indented using spaces instead of 103 * TABs to avoid misalignment in generated documentation. Use TABs in the 104 * definitions.):: 105 * 106 * #define _FOO_A 0xf000 107 * #define _FOO_B 0xf001 108 * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B) 109 * #define FOO_ENABLE REG_BIT(31) 110 * #define FOO_MODE_MASK REG_GENMASK(19, 16) 111 * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0) 112 * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1) 113 * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2) 114 * 115 * #define BAR _MMIO(0xb000) 116 * #define GEN8_BAR _MMIO(0xb888) 117 */ 118 119 /** 120 * REG_BIT() - Prepare a u32 bit value 121 * @__n: 0-based bit number 122 * 123 * Local wrapper for BIT() to force u32, with compile time checks. 124 * 125 * @return: Value with bit @__n set. 126 */ 127 #define REG_BIT(__n) \ 128 ((u32)(BIT(__n) + \ 129 BUILD_BUG_ON_ZERO(__builtin_constant_p(__n) && \ 130 ((__n) < 0 || (__n) > 31)))) 131 132 /** 133 * REG_GENMASK() - Prepare a continuous u32 bitmask 134 * @__high: 0-based high bit 135 * @__low: 0-based low bit 136 * 137 * Local wrapper for GENMASK() to force u32, with compile time checks. 138 * 139 * @return: Continuous bitmask from @__high to @__low, inclusive. 140 */ 141 #define REG_GENMASK(__high, __low) \ 142 ((u32)(GENMASK(__high, __low) + \ 143 BUILD_BUG_ON_ZERO(__builtin_constant_p(__high) && \ 144 __builtin_constant_p(__low) && \ 145 ((__low) < 0 || (__high) > 31 || (__low) > (__high))))) 146 147 /* 148 * Local integer constant expression version of is_power_of_2(). 149 */ 150 #define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0)) 151 152 /** 153 * REG_FIELD_PREP() - Prepare a u32 bitfield value 154 * @__mask: shifted mask defining the field's length and position 155 * @__val: value to put in the field 156 157 * Local copy of FIELD_PREP() to generate an integer constant expression, force 158 * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK(). 159 * 160 * @return: @__val masked and shifted into the field defined by @__mask. 161 */ 162 #define REG_FIELD_PREP(__mask, __val) \ 163 ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \ 164 BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \ 165 BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \ 166 BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \ 167 BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0)))) 168 169 /** 170 * REG_FIELD_GET() - Extract a u32 bitfield value 171 * @__mask: shifted mask defining the field's length and position 172 * @__val: value to extract the bitfield value from 173 * 174 * Local wrapper for FIELD_GET() to force u32 and for consistency with 175 * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK(). 176 * 177 * @return: Masked and shifted value of the field defined by @__mask in @__val. 178 */ 179 #define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val)) 180 181 typedef struct { 182 u32 reg; 183 } i915_reg_t; 184 185 #define _MMIO(r) ((const i915_reg_t){ .reg = (r) }) 186 187 #define INVALID_MMIO_REG _MMIO(0) 188 189 static inline u32 i915_mmio_reg_offset(i915_reg_t reg) 190 { 191 return reg.reg; 192 } 193 194 static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b) 195 { 196 return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b); 197 } 198 199 static inline bool i915_mmio_reg_valid(i915_reg_t reg) 200 { 201 return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG); 202 } 203 204 #define VLV_DISPLAY_BASE 0x180000 205 #define VLV_MIPI_BASE VLV_DISPLAY_BASE 206 #define BXT_MIPI_BASE 0x60000 207 208 #define DISPLAY_MMIO_BASE(dev_priv) (INTEL_INFO(dev_priv)->display_mmio_offset) 209 210 /* 211 * Given the first two numbers __a and __b of arbitrarily many evenly spaced 212 * numbers, pick the 0-based __index'th value. 213 * 214 * Always prefer this over _PICK() if the numbers are evenly spaced. 215 */ 216 #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a))) 217 218 /* 219 * Given the arbitrary numbers in varargs, pick the 0-based __index'th number. 220 * 221 * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced. 222 */ 223 #define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index]) 224 225 /* 226 * Named helper wrappers around _PICK_EVEN() and _PICK(). 227 */ 228 #define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b) 229 #define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b) 230 #define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b) 231 #define _PORT(port, a, b) _PICK_EVEN(port, a, b) 232 #define _PLL(pll, a, b) _PICK_EVEN(pll, a, b) 233 234 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) 235 #define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b)) 236 #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b)) 237 #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b)) 238 #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b)) 239 240 #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__) 241 242 #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) 243 #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) 244 #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c)) 245 246 /* 247 * Device info offset array based helpers for groups of registers with unevenly 248 * spaced base offsets. 249 */ 250 #define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \ 251 INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \ 252 DISPLAY_MMIO_BASE(dev_priv)) 253 #define _MMIO_TRANS2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->trans_offsets[(pipe)] - \ 254 INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \ 255 DISPLAY_MMIO_BASE(dev_priv)) 256 #define _CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \ 257 INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \ 258 DISPLAY_MMIO_BASE(dev_priv)) 259 260 #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value)) 261 #define _MASKED_FIELD(mask, value) ({ \ 262 if (__builtin_constant_p(mask)) \ 263 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \ 264 if (__builtin_constant_p(value)) \ 265 BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \ 266 if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \ 267 BUILD_BUG_ON_MSG((value) & ~(mask), \ 268 "Incorrect value for mask"); \ 269 __MASKED_FIELD(mask, value); }) 270 #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) 271 #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0)) 272 273 /* Engine ID */ 274 275 #define RCS0_HW 0 276 #define VCS0_HW 1 277 #define BCS0_HW 2 278 #define VECS0_HW 3 279 #define VCS1_HW 4 280 #define VCS2_HW 6 281 #define VCS3_HW 7 282 #define VECS1_HW 12 283 284 /* Engine class */ 285 286 #define RENDER_CLASS 0 287 #define VIDEO_DECODE_CLASS 1 288 #define VIDEO_ENHANCEMENT_CLASS 2 289 #define COPY_ENGINE_CLASS 3 290 #define OTHER_CLASS 4 291 #define MAX_ENGINE_CLASS 4 292 293 #define OTHER_GTPM_INSTANCE 1 294 #define MAX_ENGINE_INSTANCE 3 295 296 /* PCI config space */ 297 298 #define MCHBAR_I915 0x44 299 #define MCHBAR_I965 0x48 300 #define MCHBAR_SIZE (4 * 4096) 301 302 #define DEVEN 0x54 303 #define DEVEN_MCHBAR_EN (1 << 28) 304 305 /* BSM in include/drm/i915_drm.h */ 306 307 #define HPLLCC 0xc0 /* 85x only */ 308 #define GC_CLOCK_CONTROL_MASK (0x7 << 0) 309 #define GC_CLOCK_133_200 (0 << 0) 310 #define GC_CLOCK_100_200 (1 << 0) 311 #define GC_CLOCK_100_133 (2 << 0) 312 #define GC_CLOCK_133_266 (3 << 0) 313 #define GC_CLOCK_133_200_2 (4 << 0) 314 #define GC_CLOCK_133_266_2 (5 << 0) 315 #define GC_CLOCK_166_266 (6 << 0) 316 #define GC_CLOCK_166_250 (7 << 0) 317 318 #define I915_GDRST 0xc0 /* PCI config register */ 319 #define GRDOM_FULL (0 << 2) 320 #define GRDOM_RENDER (1 << 2) 321 #define GRDOM_MEDIA (3 << 2) 322 #define GRDOM_MASK (3 << 2) 323 #define GRDOM_RESET_STATUS (1 << 1) 324 #define GRDOM_RESET_ENABLE (1 << 0) 325 326 /* BSpec only has register offset, PCI device and bit found empirically */ 327 #define I830_CLOCK_GATE 0xc8 /* device 0 */ 328 #define I830_L2_CACHE_CLOCK_GATE_DISABLE (1 << 2) 329 330 #define GCDGMBUS 0xcc 331 332 #define GCFGC2 0xda 333 #define GCFGC 0xf0 /* 915+ only */ 334 #define GC_LOW_FREQUENCY_ENABLE (1 << 7) 335 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) 336 #define GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4) 337 #define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4) 338 #define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4) 339 #define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4) 340 #define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4) 341 #define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4) 342 #define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4) 343 #define GC_DISPLAY_CLOCK_MASK (7 << 4) 344 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) 345 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) 346 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) 347 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) 348 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) 349 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0) 350 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) 351 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) 352 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) 353 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) 354 #define I945_GC_RENDER_CLOCK_MASK (7 << 0) 355 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) 356 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) 357 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) 358 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) 359 #define I915_GC_RENDER_CLOCK_MASK (7 << 0) 360 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) 361 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) 362 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) 363 364 #define ASLE 0xe4 365 #define ASLS 0xfc 366 367 #define SWSCI 0xe8 368 #define SWSCI_SCISEL (1 << 15) 369 #define SWSCI_GSSCIE (1 << 0) 370 371 #define LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */ 372 373 374 #define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4) 375 #define ILK_GRDOM_FULL (0 << 1) 376 #define ILK_GRDOM_RENDER (1 << 1) 377 #define ILK_GRDOM_MEDIA (3 << 1) 378 #define ILK_GRDOM_MASK (3 << 1) 379 #define ILK_GRDOM_RESET_ENABLE (1 << 0) 380 381 #define GEN6_MBCUNIT_SNPCR _MMIO(0x900c) /* for LLC config */ 382 #define GEN6_MBC_SNPCR_SHIFT 21 383 #define GEN6_MBC_SNPCR_MASK (3 << 21) 384 #define GEN6_MBC_SNPCR_MAX (0 << 21) 385 #define GEN6_MBC_SNPCR_MED (1 << 21) 386 #define GEN6_MBC_SNPCR_LOW (2 << 21) 387 #define GEN6_MBC_SNPCR_MIN (3 << 21) /* only 1/16th of the cache is shared */ 388 389 #define VLV_G3DCTL _MMIO(0x9024) 390 #define VLV_GSCKGCTL _MMIO(0x9028) 391 392 #define GEN6_MBCTL _MMIO(0x0907c) 393 #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4) 394 #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3) 395 #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2) 396 #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1) 397 #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0) 398 399 #define GEN6_GDRST _MMIO(0x941c) 400 #define GEN6_GRDOM_FULL (1 << 0) 401 #define GEN6_GRDOM_RENDER (1 << 1) 402 #define GEN6_GRDOM_MEDIA (1 << 2) 403 #define GEN6_GRDOM_BLT (1 << 3) 404 #define GEN6_GRDOM_VECS (1 << 4) 405 #define GEN9_GRDOM_GUC (1 << 5) 406 #define GEN8_GRDOM_MEDIA2 (1 << 7) 407 /* GEN11 changed all bit defs except for FULL & RENDER */ 408 #define GEN11_GRDOM_FULL GEN6_GRDOM_FULL 409 #define GEN11_GRDOM_RENDER GEN6_GRDOM_RENDER 410 #define GEN11_GRDOM_BLT (1 << 2) 411 #define GEN11_GRDOM_GUC (1 << 3) 412 #define GEN11_GRDOM_MEDIA (1 << 5) 413 #define GEN11_GRDOM_MEDIA2 (1 << 6) 414 #define GEN11_GRDOM_MEDIA3 (1 << 7) 415 #define GEN11_GRDOM_MEDIA4 (1 << 8) 416 #define GEN11_GRDOM_VECS (1 << 13) 417 #define GEN11_GRDOM_VECS2 (1 << 14) 418 #define GEN11_GRDOM_SFC0 (1 << 17) 419 #define GEN11_GRDOM_SFC1 (1 << 18) 420 421 #define GEN11_VCS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << ((instance) >> 1)) 422 #define GEN11_VECS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << (instance)) 423 424 #define GEN11_VCS_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x88C) 425 #define GEN11_VCS_SFC_FORCED_LOCK_BIT (1 << 0) 426 #define GEN11_VCS_SFC_LOCK_STATUS(engine) _MMIO((engine)->mmio_base + 0x890) 427 #define GEN11_VCS_SFC_USAGE_BIT (1 << 0) 428 #define GEN11_VCS_SFC_LOCK_ACK_BIT (1 << 1) 429 430 #define GEN11_VECS_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x201C) 431 #define GEN11_VECS_SFC_FORCED_LOCK_BIT (1 << 0) 432 #define GEN11_VECS_SFC_LOCK_ACK(engine) _MMIO((engine)->mmio_base + 0x2018) 433 #define GEN11_VECS_SFC_LOCK_ACK_BIT (1 << 0) 434 #define GEN11_VECS_SFC_USAGE(engine) _MMIO((engine)->mmio_base + 0x2014) 435 #define GEN11_VECS_SFC_USAGE_BIT (1 << 0) 436 437 #define RING_PP_DIR_BASE(base) _MMIO((base) + 0x228) 438 #define RING_PP_DIR_BASE_READ(base) _MMIO((base) + 0x518) 439 #define RING_PP_DIR_DCLV(base) _MMIO((base) + 0x220) 440 #define PP_DIR_DCLV_2G 0xffffffff 441 442 #define GEN8_RING_PDP_UDW(base, n) _MMIO((base) + 0x270 + (n) * 8 + 4) 443 #define GEN8_RING_PDP_LDW(base, n) _MMIO((base) + 0x270 + (n) * 8) 444 445 #define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8) 446 #define GEN8_RPCS_ENABLE (1 << 31) 447 #define GEN8_RPCS_S_CNT_ENABLE (1 << 18) 448 #define GEN8_RPCS_S_CNT_SHIFT 15 449 #define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT) 450 #define GEN11_RPCS_S_CNT_SHIFT 12 451 #define GEN11_RPCS_S_CNT_MASK (0x3f << GEN11_RPCS_S_CNT_SHIFT) 452 #define GEN8_RPCS_SS_CNT_ENABLE (1 << 11) 453 #define GEN8_RPCS_SS_CNT_SHIFT 8 454 #define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT) 455 #define GEN8_RPCS_EU_MAX_SHIFT 4 456 #define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT) 457 #define GEN8_RPCS_EU_MIN_SHIFT 0 458 #define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT) 459 460 #define WAIT_FOR_RC6_EXIT _MMIO(0x20CC) 461 /* HSW only */ 462 #define HSW_SELECTIVE_READ_ADDRESSING_SHIFT 2 463 #define HSW_SELECTIVE_READ_ADDRESSING_MASK (0x3 << HSW_SLECTIVE_READ_ADDRESSING_SHIFT) 464 #define HSW_SELECTIVE_WRITE_ADDRESS_SHIFT 4 465 #define HSW_SELECTIVE_WRITE_ADDRESS_MASK (0x7 << HSW_SELECTIVE_WRITE_ADDRESS_SHIFT) 466 /* HSW+ */ 467 #define HSW_WAIT_FOR_RC6_EXIT_ENABLE (1 << 0) 468 #define HSW_RCS_CONTEXT_ENABLE (1 << 7) 469 #define HSW_RCS_INHIBIT (1 << 8) 470 /* Gen8 */ 471 #define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4 472 #define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT) 473 #define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4 474 #define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT) 475 #define GEN8_SELECTIVE_WRITE_ADDRESSING_ENABLE (1 << 6) 476 #define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT 9 477 #define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT) 478 #define GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT 11 479 #define GEN8_SELECTIVE_READ_SLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT) 480 #define GEN8_SELECTIVE_READ_ADDRESSING_ENABLE (1 << 13) 481 482 #define GAM_ECOCHK _MMIO(0x4090) 483 #define BDW_DISABLE_HDC_INVALIDATION (1 << 25) 484 #define ECOCHK_SNB_BIT (1 << 10) 485 #define ECOCHK_DIS_TLB (1 << 8) 486 #define HSW_ECOCHK_ARB_PRIO_SOL (1 << 6) 487 #define ECOCHK_PPGTT_CACHE64B (0x3 << 3) 488 #define ECOCHK_PPGTT_CACHE4B (0x0 << 3) 489 #define ECOCHK_PPGTT_GFDT_IVB (0x1 << 4) 490 #define ECOCHK_PPGTT_LLC_IVB (0x1 << 3) 491 #define ECOCHK_PPGTT_UC_HSW (0x1 << 3) 492 #define ECOCHK_PPGTT_WT_HSW (0x2 << 3) 493 #define ECOCHK_PPGTT_WB_HSW (0x3 << 3) 494 495 #define GAC_ECO_BITS _MMIO(0x14090) 496 #define ECOBITS_SNB_BIT (1 << 13) 497 #define ECOBITS_PPGTT_CACHE64B (3 << 8) 498 #define ECOBITS_PPGTT_CACHE4B (0 << 8) 499 500 #define GAB_CTL _MMIO(0x24000) 501 #define GAB_CTL_CONT_AFTER_PAGEFAULT (1 << 8) 502 503 #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0) 504 #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20) 505 #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18) 506 #define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4) 507 #define GEN6_STOLEN_RESERVED_1M (0 << 4) 508 #define GEN6_STOLEN_RESERVED_512K (1 << 4) 509 #define GEN6_STOLEN_RESERVED_256K (2 << 4) 510 #define GEN6_STOLEN_RESERVED_128K (3 << 4) 511 #define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5) 512 #define GEN7_STOLEN_RESERVED_1M (0 << 5) 513 #define GEN7_STOLEN_RESERVED_256K (1 << 5) 514 #define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7) 515 #define GEN8_STOLEN_RESERVED_1M (0 << 7) 516 #define GEN8_STOLEN_RESERVED_2M (1 << 7) 517 #define GEN8_STOLEN_RESERVED_4M (2 << 7) 518 #define GEN8_STOLEN_RESERVED_8M (3 << 7) 519 #define GEN6_STOLEN_RESERVED_ENABLE (1 << 0) 520 #define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20) 521 522 /* VGA stuff */ 523 524 #define VGA_ST01_MDA 0x3ba 525 #define VGA_ST01_CGA 0x3da 526 527 #define _VGA_MSR_WRITE _MMIO(0x3c2) 528 #define VGA_MSR_WRITE 0x3c2 529 #define VGA_MSR_READ 0x3cc 530 #define VGA_MSR_MEM_EN (1 << 1) 531 #define VGA_MSR_CGA_MODE (1 << 0) 532 533 #define VGA_SR_INDEX 0x3c4 534 #define SR01 1 535 #define VGA_SR_DATA 0x3c5 536 537 #define VGA_AR_INDEX 0x3c0 538 #define VGA_AR_VID_EN (1 << 5) 539 #define VGA_AR_DATA_WRITE 0x3c0 540 #define VGA_AR_DATA_READ 0x3c1 541 542 #define VGA_GR_INDEX 0x3ce 543 #define VGA_GR_DATA 0x3cf 544 /* GR05 */ 545 #define VGA_GR_MEM_READ_MODE_SHIFT 3 546 #define VGA_GR_MEM_READ_MODE_PLANE 1 547 /* GR06 */ 548 #define VGA_GR_MEM_MODE_MASK 0xc 549 #define VGA_GR_MEM_MODE_SHIFT 2 550 #define VGA_GR_MEM_A0000_AFFFF 0 551 #define VGA_GR_MEM_A0000_BFFFF 1 552 #define VGA_GR_MEM_B0000_B7FFF 2 553 #define VGA_GR_MEM_B0000_BFFFF 3 554 555 #define VGA_DACMASK 0x3c6 556 #define VGA_DACRX 0x3c7 557 #define VGA_DACWX 0x3c8 558 #define VGA_DACDATA 0x3c9 559 560 #define VGA_CR_INDEX_MDA 0x3b4 561 #define VGA_CR_DATA_MDA 0x3b5 562 #define VGA_CR_INDEX_CGA 0x3d4 563 #define VGA_CR_DATA_CGA 0x3d5 564 565 #define MI_PREDICATE_SRC0 _MMIO(0x2400) 566 #define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4) 567 #define MI_PREDICATE_SRC1 _MMIO(0x2408) 568 #define MI_PREDICATE_SRC1_UDW _MMIO(0x2408 + 4) 569 570 #define MI_PREDICATE_RESULT_2 _MMIO(0x2214) 571 #define LOWER_SLICE_ENABLED (1 << 0) 572 #define LOWER_SLICE_DISABLED (0 << 0) 573 574 /* 575 * Registers used only by the command parser 576 */ 577 #define BCS_SWCTRL _MMIO(0x22200) 578 579 #define GPGPU_THREADS_DISPATCHED _MMIO(0x2290) 580 #define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4) 581 #define HS_INVOCATION_COUNT _MMIO(0x2300) 582 #define HS_INVOCATION_COUNT_UDW _MMIO(0x2300 + 4) 583 #define DS_INVOCATION_COUNT _MMIO(0x2308) 584 #define DS_INVOCATION_COUNT_UDW _MMIO(0x2308 + 4) 585 #define IA_VERTICES_COUNT _MMIO(0x2310) 586 #define IA_VERTICES_COUNT_UDW _MMIO(0x2310 + 4) 587 #define IA_PRIMITIVES_COUNT _MMIO(0x2318) 588 #define IA_PRIMITIVES_COUNT_UDW _MMIO(0x2318 + 4) 589 #define VS_INVOCATION_COUNT _MMIO(0x2320) 590 #define VS_INVOCATION_COUNT_UDW _MMIO(0x2320 + 4) 591 #define GS_INVOCATION_COUNT _MMIO(0x2328) 592 #define GS_INVOCATION_COUNT_UDW _MMIO(0x2328 + 4) 593 #define GS_PRIMITIVES_COUNT _MMIO(0x2330) 594 #define GS_PRIMITIVES_COUNT_UDW _MMIO(0x2330 + 4) 595 #define CL_INVOCATION_COUNT _MMIO(0x2338) 596 #define CL_INVOCATION_COUNT_UDW _MMIO(0x2338 + 4) 597 #define CL_PRIMITIVES_COUNT _MMIO(0x2340) 598 #define CL_PRIMITIVES_COUNT_UDW _MMIO(0x2340 + 4) 599 #define PS_INVOCATION_COUNT _MMIO(0x2348) 600 #define PS_INVOCATION_COUNT_UDW _MMIO(0x2348 + 4) 601 #define PS_DEPTH_COUNT _MMIO(0x2350) 602 #define PS_DEPTH_COUNT_UDW _MMIO(0x2350 + 4) 603 604 /* There are the 4 64-bit counter registers, one for each stream output */ 605 #define GEN7_SO_NUM_PRIMS_WRITTEN(n) _MMIO(0x5200 + (n) * 8) 606 #define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n) _MMIO(0x5200 + (n) * 8 + 4) 607 608 #define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8) 609 #define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4) 610 611 #define GEN7_3DPRIM_END_OFFSET _MMIO(0x2420) 612 #define GEN7_3DPRIM_START_VERTEX _MMIO(0x2430) 613 #define GEN7_3DPRIM_VERTEX_COUNT _MMIO(0x2434) 614 #define GEN7_3DPRIM_INSTANCE_COUNT _MMIO(0x2438) 615 #define GEN7_3DPRIM_START_INSTANCE _MMIO(0x243C) 616 #define GEN7_3DPRIM_BASE_VERTEX _MMIO(0x2440) 617 618 #define GEN7_GPGPU_DISPATCHDIMX _MMIO(0x2500) 619 #define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504) 620 #define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508) 621 622 /* There are the 16 64-bit CS General Purpose Registers */ 623 #define HSW_CS_GPR(n) _MMIO(0x2600 + (n) * 8) 624 #define HSW_CS_GPR_UDW(n) _MMIO(0x2600 + (n) * 8 + 4) 625 626 #define GEN7_OACONTROL _MMIO(0x2360) 627 #define GEN7_OACONTROL_CTX_MASK 0xFFFFF000 628 #define GEN7_OACONTROL_TIMER_PERIOD_MASK 0x3F 629 #define GEN7_OACONTROL_TIMER_PERIOD_SHIFT 6 630 #define GEN7_OACONTROL_TIMER_ENABLE (1 << 5) 631 #define GEN7_OACONTROL_FORMAT_A13 (0 << 2) 632 #define GEN7_OACONTROL_FORMAT_A29 (1 << 2) 633 #define GEN7_OACONTROL_FORMAT_A13_B8_C8 (2 << 2) 634 #define GEN7_OACONTROL_FORMAT_A29_B8_C8 (3 << 2) 635 #define GEN7_OACONTROL_FORMAT_B4_C8 (4 << 2) 636 #define GEN7_OACONTROL_FORMAT_A45_B8_C8 (5 << 2) 637 #define GEN7_OACONTROL_FORMAT_B4_C8_A16 (6 << 2) 638 #define GEN7_OACONTROL_FORMAT_C4_B8 (7 << 2) 639 #define GEN7_OACONTROL_FORMAT_SHIFT 2 640 #define GEN7_OACONTROL_PER_CTX_ENABLE (1 << 1) 641 #define GEN7_OACONTROL_ENABLE (1 << 0) 642 643 #define GEN8_OACTXID _MMIO(0x2364) 644 645 #define GEN8_OA_DEBUG _MMIO(0x2B04) 646 #define GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1 << 5) 647 #define GEN9_OA_DEBUG_INCLUDE_CLK_RATIO (1 << 6) 648 #define GEN9_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2) 649 #define GEN9_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1) 650 651 #define GEN8_OACONTROL _MMIO(0x2B00) 652 #define GEN8_OA_REPORT_FORMAT_A12 (0 << 2) 653 #define GEN8_OA_REPORT_FORMAT_A12_B8_C8 (2 << 2) 654 #define GEN8_OA_REPORT_FORMAT_A36_B8_C8 (5 << 2) 655 #define GEN8_OA_REPORT_FORMAT_C4_B8 (7 << 2) 656 #define GEN8_OA_REPORT_FORMAT_SHIFT 2 657 #define GEN8_OA_SPECIFIC_CONTEXT_ENABLE (1 << 1) 658 #define GEN8_OA_COUNTER_ENABLE (1 << 0) 659 660 #define GEN8_OACTXCONTROL _MMIO(0x2360) 661 #define GEN8_OA_TIMER_PERIOD_MASK 0x3F 662 #define GEN8_OA_TIMER_PERIOD_SHIFT 2 663 #define GEN8_OA_TIMER_ENABLE (1 << 1) 664 #define GEN8_OA_COUNTER_RESUME (1 << 0) 665 666 #define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */ 667 #define GEN7_OABUFFER_OVERRUN_DISABLE (1 << 3) 668 #define GEN7_OABUFFER_EDGE_TRIGGER (1 << 2) 669 #define GEN7_OABUFFER_STOP_RESUME_ENABLE (1 << 1) 670 #define GEN7_OABUFFER_RESUME (1 << 0) 671 672 #define GEN8_OABUFFER_UDW _MMIO(0x23b4) 673 #define GEN8_OABUFFER _MMIO(0x2b14) 674 #define GEN8_OABUFFER_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */ 675 676 #define GEN7_OASTATUS1 _MMIO(0x2364) 677 #define GEN7_OASTATUS1_TAIL_MASK 0xffffffc0 678 #define GEN7_OASTATUS1_COUNTER_OVERFLOW (1 << 2) 679 #define GEN7_OASTATUS1_OABUFFER_OVERFLOW (1 << 1) 680 #define GEN7_OASTATUS1_REPORT_LOST (1 << 0) 681 682 #define GEN7_OASTATUS2 _MMIO(0x2368) 683 #define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0 684 #define GEN7_OASTATUS2_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */ 685 686 #define GEN8_OASTATUS _MMIO(0x2b08) 687 #define GEN8_OASTATUS_OVERRUN_STATUS (1 << 3) 688 #define GEN8_OASTATUS_COUNTER_OVERFLOW (1 << 2) 689 #define GEN8_OASTATUS_OABUFFER_OVERFLOW (1 << 1) 690 #define GEN8_OASTATUS_REPORT_LOST (1 << 0) 691 692 #define GEN8_OAHEADPTR _MMIO(0x2B0C) 693 #define GEN8_OAHEADPTR_MASK 0xffffffc0 694 #define GEN8_OATAILPTR _MMIO(0x2B10) 695 #define GEN8_OATAILPTR_MASK 0xffffffc0 696 697 #define OABUFFER_SIZE_128K (0 << 3) 698 #define OABUFFER_SIZE_256K (1 << 3) 699 #define OABUFFER_SIZE_512K (2 << 3) 700 #define OABUFFER_SIZE_1M (3 << 3) 701 #define OABUFFER_SIZE_2M (4 << 3) 702 #define OABUFFER_SIZE_4M (5 << 3) 703 #define OABUFFER_SIZE_8M (6 << 3) 704 #define OABUFFER_SIZE_16M (7 << 3) 705 706 /* 707 * Flexible, Aggregate EU Counter Registers. 708 * Note: these aren't contiguous 709 */ 710 #define EU_PERF_CNTL0 _MMIO(0xe458) 711 #define EU_PERF_CNTL1 _MMIO(0xe558) 712 #define EU_PERF_CNTL2 _MMIO(0xe658) 713 #define EU_PERF_CNTL3 _MMIO(0xe758) 714 #define EU_PERF_CNTL4 _MMIO(0xe45c) 715 #define EU_PERF_CNTL5 _MMIO(0xe55c) 716 #define EU_PERF_CNTL6 _MMIO(0xe65c) 717 718 /* 719 * OA Boolean state 720 */ 721 722 #define OASTARTTRIG1 _MMIO(0x2710) 723 #define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ 0xffff0000 724 #define OASTARTTRIG1_THRESHOLD_MASK 0xffff 725 726 #define OASTARTTRIG2 _MMIO(0x2714) 727 #define OASTARTTRIG2_INVERT_A_0 (1 << 0) 728 #define OASTARTTRIG2_INVERT_A_1 (1 << 1) 729 #define OASTARTTRIG2_INVERT_A_2 (1 << 2) 730 #define OASTARTTRIG2_INVERT_A_3 (1 << 3) 731 #define OASTARTTRIG2_INVERT_A_4 (1 << 4) 732 #define OASTARTTRIG2_INVERT_A_5 (1 << 5) 733 #define OASTARTTRIG2_INVERT_A_6 (1 << 6) 734 #define OASTARTTRIG2_INVERT_A_7 (1 << 7) 735 #define OASTARTTRIG2_INVERT_A_8 (1 << 8) 736 #define OASTARTTRIG2_INVERT_A_9 (1 << 9) 737 #define OASTARTTRIG2_INVERT_A_10 (1 << 10) 738 #define OASTARTTRIG2_INVERT_A_11 (1 << 11) 739 #define OASTARTTRIG2_INVERT_A_12 (1 << 12) 740 #define OASTARTTRIG2_INVERT_A_13 (1 << 13) 741 #define OASTARTTRIG2_INVERT_A_14 (1 << 14) 742 #define OASTARTTRIG2_INVERT_A_15 (1 << 15) 743 #define OASTARTTRIG2_INVERT_B_0 (1 << 16) 744 #define OASTARTTRIG2_INVERT_B_1 (1 << 17) 745 #define OASTARTTRIG2_INVERT_B_2 (1 << 18) 746 #define OASTARTTRIG2_INVERT_B_3 (1 << 19) 747 #define OASTARTTRIG2_INVERT_C_0 (1 << 20) 748 #define OASTARTTRIG2_INVERT_C_1 (1 << 21) 749 #define OASTARTTRIG2_INVERT_D_0 (1 << 22) 750 #define OASTARTTRIG2_THRESHOLD_ENABLE (1 << 23) 751 #define OASTARTTRIG2_START_TRIG_FLAG_MBZ (1 << 24) 752 #define OASTARTTRIG2_EVENT_SELECT_0 (1 << 28) 753 #define OASTARTTRIG2_EVENT_SELECT_1 (1 << 29) 754 #define OASTARTTRIG2_EVENT_SELECT_2 (1 << 30) 755 #define OASTARTTRIG2_EVENT_SELECT_3 (1 << 31) 756 757 #define OASTARTTRIG3 _MMIO(0x2718) 758 #define OASTARTTRIG3_NOA_SELECT_MASK 0xf 759 #define OASTARTTRIG3_NOA_SELECT_8_SHIFT 0 760 #define OASTARTTRIG3_NOA_SELECT_9_SHIFT 4 761 #define OASTARTTRIG3_NOA_SELECT_10_SHIFT 8 762 #define OASTARTTRIG3_NOA_SELECT_11_SHIFT 12 763 #define OASTARTTRIG3_NOA_SELECT_12_SHIFT 16 764 #define OASTARTTRIG3_NOA_SELECT_13_SHIFT 20 765 #define OASTARTTRIG3_NOA_SELECT_14_SHIFT 24 766 #define OASTARTTRIG3_NOA_SELECT_15_SHIFT 28 767 768 #define OASTARTTRIG4 _MMIO(0x271c) 769 #define OASTARTTRIG4_NOA_SELECT_MASK 0xf 770 #define OASTARTTRIG4_NOA_SELECT_0_SHIFT 0 771 #define OASTARTTRIG4_NOA_SELECT_1_SHIFT 4 772 #define OASTARTTRIG4_NOA_SELECT_2_SHIFT 8 773 #define OASTARTTRIG4_NOA_SELECT_3_SHIFT 12 774 #define OASTARTTRIG4_NOA_SELECT_4_SHIFT 16 775 #define OASTARTTRIG4_NOA_SELECT_5_SHIFT 20 776 #define OASTARTTRIG4_NOA_SELECT_6_SHIFT 24 777 #define OASTARTTRIG4_NOA_SELECT_7_SHIFT 28 778 779 #define OASTARTTRIG5 _MMIO(0x2720) 780 #define OASTARTTRIG5_THRESHOLD_COUNT_MASK_MBZ 0xffff0000 781 #define OASTARTTRIG5_THRESHOLD_MASK 0xffff 782 783 #define OASTARTTRIG6 _MMIO(0x2724) 784 #define OASTARTTRIG6_INVERT_A_0 (1 << 0) 785 #define OASTARTTRIG6_INVERT_A_1 (1 << 1) 786 #define OASTARTTRIG6_INVERT_A_2 (1 << 2) 787 #define OASTARTTRIG6_INVERT_A_3 (1 << 3) 788 #define OASTARTTRIG6_INVERT_A_4 (1 << 4) 789 #define OASTARTTRIG6_INVERT_A_5 (1 << 5) 790 #define OASTARTTRIG6_INVERT_A_6 (1 << 6) 791 #define OASTARTTRIG6_INVERT_A_7 (1 << 7) 792 #define OASTARTTRIG6_INVERT_A_8 (1 << 8) 793 #define OASTARTTRIG6_INVERT_A_9 (1 << 9) 794 #define OASTARTTRIG6_INVERT_A_10 (1 << 10) 795 #define OASTARTTRIG6_INVERT_A_11 (1 << 11) 796 #define OASTARTTRIG6_INVERT_A_12 (1 << 12) 797 #define OASTARTTRIG6_INVERT_A_13 (1 << 13) 798 #define OASTARTTRIG6_INVERT_A_14 (1 << 14) 799 #define OASTARTTRIG6_INVERT_A_15 (1 << 15) 800 #define OASTARTTRIG6_INVERT_B_0 (1 << 16) 801 #define OASTARTTRIG6_INVERT_B_1 (1 << 17) 802 #define OASTARTTRIG6_INVERT_B_2 (1 << 18) 803 #define OASTARTTRIG6_INVERT_B_3 (1 << 19) 804 #define OASTARTTRIG6_INVERT_C_0 (1 << 20) 805 #define OASTARTTRIG6_INVERT_C_1 (1 << 21) 806 #define OASTARTTRIG6_INVERT_D_0 (1 << 22) 807 #define OASTARTTRIG6_THRESHOLD_ENABLE (1 << 23) 808 #define OASTARTTRIG6_START_TRIG_FLAG_MBZ (1 << 24) 809 #define OASTARTTRIG6_EVENT_SELECT_4 (1 << 28) 810 #define OASTARTTRIG6_EVENT_SELECT_5 (1 << 29) 811 #define OASTARTTRIG6_EVENT_SELECT_6 (1 << 30) 812 #define OASTARTTRIG6_EVENT_SELECT_7 (1 << 31) 813 814 #define OASTARTTRIG7 _MMIO(0x2728) 815 #define OASTARTTRIG7_NOA_SELECT_MASK 0xf 816 #define OASTARTTRIG7_NOA_SELECT_8_SHIFT 0 817 #define OASTARTTRIG7_NOA_SELECT_9_SHIFT 4 818 #define OASTARTTRIG7_NOA_SELECT_10_SHIFT 8 819 #define OASTARTTRIG7_NOA_SELECT_11_SHIFT 12 820 #define OASTARTTRIG7_NOA_SELECT_12_SHIFT 16 821 #define OASTARTTRIG7_NOA_SELECT_13_SHIFT 20 822 #define OASTARTTRIG7_NOA_SELECT_14_SHIFT 24 823 #define OASTARTTRIG7_NOA_SELECT_15_SHIFT 28 824 825 #define OASTARTTRIG8 _MMIO(0x272c) 826 #define OASTARTTRIG8_NOA_SELECT_MASK 0xf 827 #define OASTARTTRIG8_NOA_SELECT_0_SHIFT 0 828 #define OASTARTTRIG8_NOA_SELECT_1_SHIFT 4 829 #define OASTARTTRIG8_NOA_SELECT_2_SHIFT 8 830 #define OASTARTTRIG8_NOA_SELECT_3_SHIFT 12 831 #define OASTARTTRIG8_NOA_SELECT_4_SHIFT 16 832 #define OASTARTTRIG8_NOA_SELECT_5_SHIFT 20 833 #define OASTARTTRIG8_NOA_SELECT_6_SHIFT 24 834 #define OASTARTTRIG8_NOA_SELECT_7_SHIFT 28 835 836 #define OAREPORTTRIG1 _MMIO(0x2740) 837 #define OAREPORTTRIG1_THRESHOLD_MASK 0xffff 838 #define OAREPORTTRIG1_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */ 839 840 #define OAREPORTTRIG2 _MMIO(0x2744) 841 #define OAREPORTTRIG2_INVERT_A_0 (1 << 0) 842 #define OAREPORTTRIG2_INVERT_A_1 (1 << 1) 843 #define OAREPORTTRIG2_INVERT_A_2 (1 << 2) 844 #define OAREPORTTRIG2_INVERT_A_3 (1 << 3) 845 #define OAREPORTTRIG2_INVERT_A_4 (1 << 4) 846 #define OAREPORTTRIG2_INVERT_A_5 (1 << 5) 847 #define OAREPORTTRIG2_INVERT_A_6 (1 << 6) 848 #define OAREPORTTRIG2_INVERT_A_7 (1 << 7) 849 #define OAREPORTTRIG2_INVERT_A_8 (1 << 8) 850 #define OAREPORTTRIG2_INVERT_A_9 (1 << 9) 851 #define OAREPORTTRIG2_INVERT_A_10 (1 << 10) 852 #define OAREPORTTRIG2_INVERT_A_11 (1 << 11) 853 #define OAREPORTTRIG2_INVERT_A_12 (1 << 12) 854 #define OAREPORTTRIG2_INVERT_A_13 (1 << 13) 855 #define OAREPORTTRIG2_INVERT_A_14 (1 << 14) 856 #define OAREPORTTRIG2_INVERT_A_15 (1 << 15) 857 #define OAREPORTTRIG2_INVERT_B_0 (1 << 16) 858 #define OAREPORTTRIG2_INVERT_B_1 (1 << 17) 859 #define OAREPORTTRIG2_INVERT_B_2 (1 << 18) 860 #define OAREPORTTRIG2_INVERT_B_3 (1 << 19) 861 #define OAREPORTTRIG2_INVERT_C_0 (1 << 20) 862 #define OAREPORTTRIG2_INVERT_C_1 (1 << 21) 863 #define OAREPORTTRIG2_INVERT_D_0 (1 << 22) 864 #define OAREPORTTRIG2_THRESHOLD_ENABLE (1 << 23) 865 #define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1 << 31) 866 867 #define OAREPORTTRIG3 _MMIO(0x2748) 868 #define OAREPORTTRIG3_NOA_SELECT_MASK 0xf 869 #define OAREPORTTRIG3_NOA_SELECT_8_SHIFT 0 870 #define OAREPORTTRIG3_NOA_SELECT_9_SHIFT 4 871 #define OAREPORTTRIG3_NOA_SELECT_10_SHIFT 8 872 #define OAREPORTTRIG3_NOA_SELECT_11_SHIFT 12 873 #define OAREPORTTRIG3_NOA_SELECT_12_SHIFT 16 874 #define OAREPORTTRIG3_NOA_SELECT_13_SHIFT 20 875 #define OAREPORTTRIG3_NOA_SELECT_14_SHIFT 24 876 #define OAREPORTTRIG3_NOA_SELECT_15_SHIFT 28 877 878 #define OAREPORTTRIG4 _MMIO(0x274c) 879 #define OAREPORTTRIG4_NOA_SELECT_MASK 0xf 880 #define OAREPORTTRIG4_NOA_SELECT_0_SHIFT 0 881 #define OAREPORTTRIG4_NOA_SELECT_1_SHIFT 4 882 #define OAREPORTTRIG4_NOA_SELECT_2_SHIFT 8 883 #define OAREPORTTRIG4_NOA_SELECT_3_SHIFT 12 884 #define OAREPORTTRIG4_NOA_SELECT_4_SHIFT 16 885 #define OAREPORTTRIG4_NOA_SELECT_5_SHIFT 20 886 #define OAREPORTTRIG4_NOA_SELECT_6_SHIFT 24 887 #define OAREPORTTRIG4_NOA_SELECT_7_SHIFT 28 888 889 #define OAREPORTTRIG5 _MMIO(0x2750) 890 #define OAREPORTTRIG5_THRESHOLD_MASK 0xffff 891 #define OAREPORTTRIG5_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */ 892 893 #define OAREPORTTRIG6 _MMIO(0x2754) 894 #define OAREPORTTRIG6_INVERT_A_0 (1 << 0) 895 #define OAREPORTTRIG6_INVERT_A_1 (1 << 1) 896 #define OAREPORTTRIG6_INVERT_A_2 (1 << 2) 897 #define OAREPORTTRIG6_INVERT_A_3 (1 << 3) 898 #define OAREPORTTRIG6_INVERT_A_4 (1 << 4) 899 #define OAREPORTTRIG6_INVERT_A_5 (1 << 5) 900 #define OAREPORTTRIG6_INVERT_A_6 (1 << 6) 901 #define OAREPORTTRIG6_INVERT_A_7 (1 << 7) 902 #define OAREPORTTRIG6_INVERT_A_8 (1 << 8) 903 #define OAREPORTTRIG6_INVERT_A_9 (1 << 9) 904 #define OAREPORTTRIG6_INVERT_A_10 (1 << 10) 905 #define OAREPORTTRIG6_INVERT_A_11 (1 << 11) 906 #define OAREPORTTRIG6_INVERT_A_12 (1 << 12) 907 #define OAREPORTTRIG6_INVERT_A_13 (1 << 13) 908 #define OAREPORTTRIG6_INVERT_A_14 (1 << 14) 909 #define OAREPORTTRIG6_INVERT_A_15 (1 << 15) 910 #define OAREPORTTRIG6_INVERT_B_0 (1 << 16) 911 #define OAREPORTTRIG6_INVERT_B_1 (1 << 17) 912 #define OAREPORTTRIG6_INVERT_B_2 (1 << 18) 913 #define OAREPORTTRIG6_INVERT_B_3 (1 << 19) 914 #define OAREPORTTRIG6_INVERT_C_0 (1 << 20) 915 #define OAREPORTTRIG6_INVERT_C_1 (1 << 21) 916 #define OAREPORTTRIG6_INVERT_D_0 (1 << 22) 917 #define OAREPORTTRIG6_THRESHOLD_ENABLE (1 << 23) 918 #define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1 << 31) 919 920 #define OAREPORTTRIG7 _MMIO(0x2758) 921 #define OAREPORTTRIG7_NOA_SELECT_MASK 0xf 922 #define OAREPORTTRIG7_NOA_SELECT_8_SHIFT 0 923 #define OAREPORTTRIG7_NOA_SELECT_9_SHIFT 4 924 #define OAREPORTTRIG7_NOA_SELECT_10_SHIFT 8 925 #define OAREPORTTRIG7_NOA_SELECT_11_SHIFT 12 926 #define OAREPORTTRIG7_NOA_SELECT_12_SHIFT 16 927 #define OAREPORTTRIG7_NOA_SELECT_13_SHIFT 20 928 #define OAREPORTTRIG7_NOA_SELECT_14_SHIFT 24 929 #define OAREPORTTRIG7_NOA_SELECT_15_SHIFT 28 930 931 #define OAREPORTTRIG8 _MMIO(0x275c) 932 #define OAREPORTTRIG8_NOA_SELECT_MASK 0xf 933 #define OAREPORTTRIG8_NOA_SELECT_0_SHIFT 0 934 #define OAREPORTTRIG8_NOA_SELECT_1_SHIFT 4 935 #define OAREPORTTRIG8_NOA_SELECT_2_SHIFT 8 936 #define OAREPORTTRIG8_NOA_SELECT_3_SHIFT 12 937 #define OAREPORTTRIG8_NOA_SELECT_4_SHIFT 16 938 #define OAREPORTTRIG8_NOA_SELECT_5_SHIFT 20 939 #define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24 940 #define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28 941 942 /* CECX_0 */ 943 #define OACEC_COMPARE_LESS_OR_EQUAL 6 944 #define OACEC_COMPARE_NOT_EQUAL 5 945 #define OACEC_COMPARE_LESS_THAN 4 946 #define OACEC_COMPARE_GREATER_OR_EQUAL 3 947 #define OACEC_COMPARE_EQUAL 2 948 #define OACEC_COMPARE_GREATER_THAN 1 949 #define OACEC_COMPARE_ANY_EQUAL 0 950 951 #define OACEC_COMPARE_VALUE_MASK 0xffff 952 #define OACEC_COMPARE_VALUE_SHIFT 3 953 954 #define OACEC_SELECT_NOA (0 << 19) 955 #define OACEC_SELECT_PREV (1 << 19) 956 #define OACEC_SELECT_BOOLEAN (2 << 19) 957 958 /* CECX_1 */ 959 #define OACEC_MASK_MASK 0xffff 960 #define OACEC_CONSIDERATIONS_MASK 0xffff 961 #define OACEC_CONSIDERATIONS_SHIFT 16 962 963 #define OACEC0_0 _MMIO(0x2770) 964 #define OACEC0_1 _MMIO(0x2774) 965 #define OACEC1_0 _MMIO(0x2778) 966 #define OACEC1_1 _MMIO(0x277c) 967 #define OACEC2_0 _MMIO(0x2780) 968 #define OACEC2_1 _MMIO(0x2784) 969 #define OACEC3_0 _MMIO(0x2788) 970 #define OACEC3_1 _MMIO(0x278c) 971 #define OACEC4_0 _MMIO(0x2790) 972 #define OACEC4_1 _MMIO(0x2794) 973 #define OACEC5_0 _MMIO(0x2798) 974 #define OACEC5_1 _MMIO(0x279c) 975 #define OACEC6_0 _MMIO(0x27a0) 976 #define OACEC6_1 _MMIO(0x27a4) 977 #define OACEC7_0 _MMIO(0x27a8) 978 #define OACEC7_1 _MMIO(0x27ac) 979 980 /* OA perf counters */ 981 #define OA_PERFCNT1_LO _MMIO(0x91B8) 982 #define OA_PERFCNT1_HI _MMIO(0x91BC) 983 #define OA_PERFCNT2_LO _MMIO(0x91C0) 984 #define OA_PERFCNT2_HI _MMIO(0x91C4) 985 #define OA_PERFCNT3_LO _MMIO(0x91C8) 986 #define OA_PERFCNT3_HI _MMIO(0x91CC) 987 #define OA_PERFCNT4_LO _MMIO(0x91D8) 988 #define OA_PERFCNT4_HI _MMIO(0x91DC) 989 990 #define OA_PERFMATRIX_LO _MMIO(0x91C8) 991 #define OA_PERFMATRIX_HI _MMIO(0x91CC) 992 993 /* RPM unit config (Gen8+) */ 994 #define RPM_CONFIG0 _MMIO(0x0D00) 995 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3 996 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (1 << GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT) 997 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 0 998 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 1 999 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3 1000 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT) 1001 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0 1002 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 1 1003 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ 2 1004 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3 1005 #define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT 1 1006 #define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT) 1007 1008 #define RPM_CONFIG1 _MMIO(0x0D04) 1009 #define GEN10_GT_NOA_ENABLE (1 << 9) 1010 1011 /* GPM unit config (Gen9+) */ 1012 #define CTC_MODE _MMIO(0xA26C) 1013 #define CTC_SOURCE_PARAMETER_MASK 1 1014 #define CTC_SOURCE_CRYSTAL_CLOCK 0 1015 #define CTC_SOURCE_DIVIDE_LOGIC 1 1016 #define CTC_SHIFT_PARAMETER_SHIFT 1 1017 #define CTC_SHIFT_PARAMETER_MASK (0x3 << CTC_SHIFT_PARAMETER_SHIFT) 1018 1019 /* RCP unit config (Gen8+) */ 1020 #define RCP_CONFIG _MMIO(0x0D08) 1021 1022 /* NOA (HSW) */ 1023 #define HSW_MBVID2_NOA0 _MMIO(0x9E80) 1024 #define HSW_MBVID2_NOA1 _MMIO(0x9E84) 1025 #define HSW_MBVID2_NOA2 _MMIO(0x9E88) 1026 #define HSW_MBVID2_NOA3 _MMIO(0x9E8C) 1027 #define HSW_MBVID2_NOA4 _MMIO(0x9E90) 1028 #define HSW_MBVID2_NOA5 _MMIO(0x9E94) 1029 #define HSW_MBVID2_NOA6 _MMIO(0x9E98) 1030 #define HSW_MBVID2_NOA7 _MMIO(0x9E9C) 1031 #define HSW_MBVID2_NOA8 _MMIO(0x9EA0) 1032 #define HSW_MBVID2_NOA9 _MMIO(0x9EA4) 1033 1034 #define HSW_MBVID2_MISR0 _MMIO(0x9EC0) 1035 1036 /* NOA (Gen8+) */ 1037 #define NOA_CONFIG(i) _MMIO(0x0D0C + (i) * 4) 1038 1039 #define MICRO_BP0_0 _MMIO(0x9800) 1040 #define MICRO_BP0_2 _MMIO(0x9804) 1041 #define MICRO_BP0_1 _MMIO(0x9808) 1042 1043 #define MICRO_BP1_0 _MMIO(0x980C) 1044 #define MICRO_BP1_2 _MMIO(0x9810) 1045 #define MICRO_BP1_1 _MMIO(0x9814) 1046 1047 #define MICRO_BP2_0 _MMIO(0x9818) 1048 #define MICRO_BP2_2 _MMIO(0x981C) 1049 #define MICRO_BP2_1 _MMIO(0x9820) 1050 1051 #define MICRO_BP3_0 _MMIO(0x9824) 1052 #define MICRO_BP3_2 _MMIO(0x9828) 1053 #define MICRO_BP3_1 _MMIO(0x982C) 1054 1055 #define MICRO_BP_TRIGGER _MMIO(0x9830) 1056 #define MICRO_BP3_COUNT_STATUS01 _MMIO(0x9834) 1057 #define MICRO_BP3_COUNT_STATUS23 _MMIO(0x9838) 1058 #define MICRO_BP_FIRED_ARMED _MMIO(0x983C) 1059 1060 #define GDT_CHICKEN_BITS _MMIO(0x9840) 1061 #define GT_NOA_ENABLE 0x00000080 1062 1063 #define NOA_DATA _MMIO(0x986C) 1064 #define NOA_WRITE _MMIO(0x9888) 1065 1066 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 1067 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068 1068 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL) 1069 1070 /* 1071 * Reset registers 1072 */ 1073 #define DEBUG_RESET_I830 _MMIO(0x6070) 1074 #define DEBUG_RESET_FULL (1 << 7) 1075 #define DEBUG_RESET_RENDER (1 << 8) 1076 #define DEBUG_RESET_DISPLAY (1 << 9) 1077 1078 /* 1079 * IOSF sideband 1080 */ 1081 #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100) 1082 #define IOSF_DEVFN_SHIFT 24 1083 #define IOSF_OPCODE_SHIFT 16 1084 #define IOSF_PORT_SHIFT 8 1085 #define IOSF_BYTE_ENABLES_SHIFT 4 1086 #define IOSF_BAR_SHIFT 1 1087 #define IOSF_SB_BUSY (1 << 0) 1088 #define IOSF_PORT_BUNIT 0x03 1089 #define IOSF_PORT_PUNIT 0x04 1090 #define IOSF_PORT_NC 0x11 1091 #define IOSF_PORT_DPIO 0x12 1092 #define IOSF_PORT_GPIO_NC 0x13 1093 #define IOSF_PORT_CCK 0x14 1094 #define IOSF_PORT_DPIO_2 0x1a 1095 #define IOSF_PORT_FLISDSI 0x1b 1096 #define IOSF_PORT_GPIO_SC 0x48 1097 #define IOSF_PORT_GPIO_SUS 0xa8 1098 #define IOSF_PORT_CCU 0xa9 1099 #define CHV_IOSF_PORT_GPIO_N 0x13 1100 #define CHV_IOSF_PORT_GPIO_SE 0x48 1101 #define CHV_IOSF_PORT_GPIO_E 0xa8 1102 #define CHV_IOSF_PORT_GPIO_SW 0xb2 1103 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104) 1104 #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108) 1105 1106 /* See configdb bunit SB addr map */ 1107 #define BUNIT_REG_BISOC 0x11 1108 1109 /* PUNIT_REG_*SSPM0 */ 1110 #define _SSPM0_SSC(val) ((val) << 0) 1111 #define SSPM0_SSC_MASK _SSPM0_SSC(0x3) 1112 #define SSPM0_SSC_PWR_ON _SSPM0_SSC(0x0) 1113 #define SSPM0_SSC_CLK_GATE _SSPM0_SSC(0x1) 1114 #define SSPM0_SSC_RESET _SSPM0_SSC(0x2) 1115 #define SSPM0_SSC_PWR_GATE _SSPM0_SSC(0x3) 1116 #define _SSPM0_SSS(val) ((val) << 24) 1117 #define SSPM0_SSS_MASK _SSPM0_SSS(0x3) 1118 #define SSPM0_SSS_PWR_ON _SSPM0_SSS(0x0) 1119 #define SSPM0_SSS_CLK_GATE _SSPM0_SSS(0x1) 1120 #define SSPM0_SSS_RESET _SSPM0_SSS(0x2) 1121 #define SSPM0_SSS_PWR_GATE _SSPM0_SSS(0x3) 1122 1123 /* PUNIT_REG_*SSPM1 */ 1124 #define SSPM1_FREQSTAT_SHIFT 24 1125 #define SSPM1_FREQSTAT_MASK (0x1f << SSPM1_FREQSTAT_SHIFT) 1126 #define SSPM1_FREQGUAR_SHIFT 8 1127 #define SSPM1_FREQGUAR_MASK (0x1f << SSPM1_FREQGUAR_SHIFT) 1128 #define SSPM1_FREQ_SHIFT 0 1129 #define SSPM1_FREQ_MASK (0x1f << SSPM1_FREQ_SHIFT) 1130 1131 #define PUNIT_REG_VEDSSPM0 0x32 1132 #define PUNIT_REG_VEDSSPM1 0x33 1133 1134 #define PUNIT_REG_DSPSSPM 0x36 1135 #define DSPFREQSTAT_SHIFT_CHV 24 1136 #define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV) 1137 #define DSPFREQGUAR_SHIFT_CHV 8 1138 #define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV) 1139 #define DSPFREQSTAT_SHIFT 30 1140 #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT) 1141 #define DSPFREQGUAR_SHIFT 14 1142 #define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT) 1143 #define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */ 1144 #define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */ 1145 #define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */ 1146 #define _DP_SSC(val, pipe) ((val) << (2 * (pipe))) 1147 #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe)) 1148 #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe)) 1149 #define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe)) 1150 #define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe)) 1151 #define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe)) 1152 #define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16)) 1153 #define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe)) 1154 #define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe)) 1155 #define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe)) 1156 #define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe)) 1157 #define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe)) 1158 1159 #define PUNIT_REG_ISPSSPM0 0x39 1160 #define PUNIT_REG_ISPSSPM1 0x3a 1161 1162 /* 1163 * i915_power_well_id: 1164 * 1165 * IDs used to look up power wells. Power wells accessed directly bypassing 1166 * the power domains framework must be assigned a unique ID. The rest of power 1167 * wells must be assigned DISP_PW_ID_NONE. 1168 */ 1169 enum i915_power_well_id { 1170 DISP_PW_ID_NONE, 1171 1172 VLV_DISP_PW_DISP2D, 1173 BXT_DISP_PW_DPIO_CMN_A, 1174 VLV_DISP_PW_DPIO_CMN_BC, 1175 GLK_DISP_PW_DPIO_CMN_C, 1176 CHV_DISP_PW_DPIO_CMN_D, 1177 HSW_DISP_PW_GLOBAL, 1178 SKL_DISP_PW_MISC_IO, 1179 SKL_DISP_PW_1, 1180 SKL_DISP_PW_2, 1181 }; 1182 1183 #define PUNIT_REG_PWRGT_CTRL 0x60 1184 #define PUNIT_REG_PWRGT_STATUS 0x61 1185 #define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * 2)) 1186 #define PUNIT_PWRGT_PWR_ON(pw_idx) (0 << ((pw_idx) * 2)) 1187 #define PUNIT_PWRGT_CLK_GATE(pw_idx) (1 << ((pw_idx) * 2)) 1188 #define PUNIT_PWRGT_RESET(pw_idx) (2 << ((pw_idx) * 2)) 1189 #define PUNIT_PWRGT_PWR_GATE(pw_idx) (3 << ((pw_idx) * 2)) 1190 1191 #define PUNIT_PWGT_IDX_RENDER 0 1192 #define PUNIT_PWGT_IDX_MEDIA 1 1193 #define PUNIT_PWGT_IDX_DISP2D 3 1194 #define PUNIT_PWGT_IDX_DPIO_CMN_BC 5 1195 #define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01 6 1196 #define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23 7 1197 #define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01 8 1198 #define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23 9 1199 #define PUNIT_PWGT_IDX_DPIO_RX0 10 1200 #define PUNIT_PWGT_IDX_DPIO_RX1 11 1201 #define PUNIT_PWGT_IDX_DPIO_CMN_D 12 1202 1203 #define PUNIT_REG_GPU_LFM 0xd3 1204 #define PUNIT_REG_GPU_FREQ_REQ 0xd4 1205 #define PUNIT_REG_GPU_FREQ_STS 0xd8 1206 #define GPLLENABLE (1 << 4) 1207 #define GENFREQSTATUS (1 << 0) 1208 #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc 1209 #define PUNIT_REG_CZ_TIMESTAMP 0xce 1210 1211 #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */ 1212 #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */ 1213 1214 #define FB_GFX_FMAX_AT_VMAX_FUSE 0x136 1215 #define FB_GFX_FREQ_FUSE_MASK 0xff 1216 #define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24 1217 #define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16 1218 #define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8 1219 1220 #define FB_GFX_FMIN_AT_VMIN_FUSE 0x137 1221 #define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8 1222 1223 #define PUNIT_REG_DDR_SETUP2 0x139 1224 #define FORCE_DDR_FREQ_REQ_ACK (1 << 8) 1225 #define FORCE_DDR_LOW_FREQ (1 << 1) 1226 #define FORCE_DDR_HIGH_FREQ (1 << 0) 1227 1228 #define PUNIT_GPU_STATUS_REG 0xdb 1229 #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16 1230 #define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff 1231 #define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8 1232 #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff 1233 1234 #define PUNIT_GPU_DUTYCYCLE_REG 0xdf 1235 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8 1236 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff 1237 1238 #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c 1239 #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3 1240 #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8 1241 #define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11 1242 #define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800 1243 #define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34 1244 #define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007 1245 #define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30 1246 #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27 1247 #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 1248 1249 #define VLV_TURBO_SOC_OVERRIDE 0x04 1250 #define VLV_OVERRIDE_EN 1 1251 #define VLV_SOC_TDP_EN (1 << 1) 1252 #define VLV_BIAS_CPU_125_SOC_875 (6 << 2) 1253 #define CHV_BIAS_CPU_50_SOC_50 (3 << 2) 1254 1255 /* vlv2 north clock has */ 1256 #define CCK_FUSE_REG 0x8 1257 #define CCK_FUSE_HPLL_FREQ_MASK 0x3 1258 #define CCK_REG_DSI_PLL_FUSE 0x44 1259 #define CCK_REG_DSI_PLL_CONTROL 0x48 1260 #define DSI_PLL_VCO_EN (1 << 31) 1261 #define DSI_PLL_LDO_GATE (1 << 30) 1262 #define DSI_PLL_P1_POST_DIV_SHIFT 17 1263 #define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17) 1264 #define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13) 1265 #define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12) 1266 #define DSI_PLL_MUX_MASK (3 << 9) 1267 #define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10) 1268 #define DSI_PLL_MUX_DSI0_CCK (1 << 10) 1269 #define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9) 1270 #define DSI_PLL_MUX_DSI1_CCK (1 << 9) 1271 #define DSI_PLL_CLK_GATE_MASK (0xf << 5) 1272 #define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8) 1273 #define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7) 1274 #define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6) 1275 #define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5) 1276 #define DSI_PLL_LOCK (1 << 0) 1277 #define CCK_REG_DSI_PLL_DIVIDER 0x4c 1278 #define DSI_PLL_LFSR (1 << 31) 1279 #define DSI_PLL_FRACTION_EN (1 << 30) 1280 #define DSI_PLL_FRAC_COUNTER_SHIFT 27 1281 #define DSI_PLL_FRAC_COUNTER_MASK (7 << 27) 1282 #define DSI_PLL_USYNC_CNT_SHIFT 18 1283 #define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18) 1284 #define DSI_PLL_N1_DIV_SHIFT 16 1285 #define DSI_PLL_N1_DIV_MASK (3 << 16) 1286 #define DSI_PLL_M1_DIV_SHIFT 0 1287 #define DSI_PLL_M1_DIV_MASK (0x1ff << 0) 1288 #define CCK_CZ_CLOCK_CONTROL 0x62 1289 #define CCK_GPLL_CLOCK_CONTROL 0x67 1290 #define CCK_DISPLAY_CLOCK_CONTROL 0x6b 1291 #define CCK_DISPLAY_REF_CLOCK_CONTROL 0x6c 1292 #define CCK_TRUNK_FORCE_ON (1 << 17) 1293 #define CCK_TRUNK_FORCE_OFF (1 << 16) 1294 #define CCK_FREQUENCY_STATUS (0x1f << 8) 1295 #define CCK_FREQUENCY_STATUS_SHIFT 8 1296 #define CCK_FREQUENCY_VALUES (0x1f << 0) 1297 1298 /* DPIO registers */ 1299 #define DPIO_DEVFN 0 1300 1301 #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110) 1302 #define DPIO_MODSEL1 (1 << 3) /* if ref clk b == 27 */ 1303 #define DPIO_MODSEL0 (1 << 2) /* if ref clk a == 27 */ 1304 #define DPIO_SFR_BYPASS (1 << 1) 1305 #define DPIO_CMNRST (1 << 0) 1306 1307 #define DPIO_PHY(pipe) ((pipe) >> 1) 1308 #define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy]) 1309 1310 /* 1311 * Per pipe/PLL DPIO regs 1312 */ 1313 #define _VLV_PLL_DW3_CH0 0x800c 1314 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ 1315 #define DPIO_POST_DIV_DAC 0 1316 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ 1317 #define DPIO_POST_DIV_LVDS1 2 1318 #define DPIO_POST_DIV_LVDS2 3 1319 #define DPIO_K_SHIFT (24) /* 4 bits */ 1320 #define DPIO_P1_SHIFT (21) /* 3 bits */ 1321 #define DPIO_P2_SHIFT (16) /* 5 bits */ 1322 #define DPIO_N_SHIFT (12) /* 4 bits */ 1323 #define DPIO_ENABLE_CALIBRATION (1 << 11) 1324 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */ 1325 #define DPIO_M2DIV_MASK 0xff 1326 #define _VLV_PLL_DW3_CH1 0x802c 1327 #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1) 1328 1329 #define _VLV_PLL_DW5_CH0 0x8014 1330 #define DPIO_REFSEL_OVERRIDE 27 1331 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ 1332 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ 1333 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ 1334 #define DPIO_PLL_REFCLK_SEL_MASK 3 1335 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ 1336 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ 1337 #define _VLV_PLL_DW5_CH1 0x8034 1338 #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1) 1339 1340 #define _VLV_PLL_DW7_CH0 0x801c 1341 #define _VLV_PLL_DW7_CH1 0x803c 1342 #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1) 1343 1344 #define _VLV_PLL_DW8_CH0 0x8040 1345 #define _VLV_PLL_DW8_CH1 0x8060 1346 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1) 1347 1348 #define VLV_PLL_DW9_BCAST 0xc044 1349 #define _VLV_PLL_DW9_CH0 0x8044 1350 #define _VLV_PLL_DW9_CH1 0x8064 1351 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1) 1352 1353 #define _VLV_PLL_DW10_CH0 0x8048 1354 #define _VLV_PLL_DW10_CH1 0x8068 1355 #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1) 1356 1357 #define _VLV_PLL_DW11_CH0 0x804c 1358 #define _VLV_PLL_DW11_CH1 0x806c 1359 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1) 1360 1361 /* Spec for ref block start counts at DW10 */ 1362 #define VLV_REF_DW13 0x80ac 1363 1364 #define VLV_CMN_DW0 0x8100 1365 1366 /* 1367 * Per DDI channel DPIO regs 1368 */ 1369 1370 #define _VLV_PCS_DW0_CH0 0x8200 1371 #define _VLV_PCS_DW0_CH1 0x8400 1372 #define DPIO_PCS_TX_LANE2_RESET (1 << 16) 1373 #define DPIO_PCS_TX_LANE1_RESET (1 << 7) 1374 #define DPIO_LEFT_TXFIFO_RST_MASTER2 (1 << 4) 1375 #define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3) 1376 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1) 1377 1378 #define _VLV_PCS01_DW0_CH0 0x200 1379 #define _VLV_PCS23_DW0_CH0 0x400 1380 #define _VLV_PCS01_DW0_CH1 0x2600 1381 #define _VLV_PCS23_DW0_CH1 0x2800 1382 #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1) 1383 #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1) 1384 1385 #define _VLV_PCS_DW1_CH0 0x8204 1386 #define _VLV_PCS_DW1_CH1 0x8404 1387 #define CHV_PCS_REQ_SOFTRESET_EN (1 << 23) 1388 #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22) 1389 #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21) 1390 #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6) 1391 #define DPIO_PCS_CLK_SOFT_RESET (1 << 5) 1392 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1) 1393 1394 #define _VLV_PCS01_DW1_CH0 0x204 1395 #define _VLV_PCS23_DW1_CH0 0x404 1396 #define _VLV_PCS01_DW1_CH1 0x2604 1397 #define _VLV_PCS23_DW1_CH1 0x2804 1398 #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1) 1399 #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1) 1400 1401 #define _VLV_PCS_DW8_CH0 0x8220 1402 #define _VLV_PCS_DW8_CH1 0x8420 1403 #define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20) 1404 #define CHV_PCS_USEDCLKCHANNEL (1 << 21) 1405 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1) 1406 1407 #define _VLV_PCS01_DW8_CH0 0x0220 1408 #define _VLV_PCS23_DW8_CH0 0x0420 1409 #define _VLV_PCS01_DW8_CH1 0x2620 1410 #define _VLV_PCS23_DW8_CH1 0x2820 1411 #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1) 1412 #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1) 1413 1414 #define _VLV_PCS_DW9_CH0 0x8224 1415 #define _VLV_PCS_DW9_CH1 0x8424 1416 #define DPIO_PCS_TX2MARGIN_MASK (0x7 << 13) 1417 #define DPIO_PCS_TX2MARGIN_000 (0 << 13) 1418 #define DPIO_PCS_TX2MARGIN_101 (1 << 13) 1419 #define DPIO_PCS_TX1MARGIN_MASK (0x7 << 10) 1420 #define DPIO_PCS_TX1MARGIN_000 (0 << 10) 1421 #define DPIO_PCS_TX1MARGIN_101 (1 << 10) 1422 #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1) 1423 1424 #define _VLV_PCS01_DW9_CH0 0x224 1425 #define _VLV_PCS23_DW9_CH0 0x424 1426 #define _VLV_PCS01_DW9_CH1 0x2624 1427 #define _VLV_PCS23_DW9_CH1 0x2824 1428 #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1) 1429 #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1) 1430 1431 #define _CHV_PCS_DW10_CH0 0x8228 1432 #define _CHV_PCS_DW10_CH1 0x8428 1433 #define DPIO_PCS_SWING_CALC_TX0_TX2 (1 << 30) 1434 #define DPIO_PCS_SWING_CALC_TX1_TX3 (1 << 31) 1435 #define DPIO_PCS_TX2DEEMP_MASK (0xf << 24) 1436 #define DPIO_PCS_TX2DEEMP_9P5 (0 << 24) 1437 #define DPIO_PCS_TX2DEEMP_6P0 (2 << 24) 1438 #define DPIO_PCS_TX1DEEMP_MASK (0xf << 16) 1439 #define DPIO_PCS_TX1DEEMP_9P5 (0 << 16) 1440 #define DPIO_PCS_TX1DEEMP_6P0 (2 << 16) 1441 #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1) 1442 1443 #define _VLV_PCS01_DW10_CH0 0x0228 1444 #define _VLV_PCS23_DW10_CH0 0x0428 1445 #define _VLV_PCS01_DW10_CH1 0x2628 1446 #define _VLV_PCS23_DW10_CH1 0x2828 1447 #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1) 1448 #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1) 1449 1450 #define _VLV_PCS_DW11_CH0 0x822c 1451 #define _VLV_PCS_DW11_CH1 0x842c 1452 #define DPIO_TX2_STAGGER_MASK(x) ((x) << 24) 1453 #define DPIO_LANEDESKEW_STRAP_OVRD (1 << 3) 1454 #define DPIO_LEFT_TXFIFO_RST_MASTER (1 << 1) 1455 #define DPIO_RIGHT_TXFIFO_RST_MASTER (1 << 0) 1456 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1) 1457 1458 #define _VLV_PCS01_DW11_CH0 0x022c 1459 #define _VLV_PCS23_DW11_CH0 0x042c 1460 #define _VLV_PCS01_DW11_CH1 0x262c 1461 #define _VLV_PCS23_DW11_CH1 0x282c 1462 #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1) 1463 #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1) 1464 1465 #define _VLV_PCS01_DW12_CH0 0x0230 1466 #define _VLV_PCS23_DW12_CH0 0x0430 1467 #define _VLV_PCS01_DW12_CH1 0x2630 1468 #define _VLV_PCS23_DW12_CH1 0x2830 1469 #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1) 1470 #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1) 1471 1472 #define _VLV_PCS_DW12_CH0 0x8230 1473 #define _VLV_PCS_DW12_CH1 0x8430 1474 #define DPIO_TX2_STAGGER_MULT(x) ((x) << 20) 1475 #define DPIO_TX1_STAGGER_MULT(x) ((x) << 16) 1476 #define DPIO_TX1_STAGGER_MASK(x) ((x) << 8) 1477 #define DPIO_LANESTAGGER_STRAP_OVRD (1 << 6) 1478 #define DPIO_LANESTAGGER_STRAP(x) ((x) << 0) 1479 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1) 1480 1481 #define _VLV_PCS_DW14_CH0 0x8238 1482 #define _VLV_PCS_DW14_CH1 0x8438 1483 #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1) 1484 1485 #define _VLV_PCS_DW23_CH0 0x825c 1486 #define _VLV_PCS_DW23_CH1 0x845c 1487 #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1) 1488 1489 #define _VLV_TX_DW2_CH0 0x8288 1490 #define _VLV_TX_DW2_CH1 0x8488 1491 #define DPIO_SWING_MARGIN000_SHIFT 16 1492 #define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT) 1493 #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8 1494 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1) 1495 1496 #define _VLV_TX_DW3_CH0 0x828c 1497 #define _VLV_TX_DW3_CH1 0x848c 1498 /* The following bit for CHV phy */ 1499 #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1 << 27) 1500 #define DPIO_SWING_MARGIN101_SHIFT 16 1501 #define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT) 1502 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1) 1503 1504 #define _VLV_TX_DW4_CH0 0x8290 1505 #define _VLV_TX_DW4_CH1 0x8490 1506 #define DPIO_SWING_DEEMPH9P5_SHIFT 24 1507 #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT) 1508 #define DPIO_SWING_DEEMPH6P0_SHIFT 16 1509 #define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT) 1510 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1) 1511 1512 #define _VLV_TX3_DW4_CH0 0x690 1513 #define _VLV_TX3_DW4_CH1 0x2a90 1514 #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1) 1515 1516 #define _VLV_TX_DW5_CH0 0x8294 1517 #define _VLV_TX_DW5_CH1 0x8494 1518 #define DPIO_TX_OCALINIT_EN (1 << 31) 1519 #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1) 1520 1521 #define _VLV_TX_DW11_CH0 0x82ac 1522 #define _VLV_TX_DW11_CH1 0x84ac 1523 #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1) 1524 1525 #define _VLV_TX_DW14_CH0 0x82b8 1526 #define _VLV_TX_DW14_CH1 0x84b8 1527 #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1) 1528 1529 /* CHV dpPhy registers */ 1530 #define _CHV_PLL_DW0_CH0 0x8000 1531 #define _CHV_PLL_DW0_CH1 0x8180 1532 #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1) 1533 1534 #define _CHV_PLL_DW1_CH0 0x8004 1535 #define _CHV_PLL_DW1_CH1 0x8184 1536 #define DPIO_CHV_N_DIV_SHIFT 8 1537 #define DPIO_CHV_M1_DIV_BY_2 (0 << 0) 1538 #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1) 1539 1540 #define _CHV_PLL_DW2_CH0 0x8008 1541 #define _CHV_PLL_DW2_CH1 0x8188 1542 #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1) 1543 1544 #define _CHV_PLL_DW3_CH0 0x800c 1545 #define _CHV_PLL_DW3_CH1 0x818c 1546 #define DPIO_CHV_FRAC_DIV_EN (1 << 16) 1547 #define DPIO_CHV_FIRST_MOD (0 << 8) 1548 #define DPIO_CHV_SECOND_MOD (1 << 8) 1549 #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0 1550 #define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0) 1551 #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1) 1552 1553 #define _CHV_PLL_DW6_CH0 0x8018 1554 #define _CHV_PLL_DW6_CH1 0x8198 1555 #define DPIO_CHV_GAIN_CTRL_SHIFT 16 1556 #define DPIO_CHV_INT_COEFF_SHIFT 8 1557 #define DPIO_CHV_PROP_COEFF_SHIFT 0 1558 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1) 1559 1560 #define _CHV_PLL_DW8_CH0 0x8020 1561 #define _CHV_PLL_DW8_CH1 0x81A0 1562 #define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0 1563 #define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0) 1564 #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1) 1565 1566 #define _CHV_PLL_DW9_CH0 0x8024 1567 #define _CHV_PLL_DW9_CH1 0x81A4 1568 #define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */ 1569 #define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1) 1570 #define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */ 1571 #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1) 1572 1573 #define _CHV_CMN_DW0_CH0 0x8100 1574 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19 1575 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18 1576 #define DPIO_ALLDL_POWERDOWN (1 << 1) 1577 #define DPIO_ANYDL_POWERDOWN (1 << 0) 1578 1579 #define _CHV_CMN_DW5_CH0 0x8114 1580 #define CHV_BUFRIGHTENA1_DISABLE (0 << 20) 1581 #define CHV_BUFRIGHTENA1_NORMAL (1 << 20) 1582 #define CHV_BUFRIGHTENA1_FORCE (3 << 20) 1583 #define CHV_BUFRIGHTENA1_MASK (3 << 20) 1584 #define CHV_BUFLEFTENA1_DISABLE (0 << 22) 1585 #define CHV_BUFLEFTENA1_NORMAL (1 << 22) 1586 #define CHV_BUFLEFTENA1_FORCE (3 << 22) 1587 #define CHV_BUFLEFTENA1_MASK (3 << 22) 1588 1589 #define _CHV_CMN_DW13_CH0 0x8134 1590 #define _CHV_CMN_DW0_CH1 0x8080 1591 #define DPIO_CHV_S1_DIV_SHIFT 21 1592 #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */ 1593 #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */ 1594 #define DPIO_CHV_K_DIV_SHIFT 4 1595 #define DPIO_PLL_FREQLOCK (1 << 1) 1596 #define DPIO_PLL_LOCK (1 << 0) 1597 #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1) 1598 1599 #define _CHV_CMN_DW14_CH0 0x8138 1600 #define _CHV_CMN_DW1_CH1 0x8084 1601 #define DPIO_AFC_RECAL (1 << 14) 1602 #define DPIO_DCLKP_EN (1 << 13) 1603 #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */ 1604 #define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */ 1605 #define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */ 1606 #define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */ 1607 #define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */ 1608 #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */ 1609 #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */ 1610 #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */ 1611 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1) 1612 1613 #define _CHV_CMN_DW19_CH0 0x814c 1614 #define _CHV_CMN_DW6_CH1 0x8098 1615 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */ 1616 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */ 1617 #define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */ 1618 #define CHV_CMN_USEDCLKCHANNEL (1 << 13) 1619 1620 #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1) 1621 1622 #define CHV_CMN_DW28 0x8170 1623 #define DPIO_CL1POWERDOWNEN (1 << 23) 1624 #define DPIO_DYNPWRDOWNEN_CH0 (1 << 22) 1625 #define DPIO_SUS_CLK_CONFIG_ON (0 << 0) 1626 #define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0) 1627 #define DPIO_SUS_CLK_CONFIG_GATE (2 << 0) 1628 #define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0) 1629 1630 #define CHV_CMN_DW30 0x8178 1631 #define DPIO_CL2_LDOFUSE_PWRENB (1 << 6) 1632 #define DPIO_LRC_BYPASS (1 << 3) 1633 1634 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \ 1635 (lane) * 0x200 + (offset)) 1636 1637 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80) 1638 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84) 1639 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88) 1640 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c) 1641 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90) 1642 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94) 1643 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98) 1644 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c) 1645 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0) 1646 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4) 1647 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8) 1648 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac) 1649 #define DPIO_FRC_LATENCY_SHFIT 8 1650 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8) 1651 #define DPIO_UPAR_SHIFT 30 1652 1653 /* BXT PHY registers */ 1654 #define _BXT_PHY0_BASE 0x6C000 1655 #define _BXT_PHY1_BASE 0x162000 1656 #define _BXT_PHY2_BASE 0x163000 1657 #define BXT_PHY_BASE(phy) _PHY3((phy), _BXT_PHY0_BASE, \ 1658 _BXT_PHY1_BASE, \ 1659 _BXT_PHY2_BASE) 1660 1661 #define _BXT_PHY(phy, reg) \ 1662 _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg)) 1663 1664 #define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \ 1665 (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \ 1666 (reg_ch1) - _BXT_PHY0_BASE)) 1667 #define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \ 1668 _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1)) 1669 1670 #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090) 1671 #define MIPIO_RST_CTRL (1 << 2) 1672 1673 #define _BXT_PHY_CTL_DDI_A 0x64C00 1674 #define _BXT_PHY_CTL_DDI_B 0x64C10 1675 #define _BXT_PHY_CTL_DDI_C 0x64C20 1676 #define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10) 1677 #define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9) 1678 #define BXT_PHY_LANE_ENABLED (1 << 8) 1679 #define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \ 1680 _BXT_PHY_CTL_DDI_B) 1681 1682 #define _PHY_CTL_FAMILY_EDP 0x64C80 1683 #define _PHY_CTL_FAMILY_DDI 0x64C90 1684 #define _PHY_CTL_FAMILY_DDI_C 0x64CA0 1685 #define COMMON_RESET_DIS (1 << 31) 1686 #define BXT_PHY_CTL_FAMILY(phy) _MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \ 1687 _PHY_CTL_FAMILY_EDP, \ 1688 _PHY_CTL_FAMILY_DDI_C) 1689 1690 /* BXT PHY PLL registers */ 1691 #define _PORT_PLL_A 0x46074 1692 #define _PORT_PLL_B 0x46078 1693 #define _PORT_PLL_C 0x4607c 1694 #define PORT_PLL_ENABLE (1 << 31) 1695 #define PORT_PLL_LOCK (1 << 30) 1696 #define PORT_PLL_REF_SEL (1 << 27) 1697 #define PORT_PLL_POWER_ENABLE (1 << 26) 1698 #define PORT_PLL_POWER_STATE (1 << 25) 1699 #define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B) 1700 1701 #define _PORT_PLL_EBB_0_A 0x162034 1702 #define _PORT_PLL_EBB_0_B 0x6C034 1703 #define _PORT_PLL_EBB_0_C 0x6C340 1704 #define PORT_PLL_P1_SHIFT 13 1705 #define PORT_PLL_P1_MASK (0x07 << PORT_PLL_P1_SHIFT) 1706 #define PORT_PLL_P1(x) ((x) << PORT_PLL_P1_SHIFT) 1707 #define PORT_PLL_P2_SHIFT 8 1708 #define PORT_PLL_P2_MASK (0x1f << PORT_PLL_P2_SHIFT) 1709 #define PORT_PLL_P2(x) ((x) << PORT_PLL_P2_SHIFT) 1710 #define BXT_PORT_PLL_EBB_0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 1711 _PORT_PLL_EBB_0_B, \ 1712 _PORT_PLL_EBB_0_C) 1713 1714 #define _PORT_PLL_EBB_4_A 0x162038 1715 #define _PORT_PLL_EBB_4_B 0x6C038 1716 #define _PORT_PLL_EBB_4_C 0x6C344 1717 #define PORT_PLL_10BIT_CLK_ENABLE (1 << 13) 1718 #define PORT_PLL_RECALIBRATE (1 << 14) 1719 #define BXT_PORT_PLL_EBB_4(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 1720 _PORT_PLL_EBB_4_B, \ 1721 _PORT_PLL_EBB_4_C) 1722 1723 #define _PORT_PLL_0_A 0x162100 1724 #define _PORT_PLL_0_B 0x6C100 1725 #define _PORT_PLL_0_C 0x6C380 1726 /* PORT_PLL_0_A */ 1727 #define PORT_PLL_M2_MASK 0xFF 1728 /* PORT_PLL_1_A */ 1729 #define PORT_PLL_N_SHIFT 8 1730 #define PORT_PLL_N_MASK (0x0F << PORT_PLL_N_SHIFT) 1731 #define PORT_PLL_N(x) ((x) << PORT_PLL_N_SHIFT) 1732 /* PORT_PLL_2_A */ 1733 #define PORT_PLL_M2_FRAC_MASK 0x3FFFFF 1734 /* PORT_PLL_3_A */ 1735 #define PORT_PLL_M2_FRAC_ENABLE (1 << 16) 1736 /* PORT_PLL_6_A */ 1737 #define PORT_PLL_PROP_COEFF_MASK 0xF 1738 #define PORT_PLL_INT_COEFF_MASK (0x1F << 8) 1739 #define PORT_PLL_INT_COEFF(x) ((x) << 8) 1740 #define PORT_PLL_GAIN_CTL_MASK (0x07 << 16) 1741 #define PORT_PLL_GAIN_CTL(x) ((x) << 16) 1742 /* PORT_PLL_8_A */ 1743 #define PORT_PLL_TARGET_CNT_MASK 0x3FF 1744 /* PORT_PLL_9_A */ 1745 #define PORT_PLL_LOCK_THRESHOLD_SHIFT 1 1746 #define PORT_PLL_LOCK_THRESHOLD_MASK (0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT) 1747 /* PORT_PLL_10_A */ 1748 #define PORT_PLL_DCO_AMP_OVR_EN_H (1 << 27) 1749 #define PORT_PLL_DCO_AMP_DEFAULT 15 1750 #define PORT_PLL_DCO_AMP_MASK 0x3c00 1751 #define PORT_PLL_DCO_AMP(x) ((x) << 10) 1752 #define _PORT_PLL_BASE(phy, ch) _BXT_PHY_CH(phy, ch, \ 1753 _PORT_PLL_0_B, \ 1754 _PORT_PLL_0_C) 1755 #define BXT_PORT_PLL(phy, ch, idx) _MMIO(_PORT_PLL_BASE(phy, ch) + \ 1756 (idx) * 4) 1757 1758 /* BXT PHY common lane registers */ 1759 #define _PORT_CL1CM_DW0_A 0x162000 1760 #define _PORT_CL1CM_DW0_BC 0x6C000 1761 #define PHY_POWER_GOOD (1 << 16) 1762 #define PHY_RESERVED (1 << 7) 1763 #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC) 1764 1765 #define _PORT_CL1CM_DW9_A 0x162024 1766 #define _PORT_CL1CM_DW9_BC 0x6C024 1767 #define IREF0RC_OFFSET_SHIFT 8 1768 #define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT) 1769 #define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC) 1770 1771 #define _PORT_CL1CM_DW10_A 0x162028 1772 #define _PORT_CL1CM_DW10_BC 0x6C028 1773 #define IREF1RC_OFFSET_SHIFT 8 1774 #define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT) 1775 #define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC) 1776 1777 #define _PORT_CL1CM_DW28_A 0x162070 1778 #define _PORT_CL1CM_DW28_BC 0x6C070 1779 #define OCL1_POWER_DOWN_EN (1 << 23) 1780 #define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22) 1781 #define SUS_CLK_CONFIG 0x3 1782 #define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC) 1783 1784 #define _PORT_CL1CM_DW30_A 0x162078 1785 #define _PORT_CL1CM_DW30_BC 0x6C078 1786 #define OCL2_LDOFUSE_PWR_DIS (1 << 6) 1787 #define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC) 1788 1789 /* 1790 * CNL/ICL Port/COMBO-PHY Registers 1791 */ 1792 #define _ICL_COMBOPHY_A 0x162000 1793 #define _ICL_COMBOPHY_B 0x6C000 1794 #define _ICL_COMBOPHY(port) _PICK(port, _ICL_COMBOPHY_A, \ 1795 _ICL_COMBOPHY_B) 1796 1797 /* CNL/ICL Port CL_DW registers */ 1798 #define _ICL_PORT_CL_DW(dw, port) (_ICL_COMBOPHY(port) + \ 1799 4 * (dw)) 1800 1801 #define CNL_PORT_CL1CM_DW5 _MMIO(0x162014) 1802 #define ICL_PORT_CL_DW5(port) _MMIO(_ICL_PORT_CL_DW(5, port)) 1803 #define CL_POWER_DOWN_ENABLE (1 << 4) 1804 #define SUS_CLOCK_CONFIG (3 << 0) 1805 1806 #define ICL_PORT_CL_DW10(port) _MMIO(_ICL_PORT_CL_DW(10, port)) 1807 #define PG_SEQ_DELAY_OVERRIDE_MASK (3 << 25) 1808 #define PG_SEQ_DELAY_OVERRIDE_SHIFT 25 1809 #define PG_SEQ_DELAY_OVERRIDE_ENABLE (1 << 24) 1810 #define PWR_UP_ALL_LANES (0x0 << 4) 1811 #define PWR_DOWN_LN_3_2_1 (0xe << 4) 1812 #define PWR_DOWN_LN_3_2 (0xc << 4) 1813 #define PWR_DOWN_LN_3 (0x8 << 4) 1814 #define PWR_DOWN_LN_2_1_0 (0x7 << 4) 1815 #define PWR_DOWN_LN_1_0 (0x3 << 4) 1816 #define PWR_DOWN_LN_1 (0x2 << 4) 1817 #define PWR_DOWN_LN_3_1 (0xa << 4) 1818 #define PWR_DOWN_LN_3_1_0 (0xb << 4) 1819 #define PWR_DOWN_LN_MASK (0xf << 4) 1820 #define PWR_DOWN_LN_SHIFT 4 1821 1822 #define ICL_PORT_CL_DW12(port) _MMIO(_ICL_PORT_CL_DW(12, port)) 1823 #define ICL_LANE_ENABLE_AUX (1 << 0) 1824 1825 /* CNL/ICL Port COMP_DW registers */ 1826 #define _ICL_PORT_COMP 0x100 1827 #define _ICL_PORT_COMP_DW(dw, port) (_ICL_COMBOPHY(port) + \ 1828 _ICL_PORT_COMP + 4 * (dw)) 1829 1830 #define CNL_PORT_COMP_DW0 _MMIO(0x162100) 1831 #define ICL_PORT_COMP_DW0(port) _MMIO(_ICL_PORT_COMP_DW(0, port)) 1832 #define COMP_INIT (1 << 31) 1833 1834 #define CNL_PORT_COMP_DW1 _MMIO(0x162104) 1835 #define ICL_PORT_COMP_DW1(port) _MMIO(_ICL_PORT_COMP_DW(1, port)) 1836 1837 #define CNL_PORT_COMP_DW3 _MMIO(0x16210c) 1838 #define ICL_PORT_COMP_DW3(port) _MMIO(_ICL_PORT_COMP_DW(3, port)) 1839 #define PROCESS_INFO_DOT_0 (0 << 26) 1840 #define PROCESS_INFO_DOT_1 (1 << 26) 1841 #define PROCESS_INFO_DOT_4 (2 << 26) 1842 #define PROCESS_INFO_MASK (7 << 26) 1843 #define PROCESS_INFO_SHIFT 26 1844 #define VOLTAGE_INFO_0_85V (0 << 24) 1845 #define VOLTAGE_INFO_0_95V (1 << 24) 1846 #define VOLTAGE_INFO_1_05V (2 << 24) 1847 #define VOLTAGE_INFO_MASK (3 << 24) 1848 #define VOLTAGE_INFO_SHIFT 24 1849 1850 #define CNL_PORT_COMP_DW9 _MMIO(0x162124) 1851 #define ICL_PORT_COMP_DW9(port) _MMIO(_ICL_PORT_COMP_DW(9, port)) 1852 1853 #define CNL_PORT_COMP_DW10 _MMIO(0x162128) 1854 #define ICL_PORT_COMP_DW10(port) _MMIO(_ICL_PORT_COMP_DW(10, port)) 1855 1856 /* CNL/ICL Port PCS registers */ 1857 #define _CNL_PORT_PCS_DW1_GRP_AE 0x162304 1858 #define _CNL_PORT_PCS_DW1_GRP_B 0x162384 1859 #define _CNL_PORT_PCS_DW1_GRP_C 0x162B04 1860 #define _CNL_PORT_PCS_DW1_GRP_D 0x162B84 1861 #define _CNL_PORT_PCS_DW1_GRP_F 0x162A04 1862 #define _CNL_PORT_PCS_DW1_LN0_AE 0x162404 1863 #define _CNL_PORT_PCS_DW1_LN0_B 0x162604 1864 #define _CNL_PORT_PCS_DW1_LN0_C 0x162C04 1865 #define _CNL_PORT_PCS_DW1_LN0_D 0x162E04 1866 #define _CNL_PORT_PCS_DW1_LN0_F 0x162804 1867 #define CNL_PORT_PCS_DW1_GRP(port) _MMIO(_PICK(port, \ 1868 _CNL_PORT_PCS_DW1_GRP_AE, \ 1869 _CNL_PORT_PCS_DW1_GRP_B, \ 1870 _CNL_PORT_PCS_DW1_GRP_C, \ 1871 _CNL_PORT_PCS_DW1_GRP_D, \ 1872 _CNL_PORT_PCS_DW1_GRP_AE, \ 1873 _CNL_PORT_PCS_DW1_GRP_F)) 1874 #define CNL_PORT_PCS_DW1_LN0(port) _MMIO(_PICK(port, \ 1875 _CNL_PORT_PCS_DW1_LN0_AE, \ 1876 _CNL_PORT_PCS_DW1_LN0_B, \ 1877 _CNL_PORT_PCS_DW1_LN0_C, \ 1878 _CNL_PORT_PCS_DW1_LN0_D, \ 1879 _CNL_PORT_PCS_DW1_LN0_AE, \ 1880 _CNL_PORT_PCS_DW1_LN0_F)) 1881 1882 #define _ICL_PORT_PCS_AUX 0x300 1883 #define _ICL_PORT_PCS_GRP 0x600 1884 #define _ICL_PORT_PCS_LN(ln) (0x800 + (ln) * 0x100) 1885 #define _ICL_PORT_PCS_DW_AUX(dw, port) (_ICL_COMBOPHY(port) + \ 1886 _ICL_PORT_PCS_AUX + 4 * (dw)) 1887 #define _ICL_PORT_PCS_DW_GRP(dw, port) (_ICL_COMBOPHY(port) + \ 1888 _ICL_PORT_PCS_GRP + 4 * (dw)) 1889 #define _ICL_PORT_PCS_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \ 1890 _ICL_PORT_PCS_LN(ln) + 4 * (dw)) 1891 #define ICL_PORT_PCS_DW1_AUX(port) _MMIO(_ICL_PORT_PCS_DW_AUX(1, port)) 1892 #define ICL_PORT_PCS_DW1_GRP(port) _MMIO(_ICL_PORT_PCS_DW_GRP(1, port)) 1893 #define ICL_PORT_PCS_DW1_LN0(port) _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, port)) 1894 #define COMMON_KEEPER_EN (1 << 26) 1895 1896 /* CNL/ICL Port TX registers */ 1897 #define _CNL_PORT_TX_AE_GRP_OFFSET 0x162340 1898 #define _CNL_PORT_TX_B_GRP_OFFSET 0x1623C0 1899 #define _CNL_PORT_TX_C_GRP_OFFSET 0x162B40 1900 #define _CNL_PORT_TX_D_GRP_OFFSET 0x162BC0 1901 #define _CNL_PORT_TX_F_GRP_OFFSET 0x162A40 1902 #define _CNL_PORT_TX_AE_LN0_OFFSET 0x162440 1903 #define _CNL_PORT_TX_B_LN0_OFFSET 0x162640 1904 #define _CNL_PORT_TX_C_LN0_OFFSET 0x162C40 1905 #define _CNL_PORT_TX_D_LN0_OFFSET 0x162E40 1906 #define _CNL_PORT_TX_F_LN0_OFFSET 0x162840 1907 #define _CNL_PORT_TX_DW_GRP(dw, port) (_PICK((port), \ 1908 _CNL_PORT_TX_AE_GRP_OFFSET, \ 1909 _CNL_PORT_TX_B_GRP_OFFSET, \ 1910 _CNL_PORT_TX_B_GRP_OFFSET, \ 1911 _CNL_PORT_TX_D_GRP_OFFSET, \ 1912 _CNL_PORT_TX_AE_GRP_OFFSET, \ 1913 _CNL_PORT_TX_F_GRP_OFFSET) + \ 1914 4 * (dw)) 1915 #define _CNL_PORT_TX_DW_LN0(dw, port) (_PICK((port), \ 1916 _CNL_PORT_TX_AE_LN0_OFFSET, \ 1917 _CNL_PORT_TX_B_LN0_OFFSET, \ 1918 _CNL_PORT_TX_B_LN0_OFFSET, \ 1919 _CNL_PORT_TX_D_LN0_OFFSET, \ 1920 _CNL_PORT_TX_AE_LN0_OFFSET, \ 1921 _CNL_PORT_TX_F_LN0_OFFSET) + \ 1922 4 * (dw)) 1923 1924 #define _ICL_PORT_TX_AUX 0x380 1925 #define _ICL_PORT_TX_GRP 0x680 1926 #define _ICL_PORT_TX_LN(ln) (0x880 + (ln) * 0x100) 1927 1928 #define _ICL_PORT_TX_DW_AUX(dw, port) (_ICL_COMBOPHY(port) + \ 1929 _ICL_PORT_TX_AUX + 4 * (dw)) 1930 #define _ICL_PORT_TX_DW_GRP(dw, port) (_ICL_COMBOPHY(port) + \ 1931 _ICL_PORT_TX_GRP + 4 * (dw)) 1932 #define _ICL_PORT_TX_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \ 1933 _ICL_PORT_TX_LN(ln) + 4 * (dw)) 1934 1935 #define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(2, port)) 1936 #define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(2, port)) 1937 #define ICL_PORT_TX_DW2_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(2, port)) 1938 #define ICL_PORT_TX_DW2_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(2, port)) 1939 #define ICL_PORT_TX_DW2_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(2, 0, port)) 1940 #define SWING_SEL_UPPER(x) (((x) >> 3) << 15) 1941 #define SWING_SEL_UPPER_MASK (1 << 15) 1942 #define SWING_SEL_LOWER(x) (((x) & 0x7) << 11) 1943 #define SWING_SEL_LOWER_MASK (0x7 << 11) 1944 #define FRC_LATENCY_OPTIM_MASK (0x7 << 8) 1945 #define FRC_LATENCY_OPTIM_VAL(x) ((x) << 8) 1946 #define RCOMP_SCALAR(x) ((x) << 0) 1947 #define RCOMP_SCALAR_MASK (0xFF << 0) 1948 1949 #define _CNL_PORT_TX_DW4_LN0_AE 0x162450 1950 #define _CNL_PORT_TX_DW4_LN1_AE 0x1624D0 1951 #define CNL_PORT_TX_DW4_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(4, (port))) 1952 #define CNL_PORT_TX_DW4_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port))) 1953 #define CNL_PORT_TX_DW4_LN(ln, port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)) + \ 1954 ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \ 1955 _CNL_PORT_TX_DW4_LN0_AE))) 1956 #define ICL_PORT_TX_DW4_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(4, port)) 1957 #define ICL_PORT_TX_DW4_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(4, port)) 1958 #define ICL_PORT_TX_DW4_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(4, 0, port)) 1959 #define ICL_PORT_TX_DW4_LN(ln, port) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, port)) 1960 #define LOADGEN_SELECT (1 << 31) 1961 #define POST_CURSOR_1(x) ((x) << 12) 1962 #define POST_CURSOR_1_MASK (0x3F << 12) 1963 #define POST_CURSOR_2(x) ((x) << 6) 1964 #define POST_CURSOR_2_MASK (0x3F << 6) 1965 #define CURSOR_COEFF(x) ((x) << 0) 1966 #define CURSOR_COEFF_MASK (0x3F << 0) 1967 1968 #define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(5, port)) 1969 #define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(5, port)) 1970 #define ICL_PORT_TX_DW5_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(5, port)) 1971 #define ICL_PORT_TX_DW5_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(5, port)) 1972 #define ICL_PORT_TX_DW5_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(5, 0, port)) 1973 #define TX_TRAINING_EN (1 << 31) 1974 #define TAP2_DISABLE (1 << 30) 1975 #define TAP3_DISABLE (1 << 29) 1976 #define SCALING_MODE_SEL(x) ((x) << 18) 1977 #define SCALING_MODE_SEL_MASK (0x7 << 18) 1978 #define RTERM_SELECT(x) ((x) << 3) 1979 #define RTERM_SELECT_MASK (0x7 << 3) 1980 1981 #define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(7, (port))) 1982 #define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(7, (port))) 1983 #define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7, port)) 1984 #define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7, port)) 1985 #define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port)) 1986 #define ICL_PORT_TX_DW7_LN(ln, port) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port)) 1987 #define N_SCALAR(x) ((x) << 24) 1988 #define N_SCALAR_MASK (0x7F << 24) 1989 1990 #define MG_PHY_PORT_LN(ln, port, ln0p1, ln0p2, ln1p1) \ 1991 _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1))) 1992 1993 #define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C 1994 #define MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C 1995 #define MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C 1996 #define MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C 1997 #define MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C 1998 #define MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C 1999 #define MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C 2000 #define MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C 2001 #define MG_TX1_LINK_PARAMS(ln, port) \ 2002 MG_PHY_PORT_LN(ln, port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \ 2003 MG_TX_LINK_PARAMS_TX1LN0_PORT2, \ 2004 MG_TX_LINK_PARAMS_TX1LN1_PORT1) 2005 2006 #define MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC 2007 #define MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC 2008 #define MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC 2009 #define MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC 2010 #define MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC 2011 #define MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC 2012 #define MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC 2013 #define MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC 2014 #define MG_TX2_LINK_PARAMS(ln, port) \ 2015 MG_PHY_PORT_LN(ln, port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \ 2016 MG_TX_LINK_PARAMS_TX2LN0_PORT2, \ 2017 MG_TX_LINK_PARAMS_TX2LN1_PORT1) 2018 #define CRI_USE_FS32 (1 << 5) 2019 2020 #define MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C 2021 #define MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C 2022 #define MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C 2023 #define MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C 2024 #define MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14C 2025 #define MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C 2026 #define MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C 2027 #define MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C 2028 #define MG_TX1_PISO_READLOAD(ln, port) \ 2029 MG_PHY_PORT_LN(ln, port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \ 2030 MG_TX_PISO_READLOAD_TX1LN0_PORT2, \ 2031 MG_TX_PISO_READLOAD_TX1LN1_PORT1) 2032 2033 #define MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC 2034 #define MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC 2035 #define MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC 2036 #define MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC 2037 #define MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0CC 2038 #define MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC 2039 #define MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC 2040 #define MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC 2041 #define MG_TX2_PISO_READLOAD(ln, port) \ 2042 MG_PHY_PORT_LN(ln, port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \ 2043 MG_TX_PISO_READLOAD_TX2LN0_PORT2, \ 2044 MG_TX_PISO_READLOAD_TX2LN1_PORT1) 2045 #define CRI_CALCINIT (1 << 1) 2046 2047 #define MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148 2048 #define MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548 2049 #define MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148 2050 #define MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548 2051 #define MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148 2052 #define MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548 2053 #define MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148 2054 #define MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548 2055 #define MG_TX1_SWINGCTRL(ln, port) \ 2056 MG_PHY_PORT_LN(ln, port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \ 2057 MG_TX_SWINGCTRL_TX1LN0_PORT2, \ 2058 MG_TX_SWINGCTRL_TX1LN1_PORT1) 2059 2060 #define MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8 2061 #define MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8 2062 #define MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8 2063 #define MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8 2064 #define MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8 2065 #define MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8 2066 #define MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8 2067 #define MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8 2068 #define MG_TX2_SWINGCTRL(ln, port) \ 2069 MG_PHY_PORT_LN(ln, port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \ 2070 MG_TX_SWINGCTRL_TX2LN0_PORT2, \ 2071 MG_TX_SWINGCTRL_TX2LN1_PORT1) 2072 #define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0) 2073 #define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0) 2074 2075 #define MG_TX_DRVCTRL_TX1LN0_TXPORT1 0x168144 2076 #define MG_TX_DRVCTRL_TX1LN1_TXPORT1 0x168544 2077 #define MG_TX_DRVCTRL_TX1LN0_TXPORT2 0x169144 2078 #define MG_TX_DRVCTRL_TX1LN1_TXPORT2 0x169544 2079 #define MG_TX_DRVCTRL_TX1LN0_TXPORT3 0x16A144 2080 #define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A544 2081 #define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B144 2082 #define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B544 2083 #define MG_TX1_DRVCTRL(ln, port) \ 2084 MG_PHY_PORT_LN(ln, port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \ 2085 MG_TX_DRVCTRL_TX1LN0_TXPORT2, \ 2086 MG_TX_DRVCTRL_TX1LN1_TXPORT1) 2087 2088 #define MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4 2089 #define MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4 2090 #define MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4 2091 #define MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4 2092 #define MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A0C4 2093 #define MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4 2094 #define MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4 2095 #define MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4 2096 #define MG_TX2_DRVCTRL(ln, port) \ 2097 MG_PHY_PORT_LN(ln, port, MG_TX_DRVCTRL_TX2LN0_PORT1, \ 2098 MG_TX_DRVCTRL_TX2LN0_PORT2, \ 2099 MG_TX_DRVCTRL_TX2LN1_PORT1) 2100 #define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24) 2101 #define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F << 24) 2102 #define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22) 2103 #define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) << 16) 2104 #define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16) 2105 #define CRI_LOADGEN_SEL(x) ((x) << 12) 2106 #define CRI_LOADGEN_SEL_MASK (0x3 << 12) 2107 2108 #define MG_CLKHUB_LN0_PORT1 0x16839C 2109 #define MG_CLKHUB_LN1_PORT1 0x16879C 2110 #define MG_CLKHUB_LN0_PORT2 0x16939C 2111 #define MG_CLKHUB_LN1_PORT2 0x16979C 2112 #define MG_CLKHUB_LN0_PORT3 0x16A39C 2113 #define MG_CLKHUB_LN1_PORT3 0x16A79C 2114 #define MG_CLKHUB_LN0_PORT4 0x16B39C 2115 #define MG_CLKHUB_LN1_PORT4 0x16B79C 2116 #define MG_CLKHUB(ln, port) \ 2117 MG_PHY_PORT_LN(ln, port, MG_CLKHUB_LN0_PORT1, \ 2118 MG_CLKHUB_LN0_PORT2, \ 2119 MG_CLKHUB_LN1_PORT1) 2120 #define CFG_LOW_RATE_LKREN_EN (1 << 11) 2121 2122 #define MG_TX_DCC_TX1LN0_PORT1 0x168110 2123 #define MG_TX_DCC_TX1LN1_PORT1 0x168510 2124 #define MG_TX_DCC_TX1LN0_PORT2 0x169110 2125 #define MG_TX_DCC_TX1LN1_PORT2 0x169510 2126 #define MG_TX_DCC_TX1LN0_PORT3 0x16A110 2127 #define MG_TX_DCC_TX1LN1_PORT3 0x16A510 2128 #define MG_TX_DCC_TX1LN0_PORT4 0x16B110 2129 #define MG_TX_DCC_TX1LN1_PORT4 0x16B510 2130 #define MG_TX1_DCC(ln, port) \ 2131 MG_PHY_PORT_LN(ln, port, MG_TX_DCC_TX1LN0_PORT1, \ 2132 MG_TX_DCC_TX1LN0_PORT2, \ 2133 MG_TX_DCC_TX1LN1_PORT1) 2134 #define MG_TX_DCC_TX2LN0_PORT1 0x168090 2135 #define MG_TX_DCC_TX2LN1_PORT1 0x168490 2136 #define MG_TX_DCC_TX2LN0_PORT2 0x169090 2137 #define MG_TX_DCC_TX2LN1_PORT2 0x169490 2138 #define MG_TX_DCC_TX2LN0_PORT3 0x16A090 2139 #define MG_TX_DCC_TX2LN1_PORT3 0x16A490 2140 #define MG_TX_DCC_TX2LN0_PORT4 0x16B090 2141 #define MG_TX_DCC_TX2LN1_PORT4 0x16B490 2142 #define MG_TX2_DCC(ln, port) \ 2143 MG_PHY_PORT_LN(ln, port, MG_TX_DCC_TX2LN0_PORT1, \ 2144 MG_TX_DCC_TX2LN0_PORT2, \ 2145 MG_TX_DCC_TX2LN1_PORT1) 2146 #define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25) 2147 #define CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK (0x3 << 25) 2148 #define CFG_AMI_CK_DIV_OVERRIDE_EN (1 << 24) 2149 2150 #define MG_DP_MODE_LN0_ACU_PORT1 0x1683A0 2151 #define MG_DP_MODE_LN1_ACU_PORT1 0x1687A0 2152 #define MG_DP_MODE_LN0_ACU_PORT2 0x1693A0 2153 #define MG_DP_MODE_LN1_ACU_PORT2 0x1697A0 2154 #define MG_DP_MODE_LN0_ACU_PORT3 0x16A3A0 2155 #define MG_DP_MODE_LN1_ACU_PORT3 0x16A7A0 2156 #define MG_DP_MODE_LN0_ACU_PORT4 0x16B3A0 2157 #define MG_DP_MODE_LN1_ACU_PORT4 0x16B7A0 2158 #define MG_DP_MODE(ln, port) \ 2159 MG_PHY_PORT_LN(ln, port, MG_DP_MODE_LN0_ACU_PORT1, \ 2160 MG_DP_MODE_LN0_ACU_PORT2, \ 2161 MG_DP_MODE_LN1_ACU_PORT1) 2162 #define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7) 2163 #define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6) 2164 #define MG_DP_MODE_CFG_TR2PWR_GATING (1 << 5) 2165 #define MG_DP_MODE_CFG_TRPWR_GATING (1 << 4) 2166 #define MG_DP_MODE_CFG_CLNPWR_GATING (1 << 3) 2167 #define MG_DP_MODE_CFG_DIGPWR_GATING (1 << 2) 2168 #define MG_DP_MODE_CFG_GAONPWR_GATING (1 << 1) 2169 2170 #define MG_MISC_SUS0_PORT1 0x168814 2171 #define MG_MISC_SUS0_PORT2 0x169814 2172 #define MG_MISC_SUS0_PORT3 0x16A814 2173 #define MG_MISC_SUS0_PORT4 0x16B814 2174 #define MG_MISC_SUS0(tc_port) \ 2175 _MMIO(_PORT(tc_port, MG_MISC_SUS0_PORT1, MG_MISC_SUS0_PORT2)) 2176 #define MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK (3 << 14) 2177 #define MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(x) ((x) << 14) 2178 #define MG_MISC_SUS0_CFG_TR2PWR_GATING (1 << 12) 2179 #define MG_MISC_SUS0_CFG_CL2PWR_GATING (1 << 11) 2180 #define MG_MISC_SUS0_CFG_GAONPWR_GATING (1 << 10) 2181 #define MG_MISC_SUS0_CFG_TRPWR_GATING (1 << 7) 2182 #define MG_MISC_SUS0_CFG_CL1PWR_GATING (1 << 6) 2183 #define MG_MISC_SUS0_CFG_DGPWR_GATING (1 << 5) 2184 2185 /* The spec defines this only for BXT PHY0, but lets assume that this 2186 * would exist for PHY1 too if it had a second channel. 2187 */ 2188 #define _PORT_CL2CM_DW6_A 0x162358 2189 #define _PORT_CL2CM_DW6_BC 0x6C358 2190 #define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC) 2191 #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28) 2192 2193 #define FIA1_BASE 0x163000 2194 2195 /* ICL PHY DFLEX registers */ 2196 #define PORT_TX_DFLEXDPMLE1 _MMIO(FIA1_BASE + 0x008C0) 2197 #define DFLEXDPMLE1_DPMLETC_MASK(tc_port) (0xf << (4 * (tc_port))) 2198 #define DFLEXDPMLE1_DPMLETC_ML0(tc_port) (1 << (4 * (tc_port))) 2199 #define DFLEXDPMLE1_DPMLETC_ML1_0(tc_port) (3 << (4 * (tc_port))) 2200 #define DFLEXDPMLE1_DPMLETC_ML3(tc_port) (8 << (4 * (tc_port))) 2201 #define DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) (12 << (4 * (tc_port))) 2202 #define DFLEXDPMLE1_DPMLETC_ML3_0(tc_port) (15 << (4 * (tc_port))) 2203 2204 /* BXT PHY Ref registers */ 2205 #define _PORT_REF_DW3_A 0x16218C 2206 #define _PORT_REF_DW3_BC 0x6C18C 2207 #define GRC_DONE (1 << 22) 2208 #define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC) 2209 2210 #define _PORT_REF_DW6_A 0x162198 2211 #define _PORT_REF_DW6_BC 0x6C198 2212 #define GRC_CODE_SHIFT 24 2213 #define GRC_CODE_MASK (0xFF << GRC_CODE_SHIFT) 2214 #define GRC_CODE_FAST_SHIFT 16 2215 #define GRC_CODE_FAST_MASK (0xFF << GRC_CODE_FAST_SHIFT) 2216 #define GRC_CODE_SLOW_SHIFT 8 2217 #define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT) 2218 #define GRC_CODE_NOM_MASK 0xFF 2219 #define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC) 2220 2221 #define _PORT_REF_DW8_A 0x1621A0 2222 #define _PORT_REF_DW8_BC 0x6C1A0 2223 #define GRC_DIS (1 << 15) 2224 #define GRC_RDY_OVRD (1 << 1) 2225 #define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC) 2226 2227 /* BXT PHY PCS registers */ 2228 #define _PORT_PCS_DW10_LN01_A 0x162428 2229 #define _PORT_PCS_DW10_LN01_B 0x6C428 2230 #define _PORT_PCS_DW10_LN01_C 0x6C828 2231 #define _PORT_PCS_DW10_GRP_A 0x162C28 2232 #define _PORT_PCS_DW10_GRP_B 0x6CC28 2233 #define _PORT_PCS_DW10_GRP_C 0x6CE28 2234 #define BXT_PORT_PCS_DW10_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2235 _PORT_PCS_DW10_LN01_B, \ 2236 _PORT_PCS_DW10_LN01_C) 2237 #define BXT_PORT_PCS_DW10_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2238 _PORT_PCS_DW10_GRP_B, \ 2239 _PORT_PCS_DW10_GRP_C) 2240 2241 #define TX2_SWING_CALC_INIT (1 << 31) 2242 #define TX1_SWING_CALC_INIT (1 << 30) 2243 2244 #define _PORT_PCS_DW12_LN01_A 0x162430 2245 #define _PORT_PCS_DW12_LN01_B 0x6C430 2246 #define _PORT_PCS_DW12_LN01_C 0x6C830 2247 #define _PORT_PCS_DW12_LN23_A 0x162630 2248 #define _PORT_PCS_DW12_LN23_B 0x6C630 2249 #define _PORT_PCS_DW12_LN23_C 0x6CA30 2250 #define _PORT_PCS_DW12_GRP_A 0x162c30 2251 #define _PORT_PCS_DW12_GRP_B 0x6CC30 2252 #define _PORT_PCS_DW12_GRP_C 0x6CE30 2253 #define LANESTAGGER_STRAP_OVRD (1 << 6) 2254 #define LANE_STAGGER_MASK 0x1F 2255 #define BXT_PORT_PCS_DW12_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2256 _PORT_PCS_DW12_LN01_B, \ 2257 _PORT_PCS_DW12_LN01_C) 2258 #define BXT_PORT_PCS_DW12_LN23(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2259 _PORT_PCS_DW12_LN23_B, \ 2260 _PORT_PCS_DW12_LN23_C) 2261 #define BXT_PORT_PCS_DW12_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2262 _PORT_PCS_DW12_GRP_B, \ 2263 _PORT_PCS_DW12_GRP_C) 2264 2265 /* BXT PHY TX registers */ 2266 #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \ 2267 ((lane) & 1) * 0x80) 2268 2269 #define _PORT_TX_DW2_LN0_A 0x162508 2270 #define _PORT_TX_DW2_LN0_B 0x6C508 2271 #define _PORT_TX_DW2_LN0_C 0x6C908 2272 #define _PORT_TX_DW2_GRP_A 0x162D08 2273 #define _PORT_TX_DW2_GRP_B 0x6CD08 2274 #define _PORT_TX_DW2_GRP_C 0x6CF08 2275 #define BXT_PORT_TX_DW2_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2276 _PORT_TX_DW2_LN0_B, \ 2277 _PORT_TX_DW2_LN0_C) 2278 #define BXT_PORT_TX_DW2_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2279 _PORT_TX_DW2_GRP_B, \ 2280 _PORT_TX_DW2_GRP_C) 2281 #define MARGIN_000_SHIFT 16 2282 #define MARGIN_000 (0xFF << MARGIN_000_SHIFT) 2283 #define UNIQ_TRANS_SCALE_SHIFT 8 2284 #define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT) 2285 2286 #define _PORT_TX_DW3_LN0_A 0x16250C 2287 #define _PORT_TX_DW3_LN0_B 0x6C50C 2288 #define _PORT_TX_DW3_LN0_C 0x6C90C 2289 #define _PORT_TX_DW3_GRP_A 0x162D0C 2290 #define _PORT_TX_DW3_GRP_B 0x6CD0C 2291 #define _PORT_TX_DW3_GRP_C 0x6CF0C 2292 #define BXT_PORT_TX_DW3_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2293 _PORT_TX_DW3_LN0_B, \ 2294 _PORT_TX_DW3_LN0_C) 2295 #define BXT_PORT_TX_DW3_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2296 _PORT_TX_DW3_GRP_B, \ 2297 _PORT_TX_DW3_GRP_C) 2298 #define SCALE_DCOMP_METHOD (1 << 26) 2299 #define UNIQUE_TRANGE_EN_METHOD (1 << 27) 2300 2301 #define _PORT_TX_DW4_LN0_A 0x162510 2302 #define _PORT_TX_DW4_LN0_B 0x6C510 2303 #define _PORT_TX_DW4_LN0_C 0x6C910 2304 #define _PORT_TX_DW4_GRP_A 0x162D10 2305 #define _PORT_TX_DW4_GRP_B 0x6CD10 2306 #define _PORT_TX_DW4_GRP_C 0x6CF10 2307 #define BXT_PORT_TX_DW4_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2308 _PORT_TX_DW4_LN0_B, \ 2309 _PORT_TX_DW4_LN0_C) 2310 #define BXT_PORT_TX_DW4_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2311 _PORT_TX_DW4_GRP_B, \ 2312 _PORT_TX_DW4_GRP_C) 2313 #define DEEMPH_SHIFT 24 2314 #define DE_EMPHASIS (0xFF << DEEMPH_SHIFT) 2315 2316 #define _PORT_TX_DW5_LN0_A 0x162514 2317 #define _PORT_TX_DW5_LN0_B 0x6C514 2318 #define _PORT_TX_DW5_LN0_C 0x6C914 2319 #define _PORT_TX_DW5_GRP_A 0x162D14 2320 #define _PORT_TX_DW5_GRP_B 0x6CD14 2321 #define _PORT_TX_DW5_GRP_C 0x6CF14 2322 #define BXT_PORT_TX_DW5_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2323 _PORT_TX_DW5_LN0_B, \ 2324 _PORT_TX_DW5_LN0_C) 2325 #define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2326 _PORT_TX_DW5_GRP_B, \ 2327 _PORT_TX_DW5_GRP_C) 2328 #define DCC_DELAY_RANGE_1 (1 << 9) 2329 #define DCC_DELAY_RANGE_2 (1 << 8) 2330 2331 #define _PORT_TX_DW14_LN0_A 0x162538 2332 #define _PORT_TX_DW14_LN0_B 0x6C538 2333 #define _PORT_TX_DW14_LN0_C 0x6C938 2334 #define LATENCY_OPTIM_SHIFT 30 2335 #define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT) 2336 #define BXT_PORT_TX_DW14_LN(phy, ch, lane) \ 2337 _MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B, \ 2338 _PORT_TX_DW14_LN0_C) + \ 2339 _BXT_LANE_OFFSET(lane)) 2340 2341 /* UAIMI scratch pad register 1 */ 2342 #define UAIMI_SPR1 _MMIO(0x4F074) 2343 /* SKL VccIO mask */ 2344 #define SKL_VCCIO_MASK 0x1 2345 /* SKL balance leg register */ 2346 #define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C) 2347 /* I_boost values */ 2348 #define BALANCE_LEG_SHIFT(port) (8 + 3 * (port)) 2349 #define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port))) 2350 /* Balance leg disable bits */ 2351 #define BALANCE_LEG_DISABLE_SHIFT 23 2352 #define BALANCE_LEG_DISABLE(port) (1 << (23 + (port))) 2353 2354 /* 2355 * Fence registers 2356 * [0-7] @ 0x2000 gen2,gen3 2357 * [8-15] @ 0x3000 945,g33,pnv 2358 * 2359 * [0-15] @ 0x3000 gen4,gen5 2360 * 2361 * [0-15] @ 0x100000 gen6,vlv,chv 2362 * [0-31] @ 0x100000 gen7+ 2363 */ 2364 #define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4) 2365 #define I830_FENCE_START_MASK 0x07f80000 2366 #define I830_FENCE_TILING_Y_SHIFT 12 2367 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) 2368 #define I830_FENCE_PITCH_SHIFT 4 2369 #define I830_FENCE_REG_VALID (1 << 0) 2370 #define I915_FENCE_MAX_PITCH_VAL 4 2371 #define I830_FENCE_MAX_PITCH_VAL 6 2372 #define I830_FENCE_MAX_SIZE_VAL (1 << 8) 2373 2374 #define I915_FENCE_START_MASK 0x0ff00000 2375 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) 2376 2377 #define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8) 2378 #define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4) 2379 #define I965_FENCE_PITCH_SHIFT 2 2380 #define I965_FENCE_TILING_Y_SHIFT 1 2381 #define I965_FENCE_REG_VALID (1 << 0) 2382 #define I965_FENCE_MAX_PITCH_VAL 0x0400 2383 2384 #define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8) 2385 #define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4) 2386 #define GEN6_FENCE_PITCH_SHIFT 32 2387 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800 2388 2389 2390 /* control register for cpu gtt access */ 2391 #define TILECTL _MMIO(0x101000) 2392 #define TILECTL_SWZCTL (1 << 0) 2393 #define TILECTL_TLBPF (1 << 1) 2394 #define TILECTL_TLB_PREFETCH_DIS (1 << 2) 2395 #define TILECTL_BACKSNOOP_DIS (1 << 3) 2396 2397 /* 2398 * Instruction and interrupt control regs 2399 */ 2400 #define PGTBL_CTL _MMIO(0x02020) 2401 #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */ 2402 #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */ 2403 #define PGTBL_ER _MMIO(0x02024) 2404 #define PRB0_BASE (0x2030 - 0x30) 2405 #define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */ 2406 #define PRB2_BASE (0x2050 - 0x30) /* gen3 */ 2407 #define SRB0_BASE (0x2100 - 0x30) /* gen2 */ 2408 #define SRB1_BASE (0x2110 - 0x30) /* gen2 */ 2409 #define SRB2_BASE (0x2120 - 0x30) /* 830 */ 2410 #define SRB3_BASE (0x2130 - 0x30) /* 830 */ 2411 #define RENDER_RING_BASE 0x02000 2412 #define BSD_RING_BASE 0x04000 2413 #define GEN6_BSD_RING_BASE 0x12000 2414 #define GEN8_BSD2_RING_BASE 0x1c000 2415 #define GEN11_BSD_RING_BASE 0x1c0000 2416 #define GEN11_BSD2_RING_BASE 0x1c4000 2417 #define GEN11_BSD3_RING_BASE 0x1d0000 2418 #define GEN11_BSD4_RING_BASE 0x1d4000 2419 #define VEBOX_RING_BASE 0x1a000 2420 #define GEN11_VEBOX_RING_BASE 0x1c8000 2421 #define GEN11_VEBOX2_RING_BASE 0x1d8000 2422 #define BLT_RING_BASE 0x22000 2423 #define RING_TAIL(base) _MMIO((base) + 0x30) 2424 #define RING_HEAD(base) _MMIO((base) + 0x34) 2425 #define RING_START(base) _MMIO((base) + 0x38) 2426 #define RING_CTL(base) _MMIO((base) + 0x3c) 2427 #define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */ 2428 #define RING_SYNC_0(base) _MMIO((base) + 0x40) 2429 #define RING_SYNC_1(base) _MMIO((base) + 0x44) 2430 #define RING_SYNC_2(base) _MMIO((base) + 0x48) 2431 #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE)) 2432 #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE)) 2433 #define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE)) 2434 #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE)) 2435 #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE)) 2436 #define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE)) 2437 #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE)) 2438 #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE)) 2439 #define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE)) 2440 #define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE)) 2441 #define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE)) 2442 #define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE)) 2443 #define GEN6_NOSYNC INVALID_MMIO_REG 2444 #define RING_PSMI_CTL(base) _MMIO((base) + 0x50) 2445 #define RING_MAX_IDLE(base) _MMIO((base) + 0x54) 2446 #define RING_HWS_PGA(base) _MMIO((base) + 0x80) 2447 #define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080) 2448 #define RING_RESET_CTL(base) _MMIO((base) + 0xd0) 2449 #define RESET_CTL_CAT_ERROR REG_BIT(2) 2450 #define RESET_CTL_READY_TO_RESET REG_BIT(1) 2451 #define RESET_CTL_REQUEST_RESET REG_BIT(0) 2452 2453 #define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c) 2454 2455 #define HSW_GTT_CACHE_EN _MMIO(0x4024) 2456 #define GTT_CACHE_EN_ALL 0xF0007FFF 2457 #define GEN7_WR_WATERMARK _MMIO(0x4028) 2458 #define GEN7_GFX_PRIO_CTRL _MMIO(0x402C) 2459 #define ARB_MODE _MMIO(0x4030) 2460 #define ARB_MODE_SWIZZLE_SNB (1 << 4) 2461 #define ARB_MODE_SWIZZLE_IVB (1 << 5) 2462 #define GEN7_GFX_PEND_TLB0 _MMIO(0x4034) 2463 #define GEN7_GFX_PEND_TLB1 _MMIO(0x4038) 2464 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */ 2465 #define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4) 2466 #define GEN7_LRA_LIMITS_REG_NUM 13 2467 #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070) 2468 #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074) 2469 2470 #define GAMTARBMODE _MMIO(0x04a08) 2471 #define ARB_MODE_BWGTLB_DISABLE (1 << 9) 2472 #define ARB_MODE_SWIZZLE_BDW (1 << 1) 2473 #define RENDER_HWS_PGA_GEN7 _MMIO(0x04080) 2474 #define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100 * (engine)->hw_id) 2475 #define GEN8_RING_FAULT_REG _MMIO(0x4094) 2476 #define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7) 2477 #define RING_FAULT_GTTSEL_MASK (1 << 11) 2478 #define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff) 2479 #define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3) 2480 #define RING_FAULT_VALID (1 << 0) 2481 #define DONE_REG _MMIO(0x40b0) 2482 #define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0) 2483 #define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4) 2484 #define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + (index) * 4) 2485 #define BSD_HWS_PGA_GEN7 _MMIO(0x04180) 2486 #define BLT_HWS_PGA_GEN7 _MMIO(0x04280) 2487 #define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380) 2488 #define RING_ACTHD(base) _MMIO((base) + 0x74) 2489 #define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c) 2490 #define RING_NOPID(base) _MMIO((base) + 0x94) 2491 #define RING_IMR(base) _MMIO((base) + 0xa8) 2492 #define RING_HWSTAM(base) _MMIO((base) + 0x98) 2493 #define RING_TIMESTAMP(base) _MMIO((base) + 0x358) 2494 #define RING_TIMESTAMP_UDW(base) _MMIO((base) + 0x358 + 4) 2495 #define TAIL_ADDR 0x001FFFF8 2496 #define HEAD_WRAP_COUNT 0xFFE00000 2497 #define HEAD_WRAP_ONE 0x00200000 2498 #define HEAD_ADDR 0x001FFFFC 2499 #define RING_NR_PAGES 0x001FF000 2500 #define RING_REPORT_MASK 0x00000006 2501 #define RING_REPORT_64K 0x00000002 2502 #define RING_REPORT_128K 0x00000004 2503 #define RING_NO_REPORT 0x00000000 2504 #define RING_VALID_MASK 0x00000001 2505 #define RING_VALID 0x00000001 2506 #define RING_INVALID 0x00000000 2507 #define RING_WAIT_I8XX (1 << 0) /* gen2, PRBx_HEAD */ 2508 #define RING_WAIT (1 << 11) /* gen3+, PRBx_CTL */ 2509 #define RING_WAIT_SEMAPHORE (1 << 10) /* gen6+ */ 2510 2511 #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4) 2512 #define RING_MAX_NONPRIV_SLOTS 12 2513 2514 #define GEN7_TLB_RD_ADDR _MMIO(0x4700) 2515 2516 #define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0) 2517 #define GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS (1 << 18) 2518 2519 #define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080) 2520 #define GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF 2521 #define GAMW_ECO_DEV_CTX_RELOAD_DISABLE (1 << 7) 2522 2523 #define GAMT_CHKN_BIT_REG _MMIO(0x4ab8) 2524 #define GAMT_CHKN_DISABLE_L3_COH_PIPE (1 << 31) 2525 #define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1 << 28) 2526 #define GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT (1 << 24) 2527 2528 #if 0 2529 #define PRB0_TAIL _MMIO(0x2030) 2530 #define PRB0_HEAD _MMIO(0x2034) 2531 #define PRB0_START _MMIO(0x2038) 2532 #define PRB0_CTL _MMIO(0x203c) 2533 #define PRB1_TAIL _MMIO(0x2040) /* 915+ only */ 2534 #define PRB1_HEAD _MMIO(0x2044) /* 915+ only */ 2535 #define PRB1_START _MMIO(0x2048) /* 915+ only */ 2536 #define PRB1_CTL _MMIO(0x204c) /* 915+ only */ 2537 #endif 2538 #define IPEIR_I965 _MMIO(0x2064) 2539 #define IPEHR_I965 _MMIO(0x2068) 2540 #define GEN7_SC_INSTDONE _MMIO(0x7100) 2541 #define GEN7_SAMPLER_INSTDONE _MMIO(0xe160) 2542 #define GEN7_ROW_INSTDONE _MMIO(0xe164) 2543 #define GEN8_MCR_SELECTOR _MMIO(0xfdc) 2544 #define GEN8_MCR_SLICE(slice) (((slice) & 3) << 26) 2545 #define GEN8_MCR_SLICE_MASK GEN8_MCR_SLICE(3) 2546 #define GEN8_MCR_SUBSLICE(subslice) (((subslice) & 3) << 24) 2547 #define GEN8_MCR_SUBSLICE_MASK GEN8_MCR_SUBSLICE(3) 2548 #define GEN11_MCR_SLICE(slice) (((slice) & 0xf) << 27) 2549 #define GEN11_MCR_SLICE_MASK GEN11_MCR_SLICE(0xf) 2550 #define GEN11_MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24) 2551 #define GEN11_MCR_SUBSLICE_MASK GEN11_MCR_SUBSLICE(0x7) 2552 #define RING_IPEIR(base) _MMIO((base) + 0x64) 2553 #define RING_IPEHR(base) _MMIO((base) + 0x68) 2554 /* 2555 * On GEN4, only the render ring INSTDONE exists and has a different 2556 * layout than the GEN7+ version. 2557 * The GEN2 counterpart of this register is GEN2_INSTDONE. 2558 */ 2559 #define RING_INSTDONE(base) _MMIO((base) + 0x6c) 2560 #define RING_INSTPS(base) _MMIO((base) + 0x70) 2561 #define RING_DMA_FADD(base) _MMIO((base) + 0x78) 2562 #define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60) /* gen8+ */ 2563 #define RING_INSTPM(base) _MMIO((base) + 0xc0) 2564 #define RING_MI_MODE(base) _MMIO((base) + 0x9c) 2565 #define INSTPS _MMIO(0x2070) /* 965+ only */ 2566 #define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */ 2567 #define ACTHD_I965 _MMIO(0x2074) 2568 #define HWS_PGA _MMIO(0x2080) 2569 #define HWS_ADDRESS_MASK 0xfffff000 2570 #define HWS_START_ADDRESS_SHIFT 4 2571 #define PWRCTXA _MMIO(0x2088) /* 965GM+ only */ 2572 #define PWRCTX_EN (1 << 0) 2573 #define IPEIR(base) _MMIO((base) + 0x88) 2574 #define IPEHR(base) _MMIO((base) + 0x8c) 2575 #define GEN2_INSTDONE _MMIO(0x2090) 2576 #define NOPID _MMIO(0x2094) 2577 #define HWSTAM _MMIO(0x2098) 2578 #define DMA_FADD_I8XX(base) _MMIO((base) + 0xd0) 2579 #define RING_BBSTATE(base) _MMIO((base) + 0x110) 2580 #define RING_BB_PPGTT (1 << 5) 2581 #define RING_SBBADDR(base) _MMIO((base) + 0x114) /* hsw+ */ 2582 #define RING_SBBSTATE(base) _MMIO((base) + 0x118) /* hsw+ */ 2583 #define RING_SBBADDR_UDW(base) _MMIO((base) + 0x11c) /* gen8+ */ 2584 #define RING_BBADDR(base) _MMIO((base) + 0x140) 2585 #define RING_BBADDR_UDW(base) _MMIO((base) + 0x168) /* gen8+ */ 2586 #define RING_BB_PER_CTX_PTR(base) _MMIO((base) + 0x1c0) /* gen8+ */ 2587 #define RING_INDIRECT_CTX(base) _MMIO((base) + 0x1c4) /* gen8+ */ 2588 #define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */ 2589 #define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8) /* gen8+ */ 2590 2591 #define ERROR_GEN6 _MMIO(0x40a0) 2592 #define GEN7_ERR_INT _MMIO(0x44040) 2593 #define ERR_INT_POISON (1 << 31) 2594 #define ERR_INT_MMIO_UNCLAIMED (1 << 13) 2595 #define ERR_INT_PIPE_CRC_DONE_C (1 << 8) 2596 #define ERR_INT_FIFO_UNDERRUN_C (1 << 6) 2597 #define ERR_INT_PIPE_CRC_DONE_B (1 << 5) 2598 #define ERR_INT_FIFO_UNDERRUN_B (1 << 3) 2599 #define ERR_INT_PIPE_CRC_DONE_A (1 << 2) 2600 #define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3)) 2601 #define ERR_INT_FIFO_UNDERRUN_A (1 << 0) 2602 #define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) 2603 2604 #define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10) 2605 #define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14) 2606 #define FAULT_VA_HIGH_BITS (0xf << 0) 2607 #define FAULT_GTT_SEL (1 << 4) 2608 2609 #define FPGA_DBG _MMIO(0x42300) 2610 #define FPGA_DBG_RM_NOCLAIM (1 << 31) 2611 2612 #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028) 2613 #define CLAIM_ER_CLR (1 << 31) 2614 #define CLAIM_ER_OVERFLOW (1 << 16) 2615 #define CLAIM_ER_CTR_MASK 0xffff 2616 2617 #define DERRMR _MMIO(0x44050) 2618 /* Note that HBLANK events are reserved on bdw+ */ 2619 #define DERRMR_PIPEA_SCANLINE (1 << 0) 2620 #define DERRMR_PIPEA_PRI_FLIP_DONE (1 << 1) 2621 #define DERRMR_PIPEA_SPR_FLIP_DONE (1 << 2) 2622 #define DERRMR_PIPEA_VBLANK (1 << 3) 2623 #define DERRMR_PIPEA_HBLANK (1 << 5) 2624 #define DERRMR_PIPEB_SCANLINE (1 << 8) 2625 #define DERRMR_PIPEB_PRI_FLIP_DONE (1 << 9) 2626 #define DERRMR_PIPEB_SPR_FLIP_DONE (1 << 10) 2627 #define DERRMR_PIPEB_VBLANK (1 << 11) 2628 #define DERRMR_PIPEB_HBLANK (1 << 13) 2629 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */ 2630 #define DERRMR_PIPEC_SCANLINE (1 << 14) 2631 #define DERRMR_PIPEC_PRI_FLIP_DONE (1 << 15) 2632 #define DERRMR_PIPEC_SPR_FLIP_DONE (1 << 20) 2633 #define DERRMR_PIPEC_VBLANK (1 << 21) 2634 #define DERRMR_PIPEC_HBLANK (1 << 22) 2635 2636 2637 /* GM45+ chicken bits -- debug workaround bits that may be required 2638 * for various sorts of correct behavior. The top 16 bits of each are 2639 * the enables for writing to the corresponding low bit. 2640 */ 2641 #define _3D_CHICKEN _MMIO(0x2084) 2642 #define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10) 2643 #define _3D_CHICKEN2 _MMIO(0x208c) 2644 2645 #define FF_SLICE_CHICKEN _MMIO(0x2088) 2646 #define FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX (1 << 1) 2647 2648 /* Disables pipelining of read flushes past the SF-WIZ interface. 2649 * Required on all Ironlake steppings according to the B-Spec, but the 2650 * particular danger of not doing so is not specified. 2651 */ 2652 # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) 2653 #define _3D_CHICKEN3 _MMIO(0x2090) 2654 #define _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX (1 << 12) 2655 #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10) 2656 #define _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE (1 << 5) 2657 #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5) 2658 #define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x) << 1) /* gen8+ */ 2659 #define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */ 2660 2661 #define MI_MODE _MMIO(0x209c) 2662 # define VS_TIMER_DISPATCH (1 << 6) 2663 # define MI_FLUSH_ENABLE (1 << 12) 2664 # define ASYNC_FLIP_PERF_DISABLE (1 << 14) 2665 # define MODE_IDLE (1 << 9) 2666 # define STOP_RING (1 << 8) 2667 2668 #define GEN6_GT_MODE _MMIO(0x20d0) 2669 #define GEN7_GT_MODE _MMIO(0x7008) 2670 #define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7)) 2671 #define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0) 2672 #define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1) 2673 #define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0) 2674 #define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1) 2675 #define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5) 2676 #define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2)) 2677 #define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2)) 2678 2679 /* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */ 2680 #define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4) 2681 #define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2) 2682 #define GEN11_ENABLE_32_PLANE_MODE (1 << 7) 2683 2684 /* WaClearTdlStateAckDirtyBits */ 2685 #define GEN8_STATE_ACK _MMIO(0x20F0) 2686 #define GEN9_STATE_ACK_SLICE1 _MMIO(0x20F8) 2687 #define GEN9_STATE_ACK_SLICE2 _MMIO(0x2100) 2688 #define GEN9_STATE_ACK_TDL0 (1 << 12) 2689 #define GEN9_STATE_ACK_TDL1 (1 << 13) 2690 #define GEN9_STATE_ACK_TDL2 (1 << 14) 2691 #define GEN9_STATE_ACK_TDL3 (1 << 15) 2692 #define GEN9_SUBSLICE_TDL_ACK_BITS \ 2693 (GEN9_STATE_ACK_TDL3 | GEN9_STATE_ACK_TDL2 | \ 2694 GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0) 2695 2696 #define GFX_MODE _MMIO(0x2520) 2697 #define GFX_MODE_GEN7 _MMIO(0x229c) 2698 #define RING_MODE_GEN7(engine) _MMIO((engine)->mmio_base + 0x29c) 2699 #define GFX_RUN_LIST_ENABLE (1 << 15) 2700 #define GFX_INTERRUPT_STEERING (1 << 14) 2701 #define GFX_TLB_INVALIDATE_EXPLICIT (1 << 13) 2702 #define GFX_SURFACE_FAULT_ENABLE (1 << 12) 2703 #define GFX_REPLAY_MODE (1 << 11) 2704 #define GFX_PSMI_GRANULARITY (1 << 10) 2705 #define GFX_PPGTT_ENABLE (1 << 9) 2706 #define GEN8_GFX_PPGTT_48B (1 << 7) 2707 2708 #define GFX_FORWARD_VBLANK_MASK (3 << 5) 2709 #define GFX_FORWARD_VBLANK_NEVER (0 << 5) 2710 #define GFX_FORWARD_VBLANK_ALWAYS (1 << 5) 2711 #define GFX_FORWARD_VBLANK_COND (2 << 5) 2712 2713 #define GEN11_GFX_DISABLE_LEGACY_MODE (1 << 3) 2714 2715 #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030) 2716 #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034) 2717 #define SCPD0 _MMIO(0x209c) /* 915+ only */ 2718 #define GEN2_IER _MMIO(0x20a0) 2719 #define GEN2_IIR _MMIO(0x20a4) 2720 #define GEN2_IMR _MMIO(0x20a8) 2721 #define GEN2_ISR _MMIO(0x20ac) 2722 #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060) 2723 #define GINT_DIS (1 << 22) 2724 #define GCFG_DIS (1 << 8) 2725 #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064) 2726 #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084) 2727 #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0) 2728 #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4) 2729 #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8) 2730 #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac) 2731 #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120) 2732 #define VLV_PCBR_ADDR_SHIFT 12 2733 2734 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */ 2735 #define EIR _MMIO(0x20b0) 2736 #define EMR _MMIO(0x20b4) 2737 #define ESR _MMIO(0x20b8) 2738 #define GM45_ERROR_PAGE_TABLE (1 << 5) 2739 #define GM45_ERROR_MEM_PRIV (1 << 4) 2740 #define I915_ERROR_PAGE_TABLE (1 << 4) 2741 #define GM45_ERROR_CP_PRIV (1 << 3) 2742 #define I915_ERROR_MEMORY_REFRESH (1 << 1) 2743 #define I915_ERROR_INSTRUCTION (1 << 0) 2744 #define INSTPM _MMIO(0x20c0) 2745 #define INSTPM_SELF_EN (1 << 12) /* 915GM only */ 2746 #define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts 2747 will not assert AGPBUSY# and will only 2748 be delivered when out of C3. */ 2749 #define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */ 2750 #define INSTPM_TLB_INVALIDATE (1 << 9) 2751 #define INSTPM_SYNC_FLUSH (1 << 5) 2752 #define ACTHD(base) _MMIO((base) + 0xc8) 2753 #define MEM_MODE _MMIO(0x20cc) 2754 #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */ 2755 #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */ 2756 #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */ 2757 #define FW_BLC _MMIO(0x20d8) 2758 #define FW_BLC2 _MMIO(0x20dc) 2759 #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */ 2760 #define FW_BLC_SELF_EN_MASK (1 << 31) 2761 #define FW_BLC_SELF_FIFO_MASK (1 << 16) /* 945 only */ 2762 #define FW_BLC_SELF_EN (1 << 15) /* 945 only */ 2763 #define MM_BURST_LENGTH 0x00700000 2764 #define MM_FIFO_WATERMARK 0x0001F000 2765 #define LM_BURST_LENGTH 0x00000700 2766 #define LM_FIFO_WATERMARK 0x0000001F 2767 #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */ 2768 2769 #define MBUS_ABOX_CTL _MMIO(0x45038) 2770 #define MBUS_ABOX_BW_CREDIT_MASK (3 << 20) 2771 #define MBUS_ABOX_BW_CREDIT(x) ((x) << 20) 2772 #define MBUS_ABOX_B_CREDIT_MASK (0xF << 16) 2773 #define MBUS_ABOX_B_CREDIT(x) ((x) << 16) 2774 #define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8) 2775 #define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8) 2776 #define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0) 2777 #define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0) 2778 2779 #define _PIPEA_MBUS_DBOX_CTL 0x7003C 2780 #define _PIPEB_MBUS_DBOX_CTL 0x7103C 2781 #define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \ 2782 _PIPEB_MBUS_DBOX_CTL) 2783 #define MBUS_DBOX_BW_CREDIT_MASK (3 << 14) 2784 #define MBUS_DBOX_BW_CREDIT(x) ((x) << 14) 2785 #define MBUS_DBOX_B_CREDIT_MASK (0x1F << 8) 2786 #define MBUS_DBOX_B_CREDIT(x) ((x) << 8) 2787 #define MBUS_DBOX_A_CREDIT_MASK (0xF << 0) 2788 #define MBUS_DBOX_A_CREDIT(x) ((x) << 0) 2789 2790 #define MBUS_UBOX_CTL _MMIO(0x4503C) 2791 #define MBUS_BBOX_CTL_S1 _MMIO(0x45040) 2792 #define MBUS_BBOX_CTL_S2 _MMIO(0x45044) 2793 2794 /* Make render/texture TLB fetches lower priorty than associated data 2795 * fetches. This is not turned on by default 2796 */ 2797 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) 2798 2799 /* Isoch request wait on GTT enable (Display A/B/C streams). 2800 * Make isoch requests stall on the TLB update. May cause 2801 * display underruns (test mode only) 2802 */ 2803 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14) 2804 2805 /* Block grant count for isoch requests when block count is 2806 * set to a finite value. 2807 */ 2808 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12) 2809 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ 2810 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ 2811 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ 2812 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ 2813 2814 /* Enable render writes to complete in C2/C3/C4 power states. 2815 * If this isn't enabled, render writes are prevented in low 2816 * power states. That seems bad to me. 2817 */ 2818 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) 2819 2820 /* This acknowledges an async flip immediately instead 2821 * of waiting for 2TLB fetches. 2822 */ 2823 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) 2824 2825 /* Enables non-sequential data reads through arbiter 2826 */ 2827 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) 2828 2829 /* Disable FSB snooping of cacheable write cycles from binner/render 2830 * command stream 2831 */ 2832 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) 2833 2834 /* Arbiter time slice for non-isoch streams */ 2835 #define MI_ARB_TIME_SLICE_MASK (7 << 5) 2836 #define MI_ARB_TIME_SLICE_1 (0 << 5) 2837 #define MI_ARB_TIME_SLICE_2 (1 << 5) 2838 #define MI_ARB_TIME_SLICE_4 (2 << 5) 2839 #define MI_ARB_TIME_SLICE_6 (3 << 5) 2840 #define MI_ARB_TIME_SLICE_8 (4 << 5) 2841 #define MI_ARB_TIME_SLICE_10 (5 << 5) 2842 #define MI_ARB_TIME_SLICE_14 (6 << 5) 2843 #define MI_ARB_TIME_SLICE_16 (7 << 5) 2844 2845 /* Low priority grace period page size */ 2846 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ 2847 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) 2848 2849 /* Disable display A/B trickle feed */ 2850 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) 2851 2852 /* Set display plane priority */ 2853 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ 2854 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ 2855 2856 #define MI_STATE _MMIO(0x20e4) /* gen2 only */ 2857 #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */ 2858 #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */ 2859 2860 #define CACHE_MODE_0 _MMIO(0x2120) /* 915+ only */ 2861 #define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1 << 8) 2862 #define CM0_IZ_OPT_DISABLE (1 << 6) 2863 #define CM0_ZR_OPT_DISABLE (1 << 5) 2864 #define CM0_STC_EVICT_DISABLE_LRA_SNB (1 << 5) 2865 #define CM0_DEPTH_EVICT_DISABLE (1 << 4) 2866 #define CM0_COLOR_EVICT_DISABLE (1 << 3) 2867 #define CM0_DEPTH_WRITE_DISABLE (1 << 1) 2868 #define CM0_RC_OP_FLUSH_DISABLE (1 << 0) 2869 #define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */ 2870 #define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008) 2871 #define GFX_FLSH_CNTL_EN (1 << 0) 2872 #define ECOSKPD _MMIO(0x21d0) 2873 #define ECO_GATING_CX_ONLY (1 << 3) 2874 #define ECO_FLIP_DONE (1 << 0) 2875 2876 #define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */ 2877 #define RC_OP_FLUSH_ENABLE (1 << 0) 2878 #define HIZ_RAW_STALL_OPT_DISABLE (1 << 2) 2879 #define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */ 2880 #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1 << 6) 2881 #define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1 << 6) 2882 #define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1 << 1) 2883 2884 #define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0) 2885 #define GEN6_BLITTER_LOCK_SHIFT 16 2886 #define GEN6_BLITTER_FBC_NOTIFY (1 << 3) 2887 2888 #define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050) 2889 #define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0) 2890 #define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12) 2891 #define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1 << 10) 2892 2893 #define GEN6_RCS_PWR_FSM _MMIO(0x22ac) 2894 #define GEN9_RCS_FE_FSM2 _MMIO(0x22a4) 2895 2896 #define GEN10_CACHE_MODE_SS _MMIO(0xe420) 2897 #define FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4) 2898 2899 /* Fuse readout registers for GT */ 2900 #define HSW_PAVP_FUSE1 _MMIO(0x911C) 2901 #define HSW_F1_EU_DIS_SHIFT 16 2902 #define HSW_F1_EU_DIS_MASK (0x3 << HSW_F1_EU_DIS_SHIFT) 2903 #define HSW_F1_EU_DIS_10EUS 0 2904 #define HSW_F1_EU_DIS_8EUS 1 2905 #define HSW_F1_EU_DIS_6EUS 2 2906 2907 #define CHV_FUSE_GT _MMIO(VLV_DISPLAY_BASE + 0x2168) 2908 #define CHV_FGT_DISABLE_SS0 (1 << 10) 2909 #define CHV_FGT_DISABLE_SS1 (1 << 11) 2910 #define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16 2911 #define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT) 2912 #define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20 2913 #define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT) 2914 #define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24 2915 #define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT) 2916 #define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28 2917 #define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT) 2918 2919 #define GEN8_FUSE2 _MMIO(0x9120) 2920 #define GEN8_F2_SS_DIS_SHIFT 21 2921 #define GEN8_F2_SS_DIS_MASK (0x7 << GEN8_F2_SS_DIS_SHIFT) 2922 #define GEN8_F2_S_ENA_SHIFT 25 2923 #define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT) 2924 2925 #define GEN9_F2_SS_DIS_SHIFT 20 2926 #define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT) 2927 2928 #define GEN10_F2_S_ENA_SHIFT 22 2929 #define GEN10_F2_S_ENA_MASK (0x3f << GEN10_F2_S_ENA_SHIFT) 2930 #define GEN10_F2_SS_DIS_SHIFT 18 2931 #define GEN10_F2_SS_DIS_MASK (0xf << GEN10_F2_SS_DIS_SHIFT) 2932 2933 #define GEN10_MIRROR_FUSE3 _MMIO(0x9118) 2934 #define GEN10_L3BANK_PAIR_COUNT 4 2935 #define GEN10_L3BANK_MASK 0x0F 2936 2937 #define GEN8_EU_DISABLE0 _MMIO(0x9134) 2938 #define GEN8_EU_DIS0_S0_MASK 0xffffff 2939 #define GEN8_EU_DIS0_S1_SHIFT 24 2940 #define GEN8_EU_DIS0_S1_MASK (0xff << GEN8_EU_DIS0_S1_SHIFT) 2941 2942 #define GEN8_EU_DISABLE1 _MMIO(0x9138) 2943 #define GEN8_EU_DIS1_S1_MASK 0xffff 2944 #define GEN8_EU_DIS1_S2_SHIFT 16 2945 #define GEN8_EU_DIS1_S2_MASK (0xffff << GEN8_EU_DIS1_S2_SHIFT) 2946 2947 #define GEN8_EU_DISABLE2 _MMIO(0x913c) 2948 #define GEN8_EU_DIS2_S2_MASK 0xff 2949 2950 #define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice) * 0x4) 2951 2952 #define GEN10_EU_DISABLE3 _MMIO(0x9140) 2953 #define GEN10_EU_DIS_SS_MASK 0xff 2954 2955 #define GEN11_GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140) 2956 #define GEN11_GT_VDBOX_DISABLE_MASK 0xff 2957 #define GEN11_GT_VEBOX_DISABLE_SHIFT 16 2958 #define GEN11_GT_VEBOX_DISABLE_MASK (0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT) 2959 2960 #define GEN11_EU_DISABLE _MMIO(0x9134) 2961 #define GEN11_EU_DIS_MASK 0xFF 2962 2963 #define GEN11_GT_SLICE_ENABLE _MMIO(0x9138) 2964 #define GEN11_GT_S_ENA_MASK 0xFF 2965 2966 #define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C) 2967 2968 #define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050) 2969 #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0) 2970 #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2) 2971 #define GEN6_BSD_SLEEP_INDICATOR (1 << 3) 2972 #define GEN6_BSD_GO_INDICATOR (1 << 4) 2973 2974 /* On modern GEN architectures interrupt control consists of two sets 2975 * of registers. The first set pertains to the ring generating the 2976 * interrupt. The second control is for the functional block generating the 2977 * interrupt. These are PM, GT, DE, etc. 2978 * 2979 * Luckily *knocks on wood* all the ring interrupt bits match up with the 2980 * GT interrupt bits, so we don't need to duplicate the defines. 2981 * 2982 * These defines should cover us well from SNB->HSW with minor exceptions 2983 * it can also work on ILK. 2984 */ 2985 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) 2986 #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25) 2987 #define GT_BLT_USER_INTERRUPT (1 << 22) 2988 #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15) 2989 #define GT_BSD_USER_INTERRUPT (1 << 12) 2990 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */ 2991 #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8) 2992 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */ 2993 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4) 2994 #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3) 2995 #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2) 2996 #define GT_RENDER_DEBUG_INTERRUPT (1 << 1) 2997 #define GT_RENDER_USER_INTERRUPT (1 << 0) 2998 2999 #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */ 3000 #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */ 3001 3002 #define GT_PARITY_ERROR(dev_priv) \ 3003 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \ 3004 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0)) 3005 3006 /* These are all the "old" interrupts */ 3007 #define ILK_BSD_USER_INTERRUPT (1 << 5) 3008 3009 #define I915_PM_INTERRUPT (1 << 31) 3010 #define I915_ISP_INTERRUPT (1 << 22) 3011 #define I915_LPE_PIPE_B_INTERRUPT (1 << 21) 3012 #define I915_LPE_PIPE_A_INTERRUPT (1 << 20) 3013 #define I915_MIPIC_INTERRUPT (1 << 19) 3014 #define I915_MIPIA_INTERRUPT (1 << 18) 3015 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18) 3016 #define I915_DISPLAY_PORT_INTERRUPT (1 << 17) 3017 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16) 3018 #define I915_MASTER_ERROR_INTERRUPT (1 << 15) 3019 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14) 3020 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */ 3021 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13) 3022 #define I915_HWB_OOM_INTERRUPT (1 << 13) 3023 #define I915_LPE_PIPE_C_INTERRUPT (1 << 12) 3024 #define I915_SYNC_STATUS_INTERRUPT (1 << 12) 3025 #define I915_MISC_INTERRUPT (1 << 11) 3026 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11) 3027 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10) 3028 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10) 3029 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9) 3030 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9) 3031 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8) 3032 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8) 3033 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7) 3034 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6) 3035 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5) 3036 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4) 3037 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3) 3038 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2) 3039 #define I915_DEBUG_INTERRUPT (1 << 2) 3040 #define I915_WINVALID_INTERRUPT (1 << 1) 3041 #define I915_USER_INTERRUPT (1 << 1) 3042 #define I915_ASLE_INTERRUPT (1 << 0) 3043 #define I915_BSD_USER_INTERRUPT (1 << 25) 3044 3045 #define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000) 3046 #define I915_HDMI_LPE_AUDIO_SIZE 0x1000 3047 3048 /* DisplayPort Audio w/ LPE */ 3049 #define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38) 3050 #define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0) 3051 3052 #define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62F20) 3053 #define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62F30) 3054 #define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62F34) 3055 #define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \ 3056 _VLV_AUD_PORT_EN_B_DBG, \ 3057 _VLV_AUD_PORT_EN_C_DBG, \ 3058 _VLV_AUD_PORT_EN_D_DBG) 3059 #define VLV_AMP_MUTE (1 << 1) 3060 3061 #define GEN6_BSD_RNCID _MMIO(0x12198) 3062 3063 #define GEN7_FF_THREAD_MODE _MMIO(0x20a0) 3064 #define GEN7_FF_SCHED_MASK 0x0077070 3065 #define GEN8_FF_DS_REF_CNT_FFME (1 << 19) 3066 #define GEN7_FF_TS_SCHED_HS1 (0x5 << 16) 3067 #define GEN7_FF_TS_SCHED_HS0 (0x3 << 16) 3068 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16) 3069 #define GEN7_FF_TS_SCHED_HW (0x0 << 16) /* Default */ 3070 #define GEN7_FF_VS_REF_CNT_FFME (1 << 15) 3071 #define GEN7_FF_VS_SCHED_HS1 (0x5 << 12) 3072 #define GEN7_FF_VS_SCHED_HS0 (0x3 << 12) 3073 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12) /* Default */ 3074 #define GEN7_FF_VS_SCHED_HW (0x0 << 12) 3075 #define GEN7_FF_DS_SCHED_HS1 (0x5 << 4) 3076 #define GEN7_FF_DS_SCHED_HS0 (0x3 << 4) 3077 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */ 3078 #define GEN7_FF_DS_SCHED_HW (0x0 << 4) 3079 3080 /* 3081 * Framebuffer compression (915+ only) 3082 */ 3083 3084 #define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */ 3085 #define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */ 3086 #define FBC_CONTROL _MMIO(0x3208) 3087 #define FBC_CTL_EN (1 << 31) 3088 #define FBC_CTL_PERIODIC (1 << 30) 3089 #define FBC_CTL_INTERVAL_SHIFT (16) 3090 #define FBC_CTL_UNCOMPRESSIBLE (1 << 14) 3091 #define FBC_CTL_C3_IDLE (1 << 13) 3092 #define FBC_CTL_STRIDE_SHIFT (5) 3093 #define FBC_CTL_FENCENO_SHIFT (0) 3094 #define FBC_COMMAND _MMIO(0x320c) 3095 #define FBC_CMD_COMPRESS (1 << 0) 3096 #define FBC_STATUS _MMIO(0x3210) 3097 #define FBC_STAT_COMPRESSING (1 << 31) 3098 #define FBC_STAT_COMPRESSED (1 << 30) 3099 #define FBC_STAT_MODIFIED (1 << 29) 3100 #define FBC_STAT_CURRENT_LINE_SHIFT (0) 3101 #define FBC_CONTROL2 _MMIO(0x3214) 3102 #define FBC_CTL_FENCE_DBL (0 << 4) 3103 #define FBC_CTL_IDLE_IMM (0 << 2) 3104 #define FBC_CTL_IDLE_FULL (1 << 2) 3105 #define FBC_CTL_IDLE_LINE (2 << 2) 3106 #define FBC_CTL_IDLE_DEBUG (3 << 2) 3107 #define FBC_CTL_CPU_FENCE (1 << 1) 3108 #define FBC_CTL_PLANE(plane) ((plane) << 0) 3109 #define FBC_FENCE_OFF _MMIO(0x3218) /* BSpec typo has 321Bh */ 3110 #define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) 3111 3112 #define FBC_LL_SIZE (1536) 3113 3114 #define FBC_LLC_READ_CTRL _MMIO(0x9044) 3115 #define FBC_LLC_FULLY_OPEN (1 << 30) 3116 3117 /* Framebuffer compression for GM45+ */ 3118 #define DPFC_CB_BASE _MMIO(0x3200) 3119 #define DPFC_CONTROL _MMIO(0x3208) 3120 #define DPFC_CTL_EN (1 << 31) 3121 #define DPFC_CTL_PLANE(plane) ((plane) << 30) 3122 #define IVB_DPFC_CTL_PLANE(plane) ((plane) << 29) 3123 #define DPFC_CTL_FENCE_EN (1 << 29) 3124 #define IVB_DPFC_CTL_FENCE_EN (1 << 28) 3125 #define DPFC_CTL_PERSISTENT_MODE (1 << 25) 3126 #define DPFC_SR_EN (1 << 10) 3127 #define DPFC_CTL_LIMIT_1X (0 << 6) 3128 #define DPFC_CTL_LIMIT_2X (1 << 6) 3129 #define DPFC_CTL_LIMIT_4X (2 << 6) 3130 #define DPFC_RECOMP_CTL _MMIO(0x320c) 3131 #define DPFC_RECOMP_STALL_EN (1 << 27) 3132 #define DPFC_RECOMP_STALL_WM_SHIFT (16) 3133 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) 3134 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) 3135 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) 3136 #define DPFC_STATUS _MMIO(0x3210) 3137 #define DPFC_INVAL_SEG_SHIFT (16) 3138 #define DPFC_INVAL_SEG_MASK (0x07ff0000) 3139 #define DPFC_COMP_SEG_SHIFT (0) 3140 #define DPFC_COMP_SEG_MASK (0x000007ff) 3141 #define DPFC_STATUS2 _MMIO(0x3214) 3142 #define DPFC_FENCE_YOFF _MMIO(0x3218) 3143 #define DPFC_CHICKEN _MMIO(0x3224) 3144 #define DPFC_HT_MODIFY (1 << 31) 3145 3146 /* Framebuffer compression for Ironlake */ 3147 #define ILK_DPFC_CB_BASE _MMIO(0x43200) 3148 #define ILK_DPFC_CONTROL _MMIO(0x43208) 3149 #define FBC_CTL_FALSE_COLOR (1 << 10) 3150 /* The bit 28-8 is reserved */ 3151 #define DPFC_RESERVED (0x1FFFFF00) 3152 #define ILK_DPFC_RECOMP_CTL _MMIO(0x4320c) 3153 #define ILK_DPFC_STATUS _MMIO(0x43210) 3154 #define ILK_DPFC_COMP_SEG_MASK 0x7ff 3155 #define IVB_FBC_STATUS2 _MMIO(0x43214) 3156 #define IVB_FBC_COMP_SEG_MASK 0x7ff 3157 #define BDW_FBC_COMP_SEG_MASK 0xfff 3158 #define ILK_DPFC_FENCE_YOFF _MMIO(0x43218) 3159 #define ILK_DPFC_CHICKEN _MMIO(0x43224) 3160 #define ILK_DPFC_DISABLE_DUMMY0 (1 << 8) 3161 #define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1 << 23) 3162 #define ILK_FBC_RT_BASE _MMIO(0x2128) 3163 #define ILK_FBC_RT_VALID (1 << 0) 3164 #define SNB_FBC_FRONT_BUFFER (1 << 1) 3165 3166 #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000) 3167 #define ILK_FBCQ_DIS (1 << 22) 3168 #define ILK_PABSTRETCH_DIS (1 << 21) 3169 3170 3171 /* 3172 * Framebuffer compression for Sandybridge 3173 * 3174 * The following two registers are of type GTTMMADR 3175 */ 3176 #define SNB_DPFC_CTL_SA _MMIO(0x100100) 3177 #define SNB_CPU_FENCE_ENABLE (1 << 29) 3178 #define DPFC_CPU_FENCE_OFFSET _MMIO(0x100104) 3179 3180 /* Framebuffer compression for Ivybridge */ 3181 #define IVB_FBC_RT_BASE _MMIO(0x7020) 3182 3183 #define IPS_CTL _MMIO(0x43408) 3184 #define IPS_ENABLE (1 << 31) 3185 3186 #define MSG_FBC_REND_STATE _MMIO(0x50380) 3187 #define FBC_REND_NUKE (1 << 2) 3188 #define FBC_REND_CACHE_CLEAN (1 << 1) 3189 3190 /* 3191 * GPIO regs 3192 */ 3193 #define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + \ 3194 4 * (gpio)) 3195 3196 # define GPIO_CLOCK_DIR_MASK (1 << 0) 3197 # define GPIO_CLOCK_DIR_IN (0 << 1) 3198 # define GPIO_CLOCK_DIR_OUT (1 << 1) 3199 # define GPIO_CLOCK_VAL_MASK (1 << 2) 3200 # define GPIO_CLOCK_VAL_OUT (1 << 3) 3201 # define GPIO_CLOCK_VAL_IN (1 << 4) 3202 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) 3203 # define GPIO_DATA_DIR_MASK (1 << 8) 3204 # define GPIO_DATA_DIR_IN (0 << 9) 3205 # define GPIO_DATA_DIR_OUT (1 << 9) 3206 # define GPIO_DATA_VAL_MASK (1 << 10) 3207 # define GPIO_DATA_VAL_OUT (1 << 11) 3208 # define GPIO_DATA_VAL_IN (1 << 12) 3209 # define GPIO_DATA_PULLUP_DISABLE (1 << 13) 3210 3211 #define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */ 3212 #define GMBUS_AKSV_SELECT (1 << 11) 3213 #define GMBUS_RATE_100KHZ (0 << 8) 3214 #define GMBUS_RATE_50KHZ (1 << 8) 3215 #define GMBUS_RATE_400KHZ (2 << 8) /* reserved on Pineview */ 3216 #define GMBUS_RATE_1MHZ (3 << 8) /* reserved on Pineview */ 3217 #define GMBUS_HOLD_EXT (1 << 7) /* 300ns hold time, rsvd on Pineview */ 3218 #define GMBUS_BYTE_CNT_OVERRIDE (1 << 6) 3219 #define GMBUS_PIN_DISABLED 0 3220 #define GMBUS_PIN_SSC 1 3221 #define GMBUS_PIN_VGADDC 2 3222 #define GMBUS_PIN_PANEL 3 3223 #define GMBUS_PIN_DPD_CHV 3 /* HDMID_CHV */ 3224 #define GMBUS_PIN_DPC 4 /* HDMIC */ 3225 #define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */ 3226 #define GMBUS_PIN_DPD 6 /* HDMID */ 3227 #define GMBUS_PIN_RESERVED 7 /* 7 reserved */ 3228 #define GMBUS_PIN_1_BXT 1 /* BXT+ (atom) and CNP+ (big core) */ 3229 #define GMBUS_PIN_2_BXT 2 3230 #define GMBUS_PIN_3_BXT 3 3231 #define GMBUS_PIN_4_CNP 4 3232 #define GMBUS_PIN_9_TC1_ICP 9 3233 #define GMBUS_PIN_10_TC2_ICP 10 3234 #define GMBUS_PIN_11_TC3_ICP 11 3235 #define GMBUS_PIN_12_TC4_ICP 12 3236 3237 #define GMBUS_NUM_PINS 13 /* including 0 */ 3238 #define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */ 3239 #define GMBUS_SW_CLR_INT (1 << 31) 3240 #define GMBUS_SW_RDY (1 << 30) 3241 #define GMBUS_ENT (1 << 29) /* enable timeout */ 3242 #define GMBUS_CYCLE_NONE (0 << 25) 3243 #define GMBUS_CYCLE_WAIT (1 << 25) 3244 #define GMBUS_CYCLE_INDEX (2 << 25) 3245 #define GMBUS_CYCLE_STOP (4 << 25) 3246 #define GMBUS_BYTE_COUNT_SHIFT 16 3247 #define GMBUS_BYTE_COUNT_MAX 256U 3248 #define GEN9_GMBUS_BYTE_COUNT_MAX 511U 3249 #define GMBUS_SLAVE_INDEX_SHIFT 8 3250 #define GMBUS_SLAVE_ADDR_SHIFT 1 3251 #define GMBUS_SLAVE_READ (1 << 0) 3252 #define GMBUS_SLAVE_WRITE (0 << 0) 3253 #define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */ 3254 #define GMBUS_INUSE (1 << 15) 3255 #define GMBUS_HW_WAIT_PHASE (1 << 14) 3256 #define GMBUS_STALL_TIMEOUT (1 << 13) 3257 #define GMBUS_INT (1 << 12) 3258 #define GMBUS_HW_RDY (1 << 11) 3259 #define GMBUS_SATOER (1 << 10) 3260 #define GMBUS_ACTIVE (1 << 9) 3261 #define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */ 3262 #define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */ 3263 #define GMBUS_SLAVE_TIMEOUT_EN (1 << 4) 3264 #define GMBUS_NAK_EN (1 << 3) 3265 #define GMBUS_IDLE_EN (1 << 2) 3266 #define GMBUS_HW_WAIT_EN (1 << 1) 3267 #define GMBUS_HW_RDY_EN (1 << 0) 3268 #define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */ 3269 #define GMBUS_2BYTE_INDEX_EN (1 << 31) 3270 3271 /* 3272 * Clock control & power management 3273 */ 3274 #define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014) 3275 #define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018) 3276 #define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030) 3277 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) 3278 3279 #define VGA0 _MMIO(0x6000) 3280 #define VGA1 _MMIO(0x6004) 3281 #define VGA_PD _MMIO(0x6010) 3282 #define VGA0_PD_P2_DIV_4 (1 << 7) 3283 #define VGA0_PD_P1_DIV_2 (1 << 5) 3284 #define VGA0_PD_P1_SHIFT 0 3285 #define VGA0_PD_P1_MASK (0x1f << 0) 3286 #define VGA1_PD_P2_DIV_4 (1 << 15) 3287 #define VGA1_PD_P1_DIV_2 (1 << 13) 3288 #define VGA1_PD_P1_SHIFT 8 3289 #define VGA1_PD_P1_MASK (0x1f << 8) 3290 #define DPLL_VCO_ENABLE (1 << 31) 3291 #define DPLL_SDVO_HIGH_SPEED (1 << 30) 3292 #define DPLL_DVO_2X_MODE (1 << 30) 3293 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) 3294 #define DPLL_SYNCLOCK_ENABLE (1 << 29) 3295 #define DPLL_REF_CLK_ENABLE_VLV (1 << 29) 3296 #define DPLL_VGA_MODE_DIS (1 << 28) 3297 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 3298 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 3299 #define DPLL_MODE_MASK (3 << 26) 3300 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 3301 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 3302 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 3303 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 3304 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 3305 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 3306 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ 3307 #define DPLL_LOCK_VLV (1 << 15) 3308 #define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14) 3309 #define DPLL_INTEGRATED_REF_CLK_VLV (1 << 13) 3310 #define DPLL_SSC_REF_CLK_CHV (1 << 13) 3311 #define DPLL_PORTC_READY_MASK (0xf << 4) 3312 #define DPLL_PORTB_READY_MASK (0xf) 3313 3314 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 3315 3316 /* Additional CHV pll/phy registers */ 3317 #define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240) 3318 #define DPLL_PORTD_READY_MASK (0xf) 3319 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100) 3320 #define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2 * (phy) + (ch) + 27)) 3321 #define PHY_LDO_DELAY_0NS 0x0 3322 #define PHY_LDO_DELAY_200NS 0x1 3323 #define PHY_LDO_DELAY_600NS 0x2 3324 #define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2 * (phy) + 23)) 3325 #define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11)) 3326 #define PHY_CH_SU_PSR 0x1 3327 #define PHY_CH_DEEP_PSR 0x7 3328 #define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6 * (phy) + 3 * (ch) + 2)) 3329 #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy)) 3330 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104) 3331 #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30)) 3332 #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch)))) 3333 #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline)))) 3334 3335 /* 3336 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 3337 * this field (only one bit may be set). 3338 */ 3339 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 3340 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 3341 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 3342 /* i830, required in DVO non-gang */ 3343 #define PLL_P2_DIVIDE_BY_4 (1 << 23) 3344 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 3345 #define PLL_REF_INPUT_DREFCLK (0 << 13) 3346 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 3347 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 3348 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 3349 #define PLL_REF_INPUT_MASK (3 << 13) 3350 #define PLL_LOAD_PULSE_PHASE_SHIFT 9 3351 /* Ironlake */ 3352 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 3353 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) 3354 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9) 3355 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 3356 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff 3357 3358 /* 3359 * Parallel to Serial Load Pulse phase selection. 3360 * Selects the phase for the 10X DPLL clock for the PCIe 3361 * digital display port. The range is 4 to 13; 10 or more 3362 * is just a flip delay. The default is 6 3363 */ 3364 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 3365 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 3366 /* 3367 * SDVO multiplier for 945G/GM. Not used on 965. 3368 */ 3369 #define SDVO_MULTIPLIER_MASK 0x000000ff 3370 #define SDVO_MULTIPLIER_SHIFT_HIRES 4 3371 #define SDVO_MULTIPLIER_SHIFT_VGA 0 3372 3373 #define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c) 3374 #define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020) 3375 #define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c) 3376 #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD) 3377 3378 /* 3379 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 3380 * 3381 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 3382 */ 3383 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 3384 #define DPLL_MD_UDI_DIVIDER_SHIFT 24 3385 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 3386 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 3387 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 3388 /* 3389 * SDVO/UDI pixel multiplier. 3390 * 3391 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 3392 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 3393 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 3394 * dummy bytes in the datastream at an increased clock rate, with both sides of 3395 * the link knowing how many bytes are fill. 3396 * 3397 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 3398 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 3399 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 3400 * through an SDVO command. 3401 * 3402 * This register field has values of multiplication factor minus 1, with 3403 * a maximum multiplier of 5 for SDVO. 3404 */ 3405 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 3406 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 3407 /* 3408 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 3409 * This best be set to the default value (3) or the CRT won't work. No, 3410 * I don't entirely understand what this does... 3411 */ 3412 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 3413 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 3414 3415 #define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024) 3416 3417 #define _FPA0 0x6040 3418 #define _FPA1 0x6044 3419 #define _FPB0 0x6048 3420 #define _FPB1 0x604c 3421 #define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0) 3422 #define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1) 3423 #define FP_N_DIV_MASK 0x003f0000 3424 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 3425 #define FP_N_DIV_SHIFT 16 3426 #define FP_M1_DIV_MASK 0x00003f00 3427 #define FP_M1_DIV_SHIFT 8 3428 #define FP_M2_DIV_MASK 0x0000003f 3429 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff 3430 #define FP_M2_DIV_SHIFT 0 3431 #define DPLL_TEST _MMIO(0x606c) 3432 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 3433 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 3434 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 3435 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 3436 #define DPLLB_TEST_N_BYPASS (1 << 19) 3437 #define DPLLB_TEST_M_BYPASS (1 << 18) 3438 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 3439 #define DPLLA_TEST_N_BYPASS (1 << 3) 3440 #define DPLLA_TEST_M_BYPASS (1 << 2) 3441 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 3442 #define D_STATE _MMIO(0x6104) 3443 #define DSTATE_GFX_RESET_I830 (1 << 6) 3444 #define DSTATE_PLL_D3_OFF (1 << 3) 3445 #define DSTATE_GFX_CLOCK_GATING (1 << 1) 3446 #define DSTATE_DOT_CLOCK_GATING (1 << 0) 3447 #define DSPCLK_GATE_D _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x6200) 3448 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ 3449 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ 3450 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ 3451 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ 3452 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ 3453 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ 3454 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ 3455 # define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */ 3456 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ 3457 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ 3458 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ 3459 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ 3460 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ 3461 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ 3462 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ 3463 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ 3464 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ 3465 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ 3466 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ 3467 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ 3468 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) 3469 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) 3470 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) 3471 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) 3472 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ 3473 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ 3474 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ 3475 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) 3476 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) 3477 /* 3478 * This bit must be set on the 830 to prevent hangs when turning off the 3479 * overlay scaler. 3480 */ 3481 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) 3482 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) 3483 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) 3484 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ 3485 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ 3486 3487 #define RENCLK_GATE_D1 _MMIO(0x6204) 3488 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ 3489 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ 3490 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) 3491 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) 3492 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) 3493 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) 3494 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) 3495 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) 3496 # define MAG_CLOCK_GATE_DISABLE (1 << 5) 3497 /* This bit must be unset on 855,865 */ 3498 # define MECI_CLOCK_GATE_DISABLE (1 << 4) 3499 # define DCMP_CLOCK_GATE_DISABLE (1 << 3) 3500 # define MEC_CLOCK_GATE_DISABLE (1 << 2) 3501 # define MECO_CLOCK_GATE_DISABLE (1 << 1) 3502 /* This bit must be set on 855,865. */ 3503 # define SV_CLOCK_GATE_DISABLE (1 << 0) 3504 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) 3505 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) 3506 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) 3507 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) 3508 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) 3509 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) 3510 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) 3511 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) 3512 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) 3513 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) 3514 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) 3515 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) 3516 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) 3517 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) 3518 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) 3519 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) 3520 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) 3521 3522 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) 3523 /* This bit must always be set on 965G/965GM */ 3524 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) 3525 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) 3526 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) 3527 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) 3528 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) 3529 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) 3530 /* This bit must always be set on 965G */ 3531 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) 3532 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) 3533 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) 3534 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) 3535 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) 3536 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) 3537 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) 3538 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) 3539 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) 3540 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) 3541 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) 3542 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) 3543 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) 3544 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) 3545 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) 3546 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) 3547 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) 3548 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) 3549 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) 3550 3551 #define RENCLK_GATE_D2 _MMIO(0x6208) 3552 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) 3553 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) 3554 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) 3555 3556 #define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */ 3557 #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4) 3558 3559 #define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */ 3560 #define DEUC _MMIO(0x6214) /* CRL only */ 3561 3562 #define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500) 3563 #define FW_CSPWRDWNEN (1 << 15) 3564 3565 #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504) 3566 3567 #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508) 3568 #define CDCLK_FREQ_SHIFT 4 3569 #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT) 3570 #define CZCLK_FREQ_MASK 0xf 3571 3572 #define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C) 3573 #define PFI_CREDIT_63 (9 << 28) /* chv only */ 3574 #define PFI_CREDIT_31 (8 << 28) /* chv only */ 3575 #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */ 3576 #define PFI_CREDIT_RESEND (1 << 27) 3577 #define VGA_FAST_MODE_DISABLE (1 << 14) 3578 3579 #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510) 3580 3581 /* 3582 * Palette regs 3583 */ 3584 #define _PALETTE_A 0xa000 3585 #define _PALETTE_B 0xa800 3586 #define _CHV_PALETTE_C 0xc000 3587 #define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \ 3588 _PICK((pipe), _PALETTE_A, \ 3589 _PALETTE_B, _CHV_PALETTE_C) + \ 3590 (i) * 4) 3591 3592 /* MCH MMIO space */ 3593 3594 /* 3595 * MCHBAR mirror. 3596 * 3597 * This mirrors the MCHBAR MMIO space whose location is determined by 3598 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in 3599 * every way. It is not accessible from the CP register read instructions. 3600 * 3601 * Starting from Haswell, you can't write registers using the MCHBAR mirror, 3602 * just read. 3603 */ 3604 #define MCHBAR_MIRROR_BASE 0x10000 3605 3606 #define MCHBAR_MIRROR_BASE_SNB 0x140000 3607 3608 #define CTG_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x34) 3609 #define ELK_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x48) 3610 #define G4X_STOLEN_RESERVED_ADDR1_MASK (0xFFFF << 16) 3611 #define G4X_STOLEN_RESERVED_ADDR2_MASK (0xFFF << 4) 3612 #define G4X_STOLEN_RESERVED_ENABLE (1 << 0) 3613 3614 /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */ 3615 #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04) 3616 3617 /* 915-945 and GM965 MCH register controlling DRAM channel access */ 3618 #define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200) 3619 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) 3620 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) 3621 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) 3622 #define DCC_ADDRESSING_MODE_MASK (3 << 0) 3623 #define DCC_CHANNEL_XOR_DISABLE (1 << 10) 3624 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9) 3625 #define DCC2 _MMIO(MCHBAR_MIRROR_BASE + 0x204) 3626 #define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20) 3627 3628 /* Pineview MCH register contains DDR3 setting */ 3629 #define CSHRDDR3CTL _MMIO(MCHBAR_MIRROR_BASE + 0x1a8) 3630 #define CSHRDDR3CTL_DDR3 (1 << 2) 3631 3632 /* 965 MCH register controlling DRAM channel configuration */ 3633 #define C0DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x206) 3634 #define C1DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x606) 3635 3636 /* snb MCH registers for reading the DRAM channel configuration */ 3637 #define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004) 3638 #define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008) 3639 #define MAD_DIMM_C2 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C) 3640 #define MAD_DIMM_ECC_MASK (0x3 << 24) 3641 #define MAD_DIMM_ECC_OFF (0x0 << 24) 3642 #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24) 3643 #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24) 3644 #define MAD_DIMM_ECC_ON (0x3 << 24) 3645 #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22) 3646 #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21) 3647 #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */ 3648 #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */ 3649 #define MAD_DIMM_B_DUAL_RANK (0x1 << 18) 3650 #define MAD_DIMM_A_DUAL_RANK (0x1 << 17) 3651 #define MAD_DIMM_A_SELECT (0x1 << 16) 3652 /* DIMM sizes are in multiples of 256mb. */ 3653 #define MAD_DIMM_B_SIZE_SHIFT 8 3654 #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT) 3655 #define MAD_DIMM_A_SIZE_SHIFT 0 3656 #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT) 3657 3658 /* snb MCH registers for priority tuning */ 3659 #define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10) 3660 #define MCH_SSKPD_WM0_MASK 0x3f 3661 #define MCH_SSKPD_WM0_VAL 0xc 3662 3663 #define MCH_SECP_NRG_STTS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x592c) 3664 3665 /* Clocking configuration register */ 3666 #define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00) 3667 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */ 3668 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */ 3669 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */ 3670 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */ 3671 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */ 3672 #define CLKCFG_FSB_1067_ALT (0 << 0) /* hrawclk 266 */ 3673 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */ 3674 /* 3675 * Note that on at least on ELK the below value is reported for both 3676 * 333 and 400 MHz BIOS FSB setting, but given that the gmch datasheet 3677 * lists only 200/266/333 MHz FSB as supported let's decode it as 333 MHz. 3678 */ 3679 #define CLKCFG_FSB_1333_ALT (4 << 0) /* hrawclk 333 */ 3680 #define CLKCFG_FSB_MASK (7 << 0) 3681 #define CLKCFG_MEM_533 (1 << 4) 3682 #define CLKCFG_MEM_667 (2 << 4) 3683 #define CLKCFG_MEM_800 (3 << 4) 3684 #define CLKCFG_MEM_MASK (7 << 4) 3685 3686 #define HPLLVCO _MMIO(MCHBAR_MIRROR_BASE + 0xc38) 3687 #define HPLLVCO_MOBILE _MMIO(MCHBAR_MIRROR_BASE + 0xc0f) 3688 3689 #define TSC1 _MMIO(0x11001) 3690 #define TSE (1 << 0) 3691 #define TR1 _MMIO(0x11006) 3692 #define TSFS _MMIO(0x11020) 3693 #define TSFS_SLOPE_MASK 0x0000ff00 3694 #define TSFS_SLOPE_SHIFT 8 3695 #define TSFS_INTR_MASK 0x000000ff 3696 3697 #define CRSTANDVID _MMIO(0x11100) 3698 #define PXVFREQ(fstart) _MMIO(0x11110 + (fstart) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ 3699 #define PXVFREQ_PX_MASK 0x7f000000 3700 #define PXVFREQ_PX_SHIFT 24 3701 #define VIDFREQ_BASE _MMIO(0x11110) 3702 #define VIDFREQ1 _MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */ 3703 #define VIDFREQ2 _MMIO(0x11114) 3704 #define VIDFREQ3 _MMIO(0x11118) 3705 #define VIDFREQ4 _MMIO(0x1111c) 3706 #define VIDFREQ_P0_MASK 0x1f000000 3707 #define VIDFREQ_P0_SHIFT 24 3708 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000 3709 #define VIDFREQ_P0_CSCLK_SHIFT 20 3710 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000 3711 #define VIDFREQ_P0_CRCLK_SHIFT 16 3712 #define VIDFREQ_P1_MASK 0x00001f00 3713 #define VIDFREQ_P1_SHIFT 8 3714 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0 3715 #define VIDFREQ_P1_CSCLK_SHIFT 4 3716 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f 3717 #define INTTOEXT_BASE_ILK _MMIO(0x11300) 3718 #define INTTOEXT_BASE _MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */ 3719 #define INTTOEXT_MAP3_SHIFT 24 3720 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) 3721 #define INTTOEXT_MAP2_SHIFT 16 3722 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) 3723 #define INTTOEXT_MAP1_SHIFT 8 3724 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) 3725 #define INTTOEXT_MAP0_SHIFT 0 3726 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) 3727 #define MEMSWCTL _MMIO(0x11170) /* Ironlake only */ 3728 #define MEMCTL_CMD_MASK 0xe000 3729 #define MEMCTL_CMD_SHIFT 13 3730 #define MEMCTL_CMD_RCLK_OFF 0 3731 #define MEMCTL_CMD_RCLK_ON 1 3732 #define MEMCTL_CMD_CHFREQ 2 3733 #define MEMCTL_CMD_CHVID 3 3734 #define MEMCTL_CMD_VMMOFF 4 3735 #define MEMCTL_CMD_VMMON 5 3736 #define MEMCTL_CMD_STS (1 << 12) /* write 1 triggers command, clears 3737 when command complete */ 3738 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ 3739 #define MEMCTL_FREQ_SHIFT 8 3740 #define MEMCTL_SFCAVM (1 << 7) 3741 #define MEMCTL_TGT_VID_MASK 0x007f 3742 #define MEMIHYST _MMIO(0x1117c) 3743 #define MEMINTREN _MMIO(0x11180) /* 16 bits */ 3744 #define MEMINT_RSEXIT_EN (1 << 8) 3745 #define MEMINT_CX_SUPR_EN (1 << 7) 3746 #define MEMINT_CONT_BUSY_EN (1 << 6) 3747 #define MEMINT_AVG_BUSY_EN (1 << 5) 3748 #define MEMINT_EVAL_CHG_EN (1 << 4) 3749 #define MEMINT_MON_IDLE_EN (1 << 3) 3750 #define MEMINT_UP_EVAL_EN (1 << 2) 3751 #define MEMINT_DOWN_EVAL_EN (1 << 1) 3752 #define MEMINT_SW_CMD_EN (1 << 0) 3753 #define MEMINTRSTR _MMIO(0x11182) /* 16 bits */ 3754 #define MEM_RSEXIT_MASK 0xc000 3755 #define MEM_RSEXIT_SHIFT 14 3756 #define MEM_CONT_BUSY_MASK 0x3000 3757 #define MEM_CONT_BUSY_SHIFT 12 3758 #define MEM_AVG_BUSY_MASK 0x0c00 3759 #define MEM_AVG_BUSY_SHIFT 10 3760 #define MEM_EVAL_CHG_MASK 0x0300 3761 #define MEM_EVAL_BUSY_SHIFT 8 3762 #define MEM_MON_IDLE_MASK 0x00c0 3763 #define MEM_MON_IDLE_SHIFT 6 3764 #define MEM_UP_EVAL_MASK 0x0030 3765 #define MEM_UP_EVAL_SHIFT 4 3766 #define MEM_DOWN_EVAL_MASK 0x000c 3767 #define MEM_DOWN_EVAL_SHIFT 2 3768 #define MEM_SW_CMD_MASK 0x0003 3769 #define MEM_INT_STEER_GFX 0 3770 #define MEM_INT_STEER_CMR 1 3771 #define MEM_INT_STEER_SMI 2 3772 #define MEM_INT_STEER_SCI 3 3773 #define MEMINTRSTS _MMIO(0x11184) 3774 #define MEMINT_RSEXIT (1 << 7) 3775 #define MEMINT_CONT_BUSY (1 << 6) 3776 #define MEMINT_AVG_BUSY (1 << 5) 3777 #define MEMINT_EVAL_CHG (1 << 4) 3778 #define MEMINT_MON_IDLE (1 << 3) 3779 #define MEMINT_UP_EVAL (1 << 2) 3780 #define MEMINT_DOWN_EVAL (1 << 1) 3781 #define MEMINT_SW_CMD (1 << 0) 3782 #define MEMMODECTL _MMIO(0x11190) 3783 #define MEMMODE_BOOST_EN (1 << 31) 3784 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ 3785 #define MEMMODE_BOOST_FREQ_SHIFT 24 3786 #define MEMMODE_IDLE_MODE_MASK 0x00030000 3787 #define MEMMODE_IDLE_MODE_SHIFT 16 3788 #define MEMMODE_IDLE_MODE_EVAL 0 3789 #define MEMMODE_IDLE_MODE_CONT 1 3790 #define MEMMODE_HWIDLE_EN (1 << 15) 3791 #define MEMMODE_SWMODE_EN (1 << 14) 3792 #define MEMMODE_RCLK_GATE (1 << 13) 3793 #define MEMMODE_HW_UPDATE (1 << 12) 3794 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ 3795 #define MEMMODE_FSTART_SHIFT 8 3796 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ 3797 #define MEMMODE_FMAX_SHIFT 4 3798 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ 3799 #define RCBMAXAVG _MMIO(0x1119c) 3800 #define MEMSWCTL2 _MMIO(0x1119e) /* Cantiga only */ 3801 #define SWMEMCMD_RENDER_OFF (0 << 13) 3802 #define SWMEMCMD_RENDER_ON (1 << 13) 3803 #define SWMEMCMD_SWFREQ (2 << 13) 3804 #define SWMEMCMD_TARVID (3 << 13) 3805 #define SWMEMCMD_VRM_OFF (4 << 13) 3806 #define SWMEMCMD_VRM_ON (5 << 13) 3807 #define CMDSTS (1 << 12) 3808 #define SFCAVM (1 << 11) 3809 #define SWFREQ_MASK 0x0380 /* P0-7 */ 3810 #define SWFREQ_SHIFT 7 3811 #define TARVID_MASK 0x001f 3812 #define MEMSTAT_CTG _MMIO(0x111a0) 3813 #define RCBMINAVG _MMIO(0x111a0) 3814 #define RCUPEI _MMIO(0x111b0) 3815 #define RCDNEI _MMIO(0x111b4) 3816 #define RSTDBYCTL _MMIO(0x111b8) 3817 #define RS1EN (1 << 31) 3818 #define RS2EN (1 << 30) 3819 #define RS3EN (1 << 29) 3820 #define D3RS3EN (1 << 28) /* Display D3 imlies RS3 */ 3821 #define SWPROMORSX (1 << 27) /* RSx promotion timers ignored */ 3822 #define RCWAKERW (1 << 26) /* Resetwarn from PCH causes wakeup */ 3823 #define DPRSLPVREN (1 << 25) /* Fast voltage ramp enable */ 3824 #define GFXTGHYST (1 << 24) /* Hysteresis to allow trunk gating */ 3825 #define RCX_SW_EXIT (1 << 23) /* Leave RSx and prevent re-entry */ 3826 #define RSX_STATUS_MASK (7 << 20) 3827 #define RSX_STATUS_ON (0 << 20) 3828 #define RSX_STATUS_RC1 (1 << 20) 3829 #define RSX_STATUS_RC1E (2 << 20) 3830 #define RSX_STATUS_RS1 (3 << 20) 3831 #define RSX_STATUS_RS2 (4 << 20) /* aka rc6 */ 3832 #define RSX_STATUS_RSVD (5 << 20) /* deep rc6 unsupported on ilk */ 3833 #define RSX_STATUS_RS3 (6 << 20) /* rs3 unsupported on ilk */ 3834 #define RSX_STATUS_RSVD2 (7 << 20) 3835 #define UWRCRSXE (1 << 19) /* wake counter limit prevents rsx */ 3836 #define RSCRP (1 << 18) /* rs requests control on rs1/2 reqs */ 3837 #define JRSC (1 << 17) /* rsx coupled to cpu c-state */ 3838 #define RS2INC0 (1 << 16) /* allow rs2 in cpu c0 */ 3839 #define RS1CONTSAV_MASK (3 << 14) 3840 #define RS1CONTSAV_NO_RS1 (0 << 14) /* rs1 doesn't save/restore context */ 3841 #define RS1CONTSAV_RSVD (1 << 14) 3842 #define RS1CONTSAV_SAVE_RS1 (2 << 14) /* rs1 saves context */ 3843 #define RS1CONTSAV_FULL_RS1 (3 << 14) /* rs1 saves and restores context */ 3844 #define NORMSLEXLAT_MASK (3 << 12) 3845 #define SLOW_RS123 (0 << 12) 3846 #define SLOW_RS23 (1 << 12) 3847 #define SLOW_RS3 (2 << 12) 3848 #define NORMAL_RS123 (3 << 12) 3849 #define RCMODE_TIMEOUT (1 << 11) /* 0 is eval interval method */ 3850 #define IMPROMOEN (1 << 10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */ 3851 #define RCENTSYNC (1 << 9) /* rs coupled to cpu c-state (3/6/7) */ 3852 #define STATELOCK (1 << 7) /* locked to rs_cstate if 0 */ 3853 #define RS_CSTATE_MASK (3 << 4) 3854 #define RS_CSTATE_C367_RS1 (0 << 4) 3855 #define RS_CSTATE_C36_RS1_C7_RS2 (1 << 4) 3856 #define RS_CSTATE_RSVD (2 << 4) 3857 #define RS_CSTATE_C367_RS2 (3 << 4) 3858 #define REDSAVES (1 << 3) /* no context save if was idle during rs0 */ 3859 #define REDRESTORES (1 << 2) /* no restore if was idle during rs0 */ 3860 #define VIDCTL _MMIO(0x111c0) 3861 #define VIDSTS _MMIO(0x111c8) 3862 #define VIDSTART _MMIO(0x111cc) /* 8 bits */ 3863 #define MEMSTAT_ILK _MMIO(0x111f8) 3864 #define MEMSTAT_VID_MASK 0x7f00 3865 #define MEMSTAT_VID_SHIFT 8 3866 #define MEMSTAT_PSTATE_MASK 0x00f8 3867 #define MEMSTAT_PSTATE_SHIFT 3 3868 #define MEMSTAT_MON_ACTV (1 << 2) 3869 #define MEMSTAT_SRC_CTL_MASK 0x0003 3870 #define MEMSTAT_SRC_CTL_CORE 0 3871 #define MEMSTAT_SRC_CTL_TRB 1 3872 #define MEMSTAT_SRC_CTL_THM 2 3873 #define MEMSTAT_SRC_CTL_STDBY 3 3874 #define RCPREVBSYTUPAVG _MMIO(0x113b8) 3875 #define RCPREVBSYTDNAVG _MMIO(0x113bc) 3876 #define PMMISC _MMIO(0x11214) 3877 #define MCPPCE_EN (1 << 0) /* enable PM_MSG from PCH->MPC */ 3878 #define SDEW _MMIO(0x1124c) 3879 #define CSIEW0 _MMIO(0x11250) 3880 #define CSIEW1 _MMIO(0x11254) 3881 #define CSIEW2 _MMIO(0x11258) 3882 #define PEW(i) _MMIO(0x1125c + (i) * 4) /* 5 registers */ 3883 #define DEW(i) _MMIO(0x11270 + (i) * 4) /* 3 registers */ 3884 #define MCHAFE _MMIO(0x112c0) 3885 #define CSIEC _MMIO(0x112e0) 3886 #define DMIEC _MMIO(0x112e4) 3887 #define DDREC _MMIO(0x112e8) 3888 #define PEG0EC _MMIO(0x112ec) 3889 #define PEG1EC _MMIO(0x112f0) 3890 #define GFXEC _MMIO(0x112f4) 3891 #define RPPREVBSYTUPAVG _MMIO(0x113b8) 3892 #define RPPREVBSYTDNAVG _MMIO(0x113bc) 3893 #define ECR _MMIO(0x11600) 3894 #define ECR_GPFE (1 << 31) 3895 #define ECR_IMONE (1 << 30) 3896 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */ 3897 #define OGW0 _MMIO(0x11608) 3898 #define OGW1 _MMIO(0x1160c) 3899 #define EG0 _MMIO(0x11610) 3900 #define EG1 _MMIO(0x11614) 3901 #define EG2 _MMIO(0x11618) 3902 #define EG3 _MMIO(0x1161c) 3903 #define EG4 _MMIO(0x11620) 3904 #define EG5 _MMIO(0x11624) 3905 #define EG6 _MMIO(0x11628) 3906 #define EG7 _MMIO(0x1162c) 3907 #define PXW(i) _MMIO(0x11664 + (i) * 4) /* 4 registers */ 3908 #define PXWL(i) _MMIO(0x11680 + (i) * 8) /* 8 registers */ 3909 #define LCFUSE02 _MMIO(0x116c0) 3910 #define LCFUSE_HIV_MASK 0x000000ff 3911 #define CSIPLL0 _MMIO(0x12c10) 3912 #define DDRMPLL1 _MMIO(0X12c20) 3913 #define PEG_BAND_GAP_DATA _MMIO(0x14d68) 3914 3915 #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c) 3916 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7 3917 3918 #define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948) 3919 #define BXT_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070) 3920 #define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994) 3921 #define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998) 3922 #define BXT_RP_STATE_CAP _MMIO(0x138170) 3923 3924 /* 3925 * Make these a multiple of magic 25 to avoid SNB (eg. Dell XPS 3926 * 8300) freezing up around GPU hangs. Looks as if even 3927 * scheduling/timer interrupts start misbehaving if the RPS 3928 * EI/thresholds are "bad", leading to a very sluggish or even 3929 * frozen machine. 3930 */ 3931 #define INTERVAL_1_28_US(us) roundup(((us) * 100) >> 7, 25) 3932 #define INTERVAL_1_33_US(us) (((us) * 3) >> 2) 3933 #define INTERVAL_0_833_US(us) (((us) * 6) / 5) 3934 #define GT_INTERVAL_FROM_US(dev_priv, us) (INTEL_GEN(dev_priv) >= 9 ? \ 3935 (IS_GEN9_LP(dev_priv) ? \ 3936 INTERVAL_0_833_US(us) : \ 3937 INTERVAL_1_33_US(us)) : \ 3938 INTERVAL_1_28_US(us)) 3939 3940 #define INTERVAL_1_28_TO_US(interval) (((interval) << 7) / 100) 3941 #define INTERVAL_1_33_TO_US(interval) (((interval) << 2) / 3) 3942 #define INTERVAL_0_833_TO_US(interval) (((interval) * 5) / 6) 3943 #define GT_PM_INTERVAL_TO_US(dev_priv, interval) (INTEL_GEN(dev_priv) >= 9 ? \ 3944 (IS_GEN9_LP(dev_priv) ? \ 3945 INTERVAL_0_833_TO_US(interval) : \ 3946 INTERVAL_1_33_TO_US(interval)) : \ 3947 INTERVAL_1_28_TO_US(interval)) 3948 3949 /* 3950 * Logical Context regs 3951 */ 3952 #define CCID(base) _MMIO((base) + 0x180) 3953 #define CCID_EN BIT(0) 3954 #define CCID_EXTENDED_STATE_RESTORE BIT(2) 3955 #define CCID_EXTENDED_STATE_SAVE BIT(3) 3956 /* 3957 * Notes on SNB/IVB/VLV context size: 3958 * - Power context is saved elsewhere (LLC or stolen) 3959 * - Ring/execlist context is saved on SNB, not on IVB 3960 * - Extended context size already includes render context size 3961 * - We always need to follow the extended context size. 3962 * SNB BSpec has comments indicating that we should use the 3963 * render context size instead if execlists are disabled, but 3964 * based on empirical testing that's just nonsense. 3965 * - Pipelined/VF state is saved on SNB/IVB respectively 3966 * - GT1 size just indicates how much of render context 3967 * doesn't need saving on GT1 3968 */ 3969 #define CXT_SIZE _MMIO(0x21a0) 3970 #define GEN6_CXT_POWER_SIZE(cxt_reg) (((cxt_reg) >> 24) & 0x3f) 3971 #define GEN6_CXT_RING_SIZE(cxt_reg) (((cxt_reg) >> 18) & 0x3f) 3972 #define GEN6_CXT_RENDER_SIZE(cxt_reg) (((cxt_reg) >> 12) & 0x3f) 3973 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) (((cxt_reg) >> 6) & 0x3f) 3974 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) (((cxt_reg) >> 0) & 0x3f) 3975 #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \ 3976 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \ 3977 GEN6_CXT_PIPELINE_SIZE(cxt_reg)) 3978 #define GEN7_CXT_SIZE _MMIO(0x21a8) 3979 #define GEN7_CXT_POWER_SIZE(ctx_reg) (((ctx_reg) >> 25) & 0x7f) 3980 #define GEN7_CXT_RING_SIZE(ctx_reg) (((ctx_reg) >> 22) & 0x7) 3981 #define GEN7_CXT_RENDER_SIZE(ctx_reg) (((ctx_reg) >> 16) & 0x3f) 3982 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) (((ctx_reg) >> 9) & 0x7f) 3983 #define GEN7_CXT_GT1_SIZE(ctx_reg) (((ctx_reg) >> 6) & 0x7) 3984 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) (((ctx_reg) >> 0) & 0x3f) 3985 #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \ 3986 GEN7_CXT_VFSTATE_SIZE(ctx_reg)) 3987 3988 enum { 3989 INTEL_ADVANCED_CONTEXT = 0, 3990 INTEL_LEGACY_32B_CONTEXT, 3991 INTEL_ADVANCED_AD_CONTEXT, 3992 INTEL_LEGACY_64B_CONTEXT 3993 }; 3994 3995 enum { 3996 FAULT_AND_HANG = 0, 3997 FAULT_AND_HALT, /* Debug only */ 3998 FAULT_AND_STREAM, 3999 FAULT_AND_CONTINUE /* Unsupported */ 4000 }; 4001 4002 #define GEN8_CTX_VALID (1 << 0) 4003 #define GEN8_CTX_FORCE_PD_RESTORE (1 << 1) 4004 #define GEN8_CTX_FORCE_RESTORE (1 << 2) 4005 #define GEN8_CTX_L3LLC_COHERENT (1 << 5) 4006 #define GEN8_CTX_PRIVILEGE (1 << 8) 4007 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3 4008 4009 #define GEN8_CTX_ID_SHIFT 32 4010 #define GEN8_CTX_ID_WIDTH 21 4011 #define GEN11_SW_CTX_ID_SHIFT 37 4012 #define GEN11_SW_CTX_ID_WIDTH 11 4013 #define GEN11_ENGINE_CLASS_SHIFT 61 4014 #define GEN11_ENGINE_CLASS_WIDTH 3 4015 #define GEN11_ENGINE_INSTANCE_SHIFT 48 4016 #define GEN11_ENGINE_INSTANCE_WIDTH 6 4017 4018 #define CHV_CLK_CTL1 _MMIO(0x101100) 4019 #define VLV_CLK_CTL2 _MMIO(0x101104) 4020 #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28 4021 4022 /* 4023 * Overlay regs 4024 */ 4025 4026 #define OVADD _MMIO(0x30000) 4027 #define DOVSTA _MMIO(0x30008) 4028 #define OC_BUF (0x3 << 20) 4029 #define OGAMC5 _MMIO(0x30010) 4030 #define OGAMC4 _MMIO(0x30014) 4031 #define OGAMC3 _MMIO(0x30018) 4032 #define OGAMC2 _MMIO(0x3001c) 4033 #define OGAMC1 _MMIO(0x30020) 4034 #define OGAMC0 _MMIO(0x30024) 4035 4036 /* 4037 * GEN9 clock gating regs 4038 */ 4039 #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530) 4040 #define DARBF_GATING_DIS (1 << 27) 4041 #define PWM2_GATING_DIS (1 << 14) 4042 #define PWM1_GATING_DIS (1 << 13) 4043 4044 #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C) 4045 #define BXT_GMBUS_GATING_DIS (1 << 14) 4046 4047 #define _CLKGATE_DIS_PSL_A 0x46520 4048 #define _CLKGATE_DIS_PSL_B 0x46524 4049 #define _CLKGATE_DIS_PSL_C 0x46528 4050 #define DUPS1_GATING_DIS (1 << 15) 4051 #define DUPS2_GATING_DIS (1 << 19) 4052 #define DUPS3_GATING_DIS (1 << 23) 4053 #define DPF_GATING_DIS (1 << 10) 4054 #define DPF_RAM_GATING_DIS (1 << 9) 4055 #define DPFR_GATING_DIS (1 << 8) 4056 4057 #define CLKGATE_DIS_PSL(pipe) \ 4058 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B) 4059 4060 /* 4061 * GEN10 clock gating regs 4062 */ 4063 #define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4) 4064 #define SARBUNIT_CLKGATE_DIS (1 << 5) 4065 #define RCCUNIT_CLKGATE_DIS (1 << 7) 4066 #define MSCUNIT_CLKGATE_DIS (1 << 10) 4067 4068 #define SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524) 4069 #define GWUNIT_CLKGATE_DIS (1 << 16) 4070 4071 #define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434) 4072 #define VFUNIT_CLKGATE_DIS (1 << 20) 4073 4074 #define INF_UNIT_LEVEL_CLKGATE _MMIO(0x9560) 4075 #define CGPSF_CLKGATE_DIS (1 << 3) 4076 4077 /* 4078 * Display engine regs 4079 */ 4080 4081 /* Pipe A CRC regs */ 4082 #define _PIPE_CRC_CTL_A 0x60050 4083 #define PIPE_CRC_ENABLE (1 << 31) 4084 /* skl+ source selection */ 4085 #define PIPE_CRC_SOURCE_PLANE_1_SKL (0 << 28) 4086 #define PIPE_CRC_SOURCE_PLANE_2_SKL (2 << 28) 4087 #define PIPE_CRC_SOURCE_DMUX_SKL (4 << 28) 4088 #define PIPE_CRC_SOURCE_PLANE_3_SKL (6 << 28) 4089 #define PIPE_CRC_SOURCE_PLANE_4_SKL (7 << 28) 4090 #define PIPE_CRC_SOURCE_PLANE_5_SKL (5 << 28) 4091 #define PIPE_CRC_SOURCE_PLANE_6_SKL (3 << 28) 4092 #define PIPE_CRC_SOURCE_PLANE_7_SKL (1 << 28) 4093 /* ivb+ source selection */ 4094 #define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29) 4095 #define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29) 4096 #define PIPE_CRC_SOURCE_PF_IVB (2 << 29) 4097 /* ilk+ source selection */ 4098 #define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28) 4099 #define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28) 4100 #define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28) 4101 /* embedded DP port on the north display block, reserved on ivb */ 4102 #define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28) 4103 #define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */ 4104 /* vlv source selection */ 4105 #define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27) 4106 #define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27) 4107 #define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27) 4108 /* with DP port the pipe source is invalid */ 4109 #define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27) 4110 #define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27) 4111 #define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27) 4112 /* gen3+ source selection */ 4113 #define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28) 4114 #define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28) 4115 #define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28) 4116 /* with DP/TV port the pipe source is invalid */ 4117 #define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28) 4118 #define PIPE_CRC_SOURCE_TV_PRE (4 << 28) 4119 #define PIPE_CRC_SOURCE_TV_POST (5 << 28) 4120 #define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28) 4121 #define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28) 4122 /* gen2 doesn't have source selection bits */ 4123 #define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30) 4124 4125 #define _PIPE_CRC_RES_1_A_IVB 0x60064 4126 #define _PIPE_CRC_RES_2_A_IVB 0x60068 4127 #define _PIPE_CRC_RES_3_A_IVB 0x6006c 4128 #define _PIPE_CRC_RES_4_A_IVB 0x60070 4129 #define _PIPE_CRC_RES_5_A_IVB 0x60074 4130 4131 #define _PIPE_CRC_RES_RED_A 0x60060 4132 #define _PIPE_CRC_RES_GREEN_A 0x60064 4133 #define _PIPE_CRC_RES_BLUE_A 0x60068 4134 #define _PIPE_CRC_RES_RES1_A_I915 0x6006c 4135 #define _PIPE_CRC_RES_RES2_A_G4X 0x60080 4136 4137 /* Pipe B CRC regs */ 4138 #define _PIPE_CRC_RES_1_B_IVB 0x61064 4139 #define _PIPE_CRC_RES_2_B_IVB 0x61068 4140 #define _PIPE_CRC_RES_3_B_IVB 0x6106c 4141 #define _PIPE_CRC_RES_4_B_IVB 0x61070 4142 #define _PIPE_CRC_RES_5_B_IVB 0x61074 4143 4144 #define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A) 4145 #define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB) 4146 #define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB) 4147 #define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB) 4148 #define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB) 4149 #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB) 4150 4151 #define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A) 4152 #define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A) 4153 #define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A) 4154 #define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915) 4155 #define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X) 4156 4157 /* Pipe A timing regs */ 4158 #define _HTOTAL_A 0x60000 4159 #define _HBLANK_A 0x60004 4160 #define _HSYNC_A 0x60008 4161 #define _VTOTAL_A 0x6000c 4162 #define _VBLANK_A 0x60010 4163 #define _VSYNC_A 0x60014 4164 #define _PIPEASRC 0x6001c 4165 #define _BCLRPAT_A 0x60020 4166 #define _VSYNCSHIFT_A 0x60028 4167 #define _PIPE_MULT_A 0x6002c 4168 4169 /* Pipe B timing regs */ 4170 #define _HTOTAL_B 0x61000 4171 #define _HBLANK_B 0x61004 4172 #define _HSYNC_B 0x61008 4173 #define _VTOTAL_B 0x6100c 4174 #define _VBLANK_B 0x61010 4175 #define _VSYNC_B 0x61014 4176 #define _PIPEBSRC 0x6101c 4177 #define _BCLRPAT_B 0x61020 4178 #define _VSYNCSHIFT_B 0x61028 4179 #define _PIPE_MULT_B 0x6102c 4180 4181 /* DSI 0 timing regs */ 4182 #define _HTOTAL_DSI0 0x6b000 4183 #define _HSYNC_DSI0 0x6b008 4184 #define _VTOTAL_DSI0 0x6b00c 4185 #define _VSYNC_DSI0 0x6b014 4186 #define _VSYNCSHIFT_DSI0 0x6b028 4187 4188 /* DSI 1 timing regs */ 4189 #define _HTOTAL_DSI1 0x6b800 4190 #define _HSYNC_DSI1 0x6b808 4191 #define _VTOTAL_DSI1 0x6b80c 4192 #define _VSYNC_DSI1 0x6b814 4193 #define _VSYNCSHIFT_DSI1 0x6b828 4194 4195 #define TRANSCODER_A_OFFSET 0x60000 4196 #define TRANSCODER_B_OFFSET 0x61000 4197 #define TRANSCODER_C_OFFSET 0x62000 4198 #define CHV_TRANSCODER_C_OFFSET 0x63000 4199 #define TRANSCODER_EDP_OFFSET 0x6f000 4200 #define TRANSCODER_DSI0_OFFSET 0x6b000 4201 #define TRANSCODER_DSI1_OFFSET 0x6b800 4202 4203 #define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A) 4204 #define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A) 4205 #define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A) 4206 #define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A) 4207 #define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A) 4208 #define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A) 4209 #define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A) 4210 #define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A) 4211 #define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC) 4212 #define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A) 4213 4214 /* HSW+ eDP PSR registers */ 4215 #define HSW_EDP_PSR_BASE 0x64800 4216 #define BDW_EDP_PSR_BASE 0x6f800 4217 #define EDP_PSR_CTL _MMIO(dev_priv->psr_mmio_base + 0) 4218 #define EDP_PSR_ENABLE (1 << 31) 4219 #define BDW_PSR_SINGLE_FRAME (1 << 30) 4220 #define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1 << 29) /* SW can't modify */ 4221 #define EDP_PSR_LINK_STANDBY (1 << 27) 4222 #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3 << 25) 4223 #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0 << 25) 4224 #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1 << 25) 4225 #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2 << 25) 4226 #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3 << 25) 4227 #define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20 4228 #define EDP_PSR_SKIP_AUX_EXIT (1 << 12) 4229 #define EDP_PSR_TP1_TP2_SEL (0 << 11) 4230 #define EDP_PSR_TP1_TP3_SEL (1 << 11) 4231 #define EDP_PSR_CRC_ENABLE (1 << 10) /* BDW+ */ 4232 #define EDP_PSR_TP2_TP3_TIME_500us (0 << 8) 4233 #define EDP_PSR_TP2_TP3_TIME_100us (1 << 8) 4234 #define EDP_PSR_TP2_TP3_TIME_2500us (2 << 8) 4235 #define EDP_PSR_TP2_TP3_TIME_0us (3 << 8) 4236 #define EDP_PSR_TP4_TIME_0US (3 << 6) /* ICL+ */ 4237 #define EDP_PSR_TP1_TIME_500us (0 << 4) 4238 #define EDP_PSR_TP1_TIME_100us (1 << 4) 4239 #define EDP_PSR_TP1_TIME_2500us (2 << 4) 4240 #define EDP_PSR_TP1_TIME_0us (3 << 4) 4241 #define EDP_PSR_IDLE_FRAME_SHIFT 0 4242 4243 /* Bspec claims those aren't shifted but stay at 0x64800 */ 4244 #define EDP_PSR_IMR _MMIO(0x64834) 4245 #define EDP_PSR_IIR _MMIO(0x64838) 4246 #define EDP_PSR_ERROR(shift) (1 << ((shift) + 2)) 4247 #define EDP_PSR_POST_EXIT(shift) (1 << ((shift) + 1)) 4248 #define EDP_PSR_PRE_ENTRY(shift) (1 << (shift)) 4249 #define EDP_PSR_TRANSCODER_C_SHIFT 24 4250 #define EDP_PSR_TRANSCODER_B_SHIFT 16 4251 #define EDP_PSR_TRANSCODER_A_SHIFT 8 4252 #define EDP_PSR_TRANSCODER_EDP_SHIFT 0 4253 4254 #define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr_mmio_base + 0x10) 4255 #define EDP_PSR_AUX_CTL_TIME_OUT_MASK (3 << 26) 4256 #define EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK (0x1f << 20) 4257 #define EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK (0xf << 16) 4258 #define EDP_PSR_AUX_CTL_ERROR_INTERRUPT (1 << 11) 4259 #define EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK (0x7ff) 4260 4261 #define EDP_PSR_AUX_DATA(i) _MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */ 4262 4263 #define EDP_PSR_STATUS _MMIO(dev_priv->psr_mmio_base + 0x40) 4264 #define EDP_PSR_STATUS_STATE_MASK (7 << 29) 4265 #define EDP_PSR_STATUS_STATE_SHIFT 29 4266 #define EDP_PSR_STATUS_STATE_IDLE (0 << 29) 4267 #define EDP_PSR_STATUS_STATE_SRDONACK (1 << 29) 4268 #define EDP_PSR_STATUS_STATE_SRDENT (2 << 29) 4269 #define EDP_PSR_STATUS_STATE_BUFOFF (3 << 29) 4270 #define EDP_PSR_STATUS_STATE_BUFON (4 << 29) 4271 #define EDP_PSR_STATUS_STATE_AUXACK (5 << 29) 4272 #define EDP_PSR_STATUS_STATE_SRDOFFACK (6 << 29) 4273 #define EDP_PSR_STATUS_LINK_MASK (3 << 26) 4274 #define EDP_PSR_STATUS_LINK_FULL_OFF (0 << 26) 4275 #define EDP_PSR_STATUS_LINK_FULL_ON (1 << 26) 4276 #define EDP_PSR_STATUS_LINK_STANDBY (2 << 26) 4277 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20 4278 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f 4279 #define EDP_PSR_STATUS_COUNT_SHIFT 16 4280 #define EDP_PSR_STATUS_COUNT_MASK 0xf 4281 #define EDP_PSR_STATUS_AUX_ERROR (1 << 15) 4282 #define EDP_PSR_STATUS_AUX_SENDING (1 << 12) 4283 #define EDP_PSR_STATUS_SENDING_IDLE (1 << 9) 4284 #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1 << 8) 4285 #define EDP_PSR_STATUS_SENDING_TP1 (1 << 4) 4286 #define EDP_PSR_STATUS_IDLE_MASK 0xf 4287 4288 #define EDP_PSR_PERF_CNT _MMIO(dev_priv->psr_mmio_base + 0x44) 4289 #define EDP_PSR_PERF_CNT_MASK 0xffffff 4290 4291 #define EDP_PSR_DEBUG _MMIO(dev_priv->psr_mmio_base + 0x60) /* PSR_MASK on SKL+ */ 4292 #define EDP_PSR_DEBUG_MASK_MAX_SLEEP (1 << 28) 4293 #define EDP_PSR_DEBUG_MASK_LPSP (1 << 27) 4294 #define EDP_PSR_DEBUG_MASK_MEMUP (1 << 26) 4295 #define EDP_PSR_DEBUG_MASK_HPD (1 << 25) 4296 #define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) /* Reserved in ICL+ */ 4297 #define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */ 4298 4299 #define EDP_PSR2_CTL _MMIO(0x6f900) 4300 #define EDP_PSR2_ENABLE (1 << 31) 4301 #define EDP_SU_TRACK_ENABLE (1 << 30) 4302 #define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */ 4303 #define EDP_Y_COORDINATE_ENABLE (1 << 25) /* GLK and CNL+ */ 4304 #define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20) 4305 #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20) 4306 #define EDP_PSR2_TP2_TIME_500us (0 << 8) 4307 #define EDP_PSR2_TP2_TIME_100us (1 << 8) 4308 #define EDP_PSR2_TP2_TIME_2500us (2 << 8) 4309 #define EDP_PSR2_TP2_TIME_50us (3 << 8) 4310 #define EDP_PSR2_TP2_TIME_MASK (3 << 8) 4311 #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 4312 #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4) 4313 #define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4) 4314 #define EDP_PSR2_IDLE_FRAME_MASK 0xf 4315 #define EDP_PSR2_IDLE_FRAME_SHIFT 0 4316 4317 #define _PSR_EVENT_TRANS_A 0x60848 4318 #define _PSR_EVENT_TRANS_B 0x61848 4319 #define _PSR_EVENT_TRANS_C 0x62848 4320 #define _PSR_EVENT_TRANS_D 0x63848 4321 #define _PSR_EVENT_TRANS_EDP 0x6F848 4322 #define PSR_EVENT(trans) _MMIO_TRANS2(trans, _PSR_EVENT_TRANS_A) 4323 #define PSR_EVENT_PSR2_WD_TIMER_EXPIRE (1 << 17) 4324 #define PSR_EVENT_PSR2_DISABLED (1 << 16) 4325 #define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN (1 << 15) 4326 #define PSR_EVENT_SU_CRC_FIFO_UNDERRUN (1 << 14) 4327 #define PSR_EVENT_GRAPHICS_RESET (1 << 12) 4328 #define PSR_EVENT_PCH_INTERRUPT (1 << 11) 4329 #define PSR_EVENT_MEMORY_UP (1 << 10) 4330 #define PSR_EVENT_FRONT_BUFFER_MODIFY (1 << 9) 4331 #define PSR_EVENT_WD_TIMER_EXPIRE (1 << 8) 4332 #define PSR_EVENT_PIPE_REGISTERS_UPDATE (1 << 6) 4333 #define PSR_EVENT_REGISTER_UPDATE (1 << 5) /* Reserved in ICL+ */ 4334 #define PSR_EVENT_HDCP_ENABLE (1 << 4) 4335 #define PSR_EVENT_KVMR_SESSION_ENABLE (1 << 3) 4336 #define PSR_EVENT_VBI_ENABLE (1 << 2) 4337 #define PSR_EVENT_LPSP_MODE_EXIT (1 << 1) 4338 #define PSR_EVENT_PSR_DISABLE (1 << 0) 4339 4340 #define EDP_PSR2_STATUS _MMIO(0x6f940) 4341 #define EDP_PSR2_STATUS_STATE_MASK (0xf << 28) 4342 #define EDP_PSR2_STATUS_STATE_SHIFT 28 4343 4344 #define _PSR2_SU_STATUS_0 0x6F914 4345 #define _PSR2_SU_STATUS_1 0x6F918 4346 #define _PSR2_SU_STATUS_2 0x6F91C 4347 #define _PSR2_SU_STATUS(index) _MMIO(_PICK_EVEN((index), _PSR2_SU_STATUS_0, _PSR2_SU_STATUS_1)) 4348 #define PSR2_SU_STATUS(frame) (_PSR2_SU_STATUS((frame) / 3)) 4349 #define PSR2_SU_STATUS_SHIFT(frame) (((frame) % 3) * 10) 4350 #define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame)) 4351 #define PSR2_SU_STATUS_FRAMES 8 4352 4353 /* VGA port control */ 4354 #define ADPA _MMIO(0x61100) 4355 #define PCH_ADPA _MMIO(0xe1100) 4356 #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100) 4357 4358 #define ADPA_DAC_ENABLE (1 << 31) 4359 #define ADPA_DAC_DISABLE 0 4360 #define ADPA_PIPE_SEL_SHIFT 30 4361 #define ADPA_PIPE_SEL_MASK (1 << 30) 4362 #define ADPA_PIPE_SEL(pipe) ((pipe) << 30) 4363 #define ADPA_PIPE_SEL_SHIFT_CPT 29 4364 #define ADPA_PIPE_SEL_MASK_CPT (3 << 29) 4365 #define ADPA_PIPE_SEL_CPT(pipe) ((pipe) << 29) 4366 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ 4367 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0 << 24) 4368 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3 << 24) 4369 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3 << 24) 4370 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2 << 24) 4371 #define ADPA_CRT_HOTPLUG_ENABLE (1 << 23) 4372 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0 << 22) 4373 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1 << 22) 4374 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0 << 21) 4375 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1 << 21) 4376 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0 << 20) 4377 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1 << 20) 4378 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0 << 18) 4379 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1 << 18) 4380 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2 << 18) 4381 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3 << 18) 4382 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0 << 17) 4383 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1 << 17) 4384 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1 << 16) 4385 #define ADPA_USE_VGA_HVPOLARITY (1 << 15) 4386 #define ADPA_SETS_HVPOLARITY 0 4387 #define ADPA_VSYNC_CNTL_DISABLE (1 << 10) 4388 #define ADPA_VSYNC_CNTL_ENABLE 0 4389 #define ADPA_HSYNC_CNTL_DISABLE (1 << 11) 4390 #define ADPA_HSYNC_CNTL_ENABLE 0 4391 #define ADPA_VSYNC_ACTIVE_HIGH (1 << 4) 4392 #define ADPA_VSYNC_ACTIVE_LOW 0 4393 #define ADPA_HSYNC_ACTIVE_HIGH (1 << 3) 4394 #define ADPA_HSYNC_ACTIVE_LOW 0 4395 #define ADPA_DPMS_MASK (~(3 << 10)) 4396 #define ADPA_DPMS_ON (0 << 10) 4397 #define ADPA_DPMS_SUSPEND (1 << 10) 4398 #define ADPA_DPMS_STANDBY (2 << 10) 4399 #define ADPA_DPMS_OFF (3 << 10) 4400 4401 4402 /* Hotplug control (945+ only) */ 4403 #define PORT_HOTPLUG_EN _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110) 4404 #define PORTB_HOTPLUG_INT_EN (1 << 29) 4405 #define PORTC_HOTPLUG_INT_EN (1 << 28) 4406 #define PORTD_HOTPLUG_INT_EN (1 << 27) 4407 #define SDVOB_HOTPLUG_INT_EN (1 << 26) 4408 #define SDVOC_HOTPLUG_INT_EN (1 << 25) 4409 #define TV_HOTPLUG_INT_EN (1 << 18) 4410 #define CRT_HOTPLUG_INT_EN (1 << 9) 4411 #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \ 4412 PORTC_HOTPLUG_INT_EN | \ 4413 PORTD_HOTPLUG_INT_EN | \ 4414 SDVOC_HOTPLUG_INT_EN | \ 4415 SDVOB_HOTPLUG_INT_EN | \ 4416 CRT_HOTPLUG_INT_EN) 4417 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 4418 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) 4419 /* must use period 64 on GM45 according to docs */ 4420 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) 4421 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) 4422 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) 4423 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) 4424 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) 4425 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) 4426 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) 4427 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) 4428 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) 4429 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) 4430 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) 4431 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 4432 4433 #define PORT_HOTPLUG_STAT _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114) 4434 /* 4435 * HDMI/DP bits are g4x+ 4436 * 4437 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused. 4438 * Please check the detailed lore in the commit message for for experimental 4439 * evidence. 4440 */ 4441 /* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */ 4442 #define PORTD_HOTPLUG_LIVE_STATUS_GM45 (1 << 29) 4443 #define PORTC_HOTPLUG_LIVE_STATUS_GM45 (1 << 28) 4444 #define PORTB_HOTPLUG_LIVE_STATUS_GM45 (1 << 27) 4445 /* G4X/VLV/CHV DP/HDMI bits again match Bspec */ 4446 #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27) 4447 #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28) 4448 #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29) 4449 #define PORTD_HOTPLUG_INT_STATUS (3 << 21) 4450 #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21) 4451 #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21) 4452 #define PORTC_HOTPLUG_INT_STATUS (3 << 19) 4453 #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19) 4454 #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19) 4455 #define PORTB_HOTPLUG_INT_STATUS (3 << 17) 4456 #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17) 4457 #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17) 4458 /* CRT/TV common between gen3+ */ 4459 #define CRT_HOTPLUG_INT_STATUS (1 << 11) 4460 #define TV_HOTPLUG_INT_STATUS (1 << 10) 4461 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 4462 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 4463 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 4464 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 4465 #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6) 4466 #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5) 4467 #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4) 4468 #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4) 4469 4470 /* SDVO is different across gen3/4 */ 4471 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) 4472 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) 4473 /* 4474 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm, 4475 * since reality corrobates that they're the same as on gen3. But keep these 4476 * bits here (and the comment!) to help any other lost wanderers back onto the 4477 * right tracks. 4478 */ 4479 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4) 4480 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) 4481 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) 4482 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) 4483 #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \ 4484 SDVOB_HOTPLUG_INT_STATUS_G4X | \ 4485 SDVOC_HOTPLUG_INT_STATUS_G4X | \ 4486 PORTB_HOTPLUG_INT_STATUS | \ 4487 PORTC_HOTPLUG_INT_STATUS | \ 4488 PORTD_HOTPLUG_INT_STATUS) 4489 4490 #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \ 4491 SDVOB_HOTPLUG_INT_STATUS_I915 | \ 4492 SDVOC_HOTPLUG_INT_STATUS_I915 | \ 4493 PORTB_HOTPLUG_INT_STATUS | \ 4494 PORTC_HOTPLUG_INT_STATUS | \ 4495 PORTD_HOTPLUG_INT_STATUS) 4496 4497 /* SDVO and HDMI port control. 4498 * The same register may be used for SDVO or HDMI */ 4499 #define _GEN3_SDVOB 0x61140 4500 #define _GEN3_SDVOC 0x61160 4501 #define GEN3_SDVOB _MMIO(_GEN3_SDVOB) 4502 #define GEN3_SDVOC _MMIO(_GEN3_SDVOC) 4503 #define GEN4_HDMIB GEN3_SDVOB 4504 #define GEN4_HDMIC GEN3_SDVOC 4505 #define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140) 4506 #define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160) 4507 #define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C) 4508 #define PCH_SDVOB _MMIO(0xe1140) 4509 #define PCH_HDMIB PCH_SDVOB 4510 #define PCH_HDMIC _MMIO(0xe1150) 4511 #define PCH_HDMID _MMIO(0xe1160) 4512 4513 #define PORT_DFT_I9XX _MMIO(0x61150) 4514 #define DC_BALANCE_RESET (1 << 25) 4515 #define PORT_DFT2_G4X _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154) 4516 #define DC_BALANCE_RESET_VLV (1 << 31) 4517 #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0)) 4518 #define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */ 4519 #define PIPE_B_SCRAMBLE_RESET (1 << 1) 4520 #define PIPE_A_SCRAMBLE_RESET (1 << 0) 4521 4522 /* Gen 3 SDVO bits: */ 4523 #define SDVO_ENABLE (1 << 31) 4524 #define SDVO_PIPE_SEL_SHIFT 30 4525 #define SDVO_PIPE_SEL_MASK (1 << 30) 4526 #define SDVO_PIPE_SEL(pipe) ((pipe) << 30) 4527 #define SDVO_STALL_SELECT (1 << 29) 4528 #define SDVO_INTERRUPT_ENABLE (1 << 26) 4529 /* 4530 * 915G/GM SDVO pixel multiplier. 4531 * Programmed value is multiplier - 1, up to 5x. 4532 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 4533 */ 4534 #define SDVO_PORT_MULTIPLY_MASK (7 << 23) 4535 #define SDVO_PORT_MULTIPLY_SHIFT 23 4536 #define SDVO_PHASE_SELECT_MASK (15 << 19) 4537 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 4538 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 4539 #define SDVOC_GANG_MODE (1 << 16) /* Port C only */ 4540 #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */ 4541 #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */ 4542 #define SDVO_DETECTED (1 << 2) 4543 /* Bits to be preserved when writing */ 4544 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \ 4545 SDVO_INTERRUPT_ENABLE) 4546 #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE) 4547 4548 /* Gen 4 SDVO/HDMI bits: */ 4549 #define SDVO_COLOR_FORMAT_8bpc (0 << 26) 4550 #define SDVO_COLOR_FORMAT_MASK (7 << 26) 4551 #define SDVO_ENCODING_SDVO (0 << 10) 4552 #define SDVO_ENCODING_HDMI (2 << 10) 4553 #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */ 4554 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */ 4555 #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */ 4556 #define SDVO_AUDIO_ENABLE (1 << 6) 4557 /* VSYNC/HSYNC bits new with 965, default is to be set */ 4558 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) 4559 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) 4560 4561 /* Gen 5 (IBX) SDVO/HDMI bits: */ 4562 #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */ 4563 #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */ 4564 4565 /* Gen 6 (CPT) SDVO/HDMI bits: */ 4566 #define SDVO_PIPE_SEL_SHIFT_CPT 29 4567 #define SDVO_PIPE_SEL_MASK_CPT (3 << 29) 4568 #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29) 4569 4570 /* CHV SDVO/HDMI bits: */ 4571 #define SDVO_PIPE_SEL_SHIFT_CHV 24 4572 #define SDVO_PIPE_SEL_MASK_CHV (3 << 24) 4573 #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24) 4574 4575 4576 /* DVO port control */ 4577 #define _DVOA 0x61120 4578 #define DVOA _MMIO(_DVOA) 4579 #define _DVOB 0x61140 4580 #define DVOB _MMIO(_DVOB) 4581 #define _DVOC 0x61160 4582 #define DVOC _MMIO(_DVOC) 4583 #define DVO_ENABLE (1 << 31) 4584 #define DVO_PIPE_SEL_SHIFT 30 4585 #define DVO_PIPE_SEL_MASK (1 << 30) 4586 #define DVO_PIPE_SEL(pipe) ((pipe) << 30) 4587 #define DVO_PIPE_STALL_UNUSED (0 << 28) 4588 #define DVO_PIPE_STALL (1 << 28) 4589 #define DVO_PIPE_STALL_TV (2 << 28) 4590 #define DVO_PIPE_STALL_MASK (3 << 28) 4591 #define DVO_USE_VGA_SYNC (1 << 15) 4592 #define DVO_DATA_ORDER_I740 (0 << 14) 4593 #define DVO_DATA_ORDER_FP (1 << 14) 4594 #define DVO_VSYNC_DISABLE (1 << 11) 4595 #define DVO_HSYNC_DISABLE (1 << 10) 4596 #define DVO_VSYNC_TRISTATE (1 << 9) 4597 #define DVO_HSYNC_TRISTATE (1 << 8) 4598 #define DVO_BORDER_ENABLE (1 << 7) 4599 #define DVO_DATA_ORDER_GBRG (1 << 6) 4600 #define DVO_DATA_ORDER_RGGB (0 << 6) 4601 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) 4602 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) 4603 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4) 4604 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3) 4605 #define DVO_BLANK_ACTIVE_HIGH (1 << 2) 4606 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ 4607 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ 4608 #define DVO_PRESERVE_MASK (0x7 << 24) 4609 #define DVOA_SRCDIM _MMIO(0x61124) 4610 #define DVOB_SRCDIM _MMIO(0x61144) 4611 #define DVOC_SRCDIM _MMIO(0x61164) 4612 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12 4613 #define DVO_SRCDIM_VERTICAL_SHIFT 0 4614 4615 /* LVDS port control */ 4616 #define LVDS _MMIO(0x61180) 4617 /* 4618 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 4619 * the DPLL semantics change when the LVDS is assigned to that pipe. 4620 */ 4621 #define LVDS_PORT_EN (1 << 31) 4622 /* Selects pipe B for LVDS data. Must be set on pre-965. */ 4623 #define LVDS_PIPE_SEL_SHIFT 30 4624 #define LVDS_PIPE_SEL_MASK (1 << 30) 4625 #define LVDS_PIPE_SEL(pipe) ((pipe) << 30) 4626 #define LVDS_PIPE_SEL_SHIFT_CPT 29 4627 #define LVDS_PIPE_SEL_MASK_CPT (3 << 29) 4628 #define LVDS_PIPE_SEL_CPT(pipe) ((pipe) << 29) 4629 /* LVDS dithering flag on 965/g4x platform */ 4630 #define LVDS_ENABLE_DITHER (1 << 25) 4631 /* LVDS sync polarity flags. Set to invert (i.e. negative) */ 4632 #define LVDS_VSYNC_POLARITY (1 << 21) 4633 #define LVDS_HSYNC_POLARITY (1 << 20) 4634 4635 /* Enable border for unscaled (or aspect-scaled) display */ 4636 #define LVDS_BORDER_ENABLE (1 << 15) 4637 /* 4638 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 4639 * pixel. 4640 */ 4641 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) 4642 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) 4643 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 4644 /* 4645 * Controls the A3 data pair, which contains the additional LSBs for 24 bit 4646 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be 4647 * on. 4648 */ 4649 #define LVDS_A3_POWER_MASK (3 << 6) 4650 #define LVDS_A3_POWER_DOWN (0 << 6) 4651 #define LVDS_A3_POWER_UP (3 << 6) 4652 /* 4653 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP 4654 * is set. 4655 */ 4656 #define LVDS_CLKB_POWER_MASK (3 << 4) 4657 #define LVDS_CLKB_POWER_DOWN (0 << 4) 4658 #define LVDS_CLKB_POWER_UP (3 << 4) 4659 /* 4660 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 4661 * setting for whether we are in dual-channel mode. The B3 pair will 4662 * additionally only be powered up when LVDS_A3_POWER_UP is set. 4663 */ 4664 #define LVDS_B0B3_POWER_MASK (3 << 2) 4665 #define LVDS_B0B3_POWER_DOWN (0 << 2) 4666 #define LVDS_B0B3_POWER_UP (3 << 2) 4667 4668 /* Video Data Island Packet control */ 4669 #define VIDEO_DIP_DATA _MMIO(0x61178) 4670 /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC 4671 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte 4672 * of the infoframe structure specified by CEA-861. */ 4673 #define VIDEO_DIP_DATA_SIZE 32 4674 #define VIDEO_DIP_VSC_DATA_SIZE 36 4675 #define VIDEO_DIP_PPS_DATA_SIZE 132 4676 #define VIDEO_DIP_CTL _MMIO(0x61170) 4677 /* Pre HSW: */ 4678 #define VIDEO_DIP_ENABLE (1 << 31) 4679 #define VIDEO_DIP_PORT(port) ((port) << 29) 4680 #define VIDEO_DIP_PORT_MASK (3 << 29) 4681 #define VIDEO_DIP_ENABLE_GCP (1 << 25) /* ilk+ */ 4682 #define VIDEO_DIP_ENABLE_AVI (1 << 21) 4683 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) 4684 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21) /* ilk+ */ 4685 #define VIDEO_DIP_ENABLE_SPD (8 << 21) 4686 #define VIDEO_DIP_SELECT_AVI (0 << 19) 4687 #define VIDEO_DIP_SELECT_VENDOR (1 << 19) 4688 #define VIDEO_DIP_SELECT_GAMUT (2 << 19) 4689 #define VIDEO_DIP_SELECT_SPD (3 << 19) 4690 #define VIDEO_DIP_SELECT_MASK (3 << 19) 4691 #define VIDEO_DIP_FREQ_ONCE (0 << 16) 4692 #define VIDEO_DIP_FREQ_VSYNC (1 << 16) 4693 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) 4694 #define VIDEO_DIP_FREQ_MASK (3 << 16) 4695 /* HSW and later: */ 4696 #define DRM_DIP_ENABLE (1 << 28) 4697 #define PSR_VSC_BIT_7_SET (1 << 27) 4698 #define VSC_SELECT_MASK (0x3 << 25) 4699 #define VSC_SELECT_SHIFT 25 4700 #define VSC_DIP_HW_HEA_DATA (0 << 25) 4701 #define VSC_DIP_HW_HEA_SW_DATA (1 << 25) 4702 #define VSC_DIP_HW_DATA_SW_HEA (2 << 25) 4703 #define VSC_DIP_SW_HEA_DATA (3 << 25) 4704 #define VDIP_ENABLE_PPS (1 << 24) 4705 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) 4706 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) 4707 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) 4708 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) 4709 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) 4710 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) 4711 4712 /* Panel power sequencing */ 4713 #define PPS_BASE 0x61200 4714 #define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE) 4715 #define PCH_PPS_BASE 0xC7200 4716 4717 #define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->pps_mmio_base - \ 4718 PPS_BASE + (reg) + \ 4719 (pps_idx) * 0x100) 4720 4721 #define _PP_STATUS 0x61200 4722 #define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS) 4723 #define PP_ON REG_BIT(31) 4724 4725 #define _PP_CONTROL_1 0xc7204 4726 #define _PP_CONTROL_2 0xc7304 4727 #define ICP_PP_CONTROL(x) _MMIO(((x) == 1) ? _PP_CONTROL_1 : \ 4728 _PP_CONTROL_2) 4729 #define POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4) 4730 #define VDD_OVERRIDE_FORCE REG_BIT(3) 4731 #define BACKLIGHT_ENABLE REG_BIT(2) 4732 #define PWR_DOWN_ON_RESET REG_BIT(1) 4733 #define PWR_STATE_TARGET REG_BIT(0) 4734 /* 4735 * Indicates that all dependencies of the panel are on: 4736 * 4737 * - PLL enabled 4738 * - pipe enabled 4739 * - LVDS/DVOB/DVOC on 4740 */ 4741 #define PP_READY REG_BIT(30) 4742 #define PP_SEQUENCE_MASK REG_GENMASK(29, 28) 4743 #define PP_SEQUENCE_NONE REG_FIELD_PREP(PP_SEQUENCE_MASK, 0) 4744 #define PP_SEQUENCE_POWER_UP REG_FIELD_PREP(PP_SEQUENCE_MASK, 1) 4745 #define PP_SEQUENCE_POWER_DOWN REG_FIELD_PREP(PP_SEQUENCE_MASK, 2) 4746 #define PP_CYCLE_DELAY_ACTIVE REG_BIT(27) 4747 #define PP_SEQUENCE_STATE_MASK REG_GENMASK(3, 0) 4748 #define PP_SEQUENCE_STATE_OFF_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0) 4749 #define PP_SEQUENCE_STATE_OFF_S0_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1) 4750 #define PP_SEQUENCE_STATE_OFF_S0_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2) 4751 #define PP_SEQUENCE_STATE_OFF_S0_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3) 4752 #define PP_SEQUENCE_STATE_ON_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8) 4753 #define PP_SEQUENCE_STATE_ON_S1_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9) 4754 #define PP_SEQUENCE_STATE_ON_S1_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xa) 4755 #define PP_SEQUENCE_STATE_ON_S1_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xb) 4756 #define PP_SEQUENCE_STATE_RESET REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf) 4757 4758 #define _PP_CONTROL 0x61204 4759 #define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL) 4760 #define PANEL_UNLOCK_MASK REG_GENMASK(31, 16) 4761 #define PANEL_UNLOCK_REGS REG_FIELD_PREP(PANEL_UNLOCK_MASK, 0xabcd) 4762 #define BXT_POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4) 4763 #define EDP_FORCE_VDD REG_BIT(3) 4764 #define EDP_BLC_ENABLE REG_BIT(2) 4765 #define PANEL_POWER_RESET REG_BIT(1) 4766 #define PANEL_POWER_ON REG_BIT(0) 4767 4768 #define _PP_ON_DELAYS 0x61208 4769 #define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS) 4770 #define PANEL_PORT_SELECT_MASK REG_GENMASK(31, 30) 4771 #define PANEL_PORT_SELECT_LVDS REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 0) 4772 #define PANEL_PORT_SELECT_DPA REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 1) 4773 #define PANEL_PORT_SELECT_DPC REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 2) 4774 #define PANEL_PORT_SELECT_DPD REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 3) 4775 #define PANEL_PORT_SELECT_VLV(port) REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, port) 4776 #define PANEL_POWER_UP_DELAY_MASK REG_GENMASK(28, 16) 4777 #define PANEL_LIGHT_ON_DELAY_MASK REG_GENMASK(12, 0) 4778 4779 #define _PP_OFF_DELAYS 0x6120C 4780 #define PP_OFF_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_OFF_DELAYS) 4781 #define PANEL_POWER_DOWN_DELAY_MASK REG_GENMASK(28, 16) 4782 #define PANEL_LIGHT_OFF_DELAY_MASK REG_GENMASK(12, 0) 4783 4784 #define _PP_DIVISOR 0x61210 4785 #define PP_DIVISOR(pps_idx) _MMIO_PPS(pps_idx, _PP_DIVISOR) 4786 #define PP_REFERENCE_DIVIDER_MASK REG_GENMASK(31, 8) 4787 #define PANEL_POWER_CYCLE_DELAY_MASK REG_GENMASK(4, 0) 4788 4789 /* Panel fitting */ 4790 #define PFIT_CONTROL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230) 4791 #define PFIT_ENABLE (1 << 31) 4792 #define PFIT_PIPE_MASK (3 << 29) 4793 #define PFIT_PIPE_SHIFT 29 4794 #define VERT_INTERP_DISABLE (0 << 10) 4795 #define VERT_INTERP_BILINEAR (1 << 10) 4796 #define VERT_INTERP_MASK (3 << 10) 4797 #define VERT_AUTO_SCALE (1 << 9) 4798 #define HORIZ_INTERP_DISABLE (0 << 6) 4799 #define HORIZ_INTERP_BILINEAR (1 << 6) 4800 #define HORIZ_INTERP_MASK (3 << 6) 4801 #define HORIZ_AUTO_SCALE (1 << 5) 4802 #define PANEL_8TO6_DITHER_ENABLE (1 << 3) 4803 #define PFIT_FILTER_FUZZY (0 << 24) 4804 #define PFIT_SCALING_AUTO (0 << 26) 4805 #define PFIT_SCALING_PROGRAMMED (1 << 26) 4806 #define PFIT_SCALING_PILLAR (2 << 26) 4807 #define PFIT_SCALING_LETTER (3 << 26) 4808 #define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234) 4809 /* Pre-965 */ 4810 #define PFIT_VERT_SCALE_SHIFT 20 4811 #define PFIT_VERT_SCALE_MASK 0xfff00000 4812 #define PFIT_HORIZ_SCALE_SHIFT 4 4813 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 4814 /* 965+ */ 4815 #define PFIT_VERT_SCALE_SHIFT_965 16 4816 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000 4817 #define PFIT_HORIZ_SCALE_SHIFT_965 0 4818 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff 4819 4820 #define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238) 4821 4822 #define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61250) 4823 #define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61350) 4824 #define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \ 4825 _VLV_BLC_PWM_CTL2_B) 4826 4827 #define _VLV_BLC_PWM_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61254) 4828 #define _VLV_BLC_PWM_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61354) 4829 #define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \ 4830 _VLV_BLC_PWM_CTL_B) 4831 4832 #define _VLV_BLC_HIST_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61260) 4833 #define _VLV_BLC_HIST_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61360) 4834 #define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \ 4835 _VLV_BLC_HIST_CTL_B) 4836 4837 /* Backlight control */ 4838 #define BLC_PWM_CTL2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61250) /* 965+ only */ 4839 #define BLM_PWM_ENABLE (1 << 31) 4840 #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */ 4841 #define BLM_PIPE_SELECT (1 << 29) 4842 #define BLM_PIPE_SELECT_IVB (3 << 29) 4843 #define BLM_PIPE_A (0 << 29) 4844 #define BLM_PIPE_B (1 << 29) 4845 #define BLM_PIPE_C (2 << 29) /* ivb + */ 4846 #define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */ 4847 #define BLM_TRANSCODER_B BLM_PIPE_B 4848 #define BLM_TRANSCODER_C BLM_PIPE_C 4849 #define BLM_TRANSCODER_EDP (3 << 29) 4850 #define BLM_PIPE(pipe) ((pipe) << 29) 4851 #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */ 4852 #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26) 4853 #define BLM_PHASE_IN_ENABLE (1 << 25) 4854 #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24) 4855 #define BLM_PHASE_IN_TIME_BASE_SHIFT (16) 4856 #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16) 4857 #define BLM_PHASE_IN_COUNT_SHIFT (8) 4858 #define BLM_PHASE_IN_COUNT_MASK (0xff << 8) 4859 #define BLM_PHASE_IN_INCR_SHIFT (0) 4860 #define BLM_PHASE_IN_INCR_MASK (0xff << 0) 4861 #define BLC_PWM_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61254) 4862 /* 4863 * This is the most significant 15 bits of the number of backlight cycles in a 4864 * complete cycle of the modulated backlight control. 4865 * 4866 * The actual value is this field multiplied by two. 4867 */ 4868 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) 4869 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) 4870 #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */ 4871 /* 4872 * This is the number of cycles out of the backlight modulation cycle for which 4873 * the backlight is on. 4874 * 4875 * This field must be no greater than the number of cycles in the complete 4876 * backlight modulation cycle. 4877 */ 4878 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) 4879 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) 4880 #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe) 4881 #define BLM_POLARITY_PNV (1 << 0) /* pnv only */ 4882 4883 #define BLC_HIST_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260) 4884 #define BLM_HISTOGRAM_ENABLE (1 << 31) 4885 4886 /* New registers for PCH-split platforms. Safe where new bits show up, the 4887 * register layout machtes with gen4 BLC_PWM_CTL[12]. */ 4888 #define BLC_PWM_CPU_CTL2 _MMIO(0x48250) 4889 #define BLC_PWM_CPU_CTL _MMIO(0x48254) 4890 4891 #define HSW_BLC_PWM2_CTL _MMIO(0x48350) 4892 4893 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is 4894 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */ 4895 #define BLC_PWM_PCH_CTL1 _MMIO(0xc8250) 4896 #define BLM_PCH_PWM_ENABLE (1 << 31) 4897 #define BLM_PCH_OVERRIDE_ENABLE (1 << 30) 4898 #define BLM_PCH_POLARITY (1 << 29) 4899 #define BLC_PWM_PCH_CTL2 _MMIO(0xc8254) 4900 4901 #define UTIL_PIN_CTL _MMIO(0x48400) 4902 #define UTIL_PIN_ENABLE (1 << 31) 4903 4904 #define UTIL_PIN_PIPE(x) ((x) << 29) 4905 #define UTIL_PIN_PIPE_MASK (3 << 29) 4906 #define UTIL_PIN_MODE_PWM (1 << 24) 4907 #define UTIL_PIN_MODE_MASK (0xf << 24) 4908 #define UTIL_PIN_POLARITY (1 << 22) 4909 4910 /* BXT backlight register definition. */ 4911 #define _BXT_BLC_PWM_CTL1 0xC8250 4912 #define BXT_BLC_PWM_ENABLE (1 << 31) 4913 #define BXT_BLC_PWM_POLARITY (1 << 29) 4914 #define _BXT_BLC_PWM_FREQ1 0xC8254 4915 #define _BXT_BLC_PWM_DUTY1 0xC8258 4916 4917 #define _BXT_BLC_PWM_CTL2 0xC8350 4918 #define _BXT_BLC_PWM_FREQ2 0xC8354 4919 #define _BXT_BLC_PWM_DUTY2 0xC8358 4920 4921 #define BXT_BLC_PWM_CTL(controller) _MMIO_PIPE(controller, \ 4922 _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2) 4923 #define BXT_BLC_PWM_FREQ(controller) _MMIO_PIPE(controller, \ 4924 _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2) 4925 #define BXT_BLC_PWM_DUTY(controller) _MMIO_PIPE(controller, \ 4926 _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2) 4927 4928 #define PCH_GTC_CTL _MMIO(0xe7000) 4929 #define PCH_GTC_ENABLE (1 << 31) 4930 4931 /* TV port control */ 4932 #define TV_CTL _MMIO(0x68000) 4933 /* Enables the TV encoder */ 4934 # define TV_ENC_ENABLE (1 << 31) 4935 /* Sources the TV encoder input from pipe B instead of A. */ 4936 # define TV_ENC_PIPE_SEL_SHIFT 30 4937 # define TV_ENC_PIPE_SEL_MASK (1 << 30) 4938 # define TV_ENC_PIPE_SEL(pipe) ((pipe) << 30) 4939 /* Outputs composite video (DAC A only) */ 4940 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28) 4941 /* Outputs SVideo video (DAC B/C) */ 4942 # define TV_ENC_OUTPUT_SVIDEO (1 << 28) 4943 /* Outputs Component video (DAC A/B/C) */ 4944 # define TV_ENC_OUTPUT_COMPONENT (2 << 28) 4945 /* Outputs Composite and SVideo (DAC A/B/C) */ 4946 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) 4947 # define TV_TRILEVEL_SYNC (1 << 21) 4948 /* Enables slow sync generation (945GM only) */ 4949 # define TV_SLOW_SYNC (1 << 20) 4950 /* Selects 4x oversampling for 480i and 576p */ 4951 # define TV_OVERSAMPLE_4X (0 << 18) 4952 /* Selects 2x oversampling for 720p and 1080i */ 4953 # define TV_OVERSAMPLE_2X (1 << 18) 4954 /* Selects no oversampling for 1080p */ 4955 # define TV_OVERSAMPLE_NONE (2 << 18) 4956 /* Selects 8x oversampling */ 4957 # define TV_OVERSAMPLE_8X (3 << 18) 4958 # define TV_OVERSAMPLE_MASK (3 << 18) 4959 /* Selects progressive mode rather than interlaced */ 4960 # define TV_PROGRESSIVE (1 << 17) 4961 /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */ 4962 # define TV_PAL_BURST (1 << 16) 4963 /* Field for setting delay of Y compared to C */ 4964 # define TV_YC_SKEW_MASK (7 << 12) 4965 /* Enables a fix for 480p/576p standard definition modes on the 915GM only */ 4966 # define TV_ENC_SDP_FIX (1 << 11) 4967 /* 4968 * Enables a fix for the 915GM only. 4969 * 4970 * Not sure what it does. 4971 */ 4972 # define TV_ENC_C0_FIX (1 << 10) 4973 /* Bits that must be preserved by software */ 4974 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) 4975 # define TV_FUSE_STATE_MASK (3 << 4) 4976 /* Read-only state that reports all features enabled */ 4977 # define TV_FUSE_STATE_ENABLED (0 << 4) 4978 /* Read-only state that reports that Macrovision is disabled in hardware*/ 4979 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4) 4980 /* Read-only state that reports that TV-out is disabled in hardware. */ 4981 # define TV_FUSE_STATE_DISABLED (2 << 4) 4982 /* Normal operation */ 4983 # define TV_TEST_MODE_NORMAL (0 << 0) 4984 /* Encoder test pattern 1 - combo pattern */ 4985 # define TV_TEST_MODE_PATTERN_1 (1 << 0) 4986 /* Encoder test pattern 2 - full screen vertical 75% color bars */ 4987 # define TV_TEST_MODE_PATTERN_2 (2 << 0) 4988 /* Encoder test pattern 3 - full screen horizontal 75% color bars */ 4989 # define TV_TEST_MODE_PATTERN_3 (3 << 0) 4990 /* Encoder test pattern 4 - random noise */ 4991 # define TV_TEST_MODE_PATTERN_4 (4 << 0) 4992 /* Encoder test pattern 5 - linear color ramps */ 4993 # define TV_TEST_MODE_PATTERN_5 (5 << 0) 4994 /* 4995 * This test mode forces the DACs to 50% of full output. 4996 * 4997 * This is used for load detection in combination with TVDAC_SENSE_MASK 4998 */ 4999 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0) 5000 # define TV_TEST_MODE_MASK (7 << 0) 5001 5002 #define TV_DAC _MMIO(0x68004) 5003 # define TV_DAC_SAVE 0x00ffff00 5004 /* 5005 * Reports that DAC state change logic has reported change (RO). 5006 * 5007 * This gets cleared when TV_DAC_STATE_EN is cleared 5008 */ 5009 # define TVDAC_STATE_CHG (1 << 31) 5010 # define TVDAC_SENSE_MASK (7 << 28) 5011 /* Reports that DAC A voltage is above the detect threshold */ 5012 # define TVDAC_A_SENSE (1 << 30) 5013 /* Reports that DAC B voltage is above the detect threshold */ 5014 # define TVDAC_B_SENSE (1 << 29) 5015 /* Reports that DAC C voltage is above the detect threshold */ 5016 # define TVDAC_C_SENSE (1 << 28) 5017 /* 5018 * Enables DAC state detection logic, for load-based TV detection. 5019 * 5020 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set 5021 * to off, for load detection to work. 5022 */ 5023 # define TVDAC_STATE_CHG_EN (1 << 27) 5024 /* Sets the DAC A sense value to high */ 5025 # define TVDAC_A_SENSE_CTL (1 << 26) 5026 /* Sets the DAC B sense value to high */ 5027 # define TVDAC_B_SENSE_CTL (1 << 25) 5028 /* Sets the DAC C sense value to high */ 5029 # define TVDAC_C_SENSE_CTL (1 << 24) 5030 /* Overrides the ENC_ENABLE and DAC voltage levels */ 5031 # define DAC_CTL_OVERRIDE (1 << 7) 5032 /* Sets the slew rate. Must be preserved in software */ 5033 # define ENC_TVDAC_SLEW_FAST (1 << 6) 5034 # define DAC_A_1_3_V (0 << 4) 5035 # define DAC_A_1_1_V (1 << 4) 5036 # define DAC_A_0_7_V (2 << 4) 5037 # define DAC_A_MASK (3 << 4) 5038 # define DAC_B_1_3_V (0 << 2) 5039 # define DAC_B_1_1_V (1 << 2) 5040 # define DAC_B_0_7_V (2 << 2) 5041 # define DAC_B_MASK (3 << 2) 5042 # define DAC_C_1_3_V (0 << 0) 5043 # define DAC_C_1_1_V (1 << 0) 5044 # define DAC_C_0_7_V (2 << 0) 5045 # define DAC_C_MASK (3 << 0) 5046 5047 /* 5048 * CSC coefficients are stored in a floating point format with 9 bits of 5049 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, 5050 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with 5051 * -1 (0x3) being the only legal negative value. 5052 */ 5053 #define TV_CSC_Y _MMIO(0x68010) 5054 # define TV_RY_MASK 0x07ff0000 5055 # define TV_RY_SHIFT 16 5056 # define TV_GY_MASK 0x00000fff 5057 # define TV_GY_SHIFT 0 5058 5059 #define TV_CSC_Y2 _MMIO(0x68014) 5060 # define TV_BY_MASK 0x07ff0000 5061 # define TV_BY_SHIFT 16 5062 /* 5063 * Y attenuation for component video. 5064 * 5065 * Stored in 1.9 fixed point. 5066 */ 5067 # define TV_AY_MASK 0x000003ff 5068 # define TV_AY_SHIFT 0 5069 5070 #define TV_CSC_U _MMIO(0x68018) 5071 # define TV_RU_MASK 0x07ff0000 5072 # define TV_RU_SHIFT 16 5073 # define TV_GU_MASK 0x000007ff 5074 # define TV_GU_SHIFT 0 5075 5076 #define TV_CSC_U2 _MMIO(0x6801c) 5077 # define TV_BU_MASK 0x07ff0000 5078 # define TV_BU_SHIFT 16 5079 /* 5080 * U attenuation for component video. 5081 * 5082 * Stored in 1.9 fixed point. 5083 */ 5084 # define TV_AU_MASK 0x000003ff 5085 # define TV_AU_SHIFT 0 5086 5087 #define TV_CSC_V _MMIO(0x68020) 5088 # define TV_RV_MASK 0x0fff0000 5089 # define TV_RV_SHIFT 16 5090 # define TV_GV_MASK 0x000007ff 5091 # define TV_GV_SHIFT 0 5092 5093 #define TV_CSC_V2 _MMIO(0x68024) 5094 # define TV_BV_MASK 0x07ff0000 5095 # define TV_BV_SHIFT 16 5096 /* 5097 * V attenuation for component video. 5098 * 5099 * Stored in 1.9 fixed point. 5100 */ 5101 # define TV_AV_MASK 0x000007ff 5102 # define TV_AV_SHIFT 0 5103 5104 #define TV_CLR_KNOBS _MMIO(0x68028) 5105 /* 2s-complement brightness adjustment */ 5106 # define TV_BRIGHTNESS_MASK 0xff000000 5107 # define TV_BRIGHTNESS_SHIFT 24 5108 /* Contrast adjustment, as a 2.6 unsigned floating point number */ 5109 # define TV_CONTRAST_MASK 0x00ff0000 5110 # define TV_CONTRAST_SHIFT 16 5111 /* Saturation adjustment, as a 2.6 unsigned floating point number */ 5112 # define TV_SATURATION_MASK 0x0000ff00 5113 # define TV_SATURATION_SHIFT 8 5114 /* Hue adjustment, as an integer phase angle in degrees */ 5115 # define TV_HUE_MASK 0x000000ff 5116 # define TV_HUE_SHIFT 0 5117 5118 #define TV_CLR_LEVEL _MMIO(0x6802c) 5119 /* Controls the DAC level for black */ 5120 # define TV_BLACK_LEVEL_MASK 0x01ff0000 5121 # define TV_BLACK_LEVEL_SHIFT 16 5122 /* Controls the DAC level for blanking */ 5123 # define TV_BLANK_LEVEL_MASK 0x000001ff 5124 # define TV_BLANK_LEVEL_SHIFT 0 5125 5126 #define TV_H_CTL_1 _MMIO(0x68030) 5127 /* Number of pixels in the hsync. */ 5128 # define TV_HSYNC_END_MASK 0x1fff0000 5129 # define TV_HSYNC_END_SHIFT 16 5130 /* Total number of pixels minus one in the line (display and blanking). */ 5131 # define TV_HTOTAL_MASK 0x00001fff 5132 # define TV_HTOTAL_SHIFT 0 5133 5134 #define TV_H_CTL_2 _MMIO(0x68034) 5135 /* Enables the colorburst (needed for non-component color) */ 5136 # define TV_BURST_ENA (1 << 31) 5137 /* Offset of the colorburst from the start of hsync, in pixels minus one. */ 5138 # define TV_HBURST_START_SHIFT 16 5139 # define TV_HBURST_START_MASK 0x1fff0000 5140 /* Length of the colorburst */ 5141 # define TV_HBURST_LEN_SHIFT 0 5142 # define TV_HBURST_LEN_MASK 0x0001fff 5143 5144 #define TV_H_CTL_3 _MMIO(0x68038) 5145 /* End of hblank, measured in pixels minus one from start of hsync */ 5146 # define TV_HBLANK_END_SHIFT 16 5147 # define TV_HBLANK_END_MASK 0x1fff0000 5148 /* Start of hblank, measured in pixels minus one from start of hsync */ 5149 # define TV_HBLANK_START_SHIFT 0 5150 # define TV_HBLANK_START_MASK 0x0001fff 5151 5152 #define TV_V_CTL_1 _MMIO(0x6803c) 5153 /* XXX */ 5154 # define TV_NBR_END_SHIFT 16 5155 # define TV_NBR_END_MASK 0x07ff0000 5156 /* XXX */ 5157 # define TV_VI_END_F1_SHIFT 8 5158 # define TV_VI_END_F1_MASK 0x00003f00 5159 /* XXX */ 5160 # define TV_VI_END_F2_SHIFT 0 5161 # define TV_VI_END_F2_MASK 0x0000003f 5162 5163 #define TV_V_CTL_2 _MMIO(0x68040) 5164 /* Length of vsync, in half lines */ 5165 # define TV_VSYNC_LEN_MASK 0x07ff0000 5166 # define TV_VSYNC_LEN_SHIFT 16 5167 /* Offset of the start of vsync in field 1, measured in one less than the 5168 * number of half lines. 5169 */ 5170 # define TV_VSYNC_START_F1_MASK 0x00007f00 5171 # define TV_VSYNC_START_F1_SHIFT 8 5172 /* 5173 * Offset of the start of vsync in field 2, measured in one less than the 5174 * number of half lines. 5175 */ 5176 # define TV_VSYNC_START_F2_MASK 0x0000007f 5177 # define TV_VSYNC_START_F2_SHIFT 0 5178 5179 #define TV_V_CTL_3 _MMIO(0x68044) 5180 /* Enables generation of the equalization signal */ 5181 # define TV_EQUAL_ENA (1 << 31) 5182 /* Length of vsync, in half lines */ 5183 # define TV_VEQ_LEN_MASK 0x007f0000 5184 # define TV_VEQ_LEN_SHIFT 16 5185 /* Offset of the start of equalization in field 1, measured in one less than 5186 * the number of half lines. 5187 */ 5188 # define TV_VEQ_START_F1_MASK 0x0007f00 5189 # define TV_VEQ_START_F1_SHIFT 8 5190 /* 5191 * Offset of the start of equalization in field 2, measured in one less than 5192 * the number of half lines. 5193 */ 5194 # define TV_VEQ_START_F2_MASK 0x000007f 5195 # define TV_VEQ_START_F2_SHIFT 0 5196 5197 #define TV_V_CTL_4 _MMIO(0x68048) 5198 /* 5199 * Offset to start of vertical colorburst, measured in one less than the 5200 * number of lines from vertical start. 5201 */ 5202 # define TV_VBURST_START_F1_MASK 0x003f0000 5203 # define TV_VBURST_START_F1_SHIFT 16 5204 /* 5205 * Offset to the end of vertical colorburst, measured in one less than the 5206 * number of lines from the start of NBR. 5207 */ 5208 # define TV_VBURST_END_F1_MASK 0x000000ff 5209 # define TV_VBURST_END_F1_SHIFT 0 5210 5211 #define TV_V_CTL_5 _MMIO(0x6804c) 5212 /* 5213 * Offset to start of vertical colorburst, measured in one less than the 5214 * number of lines from vertical start. 5215 */ 5216 # define TV_VBURST_START_F2_MASK 0x003f0000 5217 # define TV_VBURST_START_F2_SHIFT 16 5218 /* 5219 * Offset to the end of vertical colorburst, measured in one less than the 5220 * number of lines from the start of NBR. 5221 */ 5222 # define TV_VBURST_END_F2_MASK 0x000000ff 5223 # define TV_VBURST_END_F2_SHIFT 0 5224 5225 #define TV_V_CTL_6 _MMIO(0x68050) 5226 /* 5227 * Offset to start of vertical colorburst, measured in one less than the 5228 * number of lines from vertical start. 5229 */ 5230 # define TV_VBURST_START_F3_MASK 0x003f0000 5231 # define TV_VBURST_START_F3_SHIFT 16 5232 /* 5233 * Offset to the end of vertical colorburst, measured in one less than the 5234 * number of lines from the start of NBR. 5235 */ 5236 # define TV_VBURST_END_F3_MASK 0x000000ff 5237 # define TV_VBURST_END_F3_SHIFT 0 5238 5239 #define TV_V_CTL_7 _MMIO(0x68054) 5240 /* 5241 * Offset to start of vertical colorburst, measured in one less than the 5242 * number of lines from vertical start. 5243 */ 5244 # define TV_VBURST_START_F4_MASK 0x003f0000 5245 # define TV_VBURST_START_F4_SHIFT 16 5246 /* 5247 * Offset to the end of vertical colorburst, measured in one less than the 5248 * number of lines from the start of NBR. 5249 */ 5250 # define TV_VBURST_END_F4_MASK 0x000000ff 5251 # define TV_VBURST_END_F4_SHIFT 0 5252 5253 #define TV_SC_CTL_1 _MMIO(0x68060) 5254 /* Turns on the first subcarrier phase generation DDA */ 5255 # define TV_SC_DDA1_EN (1 << 31) 5256 /* Turns on the first subcarrier phase generation DDA */ 5257 # define TV_SC_DDA2_EN (1 << 30) 5258 /* Turns on the first subcarrier phase generation DDA */ 5259 # define TV_SC_DDA3_EN (1 << 29) 5260 /* Sets the subcarrier DDA to reset frequency every other field */ 5261 # define TV_SC_RESET_EVERY_2 (0 << 24) 5262 /* Sets the subcarrier DDA to reset frequency every fourth field */ 5263 # define TV_SC_RESET_EVERY_4 (1 << 24) 5264 /* Sets the subcarrier DDA to reset frequency every eighth field */ 5265 # define TV_SC_RESET_EVERY_8 (2 << 24) 5266 /* Sets the subcarrier DDA to never reset the frequency */ 5267 # define TV_SC_RESET_NEVER (3 << 24) 5268 /* Sets the peak amplitude of the colorburst.*/ 5269 # define TV_BURST_LEVEL_MASK 0x00ff0000 5270 # define TV_BURST_LEVEL_SHIFT 16 5271 /* Sets the increment of the first subcarrier phase generation DDA */ 5272 # define TV_SCDDA1_INC_MASK 0x00000fff 5273 # define TV_SCDDA1_INC_SHIFT 0 5274 5275 #define TV_SC_CTL_2 _MMIO(0x68064) 5276 /* Sets the rollover for the second subcarrier phase generation DDA */ 5277 # define TV_SCDDA2_SIZE_MASK 0x7fff0000 5278 # define TV_SCDDA2_SIZE_SHIFT 16 5279 /* Sets the increent of the second subcarrier phase generation DDA */ 5280 # define TV_SCDDA2_INC_MASK 0x00007fff 5281 # define TV_SCDDA2_INC_SHIFT 0 5282 5283 #define TV_SC_CTL_3 _MMIO(0x68068) 5284 /* Sets the rollover for the third subcarrier phase generation DDA */ 5285 # define TV_SCDDA3_SIZE_MASK 0x7fff0000 5286 # define TV_SCDDA3_SIZE_SHIFT 16 5287 /* Sets the increent of the third subcarrier phase generation DDA */ 5288 # define TV_SCDDA3_INC_MASK 0x00007fff 5289 # define TV_SCDDA3_INC_SHIFT 0 5290 5291 #define TV_WIN_POS _MMIO(0x68070) 5292 /* X coordinate of the display from the start of horizontal active */ 5293 # define TV_XPOS_MASK 0x1fff0000 5294 # define TV_XPOS_SHIFT 16 5295 /* Y coordinate of the display from the start of vertical active (NBR) */ 5296 # define TV_YPOS_MASK 0x00000fff 5297 # define TV_YPOS_SHIFT 0 5298 5299 #define TV_WIN_SIZE _MMIO(0x68074) 5300 /* Horizontal size of the display window, measured in pixels*/ 5301 # define TV_XSIZE_MASK 0x1fff0000 5302 # define TV_XSIZE_SHIFT 16 5303 /* 5304 * Vertical size of the display window, measured in pixels. 5305 * 5306 * Must be even for interlaced modes. 5307 */ 5308 # define TV_YSIZE_MASK 0x00000fff 5309 # define TV_YSIZE_SHIFT 0 5310 5311 #define TV_FILTER_CTL_1 _MMIO(0x68080) 5312 /* 5313 * Enables automatic scaling calculation. 5314 * 5315 * If set, the rest of the registers are ignored, and the calculated values can 5316 * be read back from the register. 5317 */ 5318 # define TV_AUTO_SCALE (1 << 31) 5319 /* 5320 * Disables the vertical filter. 5321 * 5322 * This is required on modes more than 1024 pixels wide */ 5323 # define TV_V_FILTER_BYPASS (1 << 29) 5324 /* Enables adaptive vertical filtering */ 5325 # define TV_VADAPT (1 << 28) 5326 # define TV_VADAPT_MODE_MASK (3 << 26) 5327 /* Selects the least adaptive vertical filtering mode */ 5328 # define TV_VADAPT_MODE_LEAST (0 << 26) 5329 /* Selects the moderately adaptive vertical filtering mode */ 5330 # define TV_VADAPT_MODE_MODERATE (1 << 26) 5331 /* Selects the most adaptive vertical filtering mode */ 5332 # define TV_VADAPT_MODE_MOST (3 << 26) 5333 /* 5334 * Sets the horizontal scaling factor. 5335 * 5336 * This should be the fractional part of the horizontal scaling factor divided 5337 * by the oversampling rate. TV_HSCALE should be less than 1, and set to: 5338 * 5339 * (src width - 1) / ((oversample * dest width) - 1) 5340 */ 5341 # define TV_HSCALE_FRAC_MASK 0x00003fff 5342 # define TV_HSCALE_FRAC_SHIFT 0 5343 5344 #define TV_FILTER_CTL_2 _MMIO(0x68084) 5345 /* 5346 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 5347 * 5348 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) 5349 */ 5350 # define TV_VSCALE_INT_MASK 0x00038000 5351 # define TV_VSCALE_INT_SHIFT 15 5352 /* 5353 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 5354 * 5355 * \sa TV_VSCALE_INT_MASK 5356 */ 5357 # define TV_VSCALE_FRAC_MASK 0x00007fff 5358 # define TV_VSCALE_FRAC_SHIFT 0 5359 5360 #define TV_FILTER_CTL_3 _MMIO(0x68088) 5361 /* 5362 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 5363 * 5364 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) 5365 * 5366 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 5367 */ 5368 # define TV_VSCALE_IP_INT_MASK 0x00038000 5369 # define TV_VSCALE_IP_INT_SHIFT 15 5370 /* 5371 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 5372 * 5373 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 5374 * 5375 * \sa TV_VSCALE_IP_INT_MASK 5376 */ 5377 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff 5378 # define TV_VSCALE_IP_FRAC_SHIFT 0 5379 5380 #define TV_CC_CONTROL _MMIO(0x68090) 5381 # define TV_CC_ENABLE (1 << 31) 5382 /* 5383 * Specifies which field to send the CC data in. 5384 * 5385 * CC data is usually sent in field 0. 5386 */ 5387 # define TV_CC_FID_MASK (1 << 27) 5388 # define TV_CC_FID_SHIFT 27 5389 /* Sets the horizontal position of the CC data. Usually 135. */ 5390 # define TV_CC_HOFF_MASK 0x03ff0000 5391 # define TV_CC_HOFF_SHIFT 16 5392 /* Sets the vertical position of the CC data. Usually 21 */ 5393 # define TV_CC_LINE_MASK 0x0000003f 5394 # define TV_CC_LINE_SHIFT 0 5395 5396 #define TV_CC_DATA _MMIO(0x68094) 5397 # define TV_CC_RDY (1 << 31) 5398 /* Second word of CC data to be transmitted. */ 5399 # define TV_CC_DATA_2_MASK 0x007f0000 5400 # define TV_CC_DATA_2_SHIFT 16 5401 /* First word of CC data to be transmitted. */ 5402 # define TV_CC_DATA_1_MASK 0x0000007f 5403 # define TV_CC_DATA_1_SHIFT 0 5404 5405 #define TV_H_LUMA(i) _MMIO(0x68100 + (i) * 4) /* 60 registers */ 5406 #define TV_H_CHROMA(i) _MMIO(0x68200 + (i) * 4) /* 60 registers */ 5407 #define TV_V_LUMA(i) _MMIO(0x68300 + (i) * 4) /* 43 registers */ 5408 #define TV_V_CHROMA(i) _MMIO(0x68400 + (i) * 4) /* 43 registers */ 5409 5410 /* Display Port */ 5411 #define DP_A _MMIO(0x64000) /* eDP */ 5412 #define DP_B _MMIO(0x64100) 5413 #define DP_C _MMIO(0x64200) 5414 #define DP_D _MMIO(0x64300) 5415 5416 #define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100) 5417 #define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200) 5418 #define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300) 5419 5420 #define DP_PORT_EN (1 << 31) 5421 #define DP_PIPE_SEL_SHIFT 30 5422 #define DP_PIPE_SEL_MASK (1 << 30) 5423 #define DP_PIPE_SEL(pipe) ((pipe) << 30) 5424 #define DP_PIPE_SEL_SHIFT_IVB 29 5425 #define DP_PIPE_SEL_MASK_IVB (3 << 29) 5426 #define DP_PIPE_SEL_IVB(pipe) ((pipe) << 29) 5427 #define DP_PIPE_SEL_SHIFT_CHV 16 5428 #define DP_PIPE_SEL_MASK_CHV (3 << 16) 5429 #define DP_PIPE_SEL_CHV(pipe) ((pipe) << 16) 5430 5431 /* Link training mode - select a suitable mode for each stage */ 5432 #define DP_LINK_TRAIN_PAT_1 (0 << 28) 5433 #define DP_LINK_TRAIN_PAT_2 (1 << 28) 5434 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) 5435 #define DP_LINK_TRAIN_OFF (3 << 28) 5436 #define DP_LINK_TRAIN_MASK (3 << 28) 5437 #define DP_LINK_TRAIN_SHIFT 28 5438 5439 /* CPT Link training mode */ 5440 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) 5441 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) 5442 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) 5443 #define DP_LINK_TRAIN_OFF_CPT (3 << 8) 5444 #define DP_LINK_TRAIN_MASK_CPT (7 << 8) 5445 #define DP_LINK_TRAIN_SHIFT_CPT 8 5446 5447 /* Signal voltages. These are mostly controlled by the other end */ 5448 #define DP_VOLTAGE_0_4 (0 << 25) 5449 #define DP_VOLTAGE_0_6 (1 << 25) 5450 #define DP_VOLTAGE_0_8 (2 << 25) 5451 #define DP_VOLTAGE_1_2 (3 << 25) 5452 #define DP_VOLTAGE_MASK (7 << 25) 5453 #define DP_VOLTAGE_SHIFT 25 5454 5455 /* Signal pre-emphasis levels, like voltages, the other end tells us what 5456 * they want 5457 */ 5458 #define DP_PRE_EMPHASIS_0 (0 << 22) 5459 #define DP_PRE_EMPHASIS_3_5 (1 << 22) 5460 #define DP_PRE_EMPHASIS_6 (2 << 22) 5461 #define DP_PRE_EMPHASIS_9_5 (3 << 22) 5462 #define DP_PRE_EMPHASIS_MASK (7 << 22) 5463 #define DP_PRE_EMPHASIS_SHIFT 22 5464 5465 /* How many wires to use. I guess 3 was too hard */ 5466 #define DP_PORT_WIDTH(width) (((width) - 1) << 19) 5467 #define DP_PORT_WIDTH_MASK (7 << 19) 5468 #define DP_PORT_WIDTH_SHIFT 19 5469 5470 /* Mystic DPCD version 1.1 special mode */ 5471 #define DP_ENHANCED_FRAMING (1 << 18) 5472 5473 /* eDP */ 5474 #define DP_PLL_FREQ_270MHZ (0 << 16) 5475 #define DP_PLL_FREQ_162MHZ (1 << 16) 5476 #define DP_PLL_FREQ_MASK (3 << 16) 5477 5478 /* locked once port is enabled */ 5479 #define DP_PORT_REVERSAL (1 << 15) 5480 5481 /* eDP */ 5482 #define DP_PLL_ENABLE (1 << 14) 5483 5484 /* sends the clock on lane 15 of the PEG for debug */ 5485 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) 5486 5487 #define DP_SCRAMBLING_DISABLE (1 << 12) 5488 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) 5489 5490 /* limit RGB values to avoid confusing TVs */ 5491 #define DP_COLOR_RANGE_16_235 (1 << 8) 5492 5493 /* Turn on the audio link */ 5494 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) 5495 5496 /* vs and hs sync polarity */ 5497 #define DP_SYNC_VS_HIGH (1 << 4) 5498 #define DP_SYNC_HS_HIGH (1 << 3) 5499 5500 /* A fantasy */ 5501 #define DP_DETECTED (1 << 2) 5502 5503 /* The aux channel provides a way to talk to the 5504 * signal sink for DDC etc. Max packet size supported 5505 * is 20 bytes in each direction, hence the 5 fixed 5506 * data registers 5507 */ 5508 #define _DPA_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64010) 5509 #define _DPA_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64014) 5510 #define _DPA_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64018) 5511 #define _DPA_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6401c) 5512 #define _DPA_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64020) 5513 #define _DPA_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64024) 5514 5515 #define _DPB_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64110) 5516 #define _DPB_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64114) 5517 #define _DPB_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64118) 5518 #define _DPB_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6411c) 5519 #define _DPB_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64120) 5520 #define _DPB_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64124) 5521 5522 #define _DPC_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64210) 5523 #define _DPC_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64214) 5524 #define _DPC_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64218) 5525 #define _DPC_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6421c) 5526 #define _DPC_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64220) 5527 #define _DPC_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64224) 5528 5529 #define _DPD_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64310) 5530 #define _DPD_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64314) 5531 #define _DPD_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64318) 5532 #define _DPD_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6431c) 5533 #define _DPD_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64320) 5534 #define _DPD_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64324) 5535 5536 #define _DPE_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64410) 5537 #define _DPE_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64414) 5538 #define _DPE_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64418) 5539 #define _DPE_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6441c) 5540 #define _DPE_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64420) 5541 #define _DPE_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64424) 5542 5543 #define _DPF_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64510) 5544 #define _DPF_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64514) 5545 #define _DPF_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64518) 5546 #define _DPF_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6451c) 5547 #define _DPF_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64520) 5548 #define _DPF_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64524) 5549 5550 #define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL) 5551 #define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ 5552 5553 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) 5554 #define DP_AUX_CH_CTL_DONE (1 << 30) 5555 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) 5556 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) 5557 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) 5558 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) 5559 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) 5560 #define DP_AUX_CH_CTL_TIME_OUT_MAX (3 << 26) /* Varies per platform */ 5561 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) 5562 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) 5563 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) 5564 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 5565 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) 5566 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 5567 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) 5568 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) 5569 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) 5570 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) 5571 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) 5572 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) 5573 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 5574 #define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14) 5575 #define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13) 5576 #define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12) 5577 #define DP_AUX_CH_CTL_TBT_IO (1 << 11) 5578 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5) 5579 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5) 5580 #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1) 5581 5582 /* 5583 * Computing GMCH M and N values for the Display Port link 5584 * 5585 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes 5586 * 5587 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) 5588 * 5589 * The GMCH value is used internally 5590 * 5591 * bytes_per_pixel is the number of bytes coming out of the plane, 5592 * which is after the LUTs, so we want the bytes for our color format. 5593 * For our current usage, this is always 3, one byte for R, G and B. 5594 */ 5595 #define _PIPEA_DATA_M_G4X 0x70050 5596 #define _PIPEB_DATA_M_G4X 0x71050 5597 5598 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ 5599 #define TU_SIZE(x) (((x) - 1) << 25) /* default size 64 */ 5600 #define TU_SIZE_SHIFT 25 5601 #define TU_SIZE_MASK (0x3f << 25) 5602 5603 #define DATA_LINK_M_N_MASK (0xffffff) 5604 #define DATA_LINK_N_MAX (0x800000) 5605 5606 #define _PIPEA_DATA_N_G4X 0x70054 5607 #define _PIPEB_DATA_N_G4X 0x71054 5608 #define PIPE_GMCH_DATA_N_MASK (0xffffff) 5609 5610 /* 5611 * Computing Link M and N values for the Display Port link 5612 * 5613 * Link M / N = pixel_clock / ls_clk 5614 * 5615 * (the DP spec calls pixel_clock the 'strm_clk') 5616 * 5617 * The Link value is transmitted in the Main Stream 5618 * Attributes and VB-ID. 5619 */ 5620 5621 #define _PIPEA_LINK_M_G4X 0x70060 5622 #define _PIPEB_LINK_M_G4X 0x71060 5623 #define PIPEA_DP_LINK_M_MASK (0xffffff) 5624 5625 #define _PIPEA_LINK_N_G4X 0x70064 5626 #define _PIPEB_LINK_N_G4X 0x71064 5627 #define PIPEA_DP_LINK_N_MASK (0xffffff) 5628 5629 #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X) 5630 #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X) 5631 #define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X) 5632 #define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X) 5633 5634 /* Display & cursor control */ 5635 5636 /* Pipe A */ 5637 #define _PIPEADSL 0x70000 5638 #define DSL_LINEMASK_GEN2 0x00000fff 5639 #define DSL_LINEMASK_GEN3 0x00001fff 5640 #define _PIPEACONF 0x70008 5641 #define PIPECONF_ENABLE (1 << 31) 5642 #define PIPECONF_DISABLE 0 5643 #define PIPECONF_DOUBLE_WIDE (1 << 30) 5644 #define I965_PIPECONF_ACTIVE (1 << 30) 5645 #define PIPECONF_DSI_PLL_LOCKED (1 << 29) /* vlv & pipe A only */ 5646 #define PIPECONF_FRAME_START_DELAY_MASK (3 << 27) 5647 #define PIPECONF_SINGLE_WIDE 0 5648 #define PIPECONF_PIPE_UNLOCKED 0 5649 #define PIPECONF_PIPE_LOCKED (1 << 25) 5650 #define PIPECONF_FORCE_BORDER (1 << 25) 5651 #define PIPECONF_GAMMA_MODE_MASK_I9XX (1 << 24) /* gmch */ 5652 #define PIPECONF_GAMMA_MODE_MASK_ILK (3 << 24) /* ilk-ivb */ 5653 #define PIPECONF_GAMMA_MODE_8BIT (0 << 24) /* gmch,ilk-ivb */ 5654 #define PIPECONF_GAMMA_MODE_10BIT (1 << 24) /* gmch,ilk-ivb */ 5655 #define PIPECONF_GAMMA_MODE_12BIT (2 << 24) /* ilk-ivb */ 5656 #define PIPECONF_GAMMA_MODE_SPLIT (3 << 24) /* ivb */ 5657 #define PIPECONF_GAMMA_MODE(x) ((x) << 24) /* pass in GAMMA_MODE_MODE_* */ 5658 #define PIPECONF_GAMMA_MODE_SHIFT 24 5659 #define PIPECONF_INTERLACE_MASK (7 << 21) 5660 #define PIPECONF_INTERLACE_MASK_HSW (3 << 21) 5661 /* Note that pre-gen3 does not support interlaced display directly. Panel 5662 * fitting must be disabled on pre-ilk for interlaced. */ 5663 #define PIPECONF_PROGRESSIVE (0 << 21) 5664 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */ 5665 #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */ 5666 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 5667 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */ 5668 /* Ironlake and later have a complete new set of values for interlaced. PFIT 5669 * means panel fitter required, PF means progressive fetch, DBL means power 5670 * saving pixel doubling. */ 5671 #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21) 5672 #define PIPECONF_INTERLACED_ILK (3 << 21) 5673 #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ 5674 #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ 5675 #define PIPECONF_INTERLACE_MODE_MASK (7 << 21) 5676 #define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20) 5677 #define PIPECONF_CXSR_DOWNCLOCK (1 << 16) 5678 #define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14) 5679 #define PIPECONF_COLOR_RANGE_SELECT (1 << 13) 5680 #define PIPECONF_BPC_MASK (0x7 << 5) 5681 #define PIPECONF_8BPC (0 << 5) 5682 #define PIPECONF_10BPC (1 << 5) 5683 #define PIPECONF_6BPC (2 << 5) 5684 #define PIPECONF_12BPC (3 << 5) 5685 #define PIPECONF_DITHER_EN (1 << 4) 5686 #define PIPECONF_DITHER_TYPE_MASK (0x0000000c) 5687 #define PIPECONF_DITHER_TYPE_SP (0 << 2) 5688 #define PIPECONF_DITHER_TYPE_ST1 (1 << 2) 5689 #define PIPECONF_DITHER_TYPE_ST2 (2 << 2) 5690 #define PIPECONF_DITHER_TYPE_TEMP (3 << 2) 5691 #define _PIPEASTAT 0x70024 5692 #define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31) 5693 #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30) 5694 #define PIPE_CRC_ERROR_ENABLE (1UL << 29) 5695 #define PIPE_CRC_DONE_ENABLE (1UL << 28) 5696 #define PERF_COUNTER2_INTERRUPT_EN (1UL << 27) 5697 #define PIPE_GMBUS_EVENT_ENABLE (1UL << 27) 5698 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL << 26) 5699 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26) 5700 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25) 5701 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24) 5702 #define PIPE_DPST_EVENT_ENABLE (1UL << 23) 5703 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22) 5704 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22) 5705 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21) 5706 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL << 20) 5707 #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL << 19) 5708 #define PERF_COUNTER_INTERRUPT_EN (1UL << 19) 5709 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */ 5710 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18) /* 965 or later */ 5711 #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL << 17) 5712 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17) 5713 #define PIPEA_HBLANK_INT_EN_VLV (1UL << 16) 5714 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL << 16) 5715 #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL << 15) 5716 #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL << 14) 5717 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL << 13) 5718 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL << 12) 5719 #define PERF_COUNTER2_INTERRUPT_STATUS (1UL << 11) 5720 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL << 11) 5721 #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL << 10) 5722 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10) 5723 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9) 5724 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8) 5725 #define PIPE_DPST_EVENT_STATUS (1UL << 7) 5726 #define PIPE_A_PSR_STATUS_VLV (1UL << 6) 5727 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6) 5728 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5) 5729 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL << 4) 5730 #define PIPE_B_PSR_STATUS_VLV (1UL << 3) 5731 #define PERF_COUNTER_INTERRUPT_STATUS (1UL << 3) 5732 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */ 5733 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2) /* 965 or later */ 5734 #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL << 1) 5735 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1) 5736 #define PIPE_HBLANK_INT_STATUS (1UL << 0) 5737 #define PIPE_OVERLAY_UPDATED_STATUS (1UL << 0) 5738 5739 #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000 5740 #define PIPESTAT_INT_STATUS_MASK 0x0000ffff 5741 5742 #define PIPE_A_OFFSET 0x70000 5743 #define PIPE_B_OFFSET 0x71000 5744 #define PIPE_C_OFFSET 0x72000 5745 #define CHV_PIPE_C_OFFSET 0x74000 5746 /* 5747 * There's actually no pipe EDP. Some pipe registers have 5748 * simply shifted from the pipe to the transcoder, while 5749 * keeping their original offset. Thus we need PIPE_EDP_OFFSET 5750 * to access such registers in transcoder EDP. 5751 */ 5752 #define PIPE_EDP_OFFSET 0x7f000 5753 5754 /* ICL DSI 0 and 1 */ 5755 #define PIPE_DSI0_OFFSET 0x7b000 5756 #define PIPE_DSI1_OFFSET 0x7b800 5757 5758 #define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF) 5759 #define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL) 5760 #define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH) 5761 #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL) 5762 #define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT) 5763 5764 #define _PIPEAGCMAX 0x70010 5765 #define _PIPEBGCMAX 0x71010 5766 #define PIPEGCMAX(pipe, i) _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4) 5767 5768 #define _PIPE_MISC_A 0x70030 5769 #define _PIPE_MISC_B 0x71030 5770 #define PIPEMISC_YUV420_ENABLE (1 << 27) 5771 #define PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26) 5772 #define PIPEMISC_OUTPUT_COLORSPACE_YUV (1 << 11) 5773 #define PIPEMISC_DITHER_BPC_MASK (7 << 5) 5774 #define PIPEMISC_DITHER_8_BPC (0 << 5) 5775 #define PIPEMISC_DITHER_10_BPC (1 << 5) 5776 #define PIPEMISC_DITHER_6_BPC (2 << 5) 5777 #define PIPEMISC_DITHER_12_BPC (3 << 5) 5778 #define PIPEMISC_DITHER_ENABLE (1 << 4) 5779 #define PIPEMISC_DITHER_TYPE_MASK (3 << 2) 5780 #define PIPEMISC_DITHER_TYPE_SP (0 << 2) 5781 #define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A) 5782 5783 /* Skylake+ pipe bottom (background) color */ 5784 #define _SKL_BOTTOM_COLOR_A 0x70034 5785 #define SKL_BOTTOM_COLOR_GAMMA_ENABLE (1 << 31) 5786 #define SKL_BOTTOM_COLOR_CSC_ENABLE (1 << 30) 5787 #define SKL_BOTTOM_COLOR(pipe) _MMIO_PIPE2(pipe, _SKL_BOTTOM_COLOR_A) 5788 5789 #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028) 5790 #define PIPEB_LINE_COMPARE_INT_EN (1 << 29) 5791 #define PIPEB_HLINE_INT_EN (1 << 28) 5792 #define PIPEB_VBLANK_INT_EN (1 << 27) 5793 #define SPRITED_FLIP_DONE_INT_EN (1 << 26) 5794 #define SPRITEC_FLIP_DONE_INT_EN (1 << 25) 5795 #define PLANEB_FLIP_DONE_INT_EN (1 << 24) 5796 #define PIPE_PSR_INT_EN (1 << 22) 5797 #define PIPEA_LINE_COMPARE_INT_EN (1 << 21) 5798 #define PIPEA_HLINE_INT_EN (1 << 20) 5799 #define PIPEA_VBLANK_INT_EN (1 << 19) 5800 #define SPRITEB_FLIP_DONE_INT_EN (1 << 18) 5801 #define SPRITEA_FLIP_DONE_INT_EN (1 << 17) 5802 #define PLANEA_FLIPDONE_INT_EN (1 << 16) 5803 #define PIPEC_LINE_COMPARE_INT_EN (1 << 13) 5804 #define PIPEC_HLINE_INT_EN (1 << 12) 5805 #define PIPEC_VBLANK_INT_EN (1 << 11) 5806 #define SPRITEF_FLIPDONE_INT_EN (1 << 10) 5807 #define SPRITEE_FLIPDONE_INT_EN (1 << 9) 5808 #define PLANEC_FLIPDONE_INT_EN (1 << 8) 5809 5810 #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */ 5811 #define SPRITEF_INVALID_GTT_INT_EN (1 << 27) 5812 #define SPRITEE_INVALID_GTT_INT_EN (1 << 26) 5813 #define PLANEC_INVALID_GTT_INT_EN (1 << 25) 5814 #define CURSORC_INVALID_GTT_INT_EN (1 << 24) 5815 #define CURSORB_INVALID_GTT_INT_EN (1 << 23) 5816 #define CURSORA_INVALID_GTT_INT_EN (1 << 22) 5817 #define SPRITED_INVALID_GTT_INT_EN (1 << 21) 5818 #define SPRITEC_INVALID_GTT_INT_EN (1 << 20) 5819 #define PLANEB_INVALID_GTT_INT_EN (1 << 19) 5820 #define SPRITEB_INVALID_GTT_INT_EN (1 << 18) 5821 #define SPRITEA_INVALID_GTT_INT_EN (1 << 17) 5822 #define PLANEA_INVALID_GTT_INT_EN (1 << 16) 5823 #define DPINVGTT_EN_MASK 0xff0000 5824 #define DPINVGTT_EN_MASK_CHV 0xfff0000 5825 #define SPRITEF_INVALID_GTT_STATUS (1 << 11) 5826 #define SPRITEE_INVALID_GTT_STATUS (1 << 10) 5827 #define PLANEC_INVALID_GTT_STATUS (1 << 9) 5828 #define CURSORC_INVALID_GTT_STATUS (1 << 8) 5829 #define CURSORB_INVALID_GTT_STATUS (1 << 7) 5830 #define CURSORA_INVALID_GTT_STATUS (1 << 6) 5831 #define SPRITED_INVALID_GTT_STATUS (1 << 5) 5832 #define SPRITEC_INVALID_GTT_STATUS (1 << 4) 5833 #define PLANEB_INVALID_GTT_STATUS (1 << 3) 5834 #define SPRITEB_INVALID_GTT_STATUS (1 << 2) 5835 #define SPRITEA_INVALID_GTT_STATUS (1 << 1) 5836 #define PLANEA_INVALID_GTT_STATUS (1 << 0) 5837 #define DPINVGTT_STATUS_MASK 0xff 5838 #define DPINVGTT_STATUS_MASK_CHV 0xfff 5839 5840 #define DSPARB _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030) 5841 #define DSPARB_CSTART_MASK (0x7f << 7) 5842 #define DSPARB_CSTART_SHIFT 7 5843 #define DSPARB_BSTART_MASK (0x7f) 5844 #define DSPARB_BSTART_SHIFT 0 5845 #define DSPARB_BEND_SHIFT 9 /* on 855 */ 5846 #define DSPARB_AEND_SHIFT 0 5847 #define DSPARB_SPRITEA_SHIFT_VLV 0 5848 #define DSPARB_SPRITEA_MASK_VLV (0xff << 0) 5849 #define DSPARB_SPRITEB_SHIFT_VLV 8 5850 #define DSPARB_SPRITEB_MASK_VLV (0xff << 8) 5851 #define DSPARB_SPRITEC_SHIFT_VLV 16 5852 #define DSPARB_SPRITEC_MASK_VLV (0xff << 16) 5853 #define DSPARB_SPRITED_SHIFT_VLV 24 5854 #define DSPARB_SPRITED_MASK_VLV (0xff << 24) 5855 #define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */ 5856 #define DSPARB_SPRITEA_HI_SHIFT_VLV 0 5857 #define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0) 5858 #define DSPARB_SPRITEB_HI_SHIFT_VLV 4 5859 #define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4) 5860 #define DSPARB_SPRITEC_HI_SHIFT_VLV 8 5861 #define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8) 5862 #define DSPARB_SPRITED_HI_SHIFT_VLV 12 5863 #define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12) 5864 #define DSPARB_SPRITEE_HI_SHIFT_VLV 16 5865 #define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16) 5866 #define DSPARB_SPRITEF_HI_SHIFT_VLV 20 5867 #define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20) 5868 #define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */ 5869 #define DSPARB_SPRITEE_SHIFT_VLV 0 5870 #define DSPARB_SPRITEE_MASK_VLV (0xff << 0) 5871 #define DSPARB_SPRITEF_SHIFT_VLV 8 5872 #define DSPARB_SPRITEF_MASK_VLV (0xff << 8) 5873 5874 /* pnv/gen4/g4x/vlv/chv */ 5875 #define DSPFW1 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034) 5876 #define DSPFW_SR_SHIFT 23 5877 #define DSPFW_SR_MASK (0x1ff << 23) 5878 #define DSPFW_CURSORB_SHIFT 16 5879 #define DSPFW_CURSORB_MASK (0x3f << 16) 5880 #define DSPFW_PLANEB_SHIFT 8 5881 #define DSPFW_PLANEB_MASK (0x7f << 8) 5882 #define DSPFW_PLANEB_MASK_VLV (0xff << 8) /* vlv/chv */ 5883 #define DSPFW_PLANEA_SHIFT 0 5884 #define DSPFW_PLANEA_MASK (0x7f << 0) 5885 #define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */ 5886 #define DSPFW2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038) 5887 #define DSPFW_FBC_SR_EN (1 << 31) /* g4x */ 5888 #define DSPFW_FBC_SR_SHIFT 28 5889 #define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */ 5890 #define DSPFW_FBC_HPLL_SR_SHIFT 24 5891 #define DSPFW_FBC_HPLL_SR_MASK (0xf << 24) /* g4x */ 5892 #define DSPFW_SPRITEB_SHIFT (16) 5893 #define DSPFW_SPRITEB_MASK (0x7f << 16) /* g4x */ 5894 #define DSPFW_SPRITEB_MASK_VLV (0xff << 16) /* vlv/chv */ 5895 #define DSPFW_CURSORA_SHIFT 8 5896 #define DSPFW_CURSORA_MASK (0x3f << 8) 5897 #define DSPFW_PLANEC_OLD_SHIFT 0 5898 #define DSPFW_PLANEC_OLD_MASK (0x7f << 0) /* pre-gen4 sprite C */ 5899 #define DSPFW_SPRITEA_SHIFT 0 5900 #define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */ 5901 #define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */ 5902 #define DSPFW3 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c) 5903 #define DSPFW_HPLL_SR_EN (1 << 31) 5904 #define PINEVIEW_SELF_REFRESH_EN (1 << 30) 5905 #define DSPFW_CURSOR_SR_SHIFT 24 5906 #define DSPFW_CURSOR_SR_MASK (0x3f << 24) 5907 #define DSPFW_HPLL_CURSOR_SHIFT 16 5908 #define DSPFW_HPLL_CURSOR_MASK (0x3f << 16) 5909 #define DSPFW_HPLL_SR_SHIFT 0 5910 #define DSPFW_HPLL_SR_MASK (0x1ff << 0) 5911 5912 /* vlv/chv */ 5913 #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070) 5914 #define DSPFW_SPRITEB_WM1_SHIFT 16 5915 #define DSPFW_SPRITEB_WM1_MASK (0xff << 16) 5916 #define DSPFW_CURSORA_WM1_SHIFT 8 5917 #define DSPFW_CURSORA_WM1_MASK (0x3f << 8) 5918 #define DSPFW_SPRITEA_WM1_SHIFT 0 5919 #define DSPFW_SPRITEA_WM1_MASK (0xff << 0) 5920 #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074) 5921 #define DSPFW_PLANEB_WM1_SHIFT 24 5922 #define DSPFW_PLANEB_WM1_MASK (0xff << 24) 5923 #define DSPFW_PLANEA_WM1_SHIFT 16 5924 #define DSPFW_PLANEA_WM1_MASK (0xff << 16) 5925 #define DSPFW_CURSORB_WM1_SHIFT 8 5926 #define DSPFW_CURSORB_WM1_MASK (0x3f << 8) 5927 #define DSPFW_CURSOR_SR_WM1_SHIFT 0 5928 #define DSPFW_CURSOR_SR_WM1_MASK (0x3f << 0) 5929 #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078) 5930 #define DSPFW_SR_WM1_SHIFT 0 5931 #define DSPFW_SR_WM1_MASK (0x1ff << 0) 5932 #define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c) 5933 #define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */ 5934 #define DSPFW_SPRITED_WM1_SHIFT 24 5935 #define DSPFW_SPRITED_WM1_MASK (0xff << 24) 5936 #define DSPFW_SPRITED_SHIFT 16 5937 #define DSPFW_SPRITED_MASK_VLV (0xff << 16) 5938 #define DSPFW_SPRITEC_WM1_SHIFT 8 5939 #define DSPFW_SPRITEC_WM1_MASK (0xff << 8) 5940 #define DSPFW_SPRITEC_SHIFT 0 5941 #define DSPFW_SPRITEC_MASK_VLV (0xff << 0) 5942 #define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8) 5943 #define DSPFW_SPRITEF_WM1_SHIFT 24 5944 #define DSPFW_SPRITEF_WM1_MASK (0xff << 24) 5945 #define DSPFW_SPRITEF_SHIFT 16 5946 #define DSPFW_SPRITEF_MASK_VLV (0xff << 16) 5947 #define DSPFW_SPRITEE_WM1_SHIFT 8 5948 #define DSPFW_SPRITEE_WM1_MASK (0xff << 8) 5949 #define DSPFW_SPRITEE_SHIFT 0 5950 #define DSPFW_SPRITEE_MASK_VLV (0xff << 0) 5951 #define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */ 5952 #define DSPFW_PLANEC_WM1_SHIFT 24 5953 #define DSPFW_PLANEC_WM1_MASK (0xff << 24) 5954 #define DSPFW_PLANEC_SHIFT 16 5955 #define DSPFW_PLANEC_MASK_VLV (0xff << 16) 5956 #define DSPFW_CURSORC_WM1_SHIFT 8 5957 #define DSPFW_CURSORC_WM1_MASK (0x3f << 16) 5958 #define DSPFW_CURSORC_SHIFT 0 5959 #define DSPFW_CURSORC_MASK (0x3f << 0) 5960 5961 /* vlv/chv high order bits */ 5962 #define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064) 5963 #define DSPFW_SR_HI_SHIFT 24 5964 #define DSPFW_SR_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */ 5965 #define DSPFW_SPRITEF_HI_SHIFT 23 5966 #define DSPFW_SPRITEF_HI_MASK (1 << 23) 5967 #define DSPFW_SPRITEE_HI_SHIFT 22 5968 #define DSPFW_SPRITEE_HI_MASK (1 << 22) 5969 #define DSPFW_PLANEC_HI_SHIFT 21 5970 #define DSPFW_PLANEC_HI_MASK (1 << 21) 5971 #define DSPFW_SPRITED_HI_SHIFT 20 5972 #define DSPFW_SPRITED_HI_MASK (1 << 20) 5973 #define DSPFW_SPRITEC_HI_SHIFT 16 5974 #define DSPFW_SPRITEC_HI_MASK (1 << 16) 5975 #define DSPFW_PLANEB_HI_SHIFT 12 5976 #define DSPFW_PLANEB_HI_MASK (1 << 12) 5977 #define DSPFW_SPRITEB_HI_SHIFT 8 5978 #define DSPFW_SPRITEB_HI_MASK (1 << 8) 5979 #define DSPFW_SPRITEA_HI_SHIFT 4 5980 #define DSPFW_SPRITEA_HI_MASK (1 << 4) 5981 #define DSPFW_PLANEA_HI_SHIFT 0 5982 #define DSPFW_PLANEA_HI_MASK (1 << 0) 5983 #define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068) 5984 #define DSPFW_SR_WM1_HI_SHIFT 24 5985 #define DSPFW_SR_WM1_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */ 5986 #define DSPFW_SPRITEF_WM1_HI_SHIFT 23 5987 #define DSPFW_SPRITEF_WM1_HI_MASK (1 << 23) 5988 #define DSPFW_SPRITEE_WM1_HI_SHIFT 22 5989 #define DSPFW_SPRITEE_WM1_HI_MASK (1 << 22) 5990 #define DSPFW_PLANEC_WM1_HI_SHIFT 21 5991 #define DSPFW_PLANEC_WM1_HI_MASK (1 << 21) 5992 #define DSPFW_SPRITED_WM1_HI_SHIFT 20 5993 #define DSPFW_SPRITED_WM1_HI_MASK (1 << 20) 5994 #define DSPFW_SPRITEC_WM1_HI_SHIFT 16 5995 #define DSPFW_SPRITEC_WM1_HI_MASK (1 << 16) 5996 #define DSPFW_PLANEB_WM1_HI_SHIFT 12 5997 #define DSPFW_PLANEB_WM1_HI_MASK (1 << 12) 5998 #define DSPFW_SPRITEB_WM1_HI_SHIFT 8 5999 #define DSPFW_SPRITEB_WM1_HI_MASK (1 << 8) 6000 #define DSPFW_SPRITEA_WM1_HI_SHIFT 4 6001 #define DSPFW_SPRITEA_WM1_HI_MASK (1 << 4) 6002 #define DSPFW_PLANEA_WM1_HI_SHIFT 0 6003 #define DSPFW_PLANEA_WM1_HI_MASK (1 << 0) 6004 6005 /* drain latency register values*/ 6006 #define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe)) 6007 #define DDL_CURSOR_SHIFT 24 6008 #define DDL_SPRITE_SHIFT(sprite) (8 + 8 * (sprite)) 6009 #define DDL_PLANE_SHIFT 0 6010 #define DDL_PRECISION_HIGH (1 << 7) 6011 #define DDL_PRECISION_LOW (0 << 7) 6012 #define DRAIN_LATENCY_MASK 0x7f 6013 6014 #define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400) 6015 #define CBR_PND_DEADLINE_DISABLE (1 << 31) 6016 #define CBR_PWM_CLOCK_MUX_SELECT (1 << 30) 6017 6018 #define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450) 6019 #define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11)) /* pipes B and C */ 6020 6021 /* FIFO watermark sizes etc */ 6022 #define G4X_FIFO_LINE_SIZE 64 6023 #define I915_FIFO_LINE_SIZE 64 6024 #define I830_FIFO_LINE_SIZE 32 6025 6026 #define VALLEYVIEW_FIFO_SIZE 255 6027 #define G4X_FIFO_SIZE 127 6028 #define I965_FIFO_SIZE 512 6029 #define I945_FIFO_SIZE 127 6030 #define I915_FIFO_SIZE 95 6031 #define I855GM_FIFO_SIZE 127 /* In cachelines */ 6032 #define I830_FIFO_SIZE 95 6033 6034 #define VALLEYVIEW_MAX_WM 0xff 6035 #define G4X_MAX_WM 0x3f 6036 #define I915_MAX_WM 0x3f 6037 6038 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ 6039 #define PINEVIEW_FIFO_LINE_SIZE 64 6040 #define PINEVIEW_MAX_WM 0x1ff 6041 #define PINEVIEW_DFT_WM 0x3f 6042 #define PINEVIEW_DFT_HPLLOFF_WM 0 6043 #define PINEVIEW_GUARD_WM 10 6044 #define PINEVIEW_CURSOR_FIFO 64 6045 #define PINEVIEW_CURSOR_MAX_WM 0x3f 6046 #define PINEVIEW_CURSOR_DFT_WM 0 6047 #define PINEVIEW_CURSOR_GUARD_WM 5 6048 6049 #define VALLEYVIEW_CURSOR_MAX_WM 64 6050 #define I965_CURSOR_FIFO 64 6051 #define I965_CURSOR_MAX_WM 32 6052 #define I965_CURSOR_DFT_WM 8 6053 6054 /* Watermark register definitions for SKL */ 6055 #define _CUR_WM_A_0 0x70140 6056 #define _CUR_WM_B_0 0x71140 6057 #define _PLANE_WM_1_A_0 0x70240 6058 #define _PLANE_WM_1_B_0 0x71240 6059 #define _PLANE_WM_2_A_0 0x70340 6060 #define _PLANE_WM_2_B_0 0x71340 6061 #define _PLANE_WM_TRANS_1_A_0 0x70268 6062 #define _PLANE_WM_TRANS_1_B_0 0x71268 6063 #define _PLANE_WM_TRANS_2_A_0 0x70368 6064 #define _PLANE_WM_TRANS_2_B_0 0x71368 6065 #define _CUR_WM_TRANS_A_0 0x70168 6066 #define _CUR_WM_TRANS_B_0 0x71168 6067 #define PLANE_WM_EN (1 << 31) 6068 #define PLANE_WM_IGNORE_LINES (1 << 30) 6069 #define PLANE_WM_LINES_SHIFT 14 6070 #define PLANE_WM_LINES_MASK 0x1f 6071 #define PLANE_WM_BLOCKS_MASK 0x7ff /* skl+: 10 bits, icl+ 11 bits */ 6072 6073 #define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0) 6074 #define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level))) 6075 #define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0) 6076 6077 #define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0) 6078 #define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0) 6079 #define _PLANE_WM_BASE(pipe, plane) \ 6080 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe)) 6081 #define PLANE_WM(pipe, plane, level) \ 6082 _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level))) 6083 #define _PLANE_WM_TRANS_1(pipe) \ 6084 _PIPE(pipe, _PLANE_WM_TRANS_1_A_0, _PLANE_WM_TRANS_1_B_0) 6085 #define _PLANE_WM_TRANS_2(pipe) \ 6086 _PIPE(pipe, _PLANE_WM_TRANS_2_A_0, _PLANE_WM_TRANS_2_B_0) 6087 #define PLANE_WM_TRANS(pipe, plane) \ 6088 _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe))) 6089 6090 /* define the Watermark register on Ironlake */ 6091 #define WM0_PIPEA_ILK _MMIO(0x45100) 6092 #define WM0_PIPE_PLANE_MASK (0xffff << 16) 6093 #define WM0_PIPE_PLANE_SHIFT 16 6094 #define WM0_PIPE_SPRITE_MASK (0xff << 8) 6095 #define WM0_PIPE_SPRITE_SHIFT 8 6096 #define WM0_PIPE_CURSOR_MASK (0xff) 6097 6098 #define WM0_PIPEB_ILK _MMIO(0x45104) 6099 #define WM0_PIPEC_IVB _MMIO(0x45200) 6100 #define WM1_LP_ILK _MMIO(0x45108) 6101 #define WM1_LP_SR_EN (1 << 31) 6102 #define WM1_LP_LATENCY_SHIFT 24 6103 #define WM1_LP_LATENCY_MASK (0x7f << 24) 6104 #define WM1_LP_FBC_MASK (0xf << 20) 6105 #define WM1_LP_FBC_SHIFT 20 6106 #define WM1_LP_FBC_SHIFT_BDW 19 6107 #define WM1_LP_SR_MASK (0x7ff << 8) 6108 #define WM1_LP_SR_SHIFT 8 6109 #define WM1_LP_CURSOR_MASK (0xff) 6110 #define WM2_LP_ILK _MMIO(0x4510c) 6111 #define WM2_LP_EN (1 << 31) 6112 #define WM3_LP_ILK _MMIO(0x45110) 6113 #define WM3_LP_EN (1 << 31) 6114 #define WM1S_LP_ILK _MMIO(0x45120) 6115 #define WM2S_LP_IVB _MMIO(0x45124) 6116 #define WM3S_LP_IVB _MMIO(0x45128) 6117 #define WM1S_LP_EN (1 << 31) 6118 6119 #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \ 6120 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \ 6121 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur)) 6122 6123 /* Memory latency timer register */ 6124 #define MLTR_ILK _MMIO(0x11222) 6125 #define MLTR_WM1_SHIFT 0 6126 #define MLTR_WM2_SHIFT 8 6127 /* the unit of memory self-refresh latency time is 0.5us */ 6128 #define ILK_SRLT_MASK 0x3f 6129 6130 6131 /* the address where we get all kinds of latency value */ 6132 #define SSKPD _MMIO(0x5d10) 6133 #define SSKPD_WM_MASK 0x3f 6134 #define SSKPD_WM0_SHIFT 0 6135 #define SSKPD_WM1_SHIFT 8 6136 #define SSKPD_WM2_SHIFT 16 6137 #define SSKPD_WM3_SHIFT 24 6138 6139 /* 6140 * The two pipe frame counter registers are not synchronized, so 6141 * reading a stable value is somewhat tricky. The following code 6142 * should work: 6143 * 6144 * do { 6145 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 6146 * PIPE_FRAME_HIGH_SHIFT; 6147 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> 6148 * PIPE_FRAME_LOW_SHIFT); 6149 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 6150 * PIPE_FRAME_HIGH_SHIFT); 6151 * } while (high1 != high2); 6152 * frame = (high1 << 8) | low1; 6153 */ 6154 #define _PIPEAFRAMEHIGH 0x70040 6155 #define PIPE_FRAME_HIGH_MASK 0x0000ffff 6156 #define PIPE_FRAME_HIGH_SHIFT 0 6157 #define _PIPEAFRAMEPIXEL 0x70044 6158 #define PIPE_FRAME_LOW_MASK 0xff000000 6159 #define PIPE_FRAME_LOW_SHIFT 24 6160 #define PIPE_PIXEL_MASK 0x00ffffff 6161 #define PIPE_PIXEL_SHIFT 0 6162 /* GM45+ just has to be different */ 6163 #define _PIPEA_FRMCOUNT_G4X 0x70040 6164 #define _PIPEA_FLIPCOUNT_G4X 0x70044 6165 #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X) 6166 #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X) 6167 6168 /* Cursor A & B regs */ 6169 #define _CURACNTR 0x70080 6170 /* Old style CUR*CNTR flags (desktop 8xx) */ 6171 #define CURSOR_ENABLE 0x80000000 6172 #define CURSOR_GAMMA_ENABLE 0x40000000 6173 #define CURSOR_STRIDE_SHIFT 28 6174 #define CURSOR_STRIDE(x) ((ffs(x) - 9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */ 6175 #define CURSOR_FORMAT_SHIFT 24 6176 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) 6177 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) 6178 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) 6179 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) 6180 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) 6181 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) 6182 /* New style CUR*CNTR flags */ 6183 #define MCURSOR_MODE 0x27 6184 #define MCURSOR_MODE_DISABLE 0x00 6185 #define MCURSOR_MODE_128_32B_AX 0x02 6186 #define MCURSOR_MODE_256_32B_AX 0x03 6187 #define MCURSOR_MODE_64_32B_AX 0x07 6188 #define MCURSOR_MODE_128_ARGB_AX ((1 << 5) | MCURSOR_MODE_128_32B_AX) 6189 #define MCURSOR_MODE_256_ARGB_AX ((1 << 5) | MCURSOR_MODE_256_32B_AX) 6190 #define MCURSOR_MODE_64_ARGB_AX ((1 << 5) | MCURSOR_MODE_64_32B_AX) 6191 #define MCURSOR_PIPE_SELECT_MASK (0x3 << 28) 6192 #define MCURSOR_PIPE_SELECT_SHIFT 28 6193 #define MCURSOR_PIPE_SELECT(pipe) ((pipe) << 28) 6194 #define MCURSOR_GAMMA_ENABLE (1 << 26) 6195 #define MCURSOR_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */ 6196 #define MCURSOR_ROTATE_180 (1 << 15) 6197 #define MCURSOR_TRICKLE_FEED_DISABLE (1 << 14) 6198 #define _CURABASE 0x70084 6199 #define _CURAPOS 0x70088 6200 #define CURSOR_POS_MASK 0x007FF 6201 #define CURSOR_POS_SIGN 0x8000 6202 #define CURSOR_X_SHIFT 0 6203 #define CURSOR_Y_SHIFT 16 6204 #define CURSIZE _MMIO(0x700a0) /* 845/865 */ 6205 #define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */ 6206 #define CUR_FBC_CTL_EN (1 << 31) 6207 #define _CURASURFLIVE 0x700ac /* g4x+ */ 6208 #define _CURBCNTR 0x700c0 6209 #define _CURBBASE 0x700c4 6210 #define _CURBPOS 0x700c8 6211 6212 #define _CURBCNTR_IVB 0x71080 6213 #define _CURBBASE_IVB 0x71084 6214 #define _CURBPOS_IVB 0x71088 6215 6216 #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR) 6217 #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE) 6218 #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS) 6219 #define CUR_FBC_CTL(pipe) _CURSOR2(pipe, _CUR_FBC_CTL_A) 6220 #define CURSURFLIVE(pipe) _CURSOR2(pipe, _CURASURFLIVE) 6221 6222 #define CURSOR_A_OFFSET 0x70080 6223 #define CURSOR_B_OFFSET 0x700c0 6224 #define CHV_CURSOR_C_OFFSET 0x700e0 6225 #define IVB_CURSOR_B_OFFSET 0x71080 6226 #define IVB_CURSOR_C_OFFSET 0x72080 6227 6228 /* Display A control */ 6229 #define _DSPACNTR 0x70180 6230 #define DISPLAY_PLANE_ENABLE (1 << 31) 6231 #define DISPLAY_PLANE_DISABLE 0 6232 #define DISPPLANE_GAMMA_ENABLE (1 << 30) 6233 #define DISPPLANE_GAMMA_DISABLE 0 6234 #define DISPPLANE_PIXFORMAT_MASK (0xf << 26) 6235 #define DISPPLANE_YUV422 (0x0 << 26) 6236 #define DISPPLANE_8BPP (0x2 << 26) 6237 #define DISPPLANE_BGRA555 (0x3 << 26) 6238 #define DISPPLANE_BGRX555 (0x4 << 26) 6239 #define DISPPLANE_BGRX565 (0x5 << 26) 6240 #define DISPPLANE_BGRX888 (0x6 << 26) 6241 #define DISPPLANE_BGRA888 (0x7 << 26) 6242 #define DISPPLANE_RGBX101010 (0x8 << 26) 6243 #define DISPPLANE_RGBA101010 (0x9 << 26) 6244 #define DISPPLANE_BGRX101010 (0xa << 26) 6245 #define DISPPLANE_RGBX161616 (0xc << 26) 6246 #define DISPPLANE_RGBX888 (0xe << 26) 6247 #define DISPPLANE_RGBA888 (0xf << 26) 6248 #define DISPPLANE_STEREO_ENABLE (1 << 25) 6249 #define DISPPLANE_STEREO_DISABLE 0 6250 #define DISPPLANE_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */ 6251 #define DISPPLANE_SEL_PIPE_SHIFT 24 6252 #define DISPPLANE_SEL_PIPE_MASK (3 << DISPPLANE_SEL_PIPE_SHIFT) 6253 #define DISPPLANE_SEL_PIPE(pipe) ((pipe) << DISPPLANE_SEL_PIPE_SHIFT) 6254 #define DISPPLANE_SRC_KEY_ENABLE (1 << 22) 6255 #define DISPPLANE_SRC_KEY_DISABLE 0 6256 #define DISPPLANE_LINE_DOUBLE (1 << 20) 6257 #define DISPPLANE_NO_LINE_DOUBLE 0 6258 #define DISPPLANE_STEREO_POLARITY_FIRST 0 6259 #define DISPPLANE_STEREO_POLARITY_SECOND (1 << 18) 6260 #define DISPPLANE_ALPHA_PREMULTIPLY (1 << 16) /* CHV pipe B */ 6261 #define DISPPLANE_ROTATE_180 (1 << 15) 6262 #define DISPPLANE_TRICKLE_FEED_DISABLE (1 << 14) /* Ironlake */ 6263 #define DISPPLANE_TILED (1 << 10) 6264 #define DISPPLANE_MIRROR (1 << 8) /* CHV pipe B */ 6265 #define _DSPAADDR 0x70184 6266 #define _DSPASTRIDE 0x70188 6267 #define _DSPAPOS 0x7018C /* reserved */ 6268 #define _DSPASIZE 0x70190 6269 #define _DSPASURF 0x7019C /* 965+ only */ 6270 #define _DSPATILEOFF 0x701A4 /* 965+ only */ 6271 #define _DSPAOFFSET 0x701A4 /* HSW */ 6272 #define _DSPASURFLIVE 0x701AC 6273 6274 #define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR) 6275 #define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR) 6276 #define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE) 6277 #define DSPPOS(plane) _MMIO_PIPE2(plane, _DSPAPOS) 6278 #define DSPSIZE(plane) _MMIO_PIPE2(plane, _DSPASIZE) 6279 #define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF) 6280 #define DSPTILEOFF(plane) _MMIO_PIPE2(plane, _DSPATILEOFF) 6281 #define DSPLINOFF(plane) DSPADDR(plane) 6282 #define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET) 6283 #define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE) 6284 6285 /* CHV pipe B blender and primary plane */ 6286 #define _CHV_BLEND_A 0x60a00 6287 #define CHV_BLEND_LEGACY (0 << 30) 6288 #define CHV_BLEND_ANDROID (1 << 30) 6289 #define CHV_BLEND_MPO (2 << 30) 6290 #define CHV_BLEND_MASK (3 << 30) 6291 #define _CHV_CANVAS_A 0x60a04 6292 #define _PRIMPOS_A 0x60a08 6293 #define _PRIMSIZE_A 0x60a0c 6294 #define _PRIMCNSTALPHA_A 0x60a10 6295 #define PRIM_CONST_ALPHA_ENABLE (1 << 31) 6296 6297 #define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A) 6298 #define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A) 6299 #define PRIMPOS(plane) _MMIO_TRANS2(plane, _PRIMPOS_A) 6300 #define PRIMSIZE(plane) _MMIO_TRANS2(plane, _PRIMSIZE_A) 6301 #define PRIMCNSTALPHA(plane) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A) 6302 6303 /* Display/Sprite base address macros */ 6304 #define DISP_BASEADDR_MASK (0xfffff000) 6305 #define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK) 6306 #define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK) 6307 6308 /* 6309 * VBIOS flags 6310 * gen2: 6311 * [00:06] alm,mgm 6312 * [10:16] all 6313 * [30:32] alm,mgm 6314 * gen3+: 6315 * [00:0f] all 6316 * [10:1f] all 6317 * [30:32] all 6318 */ 6319 #define SWF0(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4) 6320 #define SWF1(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4) 6321 #define SWF3(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4) 6322 #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4) 6323 6324 /* Pipe B */ 6325 #define _PIPEBDSL (DISPLAY_MMIO_BASE(dev_priv) + 0x71000) 6326 #define _PIPEBCONF (DISPLAY_MMIO_BASE(dev_priv) + 0x71008) 6327 #define _PIPEBSTAT (DISPLAY_MMIO_BASE(dev_priv) + 0x71024) 6328 #define _PIPEBFRAMEHIGH 0x71040 6329 #define _PIPEBFRAMEPIXEL 0x71044 6330 #define _PIPEB_FRMCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71040) 6331 #define _PIPEB_FLIPCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71044) 6332 6333 6334 /* Display B control */ 6335 #define _DSPBCNTR (DISPLAY_MMIO_BASE(dev_priv) + 0x71180) 6336 #define DISPPLANE_ALPHA_TRANS_ENABLE (1 << 15) 6337 #define DISPPLANE_ALPHA_TRANS_DISABLE 0 6338 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 6339 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 6340 #define _DSPBADDR (DISPLAY_MMIO_BASE(dev_priv) + 0x71184) 6341 #define _DSPBSTRIDE (DISPLAY_MMIO_BASE(dev_priv) + 0x71188) 6342 #define _DSPBPOS (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C) 6343 #define _DSPBSIZE (DISPLAY_MMIO_BASE(dev_priv) + 0x71190) 6344 #define _DSPBSURF (DISPLAY_MMIO_BASE(dev_priv) + 0x7119C) 6345 #define _DSPBTILEOFF (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4) 6346 #define _DSPBOFFSET (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4) 6347 #define _DSPBSURFLIVE (DISPLAY_MMIO_BASE(dev_priv) + 0x711AC) 6348 6349 /* ICL DSI 0 and 1 */ 6350 #define _PIPEDSI0CONF 0x7b008 6351 #define _PIPEDSI1CONF 0x7b808 6352 6353 /* Sprite A control */ 6354 #define _DVSACNTR 0x72180 6355 #define DVS_ENABLE (1 << 31) 6356 #define DVS_GAMMA_ENABLE (1 << 30) 6357 #define DVS_YUV_RANGE_CORRECTION_DISABLE (1 << 27) 6358 #define DVS_PIXFORMAT_MASK (3 << 25) 6359 #define DVS_FORMAT_YUV422 (0 << 25) 6360 #define DVS_FORMAT_RGBX101010 (1 << 25) 6361 #define DVS_FORMAT_RGBX888 (2 << 25) 6362 #define DVS_FORMAT_RGBX161616 (3 << 25) 6363 #define DVS_PIPE_CSC_ENABLE (1 << 24) 6364 #define DVS_SOURCE_KEY (1 << 22) 6365 #define DVS_RGB_ORDER_XBGR (1 << 20) 6366 #define DVS_YUV_FORMAT_BT709 (1 << 18) 6367 #define DVS_YUV_BYTE_ORDER_MASK (3 << 16) 6368 #define DVS_YUV_ORDER_YUYV (0 << 16) 6369 #define DVS_YUV_ORDER_UYVY (1 << 16) 6370 #define DVS_YUV_ORDER_YVYU (2 << 16) 6371 #define DVS_YUV_ORDER_VYUY (3 << 16) 6372 #define DVS_ROTATE_180 (1 << 15) 6373 #define DVS_DEST_KEY (1 << 2) 6374 #define DVS_TRICKLE_FEED_DISABLE (1 << 14) 6375 #define DVS_TILED (1 << 10) 6376 #define _DVSALINOFF 0x72184 6377 #define _DVSASTRIDE 0x72188 6378 #define _DVSAPOS 0x7218c 6379 #define _DVSASIZE 0x72190 6380 #define _DVSAKEYVAL 0x72194 6381 #define _DVSAKEYMSK 0x72198 6382 #define _DVSASURF 0x7219c 6383 #define _DVSAKEYMAXVAL 0x721a0 6384 #define _DVSATILEOFF 0x721a4 6385 #define _DVSASURFLIVE 0x721ac 6386 #define _DVSASCALE 0x72204 6387 #define DVS_SCALE_ENABLE (1 << 31) 6388 #define DVS_FILTER_MASK (3 << 29) 6389 #define DVS_FILTER_MEDIUM (0 << 29) 6390 #define DVS_FILTER_ENHANCING (1 << 29) 6391 #define DVS_FILTER_SOFTENING (2 << 29) 6392 #define DVS_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */ 6393 #define DVS_VERTICAL_OFFSET_ENABLE (1 << 27) 6394 #define _DVSAGAMC 0x72300 6395 6396 #define _DVSBCNTR 0x73180 6397 #define _DVSBLINOFF 0x73184 6398 #define _DVSBSTRIDE 0x73188 6399 #define _DVSBPOS 0x7318c 6400 #define _DVSBSIZE 0x73190 6401 #define _DVSBKEYVAL 0x73194 6402 #define _DVSBKEYMSK 0x73198 6403 #define _DVSBSURF 0x7319c 6404 #define _DVSBKEYMAXVAL 0x731a0 6405 #define _DVSBTILEOFF 0x731a4 6406 #define _DVSBSURFLIVE 0x731ac 6407 #define _DVSBSCALE 0x73204 6408 #define _DVSBGAMC 0x73300 6409 6410 #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR) 6411 #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) 6412 #define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) 6413 #define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS) 6414 #define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF) 6415 #define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) 6416 #define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE) 6417 #define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE) 6418 #define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) 6419 #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) 6420 #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) 6421 #define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) 6422 6423 #define _SPRA_CTL 0x70280 6424 #define SPRITE_ENABLE (1 << 31) 6425 #define SPRITE_GAMMA_ENABLE (1 << 30) 6426 #define SPRITE_YUV_RANGE_CORRECTION_DISABLE (1 << 28) 6427 #define SPRITE_PIXFORMAT_MASK (7 << 25) 6428 #define SPRITE_FORMAT_YUV422 (0 << 25) 6429 #define SPRITE_FORMAT_RGBX101010 (1 << 25) 6430 #define SPRITE_FORMAT_RGBX888 (2 << 25) 6431 #define SPRITE_FORMAT_RGBX161616 (3 << 25) 6432 #define SPRITE_FORMAT_YUV444 (4 << 25) 6433 #define SPRITE_FORMAT_XR_BGR101010 (5 << 25) /* Extended range */ 6434 #define SPRITE_PIPE_CSC_ENABLE (1 << 24) 6435 #define SPRITE_SOURCE_KEY (1 << 22) 6436 #define SPRITE_RGB_ORDER_RGBX (1 << 20) /* only for 888 and 161616 */ 6437 #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1 << 19) 6438 #define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18) /* 0 is BT601 */ 6439 #define SPRITE_YUV_BYTE_ORDER_MASK (3 << 16) 6440 #define SPRITE_YUV_ORDER_YUYV (0 << 16) 6441 #define SPRITE_YUV_ORDER_UYVY (1 << 16) 6442 #define SPRITE_YUV_ORDER_YVYU (2 << 16) 6443 #define SPRITE_YUV_ORDER_VYUY (3 << 16) 6444 #define SPRITE_ROTATE_180 (1 << 15) 6445 #define SPRITE_TRICKLE_FEED_DISABLE (1 << 14) 6446 #define SPRITE_INT_GAMMA_ENABLE (1 << 13) 6447 #define SPRITE_TILED (1 << 10) 6448 #define SPRITE_DEST_KEY (1 << 2) 6449 #define _SPRA_LINOFF 0x70284 6450 #define _SPRA_STRIDE 0x70288 6451 #define _SPRA_POS 0x7028c 6452 #define _SPRA_SIZE 0x70290 6453 #define _SPRA_KEYVAL 0x70294 6454 #define _SPRA_KEYMSK 0x70298 6455 #define _SPRA_SURF 0x7029c 6456 #define _SPRA_KEYMAX 0x702a0 6457 #define _SPRA_TILEOFF 0x702a4 6458 #define _SPRA_OFFSET 0x702a4 6459 #define _SPRA_SURFLIVE 0x702ac 6460 #define _SPRA_SCALE 0x70304 6461 #define SPRITE_SCALE_ENABLE (1 << 31) 6462 #define SPRITE_FILTER_MASK (3 << 29) 6463 #define SPRITE_FILTER_MEDIUM (0 << 29) 6464 #define SPRITE_FILTER_ENHANCING (1 << 29) 6465 #define SPRITE_FILTER_SOFTENING (2 << 29) 6466 #define SPRITE_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */ 6467 #define SPRITE_VERTICAL_OFFSET_ENABLE (1 << 27) 6468 #define _SPRA_GAMC 0x70400 6469 6470 #define _SPRB_CTL 0x71280 6471 #define _SPRB_LINOFF 0x71284 6472 #define _SPRB_STRIDE 0x71288 6473 #define _SPRB_POS 0x7128c 6474 #define _SPRB_SIZE 0x71290 6475 #define _SPRB_KEYVAL 0x71294 6476 #define _SPRB_KEYMSK 0x71298 6477 #define _SPRB_SURF 0x7129c 6478 #define _SPRB_KEYMAX 0x712a0 6479 #define _SPRB_TILEOFF 0x712a4 6480 #define _SPRB_OFFSET 0x712a4 6481 #define _SPRB_SURFLIVE 0x712ac 6482 #define _SPRB_SCALE 0x71304 6483 #define _SPRB_GAMC 0x71400 6484 6485 #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL) 6486 #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) 6487 #define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) 6488 #define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS) 6489 #define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) 6490 #define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) 6491 #define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) 6492 #define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF) 6493 #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) 6494 #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) 6495 #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) 6496 #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) 6497 #define SPRGAMC(pipe) _MMIO_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) 6498 #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) 6499 6500 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180) 6501 #define SP_ENABLE (1 << 31) 6502 #define SP_GAMMA_ENABLE (1 << 30) 6503 #define SP_PIXFORMAT_MASK (0xf << 26) 6504 #define SP_FORMAT_YUV422 (0 << 26) 6505 #define SP_FORMAT_BGR565 (5 << 26) 6506 #define SP_FORMAT_BGRX8888 (6 << 26) 6507 #define SP_FORMAT_BGRA8888 (7 << 26) 6508 #define SP_FORMAT_RGBX1010102 (8 << 26) 6509 #define SP_FORMAT_RGBA1010102 (9 << 26) 6510 #define SP_FORMAT_RGBX8888 (0xe << 26) 6511 #define SP_FORMAT_RGBA8888 (0xf << 26) 6512 #define SP_ALPHA_PREMULTIPLY (1 << 23) /* CHV pipe B */ 6513 #define SP_SOURCE_KEY (1 << 22) 6514 #define SP_YUV_FORMAT_BT709 (1 << 18) 6515 #define SP_YUV_BYTE_ORDER_MASK (3 << 16) 6516 #define SP_YUV_ORDER_YUYV (0 << 16) 6517 #define SP_YUV_ORDER_UYVY (1 << 16) 6518 #define SP_YUV_ORDER_YVYU (2 << 16) 6519 #define SP_YUV_ORDER_VYUY (3 << 16) 6520 #define SP_ROTATE_180 (1 << 15) 6521 #define SP_TILED (1 << 10) 6522 #define SP_MIRROR (1 << 8) /* CHV pipe B */ 6523 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184) 6524 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188) 6525 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c) 6526 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190) 6527 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194) 6528 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198) 6529 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c) 6530 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0) 6531 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4) 6532 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8) 6533 #define SP_CONST_ALPHA_ENABLE (1 << 31) 6534 #define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0) 6535 #define SP_CONTRAST(x) ((x) << 18) /* u3.6 */ 6536 #define SP_BRIGHTNESS(x) ((x) & 0xff) /* s8 */ 6537 #define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4) 6538 #define SP_SH_SIN(x) (((x) & 0x7ff) << 16) /* s4.7 */ 6539 #define SP_SH_COS(x) (x) /* u3.7 */ 6540 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4) 6541 6542 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280) 6543 #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284) 6544 #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288) 6545 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c) 6546 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290) 6547 #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294) 6548 #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298) 6549 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c) 6550 #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0) 6551 #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4) 6552 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8) 6553 #define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0) 6554 #define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4) 6555 #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4) 6556 6557 #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \ 6558 _MMIO_PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b)) 6559 6560 #define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR) 6561 #define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF) 6562 #define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE) 6563 #define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS) 6564 #define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE) 6565 #define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL) 6566 #define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK) 6567 #define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF) 6568 #define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL) 6569 #define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF) 6570 #define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA) 6571 #define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0) 6572 #define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1) 6573 #define SPGAMC(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) 6574 6575 /* 6576 * CHV pipe B sprite CSC 6577 * 6578 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff| 6579 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff| 6580 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff| 6581 */ 6582 #define _MMIO_CHV_SPCSC(plane_id, reg) \ 6583 _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg)) 6584 6585 #define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900) 6586 #define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904) 6587 #define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908) 6588 #define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */ 6589 #define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */ 6590 6591 #define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c) 6592 #define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910) 6593 #define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914) 6594 #define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918) 6595 #define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c) 6596 #define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */ 6597 #define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */ 6598 6599 #define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920) 6600 #define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924) 6601 #define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928) 6602 #define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */ 6603 #define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */ 6604 6605 #define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c) 6606 #define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930) 6607 #define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934) 6608 #define SPCSC_OMAX(x) ((x) << 16) /* u10 */ 6609 #define SPCSC_OMIN(x) ((x) << 0) /* u10 */ 6610 6611 /* Skylake plane registers */ 6612 6613 #define _PLANE_CTL_1_A 0x70180 6614 #define _PLANE_CTL_2_A 0x70280 6615 #define _PLANE_CTL_3_A 0x70380 6616 #define PLANE_CTL_ENABLE (1 << 31) 6617 #define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-GLK */ 6618 #define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE (1 << 28) 6619 /* 6620 * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition 6621 * expanded to include bit 23 as well. However, the shift-24 based values 6622 * correctly map to the same formats in ICL, as long as bit 23 is set to 0 6623 */ 6624 #define PLANE_CTL_FORMAT_MASK (0xf << 24) 6625 #define PLANE_CTL_FORMAT_YUV422 (0 << 24) 6626 #define PLANE_CTL_FORMAT_NV12 (1 << 24) 6627 #define PLANE_CTL_FORMAT_XRGB_2101010 (2 << 24) 6628 #define PLANE_CTL_FORMAT_P010 (3 << 24) 6629 #define PLANE_CTL_FORMAT_XRGB_8888 (4 << 24) 6630 #define PLANE_CTL_FORMAT_P012 (5 << 24) 6631 #define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24) 6632 #define PLANE_CTL_FORMAT_P016 (7 << 24) 6633 #define PLANE_CTL_FORMAT_AYUV (8 << 24) 6634 #define PLANE_CTL_FORMAT_INDEXED (12 << 24) 6635 #define PLANE_CTL_FORMAT_RGB_565 (14 << 24) 6636 #define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23) 6637 #define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) /* Pre-GLK */ 6638 #define PLANE_CTL_FORMAT_Y210 (1 << 23) 6639 #define PLANE_CTL_FORMAT_Y212 (3 << 23) 6640 #define PLANE_CTL_FORMAT_Y216 (5 << 23) 6641 #define PLANE_CTL_FORMAT_Y410 (7 << 23) 6642 #define PLANE_CTL_FORMAT_Y412 (9 << 23) 6643 #define PLANE_CTL_FORMAT_Y416 (0xb << 23) 6644 #define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21) 6645 #define PLANE_CTL_KEY_ENABLE_SOURCE (1 << 21) 6646 #define PLANE_CTL_KEY_ENABLE_DESTINATION (2 << 21) 6647 #define PLANE_CTL_ORDER_BGRX (0 << 20) 6648 #define PLANE_CTL_ORDER_RGBX (1 << 20) 6649 #define PLANE_CTL_YUV420_Y_PLANE (1 << 19) 6650 #define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18) 6651 #define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16) 6652 #define PLANE_CTL_YUV422_YUYV (0 << 16) 6653 #define PLANE_CTL_YUV422_UYVY (1 << 16) 6654 #define PLANE_CTL_YUV422_YVYU (2 << 16) 6655 #define PLANE_CTL_YUV422_VYUY (3 << 16) 6656 #define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE (1 << 15) 6657 #define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14) 6658 #define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) /* Pre-GLK */ 6659 #define PLANE_CTL_TILED_MASK (0x7 << 10) 6660 #define PLANE_CTL_TILED_LINEAR (0 << 10) 6661 #define PLANE_CTL_TILED_X (1 << 10) 6662 #define PLANE_CTL_TILED_Y (4 << 10) 6663 #define PLANE_CTL_TILED_YF (5 << 10) 6664 #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8) 6665 #define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */ 6666 #define PLANE_CTL_ALPHA_DISABLE (0 << 4) 6667 #define PLANE_CTL_ALPHA_SW_PREMULTIPLY (2 << 4) 6668 #define PLANE_CTL_ALPHA_HW_PREMULTIPLY (3 << 4) 6669 #define PLANE_CTL_ROTATE_MASK 0x3 6670 #define PLANE_CTL_ROTATE_0 0x0 6671 #define PLANE_CTL_ROTATE_90 0x1 6672 #define PLANE_CTL_ROTATE_180 0x2 6673 #define PLANE_CTL_ROTATE_270 0x3 6674 #define _PLANE_STRIDE_1_A 0x70188 6675 #define _PLANE_STRIDE_2_A 0x70288 6676 #define _PLANE_STRIDE_3_A 0x70388 6677 #define _PLANE_POS_1_A 0x7018c 6678 #define _PLANE_POS_2_A 0x7028c 6679 #define _PLANE_POS_3_A 0x7038c 6680 #define _PLANE_SIZE_1_A 0x70190 6681 #define _PLANE_SIZE_2_A 0x70290 6682 #define _PLANE_SIZE_3_A 0x70390 6683 #define _PLANE_SURF_1_A 0x7019c 6684 #define _PLANE_SURF_2_A 0x7029c 6685 #define _PLANE_SURF_3_A 0x7039c 6686 #define _PLANE_OFFSET_1_A 0x701a4 6687 #define _PLANE_OFFSET_2_A 0x702a4 6688 #define _PLANE_OFFSET_3_A 0x703a4 6689 #define _PLANE_KEYVAL_1_A 0x70194 6690 #define _PLANE_KEYVAL_2_A 0x70294 6691 #define _PLANE_KEYMSK_1_A 0x70198 6692 #define _PLANE_KEYMSK_2_A 0x70298 6693 #define PLANE_KEYMSK_ALPHA_ENABLE (1 << 31) 6694 #define _PLANE_KEYMAX_1_A 0x701a0 6695 #define _PLANE_KEYMAX_2_A 0x702a0 6696 #define PLANE_KEYMAX_ALPHA(a) ((a) << 24) 6697 #define _PLANE_AUX_DIST_1_A 0x701c0 6698 #define _PLANE_AUX_DIST_2_A 0x702c0 6699 #define _PLANE_AUX_OFFSET_1_A 0x701c4 6700 #define _PLANE_AUX_OFFSET_2_A 0x702c4 6701 #define _PLANE_CUS_CTL_1_A 0x701c8 6702 #define _PLANE_CUS_CTL_2_A 0x702c8 6703 #define PLANE_CUS_ENABLE (1 << 31) 6704 #define PLANE_CUS_PLANE_6 (0 << 30) 6705 #define PLANE_CUS_PLANE_7 (1 << 30) 6706 #define PLANE_CUS_HPHASE_SIGN_NEGATIVE (1 << 19) 6707 #define PLANE_CUS_HPHASE_0 (0 << 16) 6708 #define PLANE_CUS_HPHASE_0_25 (1 << 16) 6709 #define PLANE_CUS_HPHASE_0_5 (2 << 16) 6710 #define PLANE_CUS_VPHASE_SIGN_NEGATIVE (1 << 15) 6711 #define PLANE_CUS_VPHASE_0 (0 << 12) 6712 #define PLANE_CUS_VPHASE_0_25 (1 << 12) 6713 #define PLANE_CUS_VPHASE_0_5 (2 << 12) 6714 #define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */ 6715 #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */ 6716 #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */ 6717 #define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-ICL */ 6718 #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28) 6719 #define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */ 6720 #define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */ 6721 #define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17) 6722 #define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709 (1 << 17) 6723 #define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 (2 << 17) 6724 #define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 (3 << 17) 6725 #define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 (4 << 17) 6726 #define PLANE_COLOR_PLANE_GAMMA_DISABLE (1 << 13) 6727 #define PLANE_COLOR_ALPHA_MASK (0x3 << 4) 6728 #define PLANE_COLOR_ALPHA_DISABLE (0 << 4) 6729 #define PLANE_COLOR_ALPHA_SW_PREMULTIPLY (2 << 4) 6730 #define PLANE_COLOR_ALPHA_HW_PREMULTIPLY (3 << 4) 6731 #define _PLANE_BUF_CFG_1_A 0x7027c 6732 #define _PLANE_BUF_CFG_2_A 0x7037c 6733 #define _PLANE_NV12_BUF_CFG_1_A 0x70278 6734 #define _PLANE_NV12_BUF_CFG_2_A 0x70378 6735 6736 /* Input CSC Register Definitions */ 6737 #define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0 6738 #define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0 6739 6740 #define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0 6741 #define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0 6742 6743 #define _PLANE_INPUT_CSC_RY_GY_1(pipe) \ 6744 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \ 6745 _PLANE_INPUT_CSC_RY_GY_1_B) 6746 #define _PLANE_INPUT_CSC_RY_GY_2(pipe) \ 6747 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \ 6748 _PLANE_INPUT_CSC_RY_GY_2_B) 6749 6750 #define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \ 6751 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \ 6752 _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4) 6753 6754 #define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8 6755 #define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8 6756 6757 #define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8 6758 #define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8 6759 6760 #define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \ 6761 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \ 6762 _PLANE_INPUT_CSC_PREOFF_HI_1_B) 6763 #define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \ 6764 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \ 6765 _PLANE_INPUT_CSC_PREOFF_HI_2_B) 6766 #define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \ 6767 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \ 6768 _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4) 6769 6770 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204 6771 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304 6772 6773 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204 6774 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304 6775 6776 #define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \ 6777 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \ 6778 _PLANE_INPUT_CSC_POSTOFF_HI_1_B) 6779 #define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \ 6780 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \ 6781 _PLANE_INPUT_CSC_POSTOFF_HI_2_B) 6782 #define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \ 6783 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \ 6784 _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4) 6785 6786 #define _PLANE_CTL_1_B 0x71180 6787 #define _PLANE_CTL_2_B 0x71280 6788 #define _PLANE_CTL_3_B 0x71380 6789 #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B) 6790 #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B) 6791 #define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B) 6792 #define PLANE_CTL(pipe, plane) \ 6793 _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) 6794 6795 #define _PLANE_STRIDE_1_B 0x71188 6796 #define _PLANE_STRIDE_2_B 0x71288 6797 #define _PLANE_STRIDE_3_B 0x71388 6798 #define _PLANE_STRIDE_1(pipe) \ 6799 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B) 6800 #define _PLANE_STRIDE_2(pipe) \ 6801 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) 6802 #define _PLANE_STRIDE_3(pipe) \ 6803 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B) 6804 #define PLANE_STRIDE(pipe, plane) \ 6805 _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) 6806 6807 #define _PLANE_POS_1_B 0x7118c 6808 #define _PLANE_POS_2_B 0x7128c 6809 #define _PLANE_POS_3_B 0x7138c 6810 #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B) 6811 #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B) 6812 #define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B) 6813 #define PLANE_POS(pipe, plane) \ 6814 _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) 6815 6816 #define _PLANE_SIZE_1_B 0x71190 6817 #define _PLANE_SIZE_2_B 0x71290 6818 #define _PLANE_SIZE_3_B 0x71390 6819 #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B) 6820 #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) 6821 #define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B) 6822 #define PLANE_SIZE(pipe, plane) \ 6823 _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) 6824 6825 #define _PLANE_SURF_1_B 0x7119c 6826 #define _PLANE_SURF_2_B 0x7129c 6827 #define _PLANE_SURF_3_B 0x7139c 6828 #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B) 6829 #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B) 6830 #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B) 6831 #define PLANE_SURF(pipe, plane) \ 6832 _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe)) 6833 6834 #define _PLANE_OFFSET_1_B 0x711a4 6835 #define _PLANE_OFFSET_2_B 0x712a4 6836 #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B) 6837 #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B) 6838 #define PLANE_OFFSET(pipe, plane) \ 6839 _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe)) 6840 6841 #define _PLANE_KEYVAL_1_B 0x71194 6842 #define _PLANE_KEYVAL_2_B 0x71294 6843 #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B) 6844 #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B) 6845 #define PLANE_KEYVAL(pipe, plane) \ 6846 _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe)) 6847 6848 #define _PLANE_KEYMSK_1_B 0x71198 6849 #define _PLANE_KEYMSK_2_B 0x71298 6850 #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B) 6851 #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B) 6852 #define PLANE_KEYMSK(pipe, plane) \ 6853 _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe)) 6854 6855 #define _PLANE_KEYMAX_1_B 0x711a0 6856 #define _PLANE_KEYMAX_2_B 0x712a0 6857 #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B) 6858 #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B) 6859 #define PLANE_KEYMAX(pipe, plane) \ 6860 _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe)) 6861 6862 #define _PLANE_BUF_CFG_1_B 0x7127c 6863 #define _PLANE_BUF_CFG_2_B 0x7137c 6864 #define DDB_ENTRY_MASK 0x7FF /* skl+: 10 bits, icl+ 11 bits */ 6865 #define DDB_ENTRY_END_SHIFT 16 6866 #define _PLANE_BUF_CFG_1(pipe) \ 6867 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B) 6868 #define _PLANE_BUF_CFG_2(pipe) \ 6869 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B) 6870 #define PLANE_BUF_CFG(pipe, plane) \ 6871 _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe)) 6872 6873 #define _PLANE_NV12_BUF_CFG_1_B 0x71278 6874 #define _PLANE_NV12_BUF_CFG_2_B 0x71378 6875 #define _PLANE_NV12_BUF_CFG_1(pipe) \ 6876 _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B) 6877 #define _PLANE_NV12_BUF_CFG_2(pipe) \ 6878 _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B) 6879 #define PLANE_NV12_BUF_CFG(pipe, plane) \ 6880 _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe)) 6881 6882 #define _PLANE_AUX_DIST_1_B 0x711c0 6883 #define _PLANE_AUX_DIST_2_B 0x712c0 6884 #define _PLANE_AUX_DIST_1(pipe) \ 6885 _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B) 6886 #define _PLANE_AUX_DIST_2(pipe) \ 6887 _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B) 6888 #define PLANE_AUX_DIST(pipe, plane) \ 6889 _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe)) 6890 6891 #define _PLANE_AUX_OFFSET_1_B 0x711c4 6892 #define _PLANE_AUX_OFFSET_2_B 0x712c4 6893 #define _PLANE_AUX_OFFSET_1(pipe) \ 6894 _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B) 6895 #define _PLANE_AUX_OFFSET_2(pipe) \ 6896 _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B) 6897 #define PLANE_AUX_OFFSET(pipe, plane) \ 6898 _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe)) 6899 6900 #define _PLANE_CUS_CTL_1_B 0x711c8 6901 #define _PLANE_CUS_CTL_2_B 0x712c8 6902 #define _PLANE_CUS_CTL_1(pipe) \ 6903 _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B) 6904 #define _PLANE_CUS_CTL_2(pipe) \ 6905 _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B) 6906 #define PLANE_CUS_CTL(pipe, plane) \ 6907 _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe)) 6908 6909 #define _PLANE_COLOR_CTL_1_B 0x711CC 6910 #define _PLANE_COLOR_CTL_2_B 0x712CC 6911 #define _PLANE_COLOR_CTL_3_B 0x713CC 6912 #define _PLANE_COLOR_CTL_1(pipe) \ 6913 _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B) 6914 #define _PLANE_COLOR_CTL_2(pipe) \ 6915 _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B) 6916 #define PLANE_COLOR_CTL(pipe, plane) \ 6917 _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe)) 6918 6919 #/* SKL new cursor registers */ 6920 #define _CUR_BUF_CFG_A 0x7017c 6921 #define _CUR_BUF_CFG_B 0x7117c 6922 #define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B) 6923 6924 /* VBIOS regs */ 6925 #define VGACNTRL _MMIO(0x71400) 6926 # define VGA_DISP_DISABLE (1 << 31) 6927 # define VGA_2X_MODE (1 << 30) 6928 # define VGA_PIPE_B_SELECT (1 << 29) 6929 6930 #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400) 6931 6932 /* Ironlake */ 6933 6934 #define CPU_VGACNTRL _MMIO(0x41000) 6935 6936 #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030) 6937 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) 6938 #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */ 6939 #define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */ 6940 #define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */ 6941 #define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */ 6942 #define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */ 6943 #define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0) 6944 #define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0) 6945 #define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0) 6946 #define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0) 6947 6948 /* refresh rate hardware control */ 6949 #define RR_HW_CTL _MMIO(0x45300) 6950 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff 6951 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 6952 6953 #define FDI_PLL_BIOS_0 _MMIO(0x46000) 6954 #define FDI_PLL_FB_CLOCK_MASK 0xff 6955 #define FDI_PLL_BIOS_1 _MMIO(0x46004) 6956 #define FDI_PLL_BIOS_2 _MMIO(0x46008) 6957 #define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c) 6958 #define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010) 6959 #define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014) 6960 6961 #define PCH_3DCGDIS0 _MMIO(0x46020) 6962 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) 6963 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) 6964 6965 #define PCH_3DCGDIS1 _MMIO(0x46024) 6966 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) 6967 6968 #define FDI_PLL_FREQ_CTL _MMIO(0x46030) 6969 #define FDI_PLL_FREQ_CHANGE_REQUEST (1 << 24) 6970 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 6971 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff 6972 6973 6974 #define _PIPEA_DATA_M1 0x60030 6975 #define PIPE_DATA_M1_OFFSET 0 6976 #define _PIPEA_DATA_N1 0x60034 6977 #define PIPE_DATA_N1_OFFSET 0 6978 6979 #define _PIPEA_DATA_M2 0x60038 6980 #define PIPE_DATA_M2_OFFSET 0 6981 #define _PIPEA_DATA_N2 0x6003c 6982 #define PIPE_DATA_N2_OFFSET 0 6983 6984 #define _PIPEA_LINK_M1 0x60040 6985 #define PIPE_LINK_M1_OFFSET 0 6986 #define _PIPEA_LINK_N1 0x60044 6987 #define PIPE_LINK_N1_OFFSET 0 6988 6989 #define _PIPEA_LINK_M2 0x60048 6990 #define PIPE_LINK_M2_OFFSET 0 6991 #define _PIPEA_LINK_N2 0x6004c 6992 #define PIPE_LINK_N2_OFFSET 0 6993 6994 /* PIPEB timing regs are same start from 0x61000 */ 6995 6996 #define _PIPEB_DATA_M1 0x61030 6997 #define _PIPEB_DATA_N1 0x61034 6998 #define _PIPEB_DATA_M2 0x61038 6999 #define _PIPEB_DATA_N2 0x6103c 7000 #define _PIPEB_LINK_M1 0x61040 7001 #define _PIPEB_LINK_N1 0x61044 7002 #define _PIPEB_LINK_M2 0x61048 7003 #define _PIPEB_LINK_N2 0x6104c 7004 7005 #define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1) 7006 #define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1) 7007 #define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2) 7008 #define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2) 7009 #define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1) 7010 #define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1) 7011 #define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2) 7012 #define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2) 7013 7014 /* CPU panel fitter */ 7015 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ 7016 #define _PFA_CTL_1 0x68080 7017 #define _PFB_CTL_1 0x68880 7018 #define PF_ENABLE (1 << 31) 7019 #define PF_PIPE_SEL_MASK_IVB (3 << 29) 7020 #define PF_PIPE_SEL_IVB(pipe) ((pipe) << 29) 7021 #define PF_FILTER_MASK (3 << 23) 7022 #define PF_FILTER_PROGRAMMED (0 << 23) 7023 #define PF_FILTER_MED_3x3 (1 << 23) 7024 #define PF_FILTER_EDGE_ENHANCE (2 << 23) 7025 #define PF_FILTER_EDGE_SOFTEN (3 << 23) 7026 #define _PFA_WIN_SZ 0x68074 7027 #define _PFB_WIN_SZ 0x68874 7028 #define _PFA_WIN_POS 0x68070 7029 #define _PFB_WIN_POS 0x68870 7030 #define _PFA_VSCALE 0x68084 7031 #define _PFB_VSCALE 0x68884 7032 #define _PFA_HSCALE 0x68090 7033 #define _PFB_HSCALE 0x68890 7034 7035 #define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) 7036 #define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) 7037 #define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) 7038 #define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) 7039 #define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) 7040 7041 #define _PSA_CTL 0x68180 7042 #define _PSB_CTL 0x68980 7043 #define PS_ENABLE (1 << 31) 7044 #define _PSA_WIN_SZ 0x68174 7045 #define _PSB_WIN_SZ 0x68974 7046 #define _PSA_WIN_POS 0x68170 7047 #define _PSB_WIN_POS 0x68970 7048 7049 #define PS_CTL(pipe) _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL) 7050 #define PS_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ) 7051 #define PS_WIN_POS(pipe) _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS) 7052 7053 /* 7054 * Skylake scalers 7055 */ 7056 #define _PS_1A_CTRL 0x68180 7057 #define _PS_2A_CTRL 0x68280 7058 #define _PS_1B_CTRL 0x68980 7059 #define _PS_2B_CTRL 0x68A80 7060 #define _PS_1C_CTRL 0x69180 7061 #define PS_SCALER_EN (1 << 31) 7062 #define SKL_PS_SCALER_MODE_MASK (3 << 28) 7063 #define SKL_PS_SCALER_MODE_DYN (0 << 28) 7064 #define SKL_PS_SCALER_MODE_HQ (1 << 28) 7065 #define SKL_PS_SCALER_MODE_NV12 (2 << 28) 7066 #define PS_SCALER_MODE_PLANAR (1 << 29) 7067 #define PS_SCALER_MODE_NORMAL (0 << 29) 7068 #define PS_PLANE_SEL_MASK (7 << 25) 7069 #define PS_PLANE_SEL(plane) (((plane) + 1) << 25) 7070 #define PS_FILTER_MASK (3 << 23) 7071 #define PS_FILTER_MEDIUM (0 << 23) 7072 #define PS_FILTER_EDGE_ENHANCE (2 << 23) 7073 #define PS_FILTER_BILINEAR (3 << 23) 7074 #define PS_VERT3TAP (1 << 21) 7075 #define PS_VERT_INT_INVERT_FIELD1 (0 << 20) 7076 #define PS_VERT_INT_INVERT_FIELD0 (1 << 20) 7077 #define PS_PWRUP_PROGRESS (1 << 17) 7078 #define PS_V_FILTER_BYPASS (1 << 8) 7079 #define PS_VADAPT_EN (1 << 7) 7080 #define PS_VADAPT_MODE_MASK (3 << 5) 7081 #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5) 7082 #define PS_VADAPT_MODE_MOD_ADAPT (1 << 5) 7083 #define PS_VADAPT_MODE_MOST_ADAPT (3 << 5) 7084 #define PS_PLANE_Y_SEL_MASK (7 << 5) 7085 #define PS_PLANE_Y_SEL(plane) (((plane) + 1) << 5) 7086 7087 #define _PS_PWR_GATE_1A 0x68160 7088 #define _PS_PWR_GATE_2A 0x68260 7089 #define _PS_PWR_GATE_1B 0x68960 7090 #define _PS_PWR_GATE_2B 0x68A60 7091 #define _PS_PWR_GATE_1C 0x69160 7092 #define PS_PWR_GATE_DIS_OVERRIDE (1 << 31) 7093 #define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3) 7094 #define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3) 7095 #define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3) 7096 #define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3) 7097 #define PS_PWR_GATE_SLPEN_8 0 7098 #define PS_PWR_GATE_SLPEN_16 1 7099 #define PS_PWR_GATE_SLPEN_24 2 7100 #define PS_PWR_GATE_SLPEN_32 3 7101 7102 #define _PS_WIN_POS_1A 0x68170 7103 #define _PS_WIN_POS_2A 0x68270 7104 #define _PS_WIN_POS_1B 0x68970 7105 #define _PS_WIN_POS_2B 0x68A70 7106 #define _PS_WIN_POS_1C 0x69170 7107 7108 #define _PS_WIN_SZ_1A 0x68174 7109 #define _PS_WIN_SZ_2A 0x68274 7110 #define _PS_WIN_SZ_1B 0x68974 7111 #define _PS_WIN_SZ_2B 0x68A74 7112 #define _PS_WIN_SZ_1C 0x69174 7113 7114 #define _PS_VSCALE_1A 0x68184 7115 #define _PS_VSCALE_2A 0x68284 7116 #define _PS_VSCALE_1B 0x68984 7117 #define _PS_VSCALE_2B 0x68A84 7118 #define _PS_VSCALE_1C 0x69184 7119 7120 #define _PS_HSCALE_1A 0x68190 7121 #define _PS_HSCALE_2A 0x68290 7122 #define _PS_HSCALE_1B 0x68990 7123 #define _PS_HSCALE_2B 0x68A90 7124 #define _PS_HSCALE_1C 0x69190 7125 7126 #define _PS_VPHASE_1A 0x68188 7127 #define _PS_VPHASE_2A 0x68288 7128 #define _PS_VPHASE_1B 0x68988 7129 #define _PS_VPHASE_2B 0x68A88 7130 #define _PS_VPHASE_1C 0x69188 7131 #define PS_Y_PHASE(x) ((x) << 16) 7132 #define PS_UV_RGB_PHASE(x) ((x) << 0) 7133 #define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */ 7134 #define PS_PHASE_TRIP (1 << 0) 7135 7136 #define _PS_HPHASE_1A 0x68194 7137 #define _PS_HPHASE_2A 0x68294 7138 #define _PS_HPHASE_1B 0x68994 7139 #define _PS_HPHASE_2B 0x68A94 7140 #define _PS_HPHASE_1C 0x69194 7141 7142 #define _PS_ECC_STAT_1A 0x681D0 7143 #define _PS_ECC_STAT_2A 0x682D0 7144 #define _PS_ECC_STAT_1B 0x689D0 7145 #define _PS_ECC_STAT_2B 0x68AD0 7146 #define _PS_ECC_STAT_1C 0x691D0 7147 7148 #define _ID(id, a, b) _PICK_EVEN(id, a, b) 7149 #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \ 7150 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \ 7151 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL)) 7152 #define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \ 7153 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \ 7154 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B)) 7155 #define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \ 7156 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \ 7157 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B)) 7158 #define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \ 7159 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \ 7160 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B)) 7161 #define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \ 7162 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \ 7163 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B)) 7164 #define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \ 7165 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \ 7166 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B)) 7167 #define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \ 7168 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \ 7169 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B)) 7170 #define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \ 7171 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \ 7172 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B)) 7173 #define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \ 7174 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \ 7175 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)) 7176 7177 /* legacy palette */ 7178 #define _LGC_PALETTE_A 0x4a000 7179 #define _LGC_PALETTE_B 0x4a800 7180 #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4) 7181 7182 /* ilk/snb precision palette */ 7183 #define _PREC_PALETTE_A 0x4b000 7184 #define _PREC_PALETTE_B 0x4c000 7185 #define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4) 7186 7187 #define _PREC_PIPEAGCMAX 0x4d000 7188 #define _PREC_PIPEBGCMAX 0x4d010 7189 #define PREC_PIPEGCMAX(pipe, i) _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4) 7190 7191 #define _GAMMA_MODE_A 0x4a480 7192 #define _GAMMA_MODE_B 0x4ac80 7193 #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) 7194 #define PRE_CSC_GAMMA_ENABLE (1 << 31) 7195 #define POST_CSC_GAMMA_ENABLE (1 << 30) 7196 #define GAMMA_MODE_MODE_MASK (3 << 0) 7197 #define GAMMA_MODE_MODE_8BIT (0 << 0) 7198 #define GAMMA_MODE_MODE_10BIT (1 << 0) 7199 #define GAMMA_MODE_MODE_12BIT (2 << 0) 7200 #define GAMMA_MODE_MODE_SPLIT (3 << 0) 7201 7202 /* DMC/CSR */ 7203 #define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4) 7204 #define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0 7205 #define CSR_HTP_ADDR_SKL 0x00500034 7206 #define CSR_SSP_BASE _MMIO(0x8F074) 7207 #define CSR_HTP_SKL _MMIO(0x8F004) 7208 #define CSR_LAST_WRITE _MMIO(0x8F034) 7209 #define CSR_LAST_WRITE_VALUE 0xc003b400 7210 /* MMIO address range for CSR program (0x80000 - 0x82FFF) */ 7211 #define CSR_MMIO_START_RANGE 0x80000 7212 #define CSR_MMIO_END_RANGE 0x8FFFF 7213 #define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030) 7214 #define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C) 7215 #define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038) 7216 7217 /* interrupts */ 7218 #define DE_MASTER_IRQ_CONTROL (1 << 31) 7219 #define DE_SPRITEB_FLIP_DONE (1 << 29) 7220 #define DE_SPRITEA_FLIP_DONE (1 << 28) 7221 #define DE_PLANEB_FLIP_DONE (1 << 27) 7222 #define DE_PLANEA_FLIP_DONE (1 << 26) 7223 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane))) 7224 #define DE_PCU_EVENT (1 << 25) 7225 #define DE_GTT_FAULT (1 << 24) 7226 #define DE_POISON (1 << 23) 7227 #define DE_PERFORM_COUNTER (1 << 22) 7228 #define DE_PCH_EVENT (1 << 21) 7229 #define DE_AUX_CHANNEL_A (1 << 20) 7230 #define DE_DP_A_HOTPLUG (1 << 19) 7231 #define DE_GSE (1 << 18) 7232 #define DE_PIPEB_VBLANK (1 << 15) 7233 #define DE_PIPEB_EVEN_FIELD (1 << 14) 7234 #define DE_PIPEB_ODD_FIELD (1 << 13) 7235 #define DE_PIPEB_LINE_COMPARE (1 << 12) 7236 #define DE_PIPEB_VSYNC (1 << 11) 7237 #define DE_PIPEB_CRC_DONE (1 << 10) 7238 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) 7239 #define DE_PIPEA_VBLANK (1 << 7) 7240 #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe))) 7241 #define DE_PIPEA_EVEN_FIELD (1 << 6) 7242 #define DE_PIPEA_ODD_FIELD (1 << 5) 7243 #define DE_PIPEA_LINE_COMPARE (1 << 4) 7244 #define DE_PIPEA_VSYNC (1 << 3) 7245 #define DE_PIPEA_CRC_DONE (1 << 2) 7246 #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe))) 7247 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) 7248 #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe))) 7249 7250 /* More Ivybridge lolz */ 7251 #define DE_ERR_INT_IVB (1 << 30) 7252 #define DE_GSE_IVB (1 << 29) 7253 #define DE_PCH_EVENT_IVB (1 << 28) 7254 #define DE_DP_A_HOTPLUG_IVB (1 << 27) 7255 #define DE_AUX_CHANNEL_A_IVB (1 << 26) 7256 #define DE_EDP_PSR_INT_HSW (1 << 19) 7257 #define DE_SPRITEC_FLIP_DONE_IVB (1 << 14) 7258 #define DE_PLANEC_FLIP_DONE_IVB (1 << 13) 7259 #define DE_PIPEC_VBLANK_IVB (1 << 10) 7260 #define DE_SPRITEB_FLIP_DONE_IVB (1 << 9) 7261 #define DE_PLANEB_FLIP_DONE_IVB (1 << 8) 7262 #define DE_PIPEB_VBLANK_IVB (1 << 5) 7263 #define DE_SPRITEA_FLIP_DONE_IVB (1 << 4) 7264 #define DE_PLANEA_FLIP_DONE_IVB (1 << 3) 7265 #define DE_PLANE_FLIP_DONE_IVB(plane) (1 << (3 + 5 * (plane))) 7266 #define DE_PIPEA_VBLANK_IVB (1 << 0) 7267 #define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5)) 7268 7269 #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */ 7270 #define MASTER_INTERRUPT_ENABLE (1 << 31) 7271 7272 #define DEISR _MMIO(0x44000) 7273 #define DEIMR _MMIO(0x44004) 7274 #define DEIIR _MMIO(0x44008) 7275 #define DEIER _MMIO(0x4400c) 7276 7277 #define GTISR _MMIO(0x44010) 7278 #define GTIMR _MMIO(0x44014) 7279 #define GTIIR _MMIO(0x44018) 7280 #define GTIER _MMIO(0x4401c) 7281 7282 #define GEN8_MASTER_IRQ _MMIO(0x44200) 7283 #define GEN8_MASTER_IRQ_CONTROL (1 << 31) 7284 #define GEN8_PCU_IRQ (1 << 30) 7285 #define GEN8_DE_PCH_IRQ (1 << 23) 7286 #define GEN8_DE_MISC_IRQ (1 << 22) 7287 #define GEN8_DE_PORT_IRQ (1 << 20) 7288 #define GEN8_DE_PIPE_C_IRQ (1 << 18) 7289 #define GEN8_DE_PIPE_B_IRQ (1 << 17) 7290 #define GEN8_DE_PIPE_A_IRQ (1 << 16) 7291 #define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe))) 7292 #define GEN8_GT_VECS_IRQ (1 << 6) 7293 #define GEN8_GT_GUC_IRQ (1 << 5) 7294 #define GEN8_GT_PM_IRQ (1 << 4) 7295 #define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */ 7296 #define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */ 7297 #define GEN8_GT_BCS_IRQ (1 << 1) 7298 #define GEN8_GT_RCS_IRQ (1 << 0) 7299 7300 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which))) 7301 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which))) 7302 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which))) 7303 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which))) 7304 7305 #define GEN9_GUC_TO_HOST_INT_EVENT (1 << 31) 7306 #define GEN9_GUC_EXEC_ERROR_EVENT (1 << 30) 7307 #define GEN9_GUC_DISPLAY_EVENT (1 << 29) 7308 #define GEN9_GUC_SEMA_SIGNAL_EVENT (1 << 28) 7309 #define GEN9_GUC_IOMMU_MSG_EVENT (1 << 27) 7310 #define GEN9_GUC_DB_RING_EVENT (1 << 26) 7311 #define GEN9_GUC_DMA_DONE_EVENT (1 << 25) 7312 #define GEN9_GUC_FATAL_ERROR_EVENT (1 << 24) 7313 #define GEN9_GUC_NOTIFICATION_EVENT (1 << 23) 7314 7315 #define GEN8_RCS_IRQ_SHIFT 0 7316 #define GEN8_BCS_IRQ_SHIFT 16 7317 #define GEN8_VCS0_IRQ_SHIFT 0 /* NB: VCS1 in bspec! */ 7318 #define GEN8_VCS1_IRQ_SHIFT 16 /* NB: VCS2 in bpsec! */ 7319 #define GEN8_VECS_IRQ_SHIFT 0 7320 #define GEN8_WD_IRQ_SHIFT 16 7321 7322 #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe))) 7323 #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe))) 7324 #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe))) 7325 #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe))) 7326 #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31) 7327 #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29) 7328 #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28) 7329 #define GEN8_PIPE_CURSOR_FAULT (1 << 10) 7330 #define GEN8_PIPE_SPRITE_FAULT (1 << 9) 7331 #define GEN8_PIPE_PRIMARY_FAULT (1 << 8) 7332 #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5) 7333 #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4) 7334 #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) 7335 #define GEN8_PIPE_VSYNC (1 << 1) 7336 #define GEN8_PIPE_VBLANK (1 << 0) 7337 #define GEN9_PIPE_CURSOR_FAULT (1 << 11) 7338 #define GEN9_PIPE_PLANE4_FAULT (1 << 10) 7339 #define GEN9_PIPE_PLANE3_FAULT (1 << 9) 7340 #define GEN9_PIPE_PLANE2_FAULT (1 << 8) 7341 #define GEN9_PIPE_PLANE1_FAULT (1 << 7) 7342 #define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6) 7343 #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5) 7344 #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4) 7345 #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3) 7346 #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p))) 7347 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ 7348 (GEN8_PIPE_CURSOR_FAULT | \ 7349 GEN8_PIPE_SPRITE_FAULT | \ 7350 GEN8_PIPE_PRIMARY_FAULT) 7351 #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \ 7352 (GEN9_PIPE_CURSOR_FAULT | \ 7353 GEN9_PIPE_PLANE4_FAULT | \ 7354 GEN9_PIPE_PLANE3_FAULT | \ 7355 GEN9_PIPE_PLANE2_FAULT | \ 7356 GEN9_PIPE_PLANE1_FAULT) 7357 7358 #define GEN8_DE_PORT_ISR _MMIO(0x44440) 7359 #define GEN8_DE_PORT_IMR _MMIO(0x44444) 7360 #define GEN8_DE_PORT_IIR _MMIO(0x44448) 7361 #define GEN8_DE_PORT_IER _MMIO(0x4444c) 7362 #define ICL_AUX_CHANNEL_E (1 << 29) 7363 #define CNL_AUX_CHANNEL_F (1 << 28) 7364 #define GEN9_AUX_CHANNEL_D (1 << 27) 7365 #define GEN9_AUX_CHANNEL_C (1 << 26) 7366 #define GEN9_AUX_CHANNEL_B (1 << 25) 7367 #define BXT_DE_PORT_HP_DDIC (1 << 5) 7368 #define BXT_DE_PORT_HP_DDIB (1 << 4) 7369 #define BXT_DE_PORT_HP_DDIA (1 << 3) 7370 #define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDIA | \ 7371 BXT_DE_PORT_HP_DDIB | \ 7372 BXT_DE_PORT_HP_DDIC) 7373 #define GEN8_PORT_DP_A_HOTPLUG (1 << 3) 7374 #define BXT_DE_PORT_GMBUS (1 << 1) 7375 #define GEN8_AUX_CHANNEL_A (1 << 0) 7376 7377 #define GEN8_DE_MISC_ISR _MMIO(0x44460) 7378 #define GEN8_DE_MISC_IMR _MMIO(0x44464) 7379 #define GEN8_DE_MISC_IIR _MMIO(0x44468) 7380 #define GEN8_DE_MISC_IER _MMIO(0x4446c) 7381 #define GEN8_DE_MISC_GSE (1 << 27) 7382 #define GEN8_DE_EDP_PSR (1 << 19) 7383 7384 #define GEN8_PCU_ISR _MMIO(0x444e0) 7385 #define GEN8_PCU_IMR _MMIO(0x444e4) 7386 #define GEN8_PCU_IIR _MMIO(0x444e8) 7387 #define GEN8_PCU_IER _MMIO(0x444ec) 7388 7389 #define GEN11_GU_MISC_ISR _MMIO(0x444f0) 7390 #define GEN11_GU_MISC_IMR _MMIO(0x444f4) 7391 #define GEN11_GU_MISC_IIR _MMIO(0x444f8) 7392 #define GEN11_GU_MISC_IER _MMIO(0x444fc) 7393 #define GEN11_GU_MISC_GSE (1 << 27) 7394 7395 #define GEN11_GFX_MSTR_IRQ _MMIO(0x190010) 7396 #define GEN11_MASTER_IRQ (1 << 31) 7397 #define GEN11_PCU_IRQ (1 << 30) 7398 #define GEN11_GU_MISC_IRQ (1 << 29) 7399 #define GEN11_DISPLAY_IRQ (1 << 16) 7400 #define GEN11_GT_DW_IRQ(x) (1 << (x)) 7401 #define GEN11_GT_DW1_IRQ (1 << 1) 7402 #define GEN11_GT_DW0_IRQ (1 << 0) 7403 7404 #define GEN11_DISPLAY_INT_CTL _MMIO(0x44200) 7405 #define GEN11_DISPLAY_IRQ_ENABLE (1 << 31) 7406 #define GEN11_AUDIO_CODEC_IRQ (1 << 24) 7407 #define GEN11_DE_PCH_IRQ (1 << 23) 7408 #define GEN11_DE_MISC_IRQ (1 << 22) 7409 #define GEN11_DE_HPD_IRQ (1 << 21) 7410 #define GEN11_DE_PORT_IRQ (1 << 20) 7411 #define GEN11_DE_PIPE_C (1 << 18) 7412 #define GEN11_DE_PIPE_B (1 << 17) 7413 #define GEN11_DE_PIPE_A (1 << 16) 7414 7415 #define GEN11_DE_HPD_ISR _MMIO(0x44470) 7416 #define GEN11_DE_HPD_IMR _MMIO(0x44474) 7417 #define GEN11_DE_HPD_IIR _MMIO(0x44478) 7418 #define GEN11_DE_HPD_IER _MMIO(0x4447c) 7419 #define GEN11_TC4_HOTPLUG (1 << 19) 7420 #define GEN11_TC3_HOTPLUG (1 << 18) 7421 #define GEN11_TC2_HOTPLUG (1 << 17) 7422 #define GEN11_TC1_HOTPLUG (1 << 16) 7423 #define GEN11_TC_HOTPLUG(tc_port) (1 << ((tc_port) + 16)) 7424 #define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC4_HOTPLUG | \ 7425 GEN11_TC3_HOTPLUG | \ 7426 GEN11_TC2_HOTPLUG | \ 7427 GEN11_TC1_HOTPLUG) 7428 #define GEN11_TBT4_HOTPLUG (1 << 3) 7429 #define GEN11_TBT3_HOTPLUG (1 << 2) 7430 #define GEN11_TBT2_HOTPLUG (1 << 1) 7431 #define GEN11_TBT1_HOTPLUG (1 << 0) 7432 #define GEN11_TBT_HOTPLUG(tc_port) (1 << (tc_port)) 7433 #define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT4_HOTPLUG | \ 7434 GEN11_TBT3_HOTPLUG | \ 7435 GEN11_TBT2_HOTPLUG | \ 7436 GEN11_TBT1_HOTPLUG) 7437 7438 #define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030) 7439 #define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038) 7440 #define GEN11_HOTPLUG_CTL_ENABLE(tc_port) (8 << (tc_port) * 4) 7441 #define GEN11_HOTPLUG_CTL_LONG_DETECT(tc_port) (2 << (tc_port) * 4) 7442 #define GEN11_HOTPLUG_CTL_SHORT_DETECT(tc_port) (1 << (tc_port) * 4) 7443 #define GEN11_HOTPLUG_CTL_NO_DETECT(tc_port) (0 << (tc_port) * 4) 7444 7445 #define GEN11_GT_INTR_DW0 _MMIO(0x190018) 7446 #define GEN11_CSME (31) 7447 #define GEN11_GUNIT (28) 7448 #define GEN11_GUC (25) 7449 #define GEN11_WDPERF (20) 7450 #define GEN11_KCR (19) 7451 #define GEN11_GTPM (16) 7452 #define GEN11_BCS (15) 7453 #define GEN11_RCS0 (0) 7454 7455 #define GEN11_GT_INTR_DW1 _MMIO(0x19001c) 7456 #define GEN11_VECS(x) (31 - (x)) 7457 #define GEN11_VCS(x) (x) 7458 7459 #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4)) 7460 7461 #define GEN11_INTR_IDENTITY_REG0 _MMIO(0x190060) 7462 #define GEN11_INTR_IDENTITY_REG1 _MMIO(0x190064) 7463 #define GEN11_INTR_DATA_VALID (1 << 31) 7464 #define GEN11_INTR_ENGINE_CLASS(x) (((x) & GENMASK(18, 16)) >> 16) 7465 #define GEN11_INTR_ENGINE_INSTANCE(x) (((x) & GENMASK(25, 20)) >> 20) 7466 #define GEN11_INTR_ENGINE_INTR(x) ((x) & 0xffff) 7467 7468 #define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4)) 7469 7470 #define GEN11_IIR_REG0_SELECTOR _MMIO(0x190070) 7471 #define GEN11_IIR_REG1_SELECTOR _MMIO(0x190074) 7472 7473 #define GEN11_IIR_REG_SELECTOR(x) _MMIO(0x190070 + ((x) * 4)) 7474 7475 #define GEN11_RENDER_COPY_INTR_ENABLE _MMIO(0x190030) 7476 #define GEN11_VCS_VECS_INTR_ENABLE _MMIO(0x190034) 7477 #define GEN11_GUC_SG_INTR_ENABLE _MMIO(0x190038) 7478 #define GEN11_GPM_WGBOXPERF_INTR_ENABLE _MMIO(0x19003c) 7479 #define GEN11_CRYPTO_RSVD_INTR_ENABLE _MMIO(0x190040) 7480 #define GEN11_GUNIT_CSME_INTR_ENABLE _MMIO(0x190044) 7481 7482 #define GEN11_RCS0_RSVD_INTR_MASK _MMIO(0x190090) 7483 #define GEN11_BCS_RSVD_INTR_MASK _MMIO(0x1900a0) 7484 #define GEN11_VCS0_VCS1_INTR_MASK _MMIO(0x1900a8) 7485 #define GEN11_VCS2_VCS3_INTR_MASK _MMIO(0x1900ac) 7486 #define GEN11_VECS0_VECS1_INTR_MASK _MMIO(0x1900d0) 7487 #define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8) 7488 #define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec) 7489 #define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0) 7490 #define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4) 7491 7492 #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004) 7493 /* Required on all Ironlake and Sandybridge according to the B-Spec. */ 7494 #define ILK_ELPIN_409_SELECT (1 << 25) 7495 #define ILK_DPARB_GATE (1 << 22) 7496 #define ILK_VSDPFD_FULL (1 << 21) 7497 #define FUSE_STRAP _MMIO(0x42014) 7498 #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31) 7499 #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30) 7500 #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29) 7501 #define IVB_PIPE_C_DISABLE (1 << 28) 7502 #define ILK_HDCP_DISABLE (1 << 25) 7503 #define ILK_eDP_A_DISABLE (1 << 24) 7504 #define HSW_CDCLK_LIMIT (1 << 24) 7505 #define ILK_DESKTOP (1 << 23) 7506 7507 #define ILK_DSPCLK_GATE_D _MMIO(0x42020) 7508 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) 7509 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) 7510 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8) 7511 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7) 7512 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5) 7513 7514 #define IVB_CHICKEN3 _MMIO(0x4200c) 7515 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) 7516 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) 7517 7518 #define CHICKEN_PAR1_1 _MMIO(0x42080) 7519 #define SKL_DE_COMPRESSED_HASH_MODE (1 << 15) 7520 #define DPA_MASK_VBLANK_SRD (1 << 15) 7521 #define FORCE_ARB_IDLE_PLANES (1 << 14) 7522 #define SKL_EDP_PSR_FIX_RDWRAP (1 << 3) 7523 7524 #define CHICKEN_PAR2_1 _MMIO(0x42090) 7525 #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14) 7526 7527 #define CHICKEN_MISC_2 _MMIO(0x42084) 7528 #define CNL_COMP_PWR_DOWN (1 << 23) 7529 #define GLK_CL2_PWR_DOWN (1 << 12) 7530 #define GLK_CL1_PWR_DOWN (1 << 11) 7531 #define GLK_CL0_PWR_DOWN (1 << 10) 7532 7533 #define CHICKEN_MISC_4 _MMIO(0x4208c) 7534 #define FBC_STRIDE_OVERRIDE (1 << 13) 7535 #define FBC_STRIDE_MASK 0x1FFF 7536 7537 #define _CHICKEN_PIPESL_1_A 0x420b0 7538 #define _CHICKEN_PIPESL_1_B 0x420b4 7539 #define HSW_FBCQ_DIS (1 << 22) 7540 #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0) 7541 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) 7542 7543 #define CHICKEN_TRANS_A _MMIO(0x420c0) 7544 #define CHICKEN_TRANS_B _MMIO(0x420c4) 7545 #define CHICKEN_TRANS_C _MMIO(0x420c8) 7546 #define CHICKEN_TRANS_EDP _MMIO(0x420cc) 7547 #define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK and CNL+ */ 7548 #define DDI_TRAINING_OVERRIDE_ENABLE (1 << 19) 7549 #define DDI_TRAINING_OVERRIDE_VALUE (1 << 18) 7550 #define DDIE_TRAINING_OVERRIDE_ENABLE (1 << 17) /* CHICKEN_TRANS_A only */ 7551 #define DDIE_TRAINING_OVERRIDE_VALUE (1 << 16) /* CHICKEN_TRANS_A only */ 7552 #define PSR2_ADD_VERTICAL_LINE_COUNT (1 << 15) 7553 #define PSR2_VSC_ENABLE_PROG_HEADER (1 << 12) 7554 7555 #define DISP_ARB_CTL _MMIO(0x45000) 7556 #define DISP_FBC_MEMORY_WAKE (1 << 31) 7557 #define DISP_TILE_SURFACE_SWIZZLING (1 << 13) 7558 #define DISP_FBC_WM_DIS (1 << 15) 7559 #define DISP_ARB_CTL2 _MMIO(0x45004) 7560 #define DISP_DATA_PARTITION_5_6 (1 << 6) 7561 #define DISP_IPC_ENABLE (1 << 3) 7562 #define DBUF_CTL _MMIO(0x45008) 7563 #define DBUF_CTL_S1 _MMIO(0x45008) 7564 #define DBUF_CTL_S2 _MMIO(0x44FE8) 7565 #define DBUF_POWER_REQUEST (1 << 31) 7566 #define DBUF_POWER_STATE (1 << 30) 7567 #define GEN7_MSG_CTL _MMIO(0x45010) 7568 #define WAIT_FOR_PCH_RESET_ACK (1 << 1) 7569 #define WAIT_FOR_PCH_FLR_ACK (1 << 0) 7570 #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) 7571 #define RESET_PCH_HANDSHAKE_ENABLE (1 << 4) 7572 7573 #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430) 7574 #define SKL_SELECT_ALTERNATE_DC_EXIT (1 << 30) 7575 #define MASK_WAKEMEM (1 << 13) 7576 #define CNL_DDI_CLOCK_REG_ACCESS_ON (1 << 7) 7577 7578 #define SKL_DFSM _MMIO(0x51000) 7579 #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23) 7580 #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23) 7581 #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23) 7582 #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23) 7583 #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23) 7584 #define SKL_DFSM_PIPE_A_DISABLE (1 << 30) 7585 #define SKL_DFSM_PIPE_B_DISABLE (1 << 21) 7586 #define SKL_DFSM_PIPE_C_DISABLE (1 << 28) 7587 7588 #define SKL_DSSM _MMIO(0x51004) 7589 #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31) 7590 #define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29) 7591 #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29) 7592 #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29) 7593 #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29) 7594 7595 #define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0) 7596 #define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1 << 14) 7597 7598 #define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4) 7599 #define GEN9_TSG_BARRIER_ACK_DISABLE (1 << 8) 7600 #define GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE (1 << 10) 7601 7602 #define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec) 7603 #define GEN9_CTX_PREEMPT_REG _MMIO(0x2248) 7604 #define GEN8_CS_CHICKEN1 _MMIO(0x2580) 7605 #define GEN9_PREEMPT_3D_OBJECT_LEVEL (1 << 0) 7606 #define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1)) 7607 #define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 0) 7608 #define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 1) 7609 #define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(1, 0) 7610 #define GEN9_PREEMPT_GPGPU_LEVEL_MASK GEN9_PREEMPT_GPGPU_LEVEL(1, 1) 7611 7612 /* GEN7 chicken */ 7613 #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010) 7614 #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1 << 10) | (1 << 26)) 7615 #define GEN9_RHWO_OPTIMIZATION_DISABLE (1 << 14) 7616 7617 #define COMMON_SLICE_CHICKEN2 _MMIO(0x7014) 7618 #define GEN9_PBE_COMPRESSED_HASH_SELECTION (1 << 13) 7619 #define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1 << 12) 7620 #define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1 << 8) 7621 #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1 << 0) 7622 7623 #define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304) 7624 #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC (1 << 11) 7625 7626 #define HIZ_CHICKEN _MMIO(0x7018) 7627 # define CHV_HZ_8X8_MODE_IN_1X (1 << 15) 7628 # define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE (1 << 3) 7629 7630 #define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308) 7631 #define DISABLE_PIXEL_MASK_CAMMING (1 << 14) 7632 7633 #define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c) 7634 #define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11) 7635 7636 #define GEN7_SARCHKMD _MMIO(0xB000) 7637 #define GEN7_DISABLE_DEMAND_PREFETCH (1 << 31) 7638 #define GEN7_DISABLE_SAMPLER_PREFETCH (1 << 30) 7639 7640 #define GEN7_L3SQCREG1 _MMIO(0xB010) 7641 #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000 7642 7643 #define GEN8_L3SQCREG1 _MMIO(0xB100) 7644 /* 7645 * Note that on CHV the following has an off-by-one error wrt. to BSpec. 7646 * Using the formula in BSpec leads to a hang, while the formula here works 7647 * fine and matches the formulas for all other platforms. A BSpec change 7648 * request has been filed to clarify this. 7649 */ 7650 #define L3_GENERAL_PRIO_CREDITS(x) (((x) >> 1) << 19) 7651 #define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14) 7652 #define L3_PRIO_CREDITS_MASK ((0x1f << 19) | (0x1f << 14)) 7653 7654 #define GEN7_L3CNTLREG1 _MMIO(0xB01C) 7655 #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C 7656 #define GEN7_L3AGDIS (1 << 19) 7657 #define GEN7_L3CNTLREG2 _MMIO(0xB020) 7658 #define GEN7_L3CNTLREG3 _MMIO(0xB024) 7659 7660 #define GEN7_L3_CHICKEN_MODE_REGISTER _MMIO(0xB030) 7661 #define GEN7_WA_L3_CHICKEN_MODE 0x20000000 7662 #define GEN10_L3_CHICKEN_MODE_REGISTER _MMIO(0xB114) 7663 #define GEN11_I2M_WRITE_DISABLE (1 << 28) 7664 7665 #define GEN7_L3SQCREG4 _MMIO(0xb034) 7666 #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1 << 27) 7667 7668 #define GEN8_L3SQCREG4 _MMIO(0xb118) 7669 #define GEN11_LQSC_CLEAN_EVICT_DISABLE (1 << 6) 7670 #define GEN8_LQSC_RO_PERF_DIS (1 << 27) 7671 #define GEN8_LQSC_FLUSH_COHERENT_LINES (1 << 21) 7672 7673 /* GEN8 chicken */ 7674 #define HDC_CHICKEN0 _MMIO(0x7300) 7675 #define CNL_HDC_CHICKEN0 _MMIO(0xE5F0) 7676 #define ICL_HDC_MODE _MMIO(0xE5F4) 7677 #define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1 << 15) 7678 #define HDC_FENCE_DEST_SLM_DISABLE (1 << 14) 7679 #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1 << 11) 7680 #define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1 << 5) 7681 #define HDC_FORCE_NON_COHERENT (1 << 4) 7682 #define HDC_BARRIER_PERFORMANCE_DISABLE (1 << 10) 7683 7684 #define GEN8_HDC_CHICKEN1 _MMIO(0x7304) 7685 7686 /* GEN9 chicken */ 7687 #define SLICE_ECO_CHICKEN0 _MMIO(0x7308) 7688 #define PIXEL_MASK_CAMMING_DISABLE (1 << 14) 7689 7690 #define GEN9_WM_CHICKEN3 _MMIO(0x5588) 7691 #define GEN9_FACTOR_IN_CLR_VAL_HIZ (1 << 9) 7692 7693 /* WaCatErrorRejectionIssue */ 7694 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030) 7695 #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1 << 11) 7696 7697 #define HSW_SCRATCH1 _MMIO(0xb038) 7698 #define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1 << 27) 7699 7700 #define BDW_SCRATCH1 _MMIO(0xb11c) 7701 #define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1 << 2) 7702 7703 /*GEN11 chicken */ 7704 #define _PIPEA_CHICKEN 0x70038 7705 #define _PIPEB_CHICKEN 0x71038 7706 #define _PIPEC_CHICKEN 0x72038 7707 #define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\ 7708 _PIPEB_CHICKEN) 7709 #define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU (1 << 15) 7710 #define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7) 7711 7712 /* PCH */ 7713 7714 #define PCH_DISPLAY_BASE 0xc0000u 7715 7716 /* south display engine interrupt: IBX */ 7717 #define SDE_AUDIO_POWER_D (1 << 27) 7718 #define SDE_AUDIO_POWER_C (1 << 26) 7719 #define SDE_AUDIO_POWER_B (1 << 25) 7720 #define SDE_AUDIO_POWER_SHIFT (25) 7721 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) 7722 #define SDE_GMBUS (1 << 24) 7723 #define SDE_AUDIO_HDCP_TRANSB (1 << 23) 7724 #define SDE_AUDIO_HDCP_TRANSA (1 << 22) 7725 #define SDE_AUDIO_HDCP_MASK (3 << 22) 7726 #define SDE_AUDIO_TRANSB (1 << 21) 7727 #define SDE_AUDIO_TRANSA (1 << 20) 7728 #define SDE_AUDIO_TRANS_MASK (3 << 20) 7729 #define SDE_POISON (1 << 19) 7730 /* 18 reserved */ 7731 #define SDE_FDI_RXB (1 << 17) 7732 #define SDE_FDI_RXA (1 << 16) 7733 #define SDE_FDI_MASK (3 << 16) 7734 #define SDE_AUXD (1 << 15) 7735 #define SDE_AUXC (1 << 14) 7736 #define SDE_AUXB (1 << 13) 7737 #define SDE_AUX_MASK (7 << 13) 7738 /* 12 reserved */ 7739 #define SDE_CRT_HOTPLUG (1 << 11) 7740 #define SDE_PORTD_HOTPLUG (1 << 10) 7741 #define SDE_PORTC_HOTPLUG (1 << 9) 7742 #define SDE_PORTB_HOTPLUG (1 << 8) 7743 #define SDE_SDVOB_HOTPLUG (1 << 6) 7744 #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \ 7745 SDE_SDVOB_HOTPLUG | \ 7746 SDE_PORTB_HOTPLUG | \ 7747 SDE_PORTC_HOTPLUG | \ 7748 SDE_PORTD_HOTPLUG) 7749 #define SDE_TRANSB_CRC_DONE (1 << 5) 7750 #define SDE_TRANSB_CRC_ERR (1 << 4) 7751 #define SDE_TRANSB_FIFO_UNDER (1 << 3) 7752 #define SDE_TRANSA_CRC_DONE (1 << 2) 7753 #define SDE_TRANSA_CRC_ERR (1 << 1) 7754 #define SDE_TRANSA_FIFO_UNDER (1 << 0) 7755 #define SDE_TRANS_MASK (0x3f) 7756 7757 /* south display engine interrupt: CPT - CNP */ 7758 #define SDE_AUDIO_POWER_D_CPT (1 << 31) 7759 #define SDE_AUDIO_POWER_C_CPT (1 << 30) 7760 #define SDE_AUDIO_POWER_B_CPT (1 << 29) 7761 #define SDE_AUDIO_POWER_SHIFT_CPT 29 7762 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29) 7763 #define SDE_AUXD_CPT (1 << 27) 7764 #define SDE_AUXC_CPT (1 << 26) 7765 #define SDE_AUXB_CPT (1 << 25) 7766 #define SDE_AUX_MASK_CPT (7 << 25) 7767 #define SDE_PORTE_HOTPLUG_SPT (1 << 25) 7768 #define SDE_PORTA_HOTPLUG_SPT (1 << 24) 7769 #define SDE_PORTD_HOTPLUG_CPT (1 << 23) 7770 #define SDE_PORTC_HOTPLUG_CPT (1 << 22) 7771 #define SDE_PORTB_HOTPLUG_CPT (1 << 21) 7772 #define SDE_CRT_HOTPLUG_CPT (1 << 19) 7773 #define SDE_SDVOB_HOTPLUG_CPT (1 << 18) 7774 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ 7775 SDE_SDVOB_HOTPLUG_CPT | \ 7776 SDE_PORTD_HOTPLUG_CPT | \ 7777 SDE_PORTC_HOTPLUG_CPT | \ 7778 SDE_PORTB_HOTPLUG_CPT) 7779 #define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \ 7780 SDE_PORTD_HOTPLUG_CPT | \ 7781 SDE_PORTC_HOTPLUG_CPT | \ 7782 SDE_PORTB_HOTPLUG_CPT | \ 7783 SDE_PORTA_HOTPLUG_SPT) 7784 #define SDE_GMBUS_CPT (1 << 17) 7785 #define SDE_ERROR_CPT (1 << 16) 7786 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10) 7787 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9) 7788 #define SDE_FDI_RXC_CPT (1 << 8) 7789 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6) 7790 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5) 7791 #define SDE_FDI_RXB_CPT (1 << 4) 7792 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2) 7793 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1) 7794 #define SDE_FDI_RXA_CPT (1 << 0) 7795 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \ 7796 SDE_AUDIO_CP_REQ_B_CPT | \ 7797 SDE_AUDIO_CP_REQ_A_CPT) 7798 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \ 7799 SDE_AUDIO_CP_CHG_B_CPT | \ 7800 SDE_AUDIO_CP_CHG_A_CPT) 7801 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \ 7802 SDE_FDI_RXB_CPT | \ 7803 SDE_FDI_RXA_CPT) 7804 7805 /* south display engine interrupt: ICP */ 7806 #define SDE_TC4_HOTPLUG_ICP (1 << 27) 7807 #define SDE_TC3_HOTPLUG_ICP (1 << 26) 7808 #define SDE_TC2_HOTPLUG_ICP (1 << 25) 7809 #define SDE_TC1_HOTPLUG_ICP (1 << 24) 7810 #define SDE_GMBUS_ICP (1 << 23) 7811 #define SDE_DDIB_HOTPLUG_ICP (1 << 17) 7812 #define SDE_DDIA_HOTPLUG_ICP (1 << 16) 7813 #define SDE_TC_HOTPLUG_ICP(tc_port) (1 << ((tc_port) + 24)) 7814 #define SDE_DDI_HOTPLUG_ICP(port) (1 << ((port) + 16)) 7815 #define SDE_DDI_MASK_ICP (SDE_DDIB_HOTPLUG_ICP | \ 7816 SDE_DDIA_HOTPLUG_ICP) 7817 #define SDE_TC_MASK_ICP (SDE_TC4_HOTPLUG_ICP | \ 7818 SDE_TC3_HOTPLUG_ICP | \ 7819 SDE_TC2_HOTPLUG_ICP | \ 7820 SDE_TC1_HOTPLUG_ICP) 7821 7822 #define SDEISR _MMIO(0xc4000) 7823 #define SDEIMR _MMIO(0xc4004) 7824 #define SDEIIR _MMIO(0xc4008) 7825 #define SDEIER _MMIO(0xc400c) 7826 7827 #define SERR_INT _MMIO(0xc4040) 7828 #define SERR_INT_POISON (1 << 31) 7829 #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) 7830 7831 /* digital port hotplug */ 7832 #define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */ 7833 #define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */ 7834 #define BXT_DDIA_HPD_INVERT (1 << 27) 7835 #define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */ 7836 #define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */ 7837 #define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */ 7838 #define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */ 7839 #define PORTD_HOTPLUG_ENABLE (1 << 20) 7840 #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */ 7841 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */ 7842 #define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */ 7843 #define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */ 7844 #define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */ 7845 #define PORTD_HOTPLUG_STATUS_MASK (3 << 16) 7846 #define PORTD_HOTPLUG_NO_DETECT (0 << 16) 7847 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) 7848 #define PORTD_HOTPLUG_LONG_DETECT (2 << 16) 7849 #define PORTC_HOTPLUG_ENABLE (1 << 12) 7850 #define BXT_DDIC_HPD_INVERT (1 << 11) 7851 #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */ 7852 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */ 7853 #define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */ 7854 #define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */ 7855 #define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */ 7856 #define PORTC_HOTPLUG_STATUS_MASK (3 << 8) 7857 #define PORTC_HOTPLUG_NO_DETECT (0 << 8) 7858 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) 7859 #define PORTC_HOTPLUG_LONG_DETECT (2 << 8) 7860 #define PORTB_HOTPLUG_ENABLE (1 << 4) 7861 #define BXT_DDIB_HPD_INVERT (1 << 3) 7862 #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */ 7863 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */ 7864 #define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */ 7865 #define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */ 7866 #define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */ 7867 #define PORTB_HOTPLUG_STATUS_MASK (3 << 0) 7868 #define PORTB_HOTPLUG_NO_DETECT (0 << 0) 7869 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) 7870 #define PORTB_HOTPLUG_LONG_DETECT (2 << 0) 7871 #define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \ 7872 BXT_DDIB_HPD_INVERT | \ 7873 BXT_DDIC_HPD_INVERT) 7874 7875 #define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */ 7876 #define PORTE_HOTPLUG_ENABLE (1 << 4) 7877 #define PORTE_HOTPLUG_STATUS_MASK (3 << 0) 7878 #define PORTE_HOTPLUG_NO_DETECT (0 << 0) 7879 #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0) 7880 #define PORTE_HOTPLUG_LONG_DETECT (2 << 0) 7881 7882 /* This register is a reuse of PCH_PORT_HOTPLUG register. The 7883 * functionality covered in PCH_PORT_HOTPLUG is split into 7884 * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC. 7885 */ 7886 7887 #define SHOTPLUG_CTL_DDI _MMIO(0xc4030) 7888 #define ICP_DDIB_HPD_ENABLE (1 << 7) 7889 #define ICP_DDIB_HPD_STATUS_MASK (3 << 4) 7890 #define ICP_DDIB_HPD_NO_DETECT (0 << 4) 7891 #define ICP_DDIB_HPD_SHORT_DETECT (1 << 4) 7892 #define ICP_DDIB_HPD_LONG_DETECT (2 << 4) 7893 #define ICP_DDIB_HPD_SHORT_LONG_DETECT (3 << 4) 7894 #define ICP_DDIA_HPD_ENABLE (1 << 3) 7895 #define ICP_DDIA_HPD_OP_DRIVE_1 (1 << 2) 7896 #define ICP_DDIA_HPD_STATUS_MASK (3 << 0) 7897 #define ICP_DDIA_HPD_NO_DETECT (0 << 0) 7898 #define ICP_DDIA_HPD_SHORT_DETECT (1 << 0) 7899 #define ICP_DDIA_HPD_LONG_DETECT (2 << 0) 7900 #define ICP_DDIA_HPD_SHORT_LONG_DETECT (3 << 0) 7901 7902 #define SHOTPLUG_CTL_TC _MMIO(0xc4034) 7903 #define ICP_TC_HPD_ENABLE(tc_port) (8 << (tc_port) * 4) 7904 /* Icelake DSC Rate Control Range Parameter Registers */ 7905 #define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240) 7906 #define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4) 7907 #define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40) 7908 #define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4) 7909 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208) 7910 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4) 7911 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308) 7912 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4) 7913 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408) 7914 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4) 7915 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508) 7916 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4) 7917 #define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7918 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \ 7919 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC) 7920 #define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7921 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \ 7922 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC) 7923 #define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7924 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \ 7925 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC) 7926 #define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7927 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \ 7928 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC) 7929 #define RC_BPG_OFFSET_SHIFT 10 7930 #define RC_MAX_QP_SHIFT 5 7931 #define RC_MIN_QP_SHIFT 0 7932 7933 #define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248) 7934 #define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4) 7935 #define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48) 7936 #define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4) 7937 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210) 7938 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4) 7939 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310) 7940 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4) 7941 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410) 7942 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4) 7943 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510) 7944 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4) 7945 #define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7946 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \ 7947 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC) 7948 #define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7949 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \ 7950 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC) 7951 #define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7952 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \ 7953 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC) 7954 #define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7955 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \ 7956 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC) 7957 7958 #define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250) 7959 #define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4) 7960 #define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50) 7961 #define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4) 7962 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218) 7963 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4) 7964 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318) 7965 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4) 7966 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418) 7967 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4) 7968 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518) 7969 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4) 7970 #define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7971 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \ 7972 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC) 7973 #define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7974 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \ 7975 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC) 7976 #define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7977 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \ 7978 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC) 7979 #define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7980 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \ 7981 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC) 7982 7983 #define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258) 7984 #define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4) 7985 #define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58) 7986 #define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4) 7987 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220) 7988 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4) 7989 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320) 7990 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4) 7991 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420) 7992 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4) 7993 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520) 7994 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4) 7995 #define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7996 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \ 7997 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC) 7998 #define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7999 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \ 8000 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC) 8001 #define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8002 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \ 8003 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC) 8004 #define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8005 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \ 8006 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC) 8007 8008 #define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4) 8009 #define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4) 8010 8011 #define _PCH_DPLL_A 0xc6014 8012 #define _PCH_DPLL_B 0xc6018 8013 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) 8014 8015 #define _PCH_FPA0 0xc6040 8016 #define FP_CB_TUNE (0x3 << 22) 8017 #define _PCH_FPA1 0xc6044 8018 #define _PCH_FPB0 0xc6048 8019 #define _PCH_FPB1 0xc604c 8020 #define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0) 8021 #define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1) 8022 8023 #define PCH_DPLL_TEST _MMIO(0xc606c) 8024 8025 #define PCH_DREF_CONTROL _MMIO(0xC6200) 8026 #define DREF_CONTROL_MASK 0x7fc3 8027 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13) 8028 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13) 8029 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13) 8030 #define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13) 8031 #define DREF_SSC_SOURCE_DISABLE (0 << 11) 8032 #define DREF_SSC_SOURCE_ENABLE (2 << 11) 8033 #define DREF_SSC_SOURCE_MASK (3 << 11) 8034 #define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9) 8035 #define DREF_NONSPREAD_CK505_ENABLE (1 << 9) 8036 #define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9) 8037 #define DREF_NONSPREAD_SOURCE_MASK (3 << 9) 8038 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7) 8039 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7) 8040 #define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7) 8041 #define DREF_SSC4_DOWNSPREAD (0 << 6) 8042 #define DREF_SSC4_CENTERSPREAD (1 << 6) 8043 #define DREF_SSC1_DISABLE (0 << 1) 8044 #define DREF_SSC1_ENABLE (1 << 1) 8045 #define DREF_SSC4_DISABLE (0) 8046 #define DREF_SSC4_ENABLE (1) 8047 8048 #define PCH_RAWCLK_FREQ _MMIO(0xc6204) 8049 #define FDL_TP1_TIMER_SHIFT 12 8050 #define FDL_TP1_TIMER_MASK (3 << 12) 8051 #define FDL_TP2_TIMER_SHIFT 10 8052 #define FDL_TP2_TIMER_MASK (3 << 10) 8053 #define RAWCLK_FREQ_MASK 0x3ff 8054 #define CNP_RAWCLK_DIV_MASK (0x3ff << 16) 8055 #define CNP_RAWCLK_DIV(div) ((div) << 16) 8056 #define CNP_RAWCLK_FRAC_MASK (0xf << 26) 8057 #define CNP_RAWCLK_DEN(den) ((den) << 26) 8058 #define ICP_RAWCLK_NUM(num) ((num) << 11) 8059 8060 #define PCH_DPLL_TMR_CFG _MMIO(0xc6208) 8061 8062 #define PCH_SSC4_PARMS _MMIO(0xc6210) 8063 #define PCH_SSC4_AUX_PARMS _MMIO(0xc6214) 8064 8065 #define PCH_DPLL_SEL _MMIO(0xc7000) 8066 #define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4)) 8067 #define TRANS_DPLLA_SEL(pipe) 0 8068 #define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3)) 8069 8070 /* transcoder */ 8071 8072 #define _PCH_TRANS_HTOTAL_A 0xe0000 8073 #define TRANS_HTOTAL_SHIFT 16 8074 #define TRANS_HACTIVE_SHIFT 0 8075 #define _PCH_TRANS_HBLANK_A 0xe0004 8076 #define TRANS_HBLANK_END_SHIFT 16 8077 #define TRANS_HBLANK_START_SHIFT 0 8078 #define _PCH_TRANS_HSYNC_A 0xe0008 8079 #define TRANS_HSYNC_END_SHIFT 16 8080 #define TRANS_HSYNC_START_SHIFT 0 8081 #define _PCH_TRANS_VTOTAL_A 0xe000c 8082 #define TRANS_VTOTAL_SHIFT 16 8083 #define TRANS_VACTIVE_SHIFT 0 8084 #define _PCH_TRANS_VBLANK_A 0xe0010 8085 #define TRANS_VBLANK_END_SHIFT 16 8086 #define TRANS_VBLANK_START_SHIFT 0 8087 #define _PCH_TRANS_VSYNC_A 0xe0014 8088 #define TRANS_VSYNC_END_SHIFT 16 8089 #define TRANS_VSYNC_START_SHIFT 0 8090 #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028 8091 8092 #define _PCH_TRANSA_DATA_M1 0xe0030 8093 #define _PCH_TRANSA_DATA_N1 0xe0034 8094 #define _PCH_TRANSA_DATA_M2 0xe0038 8095 #define _PCH_TRANSA_DATA_N2 0xe003c 8096 #define _PCH_TRANSA_LINK_M1 0xe0040 8097 #define _PCH_TRANSA_LINK_N1 0xe0044 8098 #define _PCH_TRANSA_LINK_M2 0xe0048 8099 #define _PCH_TRANSA_LINK_N2 0xe004c 8100 8101 /* Per-transcoder DIP controls (PCH) */ 8102 #define _VIDEO_DIP_CTL_A 0xe0200 8103 #define _VIDEO_DIP_DATA_A 0xe0208 8104 #define _VIDEO_DIP_GCP_A 0xe0210 8105 #define GCP_COLOR_INDICATION (1 << 2) 8106 #define GCP_DEFAULT_PHASE_ENABLE (1 << 1) 8107 #define GCP_AV_MUTE (1 << 0) 8108 8109 #define _VIDEO_DIP_CTL_B 0xe1200 8110 #define _VIDEO_DIP_DATA_B 0xe1208 8111 #define _VIDEO_DIP_GCP_B 0xe1210 8112 8113 #define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) 8114 #define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) 8115 #define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) 8116 8117 /* Per-transcoder DIP controls (VLV) */ 8118 #define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200) 8119 #define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208) 8120 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210) 8121 8122 #define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170) 8123 #define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174) 8124 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178) 8125 8126 #define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0) 8127 #define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4) 8128 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8) 8129 8130 #define VLV_TVIDEO_DIP_CTL(pipe) \ 8131 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \ 8132 _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C) 8133 #define VLV_TVIDEO_DIP_DATA(pipe) \ 8134 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \ 8135 _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C) 8136 #define VLV_TVIDEO_DIP_GCP(pipe) \ 8137 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \ 8138 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C) 8139 8140 /* Haswell DIP controls */ 8141 8142 #define _HSW_VIDEO_DIP_CTL_A 0x60200 8143 #define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220 8144 #define _HSW_VIDEO_DIP_VS_DATA_A 0x60260 8145 #define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 8146 #define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 8147 #define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320 8148 #define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240 8149 #define _HSW_VIDEO_DIP_VS_ECC_A 0x60280 8150 #define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 8151 #define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300 8152 #define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344 8153 #define _HSW_VIDEO_DIP_GCP_A 0x60210 8154 8155 #define _HSW_VIDEO_DIP_CTL_B 0x61200 8156 #define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220 8157 #define _HSW_VIDEO_DIP_VS_DATA_B 0x61260 8158 #define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 8159 #define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 8160 #define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320 8161 #define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240 8162 #define _HSW_VIDEO_DIP_VS_ECC_B 0x61280 8163 #define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 8164 #define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300 8165 #define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344 8166 #define _HSW_VIDEO_DIP_GCP_B 0x61210 8167 8168 /* Icelake PPS_DATA and _ECC DIP Registers. 8169 * These are available for transcoders B,C and eDP. 8170 * Adding the _A so as to reuse the _MMIO_TRANS2 8171 * definition, with which it offsets to the right location. 8172 */ 8173 8174 #define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350 8175 #define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350 8176 #define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4 8177 #define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4 8178 8179 #define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A) 8180 #define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A) 8181 #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4) 8182 #define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4) 8183 #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4) 8184 #define HSW_TVIDEO_DIP_GMP_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4) 8185 #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4) 8186 #define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4) 8187 #define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4) 8188 8189 #define _HSW_STEREO_3D_CTL_A 0x70020 8190 #define S3D_ENABLE (1 << 31) 8191 #define _HSW_STEREO_3D_CTL_B 0x71020 8192 8193 #define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A) 8194 8195 #define _PCH_TRANS_HTOTAL_B 0xe1000 8196 #define _PCH_TRANS_HBLANK_B 0xe1004 8197 #define _PCH_TRANS_HSYNC_B 0xe1008 8198 #define _PCH_TRANS_VTOTAL_B 0xe100c 8199 #define _PCH_TRANS_VBLANK_B 0xe1010 8200 #define _PCH_TRANS_VSYNC_B 0xe1014 8201 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028 8202 8203 #define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B) 8204 #define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B) 8205 #define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B) 8206 #define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B) 8207 #define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B) 8208 #define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B) 8209 #define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B) 8210 8211 #define _PCH_TRANSB_DATA_M1 0xe1030 8212 #define _PCH_TRANSB_DATA_N1 0xe1034 8213 #define _PCH_TRANSB_DATA_M2 0xe1038 8214 #define _PCH_TRANSB_DATA_N2 0xe103c 8215 #define _PCH_TRANSB_LINK_M1 0xe1040 8216 #define _PCH_TRANSB_LINK_N1 0xe1044 8217 #define _PCH_TRANSB_LINK_M2 0xe1048 8218 #define _PCH_TRANSB_LINK_N2 0xe104c 8219 8220 #define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1) 8221 #define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1) 8222 #define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2) 8223 #define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2) 8224 #define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1) 8225 #define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1) 8226 #define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2) 8227 #define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2) 8228 8229 #define _PCH_TRANSACONF 0xf0008 8230 #define _PCH_TRANSBCONF 0xf1008 8231 #define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF) 8232 #define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */ 8233 #define TRANS_DISABLE (0 << 31) 8234 #define TRANS_ENABLE (1 << 31) 8235 #define TRANS_STATE_MASK (1 << 30) 8236 #define TRANS_STATE_DISABLE (0 << 30) 8237 #define TRANS_STATE_ENABLE (1 << 30) 8238 #define TRANS_FSYNC_DELAY_HB1 (0 << 27) 8239 #define TRANS_FSYNC_DELAY_HB2 (1 << 27) 8240 #define TRANS_FSYNC_DELAY_HB3 (2 << 27) 8241 #define TRANS_FSYNC_DELAY_HB4 (3 << 27) 8242 #define TRANS_INTERLACE_MASK (7 << 21) 8243 #define TRANS_PROGRESSIVE (0 << 21) 8244 #define TRANS_INTERLACED (3 << 21) 8245 #define TRANS_LEGACY_INTERLACED_ILK (2 << 21) 8246 #define TRANS_8BPC (0 << 5) 8247 #define TRANS_10BPC (1 << 5) 8248 #define TRANS_6BPC (2 << 5) 8249 #define TRANS_12BPC (3 << 5) 8250 8251 #define _TRANSA_CHICKEN1 0xf0060 8252 #define _TRANSB_CHICKEN1 0xf1060 8253 #define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) 8254 #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE (1 << 10) 8255 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1 << 4) 8256 #define _TRANSA_CHICKEN2 0xf0064 8257 #define _TRANSB_CHICKEN2 0xf1064 8258 #define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) 8259 #define TRANS_CHICKEN2_TIMING_OVERRIDE (1 << 31) 8260 #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1 << 29) 8261 #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3 << 27) 8262 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1 << 26) 8263 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1 << 25) 8264 8265 #define SOUTH_CHICKEN1 _MMIO(0xc2000) 8266 #define FDIA_PHASE_SYNC_SHIFT_OVR 19 8267 #define FDIA_PHASE_SYNC_SHIFT_EN 18 8268 #define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) 8269 #define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) 8270 #define FDI_BC_BIFURCATION_SELECT (1 << 12) 8271 #define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8) 8272 #define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8) 8273 #define SPT_PWM_GRANULARITY (1 << 0) 8274 #define SOUTH_CHICKEN2 _MMIO(0xc2004) 8275 #define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13) 8276 #define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12) 8277 #define LPT_PWM_GRANULARITY (1 << 5) 8278 #define DPLS_EDP_PPS_FIX_DIS (1 << 0) 8279 8280 #define _FDI_RXA_CHICKEN 0xc200c 8281 #define _FDI_RXB_CHICKEN 0xc2010 8282 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1 << 1) 8283 #define FDI_RX_PHASE_SYNC_POINTER_EN (1 << 0) 8284 #define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) 8285 8286 #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020) 8287 #define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31) 8288 #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30) 8289 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29) 8290 #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14) 8291 #define CNP_PWM_CGE_GATING_DISABLE (1 << 13) 8292 #define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12) 8293 8294 /* CPU: FDI_TX */ 8295 #define _FDI_TXA_CTL 0x60100 8296 #define _FDI_TXB_CTL 0x61100 8297 #define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) 8298 #define FDI_TX_DISABLE (0 << 31) 8299 #define FDI_TX_ENABLE (1 << 31) 8300 #define FDI_LINK_TRAIN_PATTERN_1 (0 << 28) 8301 #define FDI_LINK_TRAIN_PATTERN_2 (1 << 28) 8302 #define FDI_LINK_TRAIN_PATTERN_IDLE (2 << 28) 8303 #define FDI_LINK_TRAIN_NONE (3 << 28) 8304 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0 << 25) 8305 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1 << 25) 8306 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2 << 25) 8307 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3 << 25) 8308 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22) 8309 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22) 8310 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2 << 22) 8311 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3 << 22) 8312 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. 8313 SNB has different settings. */ 8314 /* SNB A-stepping */ 8315 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) 8316 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22) 8317 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22) 8318 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22) 8319 /* SNB B-stepping */ 8320 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0 << 22) 8321 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a << 22) 8322 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39 << 22) 8323 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38 << 22) 8324 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f << 22) 8325 #define FDI_DP_PORT_WIDTH_SHIFT 19 8326 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT) 8327 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT) 8328 #define FDI_TX_ENHANCE_FRAME_ENABLE (1 << 18) 8329 /* Ironlake: hardwired to 1 */ 8330 #define FDI_TX_PLL_ENABLE (1 << 14) 8331 8332 /* Ivybridge has different bits for lolz */ 8333 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0 << 8) 8334 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1 << 8) 8335 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2 << 8) 8336 #define FDI_LINK_TRAIN_NONE_IVB (3 << 8) 8337 8338 /* both Tx and Rx */ 8339 #define FDI_COMPOSITE_SYNC (1 << 11) 8340 #define FDI_LINK_TRAIN_AUTO (1 << 10) 8341 #define FDI_SCRAMBLING_ENABLE (0 << 7) 8342 #define FDI_SCRAMBLING_DISABLE (1 << 7) 8343 8344 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */ 8345 #define _FDI_RXA_CTL 0xf000c 8346 #define _FDI_RXB_CTL 0xf100c 8347 #define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) 8348 #define FDI_RX_ENABLE (1 << 31) 8349 /* train, dp width same as FDI_TX */ 8350 #define FDI_FS_ERRC_ENABLE (1 << 27) 8351 #define FDI_FE_ERRC_ENABLE (1 << 26) 8352 #define FDI_RX_POLARITY_REVERSED_LPT (1 << 16) 8353 #define FDI_8BPC (0 << 16) 8354 #define FDI_10BPC (1 << 16) 8355 #define FDI_6BPC (2 << 16) 8356 #define FDI_12BPC (3 << 16) 8357 #define FDI_RX_LINK_REVERSAL_OVERRIDE (1 << 15) 8358 #define FDI_DMI_LINK_REVERSE_MASK (1 << 14) 8359 #define FDI_RX_PLL_ENABLE (1 << 13) 8360 #define FDI_FS_ERR_CORRECT_ENABLE (1 << 11) 8361 #define FDI_FE_ERR_CORRECT_ENABLE (1 << 10) 8362 #define FDI_FS_ERR_REPORT_ENABLE (1 << 9) 8363 #define FDI_FE_ERR_REPORT_ENABLE (1 << 8) 8364 #define FDI_RX_ENHANCE_FRAME_ENABLE (1 << 6) 8365 #define FDI_PCDCLK (1 << 4) 8366 /* CPT */ 8367 #define FDI_AUTO_TRAINING (1 << 10) 8368 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0 << 8) 8369 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1 << 8) 8370 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2 << 8) 8371 #define FDI_LINK_TRAIN_NORMAL_CPT (3 << 8) 8372 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3 << 8) 8373 8374 #define _FDI_RXA_MISC 0xf0010 8375 #define _FDI_RXB_MISC 0xf1010 8376 #define FDI_RX_PWRDN_LANE1_MASK (3 << 26) 8377 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x) << 26) 8378 #define FDI_RX_PWRDN_LANE0_MASK (3 << 24) 8379 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x) << 24) 8380 #define FDI_RX_TP1_TO_TP2_48 (2 << 20) 8381 #define FDI_RX_TP1_TO_TP2_64 (3 << 20) 8382 #define FDI_RX_FDI_DELAY_90 (0x90 << 0) 8383 #define FDI_RX_MISC(pipe) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) 8384 8385 #define _FDI_RXA_TUSIZE1 0xf0030 8386 #define _FDI_RXA_TUSIZE2 0xf0038 8387 #define _FDI_RXB_TUSIZE1 0xf1030 8388 #define _FDI_RXB_TUSIZE2 0xf1038 8389 #define FDI_RX_TUSIZE1(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) 8390 #define FDI_RX_TUSIZE2(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) 8391 8392 /* FDI_RX interrupt register format */ 8393 #define FDI_RX_INTER_LANE_ALIGN (1 << 10) 8394 #define FDI_RX_SYMBOL_LOCK (1 << 9) /* train 2 */ 8395 #define FDI_RX_BIT_LOCK (1 << 8) /* train 1 */ 8396 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1 << 7) 8397 #define FDI_RX_FS_CODE_ERR (1 << 6) 8398 #define FDI_RX_FE_CODE_ERR (1 << 5) 8399 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1 << 4) 8400 #define FDI_RX_HDCP_LINK_FAIL (1 << 3) 8401 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1 << 2) 8402 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1 << 1) 8403 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1 << 0) 8404 8405 #define _FDI_RXA_IIR 0xf0014 8406 #define _FDI_RXA_IMR 0xf0018 8407 #define _FDI_RXB_IIR 0xf1014 8408 #define _FDI_RXB_IMR 0xf1018 8409 #define FDI_RX_IIR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) 8410 #define FDI_RX_IMR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR) 8411 8412 #define FDI_PLL_CTL_1 _MMIO(0xfe000) 8413 #define FDI_PLL_CTL_2 _MMIO(0xfe004) 8414 8415 #define PCH_LVDS _MMIO(0xe1180) 8416 #define LVDS_DETECTED (1 << 1) 8417 8418 #define _PCH_DP_B 0xe4100 8419 #define PCH_DP_B _MMIO(_PCH_DP_B) 8420 #define _PCH_DPB_AUX_CH_CTL 0xe4110 8421 #define _PCH_DPB_AUX_CH_DATA1 0xe4114 8422 #define _PCH_DPB_AUX_CH_DATA2 0xe4118 8423 #define _PCH_DPB_AUX_CH_DATA3 0xe411c 8424 #define _PCH_DPB_AUX_CH_DATA4 0xe4120 8425 #define _PCH_DPB_AUX_CH_DATA5 0xe4124 8426 8427 #define _PCH_DP_C 0xe4200 8428 #define PCH_DP_C _MMIO(_PCH_DP_C) 8429 #define _PCH_DPC_AUX_CH_CTL 0xe4210 8430 #define _PCH_DPC_AUX_CH_DATA1 0xe4214 8431 #define _PCH_DPC_AUX_CH_DATA2 0xe4218 8432 #define _PCH_DPC_AUX_CH_DATA3 0xe421c 8433 #define _PCH_DPC_AUX_CH_DATA4 0xe4220 8434 #define _PCH_DPC_AUX_CH_DATA5 0xe4224 8435 8436 #define _PCH_DP_D 0xe4300 8437 #define PCH_DP_D _MMIO(_PCH_DP_D) 8438 #define _PCH_DPD_AUX_CH_CTL 0xe4310 8439 #define _PCH_DPD_AUX_CH_DATA1 0xe4314 8440 #define _PCH_DPD_AUX_CH_DATA2 0xe4318 8441 #define _PCH_DPD_AUX_CH_DATA3 0xe431c 8442 #define _PCH_DPD_AUX_CH_DATA4 0xe4320 8443 #define _PCH_DPD_AUX_CH_DATA5 0xe4324 8444 8445 #define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL) 8446 #define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ 8447 8448 /* CPT */ 8449 #define _TRANS_DP_CTL_A 0xe0300 8450 #define _TRANS_DP_CTL_B 0xe1300 8451 #define _TRANS_DP_CTL_C 0xe2300 8452 #define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B) 8453 #define TRANS_DP_OUTPUT_ENABLE (1 << 31) 8454 #define TRANS_DP_PORT_SEL_MASK (3 << 29) 8455 #define TRANS_DP_PORT_SEL_NONE (3 << 29) 8456 #define TRANS_DP_PORT_SEL(port) (((port) - PORT_B) << 29) 8457 #define TRANS_DP_AUDIO_ONLY (1 << 26) 8458 #define TRANS_DP_ENH_FRAMING (1 << 18) 8459 #define TRANS_DP_8BPC (0 << 9) 8460 #define TRANS_DP_10BPC (1 << 9) 8461 #define TRANS_DP_6BPC (2 << 9) 8462 #define TRANS_DP_12BPC (3 << 9) 8463 #define TRANS_DP_BPC_MASK (3 << 9) 8464 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1 << 4) 8465 #define TRANS_DP_VSYNC_ACTIVE_LOW 0 8466 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1 << 3) 8467 #define TRANS_DP_HSYNC_ACTIVE_LOW 0 8468 #define TRANS_DP_SYNC_MASK (3 << 3) 8469 8470 /* SNB eDP training params */ 8471 /* SNB A-stepping */ 8472 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) 8473 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22) 8474 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22) 8475 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22) 8476 /* SNB B-stepping */ 8477 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22) 8478 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22) 8479 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22) 8480 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22) 8481 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22) 8482 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22) 8483 8484 /* IVB */ 8485 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22) 8486 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22) 8487 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22) 8488 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22) 8489 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22) 8490 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22) 8491 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e << 22) 8492 8493 /* legacy values */ 8494 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22) 8495 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22) 8496 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22) 8497 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22) 8498 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22) 8499 8500 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22) 8501 8502 #define VLV_PMWGICZ _MMIO(0x1300a4) 8503 8504 #define RC6_LOCATION _MMIO(0xD40) 8505 #define RC6_CTX_IN_DRAM (1 << 0) 8506 #define RC6_CTX_BASE _MMIO(0xD48) 8507 #define RC6_CTX_BASE_MASK 0xFFFFFFF0 8508 #define PWRCTX_MAXCNT_RCSUNIT _MMIO(0x2054) 8509 #define PWRCTX_MAXCNT_VCSUNIT0 _MMIO(0x12054) 8510 #define PWRCTX_MAXCNT_BCSUNIT _MMIO(0x22054) 8511 #define PWRCTX_MAXCNT_VECSUNIT _MMIO(0x1A054) 8512 #define PWRCTX_MAXCNT_VCSUNIT1 _MMIO(0x1C054) 8513 #define IDLE_TIME_MASK 0xFFFFF 8514 #define FORCEWAKE _MMIO(0xA18C) 8515 #define FORCEWAKE_VLV _MMIO(0x1300b0) 8516 #define FORCEWAKE_ACK_VLV _MMIO(0x1300b4) 8517 #define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8) 8518 #define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc) 8519 #define FORCEWAKE_ACK_HSW _MMIO(0x130044) 8520 #define FORCEWAKE_ACK _MMIO(0x130090) 8521 #define VLV_GTLC_WAKE_CTRL _MMIO(0x130090) 8522 #define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25) 8523 #define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24) 8524 #define VLV_GTLC_ALLOWWAKEREQ (1 << 0) 8525 8526 #define VLV_GTLC_PW_STATUS _MMIO(0x130094) 8527 #define VLV_GTLC_ALLOWWAKEACK (1 << 0) 8528 #define VLV_GTLC_ALLOWWAKEERR (1 << 1) 8529 #define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5) 8530 #define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7) 8531 #define FORCEWAKE_MT _MMIO(0xa188) /* multi-threaded */ 8532 #define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270) 8533 #define FORCEWAKE_MEDIA_VDBOX_GEN11(n) _MMIO(0xa540 + (n) * 4) 8534 #define FORCEWAKE_MEDIA_VEBOX_GEN11(n) _MMIO(0xa560 + (n) * 4) 8535 #define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278) 8536 #define FORCEWAKE_BLITTER_GEN9 _MMIO(0xa188) 8537 #define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0x0D88) 8538 #define FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n) _MMIO(0x0D50 + (n) * 4) 8539 #define FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n) _MMIO(0x0D70 + (n) * 4) 8540 #define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0x0D84) 8541 #define FORCEWAKE_ACK_BLITTER_GEN9 _MMIO(0x130044) 8542 #define FORCEWAKE_KERNEL BIT(0) 8543 #define FORCEWAKE_USER BIT(1) 8544 #define FORCEWAKE_KERNEL_FALLBACK BIT(15) 8545 #define FORCEWAKE_MT_ACK _MMIO(0x130040) 8546 #define ECOBUS _MMIO(0xa180) 8547 #define FORCEWAKE_MT_ENABLE (1 << 5) 8548 #define VLV_SPAREG2H _MMIO(0xA194) 8549 #define GEN9_PWRGT_DOMAIN_STATUS _MMIO(0xA2A0) 8550 #define GEN9_PWRGT_MEDIA_STATUS_MASK (1 << 0) 8551 #define GEN9_PWRGT_RENDER_STATUS_MASK (1 << 1) 8552 8553 #define GTFIFODBG _MMIO(0x120000) 8554 #define GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV (0x1f << 20) 8555 #define GT_FIFO_FREE_ENTRIES_CHV (0x7f << 13) 8556 #define GT_FIFO_SBDROPERR (1 << 6) 8557 #define GT_FIFO_BLOBDROPERR (1 << 5) 8558 #define GT_FIFO_SB_READ_ABORTERR (1 << 4) 8559 #define GT_FIFO_DROPERR (1 << 3) 8560 #define GT_FIFO_OVFERR (1 << 2) 8561 #define GT_FIFO_IAWRERR (1 << 1) 8562 #define GT_FIFO_IARDERR (1 << 0) 8563 8564 #define GTFIFOCTL _MMIO(0x120008) 8565 #define GT_FIFO_FREE_ENTRIES_MASK 0x7f 8566 #define GT_FIFO_NUM_RESERVED_ENTRIES 20 8567 #define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12) 8568 #define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11) 8569 8570 #define HSW_IDICR _MMIO(0x9008) 8571 #define IDIHASHMSK(x) (((x) & 0x3f) << 16) 8572 #define HSW_EDRAM_CAP _MMIO(0x120010) 8573 #define EDRAM_ENABLED 0x1 8574 #define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf) 8575 #define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7) 8576 #define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3) 8577 8578 #define GEN6_UCGCTL1 _MMIO(0x9400) 8579 # define GEN6_GAMUNIT_CLOCK_GATE_DISABLE (1 << 22) 8580 # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16) 8581 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) 8582 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7) 8583 8584 #define GEN6_UCGCTL2 _MMIO(0x9404) 8585 # define GEN6_VFUNIT_CLOCK_GATE_DISABLE (1 << 31) 8586 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30) 8587 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22) 8588 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13) 8589 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12) 8590 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11) 8591 8592 #define GEN6_UCGCTL3 _MMIO(0x9408) 8593 # define GEN6_OACSUNIT_CLOCK_GATE_DISABLE (1 << 20) 8594 8595 #define GEN7_UCGCTL4 _MMIO(0x940c) 8596 #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1 << 25) 8597 #define GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE (1 << 14) 8598 8599 #define GEN6_RCGCTL1 _MMIO(0x9410) 8600 #define GEN6_RCGCTL2 _MMIO(0x9414) 8601 #define GEN6_RSTCTL _MMIO(0x9420) 8602 8603 #define GEN8_UCGCTL6 _MMIO(0x9430) 8604 #define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1 << 24) 8605 #define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1 << 14) 8606 #define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1 << 28) 8607 8608 #define GEN6_GFXPAUSE _MMIO(0xA000) 8609 #define GEN6_RPNSWREQ _MMIO(0xA008) 8610 #define GEN6_TURBO_DISABLE (1 << 31) 8611 #define GEN6_FREQUENCY(x) ((x) << 25) 8612 #define HSW_FREQUENCY(x) ((x) << 24) 8613 #define GEN9_FREQUENCY(x) ((x) << 23) 8614 #define GEN6_OFFSET(x) ((x) << 19) 8615 #define GEN6_AGGRESSIVE_TURBO (0 << 15) 8616 #define GEN6_RC_VIDEO_FREQ _MMIO(0xA00C) 8617 #define GEN6_RC_CONTROL _MMIO(0xA090) 8618 #define GEN6_RC_CTL_RC6pp_ENABLE (1 << 16) 8619 #define GEN6_RC_CTL_RC6p_ENABLE (1 << 17) 8620 #define GEN6_RC_CTL_RC6_ENABLE (1 << 18) 8621 #define GEN6_RC_CTL_RC1e_ENABLE (1 << 20) 8622 #define GEN6_RC_CTL_RC7_ENABLE (1 << 22) 8623 #define VLV_RC_CTL_CTX_RST_PARALLEL (1 << 24) 8624 #define GEN7_RC_CTL_TO_MODE (1 << 28) 8625 #define GEN6_RC_CTL_EI_MODE(x) ((x) << 27) 8626 #define GEN6_RC_CTL_HW_ENABLE (1 << 31) 8627 #define GEN6_RP_DOWN_TIMEOUT _MMIO(0xA010) 8628 #define GEN6_RP_INTERRUPT_LIMITS _MMIO(0xA014) 8629 #define GEN6_RPSTAT1 _MMIO(0xA01C) 8630 #define GEN6_CAGF_SHIFT 8 8631 #define HSW_CAGF_SHIFT 7 8632 #define GEN9_CAGF_SHIFT 23 8633 #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) 8634 #define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT) 8635 #define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT) 8636 #define GEN6_RP_CONTROL _MMIO(0xA024) 8637 #define GEN6_RP_MEDIA_TURBO (1 << 11) 8638 #define GEN6_RP_MEDIA_MODE_MASK (3 << 9) 8639 #define GEN6_RP_MEDIA_HW_TURBO_MODE (3 << 9) 8640 #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2 << 9) 8641 #define GEN6_RP_MEDIA_HW_MODE (1 << 9) 8642 #define GEN6_RP_MEDIA_SW_MODE (0 << 9) 8643 #define GEN6_RP_MEDIA_IS_GFX (1 << 8) 8644 #define GEN6_RP_ENABLE (1 << 7) 8645 #define GEN6_RP_UP_IDLE_MIN (0x1 << 3) 8646 #define GEN6_RP_UP_BUSY_AVG (0x2 << 3) 8647 #define GEN6_RP_UP_BUSY_CONT (0x4 << 3) 8648 #define GEN6_RP_DOWN_IDLE_AVG (0x2 << 0) 8649 #define GEN6_RP_DOWN_IDLE_CONT (0x1 << 0) 8650 #define GEN6_RP_UP_THRESHOLD _MMIO(0xA02C) 8651 #define GEN6_RP_DOWN_THRESHOLD _MMIO(0xA030) 8652 #define GEN6_RP_CUR_UP_EI _MMIO(0xA050) 8653 #define GEN6_RP_EI_MASK 0xffffff 8654 #define GEN6_CURICONT_MASK GEN6_RP_EI_MASK 8655 #define GEN6_RP_CUR_UP _MMIO(0xA054) 8656 #define GEN6_CURBSYTAVG_MASK GEN6_RP_EI_MASK 8657 #define GEN6_RP_PREV_UP _MMIO(0xA058) 8658 #define GEN6_RP_CUR_DOWN_EI _MMIO(0xA05C) 8659 #define GEN6_CURIAVG_MASK GEN6_RP_EI_MASK 8660 #define GEN6_RP_CUR_DOWN _MMIO(0xA060) 8661 #define GEN6_RP_PREV_DOWN _MMIO(0xA064) 8662 #define GEN6_RP_UP_EI _MMIO(0xA068) 8663 #define GEN6_RP_DOWN_EI _MMIO(0xA06C) 8664 #define GEN6_RP_IDLE_HYSTERSIS _MMIO(0xA070) 8665 #define GEN6_RPDEUHWTC _MMIO(0xA080) 8666 #define GEN6_RPDEUC _MMIO(0xA084) 8667 #define GEN6_RPDEUCSW _MMIO(0xA088) 8668 #define GEN6_RC_STATE _MMIO(0xA094) 8669 #define RC_SW_TARGET_STATE_SHIFT 16 8670 #define RC_SW_TARGET_STATE_MASK (7 << RC_SW_TARGET_STATE_SHIFT) 8671 #define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xA098) 8672 #define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xA09C) 8673 #define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xA0A0) 8674 #define GEN10_MEDIA_WAKE_RATE_LIMIT _MMIO(0xA0A0) 8675 #define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xA0A8) 8676 #define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xA0AC) 8677 #define GEN6_RC_SLEEP _MMIO(0xA0B0) 8678 #define GEN6_RCUBMABDTMR _MMIO(0xA0B0) 8679 #define GEN6_RC1e_THRESHOLD _MMIO(0xA0B4) 8680 #define GEN6_RC6_THRESHOLD _MMIO(0xA0B8) 8681 #define GEN6_RC6p_THRESHOLD _MMIO(0xA0BC) 8682 #define VLV_RCEDATA _MMIO(0xA0BC) 8683 #define GEN6_RC6pp_THRESHOLD _MMIO(0xA0C0) 8684 #define GEN6_PMINTRMSK _MMIO(0xA168) 8685 #define GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC (1 << 31) 8686 #define ARAT_EXPIRED_INTRMSK (1 << 9) 8687 #define GEN8_MISC_CTRL0 _MMIO(0xA180) 8688 #define VLV_PWRDWNUPCTL _MMIO(0xA294) 8689 #define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xA0C4) 8690 #define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xA0C8) 8691 #define GEN9_PG_ENABLE _MMIO(0xA210) 8692 #define GEN9_RENDER_PG_ENABLE REG_BIT(0) 8693 #define GEN9_MEDIA_PG_ENABLE REG_BIT(1) 8694 #define GEN11_MEDIA_SAMPLER_PG_ENABLE REG_BIT(2) 8695 #define GEN8_PUSHBUS_CONTROL _MMIO(0xA248) 8696 #define GEN8_PUSHBUS_ENABLE _MMIO(0xA250) 8697 #define GEN8_PUSHBUS_SHIFT _MMIO(0xA25C) 8698 8699 #define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C) 8700 #define PIXEL_OVERLAP_CNT_MASK (3 << 30) 8701 #define PIXEL_OVERLAP_CNT_SHIFT 30 8702 8703 #define GEN6_PMISR _MMIO(0x44020) 8704 #define GEN6_PMIMR _MMIO(0x44024) /* rps_lock */ 8705 #define GEN6_PMIIR _MMIO(0x44028) 8706 #define GEN6_PMIER _MMIO(0x4402C) 8707 #define GEN6_PM_MBOX_EVENT (1 << 25) 8708 #define GEN6_PM_THERMAL_EVENT (1 << 24) 8709 8710 /* 8711 * For Gen11 these are in the upper word of the GPM_WGBOXPERF 8712 * registers. Shifting is handled on accessing the imr and ier. 8713 */ 8714 #define GEN6_PM_RP_DOWN_TIMEOUT (1 << 6) 8715 #define GEN6_PM_RP_UP_THRESHOLD (1 << 5) 8716 #define GEN6_PM_RP_DOWN_THRESHOLD (1 << 4) 8717 #define GEN6_PM_RP_UP_EI_EXPIRED (1 << 2) 8718 #define GEN6_PM_RP_DOWN_EI_EXPIRED (1 << 1) 8719 #define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_EI_EXPIRED | \ 8720 GEN6_PM_RP_UP_THRESHOLD | \ 8721 GEN6_PM_RP_DOWN_EI_EXPIRED | \ 8722 GEN6_PM_RP_DOWN_THRESHOLD | \ 8723 GEN6_PM_RP_DOWN_TIMEOUT) 8724 8725 #define GEN7_GT_SCRATCH(i) _MMIO(0x4F100 + (i) * 4) 8726 #define GEN7_GT_SCRATCH_REG_NUM 8 8727 8728 #define VLV_GTLC_SURVIVABILITY_REG _MMIO(0x130098) 8729 #define VLV_GFX_CLK_STATUS_BIT (1 << 3) 8730 #define VLV_GFX_CLK_FORCE_ON_BIT (1 << 2) 8731 8732 #define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104) 8733 #define VLV_COUNTER_CONTROL _MMIO(0x138104) 8734 #define VLV_COUNT_RANGE_HIGH (1 << 15) 8735 #define VLV_MEDIA_RC0_COUNT_EN (1 << 5) 8736 #define VLV_RENDER_RC0_COUNT_EN (1 << 4) 8737 #define VLV_MEDIA_RC6_COUNT_EN (1 << 1) 8738 #define VLV_RENDER_RC6_COUNT_EN (1 << 0) 8739 #define GEN6_GT_GFX_RC6 _MMIO(0x138108) 8740 #define VLV_GT_RENDER_RC6 _MMIO(0x138108) 8741 #define VLV_GT_MEDIA_RC6 _MMIO(0x13810C) 8742 8743 #define GEN6_GT_GFX_RC6p _MMIO(0x13810C) 8744 #define GEN6_GT_GFX_RC6pp _MMIO(0x138110) 8745 #define VLV_RENDER_C0_COUNT _MMIO(0x138118) 8746 #define VLV_MEDIA_C0_COUNT _MMIO(0x13811C) 8747 8748 #define GEN6_PCODE_MAILBOX _MMIO(0x138124) 8749 #define GEN6_PCODE_READY (1 << 31) 8750 #define GEN6_PCODE_ERROR_MASK 0xFF 8751 #define GEN6_PCODE_SUCCESS 0x0 8752 #define GEN6_PCODE_ILLEGAL_CMD 0x1 8753 #define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2 8754 #define GEN6_PCODE_TIMEOUT 0x3 8755 #define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF 8756 #define GEN7_PCODE_TIMEOUT 0x2 8757 #define GEN7_PCODE_ILLEGAL_DATA 0x3 8758 #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10 8759 #define GEN6_PCODE_WRITE_RC6VIDS 0x4 8760 #define GEN6_PCODE_READ_RC6VIDS 0x5 8761 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) 8762 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) 8763 #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18 8764 #define GEN9_PCODE_READ_MEM_LATENCY 0x6 8765 #define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF 8766 #define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8 8767 #define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16 8768 #define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24 8769 #define SKL_PCODE_LOAD_HDCP_KEYS 0x5 8770 #define SKL_PCODE_CDCLK_CONTROL 0x7 8771 #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3 8772 #define SKL_CDCLK_READY_FOR_CHANGE 0x1 8773 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 8774 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 8775 #define GEN6_READ_OC_PARAMS 0xc 8776 #define GEN6_PCODE_READ_D_COMP 0x10 8777 #define GEN6_PCODE_WRITE_D_COMP 0x11 8778 #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17 8779 #define DISPLAY_IPS_CONTROL 0x19 8780 /* See also IPS_CTL */ 8781 #define IPS_PCODE_CONTROL (1 << 30) 8782 #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A 8783 #define GEN9_PCODE_SAGV_CONTROL 0x21 8784 #define GEN9_SAGV_DISABLE 0x0 8785 #define GEN9_SAGV_IS_DISABLED 0x1 8786 #define GEN9_SAGV_ENABLE 0x3 8787 #define GEN6_PCODE_DATA _MMIO(0x138128) 8788 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 8789 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 8790 #define GEN6_PCODE_DATA1 _MMIO(0x13812C) 8791 8792 #define GEN6_GT_CORE_STATUS _MMIO(0x138060) 8793 #define GEN6_CORE_CPD_STATE_MASK (7 << 4) 8794 #define GEN6_RCn_MASK 7 8795 #define GEN6_RC0 0 8796 #define GEN6_RC3 2 8797 #define GEN6_RC6 3 8798 #define GEN6_RC7 4 8799 8800 #define GEN8_GT_SLICE_INFO _MMIO(0x138064) 8801 #define GEN8_LSLICESTAT_MASK 0x7 8802 8803 #define CHV_POWER_SS0_SIG1 _MMIO(0xa720) 8804 #define CHV_POWER_SS1_SIG1 _MMIO(0xa728) 8805 #define CHV_SS_PG_ENABLE (1 << 1) 8806 #define CHV_EU08_PG_ENABLE (1 << 9) 8807 #define CHV_EU19_PG_ENABLE (1 << 17) 8808 #define CHV_EU210_PG_ENABLE (1 << 25) 8809 8810 #define CHV_POWER_SS0_SIG2 _MMIO(0xa724) 8811 #define CHV_POWER_SS1_SIG2 _MMIO(0xa72c) 8812 #define CHV_EU311_PG_ENABLE (1 << 1) 8813 8814 #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4) 8815 #define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \ 8816 ((slice) % 3) * 0x4) 8817 #define GEN9_PGCTL_SLICE_ACK (1 << 0) 8818 #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice) * 2)) 8819 #define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F) 8820 8821 #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice) * 0x8) 8822 #define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \ 8823 ((slice) % 3) * 0x8) 8824 #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice) * 0x8) 8825 #define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \ 8826 ((slice) % 3) * 0x8) 8827 #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0) 8828 #define GEN9_PGCTL_SSA_EU19_ACK (1 << 2) 8829 #define GEN9_PGCTL_SSA_EU210_ACK (1 << 4) 8830 #define GEN9_PGCTL_SSA_EU311_ACK (1 << 6) 8831 #define GEN9_PGCTL_SSB_EU08_ACK (1 << 8) 8832 #define GEN9_PGCTL_SSB_EU19_ACK (1 << 10) 8833 #define GEN9_PGCTL_SSB_EU210_ACK (1 << 12) 8834 #define GEN9_PGCTL_SSB_EU311_ACK (1 << 14) 8835 8836 #define GEN7_MISCCPCTL _MMIO(0x9424) 8837 #define GEN7_DOP_CLOCK_GATE_ENABLE (1 << 0) 8838 #define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1 << 2) 8839 #define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1 << 4) 8840 #define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1 << 6) 8841 8842 #define GEN8_GARBCNTL _MMIO(0xB004) 8843 #define GEN9_GAPS_TSV_CREDIT_DISABLE (1 << 7) 8844 #define GEN11_ARBITRATION_PRIO_ORDER_MASK (0x3f << 22) 8845 #define GEN11_HASH_CTRL_EXCL_MASK (0x7f << 0) 8846 #define GEN11_HASH_CTRL_EXCL_BIT0 (1 << 0) 8847 8848 #define GEN11_GLBLINVL _MMIO(0xB404) 8849 #define GEN11_BANK_HASH_ADDR_EXCL_MASK (0x7f << 5) 8850 #define GEN11_BANK_HASH_ADDR_EXCL_BIT0 (1 << 5) 8851 8852 #define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550) 8853 #define DFR_DISABLE (1 << 9) 8854 8855 #define GEN11_GACB_PERF_CTRL _MMIO(0x4B80) 8856 #define GEN11_HASH_CTRL_MASK (0x3 << 12 | 0xf << 0) 8857 #define GEN11_HASH_CTRL_BIT0 (1 << 0) 8858 #define GEN11_HASH_CTRL_BIT4 (1 << 12) 8859 8860 #define GEN11_LSN_UNSLCVC _MMIO(0xB43C) 8861 #define GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC (1 << 9) 8862 #define GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC (1 << 7) 8863 8864 #define GEN10_SAMPLER_MODE _MMIO(0xE18C) 8865 8866 /* IVYBRIDGE DPF */ 8867 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */ 8868 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14) 8869 #define GEN7_PARITY_ERROR_VALID (1 << 13) 8870 #define GEN7_L3CDERRST1_BANK_MASK (3 << 11) 8871 #define GEN7_L3CDERRST1_SUBBANK_MASK (7 << 8) 8872 #define GEN7_PARITY_ERROR_ROW(reg) \ 8873 (((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14) 8874 #define GEN7_PARITY_ERROR_BANK(reg) \ 8875 (((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11) 8876 #define GEN7_PARITY_ERROR_SUBBANK(reg) \ 8877 (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) 8878 #define GEN7_L3CDERRST1_ENABLE (1 << 7) 8879 8880 #define GEN7_L3LOG(slice, i) _MMIO(0xB070 + (slice) * 0x200 + (i) * 4) 8881 #define GEN7_L3LOG_SIZE 0x80 8882 8883 #define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */ 8884 #define GEN7_HALF_SLICE_CHICKEN1_GT2 _MMIO(0xf100) 8885 #define GEN7_MAX_PS_THREAD_DEP (8 << 12) 8886 #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1 << 10) 8887 #define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1 << 4) 8888 #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1 << 3) 8889 8890 #define GEN9_HALF_SLICE_CHICKEN5 _MMIO(0xe188) 8891 #define GEN9_DG_MIRROR_FIX_ENABLE (1 << 5) 8892 #define GEN9_CCS_TLB_PREFETCH_ENABLE (1 << 3) 8893 8894 #define GEN8_ROW_CHICKEN _MMIO(0xe4f0) 8895 #define FLOW_CONTROL_ENABLE (1 << 15) 8896 #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1 << 8) 8897 #define STALL_DOP_GATING_DISABLE (1 << 5) 8898 #define THROTTLE_12_5 (7 << 2) 8899 #define DISABLE_EARLY_EOT (1 << 1) 8900 8901 #define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4) 8902 #define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4) 8903 #define DOP_CLOCK_GATING_DISABLE (1 << 0) 8904 #define PUSH_CONSTANT_DEREF_DISABLE (1 << 8) 8905 #define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1) 8906 8907 #define HSW_ROW_CHICKEN3 _MMIO(0xe49c) 8908 #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) 8909 8910 #define HALF_SLICE_CHICKEN2 _MMIO(0xe180) 8911 #define GEN8_ST_PO_DISABLE (1 << 13) 8912 8913 #define HALF_SLICE_CHICKEN3 _MMIO(0xe184) 8914 #define HSW_SAMPLE_C_PERFORMANCE (1 << 9) 8915 #define GEN8_CENTROID_PIXEL_OPT_DIS (1 << 8) 8916 #define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1 << 5) 8917 #define CNL_FAST_ANISO_L1_BANKING_FIX (1 << 4) 8918 #define GEN8_SAMPLER_POWER_BYPASS_DIS (1 << 1) 8919 8920 #define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194) 8921 #define GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR (1 << 8) 8922 #define GEN9_ENABLE_YV12_BUGFIX (1 << 4) 8923 #define GEN9_ENABLE_GPGPU_PREEMPTION (1 << 2) 8924 8925 /* Audio */ 8926 #define G4X_AUD_VID_DID _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020) 8927 #define INTEL_AUDIO_DEVCL 0x808629FB 8928 #define INTEL_AUDIO_DEVBLC 0x80862801 8929 #define INTEL_AUDIO_DEVCTG 0x80862802 8930 8931 #define G4X_AUD_CNTL_ST _MMIO(0x620B4) 8932 #define G4X_ELDV_DEVCL_DEVBLC (1 << 13) 8933 #define G4X_ELDV_DEVCTG (1 << 14) 8934 #define G4X_ELD_ADDR_MASK (0xf << 5) 8935 #define G4X_ELD_ACK (1 << 4) 8936 #define G4X_HDMIW_HDMIEDID _MMIO(0x6210C) 8937 8938 #define _IBX_HDMIW_HDMIEDID_A 0xE2050 8939 #define _IBX_HDMIW_HDMIEDID_B 0xE2150 8940 #define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \ 8941 _IBX_HDMIW_HDMIEDID_B) 8942 #define _IBX_AUD_CNTL_ST_A 0xE20B4 8943 #define _IBX_AUD_CNTL_ST_B 0xE21B4 8944 #define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \ 8945 _IBX_AUD_CNTL_ST_B) 8946 #define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10) 8947 #define IBX_ELD_ADDRESS_MASK (0x1f << 5) 8948 #define IBX_ELD_ACK (1 << 4) 8949 #define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0) 8950 #define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4)) 8951 #define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4)) 8952 8953 #define _CPT_HDMIW_HDMIEDID_A 0xE5050 8954 #define _CPT_HDMIW_HDMIEDID_B 0xE5150 8955 #define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B) 8956 #define _CPT_AUD_CNTL_ST_A 0xE50B4 8957 #define _CPT_AUD_CNTL_ST_B 0xE51B4 8958 #define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B) 8959 #define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0) 8960 8961 #define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050) 8962 #define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150) 8963 #define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B) 8964 #define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4) 8965 #define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4) 8966 #define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B) 8967 #define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0) 8968 8969 /* These are the 4 32-bit write offset registers for each stream 8970 * output buffer. It determines the offset from the 8971 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. 8972 */ 8973 #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4) 8974 8975 #define _IBX_AUD_CONFIG_A 0xe2000 8976 #define _IBX_AUD_CONFIG_B 0xe2100 8977 #define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B) 8978 #define _CPT_AUD_CONFIG_A 0xe5000 8979 #define _CPT_AUD_CONFIG_B 0xe5100 8980 #define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B) 8981 #define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000) 8982 #define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100) 8983 #define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B) 8984 8985 #define AUD_CONFIG_N_VALUE_INDEX (1 << 29) 8986 #define AUD_CONFIG_N_PROG_ENABLE (1 << 28) 8987 #define AUD_CONFIG_UPPER_N_SHIFT 20 8988 #define AUD_CONFIG_UPPER_N_MASK (0xff << 20) 8989 #define AUD_CONFIG_LOWER_N_SHIFT 4 8990 #define AUD_CONFIG_LOWER_N_MASK (0xfff << 4) 8991 #define AUD_CONFIG_N_MASK (AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK) 8992 #define AUD_CONFIG_N(n) \ 8993 (((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) | \ 8994 (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT)) 8995 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 8996 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16) 8997 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16) 8998 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16) 8999 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16) 9000 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16) 9001 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16) 9002 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16) 9003 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16) 9004 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16) 9005 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16) 9006 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16) 9007 #define AUD_CONFIG_DISABLE_NCTS (1 << 3) 9008 9009 /* HSW Audio */ 9010 #define _HSW_AUD_CONFIG_A 0x65000 9011 #define _HSW_AUD_CONFIG_B 0x65100 9012 #define HSW_AUD_CFG(pipe) _MMIO_PIPE(pipe, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B) 9013 9014 #define _HSW_AUD_MISC_CTRL_A 0x65010 9015 #define _HSW_AUD_MISC_CTRL_B 0x65110 9016 #define HSW_AUD_MISC_CTRL(pipe) _MMIO_PIPE(pipe, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B) 9017 9018 #define _HSW_AUD_M_CTS_ENABLE_A 0x65028 9019 #define _HSW_AUD_M_CTS_ENABLE_B 0x65128 9020 #define HSW_AUD_M_CTS_ENABLE(pipe) _MMIO_PIPE(pipe, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B) 9021 #define AUD_M_CTS_M_VALUE_INDEX (1 << 21) 9022 #define AUD_M_CTS_M_PROG_ENABLE (1 << 20) 9023 #define AUD_CONFIG_M_MASK 0xfffff 9024 9025 #define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 9026 #define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 9027 #define HSW_AUD_DIP_ELD_CTRL(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B) 9028 9029 /* Audio Digital Converter */ 9030 #define _HSW_AUD_DIG_CNVT_1 0x65080 9031 #define _HSW_AUD_DIG_CNVT_2 0x65180 9032 #define AUD_DIG_CNVT(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2) 9033 #define DIP_PORT_SEL_MASK 0x3 9034 9035 #define _HSW_AUD_EDID_DATA_A 0x65050 9036 #define _HSW_AUD_EDID_DATA_B 0x65150 9037 #define HSW_AUD_EDID_DATA(pipe) _MMIO_PIPE(pipe, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B) 9038 9039 #define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c) 9040 #define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0) 9041 #define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4)) 9042 #define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4)) 9043 #define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4)) 9044 #define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4)) 9045 9046 #define HSW_AUD_CHICKENBIT _MMIO(0x65f10) 9047 #define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15) 9048 9049 /* 9050 * HSW - ICL power wells 9051 * 9052 * Platforms have up to 3 power well control register sets, each set 9053 * controlling up to 16 power wells via a request/status HW flag tuple: 9054 * - main (HSW_PWR_WELL_CTL[1-4]) 9055 * - AUX (ICL_PWR_WELL_CTL_AUX[1-4]) 9056 * - DDI (ICL_PWR_WELL_CTL_DDI[1-4]) 9057 * Each control register set consists of up to 4 registers used by different 9058 * sources that can request a power well to be enabled: 9059 * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1) 9060 * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2) 9061 * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set) 9062 * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4) 9063 */ 9064 #define HSW_PWR_WELL_CTL1 _MMIO(0x45400) 9065 #define HSW_PWR_WELL_CTL2 _MMIO(0x45404) 9066 #define HSW_PWR_WELL_CTL3 _MMIO(0x45408) 9067 #define HSW_PWR_WELL_CTL4 _MMIO(0x4540C) 9068 #define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2)) 9069 #define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2)) 9070 9071 /* HSW/BDW power well */ 9072 #define HSW_PW_CTL_IDX_GLOBAL 15 9073 9074 /* SKL/BXT/GLK/CNL power wells */ 9075 #define SKL_PW_CTL_IDX_PW_2 15 9076 #define SKL_PW_CTL_IDX_PW_1 14 9077 #define CNL_PW_CTL_IDX_AUX_F 12 9078 #define CNL_PW_CTL_IDX_AUX_D 11 9079 #define GLK_PW_CTL_IDX_AUX_C 10 9080 #define GLK_PW_CTL_IDX_AUX_B 9 9081 #define GLK_PW_CTL_IDX_AUX_A 8 9082 #define CNL_PW_CTL_IDX_DDI_F 6 9083 #define SKL_PW_CTL_IDX_DDI_D 4 9084 #define SKL_PW_CTL_IDX_DDI_C 3 9085 #define SKL_PW_CTL_IDX_DDI_B 2 9086 #define SKL_PW_CTL_IDX_DDI_A_E 1 9087 #define GLK_PW_CTL_IDX_DDI_A 1 9088 #define SKL_PW_CTL_IDX_MISC_IO 0 9089 9090 /* ICL - power wells */ 9091 #define ICL_PW_CTL_IDX_PW_4 3 9092 #define ICL_PW_CTL_IDX_PW_3 2 9093 #define ICL_PW_CTL_IDX_PW_2 1 9094 #define ICL_PW_CTL_IDX_PW_1 0 9095 9096 #define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440) 9097 #define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444) 9098 #define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C) 9099 #define ICL_PW_CTL_IDX_AUX_TBT4 11 9100 #define ICL_PW_CTL_IDX_AUX_TBT3 10 9101 #define ICL_PW_CTL_IDX_AUX_TBT2 9 9102 #define ICL_PW_CTL_IDX_AUX_TBT1 8 9103 #define ICL_PW_CTL_IDX_AUX_F 5 9104 #define ICL_PW_CTL_IDX_AUX_E 4 9105 #define ICL_PW_CTL_IDX_AUX_D 3 9106 #define ICL_PW_CTL_IDX_AUX_C 2 9107 #define ICL_PW_CTL_IDX_AUX_B 1 9108 #define ICL_PW_CTL_IDX_AUX_A 0 9109 9110 #define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450) 9111 #define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454) 9112 #define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C) 9113 #define ICL_PW_CTL_IDX_DDI_F 5 9114 #define ICL_PW_CTL_IDX_DDI_E 4 9115 #define ICL_PW_CTL_IDX_DDI_D 3 9116 #define ICL_PW_CTL_IDX_DDI_C 2 9117 #define ICL_PW_CTL_IDX_DDI_B 1 9118 #define ICL_PW_CTL_IDX_DDI_A 0 9119 9120 /* HSW - power well misc debug registers */ 9121 #define HSW_PWR_WELL_CTL5 _MMIO(0x45410) 9122 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31) 9123 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20) 9124 #define HSW_PWR_WELL_FORCE_ON (1 << 19) 9125 #define HSW_PWR_WELL_CTL6 _MMIO(0x45414) 9126 9127 /* SKL Fuse Status */ 9128 enum skl_power_gate { 9129 SKL_PG0, 9130 SKL_PG1, 9131 SKL_PG2, 9132 ICL_PG3, 9133 ICL_PG4, 9134 }; 9135 9136 #define SKL_FUSE_STATUS _MMIO(0x42000) 9137 #define SKL_FUSE_DOWNLOAD_STATUS (1 << 31) 9138 /* 9139 * PG0 is HW controlled, so doesn't have a corresponding power well control knob 9140 * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2 9141 */ 9142 #define SKL_PW_CTL_IDX_TO_PG(pw_idx) \ 9143 ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1) 9144 /* 9145 * PG0 is HW controlled, so doesn't have a corresponding power well control knob 9146 * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4 9147 */ 9148 #define ICL_PW_CTL_IDX_TO_PG(pw_idx) \ 9149 ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1) 9150 #define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg))) 9151 9152 #define _CNL_AUX_REG_IDX(pw_idx) ((pw_idx) - GLK_PW_CTL_IDX_AUX_B) 9153 #define _CNL_AUX_ANAOVRD1_B 0x162250 9154 #define _CNL_AUX_ANAOVRD1_C 0x162210 9155 #define _CNL_AUX_ANAOVRD1_D 0x1622D0 9156 #define _CNL_AUX_ANAOVRD1_F 0x162A90 9157 #define CNL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_CNL_AUX_REG_IDX(pw_idx), \ 9158 _CNL_AUX_ANAOVRD1_B, \ 9159 _CNL_AUX_ANAOVRD1_C, \ 9160 _CNL_AUX_ANAOVRD1_D, \ 9161 _CNL_AUX_ANAOVRD1_F)) 9162 #define CNL_AUX_ANAOVRD1_ENABLE (1 << 16) 9163 #define CNL_AUX_ANAOVRD1_LDO_BYPASS (1 << 23) 9164 9165 #define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A) 9166 #define _ICL_AUX_ANAOVRD1_A 0x162398 9167 #define _ICL_AUX_ANAOVRD1_B 0x6C398 9168 #define ICL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \ 9169 _ICL_AUX_ANAOVRD1_A, \ 9170 _ICL_AUX_ANAOVRD1_B)) 9171 #define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7) 9172 #define ICL_AUX_ANAOVRD1_ENABLE (1 << 0) 9173 9174 /* HDCP Key Registers */ 9175 #define HDCP_KEY_CONF _MMIO(0x66c00) 9176 #define HDCP_AKSV_SEND_TRIGGER BIT(31) 9177 #define HDCP_CLEAR_KEYS_TRIGGER BIT(30) 9178 #define HDCP_KEY_LOAD_TRIGGER BIT(8) 9179 #define HDCP_KEY_STATUS _MMIO(0x66c04) 9180 #define HDCP_FUSE_IN_PROGRESS BIT(7) 9181 #define HDCP_FUSE_ERROR BIT(6) 9182 #define HDCP_FUSE_DONE BIT(5) 9183 #define HDCP_KEY_LOAD_STATUS BIT(1) 9184 #define HDCP_KEY_LOAD_DONE BIT(0) 9185 #define HDCP_AKSV_LO _MMIO(0x66c10) 9186 #define HDCP_AKSV_HI _MMIO(0x66c14) 9187 9188 /* HDCP Repeater Registers */ 9189 #define HDCP_REP_CTL _MMIO(0x66d00) 9190 #define HDCP_DDIB_REP_PRESENT BIT(30) 9191 #define HDCP_DDIA_REP_PRESENT BIT(29) 9192 #define HDCP_DDIC_REP_PRESENT BIT(28) 9193 #define HDCP_DDID_REP_PRESENT BIT(27) 9194 #define HDCP_DDIF_REP_PRESENT BIT(26) 9195 #define HDCP_DDIE_REP_PRESENT BIT(25) 9196 #define HDCP_DDIB_SHA1_M0 (1 << 20) 9197 #define HDCP_DDIA_SHA1_M0 (2 << 20) 9198 #define HDCP_DDIC_SHA1_M0 (3 << 20) 9199 #define HDCP_DDID_SHA1_M0 (4 << 20) 9200 #define HDCP_DDIF_SHA1_M0 (5 << 20) 9201 #define HDCP_DDIE_SHA1_M0 (6 << 20) /* Bspec says 5? */ 9202 #define HDCP_SHA1_BUSY BIT(16) 9203 #define HDCP_SHA1_READY BIT(17) 9204 #define HDCP_SHA1_COMPLETE BIT(18) 9205 #define HDCP_SHA1_V_MATCH BIT(19) 9206 #define HDCP_SHA1_TEXT_32 (1 << 1) 9207 #define HDCP_SHA1_COMPLETE_HASH (2 << 1) 9208 #define HDCP_SHA1_TEXT_24 (4 << 1) 9209 #define HDCP_SHA1_TEXT_16 (5 << 1) 9210 #define HDCP_SHA1_TEXT_8 (6 << 1) 9211 #define HDCP_SHA1_TEXT_0 (7 << 1) 9212 #define HDCP_SHA_V_PRIME_H0 _MMIO(0x66d04) 9213 #define HDCP_SHA_V_PRIME_H1 _MMIO(0x66d08) 9214 #define HDCP_SHA_V_PRIME_H2 _MMIO(0x66d0C) 9215 #define HDCP_SHA_V_PRIME_H3 _MMIO(0x66d10) 9216 #define HDCP_SHA_V_PRIME_H4 _MMIO(0x66d14) 9217 #define HDCP_SHA_V_PRIME(h) _MMIO((0x66d04 + (h) * 4)) 9218 #define HDCP_SHA_TEXT _MMIO(0x66d18) 9219 9220 /* HDCP Auth Registers */ 9221 #define _PORTA_HDCP_AUTHENC 0x66800 9222 #define _PORTB_HDCP_AUTHENC 0x66500 9223 #define _PORTC_HDCP_AUTHENC 0x66600 9224 #define _PORTD_HDCP_AUTHENC 0x66700 9225 #define _PORTE_HDCP_AUTHENC 0x66A00 9226 #define _PORTF_HDCP_AUTHENC 0x66900 9227 #define _PORT_HDCP_AUTHENC(port, x) _MMIO(_PICK(port, \ 9228 _PORTA_HDCP_AUTHENC, \ 9229 _PORTB_HDCP_AUTHENC, \ 9230 _PORTC_HDCP_AUTHENC, \ 9231 _PORTD_HDCP_AUTHENC, \ 9232 _PORTE_HDCP_AUTHENC, \ 9233 _PORTF_HDCP_AUTHENC) + (x)) 9234 #define PORT_HDCP_CONF(port) _PORT_HDCP_AUTHENC(port, 0x0) 9235 #define HDCP_CONF_CAPTURE_AN BIT(0) 9236 #define HDCP_CONF_AUTH_AND_ENC (BIT(1) | BIT(0)) 9237 #define PORT_HDCP_ANINIT(port) _PORT_HDCP_AUTHENC(port, 0x4) 9238 #define PORT_HDCP_ANLO(port) _PORT_HDCP_AUTHENC(port, 0x8) 9239 #define PORT_HDCP_ANHI(port) _PORT_HDCP_AUTHENC(port, 0xC) 9240 #define PORT_HDCP_BKSVLO(port) _PORT_HDCP_AUTHENC(port, 0x10) 9241 #define PORT_HDCP_BKSVHI(port) _PORT_HDCP_AUTHENC(port, 0x14) 9242 #define PORT_HDCP_RPRIME(port) _PORT_HDCP_AUTHENC(port, 0x18) 9243 #define PORT_HDCP_STATUS(port) _PORT_HDCP_AUTHENC(port, 0x1C) 9244 #define HDCP_STATUS_STREAM_A_ENC BIT(31) 9245 #define HDCP_STATUS_STREAM_B_ENC BIT(30) 9246 #define HDCP_STATUS_STREAM_C_ENC BIT(29) 9247 #define HDCP_STATUS_STREAM_D_ENC BIT(28) 9248 #define HDCP_STATUS_AUTH BIT(21) 9249 #define HDCP_STATUS_ENC BIT(20) 9250 #define HDCP_STATUS_RI_MATCH BIT(19) 9251 #define HDCP_STATUS_R0_READY BIT(18) 9252 #define HDCP_STATUS_AN_READY BIT(17) 9253 #define HDCP_STATUS_CIPHER BIT(16) 9254 #define HDCP_STATUS_FRAME_CNT(x) (((x) >> 8) & 0xff) 9255 9256 /* HDCP2.2 Registers */ 9257 #define _PORTA_HDCP2_BASE 0x66800 9258 #define _PORTB_HDCP2_BASE 0x66500 9259 #define _PORTC_HDCP2_BASE 0x66600 9260 #define _PORTD_HDCP2_BASE 0x66700 9261 #define _PORTE_HDCP2_BASE 0x66A00 9262 #define _PORTF_HDCP2_BASE 0x66900 9263 #define _PORT_HDCP2_BASE(port, x) _MMIO(_PICK((port), \ 9264 _PORTA_HDCP2_BASE, \ 9265 _PORTB_HDCP2_BASE, \ 9266 _PORTC_HDCP2_BASE, \ 9267 _PORTD_HDCP2_BASE, \ 9268 _PORTE_HDCP2_BASE, \ 9269 _PORTF_HDCP2_BASE) + (x)) 9270 9271 #define HDCP2_AUTH_DDI(port) _PORT_HDCP2_BASE(port, 0x98) 9272 #define AUTH_LINK_AUTHENTICATED BIT(31) 9273 #define AUTH_LINK_TYPE BIT(30) 9274 #define AUTH_FORCE_CLR_INPUTCTR BIT(19) 9275 #define AUTH_CLR_KEYS BIT(18) 9276 9277 #define HDCP2_CTL_DDI(port) _PORT_HDCP2_BASE(port, 0xB0) 9278 #define CTL_LINK_ENCRYPTION_REQ BIT(31) 9279 9280 #define HDCP2_STATUS_DDI(port) _PORT_HDCP2_BASE(port, 0xB4) 9281 #define STREAM_ENCRYPTION_STATUS_A BIT(31) 9282 #define STREAM_ENCRYPTION_STATUS_B BIT(30) 9283 #define STREAM_ENCRYPTION_STATUS_C BIT(29) 9284 #define LINK_TYPE_STATUS BIT(22) 9285 #define LINK_AUTH_STATUS BIT(21) 9286 #define LINK_ENCRYPTION_STATUS BIT(20) 9287 9288 /* Per-pipe DDI Function Control */ 9289 #define _TRANS_DDI_FUNC_CTL_A 0x60400 9290 #define _TRANS_DDI_FUNC_CTL_B 0x61400 9291 #define _TRANS_DDI_FUNC_CTL_C 0x62400 9292 #define _TRANS_DDI_FUNC_CTL_EDP 0x6F400 9293 #define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400 9294 #define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00 9295 #define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A) 9296 9297 #define TRANS_DDI_FUNC_ENABLE (1 << 31) 9298 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ 9299 #define TRANS_DDI_PORT_MASK (7 << 28) 9300 #define TRANS_DDI_PORT_SHIFT 28 9301 #define TRANS_DDI_SELECT_PORT(x) ((x) << 28) 9302 #define TRANS_DDI_PORT_NONE (0 << 28) 9303 #define TRANS_DDI_MODE_SELECT_MASK (7 << 24) 9304 #define TRANS_DDI_MODE_SELECT_HDMI (0 << 24) 9305 #define TRANS_DDI_MODE_SELECT_DVI (1 << 24) 9306 #define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24) 9307 #define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24) 9308 #define TRANS_DDI_MODE_SELECT_FDI (4 << 24) 9309 #define TRANS_DDI_BPC_MASK (7 << 20) 9310 #define TRANS_DDI_BPC_8 (0 << 20) 9311 #define TRANS_DDI_BPC_10 (1 << 20) 9312 #define TRANS_DDI_BPC_6 (2 << 20) 9313 #define TRANS_DDI_BPC_12 (3 << 20) 9314 #define TRANS_DDI_PVSYNC (1 << 17) 9315 #define TRANS_DDI_PHSYNC (1 << 16) 9316 #define TRANS_DDI_EDP_INPUT_MASK (7 << 12) 9317 #define TRANS_DDI_EDP_INPUT_A_ON (0 << 12) 9318 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12) 9319 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12) 9320 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12) 9321 #define TRANS_DDI_HDCP_SIGNALLING (1 << 9) 9322 #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8) 9323 #define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7) 9324 #define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6) 9325 #define TRANS_DDI_BFI_ENABLE (1 << 4) 9326 #define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4) 9327 #define TRANS_DDI_HDMI_SCRAMBLING (1 << 0) 9328 #define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \ 9329 | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \ 9330 | TRANS_DDI_HDMI_SCRAMBLING) 9331 9332 #define _TRANS_DDI_FUNC_CTL2_A 0x60404 9333 #define _TRANS_DDI_FUNC_CTL2_B 0x61404 9334 #define _TRANS_DDI_FUNC_CTL2_C 0x62404 9335 #define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404 9336 #define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404 9337 #define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04 9338 #define TRANS_DDI_FUNC_CTL2(tran) _MMIO_TRANS2(tran, \ 9339 _TRANS_DDI_FUNC_CTL2_A) 9340 #define PORT_SYNC_MODE_ENABLE (1 << 4) 9341 #define PORT_SYNC_MODE_MASTER_SELECT(x) ((x) << 0) 9342 #define PORT_SYNC_MODE_MASTER_SELECT_MASK (0x7 << 0) 9343 #define PORT_SYNC_MODE_MASTER_SELECT_SHIFT 0 9344 9345 /* DisplayPort Transport Control */ 9346 #define _DP_TP_CTL_A 0x64040 9347 #define _DP_TP_CTL_B 0x64140 9348 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B) 9349 #define DP_TP_CTL_ENABLE (1 << 31) 9350 #define DP_TP_CTL_FEC_ENABLE (1 << 30) 9351 #define DP_TP_CTL_MODE_SST (0 << 27) 9352 #define DP_TP_CTL_MODE_MST (1 << 27) 9353 #define DP_TP_CTL_FORCE_ACT (1 << 25) 9354 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18) 9355 #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15) 9356 #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8) 9357 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0 << 8) 9358 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1 << 8) 9359 #define DP_TP_CTL_LINK_TRAIN_PAT3 (4 << 8) 9360 #define DP_TP_CTL_LINK_TRAIN_PAT4 (5 << 8) 9361 #define DP_TP_CTL_LINK_TRAIN_IDLE (2 << 8) 9362 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3 << 8) 9363 #define DP_TP_CTL_SCRAMBLE_DISABLE (1 << 7) 9364 9365 /* DisplayPort Transport Status */ 9366 #define _DP_TP_STATUS_A 0x64044 9367 #define _DP_TP_STATUS_B 0x64144 9368 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B) 9369 #define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28) 9370 #define DP_TP_STATUS_IDLE_DONE (1 << 25) 9371 #define DP_TP_STATUS_ACT_SENT (1 << 24) 9372 #define DP_TP_STATUS_MODE_STATUS_MST (1 << 23) 9373 #define DP_TP_STATUS_AUTOTRAIN_DONE (1 << 12) 9374 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8) 9375 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4) 9376 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0) 9377 9378 /* DDI Buffer Control */ 9379 #define _DDI_BUF_CTL_A 0x64000 9380 #define _DDI_BUF_CTL_B 0x64100 9381 #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B) 9382 #define DDI_BUF_CTL_ENABLE (1 << 31) 9383 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24) 9384 #define DDI_BUF_EMP_MASK (0xf << 24) 9385 #define DDI_BUF_PORT_REVERSAL (1 << 16) 9386 #define DDI_BUF_IS_IDLE (1 << 7) 9387 #define DDI_A_4_LANES (1 << 4) 9388 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) 9389 #define DDI_PORT_WIDTH_MASK (7 << 1) 9390 #define DDI_PORT_WIDTH_SHIFT 1 9391 #define DDI_INIT_DISPLAY_DETECTED (1 << 0) 9392 9393 /* DDI Buffer Translations */ 9394 #define _DDI_BUF_TRANS_A 0x64E00 9395 #define _DDI_BUF_TRANS_B 0x64E60 9396 #define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8) 9397 #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31) 9398 #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4) 9399 9400 /* Sideband Interface (SBI) is programmed indirectly, via 9401 * SBI_ADDR, which contains the register offset; and SBI_DATA, 9402 * which contains the payload */ 9403 #define SBI_ADDR _MMIO(0xC6000) 9404 #define SBI_DATA _MMIO(0xC6004) 9405 #define SBI_CTL_STAT _MMIO(0xC6008) 9406 #define SBI_CTL_DEST_ICLK (0x0 << 16) 9407 #define SBI_CTL_DEST_MPHY (0x1 << 16) 9408 #define SBI_CTL_OP_IORD (0x2 << 8) 9409 #define SBI_CTL_OP_IOWR (0x3 << 8) 9410 #define SBI_CTL_OP_CRRD (0x6 << 8) 9411 #define SBI_CTL_OP_CRWR (0x7 << 8) 9412 #define SBI_RESPONSE_FAIL (0x1 << 1) 9413 #define SBI_RESPONSE_SUCCESS (0x0 << 1) 9414 #define SBI_BUSY (0x1 << 0) 9415 #define SBI_READY (0x0 << 0) 9416 9417 /* SBI offsets */ 9418 #define SBI_SSCDIVINTPHASE 0x0200 9419 #define SBI_SSCDIVINTPHASE6 0x0600 9420 #define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1 9421 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1) 9422 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1) 9423 #define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8 9424 #define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8) 9425 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8) 9426 #define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15) 9427 #define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0) 9428 #define SBI_SSCDITHPHASE 0x0204 9429 #define SBI_SSCCTL 0x020c 9430 #define SBI_SSCCTL6 0x060C 9431 #define SBI_SSCCTL_PATHALT (1 << 3) 9432 #define SBI_SSCCTL_DISABLE (1 << 0) 9433 #define SBI_SSCAUXDIV6 0x0610 9434 #define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4 9435 #define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4) 9436 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4) 9437 #define SBI_DBUFF0 0x2a00 9438 #define SBI_GEN0 0x1f00 9439 #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0) 9440 9441 /* LPT PIXCLK_GATE */ 9442 #define PIXCLK_GATE _MMIO(0xC6020) 9443 #define PIXCLK_GATE_UNGATE (1 << 0) 9444 #define PIXCLK_GATE_GATE (0 << 0) 9445 9446 /* SPLL */ 9447 #define SPLL_CTL _MMIO(0x46020) 9448 #define SPLL_PLL_ENABLE (1 << 31) 9449 #define SPLL_PLL_SSC (1 << 28) 9450 #define SPLL_PLL_NON_SSC (2 << 28) 9451 #define SPLL_PLL_LCPLL (3 << 28) 9452 #define SPLL_PLL_REF_MASK (3 << 28) 9453 #define SPLL_PLL_FREQ_810MHz (0 << 26) 9454 #define SPLL_PLL_FREQ_1350MHz (1 << 26) 9455 #define SPLL_PLL_FREQ_2700MHz (2 << 26) 9456 #define SPLL_PLL_FREQ_MASK (3 << 26) 9457 9458 /* WRPLL */ 9459 #define _WRPLL_CTL1 0x46040 9460 #define _WRPLL_CTL2 0x46060 9461 #define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2) 9462 #define WRPLL_PLL_ENABLE (1 << 31) 9463 #define WRPLL_PLL_SSC (1 << 28) 9464 #define WRPLL_PLL_NON_SSC (2 << 28) 9465 #define WRPLL_PLL_LCPLL (3 << 28) 9466 #define WRPLL_PLL_REF_MASK (3 << 28) 9467 /* WRPLL divider programming */ 9468 #define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0) 9469 #define WRPLL_DIVIDER_REF_MASK (0xff) 9470 #define WRPLL_DIVIDER_POST(x) ((x) << 8) 9471 #define WRPLL_DIVIDER_POST_MASK (0x3f << 8) 9472 #define WRPLL_DIVIDER_POST_SHIFT 8 9473 #define WRPLL_DIVIDER_FEEDBACK(x) ((x) << 16) 9474 #define WRPLL_DIVIDER_FB_SHIFT 16 9475 #define WRPLL_DIVIDER_FB_MASK (0xff << 16) 9476 9477 /* Port clock selection */ 9478 #define _PORT_CLK_SEL_A 0x46100 9479 #define _PORT_CLK_SEL_B 0x46104 9480 #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B) 9481 #define PORT_CLK_SEL_LCPLL_2700 (0 << 29) 9482 #define PORT_CLK_SEL_LCPLL_1350 (1 << 29) 9483 #define PORT_CLK_SEL_LCPLL_810 (2 << 29) 9484 #define PORT_CLK_SEL_SPLL (3 << 29) 9485 #define PORT_CLK_SEL_WRPLL(pll) (((pll) + 4) << 29) 9486 #define PORT_CLK_SEL_WRPLL1 (4 << 29) 9487 #define PORT_CLK_SEL_WRPLL2 (5 << 29) 9488 #define PORT_CLK_SEL_NONE (7 << 29) 9489 #define PORT_CLK_SEL_MASK (7 << 29) 9490 9491 /* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */ 9492 #define DDI_CLK_SEL(port) PORT_CLK_SEL(port) 9493 #define DDI_CLK_SEL_NONE (0x0 << 28) 9494 #define DDI_CLK_SEL_MG (0x8 << 28) 9495 #define DDI_CLK_SEL_TBT_162 (0xC << 28) 9496 #define DDI_CLK_SEL_TBT_270 (0xD << 28) 9497 #define DDI_CLK_SEL_TBT_540 (0xE << 28) 9498 #define DDI_CLK_SEL_TBT_810 (0xF << 28) 9499 #define DDI_CLK_SEL_MASK (0xF << 28) 9500 9501 /* Transcoder clock selection */ 9502 #define _TRANS_CLK_SEL_A 0x46140 9503 #define _TRANS_CLK_SEL_B 0x46144 9504 #define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B) 9505 /* For each transcoder, we need to select the corresponding port clock */ 9506 #define TRANS_CLK_SEL_DISABLED (0x0 << 29) 9507 #define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29) 9508 9509 #define CDCLK_FREQ _MMIO(0x46200) 9510 9511 #define _TRANSA_MSA_MISC 0x60410 9512 #define _TRANSB_MSA_MISC 0x61410 9513 #define _TRANSC_MSA_MISC 0x62410 9514 #define _TRANS_EDP_MSA_MISC 0x6f410 9515 #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC) 9516 9517 #define TRANS_MSA_SYNC_CLK (1 << 0) 9518 #define TRANS_MSA_SAMPLING_444 (2 << 1) 9519 #define TRANS_MSA_CLRSP_YCBCR (2 << 3) 9520 #define TRANS_MSA_6_BPC (0 << 5) 9521 #define TRANS_MSA_8_BPC (1 << 5) 9522 #define TRANS_MSA_10_BPC (2 << 5) 9523 #define TRANS_MSA_12_BPC (3 << 5) 9524 #define TRANS_MSA_16_BPC (4 << 5) 9525 #define TRANS_MSA_CEA_RANGE (1 << 3) 9526 9527 /* LCPLL Control */ 9528 #define LCPLL_CTL _MMIO(0x130040) 9529 #define LCPLL_PLL_DISABLE (1 << 31) 9530 #define LCPLL_PLL_LOCK (1 << 30) 9531 #define LCPLL_CLK_FREQ_MASK (3 << 26) 9532 #define LCPLL_CLK_FREQ_450 (0 << 26) 9533 #define LCPLL_CLK_FREQ_54O_BDW (1 << 26) 9534 #define LCPLL_CLK_FREQ_337_5_BDW (2 << 26) 9535 #define LCPLL_CLK_FREQ_675_BDW (3 << 26) 9536 #define LCPLL_CD_CLOCK_DISABLE (1 << 25) 9537 #define LCPLL_ROOT_CD_CLOCK_DISABLE (1 << 24) 9538 #define LCPLL_CD2X_CLOCK_DISABLE (1 << 23) 9539 #define LCPLL_POWER_DOWN_ALLOW (1 << 22) 9540 #define LCPLL_CD_SOURCE_FCLK (1 << 21) 9541 #define LCPLL_CD_SOURCE_FCLK_DONE (1 << 19) 9542 9543 /* 9544 * SKL Clocks 9545 */ 9546 9547 /* CDCLK_CTL */ 9548 #define CDCLK_CTL _MMIO(0x46000) 9549 #define CDCLK_FREQ_SEL_MASK (3 << 26) 9550 #define CDCLK_FREQ_450_432 (0 << 26) 9551 #define CDCLK_FREQ_540 (1 << 26) 9552 #define CDCLK_FREQ_337_308 (2 << 26) 9553 #define CDCLK_FREQ_675_617 (3 << 26) 9554 #define BXT_CDCLK_CD2X_DIV_SEL_MASK (3 << 22) 9555 #define BXT_CDCLK_CD2X_DIV_SEL_1 (0 << 22) 9556 #define BXT_CDCLK_CD2X_DIV_SEL_1_5 (1 << 22) 9557 #define BXT_CDCLK_CD2X_DIV_SEL_2 (2 << 22) 9558 #define BXT_CDCLK_CD2X_DIV_SEL_4 (3 << 22) 9559 #define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20) 9560 #define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19) 9561 #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3) 9562 #define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19) 9563 #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16) 9564 #define CDCLK_FREQ_DECIMAL_MASK (0x7ff) 9565 9566 /* LCPLL_CTL */ 9567 #define LCPLL1_CTL _MMIO(0x46010) 9568 #define LCPLL2_CTL _MMIO(0x46014) 9569 #define LCPLL_PLL_ENABLE (1 << 31) 9570 9571 /* DPLL control1 */ 9572 #define DPLL_CTRL1 _MMIO(0x6C058) 9573 #define DPLL_CTRL1_HDMI_MODE(id) (1 << ((id) * 6 + 5)) 9574 #define DPLL_CTRL1_SSC(id) (1 << ((id) * 6 + 4)) 9575 #define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id) * 6 + 1)) 9576 #define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id) * 6 + 1) 9577 #define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate) << ((id) * 6 + 1)) 9578 #define DPLL_CTRL1_OVERRIDE(id) (1 << ((id) * 6)) 9579 #define DPLL_CTRL1_LINK_RATE_2700 0 9580 #define DPLL_CTRL1_LINK_RATE_1350 1 9581 #define DPLL_CTRL1_LINK_RATE_810 2 9582 #define DPLL_CTRL1_LINK_RATE_1620 3 9583 #define DPLL_CTRL1_LINK_RATE_1080 4 9584 #define DPLL_CTRL1_LINK_RATE_2160 5 9585 9586 /* DPLL control2 */ 9587 #define DPLL_CTRL2 _MMIO(0x6C05C) 9588 #define DPLL_CTRL2_DDI_CLK_OFF(port) (1 << ((port) + 15)) 9589 #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3 << ((port) * 3 + 1)) 9590 #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port) * 3 + 1) 9591 #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port) * 3 + 1)) 9592 #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1 << ((port) * 3)) 9593 9594 /* DPLL Status */ 9595 #define DPLL_STATUS _MMIO(0x6C060) 9596 #define DPLL_LOCK(id) (1 << ((id) * 8)) 9597 9598 /* DPLL cfg */ 9599 #define _DPLL1_CFGCR1 0x6C040 9600 #define _DPLL2_CFGCR1 0x6C048 9601 #define _DPLL3_CFGCR1 0x6C050 9602 #define DPLL_CFGCR1_FREQ_ENABLE (1 << 31) 9603 #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9) 9604 #define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9) 9605 #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff) 9606 9607 #define _DPLL1_CFGCR2 0x6C044 9608 #define _DPLL2_CFGCR2 0x6C04C 9609 #define _DPLL3_CFGCR2 0x6C054 9610 #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8) 9611 #define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8) 9612 #define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7) 9613 #define DPLL_CFGCR2_KDIV_MASK (3 << 5) 9614 #define DPLL_CFGCR2_KDIV(x) ((x) << 5) 9615 #define DPLL_CFGCR2_KDIV_5 (0 << 5) 9616 #define DPLL_CFGCR2_KDIV_2 (1 << 5) 9617 #define DPLL_CFGCR2_KDIV_3 (2 << 5) 9618 #define DPLL_CFGCR2_KDIV_1 (3 << 5) 9619 #define DPLL_CFGCR2_PDIV_MASK (7 << 2) 9620 #define DPLL_CFGCR2_PDIV(x) ((x) << 2) 9621 #define DPLL_CFGCR2_PDIV_1 (0 << 2) 9622 #define DPLL_CFGCR2_PDIV_2 (1 << 2) 9623 #define DPLL_CFGCR2_PDIV_3 (2 << 2) 9624 #define DPLL_CFGCR2_PDIV_7 (4 << 2) 9625 #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3) 9626 9627 #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1) 9628 #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2) 9629 9630 /* 9631 * CNL Clocks 9632 */ 9633 #define DPCLKA_CFGCR0 _MMIO(0x6C200) 9634 #define DPCLKA_CFGCR0_ICL _MMIO(0x164280) 9635 #define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 : \ 9636 (port) + 10)) 9637 #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) + 10)) 9638 #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \ 9639 21 : (tc_port) + 12)) 9640 #define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \ 9641 (port) * 2) 9642 #define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)) 9643 #define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)) 9644 9645 /* CNL PLL */ 9646 #define DPLL0_ENABLE 0x46010 9647 #define DPLL1_ENABLE 0x46014 9648 #define PLL_ENABLE (1 << 31) 9649 #define PLL_LOCK (1 << 30) 9650 #define PLL_POWER_ENABLE (1 << 27) 9651 #define PLL_POWER_STATE (1 << 26) 9652 #define CNL_DPLL_ENABLE(pll) _MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE) 9653 9654 #define TBT_PLL_ENABLE _MMIO(0x46020) 9655 9656 #define _MG_PLL1_ENABLE 0x46030 9657 #define _MG_PLL2_ENABLE 0x46034 9658 #define _MG_PLL3_ENABLE 0x46038 9659 #define _MG_PLL4_ENABLE 0x4603C 9660 /* Bits are the same as DPLL0_ENABLE */ 9661 #define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \ 9662 _MG_PLL2_ENABLE) 9663 9664 #define _MG_REFCLKIN_CTL_PORT1 0x16892C 9665 #define _MG_REFCLKIN_CTL_PORT2 0x16992C 9666 #define _MG_REFCLKIN_CTL_PORT3 0x16A92C 9667 #define _MG_REFCLKIN_CTL_PORT4 0x16B92C 9668 #define MG_REFCLKIN_CTL_OD_2_MUX(x) ((x) << 8) 9669 #define MG_REFCLKIN_CTL_OD_2_MUX_MASK (0x7 << 8) 9670 #define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \ 9671 _MG_REFCLKIN_CTL_PORT1, \ 9672 _MG_REFCLKIN_CTL_PORT2) 9673 9674 #define _MG_CLKTOP2_CORECLKCTL1_PORT1 0x1688D8 9675 #define _MG_CLKTOP2_CORECLKCTL1_PORT2 0x1698D8 9676 #define _MG_CLKTOP2_CORECLKCTL1_PORT3 0x16A8D8 9677 #define _MG_CLKTOP2_CORECLKCTL1_PORT4 0x16B8D8 9678 #define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x) ((x) << 16) 9679 #define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK (0xff << 16) 9680 #define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x) ((x) << 8) 9681 #define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK (0xff << 8) 9682 #define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \ 9683 _MG_CLKTOP2_CORECLKCTL1_PORT1, \ 9684 _MG_CLKTOP2_CORECLKCTL1_PORT2) 9685 9686 #define _MG_CLKTOP2_HSCLKCTL_PORT1 0x1688D4 9687 #define _MG_CLKTOP2_HSCLKCTL_PORT2 0x1698D4 9688 #define _MG_CLKTOP2_HSCLKCTL_PORT3 0x16A8D4 9689 #define _MG_CLKTOP2_HSCLKCTL_PORT4 0x16B8D4 9690 #define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x) ((x) << 16) 9691 #define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK (0x1 << 16) 9692 #define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x) ((x) << 14) 9693 #define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK (0x3 << 14) 9694 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK (0x3 << 12) 9695 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2 (0 << 12) 9696 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3 (1 << 12) 9697 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5 (2 << 12) 9698 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7 (3 << 12) 9699 #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8) 9700 #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT 8 9701 #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK (0xf << 8) 9702 #define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \ 9703 _MG_CLKTOP2_HSCLKCTL_PORT1, \ 9704 _MG_CLKTOP2_HSCLKCTL_PORT2) 9705 9706 #define _MG_PLL_DIV0_PORT1 0x168A00 9707 #define _MG_PLL_DIV0_PORT2 0x169A00 9708 #define _MG_PLL_DIV0_PORT3 0x16AA00 9709 #define _MG_PLL_DIV0_PORT4 0x16BA00 9710 #define MG_PLL_DIV0_FRACNEN_H (1 << 30) 9711 #define MG_PLL_DIV0_FBDIV_FRAC_MASK (0x3fffff << 8) 9712 #define MG_PLL_DIV0_FBDIV_FRAC_SHIFT 8 9713 #define MG_PLL_DIV0_FBDIV_FRAC(x) ((x) << 8) 9714 #define MG_PLL_DIV0_FBDIV_INT_MASK (0xff << 0) 9715 #define MG_PLL_DIV0_FBDIV_INT(x) ((x) << 0) 9716 #define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \ 9717 _MG_PLL_DIV0_PORT2) 9718 9719 #define _MG_PLL_DIV1_PORT1 0x168A04 9720 #define _MG_PLL_DIV1_PORT2 0x169A04 9721 #define _MG_PLL_DIV1_PORT3 0x16AA04 9722 #define _MG_PLL_DIV1_PORT4 0x16BA04 9723 #define MG_PLL_DIV1_IREF_NDIVRATIO(x) ((x) << 16) 9724 #define MG_PLL_DIV1_DITHER_DIV_1 (0 << 12) 9725 #define MG_PLL_DIV1_DITHER_DIV_2 (1 << 12) 9726 #define MG_PLL_DIV1_DITHER_DIV_4 (2 << 12) 9727 #define MG_PLL_DIV1_DITHER_DIV_8 (3 << 12) 9728 #define MG_PLL_DIV1_NDIVRATIO(x) ((x) << 4) 9729 #define MG_PLL_DIV1_FBPREDIV_MASK (0xf << 0) 9730 #define MG_PLL_DIV1_FBPREDIV(x) ((x) << 0) 9731 #define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \ 9732 _MG_PLL_DIV1_PORT2) 9733 9734 #define _MG_PLL_LF_PORT1 0x168A08 9735 #define _MG_PLL_LF_PORT2 0x169A08 9736 #define _MG_PLL_LF_PORT3 0x16AA08 9737 #define _MG_PLL_LF_PORT4 0x16BA08 9738 #define MG_PLL_LF_TDCTARGETCNT(x) ((x) << 24) 9739 #define MG_PLL_LF_AFCCNTSEL_256 (0 << 20) 9740 #define MG_PLL_LF_AFCCNTSEL_512 (1 << 20) 9741 #define MG_PLL_LF_GAINCTRL(x) ((x) << 16) 9742 #define MG_PLL_LF_INT_COEFF(x) ((x) << 8) 9743 #define MG_PLL_LF_PROP_COEFF(x) ((x) << 0) 9744 #define MG_PLL_LF(tc_port) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \ 9745 _MG_PLL_LF_PORT2) 9746 9747 #define _MG_PLL_FRAC_LOCK_PORT1 0x168A0C 9748 #define _MG_PLL_FRAC_LOCK_PORT2 0x169A0C 9749 #define _MG_PLL_FRAC_LOCK_PORT3 0x16AA0C 9750 #define _MG_PLL_FRAC_LOCK_PORT4 0x16BA0C 9751 #define MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 (1 << 18) 9752 #define MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 (1 << 16) 9753 #define MG_PLL_FRAC_LOCK_LOCKTHRESH(x) ((x) << 11) 9754 #define MG_PLL_FRAC_LOCK_DCODITHEREN (1 << 10) 9755 #define MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN (1 << 8) 9756 #define MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(x) ((x) << 0) 9757 #define MG_PLL_FRAC_LOCK(tc_port) _MMIO_PORT((tc_port), \ 9758 _MG_PLL_FRAC_LOCK_PORT1, \ 9759 _MG_PLL_FRAC_LOCK_PORT2) 9760 9761 #define _MG_PLL_SSC_PORT1 0x168A10 9762 #define _MG_PLL_SSC_PORT2 0x169A10 9763 #define _MG_PLL_SSC_PORT3 0x16AA10 9764 #define _MG_PLL_SSC_PORT4 0x16BA10 9765 #define MG_PLL_SSC_EN (1 << 28) 9766 #define MG_PLL_SSC_TYPE(x) ((x) << 26) 9767 #define MG_PLL_SSC_STEPLENGTH(x) ((x) << 16) 9768 #define MG_PLL_SSC_STEPNUM(x) ((x) << 10) 9769 #define MG_PLL_SSC_FLLEN (1 << 9) 9770 #define MG_PLL_SSC_STEPSIZE(x) ((x) << 0) 9771 #define MG_PLL_SSC(tc_port) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \ 9772 _MG_PLL_SSC_PORT2) 9773 9774 #define _MG_PLL_BIAS_PORT1 0x168A14 9775 #define _MG_PLL_BIAS_PORT2 0x169A14 9776 #define _MG_PLL_BIAS_PORT3 0x16AA14 9777 #define _MG_PLL_BIAS_PORT4 0x16BA14 9778 #define MG_PLL_BIAS_BIAS_GB_SEL(x) ((x) << 30) 9779 #define MG_PLL_BIAS_BIAS_GB_SEL_MASK (0x3 << 30) 9780 #define MG_PLL_BIAS_INIT_DCOAMP(x) ((x) << 24) 9781 #define MG_PLL_BIAS_INIT_DCOAMP_MASK (0x3f << 24) 9782 #define MG_PLL_BIAS_BIAS_BONUS(x) ((x) << 16) 9783 #define MG_PLL_BIAS_BIAS_BONUS_MASK (0xff << 16) 9784 #define MG_PLL_BIAS_BIASCAL_EN (1 << 15) 9785 #define MG_PLL_BIAS_CTRIM(x) ((x) << 8) 9786 #define MG_PLL_BIAS_CTRIM_MASK (0x1f << 8) 9787 #define MG_PLL_BIAS_VREF_RDAC(x) ((x) << 5) 9788 #define MG_PLL_BIAS_VREF_RDAC_MASK (0x7 << 5) 9789 #define MG_PLL_BIAS_IREFTRIM(x) ((x) << 0) 9790 #define MG_PLL_BIAS_IREFTRIM_MASK (0x1f << 0) 9791 #define MG_PLL_BIAS(tc_port) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \ 9792 _MG_PLL_BIAS_PORT2) 9793 9794 #define _MG_PLL_TDC_COLDST_BIAS_PORT1 0x168A18 9795 #define _MG_PLL_TDC_COLDST_BIAS_PORT2 0x169A18 9796 #define _MG_PLL_TDC_COLDST_BIAS_PORT3 0x16AA18 9797 #define _MG_PLL_TDC_COLDST_BIAS_PORT4 0x16BA18 9798 #define MG_PLL_TDC_COLDST_IREFINT_EN (1 << 27) 9799 #define MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(x) ((x) << 17) 9800 #define MG_PLL_TDC_COLDST_COLDSTART (1 << 16) 9801 #define MG_PLL_TDC_TDCOVCCORR_EN (1 << 2) 9802 #define MG_PLL_TDC_TDCSEL(x) ((x) << 0) 9803 #define MG_PLL_TDC_COLDST_BIAS(tc_port) _MMIO_PORT((tc_port), \ 9804 _MG_PLL_TDC_COLDST_BIAS_PORT1, \ 9805 _MG_PLL_TDC_COLDST_BIAS_PORT2) 9806 9807 #define _CNL_DPLL0_CFGCR0 0x6C000 9808 #define _CNL_DPLL1_CFGCR0 0x6C080 9809 #define DPLL_CFGCR0_HDMI_MODE (1 << 30) 9810 #define DPLL_CFGCR0_SSC_ENABLE (1 << 29) 9811 #define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25) 9812 #define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25) 9813 #define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25) 9814 #define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25) 9815 #define DPLL_CFGCR0_LINK_RATE_810 (2 << 25) 9816 #define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25) 9817 #define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25) 9818 #define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25) 9819 #define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25) 9820 #define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25) 9821 #define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10) 9822 #define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10) 9823 #define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10) 9824 #define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff) 9825 #define CNL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR0, _CNL_DPLL1_CFGCR0) 9826 9827 #define _CNL_DPLL0_CFGCR1 0x6C004 9828 #define _CNL_DPLL1_CFGCR1 0x6C084 9829 #define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10) 9830 #define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10) 9831 #define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10) 9832 #define DPLL_CFGCR1_QDIV_MODE_SHIFT (9) 9833 #define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9) 9834 #define DPLL_CFGCR1_KDIV_MASK (7 << 6) 9835 #define DPLL_CFGCR1_KDIV_SHIFT (6) 9836 #define DPLL_CFGCR1_KDIV(x) ((x) << 6) 9837 #define DPLL_CFGCR1_KDIV_1 (1 << 6) 9838 #define DPLL_CFGCR1_KDIV_2 (2 << 6) 9839 #define DPLL_CFGCR1_KDIV_3 (4 << 6) 9840 #define DPLL_CFGCR1_PDIV_MASK (0xf << 2) 9841 #define DPLL_CFGCR1_PDIV_SHIFT (2) 9842 #define DPLL_CFGCR1_PDIV(x) ((x) << 2) 9843 #define DPLL_CFGCR1_PDIV_2 (1 << 2) 9844 #define DPLL_CFGCR1_PDIV_3 (2 << 2) 9845 #define DPLL_CFGCR1_PDIV_5 (4 << 2) 9846 #define DPLL_CFGCR1_PDIV_7 (8 << 2) 9847 #define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0) 9848 #define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0) 9849 #define CNL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR1, _CNL_DPLL1_CFGCR1) 9850 9851 #define _ICL_DPLL0_CFGCR0 0x164000 9852 #define _ICL_DPLL1_CFGCR0 0x164080 9853 #define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \ 9854 _ICL_DPLL1_CFGCR0) 9855 9856 #define _ICL_DPLL0_CFGCR1 0x164004 9857 #define _ICL_DPLL1_CFGCR1 0x164084 9858 #define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \ 9859 _ICL_DPLL1_CFGCR1) 9860 9861 /* BXT display engine PLL */ 9862 #define BXT_DE_PLL_CTL _MMIO(0x6d000) 9863 #define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */ 9864 #define BXT_DE_PLL_RATIO_MASK 0xff 9865 9866 #define BXT_DE_PLL_ENABLE _MMIO(0x46070) 9867 #define BXT_DE_PLL_PLL_ENABLE (1 << 31) 9868 #define BXT_DE_PLL_LOCK (1 << 30) 9869 #define CNL_CDCLK_PLL_RATIO(x) (x) 9870 #define CNL_CDCLK_PLL_RATIO_MASK 0xff 9871 9872 /* GEN9 DC */ 9873 #define DC_STATE_EN _MMIO(0x45504) 9874 #define DC_STATE_DISABLE 0 9875 #define DC_STATE_EN_UPTO_DC5 (1 << 0) 9876 #define DC_STATE_EN_DC9 (1 << 3) 9877 #define DC_STATE_EN_UPTO_DC6 (2 << 0) 9878 #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3 9879 9880 #define DC_STATE_DEBUG _MMIO(0x45520) 9881 #define DC_STATE_DEBUG_MASK_CORES (1 << 0) 9882 #define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1) 9883 9884 #define BXT_P_CR_MC_BIOS_REQ_0_0_0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7114) 9885 #define BXT_REQ_DATA_MASK 0x3F 9886 #define BXT_DRAM_CHANNEL_ACTIVE_SHIFT 12 9887 #define BXT_DRAM_CHANNEL_ACTIVE_MASK (0xF << 12) 9888 #define BXT_MEMORY_FREQ_MULTIPLIER_HZ 133333333 9889 9890 #define BXT_D_CR_DRP0_DUNIT8 0x1000 9891 #define BXT_D_CR_DRP0_DUNIT9 0x1200 9892 #define BXT_D_CR_DRP0_DUNIT_START 8 9893 #define BXT_D_CR_DRP0_DUNIT_END 11 9894 #define BXT_D_CR_DRP0_DUNIT(x) _MMIO(MCHBAR_MIRROR_BASE_SNB + \ 9895 _PICK_EVEN((x) - 8, BXT_D_CR_DRP0_DUNIT8,\ 9896 BXT_D_CR_DRP0_DUNIT9)) 9897 #define BXT_DRAM_RANK_MASK 0x3 9898 #define BXT_DRAM_RANK_SINGLE 0x1 9899 #define BXT_DRAM_RANK_DUAL 0x3 9900 #define BXT_DRAM_WIDTH_MASK (0x3 << 4) 9901 #define BXT_DRAM_WIDTH_SHIFT 4 9902 #define BXT_DRAM_WIDTH_X8 (0x0 << 4) 9903 #define BXT_DRAM_WIDTH_X16 (0x1 << 4) 9904 #define BXT_DRAM_WIDTH_X32 (0x2 << 4) 9905 #define BXT_DRAM_WIDTH_X64 (0x3 << 4) 9906 #define BXT_DRAM_SIZE_MASK (0x7 << 6) 9907 #define BXT_DRAM_SIZE_SHIFT 6 9908 #define BXT_DRAM_SIZE_4GBIT (0x0 << 6) 9909 #define BXT_DRAM_SIZE_6GBIT (0x1 << 6) 9910 #define BXT_DRAM_SIZE_8GBIT (0x2 << 6) 9911 #define BXT_DRAM_SIZE_12GBIT (0x3 << 6) 9912 #define BXT_DRAM_SIZE_16GBIT (0x4 << 6) 9913 #define BXT_DRAM_TYPE_MASK (0x7 << 22) 9914 #define BXT_DRAM_TYPE_SHIFT 22 9915 #define BXT_DRAM_TYPE_DDR3 (0x0 << 22) 9916 #define BXT_DRAM_TYPE_LPDDR3 (0x1 << 22) 9917 #define BXT_DRAM_TYPE_LPDDR4 (0x2 << 22) 9918 #define BXT_DRAM_TYPE_DDR4 (0x4 << 22) 9919 9920 #define SKL_MEMORY_FREQ_MULTIPLIER_HZ 266666666 9921 #define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5E04) 9922 #define SKL_REQ_DATA_MASK (0xF << 0) 9923 9924 #define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000) 9925 #define SKL_DRAM_DDR_TYPE_MASK (0x3 << 0) 9926 #define SKL_DRAM_DDR_TYPE_DDR4 (0 << 0) 9927 #define SKL_DRAM_DDR_TYPE_DDR3 (1 << 0) 9928 #define SKL_DRAM_DDR_TYPE_LPDDR3 (2 << 0) 9929 #define SKL_DRAM_DDR_TYPE_LPDDR4 (3 << 0) 9930 9931 #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C) 9932 #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010) 9933 #define SKL_DRAM_S_SHIFT 16 9934 #define SKL_DRAM_SIZE_MASK 0x3F 9935 #define SKL_DRAM_WIDTH_MASK (0x3 << 8) 9936 #define SKL_DRAM_WIDTH_SHIFT 8 9937 #define SKL_DRAM_WIDTH_X8 (0x0 << 8) 9938 #define SKL_DRAM_WIDTH_X16 (0x1 << 8) 9939 #define SKL_DRAM_WIDTH_X32 (0x2 << 8) 9940 #define SKL_DRAM_RANK_MASK (0x1 << 10) 9941 #define SKL_DRAM_RANK_SHIFT 10 9942 #define SKL_DRAM_RANK_1 (0x0 << 10) 9943 #define SKL_DRAM_RANK_2 (0x1 << 10) 9944 #define SKL_DRAM_RANK_MASK (0x1 << 10) 9945 #define CNL_DRAM_SIZE_MASK 0x7F 9946 #define CNL_DRAM_WIDTH_MASK (0x3 << 7) 9947 #define CNL_DRAM_WIDTH_SHIFT 7 9948 #define CNL_DRAM_WIDTH_X8 (0x0 << 7) 9949 #define CNL_DRAM_WIDTH_X16 (0x1 << 7) 9950 #define CNL_DRAM_WIDTH_X32 (0x2 << 7) 9951 #define CNL_DRAM_RANK_MASK (0x3 << 9) 9952 #define CNL_DRAM_RANK_SHIFT 9 9953 #define CNL_DRAM_RANK_1 (0x0 << 9) 9954 #define CNL_DRAM_RANK_2 (0x1 << 9) 9955 #define CNL_DRAM_RANK_3 (0x2 << 9) 9956 #define CNL_DRAM_RANK_4 (0x3 << 9) 9957 9958 /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register, 9959 * since on HSW we can't write to it using I915_WRITE. */ 9960 #define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C) 9961 #define D_COMP_BDW _MMIO(0x138144) 9962 #define D_COMP_RCOMP_IN_PROGRESS (1 << 9) 9963 #define D_COMP_COMP_FORCE (1 << 8) 9964 #define D_COMP_COMP_DISABLE (1 << 0) 9965 9966 /* Pipe WM_LINETIME - watermark line time */ 9967 #define _PIPE_WM_LINETIME_A 0x45270 9968 #define _PIPE_WM_LINETIME_B 0x45274 9969 #define PIPE_WM_LINETIME(pipe) _MMIO_PIPE(pipe, _PIPE_WM_LINETIME_A, _PIPE_WM_LINETIME_B) 9970 #define PIPE_WM_LINETIME_MASK (0x1ff) 9971 #define PIPE_WM_LINETIME_TIME(x) ((x)) 9972 #define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff << 16) 9973 #define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x) << 16) 9974 9975 /* SFUSE_STRAP */ 9976 #define SFUSE_STRAP _MMIO(0xc2014) 9977 #define SFUSE_STRAP_FUSE_LOCK (1 << 13) 9978 #define SFUSE_STRAP_RAW_FREQUENCY (1 << 8) 9979 #define SFUSE_STRAP_DISPLAY_DISABLED (1 << 7) 9980 #define SFUSE_STRAP_CRT_DISABLED (1 << 6) 9981 #define SFUSE_STRAP_DDIF_DETECTED (1 << 3) 9982 #define SFUSE_STRAP_DDIB_DETECTED (1 << 2) 9983 #define SFUSE_STRAP_DDIC_DETECTED (1 << 1) 9984 #define SFUSE_STRAP_DDID_DETECTED (1 << 0) 9985 9986 #define WM_MISC _MMIO(0x45260) 9987 #define WM_MISC_DATA_PARTITION_5_6 (1 << 0) 9988 9989 #define WM_DBG _MMIO(0x45280) 9990 #define WM_DBG_DISALLOW_MULTIPLE_LP (1 << 0) 9991 #define WM_DBG_DISALLOW_MAXFIFO (1 << 1) 9992 #define WM_DBG_DISALLOW_SPRITE (1 << 2) 9993 9994 /* pipe CSC */ 9995 #define _PIPE_A_CSC_COEFF_RY_GY 0x49010 9996 #define _PIPE_A_CSC_COEFF_BY 0x49014 9997 #define _PIPE_A_CSC_COEFF_RU_GU 0x49018 9998 #define _PIPE_A_CSC_COEFF_BU 0x4901c 9999 #define _PIPE_A_CSC_COEFF_RV_GV 0x49020 10000 #define _PIPE_A_CSC_COEFF_BV 0x49024 10001 10002 #define _PIPE_A_CSC_MODE 0x49028 10003 #define ICL_CSC_ENABLE (1 << 31) 10004 #define ICL_OUTPUT_CSC_ENABLE (1 << 30) 10005 #define CSC_BLACK_SCREEN_OFFSET (1 << 2) 10006 #define CSC_POSITION_BEFORE_GAMMA (1 << 1) 10007 #define CSC_MODE_YUV_TO_RGB (1 << 0) 10008 10009 #define _PIPE_A_CSC_PREOFF_HI 0x49030 10010 #define _PIPE_A_CSC_PREOFF_ME 0x49034 10011 #define _PIPE_A_CSC_PREOFF_LO 0x49038 10012 #define _PIPE_A_CSC_POSTOFF_HI 0x49040 10013 #define _PIPE_A_CSC_POSTOFF_ME 0x49044 10014 #define _PIPE_A_CSC_POSTOFF_LO 0x49048 10015 10016 #define _PIPE_B_CSC_COEFF_RY_GY 0x49110 10017 #define _PIPE_B_CSC_COEFF_BY 0x49114 10018 #define _PIPE_B_CSC_COEFF_RU_GU 0x49118 10019 #define _PIPE_B_CSC_COEFF_BU 0x4911c 10020 #define _PIPE_B_CSC_COEFF_RV_GV 0x49120 10021 #define _PIPE_B_CSC_COEFF_BV 0x49124 10022 #define _PIPE_B_CSC_MODE 0x49128 10023 #define _PIPE_B_CSC_PREOFF_HI 0x49130 10024 #define _PIPE_B_CSC_PREOFF_ME 0x49134 10025 #define _PIPE_B_CSC_PREOFF_LO 0x49138 10026 #define _PIPE_B_CSC_POSTOFF_HI 0x49140 10027 #define _PIPE_B_CSC_POSTOFF_ME 0x49144 10028 #define _PIPE_B_CSC_POSTOFF_LO 0x49148 10029 10030 #define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY) 10031 #define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY) 10032 #define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU) 10033 #define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU) 10034 #define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV) 10035 #define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV) 10036 #define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE) 10037 #define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI) 10038 #define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME) 10039 #define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO) 10040 #define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI) 10041 #define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME) 10042 #define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) 10043 10044 /* Pipe Output CSC */ 10045 #define _PIPE_A_OUTPUT_CSC_COEFF_RY_GY 0x49050 10046 #define _PIPE_A_OUTPUT_CSC_COEFF_BY 0x49054 10047 #define _PIPE_A_OUTPUT_CSC_COEFF_RU_GU 0x49058 10048 #define _PIPE_A_OUTPUT_CSC_COEFF_BU 0x4905c 10049 #define _PIPE_A_OUTPUT_CSC_COEFF_RV_GV 0x49060 10050 #define _PIPE_A_OUTPUT_CSC_COEFF_BV 0x49064 10051 #define _PIPE_A_OUTPUT_CSC_PREOFF_HI 0x49068 10052 #define _PIPE_A_OUTPUT_CSC_PREOFF_ME 0x4906c 10053 #define _PIPE_A_OUTPUT_CSC_PREOFF_LO 0x49070 10054 #define _PIPE_A_OUTPUT_CSC_POSTOFF_HI 0x49074 10055 #define _PIPE_A_OUTPUT_CSC_POSTOFF_ME 0x49078 10056 #define _PIPE_A_OUTPUT_CSC_POSTOFF_LO 0x4907c 10057 10058 #define _PIPE_B_OUTPUT_CSC_COEFF_RY_GY 0x49150 10059 #define _PIPE_B_OUTPUT_CSC_COEFF_BY 0x49154 10060 #define _PIPE_B_OUTPUT_CSC_COEFF_RU_GU 0x49158 10061 #define _PIPE_B_OUTPUT_CSC_COEFF_BU 0x4915c 10062 #define _PIPE_B_OUTPUT_CSC_COEFF_RV_GV 0x49160 10063 #define _PIPE_B_OUTPUT_CSC_COEFF_BV 0x49164 10064 #define _PIPE_B_OUTPUT_CSC_PREOFF_HI 0x49168 10065 #define _PIPE_B_OUTPUT_CSC_PREOFF_ME 0x4916c 10066 #define _PIPE_B_OUTPUT_CSC_PREOFF_LO 0x49170 10067 #define _PIPE_B_OUTPUT_CSC_POSTOFF_HI 0x49174 10068 #define _PIPE_B_OUTPUT_CSC_POSTOFF_ME 0x49178 10069 #define _PIPE_B_OUTPUT_CSC_POSTOFF_LO 0x4917c 10070 10071 #define PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe,\ 10072 _PIPE_A_OUTPUT_CSC_COEFF_RY_GY,\ 10073 _PIPE_B_OUTPUT_CSC_COEFF_RY_GY) 10074 #define PIPE_CSC_OUTPUT_COEFF_BY(pipe) _MMIO_PIPE(pipe, \ 10075 _PIPE_A_OUTPUT_CSC_COEFF_BY, \ 10076 _PIPE_B_OUTPUT_CSC_COEFF_BY) 10077 #define PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, \ 10078 _PIPE_A_OUTPUT_CSC_COEFF_RU_GU, \ 10079 _PIPE_B_OUTPUT_CSC_COEFF_RU_GU) 10080 #define PIPE_CSC_OUTPUT_COEFF_BU(pipe) _MMIO_PIPE(pipe, \ 10081 _PIPE_A_OUTPUT_CSC_COEFF_BU, \ 10082 _PIPE_B_OUTPUT_CSC_COEFF_BU) 10083 #define PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, \ 10084 _PIPE_A_OUTPUT_CSC_COEFF_RV_GV, \ 10085 _PIPE_B_OUTPUT_CSC_COEFF_RV_GV) 10086 #define PIPE_CSC_OUTPUT_COEFF_BV(pipe) _MMIO_PIPE(pipe, \ 10087 _PIPE_A_OUTPUT_CSC_COEFF_BV, \ 10088 _PIPE_B_OUTPUT_CSC_COEFF_BV) 10089 #define PIPE_CSC_OUTPUT_PREOFF_HI(pipe) _MMIO_PIPE(pipe, \ 10090 _PIPE_A_OUTPUT_CSC_PREOFF_HI, \ 10091 _PIPE_B_OUTPUT_CSC_PREOFF_HI) 10092 #define PIPE_CSC_OUTPUT_PREOFF_ME(pipe) _MMIO_PIPE(pipe, \ 10093 _PIPE_A_OUTPUT_CSC_PREOFF_ME, \ 10094 _PIPE_B_OUTPUT_CSC_PREOFF_ME) 10095 #define PIPE_CSC_OUTPUT_PREOFF_LO(pipe) _MMIO_PIPE(pipe, \ 10096 _PIPE_A_OUTPUT_CSC_PREOFF_LO, \ 10097 _PIPE_B_OUTPUT_CSC_PREOFF_LO) 10098 #define PIPE_CSC_OUTPUT_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, \ 10099 _PIPE_A_OUTPUT_CSC_POSTOFF_HI, \ 10100 _PIPE_B_OUTPUT_CSC_POSTOFF_HI) 10101 #define PIPE_CSC_OUTPUT_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, \ 10102 _PIPE_A_OUTPUT_CSC_POSTOFF_ME, \ 10103 _PIPE_B_OUTPUT_CSC_POSTOFF_ME) 10104 #define PIPE_CSC_OUTPUT_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, \ 10105 _PIPE_A_OUTPUT_CSC_POSTOFF_LO, \ 10106 _PIPE_B_OUTPUT_CSC_POSTOFF_LO) 10107 10108 /* pipe degamma/gamma LUTs on IVB+ */ 10109 #define _PAL_PREC_INDEX_A 0x4A400 10110 #define _PAL_PREC_INDEX_B 0x4AC00 10111 #define _PAL_PREC_INDEX_C 0x4B400 10112 #define PAL_PREC_10_12_BIT (0 << 31) 10113 #define PAL_PREC_SPLIT_MODE (1 << 31) 10114 #define PAL_PREC_AUTO_INCREMENT (1 << 15) 10115 #define PAL_PREC_INDEX_VALUE_MASK (0x3ff << 0) 10116 #define PAL_PREC_INDEX_VALUE(x) ((x) << 0) 10117 #define _PAL_PREC_DATA_A 0x4A404 10118 #define _PAL_PREC_DATA_B 0x4AC04 10119 #define _PAL_PREC_DATA_C 0x4B404 10120 #define _PAL_PREC_GC_MAX_A 0x4A410 10121 #define _PAL_PREC_GC_MAX_B 0x4AC10 10122 #define _PAL_PREC_GC_MAX_C 0x4B410 10123 #define _PAL_PREC_EXT_GC_MAX_A 0x4A420 10124 #define _PAL_PREC_EXT_GC_MAX_B 0x4AC20 10125 #define _PAL_PREC_EXT_GC_MAX_C 0x4B420 10126 #define _PAL_PREC_EXT2_GC_MAX_A 0x4A430 10127 #define _PAL_PREC_EXT2_GC_MAX_B 0x4AC30 10128 #define _PAL_PREC_EXT2_GC_MAX_C 0x4B430 10129 10130 #define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B) 10131 #define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B) 10132 #define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4) 10133 #define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4) 10134 #define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4) 10135 10136 #define _PRE_CSC_GAMC_INDEX_A 0x4A484 10137 #define _PRE_CSC_GAMC_INDEX_B 0x4AC84 10138 #define _PRE_CSC_GAMC_INDEX_C 0x4B484 10139 #define PRE_CSC_GAMC_AUTO_INCREMENT (1 << 10) 10140 #define _PRE_CSC_GAMC_DATA_A 0x4A488 10141 #define _PRE_CSC_GAMC_DATA_B 0x4AC88 10142 #define _PRE_CSC_GAMC_DATA_C 0x4B488 10143 10144 #define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B) 10145 #define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B) 10146 10147 /* pipe CSC & degamma/gamma LUTs on CHV */ 10148 #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900) 10149 #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904) 10150 #define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908) 10151 #define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C) 10152 #define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910) 10153 #define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000) 10154 #define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000) 10155 #define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00) 10156 #define CGM_PIPE_MODE_GAMMA (1 << 2) 10157 #define CGM_PIPE_MODE_CSC (1 << 1) 10158 #define CGM_PIPE_MODE_DEGAMMA (1 << 0) 10159 10160 #define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900) 10161 #define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904) 10162 #define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908) 10163 #define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C) 10164 #define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910) 10165 #define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000) 10166 #define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000) 10167 #define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00) 10168 10169 #define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01) 10170 #define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23) 10171 #define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45) 10172 #define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67) 10173 #define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8) 10174 #define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4) 10175 #define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4) 10176 #define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE) 10177 10178 /* MIPI DSI registers */ 10179 10180 #define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */ 10181 #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c)) 10182 10183 /* Gen11 DSI */ 10184 #define _MMIO_DSI(tc, dsi0, dsi1) _MMIO_TRANS((tc) - TRANSCODER_DSI_0, \ 10185 dsi0, dsi1) 10186 10187 #define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004) 10188 #define GLK_TX_ESC_CLK_DIV1_MASK 0x3FF 10189 #define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008) 10190 #define GLK_TX_ESC_CLK_DIV2_MASK 0x3FF 10191 10192 #define _ICL_DSI_ESC_CLK_DIV0 0x6b090 10193 #define _ICL_DSI_ESC_CLK_DIV1 0x6b890 10194 #define ICL_DSI_ESC_CLK_DIV(port) _MMIO_PORT((port), \ 10195 _ICL_DSI_ESC_CLK_DIV0, \ 10196 _ICL_DSI_ESC_CLK_DIV1) 10197 #define _ICL_DPHY_ESC_CLK_DIV0 0x162190 10198 #define _ICL_DPHY_ESC_CLK_DIV1 0x6C190 10199 #define ICL_DPHY_ESC_CLK_DIV(port) _MMIO_PORT((port), \ 10200 _ICL_DPHY_ESC_CLK_DIV0, \ 10201 _ICL_DPHY_ESC_CLK_DIV1) 10202 #define ICL_BYTE_CLK_PER_ESC_CLK_MASK (0x1f << 16) 10203 #define ICL_BYTE_CLK_PER_ESC_CLK_SHIFT 16 10204 #define ICL_ESC_CLK_DIV_MASK 0x1ff 10205 #define ICL_ESC_CLK_DIV_SHIFT 0 10206 #define DSI_MAX_ESC_CLK 20000 /* in KHz */ 10207 10208 /* Gen4+ Timestamp and Pipe Frame time stamp registers */ 10209 #define GEN4_TIMESTAMP _MMIO(0x2358) 10210 #define ILK_TIMESTAMP_HI _MMIO(0x70070) 10211 #define IVB_TIMESTAMP_CTR _MMIO(0x44070) 10212 10213 #define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074) 10214 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0 10215 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff 10216 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12 10217 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12) 10218 10219 #define _PIPE_FRMTMSTMP_A 0x70048 10220 #define PIPE_FRMTMSTMP(pipe) \ 10221 _MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A) 10222 10223 /* BXT MIPI clock controls */ 10224 #define BXT_MAX_VAR_OUTPUT_KHZ 39500 10225 10226 #define BXT_MIPI_CLOCK_CTL _MMIO(0x46090) 10227 #define BXT_MIPI1_DIV_SHIFT 26 10228 #define BXT_MIPI2_DIV_SHIFT 10 10229 #define BXT_MIPI_DIV_SHIFT(port) \ 10230 _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \ 10231 BXT_MIPI2_DIV_SHIFT) 10232 10233 /* TX control divider to select actual TX clock output from (8x/var) */ 10234 #define BXT_MIPI1_TX_ESCLK_SHIFT 26 10235 #define BXT_MIPI2_TX_ESCLK_SHIFT 10 10236 #define BXT_MIPI_TX_ESCLK_SHIFT(port) \ 10237 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \ 10238 BXT_MIPI2_TX_ESCLK_SHIFT) 10239 #define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (0x3F << 26) 10240 #define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (0x3F << 10) 10241 #define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \ 10242 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \ 10243 BXT_MIPI2_TX_ESCLK_FIXDIV_MASK) 10244 #define BXT_MIPI_TX_ESCLK_DIVIDER(port, val) \ 10245 (((val) & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port)) 10246 /* RX upper control divider to select actual RX clock output from 8x */ 10247 #define BXT_MIPI1_RX_ESCLK_UPPER_SHIFT 21 10248 #define BXT_MIPI2_RX_ESCLK_UPPER_SHIFT 5 10249 #define BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port) \ 10250 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \ 10251 BXT_MIPI2_RX_ESCLK_UPPER_SHIFT) 10252 #define BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 21) 10253 #define BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 5) 10254 #define BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port) \ 10255 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK, \ 10256 BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK) 10257 #define BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val) \ 10258 (((val) & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port)) 10259 /* 8/3X divider to select the actual 8/3X clock output from 8x */ 10260 #define BXT_MIPI1_8X_BY3_SHIFT 19 10261 #define BXT_MIPI2_8X_BY3_SHIFT 3 10262 #define BXT_MIPI_8X_BY3_SHIFT(port) \ 10263 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \ 10264 BXT_MIPI2_8X_BY3_SHIFT) 10265 #define BXT_MIPI1_8X_BY3_DIVIDER_MASK (3 << 19) 10266 #define BXT_MIPI2_8X_BY3_DIVIDER_MASK (3 << 3) 10267 #define BXT_MIPI_8X_BY3_DIVIDER_MASK(port) \ 10268 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \ 10269 BXT_MIPI2_8X_BY3_DIVIDER_MASK) 10270 #define BXT_MIPI_8X_BY3_DIVIDER(port, val) \ 10271 (((val) & 3) << BXT_MIPI_8X_BY3_SHIFT(port)) 10272 /* RX lower control divider to select actual RX clock output from 8x */ 10273 #define BXT_MIPI1_RX_ESCLK_LOWER_SHIFT 16 10274 #define BXT_MIPI2_RX_ESCLK_LOWER_SHIFT 0 10275 #define BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port) \ 10276 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \ 10277 BXT_MIPI2_RX_ESCLK_LOWER_SHIFT) 10278 #define BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 16) 10279 #define BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 0) 10280 #define BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port) \ 10281 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \ 10282 BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK) 10283 #define BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val) \ 10284 (((val) & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port)) 10285 10286 #define RX_DIVIDER_BIT_1_2 0x3 10287 #define RX_DIVIDER_BIT_3_4 0xC 10288 10289 /* BXT MIPI mode configure */ 10290 #define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8 10291 #define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8 10292 #define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(tc, \ 10293 _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE) 10294 10295 #define _BXT_MIPIA_TRANS_VACTIVE 0x6B0FC 10296 #define _BXT_MIPIC_TRANS_VACTIVE 0x6B8FC 10297 #define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(tc, \ 10298 _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE) 10299 10300 #define _BXT_MIPIA_TRANS_VTOTAL 0x6B100 10301 #define _BXT_MIPIC_TRANS_VTOTAL 0x6B900 10302 #define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(tc, \ 10303 _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL) 10304 10305 #define BXT_DSI_PLL_CTL _MMIO(0x161000) 10306 #define BXT_DSI_PLL_PVD_RATIO_SHIFT 16 10307 #define BXT_DSI_PLL_PVD_RATIO_MASK (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT) 10308 #define BXT_DSI_PLL_PVD_RATIO_1 (1 << BXT_DSI_PLL_PVD_RATIO_SHIFT) 10309 #define BXT_DSIC_16X_BY1 (0 << 10) 10310 #define BXT_DSIC_16X_BY2 (1 << 10) 10311 #define BXT_DSIC_16X_BY3 (2 << 10) 10312 #define BXT_DSIC_16X_BY4 (3 << 10) 10313 #define BXT_DSIC_16X_MASK (3 << 10) 10314 #define BXT_DSIA_16X_BY1 (0 << 8) 10315 #define BXT_DSIA_16X_BY2 (1 << 8) 10316 #define BXT_DSIA_16X_BY3 (2 << 8) 10317 #define BXT_DSIA_16X_BY4 (3 << 8) 10318 #define BXT_DSIA_16X_MASK (3 << 8) 10319 #define BXT_DSI_FREQ_SEL_SHIFT 8 10320 #define BXT_DSI_FREQ_SEL_MASK (0xF << BXT_DSI_FREQ_SEL_SHIFT) 10321 10322 #define BXT_DSI_PLL_RATIO_MAX 0x7D 10323 #define BXT_DSI_PLL_RATIO_MIN 0x22 10324 #define GLK_DSI_PLL_RATIO_MAX 0x6F 10325 #define GLK_DSI_PLL_RATIO_MIN 0x22 10326 #define BXT_DSI_PLL_RATIO_MASK 0xFF 10327 #define BXT_REF_CLOCK_KHZ 19200 10328 10329 #define BXT_DSI_PLL_ENABLE _MMIO(0x46080) 10330 #define BXT_DSI_PLL_DO_ENABLE (1 << 31) 10331 #define BXT_DSI_PLL_LOCKED (1 << 30) 10332 10333 #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) 10334 #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) 10335 #define MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL) 10336 10337 /* BXT port control */ 10338 #define _BXT_MIPIA_PORT_CTRL 0x6B0C0 10339 #define _BXT_MIPIC_PORT_CTRL 0x6B8C0 10340 #define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL) 10341 10342 /* ICL DSI MODE control */ 10343 #define _ICL_DSI_IO_MODECTL_0 0x6B094 10344 #define _ICL_DSI_IO_MODECTL_1 0x6B894 10345 #define ICL_DSI_IO_MODECTL(port) _MMIO_PORT(port, \ 10346 _ICL_DSI_IO_MODECTL_0, \ 10347 _ICL_DSI_IO_MODECTL_1) 10348 #define COMBO_PHY_MODE_DSI (1 << 0) 10349 10350 /* Display Stream Splitter Control */ 10351 #define DSS_CTL1 _MMIO(0x67400) 10352 #define SPLITTER_ENABLE (1 << 31) 10353 #define JOINER_ENABLE (1 << 30) 10354 #define DUAL_LINK_MODE_INTERLEAVE (1 << 24) 10355 #define DUAL_LINK_MODE_FRONTBACK (0 << 24) 10356 #define OVERLAP_PIXELS_MASK (0xf << 16) 10357 #define OVERLAP_PIXELS(pixels) ((pixels) << 16) 10358 #define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) 10359 #define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) 10360 #define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0 10361 10362 #define DSS_CTL2 _MMIO(0x67404) 10363 #define LEFT_BRANCH_VDSC_ENABLE (1 << 31) 10364 #define RIGHT_BRANCH_VDSC_ENABLE (1 << 15) 10365 #define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) 10366 #define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) 10367 10368 #define _ICL_PIPE_DSS_CTL1_PB 0x78200 10369 #define _ICL_PIPE_DSS_CTL1_PC 0x78400 10370 #define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 10371 _ICL_PIPE_DSS_CTL1_PB, \ 10372 _ICL_PIPE_DSS_CTL1_PC) 10373 #define BIG_JOINER_ENABLE (1 << 29) 10374 #define MASTER_BIG_JOINER_ENABLE (1 << 28) 10375 #define VGA_CENTERING_ENABLE (1 << 27) 10376 10377 #define _ICL_PIPE_DSS_CTL2_PB 0x78204 10378 #define _ICL_PIPE_DSS_CTL2_PC 0x78404 10379 #define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 10380 _ICL_PIPE_DSS_CTL2_PB, \ 10381 _ICL_PIPE_DSS_CTL2_PC) 10382 10383 #define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020) 10384 #define STAP_SELECT (1 << 0) 10385 10386 #define BXT_P_DSI_REGULATOR_TX_CTRL _MMIO(0x160054) 10387 #define HS_IO_CTRL_SELECT (1 << 0) 10388 10389 #define DPI_ENABLE (1 << 31) /* A + C */ 10390 #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27 10391 #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27) 10392 #define DUAL_LINK_MODE_SHIFT 26 10393 #define DUAL_LINK_MODE_MASK (1 << 26) 10394 #define DUAL_LINK_MODE_FRONT_BACK (0 << 26) 10395 #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26) 10396 #define DITHERING_ENABLE (1 << 25) /* A + C */ 10397 #define FLOPPED_HSTX (1 << 23) 10398 #define DE_INVERT (1 << 19) /* XXX */ 10399 #define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18 10400 #define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18) 10401 #define AFE_LATCHOUT (1 << 17) 10402 #define LP_OUTPUT_HOLD (1 << 16) 10403 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15 10404 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15) 10405 #define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11 10406 #define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11) 10407 #define CSB_SHIFT 9 10408 #define CSB_MASK (3 << 9) 10409 #define CSB_20MHZ (0 << 9) 10410 #define CSB_10MHZ (1 << 9) 10411 #define CSB_40MHZ (2 << 9) 10412 #define BANDGAP_MASK (1 << 8) 10413 #define BANDGAP_PNW_CIRCUIT (0 << 8) 10414 #define BANDGAP_LNC_CIRCUIT (1 << 8) 10415 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5 10416 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5) 10417 #define TEARING_EFFECT_DELAY (1 << 4) /* A + C */ 10418 #define TEARING_EFFECT_SHIFT 2 /* A + C */ 10419 #define TEARING_EFFECT_MASK (3 << 2) 10420 #define TEARING_EFFECT_OFF (0 << 2) 10421 #define TEARING_EFFECT_DSI (1 << 2) 10422 #define TEARING_EFFECT_GPIO (2 << 2) 10423 #define LANE_CONFIGURATION_SHIFT 0 10424 #define LANE_CONFIGURATION_MASK (3 << 0) 10425 #define LANE_CONFIGURATION_4LANE (0 << 0) 10426 #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0) 10427 #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0) 10428 10429 #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194) 10430 #define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) 10431 #define MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL) 10432 #define TEARING_EFFECT_DELAY_SHIFT 0 10433 #define TEARING_EFFECT_DELAY_MASK (0xffff << 0) 10434 10435 /* XXX: all bits reserved */ 10436 #define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0) 10437 10438 /* MIPI DSI Controller and D-PHY registers */ 10439 10440 #define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000) 10441 #define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800) 10442 #define MIPI_DEVICE_READY(port) _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY) 10443 #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */ 10444 #define ULPS_STATE_MASK (3 << 1) 10445 #define ULPS_STATE_ENTER (2 << 1) 10446 #define ULPS_STATE_EXIT (1 << 1) 10447 #define ULPS_STATE_NORMAL_OPERATION (0 << 1) 10448 #define DEVICE_READY (1 << 0) 10449 10450 #define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004) 10451 #define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804) 10452 #define MIPI_INTR_STAT(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT) 10453 #define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008) 10454 #define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808) 10455 #define MIPI_INTR_EN(port) _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN) 10456 #define TEARING_EFFECT (1 << 31) 10457 #define SPL_PKT_SENT_INTERRUPT (1 << 30) 10458 #define GEN_READ_DATA_AVAIL (1 << 29) 10459 #define LP_GENERIC_WR_FIFO_FULL (1 << 28) 10460 #define HS_GENERIC_WR_FIFO_FULL (1 << 27) 10461 #define RX_PROT_VIOLATION (1 << 26) 10462 #define RX_INVALID_TX_LENGTH (1 << 25) 10463 #define ACK_WITH_NO_ERROR (1 << 24) 10464 #define TURN_AROUND_ACK_TIMEOUT (1 << 23) 10465 #define LP_RX_TIMEOUT (1 << 22) 10466 #define HS_TX_TIMEOUT (1 << 21) 10467 #define DPI_FIFO_UNDERRUN (1 << 20) 10468 #define LOW_CONTENTION (1 << 19) 10469 #define HIGH_CONTENTION (1 << 18) 10470 #define TXDSI_VC_ID_INVALID (1 << 17) 10471 #define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16) 10472 #define TXCHECKSUM_ERROR (1 << 15) 10473 #define TXECC_MULTIBIT_ERROR (1 << 14) 10474 #define TXECC_SINGLE_BIT_ERROR (1 << 13) 10475 #define TXFALSE_CONTROL_ERROR (1 << 12) 10476 #define RXDSI_VC_ID_INVALID (1 << 11) 10477 #define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10) 10478 #define RXCHECKSUM_ERROR (1 << 9) 10479 #define RXECC_MULTIBIT_ERROR (1 << 8) 10480 #define RXECC_SINGLE_BIT_ERROR (1 << 7) 10481 #define RXFALSE_CONTROL_ERROR (1 << 6) 10482 #define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5) 10483 #define RX_LP_TX_SYNC_ERROR (1 << 4) 10484 #define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3) 10485 #define RXEOT_SYNC_ERROR (1 << 2) 10486 #define RXSOT_SYNC_ERROR (1 << 1) 10487 #define RXSOT_ERROR (1 << 0) 10488 10489 #define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c) 10490 #define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c) 10491 #define MIPI_DSI_FUNC_PRG(port) _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG) 10492 #define CMD_MODE_DATA_WIDTH_MASK (7 << 13) 10493 #define CMD_MODE_NOT_SUPPORTED (0 << 13) 10494 #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13) 10495 #define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13) 10496 #define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13) 10497 #define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13) 10498 #define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13) 10499 #define VID_MODE_FORMAT_MASK (0xf << 7) 10500 #define VID_MODE_NOT_SUPPORTED (0 << 7) 10501 #define VID_MODE_FORMAT_RGB565 (1 << 7) 10502 #define VID_MODE_FORMAT_RGB666_PACKED (2 << 7) 10503 #define VID_MODE_FORMAT_RGB666 (3 << 7) 10504 #define VID_MODE_FORMAT_RGB888 (4 << 7) 10505 #define CMD_MODE_CHANNEL_NUMBER_SHIFT 5 10506 #define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5) 10507 #define VID_MODE_CHANNEL_NUMBER_SHIFT 3 10508 #define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3) 10509 #define DATA_LANES_PRG_REG_SHIFT 0 10510 #define DATA_LANES_PRG_REG_MASK (7 << 0) 10511 10512 #define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010) 10513 #define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810) 10514 #define MIPI_HS_TX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT) 10515 #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff 10516 10517 #define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014) 10518 #define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814) 10519 #define MIPI_LP_RX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT) 10520 #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff 10521 10522 #define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018) 10523 #define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818) 10524 #define MIPI_TURN_AROUND_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT) 10525 #define TURN_AROUND_TIMEOUT_MASK 0x3f 10526 10527 #define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c) 10528 #define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c) 10529 #define MIPI_DEVICE_RESET_TIMER(port) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER) 10530 #define DEVICE_RESET_TIMER_MASK 0xffff 10531 10532 #define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020) 10533 #define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820) 10534 #define MIPI_DPI_RESOLUTION(port) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION) 10535 #define VERTICAL_ADDRESS_SHIFT 16 10536 #define VERTICAL_ADDRESS_MASK (0xffff << 16) 10537 #define HORIZONTAL_ADDRESS_SHIFT 0 10538 #define HORIZONTAL_ADDRESS_MASK 0xffff 10539 10540 #define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024) 10541 #define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824) 10542 #define MIPI_DBI_FIFO_THROTTLE(port) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE) 10543 #define DBI_FIFO_EMPTY_HALF (0 << 0) 10544 #define DBI_FIFO_EMPTY_QUARTER (1 << 0) 10545 #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0) 10546 10547 /* regs below are bits 15:0 */ 10548 #define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028) 10549 #define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828) 10550 #define MIPI_HSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT) 10551 10552 #define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c) 10553 #define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c) 10554 #define MIPI_HBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT) 10555 10556 #define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030) 10557 #define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830) 10558 #define MIPI_HFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT) 10559 10560 #define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034) 10561 #define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834) 10562 #define MIPI_HACTIVE_AREA_COUNT(port) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT) 10563 10564 #define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038) 10565 #define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838) 10566 #define MIPI_VSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT) 10567 10568 #define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c) 10569 #define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c) 10570 #define MIPI_VBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT) 10571 10572 #define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040) 10573 #define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840) 10574 #define MIPI_VFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT) 10575 10576 #define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044) 10577 #define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844) 10578 #define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT) 10579 10580 /* regs above are bits 15:0 */ 10581 10582 #define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048) 10583 #define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848) 10584 #define MIPI_DPI_CONTROL(port) _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL) 10585 #define DPI_LP_MODE (1 << 6) 10586 #define BACKLIGHT_OFF (1 << 5) 10587 #define BACKLIGHT_ON (1 << 4) 10588 #define COLOR_MODE_OFF (1 << 3) 10589 #define COLOR_MODE_ON (1 << 2) 10590 #define TURN_ON (1 << 1) 10591 #define SHUTDOWN (1 << 0) 10592 10593 #define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c) 10594 #define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c) 10595 #define MIPI_DPI_DATA(port) _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA) 10596 #define COMMAND_BYTE_SHIFT 0 10597 #define COMMAND_BYTE_MASK (0x3f << 0) 10598 10599 #define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050) 10600 #define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850) 10601 #define MIPI_INIT_COUNT(port) _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT) 10602 #define MASTER_INIT_TIMER_SHIFT 0 10603 #define MASTER_INIT_TIMER_MASK (0xffff << 0) 10604 10605 #define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054) 10606 #define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854) 10607 #define MIPI_MAX_RETURN_PKT_SIZE(port) _MMIO_MIPI(port, \ 10608 _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE) 10609 #define MAX_RETURN_PKT_SIZE_SHIFT 0 10610 #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0) 10611 10612 #define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058) 10613 #define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858) 10614 #define MIPI_VIDEO_MODE_FORMAT(port) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT) 10615 #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4) 10616 #define DISABLE_VIDEO_BTA (1 << 3) 10617 #define IP_TG_CONFIG (1 << 2) 10618 #define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0) 10619 #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0) 10620 #define VIDEO_MODE_BURST (3 << 0) 10621 10622 #define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c) 10623 #define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c) 10624 #define MIPI_EOT_DISABLE(port) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE) 10625 #define BXT_DEFEATURE_DPI_FIFO_CTR (1 << 9) 10626 #define BXT_DPHY_DEFEATURE_EN (1 << 8) 10627 #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7) 10628 #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6) 10629 #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5) 10630 #define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4) 10631 #define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3) 10632 #define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2) 10633 #define CLOCKSTOP (1 << 1) 10634 #define EOT_DISABLE (1 << 0) 10635 10636 #define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060) 10637 #define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860) 10638 #define MIPI_LP_BYTECLK(port) _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK) 10639 #define LP_BYTECLK_SHIFT 0 10640 #define LP_BYTECLK_MASK (0xffff << 0) 10641 10642 #define _MIPIA_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb0a4) 10643 #define _MIPIC_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb8a4) 10644 #define MIPI_TLPX_TIME_COUNT(port) _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT) 10645 10646 #define _MIPIA_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb098) 10647 #define _MIPIC_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb898) 10648 #define MIPI_CLK_LANE_TIMING(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING) 10649 10650 /* bits 31:0 */ 10651 #define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064) 10652 #define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864) 10653 #define MIPI_LP_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA) 10654 10655 /* bits 31:0 */ 10656 #define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068) 10657 #define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868) 10658 #define MIPI_HS_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA) 10659 10660 #define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c) 10661 #define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c) 10662 #define MIPI_LP_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL) 10663 #define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070) 10664 #define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870) 10665 #define MIPI_HS_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL) 10666 #define LONG_PACKET_WORD_COUNT_SHIFT 8 10667 #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8) 10668 #define SHORT_PACKET_PARAM_SHIFT 8 10669 #define SHORT_PACKET_PARAM_MASK (0xffff << 8) 10670 #define VIRTUAL_CHANNEL_SHIFT 6 10671 #define VIRTUAL_CHANNEL_MASK (3 << 6) 10672 #define DATA_TYPE_SHIFT 0 10673 #define DATA_TYPE_MASK (0x3f << 0) 10674 /* data type values, see include/video/mipi_display.h */ 10675 10676 #define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074) 10677 #define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874) 10678 #define MIPI_GEN_FIFO_STAT(port) _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT) 10679 #define DPI_FIFO_EMPTY (1 << 28) 10680 #define DBI_FIFO_EMPTY (1 << 27) 10681 #define LP_CTRL_FIFO_EMPTY (1 << 26) 10682 #define LP_CTRL_FIFO_HALF_EMPTY (1 << 25) 10683 #define LP_CTRL_FIFO_FULL (1 << 24) 10684 #define HS_CTRL_FIFO_EMPTY (1 << 18) 10685 #define HS_CTRL_FIFO_HALF_EMPTY (1 << 17) 10686 #define HS_CTRL_FIFO_FULL (1 << 16) 10687 #define LP_DATA_FIFO_EMPTY (1 << 10) 10688 #define LP_DATA_FIFO_HALF_EMPTY (1 << 9) 10689 #define LP_DATA_FIFO_FULL (1 << 8) 10690 #define HS_DATA_FIFO_EMPTY (1 << 2) 10691 #define HS_DATA_FIFO_HALF_EMPTY (1 << 1) 10692 #define HS_DATA_FIFO_FULL (1 << 0) 10693 10694 #define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078) 10695 #define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878) 10696 #define MIPI_HS_LP_DBI_ENABLE(port) _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE) 10697 #define DBI_HS_LP_MODE_MASK (1 << 0) 10698 #define DBI_LP_MODE (1 << 0) 10699 #define DBI_HS_MODE (0 << 0) 10700 10701 #define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080) 10702 #define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880) 10703 #define MIPI_DPHY_PARAM(port) _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM) 10704 #define EXIT_ZERO_COUNT_SHIFT 24 10705 #define EXIT_ZERO_COUNT_MASK (0x3f << 24) 10706 #define TRAIL_COUNT_SHIFT 16 10707 #define TRAIL_COUNT_MASK (0x1f << 16) 10708 #define CLK_ZERO_COUNT_SHIFT 8 10709 #define CLK_ZERO_COUNT_MASK (0xff << 8) 10710 #define PREPARE_COUNT_SHIFT 0 10711 #define PREPARE_COUNT_MASK (0x3f << 0) 10712 10713 #define _ICL_DSI_T_INIT_MASTER_0 0x6b088 10714 #define _ICL_DSI_T_INIT_MASTER_1 0x6b888 10715 #define ICL_DSI_T_INIT_MASTER(port) _MMIO_PORT(port, \ 10716 _ICL_DSI_T_INIT_MASTER_0,\ 10717 _ICL_DSI_T_INIT_MASTER_1) 10718 10719 #define _DPHY_CLK_TIMING_PARAM_0 0x162180 10720 #define _DPHY_CLK_TIMING_PARAM_1 0x6c180 10721 #define DPHY_CLK_TIMING_PARAM(port) _MMIO_PORT(port, \ 10722 _DPHY_CLK_TIMING_PARAM_0,\ 10723 _DPHY_CLK_TIMING_PARAM_1) 10724 #define _DSI_CLK_TIMING_PARAM_0 0x6b080 10725 #define _DSI_CLK_TIMING_PARAM_1 0x6b880 10726 #define DSI_CLK_TIMING_PARAM(port) _MMIO_PORT(port, \ 10727 _DSI_CLK_TIMING_PARAM_0,\ 10728 _DSI_CLK_TIMING_PARAM_1) 10729 #define CLK_PREPARE_OVERRIDE (1 << 31) 10730 #define CLK_PREPARE(x) ((x) << 28) 10731 #define CLK_PREPARE_MASK (0x7 << 28) 10732 #define CLK_PREPARE_SHIFT 28 10733 #define CLK_ZERO_OVERRIDE (1 << 27) 10734 #define CLK_ZERO(x) ((x) << 20) 10735 #define CLK_ZERO_MASK (0xf << 20) 10736 #define CLK_ZERO_SHIFT 20 10737 #define CLK_PRE_OVERRIDE (1 << 19) 10738 #define CLK_PRE(x) ((x) << 16) 10739 #define CLK_PRE_MASK (0x3 << 16) 10740 #define CLK_PRE_SHIFT 16 10741 #define CLK_POST_OVERRIDE (1 << 15) 10742 #define CLK_POST(x) ((x) << 8) 10743 #define CLK_POST_MASK (0x7 << 8) 10744 #define CLK_POST_SHIFT 8 10745 #define CLK_TRAIL_OVERRIDE (1 << 7) 10746 #define CLK_TRAIL(x) ((x) << 0) 10747 #define CLK_TRAIL_MASK (0xf << 0) 10748 #define CLK_TRAIL_SHIFT 0 10749 10750 #define _DPHY_DATA_TIMING_PARAM_0 0x162184 10751 #define _DPHY_DATA_TIMING_PARAM_1 0x6c184 10752 #define DPHY_DATA_TIMING_PARAM(port) _MMIO_PORT(port, \ 10753 _DPHY_DATA_TIMING_PARAM_0,\ 10754 _DPHY_DATA_TIMING_PARAM_1) 10755 #define _DSI_DATA_TIMING_PARAM_0 0x6B084 10756 #define _DSI_DATA_TIMING_PARAM_1 0x6B884 10757 #define DSI_DATA_TIMING_PARAM(port) _MMIO_PORT(port, \ 10758 _DSI_DATA_TIMING_PARAM_0,\ 10759 _DSI_DATA_TIMING_PARAM_1) 10760 #define HS_PREPARE_OVERRIDE (1 << 31) 10761 #define HS_PREPARE(x) ((x) << 24) 10762 #define HS_PREPARE_MASK (0x7 << 24) 10763 #define HS_PREPARE_SHIFT 24 10764 #define HS_ZERO_OVERRIDE (1 << 23) 10765 #define HS_ZERO(x) ((x) << 16) 10766 #define HS_ZERO_MASK (0xf << 16) 10767 #define HS_ZERO_SHIFT 16 10768 #define HS_TRAIL_OVERRIDE (1 << 15) 10769 #define HS_TRAIL(x) ((x) << 8) 10770 #define HS_TRAIL_MASK (0x7 << 8) 10771 #define HS_TRAIL_SHIFT 8 10772 #define HS_EXIT_OVERRIDE (1 << 7) 10773 #define HS_EXIT(x) ((x) << 0) 10774 #define HS_EXIT_MASK (0x7 << 0) 10775 #define HS_EXIT_SHIFT 0 10776 10777 #define _DPHY_TA_TIMING_PARAM_0 0x162188 10778 #define _DPHY_TA_TIMING_PARAM_1 0x6c188 10779 #define DPHY_TA_TIMING_PARAM(port) _MMIO_PORT(port, \ 10780 _DPHY_TA_TIMING_PARAM_0,\ 10781 _DPHY_TA_TIMING_PARAM_1) 10782 #define _DSI_TA_TIMING_PARAM_0 0x6b098 10783 #define _DSI_TA_TIMING_PARAM_1 0x6b898 10784 #define DSI_TA_TIMING_PARAM(port) _MMIO_PORT(port, \ 10785 _DSI_TA_TIMING_PARAM_0,\ 10786 _DSI_TA_TIMING_PARAM_1) 10787 #define TA_SURE_OVERRIDE (1 << 31) 10788 #define TA_SURE(x) ((x) << 16) 10789 #define TA_SURE_MASK (0x1f << 16) 10790 #define TA_SURE_SHIFT 16 10791 #define TA_GO_OVERRIDE (1 << 15) 10792 #define TA_GO(x) ((x) << 8) 10793 #define TA_GO_MASK (0xf << 8) 10794 #define TA_GO_SHIFT 8 10795 #define TA_GET_OVERRIDE (1 << 7) 10796 #define TA_GET(x) ((x) << 0) 10797 #define TA_GET_MASK (0xf << 0) 10798 #define TA_GET_SHIFT 0 10799 10800 /* DSI transcoder configuration */ 10801 #define _DSI_TRANS_FUNC_CONF_0 0x6b030 10802 #define _DSI_TRANS_FUNC_CONF_1 0x6b830 10803 #define DSI_TRANS_FUNC_CONF(tc) _MMIO_DSI(tc, \ 10804 _DSI_TRANS_FUNC_CONF_0,\ 10805 _DSI_TRANS_FUNC_CONF_1) 10806 #define OP_MODE_MASK (0x3 << 28) 10807 #define OP_MODE_SHIFT 28 10808 #define CMD_MODE_NO_GATE (0x0 << 28) 10809 #define CMD_MODE_TE_GATE (0x1 << 28) 10810 #define VIDEO_MODE_SYNC_EVENT (0x2 << 28) 10811 #define VIDEO_MODE_SYNC_PULSE (0x3 << 28) 10812 #define LINK_READY (1 << 20) 10813 #define PIX_FMT_MASK (0x3 << 16) 10814 #define PIX_FMT_SHIFT 16 10815 #define PIX_FMT_RGB565 (0x0 << 16) 10816 #define PIX_FMT_RGB666_PACKED (0x1 << 16) 10817 #define PIX_FMT_RGB666_LOOSE (0x2 << 16) 10818 #define PIX_FMT_RGB888 (0x3 << 16) 10819 #define PIX_FMT_RGB101010 (0x4 << 16) 10820 #define PIX_FMT_RGB121212 (0x5 << 16) 10821 #define PIX_FMT_COMPRESSED (0x6 << 16) 10822 #define BGR_TRANSMISSION (1 << 15) 10823 #define PIX_VIRT_CHAN(x) ((x) << 12) 10824 #define PIX_VIRT_CHAN_MASK (0x3 << 12) 10825 #define PIX_VIRT_CHAN_SHIFT 12 10826 #define PIX_BUF_THRESHOLD_MASK (0x3 << 10) 10827 #define PIX_BUF_THRESHOLD_SHIFT 10 10828 #define PIX_BUF_THRESHOLD_1_4 (0x0 << 10) 10829 #define PIX_BUF_THRESHOLD_1_2 (0x1 << 10) 10830 #define PIX_BUF_THRESHOLD_3_4 (0x2 << 10) 10831 #define PIX_BUF_THRESHOLD_FULL (0x3 << 10) 10832 #define CONTINUOUS_CLK_MASK (0x3 << 8) 10833 #define CONTINUOUS_CLK_SHIFT 8 10834 #define CLK_ENTER_LP_AFTER_DATA (0x0 << 8) 10835 #define CLK_HS_OR_LP (0x2 << 8) 10836 #define CLK_HS_CONTINUOUS (0x3 << 8) 10837 #define LINK_CALIBRATION_MASK (0x3 << 4) 10838 #define LINK_CALIBRATION_SHIFT 4 10839 #define CALIBRATION_DISABLED (0x0 << 4) 10840 #define CALIBRATION_ENABLED_INITIAL_ONLY (0x2 << 4) 10841 #define CALIBRATION_ENABLED_INITIAL_PERIODIC (0x3 << 4) 10842 #define S3D_ORIENTATION_LANDSCAPE (1 << 1) 10843 #define EOTP_DISABLED (1 << 0) 10844 10845 #define _DSI_CMD_RXCTL_0 0x6b0d4 10846 #define _DSI_CMD_RXCTL_1 0x6b8d4 10847 #define DSI_CMD_RXCTL(tc) _MMIO_DSI(tc, \ 10848 _DSI_CMD_RXCTL_0,\ 10849 _DSI_CMD_RXCTL_1) 10850 #define READ_UNLOADS_DW (1 << 16) 10851 #define RECEIVED_UNASSIGNED_TRIGGER (1 << 15) 10852 #define RECEIVED_ACKNOWLEDGE_TRIGGER (1 << 14) 10853 #define RECEIVED_TEAR_EFFECT_TRIGGER (1 << 13) 10854 #define RECEIVED_RESET_TRIGGER (1 << 12) 10855 #define RECEIVED_PAYLOAD_WAS_LOST (1 << 11) 10856 #define RECEIVED_CRC_WAS_LOST (1 << 10) 10857 #define NUMBER_RX_PLOAD_DW_MASK (0xff << 0) 10858 #define NUMBER_RX_PLOAD_DW_SHIFT 0 10859 10860 #define _DSI_CMD_TXCTL_0 0x6b0d0 10861 #define _DSI_CMD_TXCTL_1 0x6b8d0 10862 #define DSI_CMD_TXCTL(tc) _MMIO_DSI(tc, \ 10863 _DSI_CMD_TXCTL_0,\ 10864 _DSI_CMD_TXCTL_1) 10865 #define KEEP_LINK_IN_HS (1 << 24) 10866 #define FREE_HEADER_CREDIT_MASK (0x1f << 8) 10867 #define FREE_HEADER_CREDIT_SHIFT 0x8 10868 #define FREE_PLOAD_CREDIT_MASK (0xff << 0) 10869 #define FREE_PLOAD_CREDIT_SHIFT 0 10870 #define MAX_HEADER_CREDIT 0x10 10871 #define MAX_PLOAD_CREDIT 0x40 10872 10873 #define _DSI_CMD_TXHDR_0 0x6b100 10874 #define _DSI_CMD_TXHDR_1 0x6b900 10875 #define DSI_CMD_TXHDR(tc) _MMIO_DSI(tc, \ 10876 _DSI_CMD_TXHDR_0,\ 10877 _DSI_CMD_TXHDR_1) 10878 #define PAYLOAD_PRESENT (1 << 31) 10879 #define LP_DATA_TRANSFER (1 << 30) 10880 #define VBLANK_FENCE (1 << 29) 10881 #define PARAM_WC_MASK (0xffff << 8) 10882 #define PARAM_WC_LOWER_SHIFT 8 10883 #define PARAM_WC_UPPER_SHIFT 16 10884 #define VC_MASK (0x3 << 6) 10885 #define VC_SHIFT 6 10886 #define DT_MASK (0x3f << 0) 10887 #define DT_SHIFT 0 10888 10889 #define _DSI_CMD_TXPYLD_0 0x6b104 10890 #define _DSI_CMD_TXPYLD_1 0x6b904 10891 #define DSI_CMD_TXPYLD(tc) _MMIO_DSI(tc, \ 10892 _DSI_CMD_TXPYLD_0,\ 10893 _DSI_CMD_TXPYLD_1) 10894 10895 #define _DSI_LP_MSG_0 0x6b0d8 10896 #define _DSI_LP_MSG_1 0x6b8d8 10897 #define DSI_LP_MSG(tc) _MMIO_DSI(tc, \ 10898 _DSI_LP_MSG_0,\ 10899 _DSI_LP_MSG_1) 10900 #define LPTX_IN_PROGRESS (1 << 17) 10901 #define LINK_IN_ULPS (1 << 16) 10902 #define LINK_ULPS_TYPE_LP11 (1 << 8) 10903 #define LINK_ENTER_ULPS (1 << 0) 10904 10905 /* DSI timeout registers */ 10906 #define _DSI_HSTX_TO_0 0x6b044 10907 #define _DSI_HSTX_TO_1 0x6b844 10908 #define DSI_HSTX_TO(tc) _MMIO_DSI(tc, \ 10909 _DSI_HSTX_TO_0,\ 10910 _DSI_HSTX_TO_1) 10911 #define HSTX_TIMEOUT_VALUE_MASK (0xffff << 16) 10912 #define HSTX_TIMEOUT_VALUE_SHIFT 16 10913 #define HSTX_TIMEOUT_VALUE(x) ((x) << 16) 10914 #define HSTX_TIMED_OUT (1 << 0) 10915 10916 #define _DSI_LPRX_HOST_TO_0 0x6b048 10917 #define _DSI_LPRX_HOST_TO_1 0x6b848 10918 #define DSI_LPRX_HOST_TO(tc) _MMIO_DSI(tc, \ 10919 _DSI_LPRX_HOST_TO_0,\ 10920 _DSI_LPRX_HOST_TO_1) 10921 #define LPRX_TIMED_OUT (1 << 16) 10922 #define LPRX_TIMEOUT_VALUE_MASK (0xffff << 0) 10923 #define LPRX_TIMEOUT_VALUE_SHIFT 0 10924 #define LPRX_TIMEOUT_VALUE(x) ((x) << 0) 10925 10926 #define _DSI_PWAIT_TO_0 0x6b040 10927 #define _DSI_PWAIT_TO_1 0x6b840 10928 #define DSI_PWAIT_TO(tc) _MMIO_DSI(tc, \ 10929 _DSI_PWAIT_TO_0,\ 10930 _DSI_PWAIT_TO_1) 10931 #define PRESET_TIMEOUT_VALUE_MASK (0xffff << 16) 10932 #define PRESET_TIMEOUT_VALUE_SHIFT 16 10933 #define PRESET_TIMEOUT_VALUE(x) ((x) << 16) 10934 #define PRESPONSE_TIMEOUT_VALUE_MASK (0xffff << 0) 10935 #define PRESPONSE_TIMEOUT_VALUE_SHIFT 0 10936 #define PRESPONSE_TIMEOUT_VALUE(x) ((x) << 0) 10937 10938 #define _DSI_TA_TO_0 0x6b04c 10939 #define _DSI_TA_TO_1 0x6b84c 10940 #define DSI_TA_TO(tc) _MMIO_DSI(tc, \ 10941 _DSI_TA_TO_0,\ 10942 _DSI_TA_TO_1) 10943 #define TA_TIMED_OUT (1 << 16) 10944 #define TA_TIMEOUT_VALUE_MASK (0xffff << 0) 10945 #define TA_TIMEOUT_VALUE_SHIFT 0 10946 #define TA_TIMEOUT_VALUE(x) ((x) << 0) 10947 10948 /* bits 31:0 */ 10949 #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084) 10950 #define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884) 10951 #define MIPI_DBI_BW_CTRL(port) _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL) 10952 10953 #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb088) 10954 #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb888) 10955 #define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT) 10956 #define LP_HS_SSW_CNT_SHIFT 16 10957 #define LP_HS_SSW_CNT_MASK (0xffff << 16) 10958 #define HS_LP_PWR_SW_CNT_SHIFT 0 10959 #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0) 10960 10961 #define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c) 10962 #define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c) 10963 #define MIPI_STOP_STATE_STALL(port) _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL) 10964 #define STOP_STATE_STALL_COUNTER_SHIFT 0 10965 #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0) 10966 10967 #define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090) 10968 #define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890) 10969 #define MIPI_INTR_STAT_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1) 10970 #define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094) 10971 #define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894) 10972 #define MIPI_INTR_EN_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1) 10973 #define RX_CONTENTION_DETECTED (1 << 0) 10974 10975 /* XXX: only pipe A ?!? */ 10976 #define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100) 10977 #define DBI_TYPEC_ENABLE (1 << 31) 10978 #define DBI_TYPEC_WIP (1 << 30) 10979 #define DBI_TYPEC_OPTION_SHIFT 28 10980 #define DBI_TYPEC_OPTION_MASK (3 << 28) 10981 #define DBI_TYPEC_FREQ_SHIFT 24 10982 #define DBI_TYPEC_FREQ_MASK (0xf << 24) 10983 #define DBI_TYPEC_OVERRIDE (1 << 8) 10984 #define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0 10985 #define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0) 10986 10987 10988 /* MIPI adapter registers */ 10989 10990 #define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104) 10991 #define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904) 10992 #define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL) 10993 #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */ 10994 #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5) 10995 #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5) 10996 #define ESCAPE_CLOCK_DIVIDER_2 (1 << 5) 10997 #define ESCAPE_CLOCK_DIVIDER_4 (2 << 5) 10998 #define READ_REQUEST_PRIORITY_SHIFT 3 10999 #define READ_REQUEST_PRIORITY_MASK (3 << 3) 11000 #define READ_REQUEST_PRIORITY_LOW (0 << 3) 11001 #define READ_REQUEST_PRIORITY_HIGH (3 << 3) 11002 #define RGB_FLIP_TO_BGR (1 << 2) 11003 11004 #define BXT_PIPE_SELECT_SHIFT 7 11005 #define BXT_PIPE_SELECT_MASK (7 << 7) 11006 #define BXT_PIPE_SELECT(pipe) ((pipe) << 7) 11007 #define GLK_PHY_STATUS_PORT_READY (1 << 31) /* RO */ 11008 #define GLK_ULPS_NOT_ACTIVE (1 << 30) /* RO */ 11009 #define GLK_MIPIIO_RESET_RELEASED (1 << 28) 11010 #define GLK_CLOCK_LANE_STOP_STATE (1 << 27) /* RO */ 11011 #define GLK_DATA_LANE_STOP_STATE (1 << 26) /* RO */ 11012 #define GLK_LP_WAKE (1 << 22) 11013 #define GLK_LP11_LOW_PWR_MODE (1 << 21) 11014 #define GLK_LP00_LOW_PWR_MODE (1 << 20) 11015 #define GLK_FIREWALL_ENABLE (1 << 16) 11016 #define BXT_PIXEL_OVERLAP_CNT_MASK (0xf << 10) 11017 #define BXT_PIXEL_OVERLAP_CNT_SHIFT 10 11018 #define BXT_DSC_ENABLE (1 << 3) 11019 #define BXT_RGB_FLIP (1 << 2) 11020 #define GLK_MIPIIO_PORT_POWERED (1 << 1) /* RO */ 11021 #define GLK_MIPIIO_ENABLE (1 << 0) 11022 11023 #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108) 11024 #define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908) 11025 #define MIPI_DATA_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS) 11026 #define DATA_MEM_ADDRESS_SHIFT 5 11027 #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5) 11028 #define DATA_VALID (1 << 0) 11029 11030 #define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c) 11031 #define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c) 11032 #define MIPI_DATA_LENGTH(port) _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH) 11033 #define DATA_LENGTH_SHIFT 0 11034 #define DATA_LENGTH_MASK (0xfffff << 0) 11035 11036 #define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110) 11037 #define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910) 11038 #define MIPI_COMMAND_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS) 11039 #define COMMAND_MEM_ADDRESS_SHIFT 5 11040 #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5) 11041 #define AUTO_PWG_ENABLE (1 << 2) 11042 #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1) 11043 #define COMMAND_VALID (1 << 0) 11044 11045 #define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114) 11046 #define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914) 11047 #define MIPI_COMMAND_LENGTH(port) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH) 11048 #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */ 11049 #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n))) 11050 11051 #define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118) 11052 #define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918) 11053 #define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */ 11054 11055 #define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138) 11056 #define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938) 11057 #define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID) 11058 #define READ_DATA_VALID(n) (1 << (n)) 11059 11060 /* MOCS (Memory Object Control State) registers */ 11061 #define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */ 11062 11063 #define GEN9_GFX_MOCS(i) _MMIO(0xc800 + (i) * 4) /* Graphics MOCS registers */ 11064 #define GEN9_MFX0_MOCS(i) _MMIO(0xc900 + (i) * 4) /* Media 0 MOCS registers */ 11065 #define GEN9_MFX1_MOCS(i) _MMIO(0xca00 + (i) * 4) /* Media 1 MOCS registers */ 11066 #define GEN9_VEBOX_MOCS(i) _MMIO(0xcb00 + (i) * 4) /* Video MOCS registers */ 11067 #define GEN9_BLT_MOCS(i) _MMIO(0xcc00 + (i) * 4) /* Blitter MOCS registers */ 11068 /* Media decoder 2 MOCS registers */ 11069 #define GEN11_MFX2_MOCS(i) _MMIO(0x10000 + (i) * 4) 11070 11071 #define GEN10_SCRATCH_LNCF2 _MMIO(0xb0a0) 11072 #define PMFLUSHDONE_LNICRSDROP (1 << 20) 11073 #define PMFLUSH_GAPL3UNBLOCK (1 << 21) 11074 #define PMFLUSHDONE_LNEBLK (1 << 22) 11075 11076 /* gamt regs */ 11077 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4) 11078 #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */ 11079 #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF /* max/min for LRA1/2 */ 11080 #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL 0x67F1427F /* " " */ 11081 #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT 0x5FF101FF /* " " */ 11082 11083 #define MMCD_MISC_CTRL _MMIO(0x4ddc) /* skl+ */ 11084 #define MMCD_PCLA (1 << 31) 11085 #define MMCD_HOTSPOT_EN (1 << 27) 11086 11087 #define _ICL_PHY_MISC_A 0x64C00 11088 #define _ICL_PHY_MISC_B 0x64C04 11089 #define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, \ 11090 _ICL_PHY_MISC_B) 11091 #define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23) 11092 11093 /* Icelake Display Stream Compression Registers */ 11094 #define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200) 11095 #define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00) 11096 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270 11097 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370 11098 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470 11099 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC 0x78570 11100 #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11101 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \ 11102 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC) 11103 #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11104 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \ 11105 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC) 11106 #define DSC_VBR_ENABLE (1 << 19) 11107 #define DSC_422_ENABLE (1 << 18) 11108 #define DSC_COLOR_SPACE_CONVERSION (1 << 17) 11109 #define DSC_BLOCK_PREDICTION (1 << 16) 11110 #define DSC_LINE_BUF_DEPTH_SHIFT 12 11111 #define DSC_BPC_SHIFT 8 11112 #define DSC_VER_MIN_SHIFT 4 11113 #define DSC_VER_MAJ (0x1 << 0) 11114 11115 #define DSCA_PICTURE_PARAMETER_SET_1 _MMIO(0x6B204) 11116 #define DSCC_PICTURE_PARAMETER_SET_1 _MMIO(0x6BA04) 11117 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB 0x78274 11118 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB 0x78374 11119 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC 0x78474 11120 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC 0x78574 11121 #define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11122 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \ 11123 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC) 11124 #define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11125 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \ 11126 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC) 11127 #define DSC_BPP(bpp) ((bpp) << 0) 11128 11129 #define DSCA_PICTURE_PARAMETER_SET_2 _MMIO(0x6B208) 11130 #define DSCC_PICTURE_PARAMETER_SET_2 _MMIO(0x6BA08) 11131 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB 0x78278 11132 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB 0x78378 11133 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC 0x78478 11134 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC 0x78578 11135 #define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11136 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \ 11137 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC) 11138 #define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11139 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \ 11140 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC) 11141 #define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16) 11142 #define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0) 11143 11144 #define DSCA_PICTURE_PARAMETER_SET_3 _MMIO(0x6B20C) 11145 #define DSCC_PICTURE_PARAMETER_SET_3 _MMIO(0x6BA0C) 11146 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB 0x7827C 11147 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB 0x7837C 11148 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC 0x7847C 11149 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC 0x7857C 11150 #define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11151 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \ 11152 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC) 11153 #define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11154 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \ 11155 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC) 11156 #define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16) 11157 #define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0) 11158 11159 #define DSCA_PICTURE_PARAMETER_SET_4 _MMIO(0x6B210) 11160 #define DSCC_PICTURE_PARAMETER_SET_4 _MMIO(0x6BA10) 11161 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB 0x78280 11162 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB 0x78380 11163 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC 0x78480 11164 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC 0x78580 11165 #define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11166 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \ 11167 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC) 11168 #define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11169 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \ 11170 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC) 11171 #define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16) 11172 #define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0) 11173 11174 #define DSCA_PICTURE_PARAMETER_SET_5 _MMIO(0x6B214) 11175 #define DSCC_PICTURE_PARAMETER_SET_5 _MMIO(0x6BA14) 11176 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB 0x78284 11177 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB 0x78384 11178 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC 0x78484 11179 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC 0x78584 11180 #define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11181 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \ 11182 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC) 11183 #define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11184 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \ 11185 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC) 11186 #define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16) 11187 #define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0) 11188 11189 #define DSCA_PICTURE_PARAMETER_SET_6 _MMIO(0x6B218) 11190 #define DSCC_PICTURE_PARAMETER_SET_6 _MMIO(0x6BA18) 11191 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB 0x78288 11192 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB 0x78388 11193 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC 0x78488 11194 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC 0x78588 11195 #define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11196 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \ 11197 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC) 11198 #define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11199 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \ 11200 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC) 11201 #define DSC_FLATNESS_MAX_QP(max_qp) ((max_qp) << 24) 11202 #define DSC_FLATNESS_MIN_QP(min_qp) ((min_qp) << 16) 11203 #define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8) 11204 #define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0) 11205 11206 #define DSCA_PICTURE_PARAMETER_SET_7 _MMIO(0x6B21C) 11207 #define DSCC_PICTURE_PARAMETER_SET_7 _MMIO(0x6BA1C) 11208 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB 0x7828C 11209 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB 0x7838C 11210 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC 0x7848C 11211 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC 0x7858C 11212 #define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11213 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \ 11214 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC) 11215 #define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11216 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \ 11217 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC) 11218 #define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16) 11219 #define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0) 11220 11221 #define DSCA_PICTURE_PARAMETER_SET_8 _MMIO(0x6B220) 11222 #define DSCC_PICTURE_PARAMETER_SET_8 _MMIO(0x6BA20) 11223 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB 0x78290 11224 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB 0x78390 11225 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC 0x78490 11226 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC 0x78590 11227 #define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11228 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \ 11229 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC) 11230 #define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11231 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \ 11232 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC) 11233 #define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16) 11234 #define DSC_FINAL_OFFSET(final_offset) ((final_offset) << 0) 11235 11236 #define DSCA_PICTURE_PARAMETER_SET_9 _MMIO(0x6B224) 11237 #define DSCC_PICTURE_PARAMETER_SET_9 _MMIO(0x6BA24) 11238 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB 0x78294 11239 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB 0x78394 11240 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC 0x78494 11241 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC 0x78594 11242 #define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11243 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \ 11244 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC) 11245 #define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11246 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \ 11247 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC) 11248 #define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16) 11249 #define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0) 11250 11251 #define DSCA_PICTURE_PARAMETER_SET_10 _MMIO(0x6B228) 11252 #define DSCC_PICTURE_PARAMETER_SET_10 _MMIO(0x6BA28) 11253 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298 11254 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398 11255 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498 11256 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC 0x78598 11257 #define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11258 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \ 11259 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC) 11260 #define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11261 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \ 11262 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC) 11263 #define DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low) ((rc_tgt_off_low) << 20) 11264 #define DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high) ((rc_tgt_off_high) << 16) 11265 #define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8) 11266 #define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0) 11267 11268 #define DSCA_PICTURE_PARAMETER_SET_11 _MMIO(0x6B22C) 11269 #define DSCC_PICTURE_PARAMETER_SET_11 _MMIO(0x6BA2C) 11270 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C 11271 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C 11272 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C 11273 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC 0x7859C 11274 #define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11275 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \ 11276 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC) 11277 #define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11278 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \ 11279 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC) 11280 11281 #define DSCA_PICTURE_PARAMETER_SET_12 _MMIO(0x6B260) 11282 #define DSCC_PICTURE_PARAMETER_SET_12 _MMIO(0x6BA60) 11283 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0 11284 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0 11285 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0 11286 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC 0x785A0 11287 #define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11288 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \ 11289 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC) 11290 #define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11291 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \ 11292 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC) 11293 11294 #define DSCA_PICTURE_PARAMETER_SET_13 _MMIO(0x6B264) 11295 #define DSCC_PICTURE_PARAMETER_SET_13 _MMIO(0x6BA64) 11296 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4 11297 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4 11298 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4 11299 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC 0x785A4 11300 #define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11301 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \ 11302 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC) 11303 #define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11304 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \ 11305 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC) 11306 11307 #define DSCA_PICTURE_PARAMETER_SET_14 _MMIO(0x6B268) 11308 #define DSCC_PICTURE_PARAMETER_SET_14 _MMIO(0x6BA68) 11309 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8 11310 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8 11311 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8 11312 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC 0x785A8 11313 #define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11314 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \ 11315 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC) 11316 #define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11317 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \ 11318 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC) 11319 11320 #define DSCA_PICTURE_PARAMETER_SET_15 _MMIO(0x6B26C) 11321 #define DSCC_PICTURE_PARAMETER_SET_15 _MMIO(0x6BA6C) 11322 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC 11323 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC 11324 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC 11325 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC 0x785AC 11326 #define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11327 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \ 11328 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC) 11329 #define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11330 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \ 11331 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC) 11332 11333 #define DSCA_PICTURE_PARAMETER_SET_16 _MMIO(0x6B270) 11334 #define DSCC_PICTURE_PARAMETER_SET_16 _MMIO(0x6BA70) 11335 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0 11336 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0 11337 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0 11338 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC 0x785B0 11339 #define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11340 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \ 11341 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC) 11342 #define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11343 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \ 11344 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC) 11345 #define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) ((slice_row_per_frame) << 20) 11346 #define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16) 11347 #define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0) 11348 11349 /* Icelake Rate Control Buffer Threshold Registers */ 11350 #define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230) 11351 #define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4) 11352 #define DSCC_RC_BUF_THRESH_0 _MMIO(0x6BA30) 11353 #define DSCC_RC_BUF_THRESH_0_UDW _MMIO(0x6BA30 + 4) 11354 #define _ICL_DSC0_RC_BUF_THRESH_0_PB (0x78254) 11355 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB (0x78254 + 4) 11356 #define _ICL_DSC1_RC_BUF_THRESH_0_PB (0x78354) 11357 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB (0x78354 + 4) 11358 #define _ICL_DSC0_RC_BUF_THRESH_0_PC (0x78454) 11359 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC (0x78454 + 4) 11360 #define _ICL_DSC1_RC_BUF_THRESH_0_PC (0x78554) 11361 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC (0x78554 + 4) 11362 #define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11363 _ICL_DSC0_RC_BUF_THRESH_0_PB, \ 11364 _ICL_DSC0_RC_BUF_THRESH_0_PC) 11365 #define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11366 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \ 11367 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC) 11368 #define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11369 _ICL_DSC1_RC_BUF_THRESH_0_PB, \ 11370 _ICL_DSC1_RC_BUF_THRESH_0_PC) 11371 #define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11372 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \ 11373 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC) 11374 11375 #define DSCA_RC_BUF_THRESH_1 _MMIO(0x6B238) 11376 #define DSCA_RC_BUF_THRESH_1_UDW _MMIO(0x6B238 + 4) 11377 #define DSCC_RC_BUF_THRESH_1 _MMIO(0x6BA38) 11378 #define DSCC_RC_BUF_THRESH_1_UDW _MMIO(0x6BA38 + 4) 11379 #define _ICL_DSC0_RC_BUF_THRESH_1_PB (0x7825C) 11380 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB (0x7825C + 4) 11381 #define _ICL_DSC1_RC_BUF_THRESH_1_PB (0x7835C) 11382 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB (0x7835C + 4) 11383 #define _ICL_DSC0_RC_BUF_THRESH_1_PC (0x7845C) 11384 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC (0x7845C + 4) 11385 #define _ICL_DSC1_RC_BUF_THRESH_1_PC (0x7855C) 11386 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC (0x7855C + 4) 11387 #define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11388 _ICL_DSC0_RC_BUF_THRESH_1_PB, \ 11389 _ICL_DSC0_RC_BUF_THRESH_1_PC) 11390 #define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11391 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \ 11392 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC) 11393 #define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11394 _ICL_DSC1_RC_BUF_THRESH_1_PB, \ 11395 _ICL_DSC1_RC_BUF_THRESH_1_PC) 11396 #define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11397 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \ 11398 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC) 11399 11400 #define PORT_TX_DFLEXDPSP _MMIO(FIA1_BASE + 0x008A0) 11401 #define TC_LIVE_STATE_TBT(tc_port) (1 << ((tc_port) * 8 + 6)) 11402 #define TC_LIVE_STATE_TC(tc_port) (1 << ((tc_port) * 8 + 5)) 11403 #define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8) 11404 #define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8)) 11405 #define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8)) 11406 11407 #define PORT_TX_DFLEXDPPMS _MMIO(FIA1_BASE + 0x00890) 11408 #define DP_PHY_MODE_STATUS_COMPLETED(tc_port) (1 << (tc_port)) 11409 11410 #define PORT_TX_DFLEXDPCSSS _MMIO(FIA1_BASE + 0x00894) 11411 #define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port)) 11412 11413 #endif /* _I915_REG_H_ */ 11414