1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 2 * All Rights Reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef _I915_REG_H_ 26 #define _I915_REG_H_ 27 28 #include "i915_reg_defs.h" 29 #include "display/intel_display_reg_defs.h" 30 31 /** 32 * DOC: The i915 register macro definition style guide 33 * 34 * Follow the style described here for new macros, and while changing existing 35 * macros. Do **not** mass change existing definitions just to update the style. 36 * 37 * File Layout 38 * ~~~~~~~~~~~ 39 * 40 * Keep helper macros near the top. For example, _PIPE() and friends. 41 * 42 * Prefix macros that generally should not be used outside of this file with 43 * underscore '_'. For example, _PIPE() and friends, single instances of 44 * registers that are defined solely for the use by function-like macros. 45 * 46 * Avoid using the underscore prefixed macros outside of this file. There are 47 * exceptions, but keep them to a minimum. 48 * 49 * There are two basic types of register definitions: Single registers and 50 * register groups. Register groups are registers which have two or more 51 * instances, for example one per pipe, port, transcoder, etc. Register groups 52 * should be defined using function-like macros. 53 * 54 * For single registers, define the register offset first, followed by register 55 * contents. 56 * 57 * For register groups, define the register instance offsets first, prefixed 58 * with underscore, followed by a function-like macro choosing the right 59 * instance based on the parameter, followed by register contents. 60 * 61 * Define the register contents (i.e. bit and bit field macros) from most 62 * significant to least significant bit. Indent the register content macros 63 * using two extra spaces between ``#define`` and the macro name. 64 * 65 * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents 66 * using ``REG_FIELD_PREP(mask, value)``. This will define the values already 67 * shifted in place, so they can be directly OR'd together. For convenience, 68 * function-like macros may be used to define bit fields, but do note that the 69 * macros may be needed to read as well as write the register contents. 70 * 71 * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name. 72 * 73 * Group the register and its contents together without blank lines, separate 74 * from other registers and their contents with one blank line. 75 * 76 * Indent macro values from macro names using TABs. Align values vertically. Use 77 * braces in macro values as needed to avoid unintended precedence after macro 78 * substitution. Use spaces in macro values according to kernel coding 79 * style. Use lower case in hexadecimal values. 80 * 81 * Naming 82 * ~~~~~~ 83 * 84 * Try to name registers according to the specs. If the register name changes in 85 * the specs from platform to another, stick to the original name. 86 * 87 * Try to re-use existing register macro definitions. Only add new macros for 88 * new register offsets, or when the register contents have changed enough to 89 * warrant a full redefinition. 90 * 91 * When a register macro changes for a new platform, prefix the new macro using 92 * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The 93 * prefix signifies the start platform/generation using the register. 94 * 95 * When a bit (field) macro changes or gets added for a new platform, while 96 * retaining the existing register macro, add a platform acronym or generation 97 * suffix to the name. For example, ``_SKL`` or ``_GEN8``. 98 * 99 * Examples 100 * ~~~~~~~~ 101 * 102 * (Note that the values in the example are indented using spaces instead of 103 * TABs to avoid misalignment in generated documentation. Use TABs in the 104 * definitions.):: 105 * 106 * #define _FOO_A 0xf000 107 * #define _FOO_B 0xf001 108 * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B) 109 * #define FOO_ENABLE REG_BIT(31) 110 * #define FOO_MODE_MASK REG_GENMASK(19, 16) 111 * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0) 112 * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1) 113 * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2) 114 * 115 * #define BAR _MMIO(0xb000) 116 * #define GEN8_BAR _MMIO(0xb888) 117 */ 118 119 #define GU_CNTL _MMIO(0x101010) 120 #define LMEM_INIT REG_BIT(7) 121 122 #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0) 123 #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20) 124 #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18) 125 #define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4) 126 #define GEN6_STOLEN_RESERVED_1M (0 << 4) 127 #define GEN6_STOLEN_RESERVED_512K (1 << 4) 128 #define GEN6_STOLEN_RESERVED_256K (2 << 4) 129 #define GEN6_STOLEN_RESERVED_128K (3 << 4) 130 #define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5) 131 #define GEN7_STOLEN_RESERVED_1M (0 << 5) 132 #define GEN7_STOLEN_RESERVED_256K (1 << 5) 133 #define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7) 134 #define GEN8_STOLEN_RESERVED_1M (0 << 7) 135 #define GEN8_STOLEN_RESERVED_2M (1 << 7) 136 #define GEN8_STOLEN_RESERVED_4M (2 << 7) 137 #define GEN8_STOLEN_RESERVED_8M (3 << 7) 138 #define GEN6_STOLEN_RESERVED_ENABLE (1 << 0) 139 #define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20) 140 141 #define _VGA_MSR_WRITE _MMIO(0x3c2) 142 143 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 144 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068 145 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL) 146 147 /* 148 * Reset registers 149 */ 150 #define DEBUG_RESET_I830 _MMIO(0x6070) 151 #define DEBUG_RESET_FULL (1 << 7) 152 #define DEBUG_RESET_RENDER (1 << 8) 153 #define DEBUG_RESET_DISPLAY (1 << 9) 154 155 /* 156 * IOSF sideband 157 */ 158 #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100) 159 #define IOSF_DEVFN_SHIFT 24 160 #define IOSF_OPCODE_SHIFT 16 161 #define IOSF_PORT_SHIFT 8 162 #define IOSF_BYTE_ENABLES_SHIFT 4 163 #define IOSF_BAR_SHIFT 1 164 #define IOSF_SB_BUSY (1 << 0) 165 #define IOSF_PORT_BUNIT 0x03 166 #define IOSF_PORT_PUNIT 0x04 167 #define IOSF_PORT_NC 0x11 168 #define IOSF_PORT_DPIO 0x12 169 #define IOSF_PORT_GPIO_NC 0x13 170 #define IOSF_PORT_CCK 0x14 171 #define IOSF_PORT_DPIO_2 0x1a 172 #define IOSF_PORT_FLISDSI 0x1b 173 #define IOSF_PORT_GPIO_SC 0x48 174 #define IOSF_PORT_GPIO_SUS 0xa8 175 #define IOSF_PORT_CCU 0xa9 176 #define CHV_IOSF_PORT_GPIO_N 0x13 177 #define CHV_IOSF_PORT_GPIO_SE 0x48 178 #define CHV_IOSF_PORT_GPIO_E 0xa8 179 #define CHV_IOSF_PORT_GPIO_SW 0xb2 180 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104) 181 #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108) 182 183 /* DPIO registers */ 184 #define DPIO_DEVFN 0 185 186 #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110) 187 #define DPIO_MODSEL1 (1 << 3) /* if ref clk b == 27 */ 188 #define DPIO_MODSEL0 (1 << 2) /* if ref clk a == 27 */ 189 #define DPIO_SFR_BYPASS (1 << 1) 190 #define DPIO_CMNRST (1 << 0) 191 192 #define DPIO_PHY(pipe) ((pipe) >> 1) 193 194 /* 195 * Per pipe/PLL DPIO regs 196 */ 197 #define _VLV_PLL_DW3_CH0 0x800c 198 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ 199 #define DPIO_POST_DIV_DAC 0 200 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ 201 #define DPIO_POST_DIV_LVDS1 2 202 #define DPIO_POST_DIV_LVDS2 3 203 #define DPIO_K_SHIFT (24) /* 4 bits */ 204 #define DPIO_P1_SHIFT (21) /* 3 bits */ 205 #define DPIO_P2_SHIFT (16) /* 5 bits */ 206 #define DPIO_N_SHIFT (12) /* 4 bits */ 207 #define DPIO_ENABLE_CALIBRATION (1 << 11) 208 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */ 209 #define DPIO_M2DIV_MASK 0xff 210 #define _VLV_PLL_DW3_CH1 0x802c 211 #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1) 212 213 #define _VLV_PLL_DW5_CH0 0x8014 214 #define DPIO_REFSEL_OVERRIDE 27 215 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ 216 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ 217 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ 218 #define DPIO_PLL_REFCLK_SEL_MASK 3 219 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ 220 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ 221 #define _VLV_PLL_DW5_CH1 0x8034 222 #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1) 223 224 #define _VLV_PLL_DW7_CH0 0x801c 225 #define _VLV_PLL_DW7_CH1 0x803c 226 #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1) 227 228 #define _VLV_PLL_DW8_CH0 0x8040 229 #define _VLV_PLL_DW8_CH1 0x8060 230 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1) 231 232 #define VLV_PLL_DW9_BCAST 0xc044 233 #define _VLV_PLL_DW9_CH0 0x8044 234 #define _VLV_PLL_DW9_CH1 0x8064 235 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1) 236 237 #define _VLV_PLL_DW10_CH0 0x8048 238 #define _VLV_PLL_DW10_CH1 0x8068 239 #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1) 240 241 #define _VLV_PLL_DW11_CH0 0x804c 242 #define _VLV_PLL_DW11_CH1 0x806c 243 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1) 244 245 /* Spec for ref block start counts at DW10 */ 246 #define VLV_REF_DW13 0x80ac 247 248 #define VLV_CMN_DW0 0x8100 249 250 /* 251 * Per DDI channel DPIO regs 252 */ 253 254 #define _VLV_PCS_DW0_CH0 0x8200 255 #define _VLV_PCS_DW0_CH1 0x8400 256 #define DPIO_PCS_TX_LANE2_RESET (1 << 16) 257 #define DPIO_PCS_TX_LANE1_RESET (1 << 7) 258 #define DPIO_LEFT_TXFIFO_RST_MASTER2 (1 << 4) 259 #define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3) 260 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1) 261 262 #define _VLV_PCS01_DW0_CH0 0x200 263 #define _VLV_PCS23_DW0_CH0 0x400 264 #define _VLV_PCS01_DW0_CH1 0x2600 265 #define _VLV_PCS23_DW0_CH1 0x2800 266 #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1) 267 #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1) 268 269 #define _VLV_PCS_DW1_CH0 0x8204 270 #define _VLV_PCS_DW1_CH1 0x8404 271 #define CHV_PCS_REQ_SOFTRESET_EN (1 << 23) 272 #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22) 273 #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21) 274 #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6) 275 #define DPIO_PCS_CLK_SOFT_RESET (1 << 5) 276 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1) 277 278 #define _VLV_PCS01_DW1_CH0 0x204 279 #define _VLV_PCS23_DW1_CH0 0x404 280 #define _VLV_PCS01_DW1_CH1 0x2604 281 #define _VLV_PCS23_DW1_CH1 0x2804 282 #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1) 283 #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1) 284 285 #define _VLV_PCS_DW8_CH0 0x8220 286 #define _VLV_PCS_DW8_CH1 0x8420 287 #define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20) 288 #define CHV_PCS_USEDCLKCHANNEL (1 << 21) 289 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1) 290 291 #define _VLV_PCS01_DW8_CH0 0x0220 292 #define _VLV_PCS23_DW8_CH0 0x0420 293 #define _VLV_PCS01_DW8_CH1 0x2620 294 #define _VLV_PCS23_DW8_CH1 0x2820 295 #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1) 296 #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1) 297 298 #define _VLV_PCS_DW9_CH0 0x8224 299 #define _VLV_PCS_DW9_CH1 0x8424 300 #define DPIO_PCS_TX2MARGIN_MASK (0x7 << 13) 301 #define DPIO_PCS_TX2MARGIN_000 (0 << 13) 302 #define DPIO_PCS_TX2MARGIN_101 (1 << 13) 303 #define DPIO_PCS_TX1MARGIN_MASK (0x7 << 10) 304 #define DPIO_PCS_TX1MARGIN_000 (0 << 10) 305 #define DPIO_PCS_TX1MARGIN_101 (1 << 10) 306 #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1) 307 308 #define _VLV_PCS01_DW9_CH0 0x224 309 #define _VLV_PCS23_DW9_CH0 0x424 310 #define _VLV_PCS01_DW9_CH1 0x2624 311 #define _VLV_PCS23_DW9_CH1 0x2824 312 #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1) 313 #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1) 314 315 #define _CHV_PCS_DW10_CH0 0x8228 316 #define _CHV_PCS_DW10_CH1 0x8428 317 #define DPIO_PCS_SWING_CALC_TX0_TX2 (1 << 30) 318 #define DPIO_PCS_SWING_CALC_TX1_TX3 (1 << 31) 319 #define DPIO_PCS_TX2DEEMP_MASK (0xf << 24) 320 #define DPIO_PCS_TX2DEEMP_9P5 (0 << 24) 321 #define DPIO_PCS_TX2DEEMP_6P0 (2 << 24) 322 #define DPIO_PCS_TX1DEEMP_MASK (0xf << 16) 323 #define DPIO_PCS_TX1DEEMP_9P5 (0 << 16) 324 #define DPIO_PCS_TX1DEEMP_6P0 (2 << 16) 325 #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1) 326 327 #define _VLV_PCS01_DW10_CH0 0x0228 328 #define _VLV_PCS23_DW10_CH0 0x0428 329 #define _VLV_PCS01_DW10_CH1 0x2628 330 #define _VLV_PCS23_DW10_CH1 0x2828 331 #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1) 332 #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1) 333 334 #define _VLV_PCS_DW11_CH0 0x822c 335 #define _VLV_PCS_DW11_CH1 0x842c 336 #define DPIO_TX2_STAGGER_MASK(x) ((x) << 24) 337 #define DPIO_LANEDESKEW_STRAP_OVRD (1 << 3) 338 #define DPIO_LEFT_TXFIFO_RST_MASTER (1 << 1) 339 #define DPIO_RIGHT_TXFIFO_RST_MASTER (1 << 0) 340 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1) 341 342 #define _VLV_PCS01_DW11_CH0 0x022c 343 #define _VLV_PCS23_DW11_CH0 0x042c 344 #define _VLV_PCS01_DW11_CH1 0x262c 345 #define _VLV_PCS23_DW11_CH1 0x282c 346 #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1) 347 #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1) 348 349 #define _VLV_PCS01_DW12_CH0 0x0230 350 #define _VLV_PCS23_DW12_CH0 0x0430 351 #define _VLV_PCS01_DW12_CH1 0x2630 352 #define _VLV_PCS23_DW12_CH1 0x2830 353 #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1) 354 #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1) 355 356 #define _VLV_PCS_DW12_CH0 0x8230 357 #define _VLV_PCS_DW12_CH1 0x8430 358 #define DPIO_TX2_STAGGER_MULT(x) ((x) << 20) 359 #define DPIO_TX1_STAGGER_MULT(x) ((x) << 16) 360 #define DPIO_TX1_STAGGER_MASK(x) ((x) << 8) 361 #define DPIO_LANESTAGGER_STRAP_OVRD (1 << 6) 362 #define DPIO_LANESTAGGER_STRAP(x) ((x) << 0) 363 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1) 364 365 #define _VLV_PCS_DW14_CH0 0x8238 366 #define _VLV_PCS_DW14_CH1 0x8438 367 #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1) 368 369 #define _VLV_PCS_DW23_CH0 0x825c 370 #define _VLV_PCS_DW23_CH1 0x845c 371 #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1) 372 373 #define _VLV_TX_DW2_CH0 0x8288 374 #define _VLV_TX_DW2_CH1 0x8488 375 #define DPIO_SWING_MARGIN000_SHIFT 16 376 #define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT) 377 #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8 378 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1) 379 380 #define _VLV_TX_DW3_CH0 0x828c 381 #define _VLV_TX_DW3_CH1 0x848c 382 /* The following bit for CHV phy */ 383 #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1 << 27) 384 #define DPIO_SWING_MARGIN101_SHIFT 16 385 #define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT) 386 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1) 387 388 #define _VLV_TX_DW4_CH0 0x8290 389 #define _VLV_TX_DW4_CH1 0x8490 390 #define DPIO_SWING_DEEMPH9P5_SHIFT 24 391 #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT) 392 #define DPIO_SWING_DEEMPH6P0_SHIFT 16 393 #define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT) 394 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1) 395 396 #define _VLV_TX3_DW4_CH0 0x690 397 #define _VLV_TX3_DW4_CH1 0x2a90 398 #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1) 399 400 #define _VLV_TX_DW5_CH0 0x8294 401 #define _VLV_TX_DW5_CH1 0x8494 402 #define DPIO_TX_OCALINIT_EN (1 << 31) 403 #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1) 404 405 #define _VLV_TX_DW11_CH0 0x82ac 406 #define _VLV_TX_DW11_CH1 0x84ac 407 #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1) 408 409 #define _VLV_TX_DW14_CH0 0x82b8 410 #define _VLV_TX_DW14_CH1 0x84b8 411 #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1) 412 413 /* CHV dpPhy registers */ 414 #define _CHV_PLL_DW0_CH0 0x8000 415 #define _CHV_PLL_DW0_CH1 0x8180 416 #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1) 417 418 #define _CHV_PLL_DW1_CH0 0x8004 419 #define _CHV_PLL_DW1_CH1 0x8184 420 #define DPIO_CHV_N_DIV_SHIFT 8 421 #define DPIO_CHV_M1_DIV_BY_2 (0 << 0) 422 #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1) 423 424 #define _CHV_PLL_DW2_CH0 0x8008 425 #define _CHV_PLL_DW2_CH1 0x8188 426 #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1) 427 428 #define _CHV_PLL_DW3_CH0 0x800c 429 #define _CHV_PLL_DW3_CH1 0x818c 430 #define DPIO_CHV_FRAC_DIV_EN (1 << 16) 431 #define DPIO_CHV_FIRST_MOD (0 << 8) 432 #define DPIO_CHV_SECOND_MOD (1 << 8) 433 #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0 434 #define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0) 435 #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1) 436 437 #define _CHV_PLL_DW6_CH0 0x8018 438 #define _CHV_PLL_DW6_CH1 0x8198 439 #define DPIO_CHV_GAIN_CTRL_SHIFT 16 440 #define DPIO_CHV_INT_COEFF_SHIFT 8 441 #define DPIO_CHV_PROP_COEFF_SHIFT 0 442 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1) 443 444 #define _CHV_PLL_DW8_CH0 0x8020 445 #define _CHV_PLL_DW8_CH1 0x81A0 446 #define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0 447 #define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0) 448 #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1) 449 450 #define _CHV_PLL_DW9_CH0 0x8024 451 #define _CHV_PLL_DW9_CH1 0x81A4 452 #define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */ 453 #define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1) 454 #define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */ 455 #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1) 456 457 #define _CHV_CMN_DW0_CH0 0x8100 458 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19 459 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18 460 #define DPIO_ALLDL_POWERDOWN (1 << 1) 461 #define DPIO_ANYDL_POWERDOWN (1 << 0) 462 463 #define _CHV_CMN_DW5_CH0 0x8114 464 #define CHV_BUFRIGHTENA1_DISABLE (0 << 20) 465 #define CHV_BUFRIGHTENA1_NORMAL (1 << 20) 466 #define CHV_BUFRIGHTENA1_FORCE (3 << 20) 467 #define CHV_BUFRIGHTENA1_MASK (3 << 20) 468 #define CHV_BUFLEFTENA1_DISABLE (0 << 22) 469 #define CHV_BUFLEFTENA1_NORMAL (1 << 22) 470 #define CHV_BUFLEFTENA1_FORCE (3 << 22) 471 #define CHV_BUFLEFTENA1_MASK (3 << 22) 472 473 #define _CHV_CMN_DW13_CH0 0x8134 474 #define _CHV_CMN_DW0_CH1 0x8080 475 #define DPIO_CHV_S1_DIV_SHIFT 21 476 #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */ 477 #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */ 478 #define DPIO_CHV_K_DIV_SHIFT 4 479 #define DPIO_PLL_FREQLOCK (1 << 1) 480 #define DPIO_PLL_LOCK (1 << 0) 481 #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1) 482 483 #define _CHV_CMN_DW14_CH0 0x8138 484 #define _CHV_CMN_DW1_CH1 0x8084 485 #define DPIO_AFC_RECAL (1 << 14) 486 #define DPIO_DCLKP_EN (1 << 13) 487 #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */ 488 #define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */ 489 #define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */ 490 #define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */ 491 #define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */ 492 #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */ 493 #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */ 494 #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */ 495 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1) 496 497 #define _CHV_CMN_DW19_CH0 0x814c 498 #define _CHV_CMN_DW6_CH1 0x8098 499 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */ 500 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */ 501 #define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */ 502 #define CHV_CMN_USEDCLKCHANNEL (1 << 13) 503 504 #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1) 505 506 #define CHV_CMN_DW28 0x8170 507 #define DPIO_CL1POWERDOWNEN (1 << 23) 508 #define DPIO_DYNPWRDOWNEN_CH0 (1 << 22) 509 #define DPIO_SUS_CLK_CONFIG_ON (0 << 0) 510 #define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0) 511 #define DPIO_SUS_CLK_CONFIG_GATE (2 << 0) 512 #define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0) 513 514 #define CHV_CMN_DW30 0x8178 515 #define DPIO_CL2_LDOFUSE_PWRENB (1 << 6) 516 #define DPIO_LRC_BYPASS (1 << 3) 517 518 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \ 519 (lane) * 0x200 + (offset)) 520 521 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80) 522 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84) 523 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88) 524 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c) 525 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90) 526 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94) 527 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98) 528 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c) 529 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0) 530 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4) 531 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8) 532 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac) 533 #define DPIO_FRC_LATENCY_SHFIT 8 534 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8) 535 #define DPIO_UPAR_SHIFT 30 536 537 /* BXT PHY registers */ 538 #define _BXT_PHY0_BASE 0x6C000 539 #define _BXT_PHY1_BASE 0x162000 540 #define _BXT_PHY2_BASE 0x163000 541 #define BXT_PHY_BASE(phy) _PHY3((phy), _BXT_PHY0_BASE, \ 542 _BXT_PHY1_BASE, \ 543 _BXT_PHY2_BASE) 544 545 #define _BXT_PHY(phy, reg) \ 546 _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg)) 547 548 #define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \ 549 (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \ 550 (reg_ch1) - _BXT_PHY0_BASE)) 551 #define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \ 552 _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1)) 553 554 #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090) 555 #define MIPIO_RST_CTRL (1 << 2) 556 557 #define _BXT_PHY_CTL_DDI_A 0x64C00 558 #define _BXT_PHY_CTL_DDI_B 0x64C10 559 #define _BXT_PHY_CTL_DDI_C 0x64C20 560 #define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10) 561 #define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9) 562 #define BXT_PHY_LANE_ENABLED (1 << 8) 563 #define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \ 564 _BXT_PHY_CTL_DDI_B) 565 566 #define _PHY_CTL_FAMILY_EDP 0x64C80 567 #define _PHY_CTL_FAMILY_DDI 0x64C90 568 #define _PHY_CTL_FAMILY_DDI_C 0x64CA0 569 #define COMMON_RESET_DIS (1 << 31) 570 #define BXT_PHY_CTL_FAMILY(phy) _MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \ 571 _PHY_CTL_FAMILY_EDP, \ 572 _PHY_CTL_FAMILY_DDI_C) 573 574 /* BXT PHY PLL registers */ 575 #define _PORT_PLL_A 0x46074 576 #define _PORT_PLL_B 0x46078 577 #define _PORT_PLL_C 0x4607c 578 #define PORT_PLL_ENABLE REG_BIT(31) 579 #define PORT_PLL_LOCK REG_BIT(30) 580 #define PORT_PLL_REF_SEL REG_BIT(27) 581 #define PORT_PLL_POWER_ENABLE REG_BIT(26) 582 #define PORT_PLL_POWER_STATE REG_BIT(25) 583 #define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B) 584 585 #define _PORT_PLL_EBB_0_A 0x162034 586 #define _PORT_PLL_EBB_0_B 0x6C034 587 #define _PORT_PLL_EBB_0_C 0x6C340 588 #define PORT_PLL_P1_MASK REG_GENMASK(15, 13) 589 #define PORT_PLL_P1(p1) REG_FIELD_PREP(PORT_PLL_P1_MASK, (p1)) 590 #define PORT_PLL_P2_MASK REG_GENMASK(12, 8) 591 #define PORT_PLL_P2(p2) REG_FIELD_PREP(PORT_PLL_P2_MASK, (p2)) 592 #define BXT_PORT_PLL_EBB_0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 593 _PORT_PLL_EBB_0_B, \ 594 _PORT_PLL_EBB_0_C) 595 596 #define _PORT_PLL_EBB_4_A 0x162038 597 #define _PORT_PLL_EBB_4_B 0x6C038 598 #define _PORT_PLL_EBB_4_C 0x6C344 599 #define PORT_PLL_RECALIBRATE REG_BIT(14) 600 #define PORT_PLL_10BIT_CLK_ENABLE REG_BIT(13) 601 #define BXT_PORT_PLL_EBB_4(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 602 _PORT_PLL_EBB_4_B, \ 603 _PORT_PLL_EBB_4_C) 604 605 #define _PORT_PLL_0_A 0x162100 606 #define _PORT_PLL_0_B 0x6C100 607 #define _PORT_PLL_0_C 0x6C380 608 /* PORT_PLL_0_A */ 609 #define PORT_PLL_M2_INT_MASK REG_GENMASK(7, 0) 610 #define PORT_PLL_M2_INT(m2_int) REG_FIELD_PREP(PORT_PLL_M2_INT_MASK, (m2_int)) 611 /* PORT_PLL_1_A */ 612 #define PORT_PLL_N_MASK REG_GENMASK(11, 8) 613 #define PORT_PLL_N(n) REG_FIELD_PREP(PORT_PLL_N_MASK, (n)) 614 /* PORT_PLL_2_A */ 615 #define PORT_PLL_M2_FRAC_MASK REG_GENMASK(21, 0) 616 #define PORT_PLL_M2_FRAC(m2_frac) REG_FIELD_PREP(PORT_PLL_M2_FRAC_MASK, (m2_frac)) 617 /* PORT_PLL_3_A */ 618 #define PORT_PLL_M2_FRAC_ENABLE REG_BIT(16) 619 /* PORT_PLL_6_A */ 620 #define PORT_PLL_GAIN_CTL_MASK REG_GENMASK(18, 16) 621 #define PORT_PLL_GAIN_CTL(x) REG_FIELD_PREP(PORT_PLL_GAIN_CTL_MASK, (x)) 622 #define PORT_PLL_INT_COEFF_MASK REG_GENMASK(12, 8) 623 #define PORT_PLL_INT_COEFF(x) REG_FIELD_PREP(PORT_PLL_INT_COEFF_MASK, (x)) 624 #define PORT_PLL_PROP_COEFF_MASK REG_GENMASK(3, 0) 625 #define PORT_PLL_PROP_COEFF(x) REG_FIELD_PREP(PORT_PLL_PROP_COEFF_MASK, (x)) 626 /* PORT_PLL_8_A */ 627 #define PORT_PLL_TARGET_CNT_MASK REG_GENMASK(9, 0) 628 #define PORT_PLL_TARGET_CNT(x) REG_FIELD_PREP(PORT_PLL_TARGET_CNT_MASK, (x)) 629 /* PORT_PLL_9_A */ 630 #define PORT_PLL_LOCK_THRESHOLD_MASK REG_GENMASK(3, 1) 631 #define PORT_PLL_LOCK_THRESHOLD(x) REG_FIELD_PREP(PORT_PLL_LOCK_THRESHOLD_MASK, (x)) 632 /* PORT_PLL_10_A */ 633 #define PORT_PLL_DCO_AMP_OVR_EN_H REG_BIT(27) 634 #define PORT_PLL_DCO_AMP_MASK REG_GENMASK(13, 10) 635 #define PORT_PLL_DCO_AMP(x) REG_FIELD_PREP(PORT_PLL_DCO_AMP_MASK, (x)) 636 #define _PORT_PLL_BASE(phy, ch) _BXT_PHY_CH(phy, ch, \ 637 _PORT_PLL_0_B, \ 638 _PORT_PLL_0_C) 639 #define BXT_PORT_PLL(phy, ch, idx) _MMIO(_PORT_PLL_BASE(phy, ch) + \ 640 (idx) * 4) 641 642 /* BXT PHY common lane registers */ 643 #define _PORT_CL1CM_DW0_A 0x162000 644 #define _PORT_CL1CM_DW0_BC 0x6C000 645 #define PHY_POWER_GOOD (1 << 16) 646 #define PHY_RESERVED (1 << 7) 647 #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC) 648 649 #define _PORT_CL1CM_DW9_A 0x162024 650 #define _PORT_CL1CM_DW9_BC 0x6C024 651 #define IREF0RC_OFFSET_SHIFT 8 652 #define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT) 653 #define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC) 654 655 #define _PORT_CL1CM_DW10_A 0x162028 656 #define _PORT_CL1CM_DW10_BC 0x6C028 657 #define IREF1RC_OFFSET_SHIFT 8 658 #define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT) 659 #define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC) 660 661 #define _PORT_CL1CM_DW28_A 0x162070 662 #define _PORT_CL1CM_DW28_BC 0x6C070 663 #define OCL1_POWER_DOWN_EN (1 << 23) 664 #define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22) 665 #define SUS_CLK_CONFIG 0x3 666 #define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC) 667 668 #define _PORT_CL1CM_DW30_A 0x162078 669 #define _PORT_CL1CM_DW30_BC 0x6C078 670 #define OCL2_LDOFUSE_PWR_DIS (1 << 6) 671 #define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC) 672 673 /* The spec defines this only for BXT PHY0, but lets assume that this 674 * would exist for PHY1 too if it had a second channel. 675 */ 676 #define _PORT_CL2CM_DW6_A 0x162358 677 #define _PORT_CL2CM_DW6_BC 0x6C358 678 #define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC) 679 #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28) 680 681 /* BXT PHY Ref registers */ 682 #define _PORT_REF_DW3_A 0x16218C 683 #define _PORT_REF_DW3_BC 0x6C18C 684 #define GRC_DONE (1 << 22) 685 #define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC) 686 687 #define _PORT_REF_DW6_A 0x162198 688 #define _PORT_REF_DW6_BC 0x6C198 689 #define GRC_CODE_SHIFT 24 690 #define GRC_CODE_MASK (0xFF << GRC_CODE_SHIFT) 691 #define GRC_CODE_FAST_SHIFT 16 692 #define GRC_CODE_FAST_MASK (0xFF << GRC_CODE_FAST_SHIFT) 693 #define GRC_CODE_SLOW_SHIFT 8 694 #define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT) 695 #define GRC_CODE_NOM_MASK 0xFF 696 #define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC) 697 698 #define _PORT_REF_DW8_A 0x1621A0 699 #define _PORT_REF_DW8_BC 0x6C1A0 700 #define GRC_DIS (1 << 15) 701 #define GRC_RDY_OVRD (1 << 1) 702 #define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC) 703 704 /* BXT PHY PCS registers */ 705 #define _PORT_PCS_DW10_LN01_A 0x162428 706 #define _PORT_PCS_DW10_LN01_B 0x6C428 707 #define _PORT_PCS_DW10_LN01_C 0x6C828 708 #define _PORT_PCS_DW10_GRP_A 0x162C28 709 #define _PORT_PCS_DW10_GRP_B 0x6CC28 710 #define _PORT_PCS_DW10_GRP_C 0x6CE28 711 #define BXT_PORT_PCS_DW10_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 712 _PORT_PCS_DW10_LN01_B, \ 713 _PORT_PCS_DW10_LN01_C) 714 #define BXT_PORT_PCS_DW10_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 715 _PORT_PCS_DW10_GRP_B, \ 716 _PORT_PCS_DW10_GRP_C) 717 718 #define TX2_SWING_CALC_INIT (1 << 31) 719 #define TX1_SWING_CALC_INIT (1 << 30) 720 721 #define _PORT_PCS_DW12_LN01_A 0x162430 722 #define _PORT_PCS_DW12_LN01_B 0x6C430 723 #define _PORT_PCS_DW12_LN01_C 0x6C830 724 #define _PORT_PCS_DW12_LN23_A 0x162630 725 #define _PORT_PCS_DW12_LN23_B 0x6C630 726 #define _PORT_PCS_DW12_LN23_C 0x6CA30 727 #define _PORT_PCS_DW12_GRP_A 0x162c30 728 #define _PORT_PCS_DW12_GRP_B 0x6CC30 729 #define _PORT_PCS_DW12_GRP_C 0x6CE30 730 #define LANESTAGGER_STRAP_OVRD (1 << 6) 731 #define LANE_STAGGER_MASK 0x1F 732 #define BXT_PORT_PCS_DW12_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 733 _PORT_PCS_DW12_LN01_B, \ 734 _PORT_PCS_DW12_LN01_C) 735 #define BXT_PORT_PCS_DW12_LN23(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 736 _PORT_PCS_DW12_LN23_B, \ 737 _PORT_PCS_DW12_LN23_C) 738 #define BXT_PORT_PCS_DW12_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 739 _PORT_PCS_DW12_GRP_B, \ 740 _PORT_PCS_DW12_GRP_C) 741 742 /* BXT PHY TX registers */ 743 #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \ 744 ((lane) & 1) * 0x80) 745 746 #define _PORT_TX_DW2_LN0_A 0x162508 747 #define _PORT_TX_DW2_LN0_B 0x6C508 748 #define _PORT_TX_DW2_LN0_C 0x6C908 749 #define _PORT_TX_DW2_GRP_A 0x162D08 750 #define _PORT_TX_DW2_GRP_B 0x6CD08 751 #define _PORT_TX_DW2_GRP_C 0x6CF08 752 #define BXT_PORT_TX_DW2_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 753 _PORT_TX_DW2_LN0_B, \ 754 _PORT_TX_DW2_LN0_C) 755 #define BXT_PORT_TX_DW2_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 756 _PORT_TX_DW2_GRP_B, \ 757 _PORT_TX_DW2_GRP_C) 758 #define MARGIN_000_SHIFT 16 759 #define MARGIN_000 (0xFF << MARGIN_000_SHIFT) 760 #define UNIQ_TRANS_SCALE_SHIFT 8 761 #define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT) 762 763 #define _PORT_TX_DW3_LN0_A 0x16250C 764 #define _PORT_TX_DW3_LN0_B 0x6C50C 765 #define _PORT_TX_DW3_LN0_C 0x6C90C 766 #define _PORT_TX_DW3_GRP_A 0x162D0C 767 #define _PORT_TX_DW3_GRP_B 0x6CD0C 768 #define _PORT_TX_DW3_GRP_C 0x6CF0C 769 #define BXT_PORT_TX_DW3_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 770 _PORT_TX_DW3_LN0_B, \ 771 _PORT_TX_DW3_LN0_C) 772 #define BXT_PORT_TX_DW3_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 773 _PORT_TX_DW3_GRP_B, \ 774 _PORT_TX_DW3_GRP_C) 775 #define SCALE_DCOMP_METHOD (1 << 26) 776 #define UNIQUE_TRANGE_EN_METHOD (1 << 27) 777 778 #define _PORT_TX_DW4_LN0_A 0x162510 779 #define _PORT_TX_DW4_LN0_B 0x6C510 780 #define _PORT_TX_DW4_LN0_C 0x6C910 781 #define _PORT_TX_DW4_GRP_A 0x162D10 782 #define _PORT_TX_DW4_GRP_B 0x6CD10 783 #define _PORT_TX_DW4_GRP_C 0x6CF10 784 #define BXT_PORT_TX_DW4_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 785 _PORT_TX_DW4_LN0_B, \ 786 _PORT_TX_DW4_LN0_C) 787 #define BXT_PORT_TX_DW4_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 788 _PORT_TX_DW4_GRP_B, \ 789 _PORT_TX_DW4_GRP_C) 790 #define DEEMPH_SHIFT 24 791 #define DE_EMPHASIS (0xFF << DEEMPH_SHIFT) 792 793 #define _PORT_TX_DW5_LN0_A 0x162514 794 #define _PORT_TX_DW5_LN0_B 0x6C514 795 #define _PORT_TX_DW5_LN0_C 0x6C914 796 #define _PORT_TX_DW5_GRP_A 0x162D14 797 #define _PORT_TX_DW5_GRP_B 0x6CD14 798 #define _PORT_TX_DW5_GRP_C 0x6CF14 799 #define BXT_PORT_TX_DW5_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 800 _PORT_TX_DW5_LN0_B, \ 801 _PORT_TX_DW5_LN0_C) 802 #define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 803 _PORT_TX_DW5_GRP_B, \ 804 _PORT_TX_DW5_GRP_C) 805 #define DCC_DELAY_RANGE_1 (1 << 9) 806 #define DCC_DELAY_RANGE_2 (1 << 8) 807 808 #define _PORT_TX_DW14_LN0_A 0x162538 809 #define _PORT_TX_DW14_LN0_B 0x6C538 810 #define _PORT_TX_DW14_LN0_C 0x6C938 811 #define LATENCY_OPTIM_SHIFT 30 812 #define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT) 813 #define BXT_PORT_TX_DW14_LN(phy, ch, lane) \ 814 _MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B, \ 815 _PORT_TX_DW14_LN0_C) + \ 816 _BXT_LANE_OFFSET(lane)) 817 818 /* UAIMI scratch pad register 1 */ 819 #define UAIMI_SPR1 _MMIO(0x4F074) 820 /* SKL VccIO mask */ 821 #define SKL_VCCIO_MASK 0x1 822 /* SKL balance leg register */ 823 #define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C) 824 /* I_boost values */ 825 #define BALANCE_LEG_SHIFT(port) (8 + 3 * (port)) 826 #define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port))) 827 /* Balance leg disable bits */ 828 #define BALANCE_LEG_DISABLE_SHIFT 23 829 #define BALANCE_LEG_DISABLE(port) (1 << (23 + (port))) 830 831 /* 832 * Fence registers 833 * [0-7] @ 0x2000 gen2,gen3 834 * [8-15] @ 0x3000 945,g33,pnv 835 * 836 * [0-15] @ 0x3000 gen4,gen5 837 * 838 * [0-15] @ 0x100000 gen6,vlv,chv 839 * [0-31] @ 0x100000 gen7+ 840 */ 841 #define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4) 842 #define I830_FENCE_START_MASK 0x07f80000 843 #define I830_FENCE_TILING_Y_SHIFT 12 844 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) 845 #define I830_FENCE_PITCH_SHIFT 4 846 #define I830_FENCE_REG_VALID (1 << 0) 847 #define I915_FENCE_MAX_PITCH_VAL 4 848 #define I830_FENCE_MAX_PITCH_VAL 6 849 #define I830_FENCE_MAX_SIZE_VAL (1 << 8) 850 851 #define I915_FENCE_START_MASK 0x0ff00000 852 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) 853 854 #define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8) 855 #define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4) 856 #define I965_FENCE_PITCH_SHIFT 2 857 #define I965_FENCE_TILING_Y_SHIFT 1 858 #define I965_FENCE_REG_VALID (1 << 0) 859 #define I965_FENCE_MAX_PITCH_VAL 0x0400 860 861 #define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8) 862 #define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4) 863 #define GEN6_FENCE_PITCH_SHIFT 32 864 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800 865 866 867 /* control register for cpu gtt access */ 868 #define TILECTL _MMIO(0x101000) 869 #define TILECTL_SWZCTL (1 << 0) 870 #define TILECTL_TLBPF (1 << 1) 871 #define TILECTL_TLB_PREFETCH_DIS (1 << 2) 872 #define TILECTL_BACKSNOOP_DIS (1 << 3) 873 874 /* 875 * Instruction and interrupt control regs 876 */ 877 #define PGTBL_CTL _MMIO(0x02020) 878 #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */ 879 #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */ 880 #define PGTBL_ER _MMIO(0x02024) 881 #define PRB0_BASE (0x2030 - 0x30) 882 #define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */ 883 #define PRB2_BASE (0x2050 - 0x30) /* gen3 */ 884 #define SRB0_BASE (0x2100 - 0x30) /* gen2 */ 885 #define SRB1_BASE (0x2110 - 0x30) /* gen2 */ 886 #define SRB2_BASE (0x2120 - 0x30) /* 830 */ 887 #define SRB3_BASE (0x2130 - 0x30) /* 830 */ 888 #define RENDER_RING_BASE 0x02000 889 #define BSD_RING_BASE 0x04000 890 #define GEN6_BSD_RING_BASE 0x12000 891 #define GEN8_BSD2_RING_BASE 0x1c000 892 #define GEN11_BSD_RING_BASE 0x1c0000 893 #define GEN11_BSD2_RING_BASE 0x1c4000 894 #define GEN11_BSD3_RING_BASE 0x1d0000 895 #define GEN11_BSD4_RING_BASE 0x1d4000 896 #define XEHP_BSD5_RING_BASE 0x1e0000 897 #define XEHP_BSD6_RING_BASE 0x1e4000 898 #define XEHP_BSD7_RING_BASE 0x1f0000 899 #define XEHP_BSD8_RING_BASE 0x1f4000 900 #define VEBOX_RING_BASE 0x1a000 901 #define GEN11_VEBOX_RING_BASE 0x1c8000 902 #define GEN11_VEBOX2_RING_BASE 0x1d8000 903 #define XEHP_VEBOX3_RING_BASE 0x1e8000 904 #define XEHP_VEBOX4_RING_BASE 0x1f8000 905 #define GEN12_COMPUTE0_RING_BASE 0x1a000 906 #define GEN12_COMPUTE1_RING_BASE 0x1c000 907 #define GEN12_COMPUTE2_RING_BASE 0x1e000 908 #define GEN12_COMPUTE3_RING_BASE 0x26000 909 #define BLT_RING_BASE 0x22000 910 #define XEHPC_BCS1_RING_BASE 0x3e0000 911 #define XEHPC_BCS2_RING_BASE 0x3e2000 912 #define XEHPC_BCS3_RING_BASE 0x3e4000 913 #define XEHPC_BCS4_RING_BASE 0x3e6000 914 #define XEHPC_BCS5_RING_BASE 0x3e8000 915 #define XEHPC_BCS6_RING_BASE 0x3ea000 916 #define XEHPC_BCS7_RING_BASE 0x3ec000 917 #define XEHPC_BCS8_RING_BASE 0x3ee000 918 #define DG1_GSC_HECI1_BASE 0x00258000 919 #define DG1_GSC_HECI2_BASE 0x00259000 920 #define DG2_GSC_HECI1_BASE 0x00373000 921 #define DG2_GSC_HECI2_BASE 0x00374000 922 923 924 925 #define HSW_GTT_CACHE_EN _MMIO(0x4024) 926 #define GTT_CACHE_EN_ALL 0xF0007FFF 927 #define GEN7_WR_WATERMARK _MMIO(0x4028) 928 #define GEN7_GFX_PRIO_CTRL _MMIO(0x402C) 929 #define ARB_MODE _MMIO(0x4030) 930 #define ARB_MODE_SWIZZLE_SNB (1 << 4) 931 #define ARB_MODE_SWIZZLE_IVB (1 << 5) 932 #define GEN7_GFX_PEND_TLB0 _MMIO(0x4034) 933 #define GEN7_GFX_PEND_TLB1 _MMIO(0x4038) 934 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */ 935 #define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4) 936 #define GEN7_LRA_LIMITS_REG_NUM 13 937 #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070) 938 #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074) 939 940 #define GEN7_ERR_INT _MMIO(0x44040) 941 #define ERR_INT_POISON (1 << 31) 942 #define ERR_INT_MMIO_UNCLAIMED (1 << 13) 943 #define ERR_INT_PIPE_CRC_DONE_C (1 << 8) 944 #define ERR_INT_FIFO_UNDERRUN_C (1 << 6) 945 #define ERR_INT_PIPE_CRC_DONE_B (1 << 5) 946 #define ERR_INT_FIFO_UNDERRUN_B (1 << 3) 947 #define ERR_INT_PIPE_CRC_DONE_A (1 << 2) 948 #define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3)) 949 #define ERR_INT_FIFO_UNDERRUN_A (1 << 0) 950 #define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) 951 952 #define FPGA_DBG _MMIO(0x42300) 953 #define FPGA_DBG_RM_NOCLAIM REG_BIT(31) 954 955 #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028) 956 #define CLAIM_ER_CLR REG_BIT(31) 957 #define CLAIM_ER_OVERFLOW REG_BIT(16) 958 #define CLAIM_ER_CTR_MASK REG_GENMASK(15, 0) 959 960 #define DERRMR _MMIO(0x44050) 961 /* Note that HBLANK events are reserved on bdw+ */ 962 #define DERRMR_PIPEA_SCANLINE (1 << 0) 963 #define DERRMR_PIPEA_PRI_FLIP_DONE (1 << 1) 964 #define DERRMR_PIPEA_SPR_FLIP_DONE (1 << 2) 965 #define DERRMR_PIPEA_VBLANK (1 << 3) 966 #define DERRMR_PIPEA_HBLANK (1 << 5) 967 #define DERRMR_PIPEB_SCANLINE (1 << 8) 968 #define DERRMR_PIPEB_PRI_FLIP_DONE (1 << 9) 969 #define DERRMR_PIPEB_SPR_FLIP_DONE (1 << 10) 970 #define DERRMR_PIPEB_VBLANK (1 << 11) 971 #define DERRMR_PIPEB_HBLANK (1 << 13) 972 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */ 973 #define DERRMR_PIPEC_SCANLINE (1 << 14) 974 #define DERRMR_PIPEC_PRI_FLIP_DONE (1 << 15) 975 #define DERRMR_PIPEC_SPR_FLIP_DONE (1 << 20) 976 #define DERRMR_PIPEC_VBLANK (1 << 21) 977 #define DERRMR_PIPEC_HBLANK (1 << 22) 978 979 #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030) 980 #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034) 981 #define SCPD0 _MMIO(0x209c) /* 915+ only */ 982 #define SCPD_FBC_IGNORE_3D (1 << 6) 983 #define CSTATE_RENDER_CLOCK_GATE_DISABLE (1 << 5) 984 #define GEN2_IER _MMIO(0x20a0) 985 #define GEN2_IIR _MMIO(0x20a4) 986 #define GEN2_IMR _MMIO(0x20a8) 987 #define GEN2_ISR _MMIO(0x20ac) 988 #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060) 989 #define GINT_DIS (1 << 22) 990 #define GCFG_DIS (1 << 8) 991 #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064) 992 #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084) 993 #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0) 994 #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4) 995 #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8) 996 #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac) 997 #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120) 998 #define VLV_PCBR_ADDR_SHIFT 12 999 1000 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */ 1001 #define EIR _MMIO(0x20b0) 1002 #define EMR _MMIO(0x20b4) 1003 #define ESR _MMIO(0x20b8) 1004 #define GM45_ERROR_PAGE_TABLE (1 << 5) 1005 #define GM45_ERROR_MEM_PRIV (1 << 4) 1006 #define I915_ERROR_PAGE_TABLE (1 << 4) 1007 #define GM45_ERROR_CP_PRIV (1 << 3) 1008 #define I915_ERROR_MEMORY_REFRESH (1 << 1) 1009 #define I915_ERROR_INSTRUCTION (1 << 0) 1010 #define INSTPM _MMIO(0x20c0) 1011 #define INSTPM_SELF_EN (1 << 12) /* 915GM only */ 1012 #define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts 1013 will not assert AGPBUSY# and will only 1014 be delivered when out of C3. */ 1015 #define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */ 1016 #define INSTPM_TLB_INVALIDATE (1 << 9) 1017 #define INSTPM_SYNC_FLUSH (1 << 5) 1018 #define MEM_MODE _MMIO(0x20cc) 1019 #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */ 1020 #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */ 1021 #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */ 1022 #define FW_BLC _MMIO(0x20d8) 1023 #define FW_BLC2 _MMIO(0x20dc) 1024 #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */ 1025 #define FW_BLC_SELF_EN_MASK (1 << 31) 1026 #define FW_BLC_SELF_FIFO_MASK (1 << 16) /* 945 only */ 1027 #define FW_BLC_SELF_EN (1 << 15) /* 945 only */ 1028 #define MM_BURST_LENGTH 0x00700000 1029 #define MM_FIFO_WATERMARK 0x0001F000 1030 #define LM_BURST_LENGTH 0x00000700 1031 #define LM_FIFO_WATERMARK 0x0000001F 1032 #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */ 1033 1034 #define _MBUS_ABOX0_CTL 0x45038 1035 #define _MBUS_ABOX1_CTL 0x45048 1036 #define _MBUS_ABOX2_CTL 0x4504C 1037 #define MBUS_ABOX_CTL(x) _MMIO(_PICK(x, _MBUS_ABOX0_CTL, \ 1038 _MBUS_ABOX1_CTL, \ 1039 _MBUS_ABOX2_CTL)) 1040 #define MBUS_ABOX_BW_CREDIT_MASK (3 << 20) 1041 #define MBUS_ABOX_BW_CREDIT(x) ((x) << 20) 1042 #define MBUS_ABOX_B_CREDIT_MASK (0xF << 16) 1043 #define MBUS_ABOX_B_CREDIT(x) ((x) << 16) 1044 #define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8) 1045 #define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8) 1046 #define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0) 1047 #define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0) 1048 1049 #define _PIPEA_MBUS_DBOX_CTL 0x7003C 1050 #define _PIPEB_MBUS_DBOX_CTL 0x7103C 1051 #define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \ 1052 _PIPEB_MBUS_DBOX_CTL) 1053 #define MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK REG_GENMASK(24, 20) /* tgl+ */ 1054 #define MBUS_DBOX_B2B_TRANSACTIONS_MAX(x) REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK, x) 1055 #define MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK REG_GENMASK(19, 17) /* tgl+ */ 1056 #define MBUS_DBOX_B2B_TRANSACTIONS_DELAY(x) REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK, x) 1057 #define MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN REG_BIT(16) /* tgl+ */ 1058 #define MBUS_DBOX_BW_CREDIT_MASK REG_GENMASK(15, 14) 1059 #define MBUS_DBOX_BW_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, x) 1060 #define MBUS_DBOX_BW_4CREDITS_MTL REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, 0x2) 1061 #define MBUS_DBOX_BW_8CREDITS_MTL REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, 0x3) 1062 #define MBUS_DBOX_B_CREDIT_MASK REG_GENMASK(12, 8) 1063 #define MBUS_DBOX_B_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_B_CREDIT_MASK, x) 1064 #define MBUS_DBOX_I_CREDIT_MASK REG_GENMASK(7, 5) 1065 #define MBUS_DBOX_I_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_I_CREDIT_MASK, x) 1066 #define MBUS_DBOX_A_CREDIT_MASK REG_GENMASK(3, 0) 1067 #define MBUS_DBOX_A_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_A_CREDIT_MASK, x) 1068 1069 #define MBUS_UBOX_CTL _MMIO(0x4503C) 1070 #define MBUS_BBOX_CTL_S1 _MMIO(0x45040) 1071 #define MBUS_BBOX_CTL_S2 _MMIO(0x45044) 1072 1073 #define MBUS_CTL _MMIO(0x4438C) 1074 #define MBUS_JOIN REG_BIT(31) 1075 #define MBUS_HASHING_MODE_MASK REG_BIT(30) 1076 #define MBUS_HASHING_MODE_2x2 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 0) 1077 #define MBUS_HASHING_MODE_1x4 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 1) 1078 #define MBUS_JOIN_PIPE_SELECT_MASK REG_GENMASK(28, 26) 1079 #define MBUS_JOIN_PIPE_SELECT(pipe) REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe) 1080 #define MBUS_JOIN_PIPE_SELECT_NONE MBUS_JOIN_PIPE_SELECT(7) 1081 1082 /* Make render/texture TLB fetches lower priorty than associated data 1083 * fetches. This is not turned on by default 1084 */ 1085 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) 1086 1087 /* Isoch request wait on GTT enable (Display A/B/C streams). 1088 * Make isoch requests stall on the TLB update. May cause 1089 * display underruns (test mode only) 1090 */ 1091 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14) 1092 1093 /* Block grant count for isoch requests when block count is 1094 * set to a finite value. 1095 */ 1096 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12) 1097 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ 1098 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ 1099 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ 1100 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ 1101 1102 /* Enable render writes to complete in C2/C3/C4 power states. 1103 * If this isn't enabled, render writes are prevented in low 1104 * power states. That seems bad to me. 1105 */ 1106 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) 1107 1108 /* This acknowledges an async flip immediately instead 1109 * of waiting for 2TLB fetches. 1110 */ 1111 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) 1112 1113 /* Enables non-sequential data reads through arbiter 1114 */ 1115 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) 1116 1117 /* Disable FSB snooping of cacheable write cycles from binner/render 1118 * command stream 1119 */ 1120 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) 1121 1122 /* Arbiter time slice for non-isoch streams */ 1123 #define MI_ARB_TIME_SLICE_MASK (7 << 5) 1124 #define MI_ARB_TIME_SLICE_1 (0 << 5) 1125 #define MI_ARB_TIME_SLICE_2 (1 << 5) 1126 #define MI_ARB_TIME_SLICE_4 (2 << 5) 1127 #define MI_ARB_TIME_SLICE_6 (3 << 5) 1128 #define MI_ARB_TIME_SLICE_8 (4 << 5) 1129 #define MI_ARB_TIME_SLICE_10 (5 << 5) 1130 #define MI_ARB_TIME_SLICE_14 (6 << 5) 1131 #define MI_ARB_TIME_SLICE_16 (7 << 5) 1132 1133 /* Low priority grace period page size */ 1134 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ 1135 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) 1136 1137 /* Disable display A/B trickle feed */ 1138 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) 1139 1140 /* Set display plane priority */ 1141 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ 1142 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ 1143 1144 #define MI_STATE _MMIO(0x20e4) /* gen2 only */ 1145 #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */ 1146 #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */ 1147 1148 /* On modern GEN architectures interrupt control consists of two sets 1149 * of registers. The first set pertains to the ring generating the 1150 * interrupt. The second control is for the functional block generating the 1151 * interrupt. These are PM, GT, DE, etc. 1152 * 1153 * Luckily *knocks on wood* all the ring interrupt bits match up with the 1154 * GT interrupt bits, so we don't need to duplicate the defines. 1155 * 1156 * These defines should cover us well from SNB->HSW with minor exceptions 1157 * it can also work on ILK. 1158 */ 1159 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) 1160 #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25) 1161 #define GT_BLT_USER_INTERRUPT (1 << 22) 1162 #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15) 1163 #define GT_BSD_USER_INTERRUPT (1 << 12) 1164 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */ 1165 #define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) /* bdw+ */ 1166 #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8) 1167 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */ 1168 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4) 1169 #define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3) 1170 #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2) 1171 #define GT_RENDER_DEBUG_INTERRUPT (1 << 1) 1172 #define GT_RENDER_USER_INTERRUPT (1 << 0) 1173 1174 #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */ 1175 #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */ 1176 1177 #define GT_PARITY_ERROR(dev_priv) \ 1178 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \ 1179 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0)) 1180 1181 /* These are all the "old" interrupts */ 1182 #define ILK_BSD_USER_INTERRUPT (1 << 5) 1183 1184 #define I915_PM_INTERRUPT (1 << 31) 1185 #define I915_ISP_INTERRUPT (1 << 22) 1186 #define I915_LPE_PIPE_B_INTERRUPT (1 << 21) 1187 #define I915_LPE_PIPE_A_INTERRUPT (1 << 20) 1188 #define I915_MIPIC_INTERRUPT (1 << 19) 1189 #define I915_MIPIA_INTERRUPT (1 << 18) 1190 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18) 1191 #define I915_DISPLAY_PORT_INTERRUPT (1 << 17) 1192 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16) 1193 #define I915_MASTER_ERROR_INTERRUPT (1 << 15) 1194 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14) 1195 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */ 1196 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13) 1197 #define I915_HWB_OOM_INTERRUPT (1 << 13) 1198 #define I915_LPE_PIPE_C_INTERRUPT (1 << 12) 1199 #define I915_SYNC_STATUS_INTERRUPT (1 << 12) 1200 #define I915_MISC_INTERRUPT (1 << 11) 1201 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11) 1202 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10) 1203 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10) 1204 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9) 1205 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9) 1206 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8) 1207 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8) 1208 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7) 1209 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6) 1210 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5) 1211 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4) 1212 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3) 1213 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2) 1214 #define I915_DEBUG_INTERRUPT (1 << 2) 1215 #define I915_WINVALID_INTERRUPT (1 << 1) 1216 #define I915_USER_INTERRUPT (1 << 1) 1217 #define I915_ASLE_INTERRUPT (1 << 0) 1218 #define I915_BSD_USER_INTERRUPT (1 << 25) 1219 1220 #define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000) 1221 #define I915_HDMI_LPE_AUDIO_SIZE 0x1000 1222 1223 /* DisplayPort Audio w/ LPE */ 1224 #define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38) 1225 #define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0) 1226 1227 #define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62F20) 1228 #define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62F30) 1229 #define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62F34) 1230 #define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \ 1231 _VLV_AUD_PORT_EN_B_DBG, \ 1232 _VLV_AUD_PORT_EN_C_DBG, \ 1233 _VLV_AUD_PORT_EN_D_DBG) 1234 #define VLV_AMP_MUTE (1 << 1) 1235 1236 #define GEN6_BSD_RNCID _MMIO(0x12198) 1237 1238 #define GEN7_FF_THREAD_MODE _MMIO(0x20a0) 1239 #define GEN7_FF_SCHED_MASK 0x0077070 1240 #define GEN8_FF_DS_REF_CNT_FFME (1 << 19) 1241 #define GEN12_FF_TESSELATION_DOP_GATE_DISABLE BIT(19) 1242 #define GEN7_FF_TS_SCHED_HS1 (0x5 << 16) 1243 #define GEN7_FF_TS_SCHED_HS0 (0x3 << 16) 1244 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16) 1245 #define GEN7_FF_TS_SCHED_HW (0x0 << 16) /* Default */ 1246 #define GEN7_FF_VS_REF_CNT_FFME (1 << 15) 1247 #define GEN7_FF_VS_SCHED_HS1 (0x5 << 12) 1248 #define GEN7_FF_VS_SCHED_HS0 (0x3 << 12) 1249 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12) /* Default */ 1250 #define GEN7_FF_VS_SCHED_HW (0x0 << 12) 1251 #define GEN7_FF_DS_SCHED_HS1 (0x5 << 4) 1252 #define GEN7_FF_DS_SCHED_HS0 (0x3 << 4) 1253 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */ 1254 #define GEN7_FF_DS_SCHED_HW (0x0 << 4) 1255 1256 /* 1257 * Framebuffer compression (915+ only) 1258 */ 1259 1260 #define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */ 1261 #define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */ 1262 #define FBC_CONTROL _MMIO(0x3208) 1263 #define FBC_CTL_EN REG_BIT(31) 1264 #define FBC_CTL_PERIODIC REG_BIT(30) 1265 #define FBC_CTL_INTERVAL_MASK REG_GENMASK(29, 16) 1266 #define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x)) 1267 #define FBC_CTL_STOP_ON_MOD REG_BIT(15) 1268 #define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */ 1269 #define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm only */ 1270 #define FBC_CTL_STRIDE_MASK REG_GENMASK(12, 5) 1271 #define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x)) 1272 #define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0) 1273 #define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x)) 1274 #define FBC_COMMAND _MMIO(0x320c) 1275 #define FBC_CMD_COMPRESS REG_BIT(0) 1276 #define FBC_STATUS _MMIO(0x3210) 1277 #define FBC_STAT_COMPRESSING REG_BIT(31) 1278 #define FBC_STAT_COMPRESSED REG_BIT(30) 1279 #define FBC_STAT_MODIFIED REG_BIT(29) 1280 #define FBC_STAT_CURRENT_LINE_MASK REG_GENMASK(10, 0) 1281 #define FBC_CONTROL2 _MMIO(0x3214) /* i965gm only */ 1282 #define FBC_CTL_FENCE_DBL REG_BIT(4) 1283 #define FBC_CTL_IDLE_MASK REG_GENMASK(3, 2) 1284 #define FBC_CTL_IDLE_IMM REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 0) 1285 #define FBC_CTL_IDLE_FULL REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 1) 1286 #define FBC_CTL_IDLE_LINE REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 2) 1287 #define FBC_CTL_IDLE_DEBUG REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 3) 1288 #define FBC_CTL_CPU_FENCE_EN REG_BIT(1) 1289 #define FBC_CTL_PLANE_MASK REG_GENMASK(1, 0) 1290 #define FBC_CTL_PLANE(i9xx_plane) REG_FIELD_PREP(FBC_CTL_PLANE_MASK, (i9xx_plane)) 1291 #define FBC_FENCE_OFF _MMIO(0x3218) /* i965gm only, BSpec typo has 321Bh */ 1292 #define FBC_MOD_NUM _MMIO(0x3220) /* i965gm only */ 1293 #define FBC_MOD_NUM_MASK REG_GENMASK(31, 1) 1294 #define FBC_MOD_NUM_VALID REG_BIT(0) 1295 #define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) /* 49 reisters */ 1296 #define FBC_TAG_MASK REG_GENMASK(1, 0) /* 16 tags per register */ 1297 #define FBC_TAG_MODIFIED REG_FIELD_PREP(FBC_TAG_MASK, 0) 1298 #define FBC_TAG_UNCOMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 1) 1299 #define FBC_TAG_UNCOMPRESSIBLE REG_FIELD_PREP(FBC_TAG_MASK, 2) 1300 #define FBC_TAG_COMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 3) 1301 1302 #define FBC_LL_SIZE (1536) 1303 1304 /* Framebuffer compression for GM45+ */ 1305 #define DPFC_CB_BASE _MMIO(0x3200) 1306 #define ILK_DPFC_CB_BASE(fbc_id) _MMIO_PIPE((fbc_id), 0x43200, 0x43240) 1307 #define DPFC_CONTROL _MMIO(0x3208) 1308 #define ILK_DPFC_CONTROL(fbc_id) _MMIO_PIPE((fbc_id), 0x43208, 0x43248) 1309 #define DPFC_CTL_EN REG_BIT(31) 1310 #define DPFC_CTL_PLANE_MASK_G4X REG_BIT(30) /* g4x-snb */ 1311 #define DPFC_CTL_PLANE_G4X(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane)) 1312 #define DPFC_CTL_FENCE_EN_G4X REG_BIT(29) /* g4x-snb */ 1313 #define DPFC_CTL_PLANE_MASK_IVB REG_GENMASK(30, 29) /* ivb only */ 1314 #define DPFC_CTL_PLANE_IVB(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_IVB, (i9xx_plane)) 1315 #define DPFC_CTL_FENCE_EN_IVB REG_BIT(28) /* ivb+ */ 1316 #define DPFC_CTL_PERSISTENT_MODE REG_BIT(25) /* g4x-snb */ 1317 #define DPFC_CTL_FALSE_COLOR REG_BIT(10) /* ivb+ */ 1318 #define DPFC_CTL_SR_EN REG_BIT(10) /* g4x only */ 1319 #define DPFC_CTL_SR_EXIT_DIS REG_BIT(9) /* g4x only */ 1320 #define DPFC_CTL_LIMIT_MASK REG_GENMASK(7, 6) 1321 #define DPFC_CTL_LIMIT_1X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 0) 1322 #define DPFC_CTL_LIMIT_2X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 1) 1323 #define DPFC_CTL_LIMIT_4X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 2) 1324 #define DPFC_CTL_FENCENO_MASK REG_GENMASK(3, 0) 1325 #define DPFC_CTL_FENCENO(fence) REG_FIELD_PREP(DPFC_CTL_FENCENO_MASK, (fence)) 1326 #define DPFC_RECOMP_CTL _MMIO(0x320c) 1327 #define ILK_DPFC_RECOMP_CTL(fbc_id) _MMIO_PIPE((fbc_id), 0x4320c, 0x4324c) 1328 #define DPFC_RECOMP_STALL_EN REG_BIT(27) 1329 #define DPFC_RECOMP_STALL_WM_MASK REG_GENMASK(26, 16) 1330 #define DPFC_RECOMP_TIMER_COUNT_MASK REG_GENMASK(5, 0) 1331 #define DPFC_STATUS _MMIO(0x3210) 1332 #define ILK_DPFC_STATUS(fbc_id) _MMIO_PIPE((fbc_id), 0x43210, 0x43250) 1333 #define DPFC_INVAL_SEG_MASK REG_GENMASK(26, 16) 1334 #define DPFC_COMP_SEG_MASK REG_GENMASK(10, 0) 1335 #define DPFC_STATUS2 _MMIO(0x3214) 1336 #define ILK_DPFC_STATUS2(fbc_id) _MMIO_PIPE((fbc_id), 0x43214, 0x43254) 1337 #define DPFC_COMP_SEG_MASK_IVB REG_GENMASK(11, 0) 1338 #define DPFC_FENCE_YOFF _MMIO(0x3218) 1339 #define ILK_DPFC_FENCE_YOFF(fbc_id) _MMIO_PIPE((fbc_id), 0x43218, 0x43258) 1340 #define DPFC_CHICKEN _MMIO(0x3224) 1341 #define ILK_DPFC_CHICKEN(fbc_id) _MMIO_PIPE((fbc_id), 0x43224, 0x43264) 1342 #define DPFC_HT_MODIFY REG_BIT(31) /* pre-ivb */ 1343 #define DPFC_NUKE_ON_ANY_MODIFICATION REG_BIT(23) /* bdw+ */ 1344 #define DPFC_CHICKEN_COMP_DUMMY_PIXEL REG_BIT(14) /* glk+ */ 1345 #define DPFC_CHICKEN_FORCE_SLB_INVALIDATION REG_BIT(13) /* icl+ */ 1346 #define DPFC_DISABLE_DUMMY0 REG_BIT(8) /* ivb+ */ 1347 1348 #define GLK_FBC_STRIDE(fbc_id) _MMIO_PIPE((fbc_id), 0x43228, 0x43268) 1349 #define FBC_STRIDE_OVERRIDE REG_BIT(15) 1350 #define FBC_STRIDE_MASK REG_GENMASK(14, 0) 1351 #define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x)) 1352 1353 #define ILK_FBC_RT_BASE _MMIO(0x2128) 1354 #define ILK_FBC_RT_VALID REG_BIT(0) 1355 #define SNB_FBC_FRONT_BUFFER REG_BIT(1) 1356 1357 #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000) 1358 #define ILK_FBCQ_DIS (1 << 22) 1359 #define ILK_PABSTRETCH_DIS REG_BIT(21) 1360 #define ILK_SABSTRETCH_DIS REG_BIT(20) 1361 #define IVB_PRI_STRETCH_MAX_MASK REG_GENMASK(21, 20) 1362 #define IVB_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0) 1363 #define IVB_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1) 1364 #define IVB_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 2) 1365 #define IVB_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 3) 1366 #define IVB_SPR_STRETCH_MAX_MASK REG_GENMASK(19, 18) 1367 #define IVB_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0) 1368 #define IVB_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 1) 1369 #define IVB_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2) 1370 #define IVB_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3) 1371 1372 1373 /* 1374 * Framebuffer compression for Sandybridge 1375 * 1376 * The following two registers are of type GTTMMADR 1377 */ 1378 #define SNB_DPFC_CTL_SA _MMIO(0x100100) 1379 #define SNB_DPFC_FENCE_EN REG_BIT(29) 1380 #define SNB_DPFC_FENCENO_MASK REG_GENMASK(4, 0) 1381 #define SNB_DPFC_FENCENO(fence) REG_FIELD_PREP(SNB_DPFC_FENCENO_MASK, (fence)) 1382 #define SNB_DPFC_CPU_FENCE_OFFSET _MMIO(0x100104) 1383 1384 /* Framebuffer compression for Ivybridge */ 1385 #define IVB_FBC_RT_BASE _MMIO(0x7020) 1386 #define IVB_FBC_RT_BASE_UPPER _MMIO(0x7024) 1387 1388 #define IPS_CTL _MMIO(0x43408) 1389 #define IPS_ENABLE (1 << 31) 1390 1391 #define MSG_FBC_REND_STATE(fbc_id) _MMIO_PIPE((fbc_id), 0x50380, 0x50384) 1392 #define FBC_REND_NUKE REG_BIT(2) 1393 #define FBC_REND_CACHE_CLEAN REG_BIT(1) 1394 1395 /* 1396 * Clock control & power management 1397 */ 1398 #define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014) 1399 #define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018) 1400 #define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030) 1401 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) 1402 1403 #define VGA0 _MMIO(0x6000) 1404 #define VGA1 _MMIO(0x6004) 1405 #define VGA_PD _MMIO(0x6010) 1406 #define VGA0_PD_P2_DIV_4 (1 << 7) 1407 #define VGA0_PD_P1_DIV_2 (1 << 5) 1408 #define VGA0_PD_P1_SHIFT 0 1409 #define VGA0_PD_P1_MASK (0x1f << 0) 1410 #define VGA1_PD_P2_DIV_4 (1 << 15) 1411 #define VGA1_PD_P1_DIV_2 (1 << 13) 1412 #define VGA1_PD_P1_SHIFT 8 1413 #define VGA1_PD_P1_MASK (0x1f << 8) 1414 #define DPLL_VCO_ENABLE (1 << 31) 1415 #define DPLL_SDVO_HIGH_SPEED (1 << 30) 1416 #define DPLL_DVO_2X_MODE (1 << 30) 1417 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) 1418 #define DPLL_SYNCLOCK_ENABLE (1 << 29) 1419 #define DPLL_REF_CLK_ENABLE_VLV (1 << 29) 1420 #define DPLL_VGA_MODE_DIS (1 << 28) 1421 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 1422 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 1423 #define DPLL_MODE_MASK (3 << 26) 1424 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 1425 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 1426 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 1427 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 1428 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 1429 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 1430 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ 1431 #define DPLL_LOCK_VLV (1 << 15) 1432 #define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14) 1433 #define DPLL_INTEGRATED_REF_CLK_VLV (1 << 13) 1434 #define DPLL_SSC_REF_CLK_CHV (1 << 13) 1435 #define DPLL_PORTC_READY_MASK (0xf << 4) 1436 #define DPLL_PORTB_READY_MASK (0xf) 1437 1438 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 1439 1440 /* Additional CHV pll/phy registers */ 1441 #define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240) 1442 #define DPLL_PORTD_READY_MASK (0xf) 1443 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100) 1444 #define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2 * (phy) + (ch) + 27)) 1445 #define PHY_LDO_DELAY_0NS 0x0 1446 #define PHY_LDO_DELAY_200NS 0x1 1447 #define PHY_LDO_DELAY_600NS 0x2 1448 #define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2 * (phy) + 23)) 1449 #define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11)) 1450 #define PHY_CH_SU_PSR 0x1 1451 #define PHY_CH_DEEP_PSR 0x7 1452 #define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6 * (phy) + 3 * (ch) + 2)) 1453 #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy)) 1454 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104) 1455 #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30)) 1456 #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch)))) 1457 #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline)))) 1458 1459 /* 1460 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 1461 * this field (only one bit may be set). 1462 */ 1463 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 1464 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 1465 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 1466 /* i830, required in DVO non-gang */ 1467 #define PLL_P2_DIVIDE_BY_4 (1 << 23) 1468 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 1469 #define PLL_REF_INPUT_DREFCLK (0 << 13) 1470 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 1471 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 1472 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 1473 #define PLL_REF_INPUT_MASK (3 << 13) 1474 #define PLL_LOAD_PULSE_PHASE_SHIFT 9 1475 /* Ironlake */ 1476 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 1477 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) 1478 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9) 1479 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 1480 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff 1481 1482 /* 1483 * Parallel to Serial Load Pulse phase selection. 1484 * Selects the phase for the 10X DPLL clock for the PCIe 1485 * digital display port. The range is 4 to 13; 10 or more 1486 * is just a flip delay. The default is 6 1487 */ 1488 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 1489 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 1490 /* 1491 * SDVO multiplier for 945G/GM. Not used on 965. 1492 */ 1493 #define SDVO_MULTIPLIER_MASK 0x000000ff 1494 #define SDVO_MULTIPLIER_SHIFT_HIRES 4 1495 #define SDVO_MULTIPLIER_SHIFT_VGA 0 1496 1497 #define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c) 1498 #define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020) 1499 #define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c) 1500 #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD) 1501 1502 /* 1503 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 1504 * 1505 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 1506 */ 1507 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 1508 #define DPLL_MD_UDI_DIVIDER_SHIFT 24 1509 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 1510 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 1511 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 1512 /* 1513 * SDVO/UDI pixel multiplier. 1514 * 1515 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 1516 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 1517 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 1518 * dummy bytes in the datastream at an increased clock rate, with both sides of 1519 * the link knowing how many bytes are fill. 1520 * 1521 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 1522 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 1523 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 1524 * through an SDVO command. 1525 * 1526 * This register field has values of multiplication factor minus 1, with 1527 * a maximum multiplier of 5 for SDVO. 1528 */ 1529 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 1530 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 1531 /* 1532 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 1533 * This best be set to the default value (3) or the CRT won't work. No, 1534 * I don't entirely understand what this does... 1535 */ 1536 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 1537 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 1538 1539 #define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024) 1540 1541 #define _FPA0 0x6040 1542 #define _FPA1 0x6044 1543 #define _FPB0 0x6048 1544 #define _FPB1 0x604c 1545 #define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0) 1546 #define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1) 1547 #define FP_N_DIV_MASK 0x003f0000 1548 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 1549 #define FP_N_DIV_SHIFT 16 1550 #define FP_M1_DIV_MASK 0x00003f00 1551 #define FP_M1_DIV_SHIFT 8 1552 #define FP_M2_DIV_MASK 0x0000003f 1553 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff 1554 #define FP_M2_DIV_SHIFT 0 1555 #define DPLL_TEST _MMIO(0x606c) 1556 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 1557 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 1558 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 1559 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 1560 #define DPLLB_TEST_N_BYPASS (1 << 19) 1561 #define DPLLB_TEST_M_BYPASS (1 << 18) 1562 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 1563 #define DPLLA_TEST_N_BYPASS (1 << 3) 1564 #define DPLLA_TEST_M_BYPASS (1 << 2) 1565 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 1566 #define D_STATE _MMIO(0x6104) 1567 #define DSTATE_GFX_RESET_I830 (1 << 6) 1568 #define DSTATE_PLL_D3_OFF (1 << 3) 1569 #define DSTATE_GFX_CLOCK_GATING (1 << 1) 1570 #define DSTATE_DOT_CLOCK_GATING (1 << 0) 1571 #define DSPCLK_GATE_D(__i915) _MMIO(DISPLAY_MMIO_BASE(__i915) + 0x6200) 1572 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ 1573 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ 1574 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ 1575 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ 1576 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ 1577 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ 1578 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ 1579 # define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */ 1580 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ 1581 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ 1582 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ 1583 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ 1584 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ 1585 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ 1586 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ 1587 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ 1588 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ 1589 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ 1590 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ 1591 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ 1592 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) 1593 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) 1594 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) 1595 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) 1596 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ 1597 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ 1598 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ 1599 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) 1600 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) 1601 /* 1602 * This bit must be set on the 830 to prevent hangs when turning off the 1603 * overlay scaler. 1604 */ 1605 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) 1606 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) 1607 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) 1608 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ 1609 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ 1610 1611 #define RENCLK_GATE_D1 _MMIO(0x6204) 1612 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ 1613 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ 1614 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) 1615 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) 1616 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) 1617 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) 1618 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) 1619 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) 1620 # define MAG_CLOCK_GATE_DISABLE (1 << 5) 1621 /* This bit must be unset on 855,865 */ 1622 # define MECI_CLOCK_GATE_DISABLE (1 << 4) 1623 # define DCMP_CLOCK_GATE_DISABLE (1 << 3) 1624 # define MEC_CLOCK_GATE_DISABLE (1 << 2) 1625 # define MECO_CLOCK_GATE_DISABLE (1 << 1) 1626 /* This bit must be set on 855,865. */ 1627 # define SV_CLOCK_GATE_DISABLE (1 << 0) 1628 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) 1629 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) 1630 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) 1631 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) 1632 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) 1633 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) 1634 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) 1635 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) 1636 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) 1637 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) 1638 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) 1639 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) 1640 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) 1641 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) 1642 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) 1643 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) 1644 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) 1645 1646 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) 1647 /* This bit must always be set on 965G/965GM */ 1648 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) 1649 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) 1650 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) 1651 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) 1652 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) 1653 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) 1654 /* This bit must always be set on 965G */ 1655 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) 1656 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) 1657 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) 1658 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) 1659 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) 1660 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) 1661 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) 1662 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) 1663 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) 1664 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) 1665 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) 1666 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) 1667 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) 1668 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) 1669 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) 1670 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) 1671 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) 1672 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) 1673 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) 1674 1675 #define RENCLK_GATE_D2 _MMIO(0x6208) 1676 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) 1677 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) 1678 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) 1679 1680 #define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */ 1681 #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4) 1682 1683 #define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */ 1684 #define DEUC _MMIO(0x6214) /* CRL only */ 1685 1686 #define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500) 1687 #define FW_CSPWRDWNEN (1 << 15) 1688 1689 #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504) 1690 1691 #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508) 1692 #define CDCLK_FREQ_SHIFT 4 1693 #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT) 1694 #define CZCLK_FREQ_MASK 0xf 1695 1696 #define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C) 1697 #define PFI_CREDIT_63 (9 << 28) /* chv only */ 1698 #define PFI_CREDIT_31 (8 << 28) /* chv only */ 1699 #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */ 1700 #define PFI_CREDIT_RESEND (1 << 27) 1701 #define VGA_FAST_MODE_DISABLE (1 << 14) 1702 1703 #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510) 1704 1705 /* 1706 * Palette regs 1707 */ 1708 #define _PALETTE_A 0xa000 1709 #define _PALETTE_B 0xa800 1710 #define _CHV_PALETTE_C 0xc000 1711 /* 8bit mode / i965+ 10.6 interpolated mode ldw/udw */ 1712 #define PALETTE_RED_MASK REG_GENMASK(23, 16) 1713 #define PALETTE_GREEN_MASK REG_GENMASK(15, 8) 1714 #define PALETTE_BLUE_MASK REG_GENMASK(7, 0) 1715 /* pre-i965 10bit interpolated mode ldw */ 1716 #define PALETTE_10BIT_RED_LDW_MASK REG_GENMASK(23, 16) 1717 #define PALETTE_10BIT_GREEN_LDW_MASK REG_GENMASK(15, 8) 1718 #define PALETTE_10BIT_BLUE_LDW_MASK REG_GENMASK(7, 0) 1719 /* pre-i965 10bit interpolated mode udw */ 1720 #define PALETTE_10BIT_RED_EXP_MASK REG_GENMASK(23, 22) 1721 #define PALETTE_10BIT_RED_MANT_MASK REG_GENMASK(21, 18) 1722 #define PALETTE_10BIT_RED_UDW_MASK REG_GENMASK(17, 16) 1723 #define PALETTE_10BIT_GREEN_EXP_MASK REG_GENMASK(15, 14) 1724 #define PALETTE_10BIT_GREEN_MANT_MASK REG_GENMASK(13, 10) 1725 #define PALETTE_10BIT_GREEN_UDW_MASK REG_GENMASK(9, 8) 1726 #define PALETTE_10BIT_BLUE_EXP_MASK REG_GENMASK(7, 6) 1727 #define PALETTE_10BIT_BLUE_MANT_MASK REG_GENMASK(5, 2) 1728 #define PALETTE_10BIT_BLUE_UDW_MASK REG_GENMASK(1, 0) 1729 #define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \ 1730 _PICK((pipe), _PALETTE_A, \ 1731 _PALETTE_B, _CHV_PALETTE_C) + \ 1732 (i) * 4) 1733 1734 #define PEG_BAND_GAP_DATA _MMIO(0x14d68) 1735 1736 #define BXT_RP_STATE_CAP _MMIO(0x138170) 1737 #define GEN9_RP_STATE_LIMITS _MMIO(0x138148) 1738 #define XEHPSDV_RP_STATE_CAP _MMIO(0x250014) 1739 #define PVC_RP_STATE_CAP _MMIO(0x281014) 1740 1741 #define MTL_RP_STATE_CAP _MMIO(0x138000) 1742 #define MTL_MEDIAP_STATE_CAP _MMIO(0x138020) 1743 #define MTL_RP0_CAP_MASK REG_GENMASK(8, 0) 1744 #define MTL_RPN_CAP_MASK REG_GENMASK(24, 16) 1745 1746 #define MTL_GT_RPE_FREQUENCY _MMIO(0x13800c) 1747 #define MTL_MPE_FREQUENCY _MMIO(0x13802c) 1748 #define MTL_RPE_MASK REG_GENMASK(8, 0) 1749 1750 #define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8) 1751 #define GT0_PERF_LIMIT_REASONS_MASK 0xde3 1752 #define PROCHOT_MASK REG_BIT(0) 1753 #define THERMAL_LIMIT_MASK REG_BIT(1) 1754 #define RATL_MASK REG_BIT(5) 1755 #define VR_THERMALERT_MASK REG_BIT(6) 1756 #define VR_TDC_MASK REG_BIT(7) 1757 #define POWER_LIMIT_4_MASK REG_BIT(8) 1758 #define POWER_LIMIT_1_MASK REG_BIT(10) 1759 #define POWER_LIMIT_2_MASK REG_BIT(11) 1760 #define GT0_PERF_LIMIT_REASONS_LOG_MASK REG_GENMASK(31, 16) 1761 #define MTL_MEDIA_PERF_LIMIT_REASONS _MMIO(0x138030) 1762 1763 #define CHV_CLK_CTL1 _MMIO(0x101100) 1764 #define VLV_CLK_CTL2 _MMIO(0x101104) 1765 #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28 1766 1767 /* 1768 * Overlay regs 1769 */ 1770 1771 #define OVADD _MMIO(0x30000) 1772 #define DOVSTA _MMIO(0x30008) 1773 #define OC_BUF (0x3 << 20) 1774 #define OGAMC5 _MMIO(0x30010) 1775 #define OGAMC4 _MMIO(0x30014) 1776 #define OGAMC3 _MMIO(0x30018) 1777 #define OGAMC2 _MMIO(0x3001c) 1778 #define OGAMC1 _MMIO(0x30020) 1779 #define OGAMC0 _MMIO(0x30024) 1780 1781 /* 1782 * GEN9 clock gating regs 1783 */ 1784 #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530) 1785 #define DARBF_GATING_DIS (1 << 27) 1786 #define PWM2_GATING_DIS (1 << 14) 1787 #define PWM1_GATING_DIS (1 << 13) 1788 1789 #define GEN9_CLKGATE_DIS_3 _MMIO(0x46538) 1790 #define TGL_VRH_GATING_DIS REG_BIT(31) 1791 #define DPT_GATING_DIS REG_BIT(22) 1792 1793 #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C) 1794 #define BXT_GMBUS_GATING_DIS (1 << 14) 1795 1796 #define GEN9_CLKGATE_DIS_5 _MMIO(0x46540) 1797 #define DPCE_GATING_DIS REG_BIT(17) 1798 1799 #define _CLKGATE_DIS_PSL_A 0x46520 1800 #define _CLKGATE_DIS_PSL_B 0x46524 1801 #define _CLKGATE_DIS_PSL_C 0x46528 1802 #define DUPS1_GATING_DIS (1 << 15) 1803 #define DUPS2_GATING_DIS (1 << 19) 1804 #define DUPS3_GATING_DIS (1 << 23) 1805 #define CURSOR_GATING_DIS REG_BIT(28) 1806 #define DPF_GATING_DIS (1 << 10) 1807 #define DPF_RAM_GATING_DIS (1 << 9) 1808 #define DPFR_GATING_DIS (1 << 8) 1809 1810 #define CLKGATE_DIS_PSL(pipe) \ 1811 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B) 1812 1813 #define _CLKGATE_DIS_PSL_EXT_A 0x4654C 1814 #define _CLKGATE_DIS_PSL_EXT_B 0x46550 1815 #define PIPEDMC_GATING_DIS REG_BIT(12) 1816 1817 #define CLKGATE_DIS_PSL_EXT(pipe) \ 1818 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_EXT_A, _CLKGATE_DIS_PSL_EXT_B) 1819 1820 /* 1821 * Display engine regs 1822 */ 1823 1824 /* Pipe A CRC regs */ 1825 #define _PIPE_CRC_CTL_A 0x60050 1826 #define PIPE_CRC_ENABLE REG_BIT(31) 1827 /* skl+ source selection */ 1828 #define PIPE_CRC_SOURCE_MASK_SKL REG_GENMASK(30, 28) 1829 #define PIPE_CRC_SOURCE_PLANE_1_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 0) 1830 #define PIPE_CRC_SOURCE_PLANE_2_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 2) 1831 #define PIPE_CRC_SOURCE_DMUX_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 4) 1832 #define PIPE_CRC_SOURCE_PLANE_3_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 6) 1833 #define PIPE_CRC_SOURCE_PLANE_4_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 7) 1834 #define PIPE_CRC_SOURCE_PLANE_5_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 5) 1835 #define PIPE_CRC_SOURCE_PLANE_6_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 3) 1836 #define PIPE_CRC_SOURCE_PLANE_7_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 1) 1837 /* ivb+ source selection */ 1838 #define PIPE_CRC_SOURCE_MASK_IVB REG_GENMASK(30, 29) 1839 #define PIPE_CRC_SOURCE_PRIMARY_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 0) 1840 #define PIPE_CRC_SOURCE_SPRITE_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 1) 1841 #define PIPE_CRC_SOURCE_PF_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 2) 1842 /* ilk+ source selection */ 1843 #define PIPE_CRC_SOURCE_MASK_ILK REG_GENMASK(30, 28) 1844 #define PIPE_CRC_SOURCE_PRIMARY_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 0) 1845 #define PIPE_CRC_SOURCE_SPRITE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 1) 1846 #define PIPE_CRC_SOURCE_PIPE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 2) 1847 /* embedded DP port on the north display block */ 1848 #define PIPE_CRC_SOURCE_PORT_A_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 4) 1849 #define PIPE_CRC_SOURCE_FDI_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 5) 1850 /* vlv source selection */ 1851 #define PIPE_CRC_SOURCE_MASK_VLV REG_GENMASK(30, 27) 1852 #define PIPE_CRC_SOURCE_PIPE_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 0) 1853 #define PIPE_CRC_SOURCE_HDMIB_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 1) 1854 #define PIPE_CRC_SOURCE_HDMIC_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 2) 1855 /* with DP port the pipe source is invalid */ 1856 #define PIPE_CRC_SOURCE_DP_D_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 3) 1857 #define PIPE_CRC_SOURCE_DP_B_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 6) 1858 #define PIPE_CRC_SOURCE_DP_C_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 7) 1859 /* gen3+ source selection */ 1860 #define PIPE_CRC_SOURCE_MASK_I9XX REG_GENMASK(30, 28) 1861 #define PIPE_CRC_SOURCE_PIPE_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 0) 1862 #define PIPE_CRC_SOURCE_SDVOB_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 1) 1863 #define PIPE_CRC_SOURCE_SDVOC_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 2) 1864 /* with DP/TV port the pipe source is invalid */ 1865 #define PIPE_CRC_SOURCE_DP_D_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 3) 1866 #define PIPE_CRC_SOURCE_TV_PRE REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 4) 1867 #define PIPE_CRC_SOURCE_TV_POST REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 5) 1868 #define PIPE_CRC_SOURCE_DP_B_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 6) 1869 #define PIPE_CRC_SOURCE_DP_C_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 7) 1870 /* gen2 doesn't have source selection bits */ 1871 #define PIPE_CRC_INCLUDE_BORDER_I8XX REG_BIT(30) 1872 1873 #define _PIPE_CRC_RES_1_A_IVB 0x60064 1874 #define _PIPE_CRC_RES_2_A_IVB 0x60068 1875 #define _PIPE_CRC_RES_3_A_IVB 0x6006c 1876 #define _PIPE_CRC_RES_4_A_IVB 0x60070 1877 #define _PIPE_CRC_RES_5_A_IVB 0x60074 1878 1879 #define _PIPE_CRC_RES_RED_A 0x60060 1880 #define _PIPE_CRC_RES_GREEN_A 0x60064 1881 #define _PIPE_CRC_RES_BLUE_A 0x60068 1882 #define _PIPE_CRC_RES_RES1_A_I915 0x6006c 1883 #define _PIPE_CRC_RES_RES2_A_G4X 0x60080 1884 1885 /* Pipe B CRC regs */ 1886 #define _PIPE_CRC_RES_1_B_IVB 0x61064 1887 #define _PIPE_CRC_RES_2_B_IVB 0x61068 1888 #define _PIPE_CRC_RES_3_B_IVB 0x6106c 1889 #define _PIPE_CRC_RES_4_B_IVB 0x61070 1890 #define _PIPE_CRC_RES_5_B_IVB 0x61074 1891 1892 #define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A) 1893 #define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB) 1894 #define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB) 1895 #define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB) 1896 #define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB) 1897 #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB) 1898 1899 #define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A) 1900 #define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A) 1901 #define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A) 1902 #define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915) 1903 #define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X) 1904 1905 /* Pipe A timing regs */ 1906 #define _HTOTAL_A 0x60000 1907 #define _HBLANK_A 0x60004 1908 #define _HSYNC_A 0x60008 1909 #define _VTOTAL_A 0x6000c 1910 #define _VBLANK_A 0x60010 1911 #define _VSYNC_A 0x60014 1912 #define _EXITLINE_A 0x60018 1913 #define _PIPEASRC 0x6001c 1914 #define PIPESRC_WIDTH_MASK REG_GENMASK(31, 16) 1915 #define PIPESRC_WIDTH(w) REG_FIELD_PREP(PIPESRC_WIDTH_MASK, (w)) 1916 #define PIPESRC_HEIGHT_MASK REG_GENMASK(15, 0) 1917 #define PIPESRC_HEIGHT(h) REG_FIELD_PREP(PIPESRC_HEIGHT_MASK, (h)) 1918 #define _BCLRPAT_A 0x60020 1919 #define _VSYNCSHIFT_A 0x60028 1920 #define _PIPE_MULT_A 0x6002c 1921 1922 /* Pipe B timing regs */ 1923 #define _HTOTAL_B 0x61000 1924 #define _HBLANK_B 0x61004 1925 #define _HSYNC_B 0x61008 1926 #define _VTOTAL_B 0x6100c 1927 #define _VBLANK_B 0x61010 1928 #define _VSYNC_B 0x61014 1929 #define _PIPEBSRC 0x6101c 1930 #define _BCLRPAT_B 0x61020 1931 #define _VSYNCSHIFT_B 0x61028 1932 #define _PIPE_MULT_B 0x6102c 1933 1934 /* DSI 0 timing regs */ 1935 #define _HTOTAL_DSI0 0x6b000 1936 #define _HSYNC_DSI0 0x6b008 1937 #define _VTOTAL_DSI0 0x6b00c 1938 #define _VSYNC_DSI0 0x6b014 1939 #define _VSYNCSHIFT_DSI0 0x6b028 1940 1941 /* DSI 1 timing regs */ 1942 #define _HTOTAL_DSI1 0x6b800 1943 #define _HSYNC_DSI1 0x6b808 1944 #define _VTOTAL_DSI1 0x6b80c 1945 #define _VSYNC_DSI1 0x6b814 1946 #define _VSYNCSHIFT_DSI1 0x6b828 1947 1948 #define TRANSCODER_A_OFFSET 0x60000 1949 #define TRANSCODER_B_OFFSET 0x61000 1950 #define TRANSCODER_C_OFFSET 0x62000 1951 #define CHV_TRANSCODER_C_OFFSET 0x63000 1952 #define TRANSCODER_D_OFFSET 0x63000 1953 #define TRANSCODER_EDP_OFFSET 0x6f000 1954 #define TRANSCODER_DSI0_OFFSET 0x6b000 1955 #define TRANSCODER_DSI1_OFFSET 0x6b800 1956 1957 #define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A) 1958 #define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A) 1959 #define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A) 1960 #define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A) 1961 #define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A) 1962 #define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A) 1963 #define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A) 1964 #define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A) 1965 #define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC) 1966 #define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A) 1967 1968 #define EXITLINE(trans) _MMIO_TRANS2(trans, _EXITLINE_A) 1969 #define EXITLINE_ENABLE REG_BIT(31) 1970 #define EXITLINE_MASK REG_GENMASK(12, 0) 1971 #define EXITLINE_SHIFT 0 1972 1973 /* VRR registers */ 1974 #define _TRANS_VRR_CTL_A 0x60420 1975 #define _TRANS_VRR_CTL_B 0x61420 1976 #define _TRANS_VRR_CTL_C 0x62420 1977 #define _TRANS_VRR_CTL_D 0x63420 1978 #define TRANS_VRR_CTL(trans) _MMIO_TRANS2(trans, _TRANS_VRR_CTL_A) 1979 #define VRR_CTL_VRR_ENABLE REG_BIT(31) 1980 #define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30) 1981 #define VRR_CTL_FLIP_LINE_EN REG_BIT(29) 1982 #define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3) 1983 #define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x)) 1984 #define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0) 1985 #define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0) 1986 #define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x)) 1987 1988 #define _TRANS_VRR_VMAX_A 0x60424 1989 #define _TRANS_VRR_VMAX_B 0x61424 1990 #define _TRANS_VRR_VMAX_C 0x62424 1991 #define _TRANS_VRR_VMAX_D 0x63424 1992 #define TRANS_VRR_VMAX(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMAX_A) 1993 #define VRR_VMAX_MASK REG_GENMASK(19, 0) 1994 1995 #define _TRANS_VRR_VMIN_A 0x60434 1996 #define _TRANS_VRR_VMIN_B 0x61434 1997 #define _TRANS_VRR_VMIN_C 0x62434 1998 #define _TRANS_VRR_VMIN_D 0x63434 1999 #define TRANS_VRR_VMIN(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMIN_A) 2000 #define VRR_VMIN_MASK REG_GENMASK(15, 0) 2001 2002 #define _TRANS_VRR_VMAXSHIFT_A 0x60428 2003 #define _TRANS_VRR_VMAXSHIFT_B 0x61428 2004 #define _TRANS_VRR_VMAXSHIFT_C 0x62428 2005 #define _TRANS_VRR_VMAXSHIFT_D 0x63428 2006 #define TRANS_VRR_VMAXSHIFT(trans) _MMIO_TRANS2(trans, \ 2007 _TRANS_VRR_VMAXSHIFT_A) 2008 #define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16) 2009 #define VRR_VMAXSHIFT_DEC REG_BIT(16) 2010 #define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0) 2011 2012 #define _TRANS_VRR_STATUS_A 0x6042C 2013 #define _TRANS_VRR_STATUS_B 0x6142C 2014 #define _TRANS_VRR_STATUS_C 0x6242C 2015 #define _TRANS_VRR_STATUS_D 0x6342C 2016 #define TRANS_VRR_STATUS(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS_A) 2017 #define VRR_STATUS_VMAX_REACHED REG_BIT(31) 2018 #define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30) 2019 #define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29) 2020 #define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28) 2021 #define VRR_STATUS_VRR_EN_LIVE REG_BIT(27) 2022 #define VRR_STATUS_FLIPS_SERVICED REG_BIT(26) 2023 #define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20) 2024 #define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0) 2025 #define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1) 2026 #define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2) 2027 #define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3) 2028 #define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4) 2029 #define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5) 2030 #define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6) 2031 2032 #define _TRANS_VRR_VTOTAL_PREV_A 0x60480 2033 #define _TRANS_VRR_VTOTAL_PREV_B 0x61480 2034 #define _TRANS_VRR_VTOTAL_PREV_C 0x62480 2035 #define _TRANS_VRR_VTOTAL_PREV_D 0x63480 2036 #define TRANS_VRR_VTOTAL_PREV(trans) _MMIO_TRANS2(trans, \ 2037 _TRANS_VRR_VTOTAL_PREV_A) 2038 #define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31) 2039 #define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30) 2040 #define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29) 2041 #define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0) 2042 2043 #define _TRANS_VRR_FLIPLINE_A 0x60438 2044 #define _TRANS_VRR_FLIPLINE_B 0x61438 2045 #define _TRANS_VRR_FLIPLINE_C 0x62438 2046 #define _TRANS_VRR_FLIPLINE_D 0x63438 2047 #define TRANS_VRR_FLIPLINE(trans) _MMIO_TRANS2(trans, \ 2048 _TRANS_VRR_FLIPLINE_A) 2049 #define VRR_FLIPLINE_MASK REG_GENMASK(19, 0) 2050 2051 #define _TRANS_VRR_STATUS2_A 0x6043C 2052 #define _TRANS_VRR_STATUS2_B 0x6143C 2053 #define _TRANS_VRR_STATUS2_C 0x6243C 2054 #define _TRANS_VRR_STATUS2_D 0x6343C 2055 #define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A) 2056 #define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0) 2057 2058 #define _TRANS_PUSH_A 0x60A70 2059 #define _TRANS_PUSH_B 0x61A70 2060 #define _TRANS_PUSH_C 0x62A70 2061 #define _TRANS_PUSH_D 0x63A70 2062 #define TRANS_PUSH(trans) _MMIO_TRANS2(trans, _TRANS_PUSH_A) 2063 #define TRANS_PUSH_EN REG_BIT(31) 2064 #define TRANS_PUSH_SEND REG_BIT(30) 2065 2066 /* 2067 * HSW+ eDP PSR registers 2068 * 2069 * HSW PSR registers are relative to DDIA(_DDI_BUF_CTL_A + 0x800) with just one 2070 * instance of it 2071 */ 2072 #define _SRD_CTL_A 0x60800 2073 #define _SRD_CTL_EDP 0x6f800 2074 #define EDP_PSR_CTL(tran) _MMIO_TRANS2(tran, _SRD_CTL_A) 2075 #define EDP_PSR_ENABLE (1 << 31) 2076 #define BDW_PSR_SINGLE_FRAME (1 << 30) 2077 #define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1 << 29) /* SW can't modify */ 2078 #define EDP_PSR_LINK_STANDBY (1 << 27) 2079 #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3 << 25) 2080 #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0 << 25) 2081 #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1 << 25) 2082 #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2 << 25) 2083 #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3 << 25) 2084 #define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20 2085 #define EDP_PSR_SKIP_AUX_EXIT (1 << 12) 2086 #define EDP_PSR_TP1_TP2_SEL (0 << 11) 2087 #define EDP_PSR_TP1_TP3_SEL (1 << 11) 2088 #define EDP_PSR_CRC_ENABLE (1 << 10) /* BDW+ */ 2089 #define EDP_PSR_TP2_TP3_TIME_500us (0 << 8) 2090 #define EDP_PSR_TP2_TP3_TIME_100us (1 << 8) 2091 #define EDP_PSR_TP2_TP3_TIME_2500us (2 << 8) 2092 #define EDP_PSR_TP2_TP3_TIME_0us (3 << 8) 2093 #define EDP_PSR_TP4_TIME_0US (3 << 6) /* ICL+ */ 2094 #define EDP_PSR_TP1_TIME_500us (0 << 4) 2095 #define EDP_PSR_TP1_TIME_100us (1 << 4) 2096 #define EDP_PSR_TP1_TIME_2500us (2 << 4) 2097 #define EDP_PSR_TP1_TIME_0us (3 << 4) 2098 #define EDP_PSR_IDLE_FRAME_SHIFT 0 2099 2100 /* 2101 * Until TGL, IMR/IIR are fixed at 0x648xx. On TGL+ those registers are relative 2102 * to transcoder and bits defined for each one as if using no shift (i.e. as if 2103 * it was for TRANSCODER_EDP) 2104 */ 2105 #define EDP_PSR_IMR _MMIO(0x64834) 2106 #define EDP_PSR_IIR _MMIO(0x64838) 2107 #define _PSR_IMR_A 0x60814 2108 #define _PSR_IIR_A 0x60818 2109 #define TRANS_PSR_IMR(tran) _MMIO_TRANS2(tran, _PSR_IMR_A) 2110 #define TRANS_PSR_IIR(tran) _MMIO_TRANS2(tran, _PSR_IIR_A) 2111 #define _EDP_PSR_TRANS_SHIFT(trans) ((trans) == TRANSCODER_EDP ? \ 2112 0 : ((trans) - TRANSCODER_A + 1) * 8) 2113 #define TGL_PSR_MASK REG_GENMASK(2, 0) 2114 #define TGL_PSR_ERROR REG_BIT(2) 2115 #define TGL_PSR_POST_EXIT REG_BIT(1) 2116 #define TGL_PSR_PRE_ENTRY REG_BIT(0) 2117 #define EDP_PSR_MASK(trans) (TGL_PSR_MASK << \ 2118 _EDP_PSR_TRANS_SHIFT(trans)) 2119 #define EDP_PSR_ERROR(trans) (TGL_PSR_ERROR << \ 2120 _EDP_PSR_TRANS_SHIFT(trans)) 2121 #define EDP_PSR_POST_EXIT(trans) (TGL_PSR_POST_EXIT << \ 2122 _EDP_PSR_TRANS_SHIFT(trans)) 2123 #define EDP_PSR_PRE_ENTRY(trans) (TGL_PSR_PRE_ENTRY << \ 2124 _EDP_PSR_TRANS_SHIFT(trans)) 2125 2126 #define _SRD_AUX_DATA_A 0x60814 2127 #define _SRD_AUX_DATA_EDP 0x6f814 2128 #define EDP_PSR_AUX_DATA(tran, i) _MMIO_TRANS2(tran, _SRD_AUX_DATA_A + (i) + 4) /* 5 registers */ 2129 2130 #define _SRD_STATUS_A 0x60840 2131 #define _SRD_STATUS_EDP 0x6f840 2132 #define EDP_PSR_STATUS(tran) _MMIO_TRANS2(tran, _SRD_STATUS_A) 2133 #define EDP_PSR_STATUS_STATE_MASK (7 << 29) 2134 #define EDP_PSR_STATUS_STATE_SHIFT 29 2135 #define EDP_PSR_STATUS_STATE_IDLE (0 << 29) 2136 #define EDP_PSR_STATUS_STATE_SRDONACK (1 << 29) 2137 #define EDP_PSR_STATUS_STATE_SRDENT (2 << 29) 2138 #define EDP_PSR_STATUS_STATE_BUFOFF (3 << 29) 2139 #define EDP_PSR_STATUS_STATE_BUFON (4 << 29) 2140 #define EDP_PSR_STATUS_STATE_AUXACK (5 << 29) 2141 #define EDP_PSR_STATUS_STATE_SRDOFFACK (6 << 29) 2142 #define EDP_PSR_STATUS_LINK_MASK (3 << 26) 2143 #define EDP_PSR_STATUS_LINK_FULL_OFF (0 << 26) 2144 #define EDP_PSR_STATUS_LINK_FULL_ON (1 << 26) 2145 #define EDP_PSR_STATUS_LINK_STANDBY (2 << 26) 2146 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20 2147 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f 2148 #define EDP_PSR_STATUS_COUNT_SHIFT 16 2149 #define EDP_PSR_STATUS_COUNT_MASK 0xf 2150 #define EDP_PSR_STATUS_AUX_ERROR (1 << 15) 2151 #define EDP_PSR_STATUS_AUX_SENDING (1 << 12) 2152 #define EDP_PSR_STATUS_SENDING_IDLE (1 << 9) 2153 #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1 << 8) 2154 #define EDP_PSR_STATUS_SENDING_TP1 (1 << 4) 2155 #define EDP_PSR_STATUS_IDLE_MASK 0xf 2156 2157 #define _SRD_PERF_CNT_A 0x60844 2158 #define _SRD_PERF_CNT_EDP 0x6f844 2159 #define EDP_PSR_PERF_CNT(tran) _MMIO_TRANS2(tran, _SRD_PERF_CNT_A) 2160 #define EDP_PSR_PERF_CNT_MASK 0xffffff 2161 2162 /* PSR_MASK on SKL+ */ 2163 #define _SRD_DEBUG_A 0x60860 2164 #define _SRD_DEBUG_EDP 0x6f860 2165 #define EDP_PSR_DEBUG(tran) _MMIO_TRANS2(tran, _SRD_DEBUG_A) 2166 #define EDP_PSR_DEBUG_MASK_MAX_SLEEP (1 << 28) 2167 #define EDP_PSR_DEBUG_MASK_LPSP (1 << 27) 2168 #define EDP_PSR_DEBUG_MASK_MEMUP (1 << 26) 2169 #define EDP_PSR_DEBUG_MASK_HPD (1 << 25) 2170 #define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) /* Reserved in ICL+ */ 2171 #define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */ 2172 2173 #define _PSR2_CTL_A 0x60900 2174 #define _PSR2_CTL_EDP 0x6f900 2175 #define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A) 2176 #define EDP_PSR2_ENABLE (1 << 31) 2177 #define EDP_SU_TRACK_ENABLE (1 << 30) /* up to adl-p */ 2178 #define TGL_EDP_PSR2_BLOCK_COUNT_NUM_2 (0 << 28) 2179 #define TGL_EDP_PSR2_BLOCK_COUNT_NUM_3 (1 << 28) 2180 #define EDP_Y_COORDINATE_ENABLE REG_BIT(25) /* display 10, 11 and 12 */ 2181 #define EDP_PSR2_SU_SDP_SCANLINE REG_BIT(25) /* display 13+ */ 2182 #define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20) 2183 #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20) 2184 #define EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES 8 2185 #define EDP_PSR2_IO_BUFFER_WAKE(lines) ((EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines)) << 13) 2186 #define EDP_PSR2_IO_BUFFER_WAKE_MASK (3 << 13) 2187 #define TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5 2188 #define TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT 13 2189 #define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) (((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT) 2190 #define TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK (7 << 13) 2191 #define EDP_PSR2_FAST_WAKE_MAX_LINES 8 2192 #define EDP_PSR2_FAST_WAKE(lines) ((EDP_PSR2_FAST_WAKE_MAX_LINES - (lines)) << 11) 2193 #define EDP_PSR2_FAST_WAKE_MASK (3 << 11) 2194 #define TGL_EDP_PSR2_FAST_WAKE_MIN_LINES 5 2195 #define TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT 10 2196 #define TGL_EDP_PSR2_FAST_WAKE(lines) (((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT) 2197 #define TGL_EDP_PSR2_FAST_WAKE_MASK (7 << 10) 2198 #define EDP_PSR2_TP2_TIME_500us (0 << 8) 2199 #define EDP_PSR2_TP2_TIME_100us (1 << 8) 2200 #define EDP_PSR2_TP2_TIME_2500us (2 << 8) 2201 #define EDP_PSR2_TP2_TIME_50us (3 << 8) 2202 #define EDP_PSR2_TP2_TIME_MASK (3 << 8) 2203 #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 2204 #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4) 2205 #define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4) 2206 #define EDP_PSR2_IDLE_FRAME_MASK 0xf 2207 #define EDP_PSR2_IDLE_FRAME_SHIFT 0 2208 2209 #define _PSR_EVENT_TRANS_A 0x60848 2210 #define _PSR_EVENT_TRANS_B 0x61848 2211 #define _PSR_EVENT_TRANS_C 0x62848 2212 #define _PSR_EVENT_TRANS_D 0x63848 2213 #define _PSR_EVENT_TRANS_EDP 0x6f848 2214 #define PSR_EVENT(tran) _MMIO_TRANS2(tran, _PSR_EVENT_TRANS_A) 2215 #define PSR_EVENT_PSR2_WD_TIMER_EXPIRE (1 << 17) 2216 #define PSR_EVENT_PSR2_DISABLED (1 << 16) 2217 #define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN (1 << 15) 2218 #define PSR_EVENT_SU_CRC_FIFO_UNDERRUN (1 << 14) 2219 #define PSR_EVENT_GRAPHICS_RESET (1 << 12) 2220 #define PSR_EVENT_PCH_INTERRUPT (1 << 11) 2221 #define PSR_EVENT_MEMORY_UP (1 << 10) 2222 #define PSR_EVENT_FRONT_BUFFER_MODIFY (1 << 9) 2223 #define PSR_EVENT_WD_TIMER_EXPIRE (1 << 8) 2224 #define PSR_EVENT_PIPE_REGISTERS_UPDATE (1 << 6) 2225 #define PSR_EVENT_REGISTER_UPDATE (1 << 5) /* Reserved in ICL+ */ 2226 #define PSR_EVENT_HDCP_ENABLE (1 << 4) 2227 #define PSR_EVENT_KVMR_SESSION_ENABLE (1 << 3) 2228 #define PSR_EVENT_VBI_ENABLE (1 << 2) 2229 #define PSR_EVENT_LPSP_MODE_EXIT (1 << 1) 2230 #define PSR_EVENT_PSR_DISABLE (1 << 0) 2231 2232 #define _PSR2_STATUS_A 0x60940 2233 #define _PSR2_STATUS_EDP 0x6f940 2234 #define EDP_PSR2_STATUS(tran) _MMIO_TRANS2(tran, _PSR2_STATUS_A) 2235 #define EDP_PSR2_STATUS_STATE_MASK REG_GENMASK(31, 28) 2236 #define EDP_PSR2_STATUS_STATE_DEEP_SLEEP REG_FIELD_PREP(EDP_PSR2_STATUS_STATE_MASK, 0x8) 2237 2238 #define _PSR2_SU_STATUS_A 0x60914 2239 #define _PSR2_SU_STATUS_EDP 0x6f914 2240 #define _PSR2_SU_STATUS(tran, index) _MMIO_TRANS2(tran, _PSR2_SU_STATUS_A + (index) * 4) 2241 #define PSR2_SU_STATUS(tran, frame) (_PSR2_SU_STATUS(tran, (frame) / 3)) 2242 #define PSR2_SU_STATUS_SHIFT(frame) (((frame) % 3) * 10) 2243 #define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame)) 2244 #define PSR2_SU_STATUS_FRAMES 8 2245 2246 #define _PSR2_MAN_TRK_CTL_A 0x60910 2247 #define _PSR2_MAN_TRK_CTL_EDP 0x6f910 2248 #define PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A) 2249 #define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31) 2250 #define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30, 21) 2251 #define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val) 2252 #define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(20, 11) 2253 #define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val) 2254 #define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3) 2255 #define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2) 2256 #define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1) 2257 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(28, 16) 2258 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val) 2259 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(12, 0) 2260 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val) 2261 #define ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(31) 2262 #define ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(14) 2263 #define ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(13) 2264 2265 /* Icelake DSC Rate Control Range Parameter Registers */ 2266 #define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240) 2267 #define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4) 2268 #define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40) 2269 #define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4) 2270 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208) 2271 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4) 2272 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308) 2273 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4) 2274 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408) 2275 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4) 2276 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508) 2277 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4) 2278 #define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2279 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \ 2280 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC) 2281 #define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2282 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \ 2283 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC) 2284 #define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2285 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \ 2286 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC) 2287 #define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2288 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \ 2289 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC) 2290 #define RC_BPG_OFFSET_SHIFT 10 2291 #define RC_MAX_QP_SHIFT 5 2292 #define RC_MIN_QP_SHIFT 0 2293 2294 #define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248) 2295 #define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4) 2296 #define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48) 2297 #define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4) 2298 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210) 2299 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4) 2300 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310) 2301 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4) 2302 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410) 2303 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4) 2304 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510) 2305 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4) 2306 #define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2307 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \ 2308 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC) 2309 #define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2310 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \ 2311 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC) 2312 #define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2313 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \ 2314 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC) 2315 #define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2316 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \ 2317 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC) 2318 2319 #define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250) 2320 #define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4) 2321 #define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50) 2322 #define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4) 2323 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218) 2324 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4) 2325 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318) 2326 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4) 2327 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418) 2328 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4) 2329 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518) 2330 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4) 2331 #define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2332 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \ 2333 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC) 2334 #define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2335 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \ 2336 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC) 2337 #define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2338 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \ 2339 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC) 2340 #define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2341 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \ 2342 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC) 2343 2344 #define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258) 2345 #define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4) 2346 #define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58) 2347 #define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4) 2348 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220) 2349 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4) 2350 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320) 2351 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4) 2352 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420) 2353 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4) 2354 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520) 2355 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4) 2356 #define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2357 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \ 2358 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC) 2359 #define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2360 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \ 2361 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC) 2362 #define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2363 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \ 2364 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC) 2365 #define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2366 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \ 2367 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC) 2368 2369 /* VGA port control */ 2370 #define ADPA _MMIO(0x61100) 2371 #define PCH_ADPA _MMIO(0xe1100) 2372 #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100) 2373 2374 #define ADPA_DAC_ENABLE (1 << 31) 2375 #define ADPA_DAC_DISABLE 0 2376 #define ADPA_PIPE_SEL_SHIFT 30 2377 #define ADPA_PIPE_SEL_MASK (1 << 30) 2378 #define ADPA_PIPE_SEL(pipe) ((pipe) << 30) 2379 #define ADPA_PIPE_SEL_SHIFT_CPT 29 2380 #define ADPA_PIPE_SEL_MASK_CPT (3 << 29) 2381 #define ADPA_PIPE_SEL_CPT(pipe) ((pipe) << 29) 2382 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ 2383 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0 << 24) 2384 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3 << 24) 2385 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3 << 24) 2386 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2 << 24) 2387 #define ADPA_CRT_HOTPLUG_ENABLE (1 << 23) 2388 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0 << 22) 2389 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1 << 22) 2390 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0 << 21) 2391 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1 << 21) 2392 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0 << 20) 2393 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1 << 20) 2394 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0 << 18) 2395 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1 << 18) 2396 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2 << 18) 2397 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3 << 18) 2398 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0 << 17) 2399 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1 << 17) 2400 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1 << 16) 2401 #define ADPA_USE_VGA_HVPOLARITY (1 << 15) 2402 #define ADPA_SETS_HVPOLARITY 0 2403 #define ADPA_VSYNC_CNTL_DISABLE (1 << 10) 2404 #define ADPA_VSYNC_CNTL_ENABLE 0 2405 #define ADPA_HSYNC_CNTL_DISABLE (1 << 11) 2406 #define ADPA_HSYNC_CNTL_ENABLE 0 2407 #define ADPA_VSYNC_ACTIVE_HIGH (1 << 4) 2408 #define ADPA_VSYNC_ACTIVE_LOW 0 2409 #define ADPA_HSYNC_ACTIVE_HIGH (1 << 3) 2410 #define ADPA_HSYNC_ACTIVE_LOW 0 2411 #define ADPA_DPMS_MASK (~(3 << 10)) 2412 #define ADPA_DPMS_ON (0 << 10) 2413 #define ADPA_DPMS_SUSPEND (1 << 10) 2414 #define ADPA_DPMS_STANDBY (2 << 10) 2415 #define ADPA_DPMS_OFF (3 << 10) 2416 2417 2418 /* Hotplug control (945+ only) */ 2419 #define PORT_HOTPLUG_EN _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110) 2420 #define PORTB_HOTPLUG_INT_EN (1 << 29) 2421 #define PORTC_HOTPLUG_INT_EN (1 << 28) 2422 #define PORTD_HOTPLUG_INT_EN (1 << 27) 2423 #define SDVOB_HOTPLUG_INT_EN (1 << 26) 2424 #define SDVOC_HOTPLUG_INT_EN (1 << 25) 2425 #define TV_HOTPLUG_INT_EN (1 << 18) 2426 #define CRT_HOTPLUG_INT_EN (1 << 9) 2427 #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \ 2428 PORTC_HOTPLUG_INT_EN | \ 2429 PORTD_HOTPLUG_INT_EN | \ 2430 SDVOC_HOTPLUG_INT_EN | \ 2431 SDVOB_HOTPLUG_INT_EN | \ 2432 CRT_HOTPLUG_INT_EN) 2433 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 2434 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) 2435 /* must use period 64 on GM45 according to docs */ 2436 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) 2437 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) 2438 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) 2439 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) 2440 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) 2441 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) 2442 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) 2443 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) 2444 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) 2445 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) 2446 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) 2447 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 2448 2449 #define PORT_HOTPLUG_STAT _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114) 2450 /* 2451 * HDMI/DP bits are g4x+ 2452 * 2453 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused. 2454 * Please check the detailed lore in the commit message for for experimental 2455 * evidence. 2456 */ 2457 /* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */ 2458 #define PORTD_HOTPLUG_LIVE_STATUS_GM45 (1 << 29) 2459 #define PORTC_HOTPLUG_LIVE_STATUS_GM45 (1 << 28) 2460 #define PORTB_HOTPLUG_LIVE_STATUS_GM45 (1 << 27) 2461 /* G4X/VLV/CHV DP/HDMI bits again match Bspec */ 2462 #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27) 2463 #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28) 2464 #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29) 2465 #define PORTD_HOTPLUG_INT_STATUS (3 << 21) 2466 #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21) 2467 #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21) 2468 #define PORTC_HOTPLUG_INT_STATUS (3 << 19) 2469 #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19) 2470 #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19) 2471 #define PORTB_HOTPLUG_INT_STATUS (3 << 17) 2472 #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17) 2473 #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17) 2474 /* CRT/TV common between gen3+ */ 2475 #define CRT_HOTPLUG_INT_STATUS (1 << 11) 2476 #define TV_HOTPLUG_INT_STATUS (1 << 10) 2477 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 2478 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 2479 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 2480 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 2481 #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6) 2482 #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5) 2483 #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4) 2484 #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4) 2485 2486 /* SDVO is different across gen3/4 */ 2487 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) 2488 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) 2489 /* 2490 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm, 2491 * since reality corrobates that they're the same as on gen3. But keep these 2492 * bits here (and the comment!) to help any other lost wanderers back onto the 2493 * right tracks. 2494 */ 2495 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4) 2496 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) 2497 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) 2498 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) 2499 #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \ 2500 SDVOB_HOTPLUG_INT_STATUS_G4X | \ 2501 SDVOC_HOTPLUG_INT_STATUS_G4X | \ 2502 PORTB_HOTPLUG_INT_STATUS | \ 2503 PORTC_HOTPLUG_INT_STATUS | \ 2504 PORTD_HOTPLUG_INT_STATUS) 2505 2506 #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \ 2507 SDVOB_HOTPLUG_INT_STATUS_I915 | \ 2508 SDVOC_HOTPLUG_INT_STATUS_I915 | \ 2509 PORTB_HOTPLUG_INT_STATUS | \ 2510 PORTC_HOTPLUG_INT_STATUS | \ 2511 PORTD_HOTPLUG_INT_STATUS) 2512 2513 /* SDVO and HDMI port control. 2514 * The same register may be used for SDVO or HDMI */ 2515 #define _GEN3_SDVOB 0x61140 2516 #define _GEN3_SDVOC 0x61160 2517 #define GEN3_SDVOB _MMIO(_GEN3_SDVOB) 2518 #define GEN3_SDVOC _MMIO(_GEN3_SDVOC) 2519 #define GEN4_HDMIB GEN3_SDVOB 2520 #define GEN4_HDMIC GEN3_SDVOC 2521 #define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140) 2522 #define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160) 2523 #define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C) 2524 #define PCH_SDVOB _MMIO(0xe1140) 2525 #define PCH_HDMIB PCH_SDVOB 2526 #define PCH_HDMIC _MMIO(0xe1150) 2527 #define PCH_HDMID _MMIO(0xe1160) 2528 2529 #define PORT_DFT_I9XX _MMIO(0x61150) 2530 #define DC_BALANCE_RESET (1 << 25) 2531 #define PORT_DFT2_G4X _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154) 2532 #define DC_BALANCE_RESET_VLV (1 << 31) 2533 #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0)) 2534 #define PIPE_C_SCRAMBLE_RESET REG_BIT(14) /* chv */ 2535 #define PIPE_B_SCRAMBLE_RESET REG_BIT(1) 2536 #define PIPE_A_SCRAMBLE_RESET REG_BIT(0) 2537 2538 /* Gen 3 SDVO bits: */ 2539 #define SDVO_ENABLE (1 << 31) 2540 #define SDVO_PIPE_SEL_SHIFT 30 2541 #define SDVO_PIPE_SEL_MASK (1 << 30) 2542 #define SDVO_PIPE_SEL(pipe) ((pipe) << 30) 2543 #define SDVO_STALL_SELECT (1 << 29) 2544 #define SDVO_INTERRUPT_ENABLE (1 << 26) 2545 /* 2546 * 915G/GM SDVO pixel multiplier. 2547 * Programmed value is multiplier - 1, up to 5x. 2548 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 2549 */ 2550 #define SDVO_PORT_MULTIPLY_MASK (7 << 23) 2551 #define SDVO_PORT_MULTIPLY_SHIFT 23 2552 #define SDVO_PHASE_SELECT_MASK (15 << 19) 2553 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 2554 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 2555 #define SDVOC_GANG_MODE (1 << 16) /* Port C only */ 2556 #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */ 2557 #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */ 2558 #define SDVO_DETECTED (1 << 2) 2559 /* Bits to be preserved when writing */ 2560 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \ 2561 SDVO_INTERRUPT_ENABLE) 2562 #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE) 2563 2564 /* Gen 4 SDVO/HDMI bits: */ 2565 #define SDVO_COLOR_FORMAT_8bpc (0 << 26) 2566 #define SDVO_COLOR_FORMAT_MASK (7 << 26) 2567 #define SDVO_ENCODING_SDVO (0 << 10) 2568 #define SDVO_ENCODING_HDMI (2 << 10) 2569 #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */ 2570 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */ 2571 #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */ 2572 #define HDMI_AUDIO_ENABLE (1 << 6) /* HDMI only */ 2573 /* VSYNC/HSYNC bits new with 965, default is to be set */ 2574 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) 2575 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) 2576 2577 /* Gen 5 (IBX) SDVO/HDMI bits: */ 2578 #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */ 2579 #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */ 2580 2581 /* Gen 6 (CPT) SDVO/HDMI bits: */ 2582 #define SDVO_PIPE_SEL_SHIFT_CPT 29 2583 #define SDVO_PIPE_SEL_MASK_CPT (3 << 29) 2584 #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29) 2585 2586 /* CHV SDVO/HDMI bits: */ 2587 #define SDVO_PIPE_SEL_SHIFT_CHV 24 2588 #define SDVO_PIPE_SEL_MASK_CHV (3 << 24) 2589 #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24) 2590 2591 /* LVDS port control */ 2592 #define LVDS _MMIO(0x61180) 2593 /* 2594 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 2595 * the DPLL semantics change when the LVDS is assigned to that pipe. 2596 */ 2597 #define LVDS_PORT_EN (1 << 31) 2598 /* Selects pipe B for LVDS data. Must be set on pre-965. */ 2599 #define LVDS_PIPE_SEL_SHIFT 30 2600 #define LVDS_PIPE_SEL_MASK (1 << 30) 2601 #define LVDS_PIPE_SEL(pipe) ((pipe) << 30) 2602 #define LVDS_PIPE_SEL_SHIFT_CPT 29 2603 #define LVDS_PIPE_SEL_MASK_CPT (3 << 29) 2604 #define LVDS_PIPE_SEL_CPT(pipe) ((pipe) << 29) 2605 /* LVDS dithering flag on 965/g4x platform */ 2606 #define LVDS_ENABLE_DITHER (1 << 25) 2607 /* LVDS sync polarity flags. Set to invert (i.e. negative) */ 2608 #define LVDS_VSYNC_POLARITY (1 << 21) 2609 #define LVDS_HSYNC_POLARITY (1 << 20) 2610 2611 /* Enable border for unscaled (or aspect-scaled) display */ 2612 #define LVDS_BORDER_ENABLE (1 << 15) 2613 /* 2614 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 2615 * pixel. 2616 */ 2617 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) 2618 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) 2619 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 2620 /* 2621 * Controls the A3 data pair, which contains the additional LSBs for 24 bit 2622 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be 2623 * on. 2624 */ 2625 #define LVDS_A3_POWER_MASK (3 << 6) 2626 #define LVDS_A3_POWER_DOWN (0 << 6) 2627 #define LVDS_A3_POWER_UP (3 << 6) 2628 /* 2629 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP 2630 * is set. 2631 */ 2632 #define LVDS_CLKB_POWER_MASK (3 << 4) 2633 #define LVDS_CLKB_POWER_DOWN (0 << 4) 2634 #define LVDS_CLKB_POWER_UP (3 << 4) 2635 /* 2636 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 2637 * setting for whether we are in dual-channel mode. The B3 pair will 2638 * additionally only be powered up when LVDS_A3_POWER_UP is set. 2639 */ 2640 #define LVDS_B0B3_POWER_MASK (3 << 2) 2641 #define LVDS_B0B3_POWER_DOWN (0 << 2) 2642 #define LVDS_B0B3_POWER_UP (3 << 2) 2643 2644 /* Video Data Island Packet control */ 2645 #define VIDEO_DIP_DATA _MMIO(0x61178) 2646 /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC 2647 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte 2648 * of the infoframe structure specified by CEA-861. */ 2649 #define VIDEO_DIP_DATA_SIZE 32 2650 #define VIDEO_DIP_GMP_DATA_SIZE 36 2651 #define VIDEO_DIP_VSC_DATA_SIZE 36 2652 #define VIDEO_DIP_PPS_DATA_SIZE 132 2653 #define VIDEO_DIP_CTL _MMIO(0x61170) 2654 /* Pre HSW: */ 2655 #define VIDEO_DIP_ENABLE (1 << 31) 2656 #define VIDEO_DIP_PORT(port) ((port) << 29) 2657 #define VIDEO_DIP_PORT_MASK (3 << 29) 2658 #define VIDEO_DIP_ENABLE_GCP (1 << 25) /* ilk+ */ 2659 #define VIDEO_DIP_ENABLE_AVI (1 << 21) 2660 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) 2661 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21) /* ilk+ */ 2662 #define VIDEO_DIP_ENABLE_SPD (8 << 21) 2663 #define VIDEO_DIP_SELECT_AVI (0 << 19) 2664 #define VIDEO_DIP_SELECT_VENDOR (1 << 19) 2665 #define VIDEO_DIP_SELECT_GAMUT (2 << 19) 2666 #define VIDEO_DIP_SELECT_SPD (3 << 19) 2667 #define VIDEO_DIP_SELECT_MASK (3 << 19) 2668 #define VIDEO_DIP_FREQ_ONCE (0 << 16) 2669 #define VIDEO_DIP_FREQ_VSYNC (1 << 16) 2670 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) 2671 #define VIDEO_DIP_FREQ_MASK (3 << 16) 2672 /* HSW and later: */ 2673 #define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28) 2674 #define PSR_VSC_BIT_7_SET (1 << 27) 2675 #define VSC_SELECT_MASK (0x3 << 25) 2676 #define VSC_SELECT_SHIFT 25 2677 #define VSC_DIP_HW_HEA_DATA (0 << 25) 2678 #define VSC_DIP_HW_HEA_SW_DATA (1 << 25) 2679 #define VSC_DIP_HW_DATA_SW_HEA (2 << 25) 2680 #define VSC_DIP_SW_HEA_DATA (3 << 25) 2681 #define VDIP_ENABLE_PPS (1 << 24) 2682 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) 2683 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) 2684 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) 2685 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) 2686 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) 2687 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) 2688 2689 /* Panel power sequencing */ 2690 #define PPS_BASE 0x61200 2691 #define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE) 2692 #define PCH_PPS_BASE 0xC7200 2693 2694 #define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->display.pps.mmio_base - \ 2695 PPS_BASE + (reg) + \ 2696 (pps_idx) * 0x100) 2697 2698 #define _PP_STATUS 0x61200 2699 #define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS) 2700 #define PP_ON REG_BIT(31) 2701 /* 2702 * Indicates that all dependencies of the panel are on: 2703 * 2704 * - PLL enabled 2705 * - pipe enabled 2706 * - LVDS/DVOB/DVOC on 2707 */ 2708 #define PP_READY REG_BIT(30) 2709 #define PP_SEQUENCE_MASK REG_GENMASK(29, 28) 2710 #define PP_SEQUENCE_NONE REG_FIELD_PREP(PP_SEQUENCE_MASK, 0) 2711 #define PP_SEQUENCE_POWER_UP REG_FIELD_PREP(PP_SEQUENCE_MASK, 1) 2712 #define PP_SEQUENCE_POWER_DOWN REG_FIELD_PREP(PP_SEQUENCE_MASK, 2) 2713 #define PP_CYCLE_DELAY_ACTIVE REG_BIT(27) 2714 #define PP_SEQUENCE_STATE_MASK REG_GENMASK(3, 0) 2715 #define PP_SEQUENCE_STATE_OFF_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0) 2716 #define PP_SEQUENCE_STATE_OFF_S0_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1) 2717 #define PP_SEQUENCE_STATE_OFF_S0_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2) 2718 #define PP_SEQUENCE_STATE_OFF_S0_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3) 2719 #define PP_SEQUENCE_STATE_ON_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8) 2720 #define PP_SEQUENCE_STATE_ON_S1_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9) 2721 #define PP_SEQUENCE_STATE_ON_S1_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xa) 2722 #define PP_SEQUENCE_STATE_ON_S1_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xb) 2723 #define PP_SEQUENCE_STATE_RESET REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf) 2724 2725 #define _PP_CONTROL 0x61204 2726 #define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL) 2727 #define PANEL_UNLOCK_MASK REG_GENMASK(31, 16) 2728 #define PANEL_UNLOCK_REGS REG_FIELD_PREP(PANEL_UNLOCK_MASK, 0xabcd) 2729 #define BXT_POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4) 2730 #define EDP_FORCE_VDD REG_BIT(3) 2731 #define EDP_BLC_ENABLE REG_BIT(2) 2732 #define PANEL_POWER_RESET REG_BIT(1) 2733 #define PANEL_POWER_ON REG_BIT(0) 2734 2735 #define _PP_ON_DELAYS 0x61208 2736 #define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS) 2737 #define PANEL_PORT_SELECT_MASK REG_GENMASK(31, 30) 2738 #define PANEL_PORT_SELECT_LVDS REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 0) 2739 #define PANEL_PORT_SELECT_DPA REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 1) 2740 #define PANEL_PORT_SELECT_DPC REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 2) 2741 #define PANEL_PORT_SELECT_DPD REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 3) 2742 #define PANEL_PORT_SELECT_VLV(port) REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, port) 2743 #define PANEL_POWER_UP_DELAY_MASK REG_GENMASK(28, 16) 2744 #define PANEL_LIGHT_ON_DELAY_MASK REG_GENMASK(12, 0) 2745 2746 #define _PP_OFF_DELAYS 0x6120C 2747 #define PP_OFF_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_OFF_DELAYS) 2748 #define PANEL_POWER_DOWN_DELAY_MASK REG_GENMASK(28, 16) 2749 #define PANEL_LIGHT_OFF_DELAY_MASK REG_GENMASK(12, 0) 2750 2751 #define _PP_DIVISOR 0x61210 2752 #define PP_DIVISOR(pps_idx) _MMIO_PPS(pps_idx, _PP_DIVISOR) 2753 #define PP_REFERENCE_DIVIDER_MASK REG_GENMASK(31, 8) 2754 #define PANEL_POWER_CYCLE_DELAY_MASK REG_GENMASK(4, 0) 2755 2756 /* Panel fitting */ 2757 #define PFIT_CONTROL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230) 2758 #define PFIT_ENABLE (1 << 31) 2759 #define PFIT_PIPE_MASK (3 << 29) 2760 #define PFIT_PIPE_SHIFT 29 2761 #define PFIT_PIPE(pipe) ((pipe) << 29) 2762 #define VERT_INTERP_DISABLE (0 << 10) 2763 #define VERT_INTERP_BILINEAR (1 << 10) 2764 #define VERT_INTERP_MASK (3 << 10) 2765 #define VERT_AUTO_SCALE (1 << 9) 2766 #define HORIZ_INTERP_DISABLE (0 << 6) 2767 #define HORIZ_INTERP_BILINEAR (1 << 6) 2768 #define HORIZ_INTERP_MASK (3 << 6) 2769 #define HORIZ_AUTO_SCALE (1 << 5) 2770 #define PANEL_8TO6_DITHER_ENABLE (1 << 3) 2771 #define PFIT_FILTER_FUZZY (0 << 24) 2772 #define PFIT_SCALING_AUTO (0 << 26) 2773 #define PFIT_SCALING_PROGRAMMED (1 << 26) 2774 #define PFIT_SCALING_PILLAR (2 << 26) 2775 #define PFIT_SCALING_LETTER (3 << 26) 2776 #define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234) 2777 /* Pre-965 */ 2778 #define PFIT_VERT_SCALE_SHIFT 20 2779 #define PFIT_VERT_SCALE_MASK 0xfff00000 2780 #define PFIT_HORIZ_SCALE_SHIFT 4 2781 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 2782 /* 965+ */ 2783 #define PFIT_VERT_SCALE_SHIFT_965 16 2784 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000 2785 #define PFIT_HORIZ_SCALE_SHIFT_965 0 2786 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff 2787 2788 #define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238) 2789 2790 #define PCH_GTC_CTL _MMIO(0xe7000) 2791 #define PCH_GTC_ENABLE (1 << 31) 2792 2793 /* TV port control */ 2794 #define TV_CTL _MMIO(0x68000) 2795 /* Enables the TV encoder */ 2796 # define TV_ENC_ENABLE (1 << 31) 2797 /* Sources the TV encoder input from pipe B instead of A. */ 2798 # define TV_ENC_PIPE_SEL_SHIFT 30 2799 # define TV_ENC_PIPE_SEL_MASK (1 << 30) 2800 # define TV_ENC_PIPE_SEL(pipe) ((pipe) << 30) 2801 /* Outputs composite video (DAC A only) */ 2802 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28) 2803 /* Outputs SVideo video (DAC B/C) */ 2804 # define TV_ENC_OUTPUT_SVIDEO (1 << 28) 2805 /* Outputs Component video (DAC A/B/C) */ 2806 # define TV_ENC_OUTPUT_COMPONENT (2 << 28) 2807 /* Outputs Composite and SVideo (DAC A/B/C) */ 2808 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) 2809 # define TV_TRILEVEL_SYNC (1 << 21) 2810 /* Enables slow sync generation (945GM only) */ 2811 # define TV_SLOW_SYNC (1 << 20) 2812 /* Selects 4x oversampling for 480i and 576p */ 2813 # define TV_OVERSAMPLE_4X (0 << 18) 2814 /* Selects 2x oversampling for 720p and 1080i */ 2815 # define TV_OVERSAMPLE_2X (1 << 18) 2816 /* Selects no oversampling for 1080p */ 2817 # define TV_OVERSAMPLE_NONE (2 << 18) 2818 /* Selects 8x oversampling */ 2819 # define TV_OVERSAMPLE_8X (3 << 18) 2820 # define TV_OVERSAMPLE_MASK (3 << 18) 2821 /* Selects progressive mode rather than interlaced */ 2822 # define TV_PROGRESSIVE (1 << 17) 2823 /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */ 2824 # define TV_PAL_BURST (1 << 16) 2825 /* Field for setting delay of Y compared to C */ 2826 # define TV_YC_SKEW_MASK (7 << 12) 2827 /* Enables a fix for 480p/576p standard definition modes on the 915GM only */ 2828 # define TV_ENC_SDP_FIX (1 << 11) 2829 /* 2830 * Enables a fix for the 915GM only. 2831 * 2832 * Not sure what it does. 2833 */ 2834 # define TV_ENC_C0_FIX (1 << 10) 2835 /* Bits that must be preserved by software */ 2836 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) 2837 # define TV_FUSE_STATE_MASK (3 << 4) 2838 /* Read-only state that reports all features enabled */ 2839 # define TV_FUSE_STATE_ENABLED (0 << 4) 2840 /* Read-only state that reports that Macrovision is disabled in hardware*/ 2841 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4) 2842 /* Read-only state that reports that TV-out is disabled in hardware. */ 2843 # define TV_FUSE_STATE_DISABLED (2 << 4) 2844 /* Normal operation */ 2845 # define TV_TEST_MODE_NORMAL (0 << 0) 2846 /* Encoder test pattern 1 - combo pattern */ 2847 # define TV_TEST_MODE_PATTERN_1 (1 << 0) 2848 /* Encoder test pattern 2 - full screen vertical 75% color bars */ 2849 # define TV_TEST_MODE_PATTERN_2 (2 << 0) 2850 /* Encoder test pattern 3 - full screen horizontal 75% color bars */ 2851 # define TV_TEST_MODE_PATTERN_3 (3 << 0) 2852 /* Encoder test pattern 4 - random noise */ 2853 # define TV_TEST_MODE_PATTERN_4 (4 << 0) 2854 /* Encoder test pattern 5 - linear color ramps */ 2855 # define TV_TEST_MODE_PATTERN_5 (5 << 0) 2856 /* 2857 * This test mode forces the DACs to 50% of full output. 2858 * 2859 * This is used for load detection in combination with TVDAC_SENSE_MASK 2860 */ 2861 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0) 2862 # define TV_TEST_MODE_MASK (7 << 0) 2863 2864 #define TV_DAC _MMIO(0x68004) 2865 # define TV_DAC_SAVE 0x00ffff00 2866 /* 2867 * Reports that DAC state change logic has reported change (RO). 2868 * 2869 * This gets cleared when TV_DAC_STATE_EN is cleared 2870 */ 2871 # define TVDAC_STATE_CHG (1 << 31) 2872 # define TVDAC_SENSE_MASK (7 << 28) 2873 /* Reports that DAC A voltage is above the detect threshold */ 2874 # define TVDAC_A_SENSE (1 << 30) 2875 /* Reports that DAC B voltage is above the detect threshold */ 2876 # define TVDAC_B_SENSE (1 << 29) 2877 /* Reports that DAC C voltage is above the detect threshold */ 2878 # define TVDAC_C_SENSE (1 << 28) 2879 /* 2880 * Enables DAC state detection logic, for load-based TV detection. 2881 * 2882 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set 2883 * to off, for load detection to work. 2884 */ 2885 # define TVDAC_STATE_CHG_EN (1 << 27) 2886 /* Sets the DAC A sense value to high */ 2887 # define TVDAC_A_SENSE_CTL (1 << 26) 2888 /* Sets the DAC B sense value to high */ 2889 # define TVDAC_B_SENSE_CTL (1 << 25) 2890 /* Sets the DAC C sense value to high */ 2891 # define TVDAC_C_SENSE_CTL (1 << 24) 2892 /* Overrides the ENC_ENABLE and DAC voltage levels */ 2893 # define DAC_CTL_OVERRIDE (1 << 7) 2894 /* Sets the slew rate. Must be preserved in software */ 2895 # define ENC_TVDAC_SLEW_FAST (1 << 6) 2896 # define DAC_A_1_3_V (0 << 4) 2897 # define DAC_A_1_1_V (1 << 4) 2898 # define DAC_A_0_7_V (2 << 4) 2899 # define DAC_A_MASK (3 << 4) 2900 # define DAC_B_1_3_V (0 << 2) 2901 # define DAC_B_1_1_V (1 << 2) 2902 # define DAC_B_0_7_V (2 << 2) 2903 # define DAC_B_MASK (3 << 2) 2904 # define DAC_C_1_3_V (0 << 0) 2905 # define DAC_C_1_1_V (1 << 0) 2906 # define DAC_C_0_7_V (2 << 0) 2907 # define DAC_C_MASK (3 << 0) 2908 2909 /* 2910 * CSC coefficients are stored in a floating point format with 9 bits of 2911 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, 2912 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with 2913 * -1 (0x3) being the only legal negative value. 2914 */ 2915 #define TV_CSC_Y _MMIO(0x68010) 2916 # define TV_RY_MASK 0x07ff0000 2917 # define TV_RY_SHIFT 16 2918 # define TV_GY_MASK 0x00000fff 2919 # define TV_GY_SHIFT 0 2920 2921 #define TV_CSC_Y2 _MMIO(0x68014) 2922 # define TV_BY_MASK 0x07ff0000 2923 # define TV_BY_SHIFT 16 2924 /* 2925 * Y attenuation for component video. 2926 * 2927 * Stored in 1.9 fixed point. 2928 */ 2929 # define TV_AY_MASK 0x000003ff 2930 # define TV_AY_SHIFT 0 2931 2932 #define TV_CSC_U _MMIO(0x68018) 2933 # define TV_RU_MASK 0x07ff0000 2934 # define TV_RU_SHIFT 16 2935 # define TV_GU_MASK 0x000007ff 2936 # define TV_GU_SHIFT 0 2937 2938 #define TV_CSC_U2 _MMIO(0x6801c) 2939 # define TV_BU_MASK 0x07ff0000 2940 # define TV_BU_SHIFT 16 2941 /* 2942 * U attenuation for component video. 2943 * 2944 * Stored in 1.9 fixed point. 2945 */ 2946 # define TV_AU_MASK 0x000003ff 2947 # define TV_AU_SHIFT 0 2948 2949 #define TV_CSC_V _MMIO(0x68020) 2950 # define TV_RV_MASK 0x0fff0000 2951 # define TV_RV_SHIFT 16 2952 # define TV_GV_MASK 0x000007ff 2953 # define TV_GV_SHIFT 0 2954 2955 #define TV_CSC_V2 _MMIO(0x68024) 2956 # define TV_BV_MASK 0x07ff0000 2957 # define TV_BV_SHIFT 16 2958 /* 2959 * V attenuation for component video. 2960 * 2961 * Stored in 1.9 fixed point. 2962 */ 2963 # define TV_AV_MASK 0x000007ff 2964 # define TV_AV_SHIFT 0 2965 2966 #define TV_CLR_KNOBS _MMIO(0x68028) 2967 /* 2s-complement brightness adjustment */ 2968 # define TV_BRIGHTNESS_MASK 0xff000000 2969 # define TV_BRIGHTNESS_SHIFT 24 2970 /* Contrast adjustment, as a 2.6 unsigned floating point number */ 2971 # define TV_CONTRAST_MASK 0x00ff0000 2972 # define TV_CONTRAST_SHIFT 16 2973 /* Saturation adjustment, as a 2.6 unsigned floating point number */ 2974 # define TV_SATURATION_MASK 0x0000ff00 2975 # define TV_SATURATION_SHIFT 8 2976 /* Hue adjustment, as an integer phase angle in degrees */ 2977 # define TV_HUE_MASK 0x000000ff 2978 # define TV_HUE_SHIFT 0 2979 2980 #define TV_CLR_LEVEL _MMIO(0x6802c) 2981 /* Controls the DAC level for black */ 2982 # define TV_BLACK_LEVEL_MASK 0x01ff0000 2983 # define TV_BLACK_LEVEL_SHIFT 16 2984 /* Controls the DAC level for blanking */ 2985 # define TV_BLANK_LEVEL_MASK 0x000001ff 2986 # define TV_BLANK_LEVEL_SHIFT 0 2987 2988 #define TV_H_CTL_1 _MMIO(0x68030) 2989 /* Number of pixels in the hsync. */ 2990 # define TV_HSYNC_END_MASK 0x1fff0000 2991 # define TV_HSYNC_END_SHIFT 16 2992 /* Total number of pixels minus one in the line (display and blanking). */ 2993 # define TV_HTOTAL_MASK 0x00001fff 2994 # define TV_HTOTAL_SHIFT 0 2995 2996 #define TV_H_CTL_2 _MMIO(0x68034) 2997 /* Enables the colorburst (needed for non-component color) */ 2998 # define TV_BURST_ENA (1 << 31) 2999 /* Offset of the colorburst from the start of hsync, in pixels minus one. */ 3000 # define TV_HBURST_START_SHIFT 16 3001 # define TV_HBURST_START_MASK 0x1fff0000 3002 /* Length of the colorburst */ 3003 # define TV_HBURST_LEN_SHIFT 0 3004 # define TV_HBURST_LEN_MASK 0x0001fff 3005 3006 #define TV_H_CTL_3 _MMIO(0x68038) 3007 /* End of hblank, measured in pixels minus one from start of hsync */ 3008 # define TV_HBLANK_END_SHIFT 16 3009 # define TV_HBLANK_END_MASK 0x1fff0000 3010 /* Start of hblank, measured in pixels minus one from start of hsync */ 3011 # define TV_HBLANK_START_SHIFT 0 3012 # define TV_HBLANK_START_MASK 0x0001fff 3013 3014 #define TV_V_CTL_1 _MMIO(0x6803c) 3015 /* XXX */ 3016 # define TV_NBR_END_SHIFT 16 3017 # define TV_NBR_END_MASK 0x07ff0000 3018 /* XXX */ 3019 # define TV_VI_END_F1_SHIFT 8 3020 # define TV_VI_END_F1_MASK 0x00003f00 3021 /* XXX */ 3022 # define TV_VI_END_F2_SHIFT 0 3023 # define TV_VI_END_F2_MASK 0x0000003f 3024 3025 #define TV_V_CTL_2 _MMIO(0x68040) 3026 /* Length of vsync, in half lines */ 3027 # define TV_VSYNC_LEN_MASK 0x07ff0000 3028 # define TV_VSYNC_LEN_SHIFT 16 3029 /* Offset of the start of vsync in field 1, measured in one less than the 3030 * number of half lines. 3031 */ 3032 # define TV_VSYNC_START_F1_MASK 0x00007f00 3033 # define TV_VSYNC_START_F1_SHIFT 8 3034 /* 3035 * Offset of the start of vsync in field 2, measured in one less than the 3036 * number of half lines. 3037 */ 3038 # define TV_VSYNC_START_F2_MASK 0x0000007f 3039 # define TV_VSYNC_START_F2_SHIFT 0 3040 3041 #define TV_V_CTL_3 _MMIO(0x68044) 3042 /* Enables generation of the equalization signal */ 3043 # define TV_EQUAL_ENA (1 << 31) 3044 /* Length of vsync, in half lines */ 3045 # define TV_VEQ_LEN_MASK 0x007f0000 3046 # define TV_VEQ_LEN_SHIFT 16 3047 /* Offset of the start of equalization in field 1, measured in one less than 3048 * the number of half lines. 3049 */ 3050 # define TV_VEQ_START_F1_MASK 0x0007f00 3051 # define TV_VEQ_START_F1_SHIFT 8 3052 /* 3053 * Offset of the start of equalization in field 2, measured in one less than 3054 * the number of half lines. 3055 */ 3056 # define TV_VEQ_START_F2_MASK 0x000007f 3057 # define TV_VEQ_START_F2_SHIFT 0 3058 3059 #define TV_V_CTL_4 _MMIO(0x68048) 3060 /* 3061 * Offset to start of vertical colorburst, measured in one less than the 3062 * number of lines from vertical start. 3063 */ 3064 # define TV_VBURST_START_F1_MASK 0x003f0000 3065 # define TV_VBURST_START_F1_SHIFT 16 3066 /* 3067 * Offset to the end of vertical colorburst, measured in one less than the 3068 * number of lines from the start of NBR. 3069 */ 3070 # define TV_VBURST_END_F1_MASK 0x000000ff 3071 # define TV_VBURST_END_F1_SHIFT 0 3072 3073 #define TV_V_CTL_5 _MMIO(0x6804c) 3074 /* 3075 * Offset to start of vertical colorburst, measured in one less than the 3076 * number of lines from vertical start. 3077 */ 3078 # define TV_VBURST_START_F2_MASK 0x003f0000 3079 # define TV_VBURST_START_F2_SHIFT 16 3080 /* 3081 * Offset to the end of vertical colorburst, measured in one less than the 3082 * number of lines from the start of NBR. 3083 */ 3084 # define TV_VBURST_END_F2_MASK 0x000000ff 3085 # define TV_VBURST_END_F2_SHIFT 0 3086 3087 #define TV_V_CTL_6 _MMIO(0x68050) 3088 /* 3089 * Offset to start of vertical colorburst, measured in one less than the 3090 * number of lines from vertical start. 3091 */ 3092 # define TV_VBURST_START_F3_MASK 0x003f0000 3093 # define TV_VBURST_START_F3_SHIFT 16 3094 /* 3095 * Offset to the end of vertical colorburst, measured in one less than the 3096 * number of lines from the start of NBR. 3097 */ 3098 # define TV_VBURST_END_F3_MASK 0x000000ff 3099 # define TV_VBURST_END_F3_SHIFT 0 3100 3101 #define TV_V_CTL_7 _MMIO(0x68054) 3102 /* 3103 * Offset to start of vertical colorburst, measured in one less than the 3104 * number of lines from vertical start. 3105 */ 3106 # define TV_VBURST_START_F4_MASK 0x003f0000 3107 # define TV_VBURST_START_F4_SHIFT 16 3108 /* 3109 * Offset to the end of vertical colorburst, measured in one less than the 3110 * number of lines from the start of NBR. 3111 */ 3112 # define TV_VBURST_END_F4_MASK 0x000000ff 3113 # define TV_VBURST_END_F4_SHIFT 0 3114 3115 #define TV_SC_CTL_1 _MMIO(0x68060) 3116 /* Turns on the first subcarrier phase generation DDA */ 3117 # define TV_SC_DDA1_EN (1 << 31) 3118 /* Turns on the first subcarrier phase generation DDA */ 3119 # define TV_SC_DDA2_EN (1 << 30) 3120 /* Turns on the first subcarrier phase generation DDA */ 3121 # define TV_SC_DDA3_EN (1 << 29) 3122 /* Sets the subcarrier DDA to reset frequency every other field */ 3123 # define TV_SC_RESET_EVERY_2 (0 << 24) 3124 /* Sets the subcarrier DDA to reset frequency every fourth field */ 3125 # define TV_SC_RESET_EVERY_4 (1 << 24) 3126 /* Sets the subcarrier DDA to reset frequency every eighth field */ 3127 # define TV_SC_RESET_EVERY_8 (2 << 24) 3128 /* Sets the subcarrier DDA to never reset the frequency */ 3129 # define TV_SC_RESET_NEVER (3 << 24) 3130 /* Sets the peak amplitude of the colorburst.*/ 3131 # define TV_BURST_LEVEL_MASK 0x00ff0000 3132 # define TV_BURST_LEVEL_SHIFT 16 3133 /* Sets the increment of the first subcarrier phase generation DDA */ 3134 # define TV_SCDDA1_INC_MASK 0x00000fff 3135 # define TV_SCDDA1_INC_SHIFT 0 3136 3137 #define TV_SC_CTL_2 _MMIO(0x68064) 3138 /* Sets the rollover for the second subcarrier phase generation DDA */ 3139 # define TV_SCDDA2_SIZE_MASK 0x7fff0000 3140 # define TV_SCDDA2_SIZE_SHIFT 16 3141 /* Sets the increent of the second subcarrier phase generation DDA */ 3142 # define TV_SCDDA2_INC_MASK 0x00007fff 3143 # define TV_SCDDA2_INC_SHIFT 0 3144 3145 #define TV_SC_CTL_3 _MMIO(0x68068) 3146 /* Sets the rollover for the third subcarrier phase generation DDA */ 3147 # define TV_SCDDA3_SIZE_MASK 0x7fff0000 3148 # define TV_SCDDA3_SIZE_SHIFT 16 3149 /* Sets the increent of the third subcarrier phase generation DDA */ 3150 # define TV_SCDDA3_INC_MASK 0x00007fff 3151 # define TV_SCDDA3_INC_SHIFT 0 3152 3153 #define TV_WIN_POS _MMIO(0x68070) 3154 /* X coordinate of the display from the start of horizontal active */ 3155 # define TV_XPOS_MASK 0x1fff0000 3156 # define TV_XPOS_SHIFT 16 3157 /* Y coordinate of the display from the start of vertical active (NBR) */ 3158 # define TV_YPOS_MASK 0x00000fff 3159 # define TV_YPOS_SHIFT 0 3160 3161 #define TV_WIN_SIZE _MMIO(0x68074) 3162 /* Horizontal size of the display window, measured in pixels*/ 3163 # define TV_XSIZE_MASK 0x1fff0000 3164 # define TV_XSIZE_SHIFT 16 3165 /* 3166 * Vertical size of the display window, measured in pixels. 3167 * 3168 * Must be even for interlaced modes. 3169 */ 3170 # define TV_YSIZE_MASK 0x00000fff 3171 # define TV_YSIZE_SHIFT 0 3172 3173 #define TV_FILTER_CTL_1 _MMIO(0x68080) 3174 /* 3175 * Enables automatic scaling calculation. 3176 * 3177 * If set, the rest of the registers are ignored, and the calculated values can 3178 * be read back from the register. 3179 */ 3180 # define TV_AUTO_SCALE (1 << 31) 3181 /* 3182 * Disables the vertical filter. 3183 * 3184 * This is required on modes more than 1024 pixels wide */ 3185 # define TV_V_FILTER_BYPASS (1 << 29) 3186 /* Enables adaptive vertical filtering */ 3187 # define TV_VADAPT (1 << 28) 3188 # define TV_VADAPT_MODE_MASK (3 << 26) 3189 /* Selects the least adaptive vertical filtering mode */ 3190 # define TV_VADAPT_MODE_LEAST (0 << 26) 3191 /* Selects the moderately adaptive vertical filtering mode */ 3192 # define TV_VADAPT_MODE_MODERATE (1 << 26) 3193 /* Selects the most adaptive vertical filtering mode */ 3194 # define TV_VADAPT_MODE_MOST (3 << 26) 3195 /* 3196 * Sets the horizontal scaling factor. 3197 * 3198 * This should be the fractional part of the horizontal scaling factor divided 3199 * by the oversampling rate. TV_HSCALE should be less than 1, and set to: 3200 * 3201 * (src width - 1) / ((oversample * dest width) - 1) 3202 */ 3203 # define TV_HSCALE_FRAC_MASK 0x00003fff 3204 # define TV_HSCALE_FRAC_SHIFT 0 3205 3206 #define TV_FILTER_CTL_2 _MMIO(0x68084) 3207 /* 3208 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 3209 * 3210 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) 3211 */ 3212 # define TV_VSCALE_INT_MASK 0x00038000 3213 # define TV_VSCALE_INT_SHIFT 15 3214 /* 3215 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 3216 * 3217 * \sa TV_VSCALE_INT_MASK 3218 */ 3219 # define TV_VSCALE_FRAC_MASK 0x00007fff 3220 # define TV_VSCALE_FRAC_SHIFT 0 3221 3222 #define TV_FILTER_CTL_3 _MMIO(0x68088) 3223 /* 3224 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 3225 * 3226 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) 3227 * 3228 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 3229 */ 3230 # define TV_VSCALE_IP_INT_MASK 0x00038000 3231 # define TV_VSCALE_IP_INT_SHIFT 15 3232 /* 3233 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 3234 * 3235 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 3236 * 3237 * \sa TV_VSCALE_IP_INT_MASK 3238 */ 3239 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff 3240 # define TV_VSCALE_IP_FRAC_SHIFT 0 3241 3242 #define TV_CC_CONTROL _MMIO(0x68090) 3243 # define TV_CC_ENABLE (1 << 31) 3244 /* 3245 * Specifies which field to send the CC data in. 3246 * 3247 * CC data is usually sent in field 0. 3248 */ 3249 # define TV_CC_FID_MASK (1 << 27) 3250 # define TV_CC_FID_SHIFT 27 3251 /* Sets the horizontal position of the CC data. Usually 135. */ 3252 # define TV_CC_HOFF_MASK 0x03ff0000 3253 # define TV_CC_HOFF_SHIFT 16 3254 /* Sets the vertical position of the CC data. Usually 21 */ 3255 # define TV_CC_LINE_MASK 0x0000003f 3256 # define TV_CC_LINE_SHIFT 0 3257 3258 #define TV_CC_DATA _MMIO(0x68094) 3259 # define TV_CC_RDY (1 << 31) 3260 /* Second word of CC data to be transmitted. */ 3261 # define TV_CC_DATA_2_MASK 0x007f0000 3262 # define TV_CC_DATA_2_SHIFT 16 3263 /* First word of CC data to be transmitted. */ 3264 # define TV_CC_DATA_1_MASK 0x0000007f 3265 # define TV_CC_DATA_1_SHIFT 0 3266 3267 #define TV_H_LUMA(i) _MMIO(0x68100 + (i) * 4) /* 60 registers */ 3268 #define TV_H_CHROMA(i) _MMIO(0x68200 + (i) * 4) /* 60 registers */ 3269 #define TV_V_LUMA(i) _MMIO(0x68300 + (i) * 4) /* 43 registers */ 3270 #define TV_V_CHROMA(i) _MMIO(0x68400 + (i) * 4) /* 43 registers */ 3271 3272 /* Display Port */ 3273 #define DP_A _MMIO(0x64000) /* eDP */ 3274 #define DP_B _MMIO(0x64100) 3275 #define DP_C _MMIO(0x64200) 3276 #define DP_D _MMIO(0x64300) 3277 3278 #define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100) 3279 #define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200) 3280 #define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300) 3281 3282 #define DP_PORT_EN (1 << 31) 3283 #define DP_PIPE_SEL_SHIFT 30 3284 #define DP_PIPE_SEL_MASK (1 << 30) 3285 #define DP_PIPE_SEL(pipe) ((pipe) << 30) 3286 #define DP_PIPE_SEL_SHIFT_IVB 29 3287 #define DP_PIPE_SEL_MASK_IVB (3 << 29) 3288 #define DP_PIPE_SEL_IVB(pipe) ((pipe) << 29) 3289 #define DP_PIPE_SEL_SHIFT_CHV 16 3290 #define DP_PIPE_SEL_MASK_CHV (3 << 16) 3291 #define DP_PIPE_SEL_CHV(pipe) ((pipe) << 16) 3292 3293 /* Link training mode - select a suitable mode for each stage */ 3294 #define DP_LINK_TRAIN_PAT_1 (0 << 28) 3295 #define DP_LINK_TRAIN_PAT_2 (1 << 28) 3296 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) 3297 #define DP_LINK_TRAIN_OFF (3 << 28) 3298 #define DP_LINK_TRAIN_MASK (3 << 28) 3299 #define DP_LINK_TRAIN_SHIFT 28 3300 3301 /* CPT Link training mode */ 3302 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) 3303 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) 3304 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) 3305 #define DP_LINK_TRAIN_OFF_CPT (3 << 8) 3306 #define DP_LINK_TRAIN_MASK_CPT (7 << 8) 3307 #define DP_LINK_TRAIN_SHIFT_CPT 8 3308 3309 /* Signal voltages. These are mostly controlled by the other end */ 3310 #define DP_VOLTAGE_0_4 (0 << 25) 3311 #define DP_VOLTAGE_0_6 (1 << 25) 3312 #define DP_VOLTAGE_0_8 (2 << 25) 3313 #define DP_VOLTAGE_1_2 (3 << 25) 3314 #define DP_VOLTAGE_MASK (7 << 25) 3315 #define DP_VOLTAGE_SHIFT 25 3316 3317 /* Signal pre-emphasis levels, like voltages, the other end tells us what 3318 * they want 3319 */ 3320 #define DP_PRE_EMPHASIS_0 (0 << 22) 3321 #define DP_PRE_EMPHASIS_3_5 (1 << 22) 3322 #define DP_PRE_EMPHASIS_6 (2 << 22) 3323 #define DP_PRE_EMPHASIS_9_5 (3 << 22) 3324 #define DP_PRE_EMPHASIS_MASK (7 << 22) 3325 #define DP_PRE_EMPHASIS_SHIFT 22 3326 3327 /* How many wires to use. I guess 3 was too hard */ 3328 #define DP_PORT_WIDTH(width) (((width) - 1) << 19) 3329 #define DP_PORT_WIDTH_MASK (7 << 19) 3330 #define DP_PORT_WIDTH_SHIFT 19 3331 3332 /* Mystic DPCD version 1.1 special mode */ 3333 #define DP_ENHANCED_FRAMING (1 << 18) 3334 3335 /* eDP */ 3336 #define DP_PLL_FREQ_270MHZ (0 << 16) 3337 #define DP_PLL_FREQ_162MHZ (1 << 16) 3338 #define DP_PLL_FREQ_MASK (3 << 16) 3339 3340 /* locked once port is enabled */ 3341 #define DP_PORT_REVERSAL (1 << 15) 3342 3343 /* eDP */ 3344 #define DP_PLL_ENABLE (1 << 14) 3345 3346 /* sends the clock on lane 15 of the PEG for debug */ 3347 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) 3348 3349 #define DP_SCRAMBLING_DISABLE (1 << 12) 3350 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) 3351 3352 /* limit RGB values to avoid confusing TVs */ 3353 #define DP_COLOR_RANGE_16_235 (1 << 8) 3354 3355 /* Turn on the audio link */ 3356 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) 3357 3358 /* vs and hs sync polarity */ 3359 #define DP_SYNC_VS_HIGH (1 << 4) 3360 #define DP_SYNC_HS_HIGH (1 << 3) 3361 3362 /* A fantasy */ 3363 #define DP_DETECTED (1 << 2) 3364 3365 /* The aux channel provides a way to talk to the 3366 * signal sink for DDC etc. Max packet size supported 3367 * is 20 bytes in each direction, hence the 5 fixed 3368 * data registers 3369 */ 3370 #define _DPA_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64010) 3371 #define _DPA_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64014) 3372 3373 #define _DPB_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64110) 3374 #define _DPB_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64114) 3375 3376 #define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL) 3377 #define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ 3378 3379 #define _XELPDP_USBC1_AUX_CH_CTL 0x16F210 3380 #define _XELPDP_USBC2_AUX_CH_CTL 0x16F410 3381 #define _XELPDP_USBC3_AUX_CH_CTL 0x16F610 3382 #define _XELPDP_USBC4_AUX_CH_CTL 0x16F810 3383 3384 #define XELPDP_DP_AUX_CH_CTL(aux_ch) _MMIO(_PICK(aux_ch, \ 3385 _DPA_AUX_CH_CTL, \ 3386 _DPB_AUX_CH_CTL, \ 3387 0, /* port/aux_ch C is non-existent */ \ 3388 _XELPDP_USBC1_AUX_CH_CTL, \ 3389 _XELPDP_USBC2_AUX_CH_CTL, \ 3390 _XELPDP_USBC3_AUX_CH_CTL, \ 3391 _XELPDP_USBC4_AUX_CH_CTL)) 3392 3393 #define _XELPDP_USBC1_AUX_CH_DATA1 0x16F214 3394 #define _XELPDP_USBC2_AUX_CH_DATA1 0x16F414 3395 #define _XELPDP_USBC3_AUX_CH_DATA1 0x16F614 3396 #define _XELPDP_USBC4_AUX_CH_DATA1 0x16F814 3397 3398 #define XELPDP_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PICK(aux_ch, \ 3399 _DPA_AUX_CH_DATA1, \ 3400 _DPB_AUX_CH_DATA1, \ 3401 0, /* port/aux_ch C is non-existent */ \ 3402 _XELPDP_USBC1_AUX_CH_DATA1, \ 3403 _XELPDP_USBC2_AUX_CH_DATA1, \ 3404 _XELPDP_USBC3_AUX_CH_DATA1, \ 3405 _XELPDP_USBC4_AUX_CH_DATA1) + (i) * 4) 3406 3407 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) 3408 #define DP_AUX_CH_CTL_DONE (1 << 30) 3409 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) 3410 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) 3411 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) 3412 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) 3413 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) 3414 #define DP_AUX_CH_CTL_TIME_OUT_MAX (3 << 26) /* Varies per platform */ 3415 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) 3416 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) 3417 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) 3418 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 3419 #define XELPDP_DP_AUX_CH_CTL_POWER_REQUEST REG_BIT(19) 3420 #define XELPDP_DP_AUX_CH_CTL_POWER_STATUS REG_BIT(18) 3421 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) 3422 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 3423 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) 3424 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) 3425 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) 3426 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) 3427 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) 3428 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) 3429 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 3430 #define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14) 3431 #define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13) 3432 #define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12) 3433 #define DP_AUX_CH_CTL_TBT_IO (1 << 11) 3434 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5) 3435 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5) 3436 #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1) 3437 3438 /* 3439 * Computing GMCH M and N values for the Display Port link 3440 * 3441 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes 3442 * 3443 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) 3444 * 3445 * The GMCH value is used internally 3446 * 3447 * bytes_per_pixel is the number of bytes coming out of the plane, 3448 * which is after the LUTs, so we want the bytes for our color format. 3449 * For our current usage, this is always 3, one byte for R, G and B. 3450 */ 3451 #define _PIPEA_DATA_M_G4X 0x70050 3452 #define _PIPEB_DATA_M_G4X 0x71050 3453 3454 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ 3455 #define TU_SIZE_MASK REG_GENMASK(30, 25) 3456 #define TU_SIZE(x) REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /* default size 64 */ 3457 3458 #define DATA_LINK_M_N_MASK REG_GENMASK(23, 0) 3459 #define DATA_LINK_N_MAX (0x800000) 3460 3461 #define _PIPEA_DATA_N_G4X 0x70054 3462 #define _PIPEB_DATA_N_G4X 0x71054 3463 3464 /* 3465 * Computing Link M and N values for the Display Port link 3466 * 3467 * Link M / N = pixel_clock / ls_clk 3468 * 3469 * (the DP spec calls pixel_clock the 'strm_clk') 3470 * 3471 * The Link value is transmitted in the Main Stream 3472 * Attributes and VB-ID. 3473 */ 3474 3475 #define _PIPEA_LINK_M_G4X 0x70060 3476 #define _PIPEB_LINK_M_G4X 0x71060 3477 #define _PIPEA_LINK_N_G4X 0x70064 3478 #define _PIPEB_LINK_N_G4X 0x71064 3479 3480 #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X) 3481 #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X) 3482 #define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X) 3483 #define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X) 3484 3485 /* Display & cursor control */ 3486 3487 /* Pipe A */ 3488 #define _PIPEADSL 0x70000 3489 #define PIPEDSL_CURR_FIELD REG_BIT(31) /* ctg+ */ 3490 #define PIPEDSL_LINE_MASK REG_GENMASK(19, 0) 3491 #define _PIPEACONF 0x70008 3492 #define PIPECONF_ENABLE REG_BIT(31) 3493 #define PIPECONF_DOUBLE_WIDE REG_BIT(30) /* pre-i965 */ 3494 #define PIPECONF_STATE_ENABLE REG_BIT(30) /* i965+ */ 3495 #define PIPECONF_DSI_PLL_LOCKED REG_BIT(29) /* vlv & pipe A only */ 3496 #define PIPECONF_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* pre-hsw */ 3497 #define PIPECONF_FRAME_START_DELAY(x) REG_FIELD_PREP(PIPECONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */ 3498 #define PIPECONF_PIPE_LOCKED REG_BIT(25) 3499 #define PIPECONF_FORCE_BORDER REG_BIT(25) 3500 #define PIPECONF_GAMMA_MODE_MASK_I9XX REG_BIT(24) /* gmch */ 3501 #define PIPECONF_GAMMA_MODE_MASK_ILK REG_GENMASK(25, 24) /* ilk-ivb */ 3502 #define PIPECONF_GAMMA_MODE_8BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK, 0) 3503 #define PIPECONF_GAMMA_MODE_10BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK, 1) 3504 #define PIPECONF_GAMMA_MODE_12BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */ 3505 #define PIPECONF_GAMMA_MODE_SPLIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */ 3506 #define PIPECONF_GAMMA_MODE(x) REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, (x)) /* pass in GAMMA_MODE_MODE_* */ 3507 #define PIPECONF_INTERLACE_MASK REG_GENMASK(23, 21) /* gen3+ */ 3508 #define PIPECONF_INTERLACE_PROGRESSIVE REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 0) 3509 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 4) /* gen4 only */ 3510 #define PIPECONF_INTERLACE_W_SYNC_SHIFT REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 5) /* gen4 only */ 3511 #define PIPECONF_INTERLACE_W_FIELD_INDICATION REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 6) 3512 #define PIPECONF_INTERLACE_FIELD_0_ONLY REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 7) /* gen3 only */ 3513 /* 3514 * ilk+: PF/D=progressive fetch/display, IF/D=interlaced fetch/display, 3515 * DBL=power saving pixel doubling, PF-ID* requires panel fitter 3516 */ 3517 #define PIPECONF_INTERLACE_MASK_ILK REG_GENMASK(23, 21) /* ilk+ */ 3518 #define PIPECONF_INTERLACE_MASK_HSW REG_GENMASK(22, 21) /* hsw+ */ 3519 #define PIPECONF_INTERLACE_PF_PD_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 0) 3520 #define PIPECONF_INTERLACE_PF_ID_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 1) 3521 #define PIPECONF_INTERLACE_IF_ID_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 3) 3522 #define PIPECONF_INTERLACE_IF_ID_DBL_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */ 3523 #define PIPECONF_INTERLACE_PF_ID_DBL_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */ 3524 #define PIPECONF_REFRESH_RATE_ALT_ILK REG_BIT(20) 3525 #define PIPECONF_MSA_TIMING_DELAY_MASK REG_GENMASK(19, 18) /* ilk/snb/ivb */ 3526 #define PIPECONF_MSA_TIMING_DELAY(x) REG_FIELD_PREP(PIPECONF_MSA_TIMING_DELAY_MASK, (x)) 3527 #define PIPECONF_CXSR_DOWNCLOCK REG_BIT(16) 3528 #define PIPECONF_REFRESH_RATE_ALT_VLV REG_BIT(14) 3529 #define PIPECONF_COLOR_RANGE_SELECT REG_BIT(13) 3530 #define PIPECONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /* ilk-ivb */ 3531 #define PIPECONF_OUTPUT_COLORSPACE_RGB REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */ 3532 #define PIPECONF_OUTPUT_COLORSPACE_YUV601 REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */ 3533 #define PIPECONF_OUTPUT_COLORSPACE_YUV709 REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */ 3534 #define PIPECONF_OUTPUT_COLORSPACE_YUV_HSW REG_BIT(11) /* hsw only */ 3535 #define PIPECONF_BPC_MASK REG_GENMASK(7, 5) /* ctg-ivb */ 3536 #define PIPECONF_BPC_8 REG_FIELD_PREP(PIPECONF_BPC_MASK, 0) 3537 #define PIPECONF_BPC_10 REG_FIELD_PREP(PIPECONF_BPC_MASK, 1) 3538 #define PIPECONF_BPC_6 REG_FIELD_PREP(PIPECONF_BPC_MASK, 2) 3539 #define PIPECONF_BPC_12 REG_FIELD_PREP(PIPECONF_BPC_MASK, 3) 3540 #define PIPECONF_DITHER_EN REG_BIT(4) 3541 #define PIPECONF_DITHER_TYPE_MASK REG_GENMASK(3, 2) 3542 #define PIPECONF_DITHER_TYPE_SP REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 0) 3543 #define PIPECONF_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 1) 3544 #define PIPECONF_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 2) 3545 #define PIPECONF_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 3) 3546 #define _PIPEASTAT 0x70024 3547 #define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31) 3548 #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30) 3549 #define PIPE_CRC_ERROR_ENABLE (1UL << 29) 3550 #define PIPE_CRC_DONE_ENABLE (1UL << 28) 3551 #define PERF_COUNTER2_INTERRUPT_EN (1UL << 27) 3552 #define PIPE_GMBUS_EVENT_ENABLE (1UL << 27) 3553 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL << 26) 3554 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26) 3555 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25) 3556 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24) 3557 #define PIPE_DPST_EVENT_ENABLE (1UL << 23) 3558 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22) 3559 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22) 3560 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21) 3561 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL << 20) 3562 #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL << 19) 3563 #define PERF_COUNTER_INTERRUPT_EN (1UL << 19) 3564 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */ 3565 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18) /* 965 or later */ 3566 #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL << 17) 3567 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17) 3568 #define PIPEA_HBLANK_INT_EN_VLV (1UL << 16) 3569 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL << 16) 3570 #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL << 15) 3571 #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL << 14) 3572 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL << 13) 3573 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL << 12) 3574 #define PERF_COUNTER2_INTERRUPT_STATUS (1UL << 11) 3575 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL << 11) 3576 #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL << 10) 3577 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10) 3578 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9) 3579 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8) 3580 #define PIPE_DPST_EVENT_STATUS (1UL << 7) 3581 #define PIPE_A_PSR_STATUS_VLV (1UL << 6) 3582 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6) 3583 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5) 3584 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL << 4) 3585 #define PIPE_B_PSR_STATUS_VLV (1UL << 3) 3586 #define PERF_COUNTER_INTERRUPT_STATUS (1UL << 3) 3587 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */ 3588 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2) /* 965 or later */ 3589 #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL << 1) 3590 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1) 3591 #define PIPE_HBLANK_INT_STATUS (1UL << 0) 3592 #define PIPE_OVERLAY_UPDATED_STATUS (1UL << 0) 3593 3594 #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000 3595 #define PIPESTAT_INT_STATUS_MASK 0x0000ffff 3596 3597 #define PIPE_A_OFFSET 0x70000 3598 #define PIPE_B_OFFSET 0x71000 3599 #define PIPE_C_OFFSET 0x72000 3600 #define PIPE_D_OFFSET 0x73000 3601 #define CHV_PIPE_C_OFFSET 0x74000 3602 /* 3603 * There's actually no pipe EDP. Some pipe registers have 3604 * simply shifted from the pipe to the transcoder, while 3605 * keeping their original offset. Thus we need PIPE_EDP_OFFSET 3606 * to access such registers in transcoder EDP. 3607 */ 3608 #define PIPE_EDP_OFFSET 0x7f000 3609 3610 /* ICL DSI 0 and 1 */ 3611 #define PIPE_DSI0_OFFSET 0x7b000 3612 #define PIPE_DSI1_OFFSET 0x7b800 3613 3614 #define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF) 3615 #define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL) 3616 #define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH) 3617 #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL) 3618 #define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT) 3619 3620 #define _PIPEAGCMAX 0x70010 3621 #define _PIPEBGCMAX 0x71010 3622 #define PIPEGCMAX(pipe, i) _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4) /* u1.16 */ 3623 3624 #define _PIPE_ARB_CTL_A 0x70028 /* icl+ */ 3625 #define PIPE_ARB_CTL(pipe) _MMIO_PIPE2(pipe, _PIPE_ARB_CTL_A) 3626 #define PIPE_ARB_USE_PROG_SLOTS REG_BIT(13) 3627 3628 #define _PIPE_MISC_A 0x70030 3629 #define _PIPE_MISC_B 0x71030 3630 #define PIPEMISC_YUV420_ENABLE REG_BIT(27) /* glk+ */ 3631 #define PIPEMISC_YUV420_MODE_FULL_BLEND REG_BIT(26) /* glk+ */ 3632 #define PIPEMISC_HDR_MODE_PRECISION REG_BIT(23) /* icl+ */ 3633 #define PIPEMISC_OUTPUT_COLORSPACE_YUV REG_BIT(11) 3634 #define PIPEMISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */ 3635 /* 3636 * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with 3637 * valid values of: 6, 8, 10 BPC. 3638 * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of: 3639 * 6, 8, 10, 12 BPC. 3640 */ 3641 #define PIPEMISC_BPC_MASK REG_GENMASK(7, 5) 3642 #define PIPEMISC_BPC_8 REG_FIELD_PREP(PIPEMISC_BPC_MASK, 0) 3643 #define PIPEMISC_BPC_10 REG_FIELD_PREP(PIPEMISC_BPC_MASK, 1) 3644 #define PIPEMISC_BPC_6 REG_FIELD_PREP(PIPEMISC_BPC_MASK, 2) 3645 #define PIPEMISC_BPC_12_ADLP REG_FIELD_PREP(PIPEMISC_BPC_MASK, 4) /* adlp+ */ 3646 #define PIPEMISC_DITHER_ENABLE REG_BIT(4) 3647 #define PIPEMISC_DITHER_TYPE_MASK REG_GENMASK(3, 2) 3648 #define PIPEMISC_DITHER_TYPE_SP REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 0) 3649 #define PIPEMISC_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 1) 3650 #define PIPEMISC_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 2) 3651 #define PIPEMISC_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 3) 3652 #define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A) 3653 3654 #define _PIPE_MISC2_A 0x7002C 3655 #define _PIPE_MISC2_B 0x7102C 3656 #define PIPE_MISC2_BUBBLE_COUNTER_MASK REG_GENMASK(31, 24) 3657 #define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 80) 3658 #define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 20) 3659 #define PIPE_MISC2(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC2_A) 3660 3661 /* Skylake+ pipe bottom (background) color */ 3662 #define _SKL_BOTTOM_COLOR_A 0x70034 3663 #define _SKL_BOTTOM_COLOR_B 0x71034 3664 #define SKL_BOTTOM_COLOR_GAMMA_ENABLE REG_BIT(31) 3665 #define SKL_BOTTOM_COLOR_CSC_ENABLE REG_BIT(30) 3666 #define SKL_BOTTOM_COLOR(pipe) _MMIO_PIPE(pipe, _SKL_BOTTOM_COLOR_A, _SKL_BOTTOM_COLOR_B) 3667 3668 #define _ICL_PIPE_A_STATUS 0x70058 3669 #define ICL_PIPESTATUS(pipe) _MMIO_PIPE2(pipe, _ICL_PIPE_A_STATUS) 3670 #define PIPE_STATUS_UNDERRUN REG_BIT(31) 3671 #define PIPE_STATUS_SOFT_UNDERRUN_XELPD REG_BIT(28) 3672 #define PIPE_STATUS_HARD_UNDERRUN_XELPD REG_BIT(27) 3673 #define PIPE_STATUS_PORT_UNDERRUN_XELPD REG_BIT(26) 3674 3675 #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028) 3676 #define PIPEB_LINE_COMPARE_INT_EN REG_BIT(29) 3677 #define PIPEB_HLINE_INT_EN REG_BIT(28) 3678 #define PIPEB_VBLANK_INT_EN REG_BIT(27) 3679 #define SPRITED_FLIP_DONE_INT_EN REG_BIT(26) 3680 #define SPRITEC_FLIP_DONE_INT_EN REG_BIT(25) 3681 #define PLANEB_FLIP_DONE_INT_EN REG_BIT(24) 3682 #define PIPE_PSR_INT_EN REG_BIT(22) 3683 #define PIPEA_LINE_COMPARE_INT_EN REG_BIT(21) 3684 #define PIPEA_HLINE_INT_EN REG_BIT(20) 3685 #define PIPEA_VBLANK_INT_EN REG_BIT(19) 3686 #define SPRITEB_FLIP_DONE_INT_EN REG_BIT(18) 3687 #define SPRITEA_FLIP_DONE_INT_EN REG_BIT(17) 3688 #define PLANEA_FLIPDONE_INT_EN REG_BIT(16) 3689 #define PIPEC_LINE_COMPARE_INT_EN REG_BIT(13) 3690 #define PIPEC_HLINE_INT_EN REG_BIT(12) 3691 #define PIPEC_VBLANK_INT_EN REG_BIT(11) 3692 #define SPRITEF_FLIPDONE_INT_EN REG_BIT(10) 3693 #define SPRITEE_FLIPDONE_INT_EN REG_BIT(9) 3694 #define PLANEC_FLIPDONE_INT_EN REG_BIT(8) 3695 3696 #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */ 3697 #define DPINVGTT_EN_MASK_CHV REG_GENMASK(27, 16) 3698 #define DPINVGTT_EN_MASK_VLV REG_GENMASK(23, 16) 3699 #define SPRITEF_INVALID_GTT_INT_EN REG_BIT(27) 3700 #define SPRITEE_INVALID_GTT_INT_EN REG_BIT(26) 3701 #define PLANEC_INVALID_GTT_INT_EN REG_BIT(25) 3702 #define CURSORC_INVALID_GTT_INT_EN REG_BIT(24) 3703 #define CURSORB_INVALID_GTT_INT_EN REG_BIT(23) 3704 #define CURSORA_INVALID_GTT_INT_EN REG_BIT(22) 3705 #define SPRITED_INVALID_GTT_INT_EN REG_BIT(21) 3706 #define SPRITEC_INVALID_GTT_INT_EN REG_BIT(20) 3707 #define PLANEB_INVALID_GTT_INT_EN REG_BIT(19) 3708 #define SPRITEB_INVALID_GTT_INT_EN REG_BIT(18) 3709 #define SPRITEA_INVALID_GTT_INT_EN REG_BIT(17) 3710 #define PLANEA_INVALID_GTT_INT_EN REG_BIT(16) 3711 #define DPINVGTT_STATUS_MASK_CHV REG_GENMASK(11, 0) 3712 #define DPINVGTT_STATUS_MASK_VLV REG_GENMASK(7, 0) 3713 #define SPRITEF_INVALID_GTT_STATUS REG_BIT(11) 3714 #define SPRITEE_INVALID_GTT_STATUS REG_BIT(10) 3715 #define PLANEC_INVALID_GTT_STATUS REG_BIT(9) 3716 #define CURSORC_INVALID_GTT_STATUS REG_BIT(8) 3717 #define CURSORB_INVALID_GTT_STATUS REG_BIT(7) 3718 #define CURSORA_INVALID_GTT_STATUS REG_BIT(6) 3719 #define SPRITED_INVALID_GTT_STATUS REG_BIT(5) 3720 #define SPRITEC_INVALID_GTT_STATUS REG_BIT(4) 3721 #define PLANEB_INVALID_GTT_STATUS REG_BIT(3) 3722 #define SPRITEB_INVALID_GTT_STATUS REG_BIT(2) 3723 #define SPRITEA_INVALID_GTT_STATUS REG_BIT(1) 3724 #define PLANEA_INVALID_GTT_STATUS REG_BIT(0) 3725 3726 #define DSPARB _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030) 3727 #define DSPARB_CSTART_MASK (0x7f << 7) 3728 #define DSPARB_CSTART_SHIFT 7 3729 #define DSPARB_BSTART_MASK (0x7f) 3730 #define DSPARB_BSTART_SHIFT 0 3731 #define DSPARB_BEND_SHIFT 9 /* on 855 */ 3732 #define DSPARB_AEND_SHIFT 0 3733 #define DSPARB_SPRITEA_SHIFT_VLV 0 3734 #define DSPARB_SPRITEA_MASK_VLV (0xff << 0) 3735 #define DSPARB_SPRITEB_SHIFT_VLV 8 3736 #define DSPARB_SPRITEB_MASK_VLV (0xff << 8) 3737 #define DSPARB_SPRITEC_SHIFT_VLV 16 3738 #define DSPARB_SPRITEC_MASK_VLV (0xff << 16) 3739 #define DSPARB_SPRITED_SHIFT_VLV 24 3740 #define DSPARB_SPRITED_MASK_VLV (0xff << 24) 3741 #define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */ 3742 #define DSPARB_SPRITEA_HI_SHIFT_VLV 0 3743 #define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0) 3744 #define DSPARB_SPRITEB_HI_SHIFT_VLV 4 3745 #define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4) 3746 #define DSPARB_SPRITEC_HI_SHIFT_VLV 8 3747 #define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8) 3748 #define DSPARB_SPRITED_HI_SHIFT_VLV 12 3749 #define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12) 3750 #define DSPARB_SPRITEE_HI_SHIFT_VLV 16 3751 #define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16) 3752 #define DSPARB_SPRITEF_HI_SHIFT_VLV 20 3753 #define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20) 3754 #define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */ 3755 #define DSPARB_SPRITEE_SHIFT_VLV 0 3756 #define DSPARB_SPRITEE_MASK_VLV (0xff << 0) 3757 #define DSPARB_SPRITEF_SHIFT_VLV 8 3758 #define DSPARB_SPRITEF_MASK_VLV (0xff << 8) 3759 3760 /* pnv/gen4/g4x/vlv/chv */ 3761 #define DSPFW1 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034) 3762 #define DSPFW_SR_SHIFT 23 3763 #define DSPFW_SR_MASK (0x1ff << 23) 3764 #define DSPFW_CURSORB_SHIFT 16 3765 #define DSPFW_CURSORB_MASK (0x3f << 16) 3766 #define DSPFW_PLANEB_SHIFT 8 3767 #define DSPFW_PLANEB_MASK (0x7f << 8) 3768 #define DSPFW_PLANEB_MASK_VLV (0xff << 8) /* vlv/chv */ 3769 #define DSPFW_PLANEA_SHIFT 0 3770 #define DSPFW_PLANEA_MASK (0x7f << 0) 3771 #define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */ 3772 #define DSPFW2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038) 3773 #define DSPFW_FBC_SR_EN (1 << 31) /* g4x */ 3774 #define DSPFW_FBC_SR_SHIFT 28 3775 #define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */ 3776 #define DSPFW_FBC_HPLL_SR_SHIFT 24 3777 #define DSPFW_FBC_HPLL_SR_MASK (0xf << 24) /* g4x */ 3778 #define DSPFW_SPRITEB_SHIFT (16) 3779 #define DSPFW_SPRITEB_MASK (0x7f << 16) /* g4x */ 3780 #define DSPFW_SPRITEB_MASK_VLV (0xff << 16) /* vlv/chv */ 3781 #define DSPFW_CURSORA_SHIFT 8 3782 #define DSPFW_CURSORA_MASK (0x3f << 8) 3783 #define DSPFW_PLANEC_OLD_SHIFT 0 3784 #define DSPFW_PLANEC_OLD_MASK (0x7f << 0) /* pre-gen4 sprite C */ 3785 #define DSPFW_SPRITEA_SHIFT 0 3786 #define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */ 3787 #define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */ 3788 #define DSPFW3 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c) 3789 #define DSPFW_HPLL_SR_EN (1 << 31) 3790 #define PINEVIEW_SELF_REFRESH_EN (1 << 30) 3791 #define DSPFW_CURSOR_SR_SHIFT 24 3792 #define DSPFW_CURSOR_SR_MASK (0x3f << 24) 3793 #define DSPFW_HPLL_CURSOR_SHIFT 16 3794 #define DSPFW_HPLL_CURSOR_MASK (0x3f << 16) 3795 #define DSPFW_HPLL_SR_SHIFT 0 3796 #define DSPFW_HPLL_SR_MASK (0x1ff << 0) 3797 3798 /* vlv/chv */ 3799 #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070) 3800 #define DSPFW_SPRITEB_WM1_SHIFT 16 3801 #define DSPFW_SPRITEB_WM1_MASK (0xff << 16) 3802 #define DSPFW_CURSORA_WM1_SHIFT 8 3803 #define DSPFW_CURSORA_WM1_MASK (0x3f << 8) 3804 #define DSPFW_SPRITEA_WM1_SHIFT 0 3805 #define DSPFW_SPRITEA_WM1_MASK (0xff << 0) 3806 #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074) 3807 #define DSPFW_PLANEB_WM1_SHIFT 24 3808 #define DSPFW_PLANEB_WM1_MASK (0xff << 24) 3809 #define DSPFW_PLANEA_WM1_SHIFT 16 3810 #define DSPFW_PLANEA_WM1_MASK (0xff << 16) 3811 #define DSPFW_CURSORB_WM1_SHIFT 8 3812 #define DSPFW_CURSORB_WM1_MASK (0x3f << 8) 3813 #define DSPFW_CURSOR_SR_WM1_SHIFT 0 3814 #define DSPFW_CURSOR_SR_WM1_MASK (0x3f << 0) 3815 #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078) 3816 #define DSPFW_SR_WM1_SHIFT 0 3817 #define DSPFW_SR_WM1_MASK (0x1ff << 0) 3818 #define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c) 3819 #define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */ 3820 #define DSPFW_SPRITED_WM1_SHIFT 24 3821 #define DSPFW_SPRITED_WM1_MASK (0xff << 24) 3822 #define DSPFW_SPRITED_SHIFT 16 3823 #define DSPFW_SPRITED_MASK_VLV (0xff << 16) 3824 #define DSPFW_SPRITEC_WM1_SHIFT 8 3825 #define DSPFW_SPRITEC_WM1_MASK (0xff << 8) 3826 #define DSPFW_SPRITEC_SHIFT 0 3827 #define DSPFW_SPRITEC_MASK_VLV (0xff << 0) 3828 #define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8) 3829 #define DSPFW_SPRITEF_WM1_SHIFT 24 3830 #define DSPFW_SPRITEF_WM1_MASK (0xff << 24) 3831 #define DSPFW_SPRITEF_SHIFT 16 3832 #define DSPFW_SPRITEF_MASK_VLV (0xff << 16) 3833 #define DSPFW_SPRITEE_WM1_SHIFT 8 3834 #define DSPFW_SPRITEE_WM1_MASK (0xff << 8) 3835 #define DSPFW_SPRITEE_SHIFT 0 3836 #define DSPFW_SPRITEE_MASK_VLV (0xff << 0) 3837 #define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */ 3838 #define DSPFW_PLANEC_WM1_SHIFT 24 3839 #define DSPFW_PLANEC_WM1_MASK (0xff << 24) 3840 #define DSPFW_PLANEC_SHIFT 16 3841 #define DSPFW_PLANEC_MASK_VLV (0xff << 16) 3842 #define DSPFW_CURSORC_WM1_SHIFT 8 3843 #define DSPFW_CURSORC_WM1_MASK (0x3f << 16) 3844 #define DSPFW_CURSORC_SHIFT 0 3845 #define DSPFW_CURSORC_MASK (0x3f << 0) 3846 3847 /* vlv/chv high order bits */ 3848 #define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064) 3849 #define DSPFW_SR_HI_SHIFT 24 3850 #define DSPFW_SR_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */ 3851 #define DSPFW_SPRITEF_HI_SHIFT 23 3852 #define DSPFW_SPRITEF_HI_MASK (1 << 23) 3853 #define DSPFW_SPRITEE_HI_SHIFT 22 3854 #define DSPFW_SPRITEE_HI_MASK (1 << 22) 3855 #define DSPFW_PLANEC_HI_SHIFT 21 3856 #define DSPFW_PLANEC_HI_MASK (1 << 21) 3857 #define DSPFW_SPRITED_HI_SHIFT 20 3858 #define DSPFW_SPRITED_HI_MASK (1 << 20) 3859 #define DSPFW_SPRITEC_HI_SHIFT 16 3860 #define DSPFW_SPRITEC_HI_MASK (1 << 16) 3861 #define DSPFW_PLANEB_HI_SHIFT 12 3862 #define DSPFW_PLANEB_HI_MASK (1 << 12) 3863 #define DSPFW_SPRITEB_HI_SHIFT 8 3864 #define DSPFW_SPRITEB_HI_MASK (1 << 8) 3865 #define DSPFW_SPRITEA_HI_SHIFT 4 3866 #define DSPFW_SPRITEA_HI_MASK (1 << 4) 3867 #define DSPFW_PLANEA_HI_SHIFT 0 3868 #define DSPFW_PLANEA_HI_MASK (1 << 0) 3869 #define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068) 3870 #define DSPFW_SR_WM1_HI_SHIFT 24 3871 #define DSPFW_SR_WM1_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */ 3872 #define DSPFW_SPRITEF_WM1_HI_SHIFT 23 3873 #define DSPFW_SPRITEF_WM1_HI_MASK (1 << 23) 3874 #define DSPFW_SPRITEE_WM1_HI_SHIFT 22 3875 #define DSPFW_SPRITEE_WM1_HI_MASK (1 << 22) 3876 #define DSPFW_PLANEC_WM1_HI_SHIFT 21 3877 #define DSPFW_PLANEC_WM1_HI_MASK (1 << 21) 3878 #define DSPFW_SPRITED_WM1_HI_SHIFT 20 3879 #define DSPFW_SPRITED_WM1_HI_MASK (1 << 20) 3880 #define DSPFW_SPRITEC_WM1_HI_SHIFT 16 3881 #define DSPFW_SPRITEC_WM1_HI_MASK (1 << 16) 3882 #define DSPFW_PLANEB_WM1_HI_SHIFT 12 3883 #define DSPFW_PLANEB_WM1_HI_MASK (1 << 12) 3884 #define DSPFW_SPRITEB_WM1_HI_SHIFT 8 3885 #define DSPFW_SPRITEB_WM1_HI_MASK (1 << 8) 3886 #define DSPFW_SPRITEA_WM1_HI_SHIFT 4 3887 #define DSPFW_SPRITEA_WM1_HI_MASK (1 << 4) 3888 #define DSPFW_PLANEA_WM1_HI_SHIFT 0 3889 #define DSPFW_PLANEA_WM1_HI_MASK (1 << 0) 3890 3891 /* drain latency register values*/ 3892 #define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe)) 3893 #define DDL_CURSOR_SHIFT 24 3894 #define DDL_SPRITE_SHIFT(sprite) (8 + 8 * (sprite)) 3895 #define DDL_PLANE_SHIFT 0 3896 #define DDL_PRECISION_HIGH (1 << 7) 3897 #define DDL_PRECISION_LOW (0 << 7) 3898 #define DRAIN_LATENCY_MASK 0x7f 3899 3900 #define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400) 3901 #define CBR_PND_DEADLINE_DISABLE (1 << 31) 3902 #define CBR_PWM_CLOCK_MUX_SELECT (1 << 30) 3903 3904 #define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450) 3905 #define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11)) /* pipes B and C */ 3906 3907 /* FIFO watermark sizes etc */ 3908 #define G4X_FIFO_LINE_SIZE 64 3909 #define I915_FIFO_LINE_SIZE 64 3910 #define I830_FIFO_LINE_SIZE 32 3911 3912 #define VALLEYVIEW_FIFO_SIZE 255 3913 #define G4X_FIFO_SIZE 127 3914 #define I965_FIFO_SIZE 512 3915 #define I945_FIFO_SIZE 127 3916 #define I915_FIFO_SIZE 95 3917 #define I855GM_FIFO_SIZE 127 /* In cachelines */ 3918 #define I830_FIFO_SIZE 95 3919 3920 #define VALLEYVIEW_MAX_WM 0xff 3921 #define G4X_MAX_WM 0x3f 3922 #define I915_MAX_WM 0x3f 3923 3924 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ 3925 #define PINEVIEW_FIFO_LINE_SIZE 64 3926 #define PINEVIEW_MAX_WM 0x1ff 3927 #define PINEVIEW_DFT_WM 0x3f 3928 #define PINEVIEW_DFT_HPLLOFF_WM 0 3929 #define PINEVIEW_GUARD_WM 10 3930 #define PINEVIEW_CURSOR_FIFO 64 3931 #define PINEVIEW_CURSOR_MAX_WM 0x3f 3932 #define PINEVIEW_CURSOR_DFT_WM 0 3933 #define PINEVIEW_CURSOR_GUARD_WM 5 3934 3935 #define VALLEYVIEW_CURSOR_MAX_WM 64 3936 #define I965_CURSOR_FIFO 64 3937 #define I965_CURSOR_MAX_WM 32 3938 #define I965_CURSOR_DFT_WM 8 3939 3940 /* Watermark register definitions for SKL */ 3941 #define _CUR_WM_A_0 0x70140 3942 #define _CUR_WM_B_0 0x71140 3943 #define _CUR_WM_SAGV_A 0x70158 3944 #define _CUR_WM_SAGV_B 0x71158 3945 #define _CUR_WM_SAGV_TRANS_A 0x7015C 3946 #define _CUR_WM_SAGV_TRANS_B 0x7115C 3947 #define _CUR_WM_TRANS_A 0x70168 3948 #define _CUR_WM_TRANS_B 0x71168 3949 #define _PLANE_WM_1_A_0 0x70240 3950 #define _PLANE_WM_1_B_0 0x71240 3951 #define _PLANE_WM_2_A_0 0x70340 3952 #define _PLANE_WM_2_B_0 0x71340 3953 #define _PLANE_WM_SAGV_1_A 0x70258 3954 #define _PLANE_WM_SAGV_1_B 0x71258 3955 #define _PLANE_WM_SAGV_2_A 0x70358 3956 #define _PLANE_WM_SAGV_2_B 0x71358 3957 #define _PLANE_WM_SAGV_TRANS_1_A 0x7025C 3958 #define _PLANE_WM_SAGV_TRANS_1_B 0x7125C 3959 #define _PLANE_WM_SAGV_TRANS_2_A 0x7035C 3960 #define _PLANE_WM_SAGV_TRANS_2_B 0x7135C 3961 #define _PLANE_WM_TRANS_1_A 0x70268 3962 #define _PLANE_WM_TRANS_1_B 0x71268 3963 #define _PLANE_WM_TRANS_2_A 0x70368 3964 #define _PLANE_WM_TRANS_2_B 0x71368 3965 #define PLANE_WM_EN (1 << 31) 3966 #define PLANE_WM_IGNORE_LINES (1 << 30) 3967 #define PLANE_WM_LINES_MASK REG_GENMASK(26, 14) 3968 #define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0) 3969 3970 #define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0) 3971 #define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level))) 3972 #define CUR_WM_SAGV(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_A, _CUR_WM_SAGV_B) 3973 #define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B) 3974 #define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A, _CUR_WM_TRANS_B) 3975 #define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0) 3976 #define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0) 3977 #define _PLANE_WM_BASE(pipe, plane) \ 3978 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe)) 3979 #define PLANE_WM(pipe, plane, level) \ 3980 _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level))) 3981 #define _PLANE_WM_SAGV_1(pipe) \ 3982 _PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B) 3983 #define _PLANE_WM_SAGV_2(pipe) \ 3984 _PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B) 3985 #define PLANE_WM_SAGV(pipe, plane) \ 3986 _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe))) 3987 #define _PLANE_WM_SAGV_TRANS_1(pipe) \ 3988 _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B) 3989 #define _PLANE_WM_SAGV_TRANS_2(pipe) \ 3990 _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B) 3991 #define PLANE_WM_SAGV_TRANS(pipe, plane) \ 3992 _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe))) 3993 #define _PLANE_WM_TRANS_1(pipe) \ 3994 _PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B) 3995 #define _PLANE_WM_TRANS_2(pipe) \ 3996 _PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B) 3997 #define PLANE_WM_TRANS(pipe, plane) \ 3998 _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe))) 3999 4000 /* define the Watermark register on Ironlake */ 4001 #define _WM0_PIPEA_ILK 0x45100 4002 #define _WM0_PIPEB_ILK 0x45104 4003 #define _WM0_PIPEC_IVB 0x45200 4004 #define WM0_PIPE_ILK(pipe) _MMIO_PIPE3((pipe), _WM0_PIPEA_ILK, \ 4005 _WM0_PIPEB_ILK, _WM0_PIPEC_IVB) 4006 #define WM0_PIPE_PRIMARY_MASK REG_GENMASK(31, 16) 4007 #define WM0_PIPE_SPRITE_MASK REG_GENMASK(15, 8) 4008 #define WM0_PIPE_CURSOR_MASK REG_GENMASK(7, 0) 4009 #define WM0_PIPE_PRIMARY(x) REG_FIELD_PREP(WM0_PIPE_PRIMARY_MASK, (x)) 4010 #define WM0_PIPE_SPRITE(x) REG_FIELD_PREP(WM0_PIPE_SPRITE_MASK, (x)) 4011 #define WM0_PIPE_CURSOR(x) REG_FIELD_PREP(WM0_PIPE_CURSOR_MASK, (x)) 4012 #define WM1_LP_ILK _MMIO(0x45108) 4013 #define WM2_LP_ILK _MMIO(0x4510c) 4014 #define WM3_LP_ILK _MMIO(0x45110) 4015 #define WM_LP_ENABLE REG_BIT(31) 4016 #define WM_LP_LATENCY_MASK REG_GENMASK(30, 24) 4017 #define WM_LP_FBC_MASK_BDW REG_GENMASK(23, 19) 4018 #define WM_LP_FBC_MASK_ILK REG_GENMASK(23, 20) 4019 #define WM_LP_PRIMARY_MASK REG_GENMASK(18, 8) 4020 #define WM_LP_CURSOR_MASK REG_GENMASK(7, 0) 4021 #define WM_LP_LATENCY(x) REG_FIELD_PREP(WM_LP_LATENCY_MASK, (x)) 4022 #define WM_LP_FBC_BDW(x) REG_FIELD_PREP(WM_LP_FBC_MASK_BDW, (x)) 4023 #define WM_LP_FBC_ILK(x) REG_FIELD_PREP(WM_LP_FBC_MASK_ILK, (x)) 4024 #define WM_LP_PRIMARY(x) REG_FIELD_PREP(WM_LP_PRIMARY_MASK, (x)) 4025 #define WM_LP_CURSOR(x) REG_FIELD_PREP(WM_LP_CURSOR_MASK, (x)) 4026 #define WM1S_LP_ILK _MMIO(0x45120) 4027 #define WM2S_LP_IVB _MMIO(0x45124) 4028 #define WM3S_LP_IVB _MMIO(0x45128) 4029 #define WM_LP_SPRITE_ENABLE REG_BIT(31) /* ilk/snb WM1S only */ 4030 #define WM_LP_SPRITE_MASK REG_GENMASK(10, 0) 4031 #define WM_LP_SPRITE(x) REG_FIELD_PREP(WM_LP_SPRITE_MASK, (x)) 4032 4033 /* 4034 * The two pipe frame counter registers are not synchronized, so 4035 * reading a stable value is somewhat tricky. The following code 4036 * should work: 4037 * 4038 * do { 4039 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 4040 * PIPE_FRAME_HIGH_SHIFT; 4041 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> 4042 * PIPE_FRAME_LOW_SHIFT); 4043 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 4044 * PIPE_FRAME_HIGH_SHIFT); 4045 * } while (high1 != high2); 4046 * frame = (high1 << 8) | low1; 4047 */ 4048 #define _PIPEAFRAMEHIGH 0x70040 4049 #define PIPE_FRAME_HIGH_MASK 0x0000ffff 4050 #define PIPE_FRAME_HIGH_SHIFT 0 4051 #define _PIPEAFRAMEPIXEL 0x70044 4052 #define PIPE_FRAME_LOW_MASK 0xff000000 4053 #define PIPE_FRAME_LOW_SHIFT 24 4054 #define PIPE_PIXEL_MASK 0x00ffffff 4055 #define PIPE_PIXEL_SHIFT 0 4056 /* GM45+ just has to be different */ 4057 #define _PIPEA_FRMCOUNT_G4X 0x70040 4058 #define _PIPEA_FLIPCOUNT_G4X 0x70044 4059 #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X) 4060 #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X) 4061 4062 /* Cursor A & B regs */ 4063 #define _CURACNTR 0x70080 4064 /* Old style CUR*CNTR flags (desktop 8xx) */ 4065 #define CURSOR_ENABLE REG_BIT(31) 4066 #define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30) 4067 #define CURSOR_STRIDE_MASK REG_GENMASK(29, 28) 4068 #define CURSOR_STRIDE(stride) REG_FIELD_PREP(CURSOR_STRIDE_MASK, ffs(stride) - 9) /* 256,512,1k,2k */ 4069 #define CURSOR_FORMAT_MASK REG_GENMASK(26, 24) 4070 #define CURSOR_FORMAT_2C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 0) 4071 #define CURSOR_FORMAT_3C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 1) 4072 #define CURSOR_FORMAT_4C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 2) 4073 #define CURSOR_FORMAT_ARGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 4) 4074 #define CURSOR_FORMAT_XRGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 5) 4075 /* New style CUR*CNTR flags */ 4076 #define MCURSOR_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ 4077 #define MCURSOR_ARB_SLOTS(x) REG_FIELD_PREP(MCURSOR_ARB_SLOTS_MASK, (x)) /* icl+ */ 4078 #define MCURSOR_PIPE_SEL_MASK REG_GENMASK(29, 28) 4079 #define MCURSOR_PIPE_SEL(pipe) REG_FIELD_PREP(MCURSOR_PIPE_SEL_MASK, (pipe)) 4080 #define MCURSOR_PIPE_GAMMA_ENABLE REG_BIT(26) 4081 #define MCURSOR_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */ 4082 #define MCURSOR_ROTATE_180 REG_BIT(15) 4083 #define MCURSOR_TRICKLE_FEED_DISABLE REG_BIT(14) 4084 #define MCURSOR_MODE_MASK 0x27 4085 #define MCURSOR_MODE_DISABLE 0x00 4086 #define MCURSOR_MODE_128_32B_AX 0x02 4087 #define MCURSOR_MODE_256_32B_AX 0x03 4088 #define MCURSOR_MODE_64_32B_AX 0x07 4089 #define MCURSOR_MODE_128_ARGB_AX (0x20 | MCURSOR_MODE_128_32B_AX) 4090 #define MCURSOR_MODE_256_ARGB_AX (0x20 | MCURSOR_MODE_256_32B_AX) 4091 #define MCURSOR_MODE_64_ARGB_AX (0x20 | MCURSOR_MODE_64_32B_AX) 4092 #define _CURABASE 0x70084 4093 #define _CURAPOS 0x70088 4094 #define CURSOR_POS_Y_SIGN REG_BIT(31) 4095 #define CURSOR_POS_Y_MASK REG_GENMASK(30, 16) 4096 #define CURSOR_POS_Y(y) REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y)) 4097 #define CURSOR_POS_X_SIGN REG_BIT(15) 4098 #define CURSOR_POS_X_MASK REG_GENMASK(14, 0) 4099 #define CURSOR_POS_X(x) REG_FIELD_PREP(CURSOR_POS_X_MASK, (x)) 4100 #define _CURASIZE 0x700a0 /* 845/865 */ 4101 #define CURSOR_HEIGHT_MASK REG_GENMASK(21, 12) 4102 #define CURSOR_HEIGHT(h) REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h)) 4103 #define CURSOR_WIDTH_MASK REG_GENMASK(9, 0) 4104 #define CURSOR_WIDTH(w) REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w)) 4105 #define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */ 4106 #define CUR_FBC_EN REG_BIT(31) 4107 #define CUR_FBC_HEIGHT_MASK REG_GENMASK(7, 0) 4108 #define CUR_FBC_HEIGHT(h) REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h)) 4109 #define _CURASURFLIVE 0x700ac /* g4x+ */ 4110 #define _CURBCNTR 0x700c0 4111 #define _CURBBASE 0x700c4 4112 #define _CURBPOS 0x700c8 4113 4114 #define _CURBCNTR_IVB 0x71080 4115 #define _CURBBASE_IVB 0x71084 4116 #define _CURBPOS_IVB 0x71088 4117 4118 #define CURCNTR(pipe) _MMIO_CURSOR2(pipe, _CURACNTR) 4119 #define CURBASE(pipe) _MMIO_CURSOR2(pipe, _CURABASE) 4120 #define CURPOS(pipe) _MMIO_CURSOR2(pipe, _CURAPOS) 4121 #define CURSIZE(pipe) _MMIO_CURSOR2(pipe, _CURASIZE) 4122 #define CUR_FBC_CTL(pipe) _MMIO_CURSOR2(pipe, _CUR_FBC_CTL_A) 4123 #define CURSURFLIVE(pipe) _MMIO_CURSOR2(pipe, _CURASURFLIVE) 4124 4125 #define CURSOR_A_OFFSET 0x70080 4126 #define CURSOR_B_OFFSET 0x700c0 4127 #define CHV_CURSOR_C_OFFSET 0x700e0 4128 #define IVB_CURSOR_B_OFFSET 0x71080 4129 #define IVB_CURSOR_C_OFFSET 0x72080 4130 #define TGL_CURSOR_D_OFFSET 0x73080 4131 4132 /* Display A control */ 4133 #define _DSPAADDR_VLV 0x7017C /* vlv/chv */ 4134 #define _DSPACNTR 0x70180 4135 #define DISP_ENABLE REG_BIT(31) 4136 #define DISP_PIPE_GAMMA_ENABLE REG_BIT(30) 4137 #define DISP_FORMAT_MASK REG_GENMASK(29, 26) 4138 #define DISP_FORMAT_8BPP REG_FIELD_PREP(DISP_FORMAT_MASK, 2) 4139 #define DISP_FORMAT_BGRA555 REG_FIELD_PREP(DISP_FORMAT_MASK, 3) 4140 #define DISP_FORMAT_BGRX555 REG_FIELD_PREP(DISP_FORMAT_MASK, 4) 4141 #define DISP_FORMAT_BGRX565 REG_FIELD_PREP(DISP_FORMAT_MASK, 5) 4142 #define DISP_FORMAT_BGRX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 6) 4143 #define DISP_FORMAT_BGRA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 7) 4144 #define DISP_FORMAT_RGBX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 8) 4145 #define DISP_FORMAT_RGBA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 9) 4146 #define DISP_FORMAT_BGRX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 10) 4147 #define DISP_FORMAT_BGRA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 11) 4148 #define DISP_FORMAT_RGBX161616 REG_FIELD_PREP(DISP_FORMAT_MASK, 12) 4149 #define DISP_FORMAT_RGBX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 14) 4150 #define DISP_FORMAT_RGBA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 15) 4151 #define DISP_STEREO_ENABLE REG_BIT(25) 4152 #define DISP_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */ 4153 #define DISP_PIPE_SEL_MASK REG_GENMASK(25, 24) 4154 #define DISP_PIPE_SEL(pipe) REG_FIELD_PREP(DISP_PIPE_SEL_MASK, (pipe)) 4155 #define DISP_SRC_KEY_ENABLE REG_BIT(22) 4156 #define DISP_LINE_DOUBLE REG_BIT(20) 4157 #define DISP_STEREO_POLARITY_SECOND REG_BIT(18) 4158 #define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */ 4159 #define DISP_ROTATE_180 REG_BIT(15) 4160 #define DISP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */ 4161 #define DISP_TILED REG_BIT(10) 4162 #define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */ 4163 #define DISP_MIRROR REG_BIT(8) /* CHV pipe B */ 4164 #define _DSPAADDR 0x70184 4165 #define _DSPASTRIDE 0x70188 4166 #define _DSPAPOS 0x7018C /* reserved */ 4167 #define DISP_POS_Y_MASK REG_GENMASK(31, 16) 4168 #define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y)) 4169 #define DISP_POS_X_MASK REG_GENMASK(15, 0) 4170 #define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x)) 4171 #define _DSPASIZE 0x70190 4172 #define DISP_HEIGHT_MASK REG_GENMASK(31, 16) 4173 #define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h)) 4174 #define DISP_WIDTH_MASK REG_GENMASK(15, 0) 4175 #define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w)) 4176 #define _DSPASURF 0x7019C /* 965+ only */ 4177 #define DISP_ADDR_MASK REG_GENMASK(31, 12) 4178 #define _DSPATILEOFF 0x701A4 /* 965+ only */ 4179 #define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16) 4180 #define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y)) 4181 #define DISP_OFFSET_X_MASK REG_GENMASK(15, 0) 4182 #define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x)) 4183 #define _DSPAOFFSET 0x701A4 /* HSW */ 4184 #define _DSPASURFLIVE 0x701AC 4185 #define _DSPAGAMC 0x701E0 4186 4187 #define DSPADDR_VLV(plane) _MMIO_PIPE2(plane, _DSPAADDR_VLV) 4188 #define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR) 4189 #define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR) 4190 #define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE) 4191 #define DSPPOS(plane) _MMIO_PIPE2(plane, _DSPAPOS) 4192 #define DSPSIZE(plane) _MMIO_PIPE2(plane, _DSPASIZE) 4193 #define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF) 4194 #define DSPTILEOFF(plane) _MMIO_PIPE2(plane, _DSPATILEOFF) 4195 #define DSPLINOFF(plane) DSPADDR(plane) 4196 #define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET) 4197 #define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE) 4198 #define DSPGAMC(plane, i) _MMIO_PIPE2(plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ 4199 4200 /* CHV pipe B blender and primary plane */ 4201 #define _CHV_BLEND_A 0x60a00 4202 #define CHV_BLEND_MASK REG_GENMASK(31, 30) 4203 #define CHV_BLEND_LEGACY REG_FIELD_PREP(CHV_BLEND_MASK, 0) 4204 #define CHV_BLEND_ANDROID REG_FIELD_PREP(CHV_BLEND_MASK, 1) 4205 #define CHV_BLEND_MPO REG_FIELD_PREP(CHV_BLEND_MASK, 2) 4206 #define _CHV_CANVAS_A 0x60a04 4207 #define CHV_CANVAS_RED_MASK REG_GENMASK(29, 20) 4208 #define CHV_CANVAS_GREEN_MASK REG_GENMASK(19, 10) 4209 #define CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0) 4210 #define _PRIMPOS_A 0x60a08 4211 #define PRIM_POS_Y_MASK REG_GENMASK(31, 16) 4212 #define PRIM_POS_Y(y) REG_FIELD_PREP(PRIM_POS_Y_MASK, (y)) 4213 #define PRIM_POS_X_MASK REG_GENMASK(15, 0) 4214 #define PRIM_POS_X(x) REG_FIELD_PREP(PRIM_POS_X_MASK, (x)) 4215 #define _PRIMSIZE_A 0x60a0c 4216 #define PRIM_HEIGHT_MASK REG_GENMASK(31, 16) 4217 #define PRIM_HEIGHT(h) REG_FIELD_PREP(PRIM_HEIGHT_MASK, (h)) 4218 #define PRIM_WIDTH_MASK REG_GENMASK(15, 0) 4219 #define PRIM_WIDTH(w) REG_FIELD_PREP(PRIM_WIDTH_MASK, (w)) 4220 #define _PRIMCNSTALPHA_A 0x60a10 4221 #define PRIM_CONST_ALPHA_ENABLE REG_BIT(31) 4222 #define PRIM_CONST_ALPHA_MASK REG_GENMASK(7, 0) 4223 #define PRIM_CONST_ALPHA(alpha) REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha)) 4224 4225 #define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A) 4226 #define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A) 4227 #define PRIMPOS(plane) _MMIO_TRANS2(plane, _PRIMPOS_A) 4228 #define PRIMSIZE(plane) _MMIO_TRANS2(plane, _PRIMSIZE_A) 4229 #define PRIMCNSTALPHA(plane) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A) 4230 4231 /* Display/Sprite base address macros */ 4232 #define DISP_BASEADDR_MASK (0xfffff000) 4233 #define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK) 4234 #define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK) 4235 4236 /* 4237 * VBIOS flags 4238 * gen2: 4239 * [00:06] alm,mgm 4240 * [10:16] all 4241 * [30:32] alm,mgm 4242 * gen3+: 4243 * [00:0f] all 4244 * [10:1f] all 4245 * [30:32] all 4246 */ 4247 #define SWF0(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4) 4248 #define SWF1(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4) 4249 #define SWF3(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4) 4250 #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4) 4251 4252 /* Pipe B */ 4253 #define _PIPEBDSL (DISPLAY_MMIO_BASE(dev_priv) + 0x71000) 4254 #define _PIPEBCONF (DISPLAY_MMIO_BASE(dev_priv) + 0x71008) 4255 #define _PIPEBSTAT (DISPLAY_MMIO_BASE(dev_priv) + 0x71024) 4256 #define _PIPEBFRAMEHIGH 0x71040 4257 #define _PIPEBFRAMEPIXEL 0x71044 4258 #define _PIPEB_FRMCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71040) 4259 #define _PIPEB_FLIPCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71044) 4260 4261 4262 /* Display B control */ 4263 #define _DSPBCNTR (DISPLAY_MMIO_BASE(dev_priv) + 0x71180) 4264 #define DISP_ALPHA_TRANS_ENABLE REG_BIT(15) 4265 #define DISP_SPRITE_ABOVE_OVERLAY REG_BIT(0) 4266 #define _DSPBADDR (DISPLAY_MMIO_BASE(dev_priv) + 0x71184) 4267 #define _DSPBSTRIDE (DISPLAY_MMIO_BASE(dev_priv) + 0x71188) 4268 #define _DSPBPOS (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C) 4269 #define _DSPBSIZE (DISPLAY_MMIO_BASE(dev_priv) + 0x71190) 4270 #define _DSPBSURF (DISPLAY_MMIO_BASE(dev_priv) + 0x7119C) 4271 #define _DSPBTILEOFF (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4) 4272 #define _DSPBOFFSET (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4) 4273 #define _DSPBSURFLIVE (DISPLAY_MMIO_BASE(dev_priv) + 0x711AC) 4274 4275 /* ICL DSI 0 and 1 */ 4276 #define _PIPEDSI0CONF 0x7b008 4277 #define _PIPEDSI1CONF 0x7b808 4278 4279 /* Sprite A control */ 4280 #define _DVSACNTR 0x72180 4281 #define DVS_ENABLE REG_BIT(31) 4282 #define DVS_PIPE_GAMMA_ENABLE REG_BIT(30) 4283 #define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27) 4284 #define DVS_FORMAT_MASK REG_GENMASK(26, 25) 4285 #define DVS_FORMAT_YUV422 REG_FIELD_PREP(DVS_FORMAT_MASK, 0) 4286 #define DVS_FORMAT_RGBX101010 REG_FIELD_PREP(DVS_FORMAT_MASK, 1) 4287 #define DVS_FORMAT_RGBX888 REG_FIELD_PREP(DVS_FORMAT_MASK, 2) 4288 #define DVS_FORMAT_RGBX161616 REG_FIELD_PREP(DVS_FORMAT_MASK, 3) 4289 #define DVS_PIPE_CSC_ENABLE REG_BIT(24) 4290 #define DVS_SOURCE_KEY REG_BIT(22) 4291 #define DVS_RGB_ORDER_XBGR REG_BIT(20) 4292 #define DVS_YUV_FORMAT_BT709 REG_BIT(18) 4293 #define DVS_YUV_ORDER_MASK REG_GENMASK(17, 16) 4294 #define DVS_YUV_ORDER_YUYV REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 0) 4295 #define DVS_YUV_ORDER_UYVY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 1) 4296 #define DVS_YUV_ORDER_YVYU REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 2) 4297 #define DVS_YUV_ORDER_VYUY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 3) 4298 #define DVS_ROTATE_180 REG_BIT(15) 4299 #define DVS_TRICKLE_FEED_DISABLE REG_BIT(14) 4300 #define DVS_TILED REG_BIT(10) 4301 #define DVS_DEST_KEY REG_BIT(2) 4302 #define _DVSALINOFF 0x72184 4303 #define _DVSASTRIDE 0x72188 4304 #define _DVSAPOS 0x7218c 4305 #define DVS_POS_Y_MASK REG_GENMASK(31, 16) 4306 #define DVS_POS_Y(y) REG_FIELD_PREP(DVS_POS_Y_MASK, (y)) 4307 #define DVS_POS_X_MASK REG_GENMASK(15, 0) 4308 #define DVS_POS_X(x) REG_FIELD_PREP(DVS_POS_X_MASK, (x)) 4309 #define _DVSASIZE 0x72190 4310 #define DVS_HEIGHT_MASK REG_GENMASK(31, 16) 4311 #define DVS_HEIGHT(h) REG_FIELD_PREP(DVS_HEIGHT_MASK, (h)) 4312 #define DVS_WIDTH_MASK REG_GENMASK(15, 0) 4313 #define DVS_WIDTH(w) REG_FIELD_PREP(DVS_WIDTH_MASK, (w)) 4314 #define _DVSAKEYVAL 0x72194 4315 #define _DVSAKEYMSK 0x72198 4316 #define _DVSASURF 0x7219c 4317 #define DVS_ADDR_MASK REG_GENMASK(31, 12) 4318 #define _DVSAKEYMAXVAL 0x721a0 4319 #define _DVSATILEOFF 0x721a4 4320 #define DVS_OFFSET_Y_MASK REG_GENMASK(31, 16) 4321 #define DVS_OFFSET_Y(y) REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y)) 4322 #define DVS_OFFSET_X_MASK REG_GENMASK(15, 0) 4323 #define DVS_OFFSET_X(x) REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x)) 4324 #define _DVSASURFLIVE 0x721ac 4325 #define _DVSAGAMC_G4X 0x721e0 /* g4x */ 4326 #define _DVSASCALE 0x72204 4327 #define DVS_SCALE_ENABLE REG_BIT(31) 4328 #define DVS_FILTER_MASK REG_GENMASK(30, 29) 4329 #define DVS_FILTER_MEDIUM REG_FIELD_PREP(DVS_FILTER_MASK, 0) 4330 #define DVS_FILTER_ENHANCING REG_FIELD_PREP(DVS_FILTER_MASK, 1) 4331 #define DVS_FILTER_SOFTENING REG_FIELD_PREP(DVS_FILTER_MASK, 2) 4332 #define DVS_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */ 4333 #define DVS_VERTICAL_OFFSET_ENABLE REG_BIT(27) 4334 #define DVS_SRC_WIDTH_MASK REG_GENMASK(26, 16) 4335 #define DVS_SRC_WIDTH(w) REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w)) 4336 #define DVS_SRC_HEIGHT_MASK REG_GENMASK(10, 0) 4337 #define DVS_SRC_HEIGHT(h) REG_FIELD_PREP(DVS_SRC_HEIGHT_MASK, (h)) 4338 #define _DVSAGAMC_ILK 0x72300 /* ilk/snb */ 4339 #define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */ 4340 4341 #define _DVSBCNTR 0x73180 4342 #define _DVSBLINOFF 0x73184 4343 #define _DVSBSTRIDE 0x73188 4344 #define _DVSBPOS 0x7318c 4345 #define _DVSBSIZE 0x73190 4346 #define _DVSBKEYVAL 0x73194 4347 #define _DVSBKEYMSK 0x73198 4348 #define _DVSBSURF 0x7319c 4349 #define _DVSBKEYMAXVAL 0x731a0 4350 #define _DVSBTILEOFF 0x731a4 4351 #define _DVSBSURFLIVE 0x731ac 4352 #define _DVSBGAMC_G4X 0x731e0 /* g4x */ 4353 #define _DVSBSCALE 0x73204 4354 #define _DVSBGAMC_ILK 0x73300 /* ilk/snb */ 4355 #define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */ 4356 4357 #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR) 4358 #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) 4359 #define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) 4360 #define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS) 4361 #define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF) 4362 #define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) 4363 #define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE) 4364 #define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE) 4365 #define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) 4366 #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) 4367 #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) 4368 #define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) 4369 #define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */ 4370 #define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */ 4371 #define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */ 4372 4373 #define _SPRA_CTL 0x70280 4374 #define SPRITE_ENABLE REG_BIT(31) 4375 #define SPRITE_PIPE_GAMMA_ENABLE REG_BIT(30) 4376 #define SPRITE_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) 4377 #define SPRITE_FORMAT_MASK REG_GENMASK(27, 25) 4378 #define SPRITE_FORMAT_YUV422 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 0) 4379 #define SPRITE_FORMAT_RGBX101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 1) 4380 #define SPRITE_FORMAT_RGBX888 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 2) 4381 #define SPRITE_FORMAT_RGBX161616 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 3) 4382 #define SPRITE_FORMAT_YUV444 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 4) 4383 #define SPRITE_FORMAT_XR_BGR101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 5) /* Extended range */ 4384 #define SPRITE_PIPE_CSC_ENABLE REG_BIT(24) 4385 #define SPRITE_SOURCE_KEY REG_BIT(22) 4386 #define SPRITE_RGB_ORDER_RGBX REG_BIT(20) /* only for 888 and 161616 */ 4387 #define SPRITE_YUV_TO_RGB_CSC_DISABLE REG_BIT(19) 4388 #define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) /* 0 is BT601 */ 4389 #define SPRITE_YUV_ORDER_MASK REG_GENMASK(17, 16) 4390 #define SPRITE_YUV_ORDER_YUYV REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 0) 4391 #define SPRITE_YUV_ORDER_UYVY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 1) 4392 #define SPRITE_YUV_ORDER_YVYU REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 2) 4393 #define SPRITE_YUV_ORDER_VYUY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 3) 4394 #define SPRITE_ROTATE_180 REG_BIT(15) 4395 #define SPRITE_TRICKLE_FEED_DISABLE REG_BIT(14) 4396 #define SPRITE_PLANE_GAMMA_DISABLE REG_BIT(13) 4397 #define SPRITE_TILED REG_BIT(10) 4398 #define SPRITE_DEST_KEY REG_BIT(2) 4399 #define _SPRA_LINOFF 0x70284 4400 #define _SPRA_STRIDE 0x70288 4401 #define _SPRA_POS 0x7028c 4402 #define SPRITE_POS_Y_MASK REG_GENMASK(31, 16) 4403 #define SPRITE_POS_Y(y) REG_FIELD_PREP(SPRITE_POS_Y_MASK, (y)) 4404 #define SPRITE_POS_X_MASK REG_GENMASK(15, 0) 4405 #define SPRITE_POS_X(x) REG_FIELD_PREP(SPRITE_POS_X_MASK, (x)) 4406 #define _SPRA_SIZE 0x70290 4407 #define SPRITE_HEIGHT_MASK REG_GENMASK(31, 16) 4408 #define SPRITE_HEIGHT(h) REG_FIELD_PREP(SPRITE_HEIGHT_MASK, (h)) 4409 #define SPRITE_WIDTH_MASK REG_GENMASK(15, 0) 4410 #define SPRITE_WIDTH(w) REG_FIELD_PREP(SPRITE_WIDTH_MASK, (w)) 4411 #define _SPRA_KEYVAL 0x70294 4412 #define _SPRA_KEYMSK 0x70298 4413 #define _SPRA_SURF 0x7029c 4414 #define SPRITE_ADDR_MASK REG_GENMASK(31, 12) 4415 #define _SPRA_KEYMAX 0x702a0 4416 #define _SPRA_TILEOFF 0x702a4 4417 #define SPRITE_OFFSET_Y_MASK REG_GENMASK(31, 16) 4418 #define SPRITE_OFFSET_Y(y) REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y)) 4419 #define SPRITE_OFFSET_X_MASK REG_GENMASK(15, 0) 4420 #define SPRITE_OFFSET_X(x) REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x)) 4421 #define _SPRA_OFFSET 0x702a4 4422 #define _SPRA_SURFLIVE 0x702ac 4423 #define _SPRA_SCALE 0x70304 4424 #define SPRITE_SCALE_ENABLE REG_BIT(31) 4425 #define SPRITE_FILTER_MASK REG_GENMASK(30, 29) 4426 #define SPRITE_FILTER_MEDIUM REG_FIELD_PREP(SPRITE_FILTER_MASK, 0) 4427 #define SPRITE_FILTER_ENHANCING REG_FIELD_PREP(SPRITE_FILTER_MASK, 1) 4428 #define SPRITE_FILTER_SOFTENING REG_FIELD_PREP(SPRITE_FILTER_MASK, 2) 4429 #define SPRITE_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */ 4430 #define SPRITE_VERTICAL_OFFSET_ENABLE REG_BIT(27) 4431 #define SPRITE_SRC_WIDTH_MASK REG_GENMASK(26, 16) 4432 #define SPRITE_SRC_WIDTH(w) REG_FIELD_PREP(SPRITE_SRC_WIDTH_MASK, (w)) 4433 #define SPRITE_SRC_HEIGHT_MASK REG_GENMASK(10, 0) 4434 #define SPRITE_SRC_HEIGHT(h) REG_FIELD_PREP(SPRITE_SRC_HEIGHT_MASK, (h)) 4435 #define _SPRA_GAMC 0x70400 4436 #define _SPRA_GAMC16 0x70440 4437 #define _SPRA_GAMC17 0x7044c 4438 4439 #define _SPRB_CTL 0x71280 4440 #define _SPRB_LINOFF 0x71284 4441 #define _SPRB_STRIDE 0x71288 4442 #define _SPRB_POS 0x7128c 4443 #define _SPRB_SIZE 0x71290 4444 #define _SPRB_KEYVAL 0x71294 4445 #define _SPRB_KEYMSK 0x71298 4446 #define _SPRB_SURF 0x7129c 4447 #define _SPRB_KEYMAX 0x712a0 4448 #define _SPRB_TILEOFF 0x712a4 4449 #define _SPRB_OFFSET 0x712a4 4450 #define _SPRB_SURFLIVE 0x712ac 4451 #define _SPRB_SCALE 0x71304 4452 #define _SPRB_GAMC 0x71400 4453 #define _SPRB_GAMC16 0x71440 4454 #define _SPRB_GAMC17 0x7144c 4455 4456 #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL) 4457 #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) 4458 #define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) 4459 #define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS) 4460 #define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) 4461 #define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) 4462 #define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) 4463 #define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF) 4464 #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) 4465 #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) 4466 #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) 4467 #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) 4468 #define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */ 4469 #define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */ 4470 #define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */ 4471 #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) 4472 4473 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180) 4474 #define SP_ENABLE REG_BIT(31) 4475 #define SP_PIPE_GAMMA_ENABLE REG_BIT(30) 4476 #define SP_FORMAT_MASK REG_GENMASK(29, 26) 4477 #define SP_FORMAT_YUV422 REG_FIELD_PREP(SP_FORMAT_MASK, 0) 4478 #define SP_FORMAT_8BPP REG_FIELD_PREP(SP_FORMAT_MASK, 2) 4479 #define SP_FORMAT_BGR565 REG_FIELD_PREP(SP_FORMAT_MASK, 5) 4480 #define SP_FORMAT_BGRX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 6) 4481 #define SP_FORMAT_BGRA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 7) 4482 #define SP_FORMAT_RGBX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 8) 4483 #define SP_FORMAT_RGBA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 9) 4484 #define SP_FORMAT_BGRX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 10) /* CHV pipe B */ 4485 #define SP_FORMAT_BGRA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 11) /* CHV pipe B */ 4486 #define SP_FORMAT_RGBX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 14) 4487 #define SP_FORMAT_RGBA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 15) 4488 #define SP_ALPHA_PREMULTIPLY REG_BIT(23) /* CHV pipe B */ 4489 #define SP_SOURCE_KEY REG_BIT(22) 4490 #define SP_YUV_FORMAT_BT709 REG_BIT(18) 4491 #define SP_YUV_ORDER_MASK REG_GENMASK(17, 16) 4492 #define SP_YUV_ORDER_YUYV REG_FIELD_PREP(SP_YUV_ORDER_MASK, 0) 4493 #define SP_YUV_ORDER_UYVY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 1) 4494 #define SP_YUV_ORDER_YVYU REG_FIELD_PREP(SP_YUV_ORDER_MASK, 2) 4495 #define SP_YUV_ORDER_VYUY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 3) 4496 #define SP_ROTATE_180 REG_BIT(15) 4497 #define SP_TILED REG_BIT(10) 4498 #define SP_MIRROR REG_BIT(8) /* CHV pipe B */ 4499 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184) 4500 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188) 4501 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c) 4502 #define SP_POS_Y_MASK REG_GENMASK(31, 16) 4503 #define SP_POS_Y(y) REG_FIELD_PREP(SP_POS_Y_MASK, (y)) 4504 #define SP_POS_X_MASK REG_GENMASK(15, 0) 4505 #define SP_POS_X(x) REG_FIELD_PREP(SP_POS_X_MASK, (x)) 4506 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190) 4507 #define SP_HEIGHT_MASK REG_GENMASK(31, 16) 4508 #define SP_HEIGHT(h) REG_FIELD_PREP(SP_HEIGHT_MASK, (h)) 4509 #define SP_WIDTH_MASK REG_GENMASK(15, 0) 4510 #define SP_WIDTH(w) REG_FIELD_PREP(SP_WIDTH_MASK, (w)) 4511 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194) 4512 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198) 4513 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c) 4514 #define SP_ADDR_MASK REG_GENMASK(31, 12) 4515 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0) 4516 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4) 4517 #define SP_OFFSET_Y_MASK REG_GENMASK(31, 16) 4518 #define SP_OFFSET_Y(y) REG_FIELD_PREP(SP_OFFSET_Y_MASK, (y)) 4519 #define SP_OFFSET_X_MASK REG_GENMASK(15, 0) 4520 #define SP_OFFSET_X(x) REG_FIELD_PREP(SP_OFFSET_X_MASK, (x)) 4521 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8) 4522 #define SP_CONST_ALPHA_ENABLE REG_BIT(31) 4523 #define SP_CONST_ALPHA_MASK REG_GENMASK(7, 0) 4524 #define SP_CONST_ALPHA(alpha) REG_FIELD_PREP(SP_CONST_ALPHA_MASK, (alpha)) 4525 #define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0) 4526 #define SP_CONTRAST_MASK REG_GENMASK(26, 18) 4527 #define SP_CONTRAST(x) REG_FIELD_PREP(SP_CONTRAST_MASK, (x)) /* u3.6 */ 4528 #define SP_BRIGHTNESS_MASK REG_GENMASK(7, 0) 4529 #define SP_BRIGHTNESS(x) REG_FIELD_PREP(SP_BRIGHTNESS_MASK, (x)) /* s8 */ 4530 #define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4) 4531 #define SP_SH_SIN_MASK REG_GENMASK(26, 16) 4532 #define SP_SH_SIN(x) REG_FIELD_PREP(SP_SH_SIN_MASK, (x)) /* s4.7 */ 4533 #define SP_SH_COS_MASK REG_GENMASK(9, 0) 4534 #define SP_SH_COS(x) REG_FIELD_PREP(SP_SH_COS_MASK, (x)) /* u3.7 */ 4535 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0) 4536 4537 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280) 4538 #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284) 4539 #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288) 4540 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c) 4541 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290) 4542 #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294) 4543 #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298) 4544 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c) 4545 #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0) 4546 #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4) 4547 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8) 4548 #define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0) 4549 #define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4) 4550 #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0) 4551 4552 #define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \ 4553 _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b)) 4554 #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \ 4555 _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b))) 4556 4557 #define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR) 4558 #define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF) 4559 #define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE) 4560 #define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS) 4561 #define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE) 4562 #define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL) 4563 #define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK) 4564 #define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF) 4565 #define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL) 4566 #define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF) 4567 #define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA) 4568 #define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0) 4569 #define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1) 4570 #define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */ 4571 4572 /* 4573 * CHV pipe B sprite CSC 4574 * 4575 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff| 4576 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff| 4577 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff| 4578 */ 4579 #define _MMIO_CHV_SPCSC(plane_id, reg) \ 4580 _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg)) 4581 4582 #define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900) 4583 #define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904) 4584 #define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908) 4585 #define SPCSC_OOFF_MASK REG_GENMASK(26, 16) 4586 #define SPCSC_OOFF(x) REG_FIELD_PREP(SPCSC_OOFF_MASK, (x) & 0x7ff) /* s11 */ 4587 #define SPCSC_IOFF_MASK REG_GENMASK(10, 0) 4588 #define SPCSC_IOFF(x) REG_FIELD_PREP(SPCSC_IOFF_MASK, (x) & 0x7ff) /* s11 */ 4589 4590 #define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c) 4591 #define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910) 4592 #define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914) 4593 #define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918) 4594 #define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c) 4595 #define SPCSC_C1_MASK REG_GENMASK(30, 16) 4596 #define SPCSC_C1(x) REG_FIELD_PREP(SPCSC_C1_MASK, (x) & 0x7fff) /* s3.12 */ 4597 #define SPCSC_C0_MASK REG_GENMASK(14, 0) 4598 #define SPCSC_C0(x) REG_FIELD_PREP(SPCSC_C0_MASK, (x) & 0x7fff) /* s3.12 */ 4599 4600 #define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920) 4601 #define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924) 4602 #define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928) 4603 #define SPCSC_IMAX_MASK REG_GENMASK(26, 16) 4604 #define SPCSC_IMAX(x) REG_FIELD_PREP(SPCSC_IMAX_MASK, (x) & 0x7ff) /* s11 */ 4605 #define SPCSC_IMIN_MASK REG_GENMASK(10, 0) 4606 #define SPCSC_IMIN(x) REG_FIELD_PREP(SPCSC_IMIN_MASK, (x) & 0x7ff) /* s11 */ 4607 4608 #define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c) 4609 #define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930) 4610 #define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934) 4611 #define SPCSC_OMAX_MASK REG_GENMASK(25, 16) 4612 #define SPCSC_OMAX(x) REG_FIELD_PREP(SPCSC_OMAX_MASK, (x)) /* u10 */ 4613 #define SPCSC_OMIN_MASK REG_GENMASK(9, 0) 4614 #define SPCSC_OMIN(x) REG_FIELD_PREP(SPCSC_OMIN_MASK, (x)) /* u10 */ 4615 4616 /* Skylake plane registers */ 4617 4618 #define _PLANE_CTL_1_A 0x70180 4619 #define _PLANE_CTL_2_A 0x70280 4620 #define _PLANE_CTL_3_A 0x70380 4621 #define PLANE_CTL_ENABLE REG_BIT(31) 4622 #define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ 4623 #define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */ 4624 #define PLANE_CTL_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-GLK */ 4625 #define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) 4626 /* 4627 * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition 4628 * expanded to include bit 23 as well. However, the shift-24 based values 4629 * correctly map to the same formats in ICL, as long as bit 23 is set to 0 4630 */ 4631 #define PLANE_CTL_FORMAT_MASK_SKL REG_GENMASK(27, 24) /* pre-icl */ 4632 #define PLANE_CTL_FORMAT_MASK_ICL REG_GENMASK(27, 23) /* icl+ */ 4633 #define PLANE_CTL_FORMAT_YUV422 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 0) 4634 #define PLANE_CTL_FORMAT_NV12 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 1) 4635 #define PLANE_CTL_FORMAT_XRGB_2101010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 2) 4636 #define PLANE_CTL_FORMAT_P010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 3) 4637 #define PLANE_CTL_FORMAT_XRGB_8888 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 4) 4638 #define PLANE_CTL_FORMAT_P012 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 5) 4639 #define PLANE_CTL_FORMAT_XRGB_16161616F REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 6) 4640 #define PLANE_CTL_FORMAT_P016 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 7) 4641 #define PLANE_CTL_FORMAT_XYUV REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 8) 4642 #define PLANE_CTL_FORMAT_INDEXED REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 12) 4643 #define PLANE_CTL_FORMAT_RGB_565 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 14) 4644 #define PLANE_CTL_FORMAT_Y210 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 1) 4645 #define PLANE_CTL_FORMAT_Y212 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 3) 4646 #define PLANE_CTL_FORMAT_Y216 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 5) 4647 #define PLANE_CTL_FORMAT_Y410 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 7) 4648 #define PLANE_CTL_FORMAT_Y412 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 9) 4649 #define PLANE_CTL_FORMAT_Y416 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 11) 4650 #define PLANE_CTL_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-GLK */ 4651 #define PLANE_CTL_KEY_ENABLE_MASK REG_GENMASK(22, 21) 4652 #define PLANE_CTL_KEY_ENABLE_SOURCE REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 1) 4653 #define PLANE_CTL_KEY_ENABLE_DESTINATION REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 2) 4654 #define PLANE_CTL_ORDER_RGBX REG_BIT(20) 4655 #define PLANE_CTL_YUV420_Y_PLANE REG_BIT(19) 4656 #define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) 4657 #define PLANE_CTL_YUV422_ORDER_MASK REG_GENMASK(17, 16) 4658 #define PLANE_CTL_YUV422_ORDER_YUYV REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 0) 4659 #define PLANE_CTL_YUV422_ORDER_UYVY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 1) 4660 #define PLANE_CTL_YUV422_ORDER_YVYU REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 2) 4661 #define PLANE_CTL_YUV422_ORDER_VYUY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 3) 4662 #define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE REG_BIT(15) 4663 #define PLANE_CTL_TRICKLE_FEED_DISABLE REG_BIT(14) 4664 #define PLANE_CTL_CLEAR_COLOR_DISABLE REG_BIT(13) /* TGL+ */ 4665 #define PLANE_CTL_PLANE_GAMMA_DISABLE REG_BIT(13) /* Pre-GLK */ 4666 #define PLANE_CTL_TILED_MASK REG_GENMASK(12, 10) 4667 #define PLANE_CTL_TILED_LINEAR REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 0) 4668 #define PLANE_CTL_TILED_X REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 1) 4669 #define PLANE_CTL_TILED_Y REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 4) 4670 #define PLANE_CTL_TILED_YF REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5) 4671 #define PLANE_CTL_TILED_4 REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5) 4672 #define PLANE_CTL_ASYNC_FLIP REG_BIT(9) 4673 #define PLANE_CTL_FLIP_HORIZONTAL REG_BIT(8) 4674 #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE REG_BIT(4) /* TGL+ */ 4675 #define PLANE_CTL_ALPHA_MASK REG_GENMASK(5, 4) /* Pre-GLK */ 4676 #define PLANE_CTL_ALPHA_DISABLE REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 0) 4677 #define PLANE_CTL_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 2) 4678 #define PLANE_CTL_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 3) 4679 #define PLANE_CTL_ROTATE_MASK REG_GENMASK(1, 0) 4680 #define PLANE_CTL_ROTATE_0 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 0) 4681 #define PLANE_CTL_ROTATE_90 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1) 4682 #define PLANE_CTL_ROTATE_180 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2) 4683 #define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3) 4684 #define _PLANE_STRIDE_1_A 0x70188 4685 #define _PLANE_STRIDE_2_A 0x70288 4686 #define _PLANE_STRIDE_3_A 0x70388 4687 #define PLANE_STRIDE__MASK REG_GENMASK(11, 0) 4688 #define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride)) 4689 #define _PLANE_POS_1_A 0x7018c 4690 #define _PLANE_POS_2_A 0x7028c 4691 #define _PLANE_POS_3_A 0x7038c 4692 #define PLANE_POS_Y_MASK REG_GENMASK(31, 16) 4693 #define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y)) 4694 #define PLANE_POS_X_MASK REG_GENMASK(15, 0) 4695 #define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x)) 4696 #define _PLANE_SIZE_1_A 0x70190 4697 #define _PLANE_SIZE_2_A 0x70290 4698 #define _PLANE_SIZE_3_A 0x70390 4699 #define PLANE_HEIGHT_MASK REG_GENMASK(31, 16) 4700 #define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h)) 4701 #define PLANE_WIDTH_MASK REG_GENMASK(15, 0) 4702 #define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w)) 4703 #define _PLANE_SURF_1_A 0x7019c 4704 #define _PLANE_SURF_2_A 0x7029c 4705 #define _PLANE_SURF_3_A 0x7039c 4706 #define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12) 4707 #define PLANE_SURF_DECRYPT REG_BIT(2) 4708 #define _PLANE_OFFSET_1_A 0x701a4 4709 #define _PLANE_OFFSET_2_A 0x702a4 4710 #define _PLANE_OFFSET_3_A 0x703a4 4711 #define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16) 4712 #define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y)) 4713 #define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0) 4714 #define PLANE_OFFSET_X(x) REG_FIELD_PREP(PLANE_OFFSET_X_MASK, (x)) 4715 #define _PLANE_KEYVAL_1_A 0x70194 4716 #define _PLANE_KEYVAL_2_A 0x70294 4717 #define _PLANE_KEYMSK_1_A 0x70198 4718 #define _PLANE_KEYMSK_2_A 0x70298 4719 #define PLANE_KEYMSK_ALPHA_ENABLE (1 << 31) 4720 #define _PLANE_KEYMAX_1_A 0x701a0 4721 #define _PLANE_KEYMAX_2_A 0x702a0 4722 #define PLANE_KEYMAX_ALPHA(a) ((a) << 24) 4723 #define _PLANE_CC_VAL_1_A 0x701b4 4724 #define _PLANE_CC_VAL_2_A 0x702b4 4725 #define _PLANE_AUX_DIST_1_A 0x701c0 4726 #define PLANE_AUX_DISTANCE_MASK REG_GENMASK(31, 12) 4727 #define PLANE_AUX_STRIDE_MASK REG_GENMASK(11, 0) 4728 #define PLANE_AUX_STRIDE(stride) REG_FIELD_PREP(PLANE_AUX_STRIDE_MASK, (stride)) 4729 #define _PLANE_AUX_DIST_2_A 0x702c0 4730 #define _PLANE_AUX_OFFSET_1_A 0x701c4 4731 #define _PLANE_AUX_OFFSET_2_A 0x702c4 4732 #define _PLANE_CUS_CTL_1_A 0x701c8 4733 #define _PLANE_CUS_CTL_2_A 0x702c8 4734 #define PLANE_CUS_ENABLE REG_BIT(31) 4735 #define PLANE_CUS_Y_PLANE_MASK REG_BIT(30) 4736 #define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0) 4737 #define PLANE_CUS_Y_PLANE_5_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1) 4738 #define PLANE_CUS_Y_PLANE_6_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0) 4739 #define PLANE_CUS_Y_PLANE_7_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1) 4740 #define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19) 4741 #define PLANE_CUS_HPHASE_MASK REG_GENMASK(17, 16) 4742 #define PLANE_CUS_HPHASE_0 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0) 4743 #define PLANE_CUS_HPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1) 4744 #define PLANE_CUS_HPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2) 4745 #define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15) 4746 #define PLANE_CUS_VPHASE_MASK REG_GENMASK(13, 12) 4747 #define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0) 4748 #define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1) 4749 #define PLANE_CUS_VPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2) 4750 #define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */ 4751 #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */ 4752 #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */ 4753 #define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */ 4754 #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) 4755 #define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */ 4756 #define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21) /* ICL+ */ 4757 #define PLANE_COLOR_INPUT_CSC_ENABLE REG_BIT(20) /* ICL+ */ 4758 #define PLANE_COLOR_CSC_MODE_MASK REG_GENMASK(19, 17) 4759 #define PLANE_COLOR_CSC_MODE_BYPASS REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0) 4760 #define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 1) 4761 #define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 2) 4762 #define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 3) 4763 #define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 4) 4764 #define PLANE_COLOR_PLANE_GAMMA_DISABLE REG_BIT(13) 4765 #define PLANE_COLOR_ALPHA_MASK REG_GENMASK(5, 4) 4766 #define PLANE_COLOR_ALPHA_DISABLE REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0) 4767 #define PLANE_COLOR_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 2) 4768 #define PLANE_COLOR_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 3) 4769 #define _PLANE_BUF_CFG_1_A 0x7027c 4770 #define _PLANE_BUF_CFG_2_A 0x7037c 4771 #define _PLANE_NV12_BUF_CFG_1_A 0x70278 4772 #define _PLANE_NV12_BUF_CFG_2_A 0x70378 4773 4774 #define _PLANE_CC_VAL_1_B 0x711b4 4775 #define _PLANE_CC_VAL_2_B 0x712b4 4776 #define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4) 4777 #define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4) 4778 #define PLANE_CC_VAL(pipe, plane, dw) \ 4779 _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw))) 4780 4781 /* Input CSC Register Definitions */ 4782 #define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0 4783 #define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0 4784 4785 #define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0 4786 #define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0 4787 4788 #define _PLANE_INPUT_CSC_RY_GY_1(pipe) \ 4789 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \ 4790 _PLANE_INPUT_CSC_RY_GY_1_B) 4791 #define _PLANE_INPUT_CSC_RY_GY_2(pipe) \ 4792 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \ 4793 _PLANE_INPUT_CSC_RY_GY_2_B) 4794 4795 #define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \ 4796 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \ 4797 _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4) 4798 4799 #define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8 4800 #define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8 4801 4802 #define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8 4803 #define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8 4804 4805 #define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \ 4806 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \ 4807 _PLANE_INPUT_CSC_PREOFF_HI_1_B) 4808 #define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \ 4809 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \ 4810 _PLANE_INPUT_CSC_PREOFF_HI_2_B) 4811 #define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \ 4812 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \ 4813 _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4) 4814 4815 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204 4816 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304 4817 4818 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204 4819 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304 4820 4821 #define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \ 4822 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \ 4823 _PLANE_INPUT_CSC_POSTOFF_HI_1_B) 4824 #define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \ 4825 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \ 4826 _PLANE_INPUT_CSC_POSTOFF_HI_2_B) 4827 #define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \ 4828 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \ 4829 _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4) 4830 4831 #define _PLANE_CTL_1_B 0x71180 4832 #define _PLANE_CTL_2_B 0x71280 4833 #define _PLANE_CTL_3_B 0x71380 4834 #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B) 4835 #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B) 4836 #define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B) 4837 #define PLANE_CTL(pipe, plane) \ 4838 _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) 4839 4840 #define _PLANE_STRIDE_1_B 0x71188 4841 #define _PLANE_STRIDE_2_B 0x71288 4842 #define _PLANE_STRIDE_3_B 0x71388 4843 #define _PLANE_STRIDE_1(pipe) \ 4844 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B) 4845 #define _PLANE_STRIDE_2(pipe) \ 4846 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) 4847 #define _PLANE_STRIDE_3(pipe) \ 4848 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B) 4849 #define PLANE_STRIDE(pipe, plane) \ 4850 _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) 4851 4852 #define _PLANE_POS_1_B 0x7118c 4853 #define _PLANE_POS_2_B 0x7128c 4854 #define _PLANE_POS_3_B 0x7138c 4855 #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B) 4856 #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B) 4857 #define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B) 4858 #define PLANE_POS(pipe, plane) \ 4859 _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) 4860 4861 #define _PLANE_SIZE_1_B 0x71190 4862 #define _PLANE_SIZE_2_B 0x71290 4863 #define _PLANE_SIZE_3_B 0x71390 4864 #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B) 4865 #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) 4866 #define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B) 4867 #define PLANE_SIZE(pipe, plane) \ 4868 _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) 4869 4870 #define _PLANE_SURF_1_B 0x7119c 4871 #define _PLANE_SURF_2_B 0x7129c 4872 #define _PLANE_SURF_3_B 0x7139c 4873 #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B) 4874 #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B) 4875 #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B) 4876 #define PLANE_SURF(pipe, plane) \ 4877 _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe)) 4878 4879 #define _PLANE_OFFSET_1_B 0x711a4 4880 #define _PLANE_OFFSET_2_B 0x712a4 4881 #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B) 4882 #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B) 4883 #define PLANE_OFFSET(pipe, plane) \ 4884 _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe)) 4885 4886 #define _PLANE_KEYVAL_1_B 0x71194 4887 #define _PLANE_KEYVAL_2_B 0x71294 4888 #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B) 4889 #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B) 4890 #define PLANE_KEYVAL(pipe, plane) \ 4891 _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe)) 4892 4893 #define _PLANE_KEYMSK_1_B 0x71198 4894 #define _PLANE_KEYMSK_2_B 0x71298 4895 #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B) 4896 #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B) 4897 #define PLANE_KEYMSK(pipe, plane) \ 4898 _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe)) 4899 4900 #define _PLANE_KEYMAX_1_B 0x711a0 4901 #define _PLANE_KEYMAX_2_B 0x712a0 4902 #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B) 4903 #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B) 4904 #define PLANE_KEYMAX(pipe, plane) \ 4905 _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe)) 4906 4907 #define _PLANE_BUF_CFG_1_B 0x7127c 4908 #define _PLANE_BUF_CFG_2_B 0x7137c 4909 /* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */ 4910 #define PLANE_BUF_END_MASK REG_GENMASK(27, 16) 4911 #define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end)) 4912 #define PLANE_BUF_START_MASK REG_GENMASK(11, 0) 4913 #define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start)) 4914 #define _PLANE_BUF_CFG_1(pipe) \ 4915 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B) 4916 #define _PLANE_BUF_CFG_2(pipe) \ 4917 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B) 4918 #define PLANE_BUF_CFG(pipe, plane) \ 4919 _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe)) 4920 4921 #define _PLANE_NV12_BUF_CFG_1_B 0x71278 4922 #define _PLANE_NV12_BUF_CFG_2_B 0x71378 4923 #define _PLANE_NV12_BUF_CFG_1(pipe) \ 4924 _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B) 4925 #define _PLANE_NV12_BUF_CFG_2(pipe) \ 4926 _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B) 4927 #define PLANE_NV12_BUF_CFG(pipe, plane) \ 4928 _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe)) 4929 4930 #define _PLANE_AUX_DIST_1_B 0x711c0 4931 #define _PLANE_AUX_DIST_2_B 0x712c0 4932 #define _PLANE_AUX_DIST_1(pipe) \ 4933 _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B) 4934 #define _PLANE_AUX_DIST_2(pipe) \ 4935 _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B) 4936 #define PLANE_AUX_DIST(pipe, plane) \ 4937 _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe)) 4938 4939 #define _PLANE_AUX_OFFSET_1_B 0x711c4 4940 #define _PLANE_AUX_OFFSET_2_B 0x712c4 4941 #define _PLANE_AUX_OFFSET_1(pipe) \ 4942 _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B) 4943 #define _PLANE_AUX_OFFSET_2(pipe) \ 4944 _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B) 4945 #define PLANE_AUX_OFFSET(pipe, plane) \ 4946 _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe)) 4947 4948 #define _PLANE_CUS_CTL_1_B 0x711c8 4949 #define _PLANE_CUS_CTL_2_B 0x712c8 4950 #define _PLANE_CUS_CTL_1(pipe) \ 4951 _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B) 4952 #define _PLANE_CUS_CTL_2(pipe) \ 4953 _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B) 4954 #define PLANE_CUS_CTL(pipe, plane) \ 4955 _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe)) 4956 4957 #define _PLANE_COLOR_CTL_1_B 0x711CC 4958 #define _PLANE_COLOR_CTL_2_B 0x712CC 4959 #define _PLANE_COLOR_CTL_3_B 0x713CC 4960 #define _PLANE_COLOR_CTL_1(pipe) \ 4961 _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B) 4962 #define _PLANE_COLOR_CTL_2(pipe) \ 4963 _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B) 4964 #define PLANE_COLOR_CTL(pipe, plane) \ 4965 _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe)) 4966 4967 #define _SEL_FETCH_PLANE_BASE_1_A 0x70890 4968 #define _SEL_FETCH_PLANE_BASE_2_A 0x708B0 4969 #define _SEL_FETCH_PLANE_BASE_3_A 0x708D0 4970 #define _SEL_FETCH_PLANE_BASE_4_A 0x708F0 4971 #define _SEL_FETCH_PLANE_BASE_5_A 0x70920 4972 #define _SEL_FETCH_PLANE_BASE_6_A 0x70940 4973 #define _SEL_FETCH_PLANE_BASE_7_A 0x70960 4974 #define _SEL_FETCH_PLANE_BASE_CUR_A 0x70880 4975 #define _SEL_FETCH_PLANE_BASE_1_B 0x71890 4976 4977 #define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \ 4978 _SEL_FETCH_PLANE_BASE_1_A, \ 4979 _SEL_FETCH_PLANE_BASE_2_A, \ 4980 _SEL_FETCH_PLANE_BASE_3_A, \ 4981 _SEL_FETCH_PLANE_BASE_4_A, \ 4982 _SEL_FETCH_PLANE_BASE_5_A, \ 4983 _SEL_FETCH_PLANE_BASE_6_A, \ 4984 _SEL_FETCH_PLANE_BASE_7_A, \ 4985 _SEL_FETCH_PLANE_BASE_CUR_A) 4986 #define _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe, _SEL_FETCH_PLANE_BASE_1_A, _SEL_FETCH_PLANE_BASE_1_B) 4987 #define _SEL_FETCH_PLANE_BASE(pipe, plane) (_SEL_FETCH_PLANE_BASE_1(pipe) - \ 4988 _SEL_FETCH_PLANE_BASE_1_A + \ 4989 _SEL_FETCH_PLANE_BASE_A(plane)) 4990 4991 #define _SEL_FETCH_PLANE_CTL_1_A 0x70890 4992 #define PLANE_SEL_FETCH_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 4993 _SEL_FETCH_PLANE_CTL_1_A - \ 4994 _SEL_FETCH_PLANE_BASE_1_A) 4995 #define PLANE_SEL_FETCH_CTL_ENABLE REG_BIT(31) 4996 4997 #define _SEL_FETCH_PLANE_POS_1_A 0x70894 4998 #define PLANE_SEL_FETCH_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 4999 _SEL_FETCH_PLANE_POS_1_A - \ 5000 _SEL_FETCH_PLANE_BASE_1_A) 5001 5002 #define _SEL_FETCH_PLANE_SIZE_1_A 0x70898 5003 #define PLANE_SEL_FETCH_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 5004 _SEL_FETCH_PLANE_SIZE_1_A - \ 5005 _SEL_FETCH_PLANE_BASE_1_A) 5006 5007 #define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089C 5008 #define PLANE_SEL_FETCH_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 5009 _SEL_FETCH_PLANE_OFFSET_1_A - \ 5010 _SEL_FETCH_PLANE_BASE_1_A) 5011 5012 /* SKL new cursor registers */ 5013 #define _CUR_BUF_CFG_A 0x7017c 5014 #define _CUR_BUF_CFG_B 0x7117c 5015 #define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B) 5016 5017 /* VBIOS regs */ 5018 #define VGACNTRL _MMIO(0x71400) 5019 # define VGA_DISP_DISABLE (1 << 31) 5020 # define VGA_2X_MODE (1 << 30) 5021 # define VGA_PIPE_B_SELECT (1 << 29) 5022 5023 #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400) 5024 5025 /* Ironlake */ 5026 5027 #define CPU_VGACNTRL _MMIO(0x41000) 5028 5029 #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030) 5030 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) 5031 #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */ 5032 #define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */ 5033 #define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */ 5034 #define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */ 5035 #define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */ 5036 #define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0) 5037 #define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0) 5038 #define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0) 5039 #define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0) 5040 5041 /* refresh rate hardware control */ 5042 #define RR_HW_CTL _MMIO(0x45300) 5043 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff 5044 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 5045 5046 #define FDI_PLL_BIOS_0 _MMIO(0x46000) 5047 #define FDI_PLL_FB_CLOCK_MASK 0xff 5048 #define FDI_PLL_BIOS_1 _MMIO(0x46004) 5049 #define FDI_PLL_BIOS_2 _MMIO(0x46008) 5050 #define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c) 5051 #define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010) 5052 #define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014) 5053 5054 #define PCH_3DCGDIS0 _MMIO(0x46020) 5055 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) 5056 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) 5057 5058 #define PCH_3DCGDIS1 _MMIO(0x46024) 5059 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) 5060 5061 #define FDI_PLL_FREQ_CTL _MMIO(0x46030) 5062 #define FDI_PLL_FREQ_CHANGE_REQUEST (1 << 24) 5063 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 5064 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff 5065 5066 5067 #define _PIPEA_DATA_M1 0x60030 5068 #define _PIPEA_DATA_N1 0x60034 5069 #define _PIPEA_DATA_M2 0x60038 5070 #define _PIPEA_DATA_N2 0x6003c 5071 #define _PIPEA_LINK_M1 0x60040 5072 #define _PIPEA_LINK_N1 0x60044 5073 #define _PIPEA_LINK_M2 0x60048 5074 #define _PIPEA_LINK_N2 0x6004c 5075 5076 /* PIPEB timing regs are same start from 0x61000 */ 5077 5078 #define _PIPEB_DATA_M1 0x61030 5079 #define _PIPEB_DATA_N1 0x61034 5080 #define _PIPEB_DATA_M2 0x61038 5081 #define _PIPEB_DATA_N2 0x6103c 5082 #define _PIPEB_LINK_M1 0x61040 5083 #define _PIPEB_LINK_N1 0x61044 5084 #define _PIPEB_LINK_M2 0x61048 5085 #define _PIPEB_LINK_N2 0x6104c 5086 5087 #define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1) 5088 #define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1) 5089 #define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2) 5090 #define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2) 5091 #define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1) 5092 #define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1) 5093 #define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2) 5094 #define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2) 5095 5096 /* CPU panel fitter */ 5097 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ 5098 #define _PFA_CTL_1 0x68080 5099 #define _PFB_CTL_1 0x68880 5100 #define PF_ENABLE (1 << 31) 5101 #define PF_PIPE_SEL_MASK_IVB (3 << 29) 5102 #define PF_PIPE_SEL_IVB(pipe) ((pipe) << 29) 5103 #define PF_FILTER_MASK (3 << 23) 5104 #define PF_FILTER_PROGRAMMED (0 << 23) 5105 #define PF_FILTER_MED_3x3 (1 << 23) 5106 #define PF_FILTER_EDGE_ENHANCE (2 << 23) 5107 #define PF_FILTER_EDGE_SOFTEN (3 << 23) 5108 #define _PFA_WIN_SZ 0x68074 5109 #define _PFB_WIN_SZ 0x68874 5110 #define _PFA_WIN_POS 0x68070 5111 #define _PFB_WIN_POS 0x68870 5112 #define _PFA_VSCALE 0x68084 5113 #define _PFB_VSCALE 0x68884 5114 #define _PFA_HSCALE 0x68090 5115 #define _PFB_HSCALE 0x68890 5116 5117 #define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) 5118 #define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) 5119 #define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) 5120 #define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) 5121 #define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) 5122 5123 #define _PSA_CTL 0x68180 5124 #define _PSB_CTL 0x68980 5125 #define PS_ENABLE (1 << 31) 5126 #define _PSA_WIN_SZ 0x68174 5127 #define _PSB_WIN_SZ 0x68974 5128 #define _PSA_WIN_POS 0x68170 5129 #define _PSB_WIN_POS 0x68970 5130 5131 #define PS_CTL(pipe) _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL) 5132 #define PS_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ) 5133 #define PS_WIN_POS(pipe) _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS) 5134 5135 /* 5136 * Skylake scalers 5137 */ 5138 #define _PS_1A_CTRL 0x68180 5139 #define _PS_2A_CTRL 0x68280 5140 #define _PS_1B_CTRL 0x68980 5141 #define _PS_2B_CTRL 0x68A80 5142 #define _PS_1C_CTRL 0x69180 5143 #define PS_SCALER_EN (1 << 31) 5144 #define SKL_PS_SCALER_MODE_MASK (3 << 28) 5145 #define SKL_PS_SCALER_MODE_DYN (0 << 28) 5146 #define SKL_PS_SCALER_MODE_HQ (1 << 28) 5147 #define SKL_PS_SCALER_MODE_NV12 (2 << 28) 5148 #define PS_SCALER_MODE_PLANAR (1 << 29) 5149 #define PS_SCALER_MODE_NORMAL (0 << 29) 5150 #define PS_PLANE_SEL_MASK (7 << 25) 5151 #define PS_PLANE_SEL(plane) (((plane) + 1) << 25) 5152 #define PS_FILTER_MASK (3 << 23) 5153 #define PS_FILTER_MEDIUM (0 << 23) 5154 #define PS_FILTER_PROGRAMMED (1 << 23) 5155 #define PS_FILTER_EDGE_ENHANCE (2 << 23) 5156 #define PS_FILTER_BILINEAR (3 << 23) 5157 #define PS_VERT3TAP (1 << 21) 5158 #define PS_VERT_INT_INVERT_FIELD1 (0 << 20) 5159 #define PS_VERT_INT_INVERT_FIELD0 (1 << 20) 5160 #define PS_PWRUP_PROGRESS (1 << 17) 5161 #define PS_V_FILTER_BYPASS (1 << 8) 5162 #define PS_VADAPT_EN (1 << 7) 5163 #define PS_VADAPT_MODE_MASK (3 << 5) 5164 #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5) 5165 #define PS_VADAPT_MODE_MOD_ADAPT (1 << 5) 5166 #define PS_VADAPT_MODE_MOST_ADAPT (3 << 5) 5167 #define PS_PLANE_Y_SEL_MASK (7 << 5) 5168 #define PS_PLANE_Y_SEL(plane) (((plane) + 1) << 5) 5169 #define PS_Y_VERT_FILTER_SELECT(set) ((set) << 4) 5170 #define PS_Y_HORZ_FILTER_SELECT(set) ((set) << 3) 5171 #define PS_UV_VERT_FILTER_SELECT(set) ((set) << 2) 5172 #define PS_UV_HORZ_FILTER_SELECT(set) ((set) << 1) 5173 5174 #define _PS_PWR_GATE_1A 0x68160 5175 #define _PS_PWR_GATE_2A 0x68260 5176 #define _PS_PWR_GATE_1B 0x68960 5177 #define _PS_PWR_GATE_2B 0x68A60 5178 #define _PS_PWR_GATE_1C 0x69160 5179 #define PS_PWR_GATE_DIS_OVERRIDE (1 << 31) 5180 #define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3) 5181 #define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3) 5182 #define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3) 5183 #define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3) 5184 #define PS_PWR_GATE_SLPEN_8 0 5185 #define PS_PWR_GATE_SLPEN_16 1 5186 #define PS_PWR_GATE_SLPEN_24 2 5187 #define PS_PWR_GATE_SLPEN_32 3 5188 5189 #define _PS_WIN_POS_1A 0x68170 5190 #define _PS_WIN_POS_2A 0x68270 5191 #define _PS_WIN_POS_1B 0x68970 5192 #define _PS_WIN_POS_2B 0x68A70 5193 #define _PS_WIN_POS_1C 0x69170 5194 5195 #define _PS_WIN_SZ_1A 0x68174 5196 #define _PS_WIN_SZ_2A 0x68274 5197 #define _PS_WIN_SZ_1B 0x68974 5198 #define _PS_WIN_SZ_2B 0x68A74 5199 #define _PS_WIN_SZ_1C 0x69174 5200 5201 #define _PS_VSCALE_1A 0x68184 5202 #define _PS_VSCALE_2A 0x68284 5203 #define _PS_VSCALE_1B 0x68984 5204 #define _PS_VSCALE_2B 0x68A84 5205 #define _PS_VSCALE_1C 0x69184 5206 5207 #define _PS_HSCALE_1A 0x68190 5208 #define _PS_HSCALE_2A 0x68290 5209 #define _PS_HSCALE_1B 0x68990 5210 #define _PS_HSCALE_2B 0x68A90 5211 #define _PS_HSCALE_1C 0x69190 5212 5213 #define _PS_VPHASE_1A 0x68188 5214 #define _PS_VPHASE_2A 0x68288 5215 #define _PS_VPHASE_1B 0x68988 5216 #define _PS_VPHASE_2B 0x68A88 5217 #define _PS_VPHASE_1C 0x69188 5218 #define PS_Y_PHASE(x) ((x) << 16) 5219 #define PS_UV_RGB_PHASE(x) ((x) << 0) 5220 #define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */ 5221 #define PS_PHASE_TRIP (1 << 0) 5222 5223 #define _PS_HPHASE_1A 0x68194 5224 #define _PS_HPHASE_2A 0x68294 5225 #define _PS_HPHASE_1B 0x68994 5226 #define _PS_HPHASE_2B 0x68A94 5227 #define _PS_HPHASE_1C 0x69194 5228 5229 #define _PS_ECC_STAT_1A 0x681D0 5230 #define _PS_ECC_STAT_2A 0x682D0 5231 #define _PS_ECC_STAT_1B 0x689D0 5232 #define _PS_ECC_STAT_2B 0x68AD0 5233 #define _PS_ECC_STAT_1C 0x691D0 5234 5235 #define _PS_COEF_SET0_INDEX_1A 0x68198 5236 #define _PS_COEF_SET0_INDEX_2A 0x68298 5237 #define _PS_COEF_SET0_INDEX_1B 0x68998 5238 #define _PS_COEF_SET0_INDEX_2B 0x68A98 5239 #define PS_COEE_INDEX_AUTO_INC (1 << 10) 5240 5241 #define _PS_COEF_SET0_DATA_1A 0x6819C 5242 #define _PS_COEF_SET0_DATA_2A 0x6829C 5243 #define _PS_COEF_SET0_DATA_1B 0x6899C 5244 #define _PS_COEF_SET0_DATA_2B 0x68A9C 5245 5246 #define _ID(id, a, b) _PICK_EVEN(id, a, b) 5247 #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \ 5248 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \ 5249 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL)) 5250 #define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \ 5251 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \ 5252 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B)) 5253 #define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \ 5254 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \ 5255 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B)) 5256 #define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \ 5257 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \ 5258 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B)) 5259 #define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \ 5260 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \ 5261 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B)) 5262 #define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \ 5263 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \ 5264 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B)) 5265 #define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \ 5266 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \ 5267 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B)) 5268 #define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \ 5269 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \ 5270 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B)) 5271 #define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \ 5272 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \ 5273 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)) 5274 #define GLK_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe, \ 5275 _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) + (set) * 8, \ 5276 _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) + (set) * 8) 5277 5278 #define GLK_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \ 5279 _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \ 5280 _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8) 5281 /* legacy palette */ 5282 #define _LGC_PALETTE_A 0x4a000 5283 #define _LGC_PALETTE_B 0x4a800 5284 /* see PALETTE_* for the bits */ 5285 #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4) 5286 5287 /* ilk/snb precision palette */ 5288 #define _PREC_PALETTE_A 0x4b000 5289 #define _PREC_PALETTE_B 0x4c000 5290 /* 10bit mode */ 5291 #define PREC_PALETTE_10_RED_MASK REG_GENMASK(29, 20) 5292 #define PREC_PALETTE_10_GREEN_MASK REG_GENMASK(19, 10) 5293 #define PREC_PALETTE_10_BLUE_MASK REG_GENMASK(9, 0) 5294 /* 12.4 interpolated mode ldw */ 5295 #define PREC_PALETTE_12P4_RED_LDW_MASK REG_GENMASK(29, 24) 5296 #define PREC_PALETTE_12P4_GREEN_LDW_MASK REG_GENMASK(19, 14) 5297 #define PREC_PALETTE_12P4_BLUE_LDW_MASK REG_GENMASK(9, 4) 5298 /* 12.4 interpolated mode udw */ 5299 #define PREC_PALETTE_12P4_RED_UDW_MASK REG_GENMASK(29, 20) 5300 #define PREC_PALETTE_12P4_GREEN_UDW_MASK REG_GENMASK(19, 10) 5301 #define PREC_PALETTE_12P4_BLUE_UDW_MASK REG_GENMASK(9, 0) 5302 #define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4) 5303 5304 #define _PREC_PIPEAGCMAX 0x4d000 5305 #define _PREC_PIPEBGCMAX 0x4d010 5306 #define PREC_PIPEGCMAX(pipe, i) _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4) /* u1.16 */ 5307 5308 #define _GAMMA_MODE_A 0x4a480 5309 #define _GAMMA_MODE_B 0x4ac80 5310 #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) 5311 #define PRE_CSC_GAMMA_ENABLE REG_BIT(31) /* icl+ */ 5312 #define POST_CSC_GAMMA_ENABLE REG_BIT(30) /* icl+ */ 5313 #define PALETTE_ANTICOL_DISABLE REG_BIT(15) /* skl+ */ 5314 #define GAMMA_MODE_MODE_MASK REG_GENMASK(1, 0) 5315 #define GAMMA_MODE_MODE_8BIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 0) 5316 #define GAMMA_MODE_MODE_10BIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 1) 5317 #define GAMMA_MODE_MODE_12BIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 2) 5318 #define GAMMA_MODE_MODE_SPLIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 3) /* ivb-bdw */ 5319 #define GAMMA_MODE_MODE_12BIT_MULTI_SEG REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 3) /* icl-tgl */ 5320 5321 /* Display Internal Timeout Register */ 5322 #define RM_TIMEOUT _MMIO(0x42060) 5323 #define MMIO_TIMEOUT_US(us) ((us) << 0) 5324 5325 /* interrupts */ 5326 #define DE_MASTER_IRQ_CONTROL (1 << 31) 5327 #define DE_SPRITEB_FLIP_DONE (1 << 29) 5328 #define DE_SPRITEA_FLIP_DONE (1 << 28) 5329 #define DE_PLANEB_FLIP_DONE (1 << 27) 5330 #define DE_PLANEA_FLIP_DONE (1 << 26) 5331 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane))) 5332 #define DE_PCU_EVENT (1 << 25) 5333 #define DE_GTT_FAULT (1 << 24) 5334 #define DE_POISON (1 << 23) 5335 #define DE_PERFORM_COUNTER (1 << 22) 5336 #define DE_PCH_EVENT (1 << 21) 5337 #define DE_AUX_CHANNEL_A (1 << 20) 5338 #define DE_DP_A_HOTPLUG (1 << 19) 5339 #define DE_GSE (1 << 18) 5340 #define DE_PIPEB_VBLANK (1 << 15) 5341 #define DE_PIPEB_EVEN_FIELD (1 << 14) 5342 #define DE_PIPEB_ODD_FIELD (1 << 13) 5343 #define DE_PIPEB_LINE_COMPARE (1 << 12) 5344 #define DE_PIPEB_VSYNC (1 << 11) 5345 #define DE_PIPEB_CRC_DONE (1 << 10) 5346 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) 5347 #define DE_PIPEA_VBLANK (1 << 7) 5348 #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe))) 5349 #define DE_PIPEA_EVEN_FIELD (1 << 6) 5350 #define DE_PIPEA_ODD_FIELD (1 << 5) 5351 #define DE_PIPEA_LINE_COMPARE (1 << 4) 5352 #define DE_PIPEA_VSYNC (1 << 3) 5353 #define DE_PIPEA_CRC_DONE (1 << 2) 5354 #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe))) 5355 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) 5356 #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe))) 5357 5358 /* More Ivybridge lolz */ 5359 #define DE_ERR_INT_IVB (1 << 30) 5360 #define DE_GSE_IVB (1 << 29) 5361 #define DE_PCH_EVENT_IVB (1 << 28) 5362 #define DE_DP_A_HOTPLUG_IVB (1 << 27) 5363 #define DE_AUX_CHANNEL_A_IVB (1 << 26) 5364 #define DE_EDP_PSR_INT_HSW (1 << 19) 5365 #define DE_SPRITEC_FLIP_DONE_IVB (1 << 14) 5366 #define DE_PLANEC_FLIP_DONE_IVB (1 << 13) 5367 #define DE_PIPEC_VBLANK_IVB (1 << 10) 5368 #define DE_SPRITEB_FLIP_DONE_IVB (1 << 9) 5369 #define DE_PLANEB_FLIP_DONE_IVB (1 << 8) 5370 #define DE_PIPEB_VBLANK_IVB (1 << 5) 5371 #define DE_SPRITEA_FLIP_DONE_IVB (1 << 4) 5372 #define DE_PLANEA_FLIP_DONE_IVB (1 << 3) 5373 #define DE_PLANE_FLIP_DONE_IVB(plane) (1 << (3 + 5 * (plane))) 5374 #define DE_PIPEA_VBLANK_IVB (1 << 0) 5375 #define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5)) 5376 5377 #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */ 5378 #define MASTER_INTERRUPT_ENABLE (1 << 31) 5379 5380 #define DEISR _MMIO(0x44000) 5381 #define DEIMR _MMIO(0x44004) 5382 #define DEIIR _MMIO(0x44008) 5383 #define DEIER _MMIO(0x4400c) 5384 5385 #define GTISR _MMIO(0x44010) 5386 #define GTIMR _MMIO(0x44014) 5387 #define GTIIR _MMIO(0x44018) 5388 #define GTIER _MMIO(0x4401c) 5389 5390 #define GEN8_MASTER_IRQ _MMIO(0x44200) 5391 #define GEN8_MASTER_IRQ_CONTROL (1 << 31) 5392 #define GEN8_PCU_IRQ (1 << 30) 5393 #define GEN8_DE_PCH_IRQ (1 << 23) 5394 #define GEN8_DE_MISC_IRQ (1 << 22) 5395 #define GEN8_DE_PORT_IRQ (1 << 20) 5396 #define GEN8_DE_PIPE_C_IRQ (1 << 18) 5397 #define GEN8_DE_PIPE_B_IRQ (1 << 17) 5398 #define GEN8_DE_PIPE_A_IRQ (1 << 16) 5399 #define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe))) 5400 #define GEN8_GT_VECS_IRQ (1 << 6) 5401 #define GEN8_GT_GUC_IRQ (1 << 5) 5402 #define GEN8_GT_PM_IRQ (1 << 4) 5403 #define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */ 5404 #define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */ 5405 #define GEN8_GT_BCS_IRQ (1 << 1) 5406 #define GEN8_GT_RCS_IRQ (1 << 0) 5407 5408 #define XELPD_DISPLAY_ERR_FATAL_MASK _MMIO(0x4421c) 5409 5410 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which))) 5411 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which))) 5412 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which))) 5413 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which))) 5414 5415 #define GEN8_RCS_IRQ_SHIFT 0 5416 #define GEN8_BCS_IRQ_SHIFT 16 5417 #define GEN8_VCS0_IRQ_SHIFT 0 /* NB: VCS1 in bspec! */ 5418 #define GEN8_VCS1_IRQ_SHIFT 16 /* NB: VCS2 in bpsec! */ 5419 #define GEN8_VECS_IRQ_SHIFT 0 5420 #define GEN8_WD_IRQ_SHIFT 16 5421 5422 #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe))) 5423 #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe))) 5424 #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe))) 5425 #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe))) 5426 #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31) 5427 #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29) 5428 #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28) 5429 #define XELPD_PIPE_SOFT_UNDERRUN (1 << 22) 5430 #define XELPD_PIPE_HARD_UNDERRUN (1 << 21) 5431 #define GEN8_PIPE_CURSOR_FAULT (1 << 10) 5432 #define GEN8_PIPE_SPRITE_FAULT (1 << 9) 5433 #define GEN8_PIPE_PRIMARY_FAULT (1 << 8) 5434 #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5) 5435 #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4) 5436 #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) 5437 #define GEN8_PIPE_VSYNC (1 << 1) 5438 #define GEN8_PIPE_VBLANK (1 << 0) 5439 #define GEN9_PIPE_CURSOR_FAULT (1 << 11) 5440 #define GEN11_PIPE_PLANE7_FAULT (1 << 22) 5441 #define GEN11_PIPE_PLANE6_FAULT (1 << 21) 5442 #define GEN11_PIPE_PLANE5_FAULT (1 << 20) 5443 #define GEN9_PIPE_PLANE4_FAULT (1 << 10) 5444 #define GEN9_PIPE_PLANE3_FAULT (1 << 9) 5445 #define GEN9_PIPE_PLANE2_FAULT (1 << 8) 5446 #define GEN9_PIPE_PLANE1_FAULT (1 << 7) 5447 #define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6) 5448 #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5) 5449 #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4) 5450 #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3) 5451 #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p))) 5452 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ 5453 (GEN8_PIPE_CURSOR_FAULT | \ 5454 GEN8_PIPE_SPRITE_FAULT | \ 5455 GEN8_PIPE_PRIMARY_FAULT) 5456 #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \ 5457 (GEN9_PIPE_CURSOR_FAULT | \ 5458 GEN9_PIPE_PLANE4_FAULT | \ 5459 GEN9_PIPE_PLANE3_FAULT | \ 5460 GEN9_PIPE_PLANE2_FAULT | \ 5461 GEN9_PIPE_PLANE1_FAULT) 5462 #define GEN11_DE_PIPE_IRQ_FAULT_ERRORS \ 5463 (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \ 5464 GEN11_PIPE_PLANE7_FAULT | \ 5465 GEN11_PIPE_PLANE6_FAULT | \ 5466 GEN11_PIPE_PLANE5_FAULT) 5467 #define RKL_DE_PIPE_IRQ_FAULT_ERRORS \ 5468 (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \ 5469 GEN11_PIPE_PLANE5_FAULT) 5470 5471 #define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A) 5472 #define _HPD_PIN_TC(hpd_pin) ((hpd_pin) - HPD_PORT_TC1) 5473 5474 #define GEN8_DE_PORT_ISR _MMIO(0x44440) 5475 #define GEN8_DE_PORT_IMR _MMIO(0x44444) 5476 #define GEN8_DE_PORT_IIR _MMIO(0x44448) 5477 #define GEN8_DE_PORT_IER _MMIO(0x4444c) 5478 #define DSI1_NON_TE (1 << 31) 5479 #define DSI0_NON_TE (1 << 30) 5480 #define ICL_AUX_CHANNEL_E (1 << 29) 5481 #define ICL_AUX_CHANNEL_F (1 << 28) 5482 #define GEN9_AUX_CHANNEL_D (1 << 27) 5483 #define GEN9_AUX_CHANNEL_C (1 << 26) 5484 #define GEN9_AUX_CHANNEL_B (1 << 25) 5485 #define DSI1_TE (1 << 24) 5486 #define DSI0_TE (1 << 23) 5487 #define GEN8_DE_PORT_HOTPLUG(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin)) 5488 #define BXT_DE_PORT_HOTPLUG_MASK (GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \ 5489 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \ 5490 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)) 5491 #define BDW_DE_PORT_HOTPLUG_MASK GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) 5492 #define BXT_DE_PORT_GMBUS (1 << 1) 5493 #define GEN8_AUX_CHANNEL_A (1 << 0) 5494 #define TGL_DE_PORT_AUX_USBC6 REG_BIT(13) 5495 #define XELPD_DE_PORT_AUX_DDIE REG_BIT(13) 5496 #define TGL_DE_PORT_AUX_USBC5 REG_BIT(12) 5497 #define XELPD_DE_PORT_AUX_DDID REG_BIT(12) 5498 #define TGL_DE_PORT_AUX_USBC4 REG_BIT(11) 5499 #define TGL_DE_PORT_AUX_USBC3 REG_BIT(10) 5500 #define TGL_DE_PORT_AUX_USBC2 REG_BIT(9) 5501 #define TGL_DE_PORT_AUX_USBC1 REG_BIT(8) 5502 #define TGL_DE_PORT_AUX_DDIC REG_BIT(2) 5503 #define TGL_DE_PORT_AUX_DDIB REG_BIT(1) 5504 #define TGL_DE_PORT_AUX_DDIA REG_BIT(0) 5505 5506 #define GEN8_DE_MISC_ISR _MMIO(0x44460) 5507 #define GEN8_DE_MISC_IMR _MMIO(0x44464) 5508 #define GEN8_DE_MISC_IIR _MMIO(0x44468) 5509 #define GEN8_DE_MISC_IER _MMIO(0x4446c) 5510 #define GEN8_DE_MISC_GSE (1 << 27) 5511 #define GEN8_DE_EDP_PSR (1 << 19) 5512 5513 #define GEN8_PCU_ISR _MMIO(0x444e0) 5514 #define GEN8_PCU_IMR _MMIO(0x444e4) 5515 #define GEN8_PCU_IIR _MMIO(0x444e8) 5516 #define GEN8_PCU_IER _MMIO(0x444ec) 5517 5518 #define GEN11_GU_MISC_ISR _MMIO(0x444f0) 5519 #define GEN11_GU_MISC_IMR _MMIO(0x444f4) 5520 #define GEN11_GU_MISC_IIR _MMIO(0x444f8) 5521 #define GEN11_GU_MISC_IER _MMIO(0x444fc) 5522 #define GEN11_GU_MISC_GSE (1 << 27) 5523 5524 #define GEN11_GFX_MSTR_IRQ _MMIO(0x190010) 5525 #define GEN11_MASTER_IRQ (1 << 31) 5526 #define GEN11_PCU_IRQ (1 << 30) 5527 #define GEN11_GU_MISC_IRQ (1 << 29) 5528 #define GEN11_DISPLAY_IRQ (1 << 16) 5529 #define GEN11_GT_DW_IRQ(x) (1 << (x)) 5530 #define GEN11_GT_DW1_IRQ (1 << 1) 5531 #define GEN11_GT_DW0_IRQ (1 << 0) 5532 5533 #define DG1_MSTR_TILE_INTR _MMIO(0x190008) 5534 #define DG1_MSTR_IRQ REG_BIT(31) 5535 #define DG1_MSTR_TILE(t) REG_BIT(t) 5536 5537 #define GEN11_DISPLAY_INT_CTL _MMIO(0x44200) 5538 #define GEN11_DISPLAY_IRQ_ENABLE (1 << 31) 5539 #define GEN11_AUDIO_CODEC_IRQ (1 << 24) 5540 #define GEN11_DE_PCH_IRQ (1 << 23) 5541 #define GEN11_DE_MISC_IRQ (1 << 22) 5542 #define GEN11_DE_HPD_IRQ (1 << 21) 5543 #define GEN11_DE_PORT_IRQ (1 << 20) 5544 #define GEN11_DE_PIPE_C (1 << 18) 5545 #define GEN11_DE_PIPE_B (1 << 17) 5546 #define GEN11_DE_PIPE_A (1 << 16) 5547 5548 #define GEN11_DE_HPD_ISR _MMIO(0x44470) 5549 #define GEN11_DE_HPD_IMR _MMIO(0x44474) 5550 #define GEN11_DE_HPD_IIR _MMIO(0x44478) 5551 #define GEN11_DE_HPD_IER _MMIO(0x4447c) 5552 #define GEN11_TC_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin)) 5553 #define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(HPD_PORT_TC6) | \ 5554 GEN11_TC_HOTPLUG(HPD_PORT_TC5) | \ 5555 GEN11_TC_HOTPLUG(HPD_PORT_TC4) | \ 5556 GEN11_TC_HOTPLUG(HPD_PORT_TC3) | \ 5557 GEN11_TC_HOTPLUG(HPD_PORT_TC2) | \ 5558 GEN11_TC_HOTPLUG(HPD_PORT_TC1)) 5559 #define GEN11_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin)) 5560 #define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(HPD_PORT_TC6) | \ 5561 GEN11_TBT_HOTPLUG(HPD_PORT_TC5) | \ 5562 GEN11_TBT_HOTPLUG(HPD_PORT_TC4) | \ 5563 GEN11_TBT_HOTPLUG(HPD_PORT_TC3) | \ 5564 GEN11_TBT_HOTPLUG(HPD_PORT_TC2) | \ 5565 GEN11_TBT_HOTPLUG(HPD_PORT_TC1)) 5566 5567 #define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030) 5568 #define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038) 5569 #define GEN11_HOTPLUG_CTL_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4)) 5570 #define GEN11_HOTPLUG_CTL_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4)) 5571 #define GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4)) 5572 #define GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin) (0 << (_HPD_PIN_TC(hpd_pin) * 4)) 5573 5574 #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004) 5575 /* Required on all Ironlake and Sandybridge according to the B-Spec. */ 5576 #define ILK_ELPIN_409_SELECT (1 << 25) 5577 #define ILK_DPARB_GATE (1 << 22) 5578 #define ILK_VSDPFD_FULL (1 << 21) 5579 #define FUSE_STRAP _MMIO(0x42014) 5580 #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31) 5581 #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30) 5582 #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29) 5583 #define IVB_PIPE_C_DISABLE (1 << 28) 5584 #define ILK_HDCP_DISABLE (1 << 25) 5585 #define ILK_eDP_A_DISABLE (1 << 24) 5586 #define HSW_CDCLK_LIMIT (1 << 24) 5587 #define ILK_DESKTOP (1 << 23) 5588 #define HSW_CPU_SSC_ENABLE (1 << 21) 5589 5590 #define FUSE_STRAP3 _MMIO(0x42020) 5591 #define HSW_REF_CLK_SELECT (1 << 1) 5592 5593 #define ILK_DSPCLK_GATE_D _MMIO(0x42020) 5594 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) 5595 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) 5596 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8) 5597 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7) 5598 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5) 5599 5600 #define IVB_CHICKEN3 _MMIO(0x4200c) 5601 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) 5602 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) 5603 5604 #define CHICKEN_PAR1_1 _MMIO(0x42080) 5605 #define IGNORE_KVMR_PIPE_A REG_BIT(23) 5606 #define KBL_ARB_FILL_SPARE_22 REG_BIT(22) 5607 #define DIS_RAM_BYPASS_PSR2_MAN_TRACK (1 << 16) 5608 #define SKL_DE_COMPRESSED_HASH_MODE (1 << 15) 5609 #define DPA_MASK_VBLANK_SRD (1 << 15) 5610 #define FORCE_ARB_IDLE_PLANES (1 << 14) 5611 #define SKL_EDP_PSR_FIX_RDWRAP (1 << 3) 5612 #define IGNORE_PSR2_HW_TRACKING (1 << 1) 5613 5614 #define CHICKEN_PAR2_1 _MMIO(0x42090) 5615 #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14) 5616 5617 #define CHICKEN_MISC_2 _MMIO(0x42084) 5618 #define KBL_ARB_FILL_SPARE_14 REG_BIT(14) 5619 #define KBL_ARB_FILL_SPARE_13 REG_BIT(13) 5620 #define GLK_CL2_PWR_DOWN (1 << 12) 5621 #define GLK_CL1_PWR_DOWN (1 << 11) 5622 #define GLK_CL0_PWR_DOWN (1 << 10) 5623 5624 #define CHICKEN_MISC_4 _MMIO(0x4208c) 5625 #define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13) 5626 #define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0) 5627 #define CHICKEN_FBC_STRIDE(x) REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x)) 5628 5629 #define _CHICKEN_PIPESL_1_A 0x420b0 5630 #define _CHICKEN_PIPESL_1_B 0x420b4 5631 #define HSW_PRI_STRETCH_MAX_MASK REG_GENMASK(28, 27) 5632 #define HSW_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0) 5633 #define HSW_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1) 5634 #define HSW_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2) 5635 #define HSW_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3) 5636 #define HSW_SPR_STRETCH_MAX_MASK REG_GENMASK(26, 25) 5637 #define HSW_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0) 5638 #define HSW_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1) 5639 #define HSW_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2) 5640 #define HSW_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3) 5641 #define HSW_FBCQ_DIS (1 << 22) 5642 #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0) 5643 #define SKL_PLANE1_STRETCH_MAX_MASK REG_GENMASK(1, 0) 5644 #define SKL_PLANE1_STRETCH_MAX_X8 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0) 5645 #define SKL_PLANE1_STRETCH_MAX_X4 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1) 5646 #define SKL_PLANE1_STRETCH_MAX_X2 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2) 5647 #define SKL_PLANE1_STRETCH_MAX_X1 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3) 5648 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) 5649 5650 #define _CHICKEN_TRANS_A 0x420c0 5651 #define _CHICKEN_TRANS_B 0x420c4 5652 #define _CHICKEN_TRANS_C 0x420c8 5653 #define _CHICKEN_TRANS_EDP 0x420cc 5654 #define _CHICKEN_TRANS_D 0x420d8 5655 #define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \ 5656 [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \ 5657 [TRANSCODER_A] = _CHICKEN_TRANS_A, \ 5658 [TRANSCODER_B] = _CHICKEN_TRANS_B, \ 5659 [TRANSCODER_C] = _CHICKEN_TRANS_C, \ 5660 [TRANSCODER_D] = _CHICKEN_TRANS_D)) 5661 5662 #define _MTL_CHICKEN_TRANS_A 0x604e0 5663 #define _MTL_CHICKEN_TRANS_B 0x614e0 5664 #define MTL_CHICKEN_TRANS(trans) _MMIO_TRANS((trans), \ 5665 _MTL_CHICKEN_TRANS_A, \ 5666 _MTL_CHICKEN_TRANS_B) 5667 5668 #define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) 5669 #define HSW_FRAME_START_DELAY(x) REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x) 5670 #define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */ 5671 #define FECSTALL_DIS_DPTSTREAM_DPTTG REG_BIT(23) 5672 #define DDI_TRAINING_OVERRIDE_ENABLE REG_BIT(19) 5673 #define ADLP_1_BASED_X_GRANULARITY REG_BIT(18) 5674 #define DDI_TRAINING_OVERRIDE_VALUE REG_BIT(18) 5675 #define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /* CHICKEN_TRANS_A only */ 5676 #define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */ 5677 #define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15) 5678 #define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12) 5679 5680 #define DISP_ARB_CTL _MMIO(0x45000) 5681 #define DISP_FBC_MEMORY_WAKE (1 << 31) 5682 #define DISP_TILE_SURFACE_SWIZZLING (1 << 13) 5683 #define DISP_FBC_WM_DIS (1 << 15) 5684 #define DISP_ARB_CTL2 _MMIO(0x45004) 5685 #define DISP_DATA_PARTITION_5_6 (1 << 6) 5686 #define DISP_IPC_ENABLE (1 << 3) 5687 5688 /* 5689 * The below are numbered starting from "S1" on gen11/gen12, but starting 5690 * with display 13, the bspec switches to a 0-based numbering scheme 5691 * (although the addresses stay the same so new S0 = old S1, new S1 = old S2). 5692 * We'll just use the 0-based numbering here for all platforms since it's the 5693 * way things will be named by the hardware team going forward, plus it's more 5694 * consistent with how most of the rest of our registers are named. 5695 */ 5696 #define _DBUF_CTL_S0 0x45008 5697 #define _DBUF_CTL_S1 0x44FE8 5698 #define _DBUF_CTL_S2 0x44300 5699 #define _DBUF_CTL_S3 0x44304 5700 #define DBUF_CTL_S(slice) _MMIO(_PICK(slice, \ 5701 _DBUF_CTL_S0, \ 5702 _DBUF_CTL_S1, \ 5703 _DBUF_CTL_S2, \ 5704 _DBUF_CTL_S3)) 5705 #define DBUF_POWER_REQUEST REG_BIT(31) 5706 #define DBUF_POWER_STATE REG_BIT(30) 5707 #define DBUF_TRACKER_STATE_SERVICE_MASK REG_GENMASK(23, 19) 5708 #define DBUF_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_TRACKER_STATE_SERVICE_MASK, x) 5709 #define DBUF_MIN_TRACKER_STATE_SERVICE_MASK REG_GENMASK(18, 16) /* ADL-P+ */ 5710 #define DBUF_MIN_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) /* ADL-P+ */ 5711 5712 #define GEN7_MSG_CTL _MMIO(0x45010) 5713 #define WAIT_FOR_PCH_RESET_ACK (1 << 1) 5714 #define WAIT_FOR_PCH_FLR_ACK (1 << 0) 5715 5716 #define _BW_BUDDY0_CTL 0x45130 5717 #define _BW_BUDDY1_CTL 0x45140 5718 #define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \ 5719 _BW_BUDDY0_CTL, \ 5720 _BW_BUDDY1_CTL)) 5721 #define BW_BUDDY_DISABLE REG_BIT(31) 5722 #define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16) 5723 #define BW_BUDDY_TLB_REQ_TIMER(x) REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, x) 5724 5725 #define _BW_BUDDY0_PAGE_MASK 0x45134 5726 #define _BW_BUDDY1_PAGE_MASK 0x45144 5727 #define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \ 5728 _BW_BUDDY0_PAGE_MASK, \ 5729 _BW_BUDDY1_PAGE_MASK)) 5730 5731 #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) 5732 #define MTL_RESET_PICA_HANDSHAKE_EN REG_BIT(6) 5733 #define RESET_PCH_HANDSHAKE_ENABLE REG_BIT(4) 5734 5735 #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430) 5736 #define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30) 5737 #define LATENCY_REPORTING_REMOVED_PIPE_C REG_BIT(25) 5738 #define LATENCY_REPORTING_REMOVED_PIPE_B REG_BIT(24) 5739 #define LATENCY_REPORTING_REMOVED_PIPE_A REG_BIT(23) 5740 #define ICL_DELAY_PMRSP REG_BIT(22) 5741 #define DISABLE_FLR_SRC REG_BIT(15) 5742 #define MASK_WAKEMEM REG_BIT(13) 5743 #define DDI_CLOCK_REG_ACCESS REG_BIT(7) 5744 5745 #define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434) 5746 #define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27) 5747 #define DCPR_MASK_LPMODE REG_BIT(26) 5748 #define DCPR_SEND_RESP_IMM REG_BIT(25) 5749 #define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24) 5750 5751 #define SKL_DFSM _MMIO(0x51000) 5752 #define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27) 5753 #define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25) 5754 #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23) 5755 #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23) 5756 #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23) 5757 #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23) 5758 #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23) 5759 #define ICL_DFSM_DMC_DISABLE (1 << 23) 5760 #define SKL_DFSM_PIPE_A_DISABLE (1 << 30) 5761 #define SKL_DFSM_PIPE_B_DISABLE (1 << 21) 5762 #define SKL_DFSM_PIPE_C_DISABLE (1 << 28) 5763 #define TGL_DFSM_PIPE_D_DISABLE (1 << 22) 5764 #define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7) 5765 5766 #define SKL_DSSM _MMIO(0x51004) 5767 #define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29) 5768 #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29) 5769 #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29) 5770 #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29) 5771 5772 #define GMD_ID_DISPLAY _MMIO(0x510a0) 5773 #define GMD_ID_ARCH_MASK REG_GENMASK(31, 22) 5774 #define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14) 5775 #define GMD_ID_STEP REG_GENMASK(5, 0) 5776 5777 /*GEN11 chicken */ 5778 #define _PIPEA_CHICKEN 0x70038 5779 #define _PIPEB_CHICKEN 0x71038 5780 #define _PIPEC_CHICKEN 0x72038 5781 #define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\ 5782 _PIPEB_CHICKEN) 5783 #define UNDERRUN_RECOVERY_DISABLE_ADLP REG_BIT(30) 5784 #define UNDERRUN_RECOVERY_ENABLE_DG2 REG_BIT(30) 5785 #define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU REG_BIT(15) 5786 #define DG2_RENDER_CCSTAG_4_3_EN REG_BIT(12) 5787 #define PER_PIXEL_ALPHA_BYPASS_EN REG_BIT(7) 5788 5789 /* PCH */ 5790 5791 #define PCH_DISPLAY_BASE 0xc0000u 5792 5793 /* south display engine interrupt: IBX */ 5794 #define SDE_AUDIO_POWER_D (1 << 27) 5795 #define SDE_AUDIO_POWER_C (1 << 26) 5796 #define SDE_AUDIO_POWER_B (1 << 25) 5797 #define SDE_AUDIO_POWER_SHIFT (25) 5798 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) 5799 #define SDE_GMBUS (1 << 24) 5800 #define SDE_AUDIO_HDCP_TRANSB (1 << 23) 5801 #define SDE_AUDIO_HDCP_TRANSA (1 << 22) 5802 #define SDE_AUDIO_HDCP_MASK (3 << 22) 5803 #define SDE_AUDIO_TRANSB (1 << 21) 5804 #define SDE_AUDIO_TRANSA (1 << 20) 5805 #define SDE_AUDIO_TRANS_MASK (3 << 20) 5806 #define SDE_POISON (1 << 19) 5807 /* 18 reserved */ 5808 #define SDE_FDI_RXB (1 << 17) 5809 #define SDE_FDI_RXA (1 << 16) 5810 #define SDE_FDI_MASK (3 << 16) 5811 #define SDE_AUXD (1 << 15) 5812 #define SDE_AUXC (1 << 14) 5813 #define SDE_AUXB (1 << 13) 5814 #define SDE_AUX_MASK (7 << 13) 5815 /* 12 reserved */ 5816 #define SDE_CRT_HOTPLUG (1 << 11) 5817 #define SDE_PORTD_HOTPLUG (1 << 10) 5818 #define SDE_PORTC_HOTPLUG (1 << 9) 5819 #define SDE_PORTB_HOTPLUG (1 << 8) 5820 #define SDE_SDVOB_HOTPLUG (1 << 6) 5821 #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \ 5822 SDE_SDVOB_HOTPLUG | \ 5823 SDE_PORTB_HOTPLUG | \ 5824 SDE_PORTC_HOTPLUG | \ 5825 SDE_PORTD_HOTPLUG) 5826 #define SDE_TRANSB_CRC_DONE (1 << 5) 5827 #define SDE_TRANSB_CRC_ERR (1 << 4) 5828 #define SDE_TRANSB_FIFO_UNDER (1 << 3) 5829 #define SDE_TRANSA_CRC_DONE (1 << 2) 5830 #define SDE_TRANSA_CRC_ERR (1 << 1) 5831 #define SDE_TRANSA_FIFO_UNDER (1 << 0) 5832 #define SDE_TRANS_MASK (0x3f) 5833 5834 /* south display engine interrupt: CPT - CNP */ 5835 #define SDE_AUDIO_POWER_D_CPT (1 << 31) 5836 #define SDE_AUDIO_POWER_C_CPT (1 << 30) 5837 #define SDE_AUDIO_POWER_B_CPT (1 << 29) 5838 #define SDE_AUDIO_POWER_SHIFT_CPT 29 5839 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29) 5840 #define SDE_AUXD_CPT (1 << 27) 5841 #define SDE_AUXC_CPT (1 << 26) 5842 #define SDE_AUXB_CPT (1 << 25) 5843 #define SDE_AUX_MASK_CPT (7 << 25) 5844 #define SDE_PORTE_HOTPLUG_SPT (1 << 25) 5845 #define SDE_PORTA_HOTPLUG_SPT (1 << 24) 5846 #define SDE_PORTD_HOTPLUG_CPT (1 << 23) 5847 #define SDE_PORTC_HOTPLUG_CPT (1 << 22) 5848 #define SDE_PORTB_HOTPLUG_CPT (1 << 21) 5849 #define SDE_CRT_HOTPLUG_CPT (1 << 19) 5850 #define SDE_SDVOB_HOTPLUG_CPT (1 << 18) 5851 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ 5852 SDE_SDVOB_HOTPLUG_CPT | \ 5853 SDE_PORTD_HOTPLUG_CPT | \ 5854 SDE_PORTC_HOTPLUG_CPT | \ 5855 SDE_PORTB_HOTPLUG_CPT) 5856 #define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \ 5857 SDE_PORTD_HOTPLUG_CPT | \ 5858 SDE_PORTC_HOTPLUG_CPT | \ 5859 SDE_PORTB_HOTPLUG_CPT | \ 5860 SDE_PORTA_HOTPLUG_SPT) 5861 #define SDE_GMBUS_CPT (1 << 17) 5862 #define SDE_ERROR_CPT (1 << 16) 5863 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10) 5864 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9) 5865 #define SDE_FDI_RXC_CPT (1 << 8) 5866 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6) 5867 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5) 5868 #define SDE_FDI_RXB_CPT (1 << 4) 5869 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2) 5870 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1) 5871 #define SDE_FDI_RXA_CPT (1 << 0) 5872 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \ 5873 SDE_AUDIO_CP_REQ_B_CPT | \ 5874 SDE_AUDIO_CP_REQ_A_CPT) 5875 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \ 5876 SDE_AUDIO_CP_CHG_B_CPT | \ 5877 SDE_AUDIO_CP_CHG_A_CPT) 5878 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \ 5879 SDE_FDI_RXB_CPT | \ 5880 SDE_FDI_RXA_CPT) 5881 5882 /* south display engine interrupt: ICP/TGP */ 5883 #define SDE_GMBUS_ICP (1 << 23) 5884 #define SDE_TC_HOTPLUG_ICP(hpd_pin) REG_BIT(24 + _HPD_PIN_TC(hpd_pin)) 5885 #define SDE_TC_HOTPLUG_DG2(hpd_pin) REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /* sigh */ 5886 #define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin)) 5887 #define SDE_DDI_HOTPLUG_MASK_ICP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \ 5888 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \ 5889 SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \ 5890 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A)) 5891 #define SDE_TC_HOTPLUG_MASK_ICP (SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \ 5892 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \ 5893 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \ 5894 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \ 5895 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \ 5896 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1)) 5897 5898 #define SDEISR _MMIO(0xc4000) 5899 #define SDEIMR _MMIO(0xc4004) 5900 #define SDEIIR _MMIO(0xc4008) 5901 #define SDEIER _MMIO(0xc400c) 5902 5903 #define SERR_INT _MMIO(0xc4040) 5904 #define SERR_INT_POISON (1 << 31) 5905 #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) 5906 5907 /* digital port hotplug */ 5908 #define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */ 5909 #define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */ 5910 #define BXT_DDIA_HPD_INVERT (1 << 27) 5911 #define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */ 5912 #define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */ 5913 #define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */ 5914 #define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */ 5915 #define PORTD_HOTPLUG_ENABLE (1 << 20) 5916 #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */ 5917 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */ 5918 #define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */ 5919 #define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */ 5920 #define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */ 5921 #define PORTD_HOTPLUG_STATUS_MASK (3 << 16) 5922 #define PORTD_HOTPLUG_NO_DETECT (0 << 16) 5923 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) 5924 #define PORTD_HOTPLUG_LONG_DETECT (2 << 16) 5925 #define PORTC_HOTPLUG_ENABLE (1 << 12) 5926 #define BXT_DDIC_HPD_INVERT (1 << 11) 5927 #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */ 5928 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */ 5929 #define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */ 5930 #define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */ 5931 #define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */ 5932 #define PORTC_HOTPLUG_STATUS_MASK (3 << 8) 5933 #define PORTC_HOTPLUG_NO_DETECT (0 << 8) 5934 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) 5935 #define PORTC_HOTPLUG_LONG_DETECT (2 << 8) 5936 #define PORTB_HOTPLUG_ENABLE (1 << 4) 5937 #define BXT_DDIB_HPD_INVERT (1 << 3) 5938 #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */ 5939 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */ 5940 #define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */ 5941 #define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */ 5942 #define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */ 5943 #define PORTB_HOTPLUG_STATUS_MASK (3 << 0) 5944 #define PORTB_HOTPLUG_NO_DETECT (0 << 0) 5945 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) 5946 #define PORTB_HOTPLUG_LONG_DETECT (2 << 0) 5947 #define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \ 5948 BXT_DDIB_HPD_INVERT | \ 5949 BXT_DDIC_HPD_INVERT) 5950 5951 #define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */ 5952 #define PORTE_HOTPLUG_ENABLE (1 << 4) 5953 #define PORTE_HOTPLUG_STATUS_MASK (3 << 0) 5954 #define PORTE_HOTPLUG_NO_DETECT (0 << 0) 5955 #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0) 5956 #define PORTE_HOTPLUG_LONG_DETECT (2 << 0) 5957 5958 /* This register is a reuse of PCH_PORT_HOTPLUG register. The 5959 * functionality covered in PCH_PORT_HOTPLUG is split into 5960 * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC. 5961 */ 5962 5963 #define SHOTPLUG_CTL_DDI _MMIO(0xc4030) 5964 #define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) (0x8 << (_HPD_PIN_DDI(hpd_pin) * 4)) 5965 #define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4)) 5966 #define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin) (0x0 << (_HPD_PIN_DDI(hpd_pin) * 4)) 5967 #define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin) (0x1 << (_HPD_PIN_DDI(hpd_pin) * 4)) 5968 #define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin) (0x2 << (_HPD_PIN_DDI(hpd_pin) * 4)) 5969 #define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4)) 5970 5971 #define SHOTPLUG_CTL_TC _MMIO(0xc4034) 5972 #define ICP_TC_HPD_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4)) 5973 #define ICP_TC_HPD_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4)) 5974 #define ICP_TC_HPD_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4)) 5975 5976 #define SHPD_FILTER_CNT _MMIO(0xc4038) 5977 #define SHPD_FILTER_CNT_500_ADJ 0x001D9 5978 5979 #define _PCH_DPLL_A 0xc6014 5980 #define _PCH_DPLL_B 0xc6018 5981 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) 5982 5983 #define _PCH_FPA0 0xc6040 5984 #define FP_CB_TUNE (0x3 << 22) 5985 #define _PCH_FPA1 0xc6044 5986 #define _PCH_FPB0 0xc6048 5987 #define _PCH_FPB1 0xc604c 5988 #define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0) 5989 #define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1) 5990 5991 #define PCH_DPLL_TEST _MMIO(0xc606c) 5992 5993 #define PCH_DREF_CONTROL _MMIO(0xC6200) 5994 #define DREF_CONTROL_MASK 0x7fc3 5995 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13) 5996 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13) 5997 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13) 5998 #define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13) 5999 #define DREF_SSC_SOURCE_DISABLE (0 << 11) 6000 #define DREF_SSC_SOURCE_ENABLE (2 << 11) 6001 #define DREF_SSC_SOURCE_MASK (3 << 11) 6002 #define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9) 6003 #define DREF_NONSPREAD_CK505_ENABLE (1 << 9) 6004 #define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9) 6005 #define DREF_NONSPREAD_SOURCE_MASK (3 << 9) 6006 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7) 6007 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7) 6008 #define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7) 6009 #define DREF_SSC4_DOWNSPREAD (0 << 6) 6010 #define DREF_SSC4_CENTERSPREAD (1 << 6) 6011 #define DREF_SSC1_DISABLE (0 << 1) 6012 #define DREF_SSC1_ENABLE (1 << 1) 6013 #define DREF_SSC4_DISABLE (0) 6014 #define DREF_SSC4_ENABLE (1) 6015 6016 #define PCH_RAWCLK_FREQ _MMIO(0xc6204) 6017 #define FDL_TP1_TIMER_SHIFT 12 6018 #define FDL_TP1_TIMER_MASK (3 << 12) 6019 #define FDL_TP2_TIMER_SHIFT 10 6020 #define FDL_TP2_TIMER_MASK (3 << 10) 6021 #define RAWCLK_FREQ_MASK 0x3ff 6022 #define CNP_RAWCLK_DIV_MASK (0x3ff << 16) 6023 #define CNP_RAWCLK_DIV(div) ((div) << 16) 6024 #define CNP_RAWCLK_FRAC_MASK (0xf << 26) 6025 #define CNP_RAWCLK_DEN(den) ((den) << 26) 6026 #define ICP_RAWCLK_NUM(num) ((num) << 11) 6027 6028 #define PCH_DPLL_TMR_CFG _MMIO(0xc6208) 6029 6030 #define PCH_SSC4_PARMS _MMIO(0xc6210) 6031 #define PCH_SSC4_AUX_PARMS _MMIO(0xc6214) 6032 6033 #define PCH_DPLL_SEL _MMIO(0xc7000) 6034 #define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4)) 6035 #define TRANS_DPLLA_SEL(pipe) 0 6036 #define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3)) 6037 6038 /* transcoder */ 6039 6040 #define _PCH_TRANS_HTOTAL_A 0xe0000 6041 #define TRANS_HTOTAL_SHIFT 16 6042 #define TRANS_HACTIVE_SHIFT 0 6043 #define _PCH_TRANS_HBLANK_A 0xe0004 6044 #define TRANS_HBLANK_END_SHIFT 16 6045 #define TRANS_HBLANK_START_SHIFT 0 6046 #define _PCH_TRANS_HSYNC_A 0xe0008 6047 #define TRANS_HSYNC_END_SHIFT 16 6048 #define TRANS_HSYNC_START_SHIFT 0 6049 #define _PCH_TRANS_VTOTAL_A 0xe000c 6050 #define TRANS_VTOTAL_SHIFT 16 6051 #define TRANS_VACTIVE_SHIFT 0 6052 #define _PCH_TRANS_VBLANK_A 0xe0010 6053 #define TRANS_VBLANK_END_SHIFT 16 6054 #define TRANS_VBLANK_START_SHIFT 0 6055 #define _PCH_TRANS_VSYNC_A 0xe0014 6056 #define TRANS_VSYNC_END_SHIFT 16 6057 #define TRANS_VSYNC_START_SHIFT 0 6058 #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028 6059 6060 #define _PCH_TRANSA_DATA_M1 0xe0030 6061 #define _PCH_TRANSA_DATA_N1 0xe0034 6062 #define _PCH_TRANSA_DATA_M2 0xe0038 6063 #define _PCH_TRANSA_DATA_N2 0xe003c 6064 #define _PCH_TRANSA_LINK_M1 0xe0040 6065 #define _PCH_TRANSA_LINK_N1 0xe0044 6066 #define _PCH_TRANSA_LINK_M2 0xe0048 6067 #define _PCH_TRANSA_LINK_N2 0xe004c 6068 6069 /* Per-transcoder DIP controls (PCH) */ 6070 #define _VIDEO_DIP_CTL_A 0xe0200 6071 #define _VIDEO_DIP_DATA_A 0xe0208 6072 #define _VIDEO_DIP_GCP_A 0xe0210 6073 #define GCP_COLOR_INDICATION (1 << 2) 6074 #define GCP_DEFAULT_PHASE_ENABLE (1 << 1) 6075 #define GCP_AV_MUTE (1 << 0) 6076 6077 #define _VIDEO_DIP_CTL_B 0xe1200 6078 #define _VIDEO_DIP_DATA_B 0xe1208 6079 #define _VIDEO_DIP_GCP_B 0xe1210 6080 6081 #define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) 6082 #define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) 6083 #define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) 6084 6085 /* Per-transcoder DIP controls (VLV) */ 6086 #define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200) 6087 #define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208) 6088 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210) 6089 6090 #define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170) 6091 #define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174) 6092 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178) 6093 6094 #define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0) 6095 #define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4) 6096 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8) 6097 6098 #define VLV_TVIDEO_DIP_CTL(pipe) \ 6099 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \ 6100 _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C) 6101 #define VLV_TVIDEO_DIP_DATA(pipe) \ 6102 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \ 6103 _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C) 6104 #define VLV_TVIDEO_DIP_GCP(pipe) \ 6105 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \ 6106 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C) 6107 6108 /* Haswell DIP controls */ 6109 6110 #define _HSW_VIDEO_DIP_CTL_A 0x60200 6111 #define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220 6112 #define _HSW_VIDEO_DIP_VS_DATA_A 0x60260 6113 #define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 6114 #define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 6115 #define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320 6116 #define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440 6117 #define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240 6118 #define _HSW_VIDEO_DIP_VS_ECC_A 0x60280 6119 #define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 6120 #define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300 6121 #define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344 6122 #define _HSW_VIDEO_DIP_GCP_A 0x60210 6123 6124 #define _HSW_VIDEO_DIP_CTL_B 0x61200 6125 #define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220 6126 #define _HSW_VIDEO_DIP_VS_DATA_B 0x61260 6127 #define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 6128 #define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 6129 #define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320 6130 #define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440 6131 #define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240 6132 #define _HSW_VIDEO_DIP_VS_ECC_B 0x61280 6133 #define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 6134 #define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300 6135 #define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344 6136 #define _HSW_VIDEO_DIP_GCP_B 0x61210 6137 6138 /* Icelake PPS_DATA and _ECC DIP Registers. 6139 * These are available for transcoders B,C and eDP. 6140 * Adding the _A so as to reuse the _MMIO_TRANS2 6141 * definition, with which it offsets to the right location. 6142 */ 6143 6144 #define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350 6145 #define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350 6146 #define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4 6147 #define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4 6148 6149 #define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A) 6150 #define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A) 6151 #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4) 6152 #define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4) 6153 #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4) 6154 #define HSW_TVIDEO_DIP_GMP_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4) 6155 #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4) 6156 #define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4) 6157 #define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4) 6158 #define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4) 6159 6160 #define _HSW_STEREO_3D_CTL_A 0x70020 6161 #define S3D_ENABLE (1 << 31) 6162 #define _HSW_STEREO_3D_CTL_B 0x71020 6163 6164 #define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A) 6165 6166 #define _PCH_TRANS_HTOTAL_B 0xe1000 6167 #define _PCH_TRANS_HBLANK_B 0xe1004 6168 #define _PCH_TRANS_HSYNC_B 0xe1008 6169 #define _PCH_TRANS_VTOTAL_B 0xe100c 6170 #define _PCH_TRANS_VBLANK_B 0xe1010 6171 #define _PCH_TRANS_VSYNC_B 0xe1014 6172 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028 6173 6174 #define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B) 6175 #define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B) 6176 #define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B) 6177 #define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B) 6178 #define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B) 6179 #define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B) 6180 #define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B) 6181 6182 #define _PCH_TRANSB_DATA_M1 0xe1030 6183 #define _PCH_TRANSB_DATA_N1 0xe1034 6184 #define _PCH_TRANSB_DATA_M2 0xe1038 6185 #define _PCH_TRANSB_DATA_N2 0xe103c 6186 #define _PCH_TRANSB_LINK_M1 0xe1040 6187 #define _PCH_TRANSB_LINK_N1 0xe1044 6188 #define _PCH_TRANSB_LINK_M2 0xe1048 6189 #define _PCH_TRANSB_LINK_N2 0xe104c 6190 6191 #define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1) 6192 #define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1) 6193 #define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2) 6194 #define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2) 6195 #define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1) 6196 #define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1) 6197 #define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2) 6198 #define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2) 6199 6200 #define _PCH_TRANSACONF 0xf0008 6201 #define _PCH_TRANSBCONF 0xf1008 6202 #define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF) 6203 #define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */ 6204 #define TRANS_ENABLE REG_BIT(31) 6205 #define TRANS_STATE_ENABLE REG_BIT(30) 6206 #define TRANS_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* ibx */ 6207 #define TRANS_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */ 6208 #define TRANS_INTERLACE_MASK REG_GENMASK(23, 21) 6209 #define TRANS_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0) 6210 #define TRANS_INTERLACE_LEGACY_VSYNC_IBX REG_FIELD_PREP(TRANS_INTERLACE_MASK, 2) /* ibx */ 6211 #define TRANS_INTERLACE_INTERLACED REG_FIELD_PREP(TRANS_INTERLACE_MASK, 3) 6212 #define TRANS_BPC_MASK REG_GENMASK(7, 5) /* ibx */ 6213 #define TRANS_BPC_8 REG_FIELD_PREP(TRANS_BPC_MASK, 0) 6214 #define TRANS_BPC_10 REG_FIELD_PREP(TRANS_BPC_MASK, 1) 6215 #define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK, 2) 6216 #define TRANS_BPC_12 REG_FIELD_PREP(TRANS_BPC_MASK, 3) 6217 #define _TRANSA_CHICKEN1 0xf0060 6218 #define _TRANSB_CHICKEN1 0xf1060 6219 #define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) 6220 #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE (1 << 10) 6221 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1 << 4) 6222 #define _TRANSA_CHICKEN2 0xf0064 6223 #define _TRANSB_CHICKEN2 0xf1064 6224 #define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) 6225 #define TRANS_CHICKEN2_TIMING_OVERRIDE (1 << 31) 6226 #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1 << 29) 6227 #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3 << 27) 6228 #define TRANS_CHICKEN2_FRAME_START_DELAY(x) ((x) << 27) /* 0-3 */ 6229 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1 << 26) 6230 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1 << 25) 6231 6232 #define SOUTH_CHICKEN1 _MMIO(0xc2000) 6233 #define FDIA_PHASE_SYNC_SHIFT_OVR 19 6234 #define FDIA_PHASE_SYNC_SHIFT_EN 18 6235 #define INVERT_DDID_HPD (1 << 18) 6236 #define INVERT_DDIC_HPD (1 << 17) 6237 #define INVERT_DDIB_HPD (1 << 16) 6238 #define INVERT_DDIA_HPD (1 << 15) 6239 #define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) 6240 #define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) 6241 #define FDI_BC_BIFURCATION_SELECT (1 << 12) 6242 #define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8) 6243 #define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8) 6244 #define SBCLK_RUN_REFCLK_DIS (1 << 7) 6245 #define ICP_SECOND_PPS_IO_SELECT REG_BIT(2) 6246 #define SPT_PWM_GRANULARITY (1 << 0) 6247 #define SOUTH_CHICKEN2 _MMIO(0xc2004) 6248 #define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13) 6249 #define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12) 6250 #define LPT_PWM_GRANULARITY (1 << 5) 6251 #define DPLS_EDP_PPS_FIX_DIS (1 << 0) 6252 6253 #define _FDI_RXA_CHICKEN 0xc200c 6254 #define _FDI_RXB_CHICKEN 0xc2010 6255 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1 << 1) 6256 #define FDI_RX_PHASE_SYNC_POINTER_EN (1 << 0) 6257 #define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) 6258 6259 #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020) 6260 #define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31) 6261 #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30) 6262 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29) 6263 #define PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15) 6264 #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14) 6265 #define CNP_PWM_CGE_GATING_DISABLE (1 << 13) 6266 #define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12) 6267 6268 /* CPU: FDI_TX */ 6269 #define _FDI_TXA_CTL 0x60100 6270 #define _FDI_TXB_CTL 0x61100 6271 #define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) 6272 #define FDI_TX_DISABLE (0 << 31) 6273 #define FDI_TX_ENABLE (1 << 31) 6274 #define FDI_LINK_TRAIN_PATTERN_1 (0 << 28) 6275 #define FDI_LINK_TRAIN_PATTERN_2 (1 << 28) 6276 #define FDI_LINK_TRAIN_PATTERN_IDLE (2 << 28) 6277 #define FDI_LINK_TRAIN_NONE (3 << 28) 6278 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0 << 25) 6279 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1 << 25) 6280 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2 << 25) 6281 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3 << 25) 6282 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22) 6283 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22) 6284 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2 << 22) 6285 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3 << 22) 6286 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. 6287 SNB has different settings. */ 6288 /* SNB A-stepping */ 6289 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) 6290 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22) 6291 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22) 6292 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22) 6293 /* SNB B-stepping */ 6294 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0 << 22) 6295 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a << 22) 6296 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39 << 22) 6297 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38 << 22) 6298 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f << 22) 6299 #define FDI_DP_PORT_WIDTH_SHIFT 19 6300 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT) 6301 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT) 6302 #define FDI_TX_ENHANCE_FRAME_ENABLE (1 << 18) 6303 /* Ironlake: hardwired to 1 */ 6304 #define FDI_TX_PLL_ENABLE (1 << 14) 6305 6306 /* Ivybridge has different bits for lolz */ 6307 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0 << 8) 6308 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1 << 8) 6309 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2 << 8) 6310 #define FDI_LINK_TRAIN_NONE_IVB (3 << 8) 6311 6312 /* both Tx and Rx */ 6313 #define FDI_COMPOSITE_SYNC (1 << 11) 6314 #define FDI_LINK_TRAIN_AUTO (1 << 10) 6315 #define FDI_SCRAMBLING_ENABLE (0 << 7) 6316 #define FDI_SCRAMBLING_DISABLE (1 << 7) 6317 6318 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */ 6319 #define _FDI_RXA_CTL 0xf000c 6320 #define _FDI_RXB_CTL 0xf100c 6321 #define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) 6322 #define FDI_RX_ENABLE (1 << 31) 6323 /* train, dp width same as FDI_TX */ 6324 #define FDI_FS_ERRC_ENABLE (1 << 27) 6325 #define FDI_FE_ERRC_ENABLE (1 << 26) 6326 #define FDI_RX_POLARITY_REVERSED_LPT (1 << 16) 6327 #define FDI_8BPC (0 << 16) 6328 #define FDI_10BPC (1 << 16) 6329 #define FDI_6BPC (2 << 16) 6330 #define FDI_12BPC (3 << 16) 6331 #define FDI_RX_LINK_REVERSAL_OVERRIDE (1 << 15) 6332 #define FDI_DMI_LINK_REVERSE_MASK (1 << 14) 6333 #define FDI_RX_PLL_ENABLE (1 << 13) 6334 #define FDI_FS_ERR_CORRECT_ENABLE (1 << 11) 6335 #define FDI_FE_ERR_CORRECT_ENABLE (1 << 10) 6336 #define FDI_FS_ERR_REPORT_ENABLE (1 << 9) 6337 #define FDI_FE_ERR_REPORT_ENABLE (1 << 8) 6338 #define FDI_RX_ENHANCE_FRAME_ENABLE (1 << 6) 6339 #define FDI_PCDCLK (1 << 4) 6340 /* CPT */ 6341 #define FDI_AUTO_TRAINING (1 << 10) 6342 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0 << 8) 6343 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1 << 8) 6344 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2 << 8) 6345 #define FDI_LINK_TRAIN_NORMAL_CPT (3 << 8) 6346 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3 << 8) 6347 6348 #define _FDI_RXA_MISC 0xf0010 6349 #define _FDI_RXB_MISC 0xf1010 6350 #define FDI_RX_PWRDN_LANE1_MASK (3 << 26) 6351 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x) << 26) 6352 #define FDI_RX_PWRDN_LANE0_MASK (3 << 24) 6353 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x) << 24) 6354 #define FDI_RX_TP1_TO_TP2_48 (2 << 20) 6355 #define FDI_RX_TP1_TO_TP2_64 (3 << 20) 6356 #define FDI_RX_FDI_DELAY_90 (0x90 << 0) 6357 #define FDI_RX_MISC(pipe) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) 6358 6359 #define _FDI_RXA_TUSIZE1 0xf0030 6360 #define _FDI_RXA_TUSIZE2 0xf0038 6361 #define _FDI_RXB_TUSIZE1 0xf1030 6362 #define _FDI_RXB_TUSIZE2 0xf1038 6363 #define FDI_RX_TUSIZE1(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) 6364 #define FDI_RX_TUSIZE2(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) 6365 6366 /* FDI_RX interrupt register format */ 6367 #define FDI_RX_INTER_LANE_ALIGN (1 << 10) 6368 #define FDI_RX_SYMBOL_LOCK (1 << 9) /* train 2 */ 6369 #define FDI_RX_BIT_LOCK (1 << 8) /* train 1 */ 6370 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1 << 7) 6371 #define FDI_RX_FS_CODE_ERR (1 << 6) 6372 #define FDI_RX_FE_CODE_ERR (1 << 5) 6373 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1 << 4) 6374 #define FDI_RX_HDCP_LINK_FAIL (1 << 3) 6375 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1 << 2) 6376 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1 << 1) 6377 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1 << 0) 6378 6379 #define _FDI_RXA_IIR 0xf0014 6380 #define _FDI_RXA_IMR 0xf0018 6381 #define _FDI_RXB_IIR 0xf1014 6382 #define _FDI_RXB_IMR 0xf1018 6383 #define FDI_RX_IIR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) 6384 #define FDI_RX_IMR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR) 6385 6386 #define FDI_PLL_CTL_1 _MMIO(0xfe000) 6387 #define FDI_PLL_CTL_2 _MMIO(0xfe004) 6388 6389 #define PCH_LVDS _MMIO(0xe1180) 6390 #define LVDS_DETECTED (1 << 1) 6391 6392 #define _PCH_DP_B 0xe4100 6393 #define PCH_DP_B _MMIO(_PCH_DP_B) 6394 #define _PCH_DPB_AUX_CH_CTL 0xe4110 6395 #define _PCH_DPB_AUX_CH_DATA1 0xe4114 6396 #define _PCH_DPB_AUX_CH_DATA2 0xe4118 6397 #define _PCH_DPB_AUX_CH_DATA3 0xe411c 6398 #define _PCH_DPB_AUX_CH_DATA4 0xe4120 6399 #define _PCH_DPB_AUX_CH_DATA5 0xe4124 6400 6401 #define _PCH_DP_C 0xe4200 6402 #define PCH_DP_C _MMIO(_PCH_DP_C) 6403 #define _PCH_DPC_AUX_CH_CTL 0xe4210 6404 #define _PCH_DPC_AUX_CH_DATA1 0xe4214 6405 #define _PCH_DPC_AUX_CH_DATA2 0xe4218 6406 #define _PCH_DPC_AUX_CH_DATA3 0xe421c 6407 #define _PCH_DPC_AUX_CH_DATA4 0xe4220 6408 #define _PCH_DPC_AUX_CH_DATA5 0xe4224 6409 6410 #define _PCH_DP_D 0xe4300 6411 #define PCH_DP_D _MMIO(_PCH_DP_D) 6412 #define _PCH_DPD_AUX_CH_CTL 0xe4310 6413 #define _PCH_DPD_AUX_CH_DATA1 0xe4314 6414 #define _PCH_DPD_AUX_CH_DATA2 0xe4318 6415 #define _PCH_DPD_AUX_CH_DATA3 0xe431c 6416 #define _PCH_DPD_AUX_CH_DATA4 0xe4320 6417 #define _PCH_DPD_AUX_CH_DATA5 0xe4324 6418 6419 #define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL) 6420 #define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ 6421 6422 /* CPT */ 6423 #define _TRANS_DP_CTL_A 0xe0300 6424 #define _TRANS_DP_CTL_B 0xe1300 6425 #define _TRANS_DP_CTL_C 0xe2300 6426 #define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B) 6427 #define TRANS_DP_OUTPUT_ENABLE REG_BIT(31) 6428 #define TRANS_DP_PORT_SEL_MASK REG_GENMASK(30, 29) 6429 #define TRANS_DP_PORT_SEL_NONE REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, 3) 6430 #define TRANS_DP_PORT_SEL(port) REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, (port) - PORT_B) 6431 #define TRANS_DP_AUDIO_ONLY REG_BIT(26) 6432 #define TRANS_DP_ENH_FRAMING REG_BIT(18) 6433 #define TRANS_DP_BPC_MASK REG_GENMASK(10, 9) 6434 #define TRANS_DP_BPC_8 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 0) 6435 #define TRANS_DP_BPC_10 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 1) 6436 #define TRANS_DP_BPC_6 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 2) 6437 #define TRANS_DP_BPC_12 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 3) 6438 #define TRANS_DP_VSYNC_ACTIVE_HIGH REG_BIT(4) 6439 #define TRANS_DP_HSYNC_ACTIVE_HIGH REG_BIT(3) 6440 6441 #define _TRANS_DP2_CTL_A 0x600a0 6442 #define _TRANS_DP2_CTL_B 0x610a0 6443 #define _TRANS_DP2_CTL_C 0x620a0 6444 #define _TRANS_DP2_CTL_D 0x630a0 6445 #define TRANS_DP2_CTL(trans) _MMIO_TRANS(trans, _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B) 6446 #define TRANS_DP2_128B132B_CHANNEL_CODING REG_BIT(31) 6447 #define TRANS_DP2_PANEL_REPLAY_ENABLE REG_BIT(30) 6448 #define TRANS_DP2_DEBUG_ENABLE REG_BIT(23) 6449 6450 #define _TRANS_DP2_VFREQHIGH_A 0x600a4 6451 #define _TRANS_DP2_VFREQHIGH_B 0x610a4 6452 #define _TRANS_DP2_VFREQHIGH_C 0x620a4 6453 #define _TRANS_DP2_VFREQHIGH_D 0x630a4 6454 #define TRANS_DP2_VFREQHIGH(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQHIGH_A, _TRANS_DP2_VFREQHIGH_B) 6455 #define TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK REG_GENMASK(31, 8) 6456 #define TRANS_DP2_VFREQ_PIXEL_CLOCK(clk_hz) REG_FIELD_PREP(TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK, (clk_hz)) 6457 6458 #define _TRANS_DP2_VFREQLOW_A 0x600a8 6459 #define _TRANS_DP2_VFREQLOW_B 0x610a8 6460 #define _TRANS_DP2_VFREQLOW_C 0x620a8 6461 #define _TRANS_DP2_VFREQLOW_D 0x630a8 6462 #define TRANS_DP2_VFREQLOW(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQLOW_A, _TRANS_DP2_VFREQLOW_B) 6463 6464 /* SNB eDP training params */ 6465 /* SNB A-stepping */ 6466 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) 6467 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22) 6468 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22) 6469 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22) 6470 /* SNB B-stepping */ 6471 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22) 6472 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22) 6473 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22) 6474 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22) 6475 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22) 6476 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22) 6477 6478 /* IVB */ 6479 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22) 6480 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22) 6481 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22) 6482 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22) 6483 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22) 6484 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22) 6485 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e << 22) 6486 6487 /* legacy values */ 6488 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22) 6489 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22) 6490 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22) 6491 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22) 6492 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22) 6493 6494 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22) 6495 6496 #define VLV_PMWGICZ _MMIO(0x1300a4) 6497 6498 #define HSW_EDRAM_CAP _MMIO(0x120010) 6499 #define EDRAM_ENABLED 0x1 6500 #define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf) 6501 #define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7) 6502 #define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3) 6503 6504 #define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C) 6505 #define PIXEL_OVERLAP_CNT_MASK (3 << 30) 6506 #define PIXEL_OVERLAP_CNT_SHIFT 30 6507 6508 #define GEN6_PCODE_MAILBOX _MMIO(0x138124) 6509 #define GEN6_PCODE_READY (1 << 31) 6510 #define GEN6_PCODE_MB_PARAM2 REG_GENMASK(23, 16) 6511 #define GEN6_PCODE_MB_PARAM1 REG_GENMASK(15, 8) 6512 #define GEN6_PCODE_MB_COMMAND REG_GENMASK(7, 0) 6513 #define GEN6_PCODE_ERROR_MASK 0xFF 6514 #define GEN6_PCODE_SUCCESS 0x0 6515 #define GEN6_PCODE_ILLEGAL_CMD 0x1 6516 #define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2 6517 #define GEN6_PCODE_TIMEOUT 0x3 6518 #define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF 6519 #define GEN7_PCODE_TIMEOUT 0x2 6520 #define GEN7_PCODE_ILLEGAL_DATA 0x3 6521 #define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4 6522 #define GEN11_PCODE_LOCKED 0x6 6523 #define GEN11_PCODE_REJECTED 0x11 6524 #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10 6525 #define GEN6_PCODE_WRITE_RC6VIDS 0x4 6526 #define GEN6_PCODE_READ_RC6VIDS 0x5 6527 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) 6528 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) 6529 #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18 6530 #define GEN9_PCODE_READ_MEM_LATENCY 0x6 6531 #define GEN9_MEM_LATENCY_LEVEL_3_7_MASK REG_GENMASK(31, 24) 6532 #define GEN9_MEM_LATENCY_LEVEL_2_6_MASK REG_GENMASK(23, 16) 6533 #define GEN9_MEM_LATENCY_LEVEL_1_5_MASK REG_GENMASK(15, 8) 6534 #define GEN9_MEM_LATENCY_LEVEL_0_4_MASK REG_GENMASK(7, 0) 6535 #define SKL_PCODE_LOAD_HDCP_KEYS 0x5 6536 #define SKL_PCODE_CDCLK_CONTROL 0x7 6537 #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3 6538 #define SKL_CDCLK_READY_FOR_CHANGE 0x1 6539 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 6540 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 6541 #define GEN6_READ_OC_PARAMS 0xc 6542 #define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd 6543 #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8) 6544 #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8)) 6545 #define ADL_PCODE_MEM_SS_READ_PSF_GV_INFO ((0) | (0x2 << 8)) 6546 #define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe 6547 #define ICL_PCODE_REP_QGV_MASK REG_GENMASK(1, 0) 6548 #define ICL_PCODE_REP_QGV_SAFE REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0) 6549 #define ICL_PCODE_REP_QGV_POLL REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1) 6550 #define ICL_PCODE_REP_QGV_REJECTED REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2) 6551 #define ADLS_PCODE_REP_PSF_MASK REG_GENMASK(3, 2) 6552 #define ADLS_PCODE_REP_PSF_SAFE REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0) 6553 #define ADLS_PCODE_REP_PSF_POLL REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1) 6554 #define ADLS_PCODE_REP_PSF_REJECTED REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2) 6555 #define ICL_PCODE_REQ_QGV_PT_MASK REG_GENMASK(7, 0) 6556 #define ICL_PCODE_REQ_QGV_PT(x) REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x)) 6557 #define ADLS_PCODE_REQ_PSF_PT_MASK REG_GENMASK(10, 8) 6558 #define ADLS_PCODE_REQ_PSF_PT(x) REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x)) 6559 #define GEN6_PCODE_READ_D_COMP 0x10 6560 #define GEN6_PCODE_WRITE_D_COMP 0x11 6561 #define ICL_PCODE_EXIT_TCCOLD 0x12 6562 #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17 6563 #define DISPLAY_IPS_CONTROL 0x19 6564 #define TGL_PCODE_TCCOLD 0x26 6565 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0) 6566 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ 0 6567 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0) 6568 /* See also IPS_CTL */ 6569 #define IPS_PCODE_CONTROL (1 << 30) 6570 #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A 6571 #define GEN9_PCODE_SAGV_CONTROL 0x21 6572 #define GEN9_SAGV_DISABLE 0x0 6573 #define GEN9_SAGV_IS_DISABLED 0x1 6574 #define GEN9_SAGV_ENABLE 0x3 6575 #define DG1_PCODE_STATUS 0x7E 6576 #define DG1_UNCORE_GET_INIT_STATUS 0x0 6577 #define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1 6578 #define PCODE_POWER_SETUP 0x7C 6579 #define POWER_SETUP_SUBCOMMAND_READ_I1 0x4 6580 #define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5 6581 #define POWER_SETUP_I1_WATTS REG_BIT(31) 6582 #define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */ 6583 #define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0) 6584 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23 6585 #define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* xehpsdv, pvc */ 6586 /* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */ 6587 #define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0 6588 #define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1 6589 /* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */ 6590 /* XEHP_PCODE_FREQUENCY_CONFIG param2 */ 6591 #define PCODE_MBOX_DOMAIN_NONE 0x0 6592 #define PCODE_MBOX_DOMAIN_MEDIAFF 0x3 6593 #define GEN6_PCODE_DATA _MMIO(0x138128) 6594 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 6595 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 6596 #define GEN6_PCODE_DATA1 _MMIO(0x13812C) 6597 6598 /* IVYBRIDGE DPF */ 6599 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */ 6600 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14) 6601 #define GEN7_PARITY_ERROR_VALID (1 << 13) 6602 #define GEN7_L3CDERRST1_BANK_MASK (3 << 11) 6603 #define GEN7_L3CDERRST1_SUBBANK_MASK (7 << 8) 6604 #define GEN7_PARITY_ERROR_ROW(reg) \ 6605 (((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14) 6606 #define GEN7_PARITY_ERROR_BANK(reg) \ 6607 (((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11) 6608 #define GEN7_PARITY_ERROR_SUBBANK(reg) \ 6609 (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) 6610 #define GEN7_L3CDERRST1_ENABLE (1 << 7) 6611 6612 /* These are the 4 32-bit write offset registers for each stream 6613 * output buffer. It determines the offset from the 6614 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. 6615 */ 6616 #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4) 6617 6618 /* 6619 * HSW - ICL power wells 6620 * 6621 * Platforms have up to 3 power well control register sets, each set 6622 * controlling up to 16 power wells via a request/status HW flag tuple: 6623 * - main (HSW_PWR_WELL_CTL[1-4]) 6624 * - AUX (ICL_PWR_WELL_CTL_AUX[1-4]) 6625 * - DDI (ICL_PWR_WELL_CTL_DDI[1-4]) 6626 * Each control register set consists of up to 4 registers used by different 6627 * sources that can request a power well to be enabled: 6628 * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1) 6629 * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2) 6630 * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set) 6631 * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4) 6632 */ 6633 #define HSW_PWR_WELL_CTL1 _MMIO(0x45400) 6634 #define HSW_PWR_WELL_CTL2 _MMIO(0x45404) 6635 #define HSW_PWR_WELL_CTL3 _MMIO(0x45408) 6636 #define HSW_PWR_WELL_CTL4 _MMIO(0x4540C) 6637 #define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2)) 6638 #define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2)) 6639 6640 /* HSW/BDW power well */ 6641 #define HSW_PW_CTL_IDX_GLOBAL 15 6642 6643 /* SKL/BXT/GLK power wells */ 6644 #define SKL_PW_CTL_IDX_PW_2 15 6645 #define SKL_PW_CTL_IDX_PW_1 14 6646 #define GLK_PW_CTL_IDX_AUX_C 10 6647 #define GLK_PW_CTL_IDX_AUX_B 9 6648 #define GLK_PW_CTL_IDX_AUX_A 8 6649 #define SKL_PW_CTL_IDX_DDI_D 4 6650 #define SKL_PW_CTL_IDX_DDI_C 3 6651 #define SKL_PW_CTL_IDX_DDI_B 2 6652 #define SKL_PW_CTL_IDX_DDI_A_E 1 6653 #define GLK_PW_CTL_IDX_DDI_A 1 6654 #define SKL_PW_CTL_IDX_MISC_IO 0 6655 6656 /* ICL/TGL - power wells */ 6657 #define TGL_PW_CTL_IDX_PW_5 4 6658 #define ICL_PW_CTL_IDX_PW_4 3 6659 #define ICL_PW_CTL_IDX_PW_3 2 6660 #define ICL_PW_CTL_IDX_PW_2 1 6661 #define ICL_PW_CTL_IDX_PW_1 0 6662 6663 /* XE_LPD - power wells */ 6664 #define XELPD_PW_CTL_IDX_PW_D 8 6665 #define XELPD_PW_CTL_IDX_PW_C 7 6666 #define XELPD_PW_CTL_IDX_PW_B 6 6667 #define XELPD_PW_CTL_IDX_PW_A 5 6668 6669 #define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440) 6670 #define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444) 6671 #define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C) 6672 #define TGL_PW_CTL_IDX_AUX_TBT6 14 6673 #define TGL_PW_CTL_IDX_AUX_TBT5 13 6674 #define TGL_PW_CTL_IDX_AUX_TBT4 12 6675 #define ICL_PW_CTL_IDX_AUX_TBT4 11 6676 #define TGL_PW_CTL_IDX_AUX_TBT3 11 6677 #define ICL_PW_CTL_IDX_AUX_TBT3 10 6678 #define TGL_PW_CTL_IDX_AUX_TBT2 10 6679 #define ICL_PW_CTL_IDX_AUX_TBT2 9 6680 #define TGL_PW_CTL_IDX_AUX_TBT1 9 6681 #define ICL_PW_CTL_IDX_AUX_TBT1 8 6682 #define TGL_PW_CTL_IDX_AUX_TC6 8 6683 #define XELPD_PW_CTL_IDX_AUX_E 8 6684 #define TGL_PW_CTL_IDX_AUX_TC5 7 6685 #define XELPD_PW_CTL_IDX_AUX_D 7 6686 #define TGL_PW_CTL_IDX_AUX_TC4 6 6687 #define ICL_PW_CTL_IDX_AUX_F 5 6688 #define TGL_PW_CTL_IDX_AUX_TC3 5 6689 #define ICL_PW_CTL_IDX_AUX_E 4 6690 #define TGL_PW_CTL_IDX_AUX_TC2 4 6691 #define ICL_PW_CTL_IDX_AUX_D 3 6692 #define TGL_PW_CTL_IDX_AUX_TC1 3 6693 #define ICL_PW_CTL_IDX_AUX_C 2 6694 #define ICL_PW_CTL_IDX_AUX_B 1 6695 #define ICL_PW_CTL_IDX_AUX_A 0 6696 6697 #define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450) 6698 #define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454) 6699 #define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C) 6700 #define XELPD_PW_CTL_IDX_DDI_E 8 6701 #define TGL_PW_CTL_IDX_DDI_TC6 8 6702 #define XELPD_PW_CTL_IDX_DDI_D 7 6703 #define TGL_PW_CTL_IDX_DDI_TC5 7 6704 #define TGL_PW_CTL_IDX_DDI_TC4 6 6705 #define ICL_PW_CTL_IDX_DDI_F 5 6706 #define TGL_PW_CTL_IDX_DDI_TC3 5 6707 #define ICL_PW_CTL_IDX_DDI_E 4 6708 #define TGL_PW_CTL_IDX_DDI_TC2 4 6709 #define ICL_PW_CTL_IDX_DDI_D 3 6710 #define TGL_PW_CTL_IDX_DDI_TC1 3 6711 #define ICL_PW_CTL_IDX_DDI_C 2 6712 #define ICL_PW_CTL_IDX_DDI_B 1 6713 #define ICL_PW_CTL_IDX_DDI_A 0 6714 6715 /* HSW - power well misc debug registers */ 6716 #define HSW_PWR_WELL_CTL5 _MMIO(0x45410) 6717 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31) 6718 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20) 6719 #define HSW_PWR_WELL_FORCE_ON (1 << 19) 6720 #define HSW_PWR_WELL_CTL6 _MMIO(0x45414) 6721 6722 /* SKL Fuse Status */ 6723 enum skl_power_gate { 6724 SKL_PG0, 6725 SKL_PG1, 6726 SKL_PG2, 6727 ICL_PG3, 6728 ICL_PG4, 6729 }; 6730 6731 #define SKL_FUSE_STATUS _MMIO(0x42000) 6732 #define SKL_FUSE_DOWNLOAD_STATUS (1 << 31) 6733 /* 6734 * PG0 is HW controlled, so doesn't have a corresponding power well control knob 6735 * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2 6736 */ 6737 #define SKL_PW_CTL_IDX_TO_PG(pw_idx) \ 6738 ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1) 6739 /* 6740 * PG0 is HW controlled, so doesn't have a corresponding power well control knob 6741 * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4 6742 */ 6743 #define ICL_PW_CTL_IDX_TO_PG(pw_idx) \ 6744 ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1) 6745 #define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg))) 6746 6747 #define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A) 6748 #define _ICL_AUX_ANAOVRD1_A 0x162398 6749 #define _ICL_AUX_ANAOVRD1_B 0x6C398 6750 #define ICL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \ 6751 _ICL_AUX_ANAOVRD1_A, \ 6752 _ICL_AUX_ANAOVRD1_B)) 6753 #define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7) 6754 #define ICL_AUX_ANAOVRD1_ENABLE (1 << 0) 6755 6756 /* Per-pipe DDI Function Control */ 6757 #define _TRANS_DDI_FUNC_CTL_A 0x60400 6758 #define _TRANS_DDI_FUNC_CTL_B 0x61400 6759 #define _TRANS_DDI_FUNC_CTL_C 0x62400 6760 #define _TRANS_DDI_FUNC_CTL_D 0x63400 6761 #define _TRANS_DDI_FUNC_CTL_EDP 0x6F400 6762 #define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400 6763 #define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00 6764 #define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A) 6765 6766 #define TRANS_DDI_FUNC_ENABLE (1 << 31) 6767 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ 6768 #define TRANS_DDI_PORT_SHIFT 28 6769 #define TGL_TRANS_DDI_PORT_SHIFT 27 6770 #define TRANS_DDI_PORT_MASK (7 << TRANS_DDI_PORT_SHIFT) 6771 #define TGL_TRANS_DDI_PORT_MASK (0xf << TGL_TRANS_DDI_PORT_SHIFT) 6772 #define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT) 6773 #define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT) 6774 #define TRANS_DDI_MODE_SELECT_MASK (7 << 24) 6775 #define TRANS_DDI_MODE_SELECT_HDMI (0 << 24) 6776 #define TRANS_DDI_MODE_SELECT_DVI (1 << 24) 6777 #define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24) 6778 #define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24) 6779 #define TRANS_DDI_MODE_SELECT_FDI_OR_128B132B (4 << 24) 6780 #define TRANS_DDI_BPC_MASK (7 << 20) 6781 #define TRANS_DDI_BPC_8 (0 << 20) 6782 #define TRANS_DDI_BPC_10 (1 << 20) 6783 #define TRANS_DDI_BPC_6 (2 << 20) 6784 #define TRANS_DDI_BPC_12 (3 << 20) 6785 #define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK REG_GENMASK(19, 18) 6786 #define TRANS_DDI_PORT_SYNC_MASTER_SELECT(x) REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, (x)) 6787 #define TRANS_DDI_PVSYNC (1 << 17) 6788 #define TRANS_DDI_PHSYNC (1 << 16) 6789 #define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15) 6790 #define TRANS_DDI_EDP_INPUT_MASK (7 << 12) 6791 #define TRANS_DDI_EDP_INPUT_A_ON (0 << 12) 6792 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12) 6793 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12) 6794 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12) 6795 #define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12) 6796 #define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10) 6797 #define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \ 6798 REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans) 6799 #define TRANS_DDI_HDCP_SIGNALLING (1 << 9) 6800 #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8) 6801 #define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7) 6802 #define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6) 6803 #define TRANS_DDI_HDCP_SELECT REG_BIT(5) 6804 #define TRANS_DDI_BFI_ENABLE (1 << 4) 6805 #define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4) 6806 #define TRANS_DDI_HDMI_SCRAMBLING (1 << 0) 6807 #define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \ 6808 | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \ 6809 | TRANS_DDI_HDMI_SCRAMBLING) 6810 6811 #define _TRANS_DDI_FUNC_CTL2_A 0x60404 6812 #define _TRANS_DDI_FUNC_CTL2_B 0x61404 6813 #define _TRANS_DDI_FUNC_CTL2_C 0x62404 6814 #define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404 6815 #define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404 6816 #define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04 6817 #define TRANS_DDI_FUNC_CTL2(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL2_A) 6818 #define PORT_SYNC_MODE_ENABLE REG_BIT(4) 6819 #define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0) 6820 #define PORT_SYNC_MODE_MASTER_SELECT(x) REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x)) 6821 6822 #define TRANS_CMTG_CHICKEN _MMIO(0x6fa90) 6823 #define DISABLE_DPT_CLK_GATING REG_BIT(1) 6824 6825 /* DisplayPort Transport Control */ 6826 #define _DP_TP_CTL_A 0x64040 6827 #define _DP_TP_CTL_B 0x64140 6828 #define _TGL_DP_TP_CTL_A 0x60540 6829 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B) 6830 #define TGL_DP_TP_CTL(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_CTL_A) 6831 #define DP_TP_CTL_ENABLE (1 << 31) 6832 #define DP_TP_CTL_FEC_ENABLE (1 << 30) 6833 #define DP_TP_CTL_MODE_SST (0 << 27) 6834 #define DP_TP_CTL_MODE_MST (1 << 27) 6835 #define DP_TP_CTL_FORCE_ACT (1 << 25) 6836 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18) 6837 #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15) 6838 #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8) 6839 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0 << 8) 6840 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1 << 8) 6841 #define DP_TP_CTL_LINK_TRAIN_PAT3 (4 << 8) 6842 #define DP_TP_CTL_LINK_TRAIN_PAT4 (5 << 8) 6843 #define DP_TP_CTL_LINK_TRAIN_IDLE (2 << 8) 6844 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3 << 8) 6845 #define DP_TP_CTL_SCRAMBLE_DISABLE (1 << 7) 6846 6847 /* DisplayPort Transport Status */ 6848 #define _DP_TP_STATUS_A 0x64044 6849 #define _DP_TP_STATUS_B 0x64144 6850 #define _TGL_DP_TP_STATUS_A 0x60544 6851 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B) 6852 #define TGL_DP_TP_STATUS(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_STATUS_A) 6853 #define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28) 6854 #define DP_TP_STATUS_IDLE_DONE (1 << 25) 6855 #define DP_TP_STATUS_ACT_SENT (1 << 24) 6856 #define DP_TP_STATUS_MODE_STATUS_MST (1 << 23) 6857 #define DP_TP_STATUS_AUTOTRAIN_DONE (1 << 12) 6858 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8) 6859 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4) 6860 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0) 6861 6862 /* DDI Buffer Control */ 6863 #define _DDI_BUF_CTL_A 0x64000 6864 #define _DDI_BUF_CTL_B 0x64100 6865 #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B) 6866 #define DDI_BUF_CTL_ENABLE (1 << 31) 6867 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24) 6868 #define DDI_BUF_EMP_MASK (0xf << 24) 6869 #define DDI_BUF_PHY_LINK_RATE(r) ((r) << 20) 6870 #define DDI_BUF_PORT_REVERSAL (1 << 16) 6871 #define DDI_BUF_IS_IDLE (1 << 7) 6872 #define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6) 6873 #define DDI_A_4_LANES (1 << 4) 6874 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) 6875 #define DDI_PORT_WIDTH_MASK (7 << 1) 6876 #define DDI_PORT_WIDTH_SHIFT 1 6877 #define DDI_INIT_DISPLAY_DETECTED (1 << 0) 6878 6879 /* DDI Buffer Translations */ 6880 #define _DDI_BUF_TRANS_A 0x64E00 6881 #define _DDI_BUF_TRANS_B 0x64E60 6882 #define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8) 6883 #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31) 6884 #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4) 6885 6886 /* DDI DP Compliance Control */ 6887 #define _DDI_DP_COMP_CTL_A 0x605F0 6888 #define _DDI_DP_COMP_CTL_B 0x615F0 6889 #define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B) 6890 #define DDI_DP_COMP_CTL_ENABLE (1 << 31) 6891 #define DDI_DP_COMP_CTL_D10_2 (0 << 28) 6892 #define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28) 6893 #define DDI_DP_COMP_CTL_PRBS7 (2 << 28) 6894 #define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28) 6895 #define DDI_DP_COMP_CTL_HBR2 (4 << 28) 6896 #define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28) 6897 #define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0) 6898 6899 /* DDI DP Compliance Pattern */ 6900 #define _DDI_DP_COMP_PAT_A 0x605F4 6901 #define _DDI_DP_COMP_PAT_B 0x615F4 6902 #define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4) 6903 6904 /* Sideband Interface (SBI) is programmed indirectly, via 6905 * SBI_ADDR, which contains the register offset; and SBI_DATA, 6906 * which contains the payload */ 6907 #define SBI_ADDR _MMIO(0xC6000) 6908 #define SBI_DATA _MMIO(0xC6004) 6909 #define SBI_CTL_STAT _MMIO(0xC6008) 6910 #define SBI_CTL_DEST_ICLK (0x0 << 16) 6911 #define SBI_CTL_DEST_MPHY (0x1 << 16) 6912 #define SBI_CTL_OP_IORD (0x2 << 8) 6913 #define SBI_CTL_OP_IOWR (0x3 << 8) 6914 #define SBI_CTL_OP_CRRD (0x6 << 8) 6915 #define SBI_CTL_OP_CRWR (0x7 << 8) 6916 #define SBI_RESPONSE_FAIL (0x1 << 1) 6917 #define SBI_RESPONSE_SUCCESS (0x0 << 1) 6918 #define SBI_BUSY (0x1 << 0) 6919 #define SBI_READY (0x0 << 0) 6920 6921 /* SBI offsets */ 6922 #define SBI_SSCDIVINTPHASE 0x0200 6923 #define SBI_SSCDIVINTPHASE6 0x0600 6924 #define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1 6925 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1) 6926 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1) 6927 #define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8 6928 #define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8) 6929 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8) 6930 #define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15) 6931 #define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0) 6932 #define SBI_SSCDITHPHASE 0x0204 6933 #define SBI_SSCCTL 0x020c 6934 #define SBI_SSCCTL6 0x060C 6935 #define SBI_SSCCTL_PATHALT (1 << 3) 6936 #define SBI_SSCCTL_DISABLE (1 << 0) 6937 #define SBI_SSCAUXDIV6 0x0610 6938 #define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4 6939 #define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4) 6940 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4) 6941 #define SBI_DBUFF0 0x2a00 6942 #define SBI_GEN0 0x1f00 6943 #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0) 6944 6945 /* LPT PIXCLK_GATE */ 6946 #define PIXCLK_GATE _MMIO(0xC6020) 6947 #define PIXCLK_GATE_UNGATE (1 << 0) 6948 #define PIXCLK_GATE_GATE (0 << 0) 6949 6950 /* SPLL */ 6951 #define SPLL_CTL _MMIO(0x46020) 6952 #define SPLL_PLL_ENABLE (1 << 31) 6953 #define SPLL_REF_BCLK (0 << 28) 6954 #define SPLL_REF_MUXED_SSC (1 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */ 6955 #define SPLL_REF_NON_SSC_HSW (2 << 28) 6956 #define SPLL_REF_PCH_SSC_BDW (2 << 28) 6957 #define SPLL_REF_LCPLL (3 << 28) 6958 #define SPLL_REF_MASK (3 << 28) 6959 #define SPLL_FREQ_810MHz (0 << 26) 6960 #define SPLL_FREQ_1350MHz (1 << 26) 6961 #define SPLL_FREQ_2700MHz (2 << 26) 6962 #define SPLL_FREQ_MASK (3 << 26) 6963 6964 /* WRPLL */ 6965 #define _WRPLL_CTL1 0x46040 6966 #define _WRPLL_CTL2 0x46060 6967 #define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2) 6968 #define WRPLL_PLL_ENABLE (1 << 31) 6969 #define WRPLL_REF_BCLK (0 << 28) 6970 #define WRPLL_REF_PCH_SSC (1 << 28) 6971 #define WRPLL_REF_MUXED_SSC_BDW (2 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */ 6972 #define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */ 6973 #define WRPLL_REF_LCPLL (3 << 28) 6974 #define WRPLL_REF_MASK (3 << 28) 6975 /* WRPLL divider programming */ 6976 #define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0) 6977 #define WRPLL_DIVIDER_REF_MASK (0xff) 6978 #define WRPLL_DIVIDER_POST(x) ((x) << 8) 6979 #define WRPLL_DIVIDER_POST_MASK (0x3f << 8) 6980 #define WRPLL_DIVIDER_POST_SHIFT 8 6981 #define WRPLL_DIVIDER_FEEDBACK(x) ((x) << 16) 6982 #define WRPLL_DIVIDER_FB_SHIFT 16 6983 #define WRPLL_DIVIDER_FB_MASK (0xff << 16) 6984 6985 /* Port clock selection */ 6986 #define _PORT_CLK_SEL_A 0x46100 6987 #define _PORT_CLK_SEL_B 0x46104 6988 #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B) 6989 #define PORT_CLK_SEL_MASK REG_GENMASK(31, 29) 6990 #define PORT_CLK_SEL_LCPLL_2700 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 0) 6991 #define PORT_CLK_SEL_LCPLL_1350 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 1) 6992 #define PORT_CLK_SEL_LCPLL_810 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 2) 6993 #define PORT_CLK_SEL_SPLL REG_FIELD_PREP(PORT_CLK_SEL_MASK, 3) 6994 #define PORT_CLK_SEL_WRPLL(pll) REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4 + (pll)) 6995 #define PORT_CLK_SEL_WRPLL1 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4) 6996 #define PORT_CLK_SEL_WRPLL2 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 5) 6997 #define PORT_CLK_SEL_NONE REG_FIELD_PREP(PORT_CLK_SEL_MASK, 7) 6998 6999 /* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */ 7000 #define DDI_CLK_SEL(port) PORT_CLK_SEL(port) 7001 #define DDI_CLK_SEL_MASK REG_GENMASK(31, 28) 7002 #define DDI_CLK_SEL_NONE REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x0) 7003 #define DDI_CLK_SEL_MG REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x8) 7004 #define DDI_CLK_SEL_TBT_162 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xC) 7005 #define DDI_CLK_SEL_TBT_270 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xD) 7006 #define DDI_CLK_SEL_TBT_540 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xE) 7007 #define DDI_CLK_SEL_TBT_810 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xF) 7008 7009 /* Transcoder clock selection */ 7010 #define _TRANS_CLK_SEL_A 0x46140 7011 #define _TRANS_CLK_SEL_B 0x46144 7012 #define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B) 7013 /* For each transcoder, we need to select the corresponding port clock */ 7014 #define TRANS_CLK_SEL_DISABLED (0x0 << 29) 7015 #define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29) 7016 #define TGL_TRANS_CLK_SEL_DISABLED (0x0 << 28) 7017 #define TGL_TRANS_CLK_SEL_PORT(x) (((x) + 1) << 28) 7018 7019 7020 #define CDCLK_FREQ _MMIO(0x46200) 7021 7022 #define _TRANSA_MSA_MISC 0x60410 7023 #define _TRANSB_MSA_MISC 0x61410 7024 #define _TRANSC_MSA_MISC 0x62410 7025 #define _TRANS_EDP_MSA_MISC 0x6f410 7026 #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC) 7027 /* See DP_MSA_MISC_* for the bit definitions */ 7028 7029 #define _TRANS_A_SET_CONTEXT_LATENCY 0x6007C 7030 #define _TRANS_B_SET_CONTEXT_LATENCY 0x6107C 7031 #define _TRANS_C_SET_CONTEXT_LATENCY 0x6207C 7032 #define _TRANS_D_SET_CONTEXT_LATENCY 0x6307C 7033 #define TRANS_SET_CONTEXT_LATENCY(tran) _MMIO_TRANS2(tran, _TRANS_A_SET_CONTEXT_LATENCY) 7034 #define TRANS_SET_CONTEXT_LATENCY_MASK REG_GENMASK(15, 0) 7035 #define TRANS_SET_CONTEXT_LATENCY_VALUE(x) REG_FIELD_PREP(TRANS_SET_CONTEXT_LATENCY_MASK, (x)) 7036 7037 /* LCPLL Control */ 7038 #define LCPLL_CTL _MMIO(0x130040) 7039 #define LCPLL_PLL_DISABLE (1 << 31) 7040 #define LCPLL_PLL_LOCK (1 << 30) 7041 #define LCPLL_REF_NON_SSC (0 << 28) 7042 #define LCPLL_REF_BCLK (2 << 28) 7043 #define LCPLL_REF_PCH_SSC (3 << 28) 7044 #define LCPLL_REF_MASK (3 << 28) 7045 #define LCPLL_CLK_FREQ_MASK (3 << 26) 7046 #define LCPLL_CLK_FREQ_450 (0 << 26) 7047 #define LCPLL_CLK_FREQ_54O_BDW (1 << 26) 7048 #define LCPLL_CLK_FREQ_337_5_BDW (2 << 26) 7049 #define LCPLL_CLK_FREQ_675_BDW (3 << 26) 7050 #define LCPLL_CD_CLOCK_DISABLE (1 << 25) 7051 #define LCPLL_ROOT_CD_CLOCK_DISABLE (1 << 24) 7052 #define LCPLL_CD2X_CLOCK_DISABLE (1 << 23) 7053 #define LCPLL_POWER_DOWN_ALLOW (1 << 22) 7054 #define LCPLL_CD_SOURCE_FCLK (1 << 21) 7055 #define LCPLL_CD_SOURCE_FCLK_DONE (1 << 19) 7056 7057 /* 7058 * SKL Clocks 7059 */ 7060 7061 /* CDCLK_CTL */ 7062 #define CDCLK_CTL _MMIO(0x46000) 7063 #define CDCLK_FREQ_SEL_MASK REG_GENMASK(27, 26) 7064 #define CDCLK_FREQ_450_432 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 0) 7065 #define CDCLK_FREQ_540 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1) 7066 #define CDCLK_FREQ_337_308 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2) 7067 #define CDCLK_FREQ_675_617 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3) 7068 #define BXT_CDCLK_CD2X_DIV_SEL_MASK REG_GENMASK(23, 22) 7069 #define BXT_CDCLK_CD2X_DIV_SEL_1 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0) 7070 #define BXT_CDCLK_CD2X_DIV_SEL_1_5 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1) 7071 #define BXT_CDCLK_CD2X_DIV_SEL_2 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 2) 7072 #define BXT_CDCLK_CD2X_DIV_SEL_4 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 3) 7073 #define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20) 7074 #define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19) 7075 #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3) 7076 #define ICL_CDCLK_CD2X_PIPE(pipe) (_PICK(pipe, 0, 2, 6) << 19) 7077 #define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19) 7078 #define TGL_CDCLK_CD2X_PIPE(pipe) BXT_CDCLK_CD2X_PIPE(pipe) 7079 #define TGL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE_NONE 7080 #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16) 7081 #define CDCLK_FREQ_DECIMAL_MASK (0x7ff) 7082 7083 /* CDCLK_SQUASH_CTL */ 7084 #define CDCLK_SQUASH_CTL _MMIO(0x46008) 7085 #define CDCLK_SQUASH_ENABLE REG_BIT(31) 7086 #define CDCLK_SQUASH_WINDOW_SIZE_MASK REG_GENMASK(27, 24) 7087 #define CDCLK_SQUASH_WINDOW_SIZE(x) REG_FIELD_PREP(CDCLK_SQUASH_WINDOW_SIZE_MASK, (x)) 7088 #define CDCLK_SQUASH_WAVEFORM_MASK REG_GENMASK(15, 0) 7089 #define CDCLK_SQUASH_WAVEFORM(x) REG_FIELD_PREP(CDCLK_SQUASH_WAVEFORM_MASK, (x)) 7090 7091 /* LCPLL_CTL */ 7092 #define LCPLL1_CTL _MMIO(0x46010) 7093 #define LCPLL2_CTL _MMIO(0x46014) 7094 #define LCPLL_PLL_ENABLE (1 << 31) 7095 7096 /* DPLL control1 */ 7097 #define DPLL_CTRL1 _MMIO(0x6C058) 7098 #define DPLL_CTRL1_HDMI_MODE(id) (1 << ((id) * 6 + 5)) 7099 #define DPLL_CTRL1_SSC(id) (1 << ((id) * 6 + 4)) 7100 #define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id) * 6 + 1)) 7101 #define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id) * 6 + 1) 7102 #define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate) << ((id) * 6 + 1)) 7103 #define DPLL_CTRL1_OVERRIDE(id) (1 << ((id) * 6)) 7104 #define DPLL_CTRL1_LINK_RATE_2700 0 7105 #define DPLL_CTRL1_LINK_RATE_1350 1 7106 #define DPLL_CTRL1_LINK_RATE_810 2 7107 #define DPLL_CTRL1_LINK_RATE_1620 3 7108 #define DPLL_CTRL1_LINK_RATE_1080 4 7109 #define DPLL_CTRL1_LINK_RATE_2160 5 7110 7111 /* DPLL control2 */ 7112 #define DPLL_CTRL2 _MMIO(0x6C05C) 7113 #define DPLL_CTRL2_DDI_CLK_OFF(port) (1 << ((port) + 15)) 7114 #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3 << ((port) * 3 + 1)) 7115 #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port) * 3 + 1) 7116 #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port) * 3 + 1)) 7117 #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1 << ((port) * 3)) 7118 7119 /* DPLL Status */ 7120 #define DPLL_STATUS _MMIO(0x6C060) 7121 #define DPLL_LOCK(id) (1 << ((id) * 8)) 7122 7123 /* DPLL cfg */ 7124 #define _DPLL1_CFGCR1 0x6C040 7125 #define _DPLL2_CFGCR1 0x6C048 7126 #define _DPLL3_CFGCR1 0x6C050 7127 #define DPLL_CFGCR1_FREQ_ENABLE (1 << 31) 7128 #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9) 7129 #define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9) 7130 #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff) 7131 7132 #define _DPLL1_CFGCR2 0x6C044 7133 #define _DPLL2_CFGCR2 0x6C04C 7134 #define _DPLL3_CFGCR2 0x6C054 7135 #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8) 7136 #define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8) 7137 #define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7) 7138 #define DPLL_CFGCR2_KDIV_MASK (3 << 5) 7139 #define DPLL_CFGCR2_KDIV(x) ((x) << 5) 7140 #define DPLL_CFGCR2_KDIV_5 (0 << 5) 7141 #define DPLL_CFGCR2_KDIV_2 (1 << 5) 7142 #define DPLL_CFGCR2_KDIV_3 (2 << 5) 7143 #define DPLL_CFGCR2_KDIV_1 (3 << 5) 7144 #define DPLL_CFGCR2_PDIV_MASK (7 << 2) 7145 #define DPLL_CFGCR2_PDIV(x) ((x) << 2) 7146 #define DPLL_CFGCR2_PDIV_1 (0 << 2) 7147 #define DPLL_CFGCR2_PDIV_2 (1 << 2) 7148 #define DPLL_CFGCR2_PDIV_3 (2 << 2) 7149 #define DPLL_CFGCR2_PDIV_7 (4 << 2) 7150 #define DPLL_CFGCR2_PDIV_7_INVALID (5 << 2) 7151 #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3) 7152 7153 #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1) 7154 #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2) 7155 7156 /* ICL Clocks */ 7157 #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280) 7158 #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24, 4, 5)) 7159 #define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10) 7160 #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \ 7161 (tc_port) + 12 : \ 7162 (tc_port) - TC_PORT_4 + 21)) 7163 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2) 7164 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 7165 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 7166 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27) 7167 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \ 7168 (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 7169 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \ 7170 ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 7171 7172 /* 7173 * DG1 Clocks 7174 * First registers controls the first A and B, while the second register 7175 * controls the phy C and D. The bits on these registers are the 7176 * same, but refer to different phys 7177 */ 7178 #define _DG1_DPCLKA_CFGCR0 0x164280 7179 #define _DG1_DPCLKA1_CFGCR0 0x16C280 7180 #define _DG1_DPCLKA_PHY_IDX(phy) ((phy) % 2) 7181 #define _DG1_DPCLKA_PLL_IDX(pll) ((pll) % 2) 7182 #define DG1_DPCLKA_CFGCR0(phy) _MMIO_PHY((phy) / 2, \ 7183 _DG1_DPCLKA_CFGCR0, \ 7184 _DG1_DPCLKA1_CFGCR0) 7185 #define DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT(_DG1_DPCLKA_PHY_IDX(phy) + 10) 7186 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) (_DG1_DPCLKA_PHY_IDX(phy) * 2) 7187 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) (_DG1_DPCLKA_PLL_IDX(pll) << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 7188 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (0x3 << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 7189 7190 /* ADLS Clocks */ 7191 #define _ADLS_DPCLKA_CFGCR0 0x164280 7192 #define _ADLS_DPCLKA_CFGCR1 0x1642BC 7193 #define ADLS_DPCLKA_CFGCR(phy) _MMIO_PHY((phy) / 3, \ 7194 _ADLS_DPCLKA_CFGCR0, \ 7195 _ADLS_DPCLKA_CFGCR1) 7196 #define ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy) (((phy) % 3) * 2) 7197 /* ADLS DPCLKA_CFGCR0 DDI mask */ 7198 #define ADLS_DPCLKA_DDII_SEL_MASK REG_GENMASK(5, 4) 7199 #define ADLS_DPCLKA_DDIB_SEL_MASK REG_GENMASK(3, 2) 7200 #define ADLS_DPCLKA_DDIA_SEL_MASK REG_GENMASK(1, 0) 7201 /* ADLS DPCLKA_CFGCR1 DDI mask */ 7202 #define ADLS_DPCLKA_DDIK_SEL_MASK REG_GENMASK(3, 2) 7203 #define ADLS_DPCLKA_DDIJ_SEL_MASK REG_GENMASK(1, 0) 7204 #define ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy) _PICK((phy), \ 7205 ADLS_DPCLKA_DDIA_SEL_MASK, \ 7206 ADLS_DPCLKA_DDIB_SEL_MASK, \ 7207 ADLS_DPCLKA_DDII_SEL_MASK, \ 7208 ADLS_DPCLKA_DDIJ_SEL_MASK, \ 7209 ADLS_DPCLKA_DDIK_SEL_MASK) 7210 7211 /* ICL PLL */ 7212 #define DPLL0_ENABLE 0x46010 7213 #define DPLL1_ENABLE 0x46014 7214 #define _ADLS_DPLL2_ENABLE 0x46018 7215 #define _ADLS_DPLL3_ENABLE 0x46030 7216 #define PLL_ENABLE (1 << 31) 7217 #define PLL_LOCK (1 << 30) 7218 #define PLL_POWER_ENABLE (1 << 27) 7219 #define PLL_POWER_STATE (1 << 26) 7220 #define ICL_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \ 7221 _ADLS_DPLL2_ENABLE, _ADLS_DPLL3_ENABLE) 7222 7223 #define _DG2_PLL3_ENABLE 0x4601C 7224 7225 #define DG2_PLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \ 7226 _ADLS_DPLL2_ENABLE, _DG2_PLL3_ENABLE) 7227 7228 #define TBT_PLL_ENABLE _MMIO(0x46020) 7229 7230 #define _MG_PLL1_ENABLE 0x46030 7231 #define _MG_PLL2_ENABLE 0x46034 7232 #define _MG_PLL3_ENABLE 0x46038 7233 #define _MG_PLL4_ENABLE 0x4603C 7234 /* Bits are the same as DPLL0_ENABLE */ 7235 #define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \ 7236 _MG_PLL2_ENABLE) 7237 7238 /* DG1 PLL */ 7239 #define DG1_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \ 7240 _MG_PLL1_ENABLE, _MG_PLL2_ENABLE) 7241 7242 /* ADL-P Type C PLL */ 7243 #define PORTTC1_PLL_ENABLE 0x46038 7244 #define PORTTC2_PLL_ENABLE 0x46040 7245 7246 #define ADLP_PORTTC_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), \ 7247 PORTTC1_PLL_ENABLE, \ 7248 PORTTC2_PLL_ENABLE) 7249 7250 #define _ICL_DPLL0_CFGCR0 0x164000 7251 #define _ICL_DPLL1_CFGCR0 0x164080 7252 #define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \ 7253 _ICL_DPLL1_CFGCR0) 7254 #define DPLL_CFGCR0_HDMI_MODE (1 << 30) 7255 #define DPLL_CFGCR0_SSC_ENABLE (1 << 29) 7256 #define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25) 7257 #define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25) 7258 #define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25) 7259 #define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25) 7260 #define DPLL_CFGCR0_LINK_RATE_810 (2 << 25) 7261 #define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25) 7262 #define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25) 7263 #define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25) 7264 #define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25) 7265 #define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25) 7266 #define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10) 7267 #define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10) 7268 #define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10) 7269 #define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff) 7270 7271 #define _ICL_DPLL0_CFGCR1 0x164004 7272 #define _ICL_DPLL1_CFGCR1 0x164084 7273 #define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \ 7274 _ICL_DPLL1_CFGCR1) 7275 #define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10) 7276 #define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10) 7277 #define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10) 7278 #define DPLL_CFGCR1_QDIV_MODE_SHIFT (9) 7279 #define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9) 7280 #define DPLL_CFGCR1_KDIV_MASK (7 << 6) 7281 #define DPLL_CFGCR1_KDIV_SHIFT (6) 7282 #define DPLL_CFGCR1_KDIV(x) ((x) << 6) 7283 #define DPLL_CFGCR1_KDIV_1 (1 << 6) 7284 #define DPLL_CFGCR1_KDIV_2 (2 << 6) 7285 #define DPLL_CFGCR1_KDIV_3 (4 << 6) 7286 #define DPLL_CFGCR1_PDIV_MASK (0xf << 2) 7287 #define DPLL_CFGCR1_PDIV_SHIFT (2) 7288 #define DPLL_CFGCR1_PDIV(x) ((x) << 2) 7289 #define DPLL_CFGCR1_PDIV_2 (1 << 2) 7290 #define DPLL_CFGCR1_PDIV_3 (2 << 2) 7291 #define DPLL_CFGCR1_PDIV_5 (4 << 2) 7292 #define DPLL_CFGCR1_PDIV_7 (8 << 2) 7293 #define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0) 7294 #define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0) 7295 #define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0) 7296 7297 #define _TGL_DPLL0_CFGCR0 0x164284 7298 #define _TGL_DPLL1_CFGCR0 0x16428C 7299 #define _TGL_TBTPLL_CFGCR0 0x16429C 7300 #define TGL_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \ 7301 _TGL_DPLL1_CFGCR0, \ 7302 _TGL_TBTPLL_CFGCR0) 7303 #define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \ 7304 _TGL_DPLL1_CFGCR0) 7305 7306 #define _TGL_DPLL0_DIV0 0x164B00 7307 #define _TGL_DPLL1_DIV0 0x164C00 7308 #define TGL_DPLL0_DIV0(pll) _MMIO_PLL(pll, _TGL_DPLL0_DIV0, _TGL_DPLL1_DIV0) 7309 #define TGL_DPLL0_DIV0_AFC_STARTUP_MASK REG_GENMASK(27, 25) 7310 #define TGL_DPLL0_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(TGL_DPLL0_DIV0_AFC_STARTUP_MASK, (val)) 7311 7312 #define _TGL_DPLL0_CFGCR1 0x164288 7313 #define _TGL_DPLL1_CFGCR1 0x164290 7314 #define _TGL_TBTPLL_CFGCR1 0x1642A0 7315 #define TGL_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ 7316 _TGL_DPLL1_CFGCR1, \ 7317 _TGL_TBTPLL_CFGCR1) 7318 #define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \ 7319 _TGL_DPLL1_CFGCR1) 7320 7321 #define _DG1_DPLL2_CFGCR0 0x16C284 7322 #define _DG1_DPLL3_CFGCR0 0x16C28C 7323 #define DG1_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \ 7324 _TGL_DPLL1_CFGCR0, \ 7325 _DG1_DPLL2_CFGCR0, \ 7326 _DG1_DPLL3_CFGCR0) 7327 7328 #define _DG1_DPLL2_CFGCR1 0x16C288 7329 #define _DG1_DPLL3_CFGCR1 0x16C290 7330 #define DG1_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ 7331 _TGL_DPLL1_CFGCR1, \ 7332 _DG1_DPLL2_CFGCR1, \ 7333 _DG1_DPLL3_CFGCR1) 7334 7335 /* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */ 7336 #define _ADLS_DPLL3_CFGCR0 0x1642C0 7337 #define _ADLS_DPLL4_CFGCR0 0x164294 7338 #define ADLS_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \ 7339 _TGL_DPLL1_CFGCR0, \ 7340 _ADLS_DPLL4_CFGCR0, \ 7341 _ADLS_DPLL3_CFGCR0) 7342 7343 #define _ADLS_DPLL3_CFGCR1 0x1642C4 7344 #define _ADLS_DPLL4_CFGCR1 0x164298 7345 #define ADLS_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ 7346 _TGL_DPLL1_CFGCR1, \ 7347 _ADLS_DPLL4_CFGCR1, \ 7348 _ADLS_DPLL3_CFGCR1) 7349 7350 /* BXT display engine PLL */ 7351 #define BXT_DE_PLL_CTL _MMIO(0x6d000) 7352 #define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */ 7353 #define BXT_DE_PLL_RATIO_MASK 0xff 7354 7355 #define BXT_DE_PLL_ENABLE _MMIO(0x46070) 7356 #define BXT_DE_PLL_PLL_ENABLE (1 << 31) 7357 #define BXT_DE_PLL_LOCK (1 << 30) 7358 #define BXT_DE_PLL_FREQ_REQ (1 << 23) 7359 #define BXT_DE_PLL_FREQ_REQ_ACK (1 << 22) 7360 #define ICL_CDCLK_PLL_RATIO(x) (x) 7361 #define ICL_CDCLK_PLL_RATIO_MASK 0xff 7362 7363 /* GEN9 DC */ 7364 #define DC_STATE_EN _MMIO(0x45504) 7365 #define DC_STATE_DISABLE 0 7366 #define DC_STATE_EN_DC3CO REG_BIT(30) 7367 #define DC_STATE_DC3CO_STATUS REG_BIT(29) 7368 #define DC_STATE_EN_UPTO_DC5 (1 << 0) 7369 #define DC_STATE_EN_DC9 (1 << 3) 7370 #define DC_STATE_EN_UPTO_DC6 (2 << 0) 7371 #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3 7372 7373 #define DC_STATE_DEBUG _MMIO(0x45520) 7374 #define DC_STATE_DEBUG_MASK_CORES (1 << 0) 7375 #define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1) 7376 7377 #define D_COMP_BDW _MMIO(0x138144) 7378 7379 /* Pipe WM_LINETIME - watermark line time */ 7380 #define _WM_LINETIME_A 0x45270 7381 #define _WM_LINETIME_B 0x45274 7382 #define WM_LINETIME(pipe) _MMIO_PIPE(pipe, _WM_LINETIME_A, _WM_LINETIME_B) 7383 #define HSW_LINETIME_MASK REG_GENMASK(8, 0) 7384 #define HSW_LINETIME(x) REG_FIELD_PREP(HSW_LINETIME_MASK, (x)) 7385 #define HSW_IPS_LINETIME_MASK REG_GENMASK(24, 16) 7386 #define HSW_IPS_LINETIME(x) REG_FIELD_PREP(HSW_IPS_LINETIME_MASK, (x)) 7387 7388 /* SFUSE_STRAP */ 7389 #define SFUSE_STRAP _MMIO(0xc2014) 7390 #define SFUSE_STRAP_FUSE_LOCK (1 << 13) 7391 #define SFUSE_STRAP_RAW_FREQUENCY (1 << 8) 7392 #define SFUSE_STRAP_DISPLAY_DISABLED (1 << 7) 7393 #define SFUSE_STRAP_CRT_DISABLED (1 << 6) 7394 #define SFUSE_STRAP_DDIF_DETECTED (1 << 3) 7395 #define SFUSE_STRAP_DDIB_DETECTED (1 << 2) 7396 #define SFUSE_STRAP_DDIC_DETECTED (1 << 1) 7397 #define SFUSE_STRAP_DDID_DETECTED (1 << 0) 7398 7399 #define WM_MISC _MMIO(0x45260) 7400 #define WM_MISC_DATA_PARTITION_5_6 (1 << 0) 7401 7402 #define WM_DBG _MMIO(0x45280) 7403 #define WM_DBG_DISALLOW_MULTIPLE_LP (1 << 0) 7404 #define WM_DBG_DISALLOW_MAXFIFO (1 << 1) 7405 #define WM_DBG_DISALLOW_SPRITE (1 << 2) 7406 7407 /* pipe CSC */ 7408 #define _PIPE_A_CSC_COEFF_RY_GY 0x49010 7409 #define _PIPE_A_CSC_COEFF_BY 0x49014 7410 #define _PIPE_A_CSC_COEFF_RU_GU 0x49018 7411 #define _PIPE_A_CSC_COEFF_BU 0x4901c 7412 #define _PIPE_A_CSC_COEFF_RV_GV 0x49020 7413 #define _PIPE_A_CSC_COEFF_BV 0x49024 7414 7415 #define _PIPE_A_CSC_MODE 0x49028 7416 #define ICL_CSC_ENABLE (1 << 31) /* icl+ */ 7417 #define ICL_OUTPUT_CSC_ENABLE (1 << 30) /* icl+ */ 7418 #define CSC_BLACK_SCREEN_OFFSET (1 << 2) /* ilk/snb */ 7419 #define CSC_POSITION_BEFORE_GAMMA (1 << 1) /* pre-glk */ 7420 #define CSC_MODE_YUV_TO_RGB (1 << 0) /* ilk/snb */ 7421 7422 #define _PIPE_A_CSC_PREOFF_HI 0x49030 7423 #define _PIPE_A_CSC_PREOFF_ME 0x49034 7424 #define _PIPE_A_CSC_PREOFF_LO 0x49038 7425 #define _PIPE_A_CSC_POSTOFF_HI 0x49040 7426 #define _PIPE_A_CSC_POSTOFF_ME 0x49044 7427 #define _PIPE_A_CSC_POSTOFF_LO 0x49048 7428 7429 #define _PIPE_B_CSC_COEFF_RY_GY 0x49110 7430 #define _PIPE_B_CSC_COEFF_BY 0x49114 7431 #define _PIPE_B_CSC_COEFF_RU_GU 0x49118 7432 #define _PIPE_B_CSC_COEFF_BU 0x4911c 7433 #define _PIPE_B_CSC_COEFF_RV_GV 0x49120 7434 #define _PIPE_B_CSC_COEFF_BV 0x49124 7435 #define _PIPE_B_CSC_MODE 0x49128 7436 #define _PIPE_B_CSC_PREOFF_HI 0x49130 7437 #define _PIPE_B_CSC_PREOFF_ME 0x49134 7438 #define _PIPE_B_CSC_PREOFF_LO 0x49138 7439 #define _PIPE_B_CSC_POSTOFF_HI 0x49140 7440 #define _PIPE_B_CSC_POSTOFF_ME 0x49144 7441 #define _PIPE_B_CSC_POSTOFF_LO 0x49148 7442 7443 #define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY) 7444 #define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY) 7445 #define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU) 7446 #define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU) 7447 #define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV) 7448 #define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV) 7449 #define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE) 7450 #define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI) 7451 #define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME) 7452 #define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO) 7453 #define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI) 7454 #define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME) 7455 #define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) 7456 7457 /* Pipe Output CSC */ 7458 #define _PIPE_A_OUTPUT_CSC_COEFF_RY_GY 0x49050 7459 #define _PIPE_A_OUTPUT_CSC_COEFF_BY 0x49054 7460 #define _PIPE_A_OUTPUT_CSC_COEFF_RU_GU 0x49058 7461 #define _PIPE_A_OUTPUT_CSC_COEFF_BU 0x4905c 7462 #define _PIPE_A_OUTPUT_CSC_COEFF_RV_GV 0x49060 7463 #define _PIPE_A_OUTPUT_CSC_COEFF_BV 0x49064 7464 #define _PIPE_A_OUTPUT_CSC_PREOFF_HI 0x49068 7465 #define _PIPE_A_OUTPUT_CSC_PREOFF_ME 0x4906c 7466 #define _PIPE_A_OUTPUT_CSC_PREOFF_LO 0x49070 7467 #define _PIPE_A_OUTPUT_CSC_POSTOFF_HI 0x49074 7468 #define _PIPE_A_OUTPUT_CSC_POSTOFF_ME 0x49078 7469 #define _PIPE_A_OUTPUT_CSC_POSTOFF_LO 0x4907c 7470 7471 #define _PIPE_B_OUTPUT_CSC_COEFF_RY_GY 0x49150 7472 #define _PIPE_B_OUTPUT_CSC_COEFF_BY 0x49154 7473 #define _PIPE_B_OUTPUT_CSC_COEFF_RU_GU 0x49158 7474 #define _PIPE_B_OUTPUT_CSC_COEFF_BU 0x4915c 7475 #define _PIPE_B_OUTPUT_CSC_COEFF_RV_GV 0x49160 7476 #define _PIPE_B_OUTPUT_CSC_COEFF_BV 0x49164 7477 #define _PIPE_B_OUTPUT_CSC_PREOFF_HI 0x49168 7478 #define _PIPE_B_OUTPUT_CSC_PREOFF_ME 0x4916c 7479 #define _PIPE_B_OUTPUT_CSC_PREOFF_LO 0x49170 7480 #define _PIPE_B_OUTPUT_CSC_POSTOFF_HI 0x49174 7481 #define _PIPE_B_OUTPUT_CSC_POSTOFF_ME 0x49178 7482 #define _PIPE_B_OUTPUT_CSC_POSTOFF_LO 0x4917c 7483 7484 #define PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe,\ 7485 _PIPE_A_OUTPUT_CSC_COEFF_RY_GY,\ 7486 _PIPE_B_OUTPUT_CSC_COEFF_RY_GY) 7487 #define PIPE_CSC_OUTPUT_COEFF_BY(pipe) _MMIO_PIPE(pipe, \ 7488 _PIPE_A_OUTPUT_CSC_COEFF_BY, \ 7489 _PIPE_B_OUTPUT_CSC_COEFF_BY) 7490 #define PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, \ 7491 _PIPE_A_OUTPUT_CSC_COEFF_RU_GU, \ 7492 _PIPE_B_OUTPUT_CSC_COEFF_RU_GU) 7493 #define PIPE_CSC_OUTPUT_COEFF_BU(pipe) _MMIO_PIPE(pipe, \ 7494 _PIPE_A_OUTPUT_CSC_COEFF_BU, \ 7495 _PIPE_B_OUTPUT_CSC_COEFF_BU) 7496 #define PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, \ 7497 _PIPE_A_OUTPUT_CSC_COEFF_RV_GV, \ 7498 _PIPE_B_OUTPUT_CSC_COEFF_RV_GV) 7499 #define PIPE_CSC_OUTPUT_COEFF_BV(pipe) _MMIO_PIPE(pipe, \ 7500 _PIPE_A_OUTPUT_CSC_COEFF_BV, \ 7501 _PIPE_B_OUTPUT_CSC_COEFF_BV) 7502 #define PIPE_CSC_OUTPUT_PREOFF_HI(pipe) _MMIO_PIPE(pipe, \ 7503 _PIPE_A_OUTPUT_CSC_PREOFF_HI, \ 7504 _PIPE_B_OUTPUT_CSC_PREOFF_HI) 7505 #define PIPE_CSC_OUTPUT_PREOFF_ME(pipe) _MMIO_PIPE(pipe, \ 7506 _PIPE_A_OUTPUT_CSC_PREOFF_ME, \ 7507 _PIPE_B_OUTPUT_CSC_PREOFF_ME) 7508 #define PIPE_CSC_OUTPUT_PREOFF_LO(pipe) _MMIO_PIPE(pipe, \ 7509 _PIPE_A_OUTPUT_CSC_PREOFF_LO, \ 7510 _PIPE_B_OUTPUT_CSC_PREOFF_LO) 7511 #define PIPE_CSC_OUTPUT_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, \ 7512 _PIPE_A_OUTPUT_CSC_POSTOFF_HI, \ 7513 _PIPE_B_OUTPUT_CSC_POSTOFF_HI) 7514 #define PIPE_CSC_OUTPUT_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, \ 7515 _PIPE_A_OUTPUT_CSC_POSTOFF_ME, \ 7516 _PIPE_B_OUTPUT_CSC_POSTOFF_ME) 7517 #define PIPE_CSC_OUTPUT_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, \ 7518 _PIPE_A_OUTPUT_CSC_POSTOFF_LO, \ 7519 _PIPE_B_OUTPUT_CSC_POSTOFF_LO) 7520 7521 /* pipe degamma/gamma LUTs on IVB+ */ 7522 #define _PAL_PREC_INDEX_A 0x4A400 7523 #define _PAL_PREC_INDEX_B 0x4AC00 7524 #define _PAL_PREC_INDEX_C 0x4B400 7525 #define PAL_PREC_SPLIT_MODE REG_BIT(31) 7526 #define PAL_PREC_AUTO_INCREMENT REG_BIT(15) 7527 #define PAL_PREC_INDEX_VALUE_MASK REG_GENMASK(9, 0) 7528 #define PAL_PREC_INDEX_VALUE(x) REG_FIELD_PREP(PAL_PREC_INDEX_VALUE_MASK, (x)) 7529 #define _PAL_PREC_DATA_A 0x4A404 7530 #define _PAL_PREC_DATA_B 0x4AC04 7531 #define _PAL_PREC_DATA_C 0x4B404 7532 /* see PREC_PALETTE_* for the bits */ 7533 #define _PAL_PREC_GC_MAX_A 0x4A410 7534 #define _PAL_PREC_GC_MAX_B 0x4AC10 7535 #define _PAL_PREC_GC_MAX_C 0x4B410 7536 #define _PAL_PREC_EXT_GC_MAX_A 0x4A420 7537 #define _PAL_PREC_EXT_GC_MAX_B 0x4AC20 7538 #define _PAL_PREC_EXT_GC_MAX_C 0x4B420 7539 #define _PAL_PREC_EXT2_GC_MAX_A 0x4A430 7540 #define _PAL_PREC_EXT2_GC_MAX_B 0x4AC30 7541 #define _PAL_PREC_EXT2_GC_MAX_C 0x4B430 7542 7543 #define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B) 7544 #define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B) 7545 #define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4) /* u1.16 */ 7546 #define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4) /* u3.16 */ 7547 #define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4) /* glk+, u3.16 */ 7548 7549 #define _PRE_CSC_GAMC_INDEX_A 0x4A484 7550 #define _PRE_CSC_GAMC_INDEX_B 0x4AC84 7551 #define _PRE_CSC_GAMC_INDEX_C 0x4B484 7552 #define PRE_CSC_GAMC_AUTO_INCREMENT REG_BIT(10) 7553 #define PRE_CSC_GAMC_INDEX_VALUE_MASK REG_GENMASK(7, 0) 7554 #define PRE_CSC_GAMC_INDEX_VALUE(x) REG_FIELD_PREP(PRE_CSC_GAMC_INDEX_VALUE_MASK, (x)) 7555 #define _PRE_CSC_GAMC_DATA_A 0x4A488 7556 #define _PRE_CSC_GAMC_DATA_B 0x4AC88 7557 #define _PRE_CSC_GAMC_DATA_C 0x4B488 7558 7559 #define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B) 7560 #define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B) 7561 7562 /* ICL Multi segmented gamma */ 7563 #define _PAL_PREC_MULTI_SEG_INDEX_A 0x4A408 7564 #define _PAL_PREC_MULTI_SEG_INDEX_B 0x4AC08 7565 #define PAL_PREC_MULTI_SEG_AUTO_INCREMENT REG_BIT(15) 7566 #define PAL_PREC_MULTI_SEG_INDEX_VALUE_MASK REG_GENMASK(4, 0) 7567 #define PAL_PREC_MULTI_SEG_INDEX_VALUE(x) REG_FIELD_PREP(PAL_PREC_MULTI_SEG_INDEX_VALUE_MASK, (x)) 7568 7569 #define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C 7570 #define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C 7571 /* see PREC_PALETTE_12P4_* for the bits */ 7572 7573 #define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \ 7574 _PAL_PREC_MULTI_SEG_INDEX_A, \ 7575 _PAL_PREC_MULTI_SEG_INDEX_B) 7576 #define PREC_PAL_MULTI_SEG_DATA(pipe) _MMIO_PIPE(pipe, \ 7577 _PAL_PREC_MULTI_SEG_DATA_A, \ 7578 _PAL_PREC_MULTI_SEG_DATA_B) 7579 7580 #define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4) 7581 7582 /* Plane CSC Registers */ 7583 #define _PLANE_CSC_RY_GY_1_A 0x70210 7584 #define _PLANE_CSC_RY_GY_2_A 0x70310 7585 7586 #define _PLANE_CSC_RY_GY_1_B 0x71210 7587 #define _PLANE_CSC_RY_GY_2_B 0x71310 7588 7589 #define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, \ 7590 _PLANE_CSC_RY_GY_1_B) 7591 #define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \ 7592 _PLANE_INPUT_CSC_RY_GY_2_B) 7593 #define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane, \ 7594 _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \ 7595 _PLANE_CSC_RY_GY_2(pipe) + (index) * 4) 7596 7597 #define _PLANE_CSC_PREOFF_HI_1_A 0x70228 7598 #define _PLANE_CSC_PREOFF_HI_2_A 0x70328 7599 7600 #define _PLANE_CSC_PREOFF_HI_1_B 0x71228 7601 #define _PLANE_CSC_PREOFF_HI_2_B 0x71328 7602 7603 #define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, \ 7604 _PLANE_CSC_PREOFF_HI_1_B) 7605 #define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, \ 7606 _PLANE_CSC_PREOFF_HI_2_B) 7607 #define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + \ 7608 (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \ 7609 (index) * 4) 7610 7611 #define _PLANE_CSC_POSTOFF_HI_1_A 0x70234 7612 #define _PLANE_CSC_POSTOFF_HI_2_A 0x70334 7613 7614 #define _PLANE_CSC_POSTOFF_HI_1_B 0x71234 7615 #define _PLANE_CSC_POSTOFF_HI_2_B 0x71334 7616 7617 #define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, \ 7618 _PLANE_CSC_POSTOFF_HI_1_B) 7619 #define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, \ 7620 _PLANE_CSC_POSTOFF_HI_2_B) 7621 #define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + \ 7622 (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \ 7623 (index) * 4) 7624 7625 /* pipe CSC & degamma/gamma LUTs on CHV */ 7626 #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900) 7627 #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904) 7628 #define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908) 7629 #define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C) 7630 #define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910) 7631 #define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000) 7632 /* cgm degamma ldw */ 7633 #define CGM_PIPE_DEGAMMA_GREEN_LDW_MASK REG_GENMASK(29, 16) 7634 #define CGM_PIPE_DEGAMMA_BLUE_LDW_MASK REG_GENMASK(13, 0) 7635 /* cgm degamma udw */ 7636 #define CGM_PIPE_DEGAMMA_RED_UDW_MASK REG_GENMASK(13, 0) 7637 #define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000) 7638 /* cgm gamma ldw */ 7639 #define CGM_PIPE_GAMMA_GREEN_LDW_MASK REG_GENMASK(25, 16) 7640 #define CGM_PIPE_GAMMA_BLUE_LDW_MASK REG_GENMASK(9, 0) 7641 /* cgm gamma udw */ 7642 #define CGM_PIPE_GAMMA_RED_UDW_MASK REG_GENMASK(9, 0) 7643 #define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00) 7644 #define CGM_PIPE_MODE_GAMMA (1 << 2) 7645 #define CGM_PIPE_MODE_CSC (1 << 1) 7646 #define CGM_PIPE_MODE_DEGAMMA (1 << 0) 7647 7648 #define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900) 7649 #define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904) 7650 #define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908) 7651 #define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C) 7652 #define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910) 7653 #define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000) 7654 #define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000) 7655 #define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00) 7656 7657 #define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01) 7658 #define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23) 7659 #define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45) 7660 #define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67) 7661 #define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8) 7662 #define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4) 7663 #define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4) 7664 #define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE) 7665 7666 /* Gen4+ Timestamp and Pipe Frame time stamp registers */ 7667 #define GEN4_TIMESTAMP _MMIO(0x2358) 7668 #define ILK_TIMESTAMP_HI _MMIO(0x70070) 7669 #define IVB_TIMESTAMP_CTR _MMIO(0x44070) 7670 7671 #define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074) 7672 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0 7673 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff 7674 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12 7675 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12) 7676 7677 #define _PIPE_FRMTMSTMP_A 0x70048 7678 #define PIPE_FRMTMSTMP(pipe) \ 7679 _MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A) 7680 7681 /* Display Stream Splitter Control */ 7682 #define DSS_CTL1 _MMIO(0x67400) 7683 #define SPLITTER_ENABLE (1 << 31) 7684 #define JOINER_ENABLE (1 << 30) 7685 #define DUAL_LINK_MODE_INTERLEAVE (1 << 24) 7686 #define DUAL_LINK_MODE_FRONTBACK (0 << 24) 7687 #define OVERLAP_PIXELS_MASK (0xf << 16) 7688 #define OVERLAP_PIXELS(pixels) ((pixels) << 16) 7689 #define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) 7690 #define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) 7691 #define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0 7692 7693 #define DSS_CTL2 _MMIO(0x67404) 7694 #define LEFT_BRANCH_VDSC_ENABLE (1 << 31) 7695 #define RIGHT_BRANCH_VDSC_ENABLE (1 << 15) 7696 #define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) 7697 #define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) 7698 7699 #define _ICL_PIPE_DSS_CTL1_PB 0x78200 7700 #define _ICL_PIPE_DSS_CTL1_PC 0x78400 7701 #define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7702 _ICL_PIPE_DSS_CTL1_PB, \ 7703 _ICL_PIPE_DSS_CTL1_PC) 7704 #define BIG_JOINER_ENABLE (1 << 29) 7705 #define MASTER_BIG_JOINER_ENABLE (1 << 28) 7706 #define VGA_CENTERING_ENABLE (1 << 27) 7707 #define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25) 7708 #define SPLITTER_CONFIGURATION_2_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0) 7709 #define SPLITTER_CONFIGURATION_4_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1) 7710 #define UNCOMPRESSED_JOINER_MASTER (1 << 21) 7711 #define UNCOMPRESSED_JOINER_SLAVE (1 << 20) 7712 7713 #define _ICL_PIPE_DSS_CTL2_PB 0x78204 7714 #define _ICL_PIPE_DSS_CTL2_PC 0x78404 7715 #define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7716 _ICL_PIPE_DSS_CTL2_PB, \ 7717 _ICL_PIPE_DSS_CTL2_PC) 7718 7719 #define GGC _MMIO(0x108040) 7720 #define GMS_MASK REG_GENMASK(15, 8) 7721 #define GGMS_MASK REG_GENMASK(7, 6) 7722 7723 #define GEN12_GSMBASE _MMIO(0x108100) 7724 #define GEN12_DSMBASE _MMIO(0x1080C0) 7725 #define GEN12_BDSM_MASK REG_GENMASK64(63, 20) 7726 7727 #define XEHP_CLOCK_GATE_DIS _MMIO(0x101014) 7728 #define SGSI_SIDECLK_DIS REG_BIT(17) 7729 #define SGGI_DIS REG_BIT(15) 7730 #define SGR_DIS REG_BIT(13) 7731 7732 #define _ICL_PHY_MISC_A 0x64C00 7733 #define _ICL_PHY_MISC_B 0x64C04 7734 #define _DG2_PHY_MISC_TC1 0x64C14 /* TC1="PHY E" but offset as if "PHY F" */ 7735 #define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, _ICL_PHY_MISC_B) 7736 #define DG2_PHY_MISC(port) ((port) == PHY_E ? _MMIO(_DG2_PHY_MISC_TC1) : \ 7737 ICL_PHY_MISC(port)) 7738 #define ICL_PHY_MISC_MUX_DDID (1 << 28) 7739 #define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23) 7740 #define DG2_PHY_DP_TX_ACK_MASK REG_GENMASK(23, 20) 7741 7742 /* Icelake Display Stream Compression Registers */ 7743 #define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200) 7744 #define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00) 7745 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270 7746 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370 7747 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470 7748 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC 0x78570 7749 #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7750 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \ 7751 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC) 7752 #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7753 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \ 7754 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC) 7755 #define DSC_ALT_ICH_SEL (1 << 20) 7756 #define DSC_VBR_ENABLE (1 << 19) 7757 #define DSC_422_ENABLE (1 << 18) 7758 #define DSC_COLOR_SPACE_CONVERSION (1 << 17) 7759 #define DSC_BLOCK_PREDICTION (1 << 16) 7760 #define DSC_LINE_BUF_DEPTH_SHIFT 12 7761 #define DSC_BPC_SHIFT 8 7762 #define DSC_VER_MIN_SHIFT 4 7763 #define DSC_VER_MAJ (0x1 << 0) 7764 7765 #define DSCA_PICTURE_PARAMETER_SET_1 _MMIO(0x6B204) 7766 #define DSCC_PICTURE_PARAMETER_SET_1 _MMIO(0x6BA04) 7767 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB 0x78274 7768 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB 0x78374 7769 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC 0x78474 7770 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC 0x78574 7771 #define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7772 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \ 7773 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC) 7774 #define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7775 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \ 7776 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC) 7777 #define DSC_BPP(bpp) ((bpp) << 0) 7778 7779 #define DSCA_PICTURE_PARAMETER_SET_2 _MMIO(0x6B208) 7780 #define DSCC_PICTURE_PARAMETER_SET_2 _MMIO(0x6BA08) 7781 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB 0x78278 7782 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB 0x78378 7783 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC 0x78478 7784 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC 0x78578 7785 #define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7786 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \ 7787 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC) 7788 #define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7789 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \ 7790 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC) 7791 #define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16) 7792 #define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0) 7793 7794 #define DSCA_PICTURE_PARAMETER_SET_3 _MMIO(0x6B20C) 7795 #define DSCC_PICTURE_PARAMETER_SET_3 _MMIO(0x6BA0C) 7796 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB 0x7827C 7797 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB 0x7837C 7798 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC 0x7847C 7799 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC 0x7857C 7800 #define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7801 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \ 7802 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC) 7803 #define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7804 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \ 7805 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC) 7806 #define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16) 7807 #define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0) 7808 7809 #define DSCA_PICTURE_PARAMETER_SET_4 _MMIO(0x6B210) 7810 #define DSCC_PICTURE_PARAMETER_SET_4 _MMIO(0x6BA10) 7811 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB 0x78280 7812 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB 0x78380 7813 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC 0x78480 7814 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC 0x78580 7815 #define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7816 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \ 7817 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC) 7818 #define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7819 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \ 7820 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC) 7821 #define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16) 7822 #define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0) 7823 7824 #define DSCA_PICTURE_PARAMETER_SET_5 _MMIO(0x6B214) 7825 #define DSCC_PICTURE_PARAMETER_SET_5 _MMIO(0x6BA14) 7826 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB 0x78284 7827 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB 0x78384 7828 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC 0x78484 7829 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC 0x78584 7830 #define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7831 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \ 7832 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC) 7833 #define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7834 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \ 7835 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC) 7836 #define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16) 7837 #define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0) 7838 7839 #define DSCA_PICTURE_PARAMETER_SET_6 _MMIO(0x6B218) 7840 #define DSCC_PICTURE_PARAMETER_SET_6 _MMIO(0x6BA18) 7841 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB 0x78288 7842 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB 0x78388 7843 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC 0x78488 7844 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC 0x78588 7845 #define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7846 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \ 7847 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC) 7848 #define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7849 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \ 7850 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC) 7851 #define DSC_FLATNESS_MAX_QP(max_qp) ((max_qp) << 24) 7852 #define DSC_FLATNESS_MIN_QP(min_qp) ((min_qp) << 16) 7853 #define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8) 7854 #define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0) 7855 7856 #define DSCA_PICTURE_PARAMETER_SET_7 _MMIO(0x6B21C) 7857 #define DSCC_PICTURE_PARAMETER_SET_7 _MMIO(0x6BA1C) 7858 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB 0x7828C 7859 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB 0x7838C 7860 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC 0x7848C 7861 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC 0x7858C 7862 #define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7863 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \ 7864 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC) 7865 #define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7866 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \ 7867 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC) 7868 #define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16) 7869 #define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0) 7870 7871 #define DSCA_PICTURE_PARAMETER_SET_8 _MMIO(0x6B220) 7872 #define DSCC_PICTURE_PARAMETER_SET_8 _MMIO(0x6BA20) 7873 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB 0x78290 7874 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB 0x78390 7875 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC 0x78490 7876 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC 0x78590 7877 #define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7878 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \ 7879 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC) 7880 #define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7881 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \ 7882 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC) 7883 #define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16) 7884 #define DSC_FINAL_OFFSET(final_offset) ((final_offset) << 0) 7885 7886 #define DSCA_PICTURE_PARAMETER_SET_9 _MMIO(0x6B224) 7887 #define DSCC_PICTURE_PARAMETER_SET_9 _MMIO(0x6BA24) 7888 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB 0x78294 7889 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB 0x78394 7890 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC 0x78494 7891 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC 0x78594 7892 #define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7893 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \ 7894 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC) 7895 #define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7896 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \ 7897 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC) 7898 #define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16) 7899 #define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0) 7900 7901 #define DSCA_PICTURE_PARAMETER_SET_10 _MMIO(0x6B228) 7902 #define DSCC_PICTURE_PARAMETER_SET_10 _MMIO(0x6BA28) 7903 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298 7904 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398 7905 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498 7906 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC 0x78598 7907 #define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7908 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \ 7909 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC) 7910 #define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7911 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \ 7912 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC) 7913 #define DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low) ((rc_tgt_off_low) << 20) 7914 #define DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high) ((rc_tgt_off_high) << 16) 7915 #define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8) 7916 #define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0) 7917 7918 #define DSCA_PICTURE_PARAMETER_SET_11 _MMIO(0x6B22C) 7919 #define DSCC_PICTURE_PARAMETER_SET_11 _MMIO(0x6BA2C) 7920 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C 7921 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C 7922 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C 7923 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC 0x7859C 7924 #define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7925 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \ 7926 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC) 7927 #define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7928 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \ 7929 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC) 7930 7931 #define DSCA_PICTURE_PARAMETER_SET_12 _MMIO(0x6B260) 7932 #define DSCC_PICTURE_PARAMETER_SET_12 _MMIO(0x6BA60) 7933 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0 7934 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0 7935 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0 7936 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC 0x785A0 7937 #define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7938 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \ 7939 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC) 7940 #define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7941 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \ 7942 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC) 7943 7944 #define DSCA_PICTURE_PARAMETER_SET_13 _MMIO(0x6B264) 7945 #define DSCC_PICTURE_PARAMETER_SET_13 _MMIO(0x6BA64) 7946 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4 7947 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4 7948 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4 7949 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC 0x785A4 7950 #define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7951 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \ 7952 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC) 7953 #define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7954 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \ 7955 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC) 7956 7957 #define DSCA_PICTURE_PARAMETER_SET_14 _MMIO(0x6B268) 7958 #define DSCC_PICTURE_PARAMETER_SET_14 _MMIO(0x6BA68) 7959 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8 7960 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8 7961 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8 7962 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC 0x785A8 7963 #define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7964 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \ 7965 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC) 7966 #define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7967 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \ 7968 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC) 7969 7970 #define DSCA_PICTURE_PARAMETER_SET_15 _MMIO(0x6B26C) 7971 #define DSCC_PICTURE_PARAMETER_SET_15 _MMIO(0x6BA6C) 7972 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC 7973 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC 7974 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC 7975 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC 0x785AC 7976 #define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7977 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \ 7978 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC) 7979 #define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7980 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \ 7981 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC) 7982 7983 #define DSCA_PICTURE_PARAMETER_SET_16 _MMIO(0x6B270) 7984 #define DSCC_PICTURE_PARAMETER_SET_16 _MMIO(0x6BA70) 7985 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0 7986 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0 7987 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0 7988 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC 0x785B0 7989 #define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7990 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \ 7991 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC) 7992 #define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7993 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \ 7994 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC) 7995 #define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) ((slice_row_per_frame) << 20) 7996 #define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16) 7997 #define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0) 7998 7999 /* Icelake Rate Control Buffer Threshold Registers */ 8000 #define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230) 8001 #define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4) 8002 #define DSCC_RC_BUF_THRESH_0 _MMIO(0x6BA30) 8003 #define DSCC_RC_BUF_THRESH_0_UDW _MMIO(0x6BA30 + 4) 8004 #define _ICL_DSC0_RC_BUF_THRESH_0_PB (0x78254) 8005 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB (0x78254 + 4) 8006 #define _ICL_DSC1_RC_BUF_THRESH_0_PB (0x78354) 8007 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB (0x78354 + 4) 8008 #define _ICL_DSC0_RC_BUF_THRESH_0_PC (0x78454) 8009 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC (0x78454 + 4) 8010 #define _ICL_DSC1_RC_BUF_THRESH_0_PC (0x78554) 8011 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC (0x78554 + 4) 8012 #define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8013 _ICL_DSC0_RC_BUF_THRESH_0_PB, \ 8014 _ICL_DSC0_RC_BUF_THRESH_0_PC) 8015 #define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8016 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \ 8017 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC) 8018 #define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8019 _ICL_DSC1_RC_BUF_THRESH_0_PB, \ 8020 _ICL_DSC1_RC_BUF_THRESH_0_PC) 8021 #define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8022 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \ 8023 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC) 8024 8025 #define DSCA_RC_BUF_THRESH_1 _MMIO(0x6B238) 8026 #define DSCA_RC_BUF_THRESH_1_UDW _MMIO(0x6B238 + 4) 8027 #define DSCC_RC_BUF_THRESH_1 _MMIO(0x6BA38) 8028 #define DSCC_RC_BUF_THRESH_1_UDW _MMIO(0x6BA38 + 4) 8029 #define _ICL_DSC0_RC_BUF_THRESH_1_PB (0x7825C) 8030 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB (0x7825C + 4) 8031 #define _ICL_DSC1_RC_BUF_THRESH_1_PB (0x7835C) 8032 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB (0x7835C + 4) 8033 #define _ICL_DSC0_RC_BUF_THRESH_1_PC (0x7845C) 8034 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC (0x7845C + 4) 8035 #define _ICL_DSC1_RC_BUF_THRESH_1_PC (0x7855C) 8036 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC (0x7855C + 4) 8037 #define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8038 _ICL_DSC0_RC_BUF_THRESH_1_PB, \ 8039 _ICL_DSC0_RC_BUF_THRESH_1_PC) 8040 #define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8041 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \ 8042 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC) 8043 #define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8044 _ICL_DSC1_RC_BUF_THRESH_1_PB, \ 8045 _ICL_DSC1_RC_BUF_THRESH_1_PC) 8046 #define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8047 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \ 8048 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC) 8049 8050 #define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0) 8051 #define MODULAR_FIA_MASK (1 << 4) 8052 #define TC_LIVE_STATE_TBT(idx) (1 << ((idx) * 8 + 6)) 8053 #define TC_LIVE_STATE_TC(idx) (1 << ((idx) * 8 + 5)) 8054 #define DP_LANE_ASSIGNMENT_SHIFT(idx) ((idx) * 8) 8055 #define DP_LANE_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 8)) 8056 #define DP_LANE_ASSIGNMENT(idx, x) ((x) << ((idx) * 8)) 8057 8058 #define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890) 8059 #define DP_PHY_MODE_STATUS_COMPLETED(idx) (1 << (idx)) 8060 8061 #define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894) 8062 #define DP_PHY_MODE_STATUS_NOT_SAFE(idx) (1 << (idx)) 8063 8064 #define PORT_TX_DFLEXPA1(fia) _MMIO_FIA((fia), 0x00880) 8065 #define DP_PIN_ASSIGNMENT_SHIFT(idx) ((idx) * 4) 8066 #define DP_PIN_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 4)) 8067 #define DP_PIN_ASSIGNMENT(idx, x) ((x) << ((idx) * 4)) 8068 8069 #define _TCSS_DDI_STATUS_1 0x161500 8070 #define _TCSS_DDI_STATUS_2 0x161504 8071 #define TCSS_DDI_STATUS(tc) _MMIO(_PICK_EVEN(tc, \ 8072 _TCSS_DDI_STATUS_1, \ 8073 _TCSS_DDI_STATUS_2)) 8074 #define TCSS_DDI_STATUS_READY REG_BIT(2) 8075 #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1) 8076 #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0) 8077 8078 #define PRIMARY_SPI_TRIGGER _MMIO(0x102040) 8079 #define PRIMARY_SPI_ADDRESS _MMIO(0x102080) 8080 #define PRIMARY_SPI_REGIONID _MMIO(0x102084) 8081 #define SPI_STATIC_REGIONS _MMIO(0x102090) 8082 #define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0) 8083 #define OROM_OFFSET _MMIO(0x1020c0) 8084 #define OROM_OFFSET_MASK REG_GENMASK(20, 16) 8085 8086 /* This register controls the Display State Buffer (DSB) engines. */ 8087 #define _DSBSL_INSTANCE_BASE 0x70B00 8088 #define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \ 8089 (pipe) * 0x1000 + (id) * 0x100) 8090 #define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0) 8091 #define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4) 8092 #define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8) 8093 #define DSB_ENABLE (1 << 31) 8094 #define DSB_STATUS (1 << 0) 8095 8096 #define CLKREQ_POLICY _MMIO(0x101038) 8097 #define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1) 8098 8099 #define CLKGATE_DIS_MISC _MMIO(0x46534) 8100 #define CLKGATE_DIS_MISC_DMASC_GATING_DIS REG_BIT(21) 8101 8102 #define GEN12_CULLBIT1 _MMIO(0x6100) 8103 #define GEN12_CULLBIT2 _MMIO(0x7030) 8104 #define GEN12_STATE_ACK_DEBUG _MMIO(0x20BC) 8105 8106 #define _MTL_CLKGATE_DIS_TRANS_A 0x604E8 8107 #define _MTL_CLKGATE_DIS_TRANS_B 0x614E8 8108 #define MTL_CLKGATE_DIS_TRANS(trans) _MMIO_TRANS2(trans, _MTL_CLKGATE_DIS_TRANS_A) 8109 #define MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS REG_BIT(7) 8110 8111 #define MTL_LATENCY_LP0_LP1 _MMIO(0x45780) 8112 #define MTL_LATENCY_LP2_LP3 _MMIO(0x45784) 8113 #define MTL_LATENCY_LP4_LP5 _MMIO(0x45788) 8114 #define MTL_LATENCY_LEVEL_EVEN_MASK REG_GENMASK(12, 0) 8115 #define MTL_LATENCY_LEVEL_ODD_MASK REG_GENMASK(28, 16) 8116 8117 #define MTL_LATENCY_SAGV _MMIO(0x4578b) 8118 #define MTL_LATENCY_QCLK_SAGV REG_GENMASK(12, 0) 8119 8120 #define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700) 8121 #define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8) 8122 #define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4) 8123 #define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0) 8124 8125 #define MTL_MEM_SS_INFO_QGV_POINT_LOW(point) _MMIO(0x45710 + (point) * 2) 8126 #define MTL_TRCD_MASK REG_GENMASK(31, 24) 8127 #define MTL_TRP_MASK REG_GENMASK(23, 16) 8128 #define MTL_DCLK_MASK REG_GENMASK(15, 0) 8129 8130 #define MTL_MEM_SS_INFO_QGV_POINT_HIGH(point) _MMIO(0x45714 + (point) * 2) 8131 #define MTL_TRAS_MASK REG_GENMASK(16, 8) 8132 #define MTL_TRDPRE_MASK REG_GENMASK(7, 0) 8133 8134 #define MTL_MEDIA_GSI_BASE 0x380000 8135 8136 #endif /* _I915_REG_H_ */ 8137