1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 2 * All Rights Reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef _I915_REG_H_ 26 #define _I915_REG_H_ 27 28 typedef struct { 29 uint32_t reg; 30 } i915_reg_t; 31 32 #define _MMIO(r) ((const i915_reg_t){ .reg = (r) }) 33 34 #define INVALID_MMIO_REG _MMIO(0) 35 36 static inline uint32_t i915_mmio_reg_offset(i915_reg_t reg) 37 { 38 return reg.reg; 39 } 40 41 static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b) 42 { 43 return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b); 44 } 45 46 static inline bool i915_mmio_reg_valid(i915_reg_t reg) 47 { 48 return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG); 49 } 50 51 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) 52 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) 53 #define _PLANE(plane, a, b) _PIPE(plane, a, b) 54 #define _MMIO_PLANE(plane, a, b) _MMIO_PIPE(plane, a, b) 55 #define _TRANS(tran, a, b) ((a) + (tran)*((b)-(a))) 56 #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b)) 57 #define _PORT(port, a, b) ((a) + (port)*((b)-(a))) 58 #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b)) 59 #define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \ 60 (pipe) == PIPE_B ? (b) : (c)) 61 #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PIPE3(pipe, a, b, c)) 62 #define _PORT3(port, a, b, c) ((port) == PORT_A ? (a) : \ 63 (port) == PORT_B ? (b) : (c)) 64 #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PORT3(pipe, a, b, c)) 65 66 #define _MASKED_FIELD(mask, value) ({ \ 67 if (__builtin_constant_p(mask)) \ 68 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \ 69 if (__builtin_constant_p(value)) \ 70 BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \ 71 if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \ 72 BUILD_BUG_ON_MSG((value) & ~(mask), \ 73 "Incorrect value for mask"); \ 74 (mask) << 16 | (value); }) 75 #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) 76 #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0)) 77 78 79 80 /* PCI config space */ 81 82 #define HPLLCC 0xc0 /* 85x only */ 83 #define GC_CLOCK_CONTROL_MASK (0x7 << 0) 84 #define GC_CLOCK_133_200 (0 << 0) 85 #define GC_CLOCK_100_200 (1 << 0) 86 #define GC_CLOCK_100_133 (2 << 0) 87 #define GC_CLOCK_133_266 (3 << 0) 88 #define GC_CLOCK_133_200_2 (4 << 0) 89 #define GC_CLOCK_133_266_2 (5 << 0) 90 #define GC_CLOCK_166_266 (6 << 0) 91 #define GC_CLOCK_166_250 (7 << 0) 92 93 #define GCFGC2 0xda 94 #define GCFGC 0xf0 /* 915+ only */ 95 #define GC_LOW_FREQUENCY_ENABLE (1 << 7) 96 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) 97 #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) 98 #define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4) 99 #define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4) 100 #define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4) 101 #define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4) 102 #define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4) 103 #define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4) 104 #define GC_DISPLAY_CLOCK_MASK (7 << 4) 105 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) 106 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) 107 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) 108 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) 109 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) 110 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0) 111 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) 112 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) 113 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) 114 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) 115 #define I945_GC_RENDER_CLOCK_MASK (7 << 0) 116 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) 117 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) 118 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) 119 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) 120 #define I915_GC_RENDER_CLOCK_MASK (7 << 0) 121 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) 122 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) 123 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) 124 #define GCDGMBUS 0xcc 125 #define PCI_LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */ 126 127 128 /* Graphics reset regs */ 129 #define I915_GDRST 0xc0 /* PCI config register */ 130 #define GRDOM_FULL (0<<2) 131 #define GRDOM_RENDER (1<<2) 132 #define GRDOM_MEDIA (3<<2) 133 #define GRDOM_MASK (3<<2) 134 #define GRDOM_RESET_STATUS (1<<1) 135 #define GRDOM_RESET_ENABLE (1<<0) 136 137 #define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4) 138 #define ILK_GRDOM_FULL (0<<1) 139 #define ILK_GRDOM_RENDER (1<<1) 140 #define ILK_GRDOM_MEDIA (3<<1) 141 #define ILK_GRDOM_MASK (3<<1) 142 #define ILK_GRDOM_RESET_ENABLE (1<<0) 143 144 #define GEN6_MBCUNIT_SNPCR _MMIO(0x900c) /* for LLC config */ 145 #define GEN6_MBC_SNPCR_SHIFT 21 146 #define GEN6_MBC_SNPCR_MASK (3<<21) 147 #define GEN6_MBC_SNPCR_MAX (0<<21) 148 #define GEN6_MBC_SNPCR_MED (1<<21) 149 #define GEN6_MBC_SNPCR_LOW (2<<21) 150 #define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */ 151 152 #define VLV_G3DCTL _MMIO(0x9024) 153 #define VLV_GSCKGCTL _MMIO(0x9028) 154 155 #define GEN6_MBCTL _MMIO(0x0907c) 156 #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4) 157 #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3) 158 #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2) 159 #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1) 160 #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0) 161 162 #define GEN6_GDRST _MMIO(0x941c) 163 #define GEN6_GRDOM_FULL (1 << 0) 164 #define GEN6_GRDOM_RENDER (1 << 1) 165 #define GEN6_GRDOM_MEDIA (1 << 2) 166 #define GEN6_GRDOM_BLT (1 << 3) 167 #define GEN6_GRDOM_VECS (1 << 4) 168 #define GEN9_GRDOM_GUC (1 << 5) 169 #define GEN8_GRDOM_MEDIA2 (1 << 7) 170 171 #define RING_PP_DIR_BASE(ring) _MMIO((ring)->mmio_base+0x228) 172 #define RING_PP_DIR_BASE_READ(ring) _MMIO((ring)->mmio_base+0x518) 173 #define RING_PP_DIR_DCLV(ring) _MMIO((ring)->mmio_base+0x220) 174 #define PP_DIR_DCLV_2G 0xffffffff 175 176 #define GEN8_RING_PDP_UDW(ring, n) _MMIO((ring)->mmio_base+0x270 + (n) * 8 + 4) 177 #define GEN8_RING_PDP_LDW(ring, n) _MMIO((ring)->mmio_base+0x270 + (n) * 8) 178 179 #define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8) 180 #define GEN8_RPCS_ENABLE (1 << 31) 181 #define GEN8_RPCS_S_CNT_ENABLE (1 << 18) 182 #define GEN8_RPCS_S_CNT_SHIFT 15 183 #define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT) 184 #define GEN8_RPCS_SS_CNT_ENABLE (1 << 11) 185 #define GEN8_RPCS_SS_CNT_SHIFT 8 186 #define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT) 187 #define GEN8_RPCS_EU_MAX_SHIFT 4 188 #define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT) 189 #define GEN8_RPCS_EU_MIN_SHIFT 0 190 #define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT) 191 192 #define GAM_ECOCHK _MMIO(0x4090) 193 #define BDW_DISABLE_HDC_INVALIDATION (1<<25) 194 #define ECOCHK_SNB_BIT (1<<10) 195 #define ECOCHK_DIS_TLB (1<<8) 196 #define HSW_ECOCHK_ARB_PRIO_SOL (1<<6) 197 #define ECOCHK_PPGTT_CACHE64B (0x3<<3) 198 #define ECOCHK_PPGTT_CACHE4B (0x0<<3) 199 #define ECOCHK_PPGTT_GFDT_IVB (0x1<<4) 200 #define ECOCHK_PPGTT_LLC_IVB (0x1<<3) 201 #define ECOCHK_PPGTT_UC_HSW (0x1<<3) 202 #define ECOCHK_PPGTT_WT_HSW (0x2<<3) 203 #define ECOCHK_PPGTT_WB_HSW (0x3<<3) 204 205 #define GAC_ECO_BITS _MMIO(0x14090) 206 #define ECOBITS_SNB_BIT (1<<13) 207 #define ECOBITS_PPGTT_CACHE64B (3<<8) 208 #define ECOBITS_PPGTT_CACHE4B (0<<8) 209 210 #define GAB_CTL _MMIO(0x24000) 211 #define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8) 212 213 #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0) 214 #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20) 215 #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18) 216 #define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4) 217 #define GEN6_STOLEN_RESERVED_1M (0 << 4) 218 #define GEN6_STOLEN_RESERVED_512K (1 << 4) 219 #define GEN6_STOLEN_RESERVED_256K (2 << 4) 220 #define GEN6_STOLEN_RESERVED_128K (3 << 4) 221 #define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5) 222 #define GEN7_STOLEN_RESERVED_1M (0 << 5) 223 #define GEN7_STOLEN_RESERVED_256K (1 << 5) 224 #define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7) 225 #define GEN8_STOLEN_RESERVED_1M (0 << 7) 226 #define GEN8_STOLEN_RESERVED_2M (1 << 7) 227 #define GEN8_STOLEN_RESERVED_4M (2 << 7) 228 #define GEN8_STOLEN_RESERVED_8M (3 << 7) 229 230 /* VGA stuff */ 231 232 #define VGA_ST01_MDA 0x3ba 233 #define VGA_ST01_CGA 0x3da 234 235 #define _VGA_MSR_WRITE _MMIO(0x3c2) 236 #define VGA_MSR_WRITE 0x3c2 237 #define VGA_MSR_READ 0x3cc 238 #define VGA_MSR_MEM_EN (1<<1) 239 #define VGA_MSR_CGA_MODE (1<<0) 240 241 #define VGA_SR_INDEX 0x3c4 242 #define SR01 1 243 #define VGA_SR_DATA 0x3c5 244 245 #define VGA_AR_INDEX 0x3c0 246 #define VGA_AR_VID_EN (1<<5) 247 #define VGA_AR_DATA_WRITE 0x3c0 248 #define VGA_AR_DATA_READ 0x3c1 249 250 #define VGA_GR_INDEX 0x3ce 251 #define VGA_GR_DATA 0x3cf 252 /* GR05 */ 253 #define VGA_GR_MEM_READ_MODE_SHIFT 3 254 #define VGA_GR_MEM_READ_MODE_PLANE 1 255 /* GR06 */ 256 #define VGA_GR_MEM_MODE_MASK 0xc 257 #define VGA_GR_MEM_MODE_SHIFT 2 258 #define VGA_GR_MEM_A0000_AFFFF 0 259 #define VGA_GR_MEM_A0000_BFFFF 1 260 #define VGA_GR_MEM_B0000_B7FFF 2 261 #define VGA_GR_MEM_B0000_BFFFF 3 262 263 #define VGA_DACMASK 0x3c6 264 #define VGA_DACRX 0x3c7 265 #define VGA_DACWX 0x3c8 266 #define VGA_DACDATA 0x3c9 267 268 #define VGA_CR_INDEX_MDA 0x3b4 269 #define VGA_CR_DATA_MDA 0x3b5 270 #define VGA_CR_INDEX_CGA 0x3d4 271 #define VGA_CR_DATA_CGA 0x3d5 272 273 /* 274 * Instruction field definitions used by the command parser 275 */ 276 #define INSTR_CLIENT_SHIFT 29 277 #define INSTR_CLIENT_MASK 0xE0000000 278 #define INSTR_MI_CLIENT 0x0 279 #define INSTR_BC_CLIENT 0x2 280 #define INSTR_RC_CLIENT 0x3 281 #define INSTR_SUBCLIENT_SHIFT 27 282 #define INSTR_SUBCLIENT_MASK 0x18000000 283 #define INSTR_MEDIA_SUBCLIENT 0x2 284 #define INSTR_26_TO_24_MASK 0x7000000 285 #define INSTR_26_TO_24_SHIFT 24 286 287 /* 288 * Memory interface instructions used by the kernel 289 */ 290 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) 291 /* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */ 292 #define MI_GLOBAL_GTT (1<<22) 293 294 #define MI_NOOP MI_INSTR(0, 0) 295 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0) 296 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) 297 #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) 298 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) 299 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) 300 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) 301 #define MI_FLUSH MI_INSTR(0x04, 0) 302 #define MI_READ_FLUSH (1 << 0) 303 #define MI_EXE_FLUSH (1 << 1) 304 #define MI_NO_WRITE_FLUSH (1 << 2) 305 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ 306 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ 307 #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ 308 #define MI_REPORT_HEAD MI_INSTR(0x07, 0) 309 #define MI_ARB_ON_OFF MI_INSTR(0x08, 0) 310 #define MI_ARB_ENABLE (1<<0) 311 #define MI_ARB_DISABLE (0<<0) 312 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) 313 #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0) 314 #define MI_SUSPEND_FLUSH_EN (1<<0) 315 #define MI_SET_APPID MI_INSTR(0x0e, 0) 316 #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0) 317 #define MI_OVERLAY_CONTINUE (0x0<<21) 318 #define MI_OVERLAY_ON (0x1<<21) 319 #define MI_OVERLAY_OFF (0x2<<21) 320 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) 321 #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) 322 #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) 323 #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) 324 /* IVB has funny definitions for which plane to flip. */ 325 #define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19) 326 #define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19) 327 #define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19) 328 #define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19) 329 #define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19) 330 #define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19) 331 /* SKL ones */ 332 #define MI_DISPLAY_FLIP_SKL_PLANE_1_A (0 << 8) 333 #define MI_DISPLAY_FLIP_SKL_PLANE_1_B (1 << 8) 334 #define MI_DISPLAY_FLIP_SKL_PLANE_1_C (2 << 8) 335 #define MI_DISPLAY_FLIP_SKL_PLANE_2_A (4 << 8) 336 #define MI_DISPLAY_FLIP_SKL_PLANE_2_B (5 << 8) 337 #define MI_DISPLAY_FLIP_SKL_PLANE_2_C (6 << 8) 338 #define MI_DISPLAY_FLIP_SKL_PLANE_3_A (7 << 8) 339 #define MI_DISPLAY_FLIP_SKL_PLANE_3_B (8 << 8) 340 #define MI_DISPLAY_FLIP_SKL_PLANE_3_C (9 << 8) 341 #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */ 342 #define MI_SEMAPHORE_GLOBAL_GTT (1<<22) 343 #define MI_SEMAPHORE_UPDATE (1<<21) 344 #define MI_SEMAPHORE_COMPARE (1<<20) 345 #define MI_SEMAPHORE_REGISTER (1<<18) 346 #define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */ 347 #define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */ 348 #define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */ 349 #define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */ 350 #define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */ 351 #define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */ 352 #define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */ 353 #define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */ 354 #define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */ 355 #define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */ 356 #define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */ 357 #define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */ 358 #define MI_SEMAPHORE_SYNC_INVALID (3<<16) 359 #define MI_SEMAPHORE_SYNC_MASK (3<<16) 360 #define MI_SET_CONTEXT MI_INSTR(0x18, 0) 361 #define MI_MM_SPACE_GTT (1<<8) 362 #define MI_MM_SPACE_PHYSICAL (0<<8) 363 #define MI_SAVE_EXT_STATE_EN (1<<3) 364 #define MI_RESTORE_EXT_STATE_EN (1<<2) 365 #define MI_FORCE_RESTORE (1<<1) 366 #define MI_RESTORE_INHIBIT (1<<0) 367 #define HSW_MI_RS_SAVE_STATE_EN (1<<3) 368 #define HSW_MI_RS_RESTORE_STATE_EN (1<<2) 369 #define MI_SEMAPHORE_SIGNAL MI_INSTR(0x1b, 0) /* GEN8+ */ 370 #define MI_SEMAPHORE_TARGET(engine) ((engine)<<15) 371 #define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */ 372 #define MI_SEMAPHORE_POLL (1<<15) 373 #define MI_SEMAPHORE_SAD_GTE_SDD (1<<12) 374 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) 375 #define MI_STORE_DWORD_IMM_GEN4 MI_INSTR(0x20, 2) 376 #define MI_MEM_VIRTUAL (1 << 22) /* 945,g33,965 */ 377 #define MI_USE_GGTT (1 << 22) /* g4x+ */ 378 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) 379 #define MI_STORE_DWORD_INDEX_SHIFT 2 380 /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM: 381 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw 382 * simply ignores the register load under certain conditions. 383 * - One can actually load arbitrary many arbitrary registers: Simply issue x 384 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold! 385 */ 386 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1) 387 #define MI_LRI_FORCE_POSTED (1<<12) 388 #define MI_STORE_REGISTER_MEM MI_INSTR(0x24, 1) 389 #define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2) 390 #define MI_SRM_LRM_GLOBAL_GTT (1<<22) 391 #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ 392 #define MI_FLUSH_DW_STORE_INDEX (1<<21) 393 #define MI_INVALIDATE_TLB (1<<18) 394 #define MI_FLUSH_DW_OP_STOREDW (1<<14) 395 #define MI_FLUSH_DW_OP_MASK (3<<14) 396 #define MI_FLUSH_DW_NOTIFY (1<<8) 397 #define MI_INVALIDATE_BSD (1<<7) 398 #define MI_FLUSH_DW_USE_GTT (1<<2) 399 #define MI_FLUSH_DW_USE_PPGTT (0<<2) 400 #define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 1) 401 #define MI_LOAD_REGISTER_MEM_GEN8 MI_INSTR(0x29, 2) 402 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) 403 #define MI_BATCH_NON_SECURE (1) 404 /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */ 405 #define MI_BATCH_NON_SECURE_I965 (1<<8) 406 #define MI_BATCH_PPGTT_HSW (1<<8) 407 #define MI_BATCH_NON_SECURE_HSW (1<<13) 408 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) 409 #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */ 410 #define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1) 411 #define MI_BATCH_RESOURCE_STREAMER (1<<10) 412 413 #define MI_PREDICATE_SRC0 _MMIO(0x2400) 414 #define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4) 415 #define MI_PREDICATE_SRC1 _MMIO(0x2408) 416 #define MI_PREDICATE_SRC1_UDW _MMIO(0x2408 + 4) 417 418 #define MI_PREDICATE_RESULT_2 _MMIO(0x2214) 419 #define LOWER_SLICE_ENABLED (1<<0) 420 #define LOWER_SLICE_DISABLED (0<<0) 421 422 /* 423 * 3D instructions used by the kernel 424 */ 425 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) 426 427 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) 428 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 429 #define SC_UPDATE_SCISSOR (0x1<<1) 430 #define SC_ENABLE_MASK (0x1<<0) 431 #define SC_ENABLE (0x1<<0) 432 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) 433 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) 434 #define SCI_YMIN_MASK (0xffff<<16) 435 #define SCI_XMIN_MASK (0xffff<<0) 436 #define SCI_YMAX_MASK (0xffff<<16) 437 #define SCI_XMAX_MASK (0xffff<<0) 438 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 439 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) 440 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) 441 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) 442 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) 443 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) 444 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) 445 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) 446 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) 447 448 #define COLOR_BLT_CMD (2<<29 | 0x40<<22 | (5-2)) 449 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) 450 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) 451 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) 452 #define BLT_WRITE_A (2<<20) 453 #define BLT_WRITE_RGB (1<<20) 454 #define BLT_WRITE_RGBA (BLT_WRITE_RGB | BLT_WRITE_A) 455 #define BLT_DEPTH_8 (0<<24) 456 #define BLT_DEPTH_16_565 (1<<24) 457 #define BLT_DEPTH_16_1555 (2<<24) 458 #define BLT_DEPTH_32 (3<<24) 459 #define BLT_ROP_SRC_COPY (0xcc<<16) 460 #define BLT_ROP_COLOR_COPY (0xf0<<16) 461 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ 462 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ 463 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) 464 #define ASYNC_FLIP (1<<22) 465 #define DISPLAY_PLANE_A (0<<20) 466 #define DISPLAY_PLANE_B (1<<20) 467 #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2)) 468 #define PIPE_CONTROL_FLUSH_L3 (1<<27) 469 #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */ 470 #define PIPE_CONTROL_MMIO_WRITE (1<<23) 471 #define PIPE_CONTROL_STORE_DATA_INDEX (1<<21) 472 #define PIPE_CONTROL_CS_STALL (1<<20) 473 #define PIPE_CONTROL_TLB_INVALIDATE (1<<18) 474 #define PIPE_CONTROL_MEDIA_STATE_CLEAR (1<<16) 475 #define PIPE_CONTROL_QW_WRITE (1<<14) 476 #define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14) 477 #define PIPE_CONTROL_DEPTH_STALL (1<<13) 478 #define PIPE_CONTROL_WRITE_FLUSH (1<<12) 479 #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */ 480 #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */ 481 #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */ 482 #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) 483 #define PIPE_CONTROL_NOTIFY (1<<8) 484 #define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */ 485 #define PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5) 486 #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4) 487 #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) 488 #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) 489 #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1) 490 #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) 491 #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ 492 493 /* 494 * Commands used only by the command parser 495 */ 496 #define MI_SET_PREDICATE MI_INSTR(0x01, 0) 497 #define MI_ARB_CHECK MI_INSTR(0x05, 0) 498 #define MI_RS_CONTROL MI_INSTR(0x06, 0) 499 #define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0) 500 #define MI_PREDICATE MI_INSTR(0x0C, 0) 501 #define MI_RS_CONTEXT MI_INSTR(0x0F, 0) 502 #define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0) 503 #define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0) 504 #define MI_URB_CLEAR MI_INSTR(0x19, 0) 505 #define MI_UPDATE_GTT MI_INSTR(0x23, 0) 506 #define MI_CLFLUSH MI_INSTR(0x27, 0) 507 #define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0) 508 #define MI_REPORT_PERF_COUNT_GGTT (1<<0) 509 #define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0) 510 #define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0) 511 #define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0) 512 #define MI_STORE_URB_MEM MI_INSTR(0x2D, 0) 513 #define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0) 514 515 #define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16)) 516 #define GFX_OP_3DSTATE_VF_STATISTICS ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16)) 517 #define MEDIA_VFE_STATE ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16)) 518 #define MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18) 519 #define GPGPU_OBJECT ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16)) 520 #define GPGPU_WALKER ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16)) 521 #define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \ 522 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16)) 523 #define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \ 524 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16)) 525 #define GFX_OP_3DSTATE_SO_DECL_LIST \ 526 ((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16)) 527 528 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \ 529 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16)) 530 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \ 531 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16)) 532 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \ 533 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16)) 534 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \ 535 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16)) 536 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \ 537 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16)) 538 539 #define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16)) 540 541 #define COLOR_BLT ((0x2<<29)|(0x40<<22)) 542 #define SRC_COPY_BLT ((0x2<<29)|(0x43<<22)) 543 544 /* 545 * Registers used only by the command parser 546 */ 547 #define BCS_SWCTRL _MMIO(0x22200) 548 549 #define GPGPU_THREADS_DISPATCHED _MMIO(0x2290) 550 #define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4) 551 #define HS_INVOCATION_COUNT _MMIO(0x2300) 552 #define HS_INVOCATION_COUNT_UDW _MMIO(0x2300 + 4) 553 #define DS_INVOCATION_COUNT _MMIO(0x2308) 554 #define DS_INVOCATION_COUNT_UDW _MMIO(0x2308 + 4) 555 #define IA_VERTICES_COUNT _MMIO(0x2310) 556 #define IA_VERTICES_COUNT_UDW _MMIO(0x2310 + 4) 557 #define IA_PRIMITIVES_COUNT _MMIO(0x2318) 558 #define IA_PRIMITIVES_COUNT_UDW _MMIO(0x2318 + 4) 559 #define VS_INVOCATION_COUNT _MMIO(0x2320) 560 #define VS_INVOCATION_COUNT_UDW _MMIO(0x2320 + 4) 561 #define GS_INVOCATION_COUNT _MMIO(0x2328) 562 #define GS_INVOCATION_COUNT_UDW _MMIO(0x2328 + 4) 563 #define GS_PRIMITIVES_COUNT _MMIO(0x2330) 564 #define GS_PRIMITIVES_COUNT_UDW _MMIO(0x2330 + 4) 565 #define CL_INVOCATION_COUNT _MMIO(0x2338) 566 #define CL_INVOCATION_COUNT_UDW _MMIO(0x2338 + 4) 567 #define CL_PRIMITIVES_COUNT _MMIO(0x2340) 568 #define CL_PRIMITIVES_COUNT_UDW _MMIO(0x2340 + 4) 569 #define PS_INVOCATION_COUNT _MMIO(0x2348) 570 #define PS_INVOCATION_COUNT_UDW _MMIO(0x2348 + 4) 571 #define PS_DEPTH_COUNT _MMIO(0x2350) 572 #define PS_DEPTH_COUNT_UDW _MMIO(0x2350 + 4) 573 574 /* There are the 4 64-bit counter registers, one for each stream output */ 575 #define GEN7_SO_NUM_PRIMS_WRITTEN(n) _MMIO(0x5200 + (n) * 8) 576 #define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n) _MMIO(0x5200 + (n) * 8 + 4) 577 578 #define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8) 579 #define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4) 580 581 #define GEN7_3DPRIM_END_OFFSET _MMIO(0x2420) 582 #define GEN7_3DPRIM_START_VERTEX _MMIO(0x2430) 583 #define GEN7_3DPRIM_VERTEX_COUNT _MMIO(0x2434) 584 #define GEN7_3DPRIM_INSTANCE_COUNT _MMIO(0x2438) 585 #define GEN7_3DPRIM_START_INSTANCE _MMIO(0x243C) 586 #define GEN7_3DPRIM_BASE_VERTEX _MMIO(0x2440) 587 588 #define GEN7_GPGPU_DISPATCHDIMX _MMIO(0x2500) 589 #define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504) 590 #define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508) 591 592 /* There are the 16 64-bit CS General Purpose Registers */ 593 #define HSW_CS_GPR(n) _MMIO(0x2600 + (n) * 8) 594 #define HSW_CS_GPR_UDW(n) _MMIO(0x2600 + (n) * 8 + 4) 595 596 #define OACONTROL _MMIO(0x2360) 597 598 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 599 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068 600 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL) 601 602 /* 603 * Reset registers 604 */ 605 #define DEBUG_RESET_I830 _MMIO(0x6070) 606 #define DEBUG_RESET_FULL (1<<7) 607 #define DEBUG_RESET_RENDER (1<<8) 608 #define DEBUG_RESET_DISPLAY (1<<9) 609 610 /* 611 * IOSF sideband 612 */ 613 #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100) 614 #define IOSF_DEVFN_SHIFT 24 615 #define IOSF_OPCODE_SHIFT 16 616 #define IOSF_PORT_SHIFT 8 617 #define IOSF_BYTE_ENABLES_SHIFT 4 618 #define IOSF_BAR_SHIFT 1 619 #define IOSF_SB_BUSY (1<<0) 620 #define IOSF_PORT_BUNIT 0x03 621 #define IOSF_PORT_PUNIT 0x04 622 #define IOSF_PORT_NC 0x11 623 #define IOSF_PORT_DPIO 0x12 624 #define IOSF_PORT_GPIO_NC 0x13 625 #define IOSF_PORT_CCK 0x14 626 #define IOSF_PORT_DPIO_2 0x1a 627 #define IOSF_PORT_FLISDSI 0x1b 628 #define IOSF_PORT_GPIO_SC 0x48 629 #define IOSF_PORT_GPIO_SUS 0xa8 630 #define IOSF_PORT_CCU 0xa9 631 #define CHV_IOSF_PORT_GPIO_N 0x13 632 #define CHV_IOSF_PORT_GPIO_SE 0x48 633 #define CHV_IOSF_PORT_GPIO_E 0xa8 634 #define CHV_IOSF_PORT_GPIO_SW 0xb2 635 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104) 636 #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108) 637 638 /* See configdb bunit SB addr map */ 639 #define BUNIT_REG_BISOC 0x11 640 641 #define PUNIT_REG_DSPFREQ 0x36 642 #define DSPFREQSTAT_SHIFT_CHV 24 643 #define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV) 644 #define DSPFREQGUAR_SHIFT_CHV 8 645 #define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV) 646 #define DSPFREQSTAT_SHIFT 30 647 #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT) 648 #define DSPFREQGUAR_SHIFT 14 649 #define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT) 650 #define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */ 651 #define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */ 652 #define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */ 653 #define _DP_SSC(val, pipe) ((val) << (2 * (pipe))) 654 #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe)) 655 #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe)) 656 #define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe)) 657 #define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe)) 658 #define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe)) 659 #define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16)) 660 #define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe)) 661 #define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe)) 662 #define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe)) 663 #define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe)) 664 #define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe)) 665 666 /* See the PUNIT HAS v0.8 for the below bits */ 667 enum punit_power_well { 668 /* These numbers are fixed and must match the position of the pw bits */ 669 PUNIT_POWER_WELL_RENDER = 0, 670 PUNIT_POWER_WELL_MEDIA = 1, 671 PUNIT_POWER_WELL_DISP2D = 3, 672 PUNIT_POWER_WELL_DPIO_CMN_BC = 5, 673 PUNIT_POWER_WELL_DPIO_TX_B_LANES_01 = 6, 674 PUNIT_POWER_WELL_DPIO_TX_B_LANES_23 = 7, 675 PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8, 676 PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9, 677 PUNIT_POWER_WELL_DPIO_RX0 = 10, 678 PUNIT_POWER_WELL_DPIO_RX1 = 11, 679 PUNIT_POWER_WELL_DPIO_CMN_D = 12, 680 681 /* Not actual bit groups. Used as IDs for lookup_power_well() */ 682 PUNIT_POWER_WELL_ALWAYS_ON, 683 }; 684 685 enum skl_disp_power_wells { 686 /* These numbers are fixed and must match the position of the pw bits */ 687 SKL_DISP_PW_MISC_IO, 688 SKL_DISP_PW_DDI_A_E, 689 SKL_DISP_PW_DDI_B, 690 SKL_DISP_PW_DDI_C, 691 SKL_DISP_PW_DDI_D, 692 SKL_DISP_PW_1 = 14, 693 SKL_DISP_PW_2, 694 695 /* Not actual bit groups. Used as IDs for lookup_power_well() */ 696 SKL_DISP_PW_ALWAYS_ON, 697 SKL_DISP_PW_DC_OFF, 698 }; 699 700 #define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2)) 701 #define SKL_POWER_WELL_REQ(pw) (1 << (((pw) * 2) + 1)) 702 703 #define PUNIT_REG_PWRGT_CTRL 0x60 704 #define PUNIT_REG_PWRGT_STATUS 0x61 705 #define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2)) 706 #define PUNIT_PWRGT_PWR_ON(power_well) (0 << ((power_well) * 2)) 707 #define PUNIT_PWRGT_CLK_GATE(power_well) (1 << ((power_well) * 2)) 708 #define PUNIT_PWRGT_RESET(power_well) (2 << ((power_well) * 2)) 709 #define PUNIT_PWRGT_PWR_GATE(power_well) (3 << ((power_well) * 2)) 710 711 #define PUNIT_REG_GPU_LFM 0xd3 712 #define PUNIT_REG_GPU_FREQ_REQ 0xd4 713 #define PUNIT_REG_GPU_FREQ_STS 0xd8 714 #define GPLLENABLE (1<<4) 715 #define GENFREQSTATUS (1<<0) 716 #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc 717 #define PUNIT_REG_CZ_TIMESTAMP 0xce 718 719 #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */ 720 #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */ 721 722 #define FB_GFX_FMAX_AT_VMAX_FUSE 0x136 723 #define FB_GFX_FREQ_FUSE_MASK 0xff 724 #define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24 725 #define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16 726 #define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8 727 728 #define FB_GFX_FMIN_AT_VMIN_FUSE 0x137 729 #define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8 730 731 #define PUNIT_REG_DDR_SETUP2 0x139 732 #define FORCE_DDR_FREQ_REQ_ACK (1 << 8) 733 #define FORCE_DDR_LOW_FREQ (1 << 1) 734 #define FORCE_DDR_HIGH_FREQ (1 << 0) 735 736 #define PUNIT_GPU_STATUS_REG 0xdb 737 #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16 738 #define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff 739 #define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8 740 #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff 741 742 #define PUNIT_GPU_DUTYCYCLE_REG 0xdf 743 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8 744 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff 745 746 #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c 747 #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3 748 #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8 749 #define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11 750 #define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800 751 #define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34 752 #define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007 753 #define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30 754 #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27 755 #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 756 757 #define VLV_TURBO_SOC_OVERRIDE 0x04 758 #define VLV_OVERRIDE_EN 1 759 #define VLV_SOC_TDP_EN (1 << 1) 760 #define VLV_BIAS_CPU_125_SOC_875 (6 << 2) 761 #define CHV_BIAS_CPU_50_SOC_50 (3 << 2) 762 763 #define VLV_CZ_CLOCK_TO_MILLI_SEC 100000 764 765 /* vlv2 north clock has */ 766 #define CCK_FUSE_REG 0x8 767 #define CCK_FUSE_HPLL_FREQ_MASK 0x3 768 #define CCK_REG_DSI_PLL_FUSE 0x44 769 #define CCK_REG_DSI_PLL_CONTROL 0x48 770 #define DSI_PLL_VCO_EN (1 << 31) 771 #define DSI_PLL_LDO_GATE (1 << 30) 772 #define DSI_PLL_P1_POST_DIV_SHIFT 17 773 #define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17) 774 #define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13) 775 #define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12) 776 #define DSI_PLL_MUX_MASK (3 << 9) 777 #define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10) 778 #define DSI_PLL_MUX_DSI0_CCK (1 << 10) 779 #define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9) 780 #define DSI_PLL_MUX_DSI1_CCK (1 << 9) 781 #define DSI_PLL_CLK_GATE_MASK (0xf << 5) 782 #define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8) 783 #define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7) 784 #define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6) 785 #define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5) 786 #define DSI_PLL_LOCK (1 << 0) 787 #define CCK_REG_DSI_PLL_DIVIDER 0x4c 788 #define DSI_PLL_LFSR (1 << 31) 789 #define DSI_PLL_FRACTION_EN (1 << 30) 790 #define DSI_PLL_FRAC_COUNTER_SHIFT 27 791 #define DSI_PLL_FRAC_COUNTER_MASK (7 << 27) 792 #define DSI_PLL_USYNC_CNT_SHIFT 18 793 #define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18) 794 #define DSI_PLL_N1_DIV_SHIFT 16 795 #define DSI_PLL_N1_DIV_MASK (3 << 16) 796 #define DSI_PLL_M1_DIV_SHIFT 0 797 #define DSI_PLL_M1_DIV_MASK (0x1ff << 0) 798 #define CCK_CZ_CLOCK_CONTROL 0x62 799 #define CCK_GPLL_CLOCK_CONTROL 0x67 800 #define CCK_DISPLAY_CLOCK_CONTROL 0x6b 801 #define CCK_DISPLAY_REF_CLOCK_CONTROL 0x6c 802 #define CCK_TRUNK_FORCE_ON (1 << 17) 803 #define CCK_TRUNK_FORCE_OFF (1 << 16) 804 #define CCK_FREQUENCY_STATUS (0x1f << 8) 805 #define CCK_FREQUENCY_STATUS_SHIFT 8 806 #define CCK_FREQUENCY_VALUES (0x1f << 0) 807 808 /** 809 * DOC: DPIO 810 * 811 * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI 812 * ports. DPIO is the name given to such a display PHY. These PHYs 813 * don't follow the standard programming model using direct MMIO 814 * registers, and instead their registers must be accessed trough IOSF 815 * sideband. VLV has one such PHY for driving ports B and C, and CHV 816 * adds another PHY for driving port D. Each PHY responds to specific 817 * IOSF-SB port. 818 * 819 * Each display PHY is made up of one or two channels. Each channel 820 * houses a common lane part which contains the PLL and other common 821 * logic. CH0 common lane also contains the IOSF-SB logic for the 822 * Common Register Interface (CRI) ie. the DPIO registers. CRI clock 823 * must be running when any DPIO registers are accessed. 824 * 825 * In addition to having their own registers, the PHYs are also 826 * controlled through some dedicated signals from the display 827 * controller. These include PLL reference clock enable, PLL enable, 828 * and CRI clock selection, for example. 829 * 830 * Eeach channel also has two splines (also called data lanes), and 831 * each spline is made up of one Physical Access Coding Sub-Layer 832 * (PCS) block and two TX lanes. So each channel has two PCS blocks 833 * and four TX lanes. The TX lanes are used as DP lanes or TMDS 834 * data/clock pairs depending on the output type. 835 * 836 * Additionally the PHY also contains an AUX lane with AUX blocks 837 * for each channel. This is used for DP AUX communication, but 838 * this fact isn't really relevant for the driver since AUX is 839 * controlled from the display controller side. No DPIO registers 840 * need to be accessed during AUX communication, 841 * 842 * Generally on VLV/CHV the common lane corresponds to the pipe and 843 * the spline (PCS/TX) corresponds to the port. 844 * 845 * For dual channel PHY (VLV/CHV): 846 * 847 * pipe A == CMN/PLL/REF CH0 848 * 849 * pipe B == CMN/PLL/REF CH1 850 * 851 * port B == PCS/TX CH0 852 * 853 * port C == PCS/TX CH1 854 * 855 * This is especially important when we cross the streams 856 * ie. drive port B with pipe B, or port C with pipe A. 857 * 858 * For single channel PHY (CHV): 859 * 860 * pipe C == CMN/PLL/REF CH0 861 * 862 * port D == PCS/TX CH0 863 * 864 * On BXT the entire PHY channel corresponds to the port. That means 865 * the PLL is also now associated with the port rather than the pipe, 866 * and so the clock needs to be routed to the appropriate transcoder. 867 * Port A PLL is directly connected to transcoder EDP and port B/C 868 * PLLs can be routed to any transcoder A/B/C. 869 * 870 * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is 871 * digital port D (CHV) or port A (BXT). 872 * 873 * 874 * Dual channel PHY (VLV/CHV/BXT) 875 * --------------------------------- 876 * | CH0 | CH1 | 877 * | CMN/PLL/REF | CMN/PLL/REF | 878 * |---------------|---------------| Display PHY 879 * | PCS01 | PCS23 | PCS01 | PCS23 | 880 * |-------|-------|-------|-------| 881 * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3| 882 * --------------------------------- 883 * | DDI0 | DDI1 | DP/HDMI ports 884 * --------------------------------- 885 * 886 * Single channel PHY (CHV/BXT) 887 * ----------------- 888 * | CH0 | 889 * | CMN/PLL/REF | 890 * |---------------| Display PHY 891 * | PCS01 | PCS23 | 892 * |-------|-------| 893 * |TX0|TX1|TX2|TX3| 894 * ----------------- 895 * | DDI2 | DP/HDMI port 896 * ----------------- 897 */ 898 #define DPIO_DEVFN 0 899 900 #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110) 901 #define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */ 902 #define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */ 903 #define DPIO_SFR_BYPASS (1<<1) 904 #define DPIO_CMNRST (1<<0) 905 906 #define DPIO_PHY(pipe) ((pipe) >> 1) 907 #define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy]) 908 909 /* 910 * Per pipe/PLL DPIO regs 911 */ 912 #define _VLV_PLL_DW3_CH0 0x800c 913 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ 914 #define DPIO_POST_DIV_DAC 0 915 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ 916 #define DPIO_POST_DIV_LVDS1 2 917 #define DPIO_POST_DIV_LVDS2 3 918 #define DPIO_K_SHIFT (24) /* 4 bits */ 919 #define DPIO_P1_SHIFT (21) /* 3 bits */ 920 #define DPIO_P2_SHIFT (16) /* 5 bits */ 921 #define DPIO_N_SHIFT (12) /* 4 bits */ 922 #define DPIO_ENABLE_CALIBRATION (1<<11) 923 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */ 924 #define DPIO_M2DIV_MASK 0xff 925 #define _VLV_PLL_DW3_CH1 0x802c 926 #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1) 927 928 #define _VLV_PLL_DW5_CH0 0x8014 929 #define DPIO_REFSEL_OVERRIDE 27 930 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ 931 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ 932 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ 933 #define DPIO_PLL_REFCLK_SEL_MASK 3 934 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ 935 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ 936 #define _VLV_PLL_DW5_CH1 0x8034 937 #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1) 938 939 #define _VLV_PLL_DW7_CH0 0x801c 940 #define _VLV_PLL_DW7_CH1 0x803c 941 #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1) 942 943 #define _VLV_PLL_DW8_CH0 0x8040 944 #define _VLV_PLL_DW8_CH1 0x8060 945 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1) 946 947 #define VLV_PLL_DW9_BCAST 0xc044 948 #define _VLV_PLL_DW9_CH0 0x8044 949 #define _VLV_PLL_DW9_CH1 0x8064 950 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1) 951 952 #define _VLV_PLL_DW10_CH0 0x8048 953 #define _VLV_PLL_DW10_CH1 0x8068 954 #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1) 955 956 #define _VLV_PLL_DW11_CH0 0x804c 957 #define _VLV_PLL_DW11_CH1 0x806c 958 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1) 959 960 /* Spec for ref block start counts at DW10 */ 961 #define VLV_REF_DW13 0x80ac 962 963 #define VLV_CMN_DW0 0x8100 964 965 /* 966 * Per DDI channel DPIO regs 967 */ 968 969 #define _VLV_PCS_DW0_CH0 0x8200 970 #define _VLV_PCS_DW0_CH1 0x8400 971 #define DPIO_PCS_TX_LANE2_RESET (1<<16) 972 #define DPIO_PCS_TX_LANE1_RESET (1<<7) 973 #define DPIO_LEFT_TXFIFO_RST_MASTER2 (1<<4) 974 #define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1<<3) 975 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1) 976 977 #define _VLV_PCS01_DW0_CH0 0x200 978 #define _VLV_PCS23_DW0_CH0 0x400 979 #define _VLV_PCS01_DW0_CH1 0x2600 980 #define _VLV_PCS23_DW0_CH1 0x2800 981 #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1) 982 #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1) 983 984 #define _VLV_PCS_DW1_CH0 0x8204 985 #define _VLV_PCS_DW1_CH1 0x8404 986 #define CHV_PCS_REQ_SOFTRESET_EN (1<<23) 987 #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22) 988 #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21) 989 #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6) 990 #define DPIO_PCS_CLK_SOFT_RESET (1<<5) 991 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1) 992 993 #define _VLV_PCS01_DW1_CH0 0x204 994 #define _VLV_PCS23_DW1_CH0 0x404 995 #define _VLV_PCS01_DW1_CH1 0x2604 996 #define _VLV_PCS23_DW1_CH1 0x2804 997 #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1) 998 #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1) 999 1000 #define _VLV_PCS_DW8_CH0 0x8220 1001 #define _VLV_PCS_DW8_CH1 0x8420 1002 #define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20) 1003 #define CHV_PCS_USEDCLKCHANNEL (1 << 21) 1004 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1) 1005 1006 #define _VLV_PCS01_DW8_CH0 0x0220 1007 #define _VLV_PCS23_DW8_CH0 0x0420 1008 #define _VLV_PCS01_DW8_CH1 0x2620 1009 #define _VLV_PCS23_DW8_CH1 0x2820 1010 #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1) 1011 #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1) 1012 1013 #define _VLV_PCS_DW9_CH0 0x8224 1014 #define _VLV_PCS_DW9_CH1 0x8424 1015 #define DPIO_PCS_TX2MARGIN_MASK (0x7<<13) 1016 #define DPIO_PCS_TX2MARGIN_000 (0<<13) 1017 #define DPIO_PCS_TX2MARGIN_101 (1<<13) 1018 #define DPIO_PCS_TX1MARGIN_MASK (0x7<<10) 1019 #define DPIO_PCS_TX1MARGIN_000 (0<<10) 1020 #define DPIO_PCS_TX1MARGIN_101 (1<<10) 1021 #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1) 1022 1023 #define _VLV_PCS01_DW9_CH0 0x224 1024 #define _VLV_PCS23_DW9_CH0 0x424 1025 #define _VLV_PCS01_DW9_CH1 0x2624 1026 #define _VLV_PCS23_DW9_CH1 0x2824 1027 #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1) 1028 #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1) 1029 1030 #define _CHV_PCS_DW10_CH0 0x8228 1031 #define _CHV_PCS_DW10_CH1 0x8428 1032 #define DPIO_PCS_SWING_CALC_TX0_TX2 (1<<30) 1033 #define DPIO_PCS_SWING_CALC_TX1_TX3 (1<<31) 1034 #define DPIO_PCS_TX2DEEMP_MASK (0xf<<24) 1035 #define DPIO_PCS_TX2DEEMP_9P5 (0<<24) 1036 #define DPIO_PCS_TX2DEEMP_6P0 (2<<24) 1037 #define DPIO_PCS_TX1DEEMP_MASK (0xf<<16) 1038 #define DPIO_PCS_TX1DEEMP_9P5 (0<<16) 1039 #define DPIO_PCS_TX1DEEMP_6P0 (2<<16) 1040 #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1) 1041 1042 #define _VLV_PCS01_DW10_CH0 0x0228 1043 #define _VLV_PCS23_DW10_CH0 0x0428 1044 #define _VLV_PCS01_DW10_CH1 0x2628 1045 #define _VLV_PCS23_DW10_CH1 0x2828 1046 #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1) 1047 #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1) 1048 1049 #define _VLV_PCS_DW11_CH0 0x822c 1050 #define _VLV_PCS_DW11_CH1 0x842c 1051 #define DPIO_TX2_STAGGER_MASK(x) ((x)<<24) 1052 #define DPIO_LANEDESKEW_STRAP_OVRD (1<<3) 1053 #define DPIO_LEFT_TXFIFO_RST_MASTER (1<<1) 1054 #define DPIO_RIGHT_TXFIFO_RST_MASTER (1<<0) 1055 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1) 1056 1057 #define _VLV_PCS01_DW11_CH0 0x022c 1058 #define _VLV_PCS23_DW11_CH0 0x042c 1059 #define _VLV_PCS01_DW11_CH1 0x262c 1060 #define _VLV_PCS23_DW11_CH1 0x282c 1061 #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1) 1062 #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1) 1063 1064 #define _VLV_PCS01_DW12_CH0 0x0230 1065 #define _VLV_PCS23_DW12_CH0 0x0430 1066 #define _VLV_PCS01_DW12_CH1 0x2630 1067 #define _VLV_PCS23_DW12_CH1 0x2830 1068 #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1) 1069 #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1) 1070 1071 #define _VLV_PCS_DW12_CH0 0x8230 1072 #define _VLV_PCS_DW12_CH1 0x8430 1073 #define DPIO_TX2_STAGGER_MULT(x) ((x)<<20) 1074 #define DPIO_TX1_STAGGER_MULT(x) ((x)<<16) 1075 #define DPIO_TX1_STAGGER_MASK(x) ((x)<<8) 1076 #define DPIO_LANESTAGGER_STRAP_OVRD (1<<6) 1077 #define DPIO_LANESTAGGER_STRAP(x) ((x)<<0) 1078 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1) 1079 1080 #define _VLV_PCS_DW14_CH0 0x8238 1081 #define _VLV_PCS_DW14_CH1 0x8438 1082 #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1) 1083 1084 #define _VLV_PCS_DW23_CH0 0x825c 1085 #define _VLV_PCS_DW23_CH1 0x845c 1086 #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1) 1087 1088 #define _VLV_TX_DW2_CH0 0x8288 1089 #define _VLV_TX_DW2_CH1 0x8488 1090 #define DPIO_SWING_MARGIN000_SHIFT 16 1091 #define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT) 1092 #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8 1093 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1) 1094 1095 #define _VLV_TX_DW3_CH0 0x828c 1096 #define _VLV_TX_DW3_CH1 0x848c 1097 /* The following bit for CHV phy */ 1098 #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1<<27) 1099 #define DPIO_SWING_MARGIN101_SHIFT 16 1100 #define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT) 1101 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1) 1102 1103 #define _VLV_TX_DW4_CH0 0x8290 1104 #define _VLV_TX_DW4_CH1 0x8490 1105 #define DPIO_SWING_DEEMPH9P5_SHIFT 24 1106 #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT) 1107 #define DPIO_SWING_DEEMPH6P0_SHIFT 16 1108 #define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT) 1109 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1) 1110 1111 #define _VLV_TX3_DW4_CH0 0x690 1112 #define _VLV_TX3_DW4_CH1 0x2a90 1113 #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1) 1114 1115 #define _VLV_TX_DW5_CH0 0x8294 1116 #define _VLV_TX_DW5_CH1 0x8494 1117 #define DPIO_TX_OCALINIT_EN (1<<31) 1118 #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1) 1119 1120 #define _VLV_TX_DW11_CH0 0x82ac 1121 #define _VLV_TX_DW11_CH1 0x84ac 1122 #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1) 1123 1124 #define _VLV_TX_DW14_CH0 0x82b8 1125 #define _VLV_TX_DW14_CH1 0x84b8 1126 #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1) 1127 1128 /* CHV dpPhy registers */ 1129 #define _CHV_PLL_DW0_CH0 0x8000 1130 #define _CHV_PLL_DW0_CH1 0x8180 1131 #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1) 1132 1133 #define _CHV_PLL_DW1_CH0 0x8004 1134 #define _CHV_PLL_DW1_CH1 0x8184 1135 #define DPIO_CHV_N_DIV_SHIFT 8 1136 #define DPIO_CHV_M1_DIV_BY_2 (0 << 0) 1137 #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1) 1138 1139 #define _CHV_PLL_DW2_CH0 0x8008 1140 #define _CHV_PLL_DW2_CH1 0x8188 1141 #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1) 1142 1143 #define _CHV_PLL_DW3_CH0 0x800c 1144 #define _CHV_PLL_DW3_CH1 0x818c 1145 #define DPIO_CHV_FRAC_DIV_EN (1 << 16) 1146 #define DPIO_CHV_FIRST_MOD (0 << 8) 1147 #define DPIO_CHV_SECOND_MOD (1 << 8) 1148 #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0 1149 #define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0) 1150 #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1) 1151 1152 #define _CHV_PLL_DW6_CH0 0x8018 1153 #define _CHV_PLL_DW6_CH1 0x8198 1154 #define DPIO_CHV_GAIN_CTRL_SHIFT 16 1155 #define DPIO_CHV_INT_COEFF_SHIFT 8 1156 #define DPIO_CHV_PROP_COEFF_SHIFT 0 1157 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1) 1158 1159 #define _CHV_PLL_DW8_CH0 0x8020 1160 #define _CHV_PLL_DW8_CH1 0x81A0 1161 #define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0 1162 #define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0) 1163 #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1) 1164 1165 #define _CHV_PLL_DW9_CH0 0x8024 1166 #define _CHV_PLL_DW9_CH1 0x81A4 1167 #define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */ 1168 #define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1) 1169 #define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */ 1170 #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1) 1171 1172 #define _CHV_CMN_DW0_CH0 0x8100 1173 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19 1174 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18 1175 #define DPIO_ALLDL_POWERDOWN (1 << 1) 1176 #define DPIO_ANYDL_POWERDOWN (1 << 0) 1177 1178 #define _CHV_CMN_DW5_CH0 0x8114 1179 #define CHV_BUFRIGHTENA1_DISABLE (0 << 20) 1180 #define CHV_BUFRIGHTENA1_NORMAL (1 << 20) 1181 #define CHV_BUFRIGHTENA1_FORCE (3 << 20) 1182 #define CHV_BUFRIGHTENA1_MASK (3 << 20) 1183 #define CHV_BUFLEFTENA1_DISABLE (0 << 22) 1184 #define CHV_BUFLEFTENA1_NORMAL (1 << 22) 1185 #define CHV_BUFLEFTENA1_FORCE (3 << 22) 1186 #define CHV_BUFLEFTENA1_MASK (3 << 22) 1187 1188 #define _CHV_CMN_DW13_CH0 0x8134 1189 #define _CHV_CMN_DW0_CH1 0x8080 1190 #define DPIO_CHV_S1_DIV_SHIFT 21 1191 #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */ 1192 #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */ 1193 #define DPIO_CHV_K_DIV_SHIFT 4 1194 #define DPIO_PLL_FREQLOCK (1 << 1) 1195 #define DPIO_PLL_LOCK (1 << 0) 1196 #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1) 1197 1198 #define _CHV_CMN_DW14_CH0 0x8138 1199 #define _CHV_CMN_DW1_CH1 0x8084 1200 #define DPIO_AFC_RECAL (1 << 14) 1201 #define DPIO_DCLKP_EN (1 << 13) 1202 #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */ 1203 #define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */ 1204 #define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */ 1205 #define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */ 1206 #define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */ 1207 #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */ 1208 #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */ 1209 #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */ 1210 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1) 1211 1212 #define _CHV_CMN_DW19_CH0 0x814c 1213 #define _CHV_CMN_DW6_CH1 0x8098 1214 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */ 1215 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */ 1216 #define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */ 1217 #define CHV_CMN_USEDCLKCHANNEL (1 << 13) 1218 1219 #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1) 1220 1221 #define CHV_CMN_DW28 0x8170 1222 #define DPIO_CL1POWERDOWNEN (1 << 23) 1223 #define DPIO_DYNPWRDOWNEN_CH0 (1 << 22) 1224 #define DPIO_SUS_CLK_CONFIG_ON (0 << 0) 1225 #define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0) 1226 #define DPIO_SUS_CLK_CONFIG_GATE (2 << 0) 1227 #define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0) 1228 1229 #define CHV_CMN_DW30 0x8178 1230 #define DPIO_CL2_LDOFUSE_PWRENB (1 << 6) 1231 #define DPIO_LRC_BYPASS (1 << 3) 1232 1233 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \ 1234 (lane) * 0x200 + (offset)) 1235 1236 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80) 1237 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84) 1238 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88) 1239 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c) 1240 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90) 1241 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94) 1242 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98) 1243 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c) 1244 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0) 1245 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4) 1246 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8) 1247 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac) 1248 #define DPIO_FRC_LATENCY_SHFIT 8 1249 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8) 1250 #define DPIO_UPAR_SHIFT 30 1251 1252 /* BXT PHY registers */ 1253 #define _BXT_PHY(phy, a, b) _MMIO_PIPE((phy), (a), (b)) 1254 1255 #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090) 1256 #define GT_DISPLAY_POWER_ON(phy) (1 << (phy)) 1257 1258 #define _PHY_CTL_FAMILY_EDP 0x64C80 1259 #define _PHY_CTL_FAMILY_DDI 0x64C90 1260 #define COMMON_RESET_DIS (1 << 31) 1261 #define BXT_PHY_CTL_FAMILY(phy) _BXT_PHY((phy), _PHY_CTL_FAMILY_DDI, \ 1262 _PHY_CTL_FAMILY_EDP) 1263 1264 /* BXT PHY PLL registers */ 1265 #define _PORT_PLL_A 0x46074 1266 #define _PORT_PLL_B 0x46078 1267 #define _PORT_PLL_C 0x4607c 1268 #define PORT_PLL_ENABLE (1 << 31) 1269 #define PORT_PLL_LOCK (1 << 30) 1270 #define PORT_PLL_REF_SEL (1 << 27) 1271 #define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B) 1272 1273 #define _PORT_PLL_EBB_0_A 0x162034 1274 #define _PORT_PLL_EBB_0_B 0x6C034 1275 #define _PORT_PLL_EBB_0_C 0x6C340 1276 #define PORT_PLL_P1_SHIFT 13 1277 #define PORT_PLL_P1_MASK (0x07 << PORT_PLL_P1_SHIFT) 1278 #define PORT_PLL_P1(x) ((x) << PORT_PLL_P1_SHIFT) 1279 #define PORT_PLL_P2_SHIFT 8 1280 #define PORT_PLL_P2_MASK (0x1f << PORT_PLL_P2_SHIFT) 1281 #define PORT_PLL_P2(x) ((x) << PORT_PLL_P2_SHIFT) 1282 #define BXT_PORT_PLL_EBB_0(port) _MMIO_PORT3(port, _PORT_PLL_EBB_0_A, \ 1283 _PORT_PLL_EBB_0_B, \ 1284 _PORT_PLL_EBB_0_C) 1285 1286 #define _PORT_PLL_EBB_4_A 0x162038 1287 #define _PORT_PLL_EBB_4_B 0x6C038 1288 #define _PORT_PLL_EBB_4_C 0x6C344 1289 #define PORT_PLL_10BIT_CLK_ENABLE (1 << 13) 1290 #define PORT_PLL_RECALIBRATE (1 << 14) 1291 #define BXT_PORT_PLL_EBB_4(port) _MMIO_PORT3(port, _PORT_PLL_EBB_4_A, \ 1292 _PORT_PLL_EBB_4_B, \ 1293 _PORT_PLL_EBB_4_C) 1294 1295 #define _PORT_PLL_0_A 0x162100 1296 #define _PORT_PLL_0_B 0x6C100 1297 #define _PORT_PLL_0_C 0x6C380 1298 /* PORT_PLL_0_A */ 1299 #define PORT_PLL_M2_MASK 0xFF 1300 /* PORT_PLL_1_A */ 1301 #define PORT_PLL_N_SHIFT 8 1302 #define PORT_PLL_N_MASK (0x0F << PORT_PLL_N_SHIFT) 1303 #define PORT_PLL_N(x) ((x) << PORT_PLL_N_SHIFT) 1304 /* PORT_PLL_2_A */ 1305 #define PORT_PLL_M2_FRAC_MASK 0x3FFFFF 1306 /* PORT_PLL_3_A */ 1307 #define PORT_PLL_M2_FRAC_ENABLE (1 << 16) 1308 /* PORT_PLL_6_A */ 1309 #define PORT_PLL_PROP_COEFF_MASK 0xF 1310 #define PORT_PLL_INT_COEFF_MASK (0x1F << 8) 1311 #define PORT_PLL_INT_COEFF(x) ((x) << 8) 1312 #define PORT_PLL_GAIN_CTL_MASK (0x07 << 16) 1313 #define PORT_PLL_GAIN_CTL(x) ((x) << 16) 1314 /* PORT_PLL_8_A */ 1315 #define PORT_PLL_TARGET_CNT_MASK 0x3FF 1316 /* PORT_PLL_9_A */ 1317 #define PORT_PLL_LOCK_THRESHOLD_SHIFT 1 1318 #define PORT_PLL_LOCK_THRESHOLD_MASK (0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT) 1319 /* PORT_PLL_10_A */ 1320 #define PORT_PLL_DCO_AMP_OVR_EN_H (1<<27) 1321 #define PORT_PLL_DCO_AMP_DEFAULT 15 1322 #define PORT_PLL_DCO_AMP_MASK 0x3c00 1323 #define PORT_PLL_DCO_AMP(x) ((x)<<10) 1324 #define _PORT_PLL_BASE(port) _PORT3(port, _PORT_PLL_0_A, \ 1325 _PORT_PLL_0_B, \ 1326 _PORT_PLL_0_C) 1327 #define BXT_PORT_PLL(port, idx) _MMIO(_PORT_PLL_BASE(port) + (idx) * 4) 1328 1329 /* BXT PHY common lane registers */ 1330 #define _PORT_CL1CM_DW0_A 0x162000 1331 #define _PORT_CL1CM_DW0_BC 0x6C000 1332 #define PHY_POWER_GOOD (1 << 16) 1333 #define PHY_RESERVED (1 << 7) 1334 #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC, \ 1335 _PORT_CL1CM_DW0_A) 1336 1337 #define _PORT_CL1CM_DW9_A 0x162024 1338 #define _PORT_CL1CM_DW9_BC 0x6C024 1339 #define IREF0RC_OFFSET_SHIFT 8 1340 #define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT) 1341 #define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC, \ 1342 _PORT_CL1CM_DW9_A) 1343 1344 #define _PORT_CL1CM_DW10_A 0x162028 1345 #define _PORT_CL1CM_DW10_BC 0x6C028 1346 #define IREF1RC_OFFSET_SHIFT 8 1347 #define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT) 1348 #define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC, \ 1349 _PORT_CL1CM_DW10_A) 1350 1351 #define _PORT_CL1CM_DW28_A 0x162070 1352 #define _PORT_CL1CM_DW28_BC 0x6C070 1353 #define OCL1_POWER_DOWN_EN (1 << 23) 1354 #define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22) 1355 #define SUS_CLK_CONFIG 0x3 1356 #define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC, \ 1357 _PORT_CL1CM_DW28_A) 1358 1359 #define _PORT_CL1CM_DW30_A 0x162078 1360 #define _PORT_CL1CM_DW30_BC 0x6C078 1361 #define OCL2_LDOFUSE_PWR_DIS (1 << 6) 1362 #define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC, \ 1363 _PORT_CL1CM_DW30_A) 1364 1365 /* Defined for PHY0 only */ 1366 #define BXT_PORT_CL2CM_DW6_BC _MMIO(0x6C358) 1367 #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28) 1368 1369 /* BXT PHY Ref registers */ 1370 #define _PORT_REF_DW3_A 0x16218C 1371 #define _PORT_REF_DW3_BC 0x6C18C 1372 #define GRC_DONE (1 << 22) 1373 #define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC, \ 1374 _PORT_REF_DW3_A) 1375 1376 #define _PORT_REF_DW6_A 0x162198 1377 #define _PORT_REF_DW6_BC 0x6C198 1378 /* 1379 * FIXME: BSpec/CHV ConfigDB disagrees on the following two fields, fix them 1380 * after testing. 1381 */ 1382 #define GRC_CODE_SHIFT 23 1383 #define GRC_CODE_MASK (0x1FF << GRC_CODE_SHIFT) 1384 #define GRC_CODE_FAST_SHIFT 16 1385 #define GRC_CODE_FAST_MASK (0x7F << GRC_CODE_FAST_SHIFT) 1386 #define GRC_CODE_SLOW_SHIFT 8 1387 #define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT) 1388 #define GRC_CODE_NOM_MASK 0xFF 1389 #define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC, \ 1390 _PORT_REF_DW6_A) 1391 1392 #define _PORT_REF_DW8_A 0x1621A0 1393 #define _PORT_REF_DW8_BC 0x6C1A0 1394 #define GRC_DIS (1 << 15) 1395 #define GRC_RDY_OVRD (1 << 1) 1396 #define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC, \ 1397 _PORT_REF_DW8_A) 1398 1399 /* BXT PHY PCS registers */ 1400 #define _PORT_PCS_DW10_LN01_A 0x162428 1401 #define _PORT_PCS_DW10_LN01_B 0x6C428 1402 #define _PORT_PCS_DW10_LN01_C 0x6C828 1403 #define _PORT_PCS_DW10_GRP_A 0x162C28 1404 #define _PORT_PCS_DW10_GRP_B 0x6CC28 1405 #define _PORT_PCS_DW10_GRP_C 0x6CE28 1406 #define BXT_PORT_PCS_DW10_LN01(port) _MMIO_PORT3(port, _PORT_PCS_DW10_LN01_A, \ 1407 _PORT_PCS_DW10_LN01_B, \ 1408 _PORT_PCS_DW10_LN01_C) 1409 #define BXT_PORT_PCS_DW10_GRP(port) _MMIO_PORT3(port, _PORT_PCS_DW10_GRP_A, \ 1410 _PORT_PCS_DW10_GRP_B, \ 1411 _PORT_PCS_DW10_GRP_C) 1412 #define TX2_SWING_CALC_INIT (1 << 31) 1413 #define TX1_SWING_CALC_INIT (1 << 30) 1414 1415 #define _PORT_PCS_DW12_LN01_A 0x162430 1416 #define _PORT_PCS_DW12_LN01_B 0x6C430 1417 #define _PORT_PCS_DW12_LN01_C 0x6C830 1418 #define _PORT_PCS_DW12_LN23_A 0x162630 1419 #define _PORT_PCS_DW12_LN23_B 0x6C630 1420 #define _PORT_PCS_DW12_LN23_C 0x6CA30 1421 #define _PORT_PCS_DW12_GRP_A 0x162c30 1422 #define _PORT_PCS_DW12_GRP_B 0x6CC30 1423 #define _PORT_PCS_DW12_GRP_C 0x6CE30 1424 #define LANESTAGGER_STRAP_OVRD (1 << 6) 1425 #define LANE_STAGGER_MASK 0x1F 1426 #define BXT_PORT_PCS_DW12_LN01(port) _MMIO_PORT3(port, _PORT_PCS_DW12_LN01_A, \ 1427 _PORT_PCS_DW12_LN01_B, \ 1428 _PORT_PCS_DW12_LN01_C) 1429 #define BXT_PORT_PCS_DW12_LN23(port) _MMIO_PORT3(port, _PORT_PCS_DW12_LN23_A, \ 1430 _PORT_PCS_DW12_LN23_B, \ 1431 _PORT_PCS_DW12_LN23_C) 1432 #define BXT_PORT_PCS_DW12_GRP(port) _MMIO_PORT3(port, _PORT_PCS_DW12_GRP_A, \ 1433 _PORT_PCS_DW12_GRP_B, \ 1434 _PORT_PCS_DW12_GRP_C) 1435 1436 /* BXT PHY TX registers */ 1437 #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \ 1438 ((lane) & 1) * 0x80) 1439 1440 #define _PORT_TX_DW2_LN0_A 0x162508 1441 #define _PORT_TX_DW2_LN0_B 0x6C508 1442 #define _PORT_TX_DW2_LN0_C 0x6C908 1443 #define _PORT_TX_DW2_GRP_A 0x162D08 1444 #define _PORT_TX_DW2_GRP_B 0x6CD08 1445 #define _PORT_TX_DW2_GRP_C 0x6CF08 1446 #define BXT_PORT_TX_DW2_GRP(port) _MMIO_PORT3(port, _PORT_TX_DW2_GRP_A, \ 1447 _PORT_TX_DW2_GRP_B, \ 1448 _PORT_TX_DW2_GRP_C) 1449 #define BXT_PORT_TX_DW2_LN0(port) _MMIO_PORT3(port, _PORT_TX_DW2_LN0_A, \ 1450 _PORT_TX_DW2_LN0_B, \ 1451 _PORT_TX_DW2_LN0_C) 1452 #define MARGIN_000_SHIFT 16 1453 #define MARGIN_000 (0xFF << MARGIN_000_SHIFT) 1454 #define UNIQ_TRANS_SCALE_SHIFT 8 1455 #define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT) 1456 1457 #define _PORT_TX_DW3_LN0_A 0x16250C 1458 #define _PORT_TX_DW3_LN0_B 0x6C50C 1459 #define _PORT_TX_DW3_LN0_C 0x6C90C 1460 #define _PORT_TX_DW3_GRP_A 0x162D0C 1461 #define _PORT_TX_DW3_GRP_B 0x6CD0C 1462 #define _PORT_TX_DW3_GRP_C 0x6CF0C 1463 #define BXT_PORT_TX_DW3_GRP(port) _MMIO_PORT3(port, _PORT_TX_DW3_GRP_A, \ 1464 _PORT_TX_DW3_GRP_B, \ 1465 _PORT_TX_DW3_GRP_C) 1466 #define BXT_PORT_TX_DW3_LN0(port) _MMIO_PORT3(port, _PORT_TX_DW3_LN0_A, \ 1467 _PORT_TX_DW3_LN0_B, \ 1468 _PORT_TX_DW3_LN0_C) 1469 #define SCALE_DCOMP_METHOD (1 << 26) 1470 #define UNIQUE_TRANGE_EN_METHOD (1 << 27) 1471 1472 #define _PORT_TX_DW4_LN0_A 0x162510 1473 #define _PORT_TX_DW4_LN0_B 0x6C510 1474 #define _PORT_TX_DW4_LN0_C 0x6C910 1475 #define _PORT_TX_DW4_GRP_A 0x162D10 1476 #define _PORT_TX_DW4_GRP_B 0x6CD10 1477 #define _PORT_TX_DW4_GRP_C 0x6CF10 1478 #define BXT_PORT_TX_DW4_LN0(port) _MMIO_PORT3(port, _PORT_TX_DW4_LN0_A, \ 1479 _PORT_TX_DW4_LN0_B, \ 1480 _PORT_TX_DW4_LN0_C) 1481 #define BXT_PORT_TX_DW4_GRP(port) _MMIO_PORT3(port, _PORT_TX_DW4_GRP_A, \ 1482 _PORT_TX_DW4_GRP_B, \ 1483 _PORT_TX_DW4_GRP_C) 1484 #define DEEMPH_SHIFT 24 1485 #define DE_EMPHASIS (0xFF << DEEMPH_SHIFT) 1486 1487 #define _PORT_TX_DW14_LN0_A 0x162538 1488 #define _PORT_TX_DW14_LN0_B 0x6C538 1489 #define _PORT_TX_DW14_LN0_C 0x6C938 1490 #define LATENCY_OPTIM_SHIFT 30 1491 #define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT) 1492 #define BXT_PORT_TX_DW14_LN(port, lane) _MMIO(_PORT3((port), _PORT_TX_DW14_LN0_A, \ 1493 _PORT_TX_DW14_LN0_B, \ 1494 _PORT_TX_DW14_LN0_C) + \ 1495 _BXT_LANE_OFFSET(lane)) 1496 1497 /* UAIMI scratch pad register 1 */ 1498 #define UAIMI_SPR1 _MMIO(0x4F074) 1499 /* SKL VccIO mask */ 1500 #define SKL_VCCIO_MASK 0x1 1501 /* SKL balance leg register */ 1502 #define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C) 1503 /* I_boost values */ 1504 #define BALANCE_LEG_SHIFT(port) (8+3*(port)) 1505 #define BALANCE_LEG_MASK(port) (7<<(8+3*(port))) 1506 /* Balance leg disable bits */ 1507 #define BALANCE_LEG_DISABLE_SHIFT 23 1508 1509 /* 1510 * Fence registers 1511 * [0-7] @ 0x2000 gen2,gen3 1512 * [8-15] @ 0x3000 945,g33,pnv 1513 * 1514 * [0-15] @ 0x3000 gen4,gen5 1515 * 1516 * [0-15] @ 0x100000 gen6,vlv,chv 1517 * [0-31] @ 0x100000 gen7+ 1518 */ 1519 #define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4) 1520 #define I830_FENCE_START_MASK 0x07f80000 1521 #define I830_FENCE_TILING_Y_SHIFT 12 1522 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) 1523 #define I830_FENCE_PITCH_SHIFT 4 1524 #define I830_FENCE_REG_VALID (1<<0) 1525 #define I915_FENCE_MAX_PITCH_VAL 4 1526 #define I830_FENCE_MAX_PITCH_VAL 6 1527 #define I830_FENCE_MAX_SIZE_VAL (1<<8) 1528 1529 #define I915_FENCE_START_MASK 0x0ff00000 1530 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) 1531 1532 #define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8) 1533 #define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4) 1534 #define I965_FENCE_PITCH_SHIFT 2 1535 #define I965_FENCE_TILING_Y_SHIFT 1 1536 #define I965_FENCE_REG_VALID (1<<0) 1537 #define I965_FENCE_MAX_PITCH_VAL 0x0400 1538 1539 #define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8) 1540 #define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4) 1541 #define GEN6_FENCE_PITCH_SHIFT 32 1542 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800 1543 1544 1545 /* control register for cpu gtt access */ 1546 #define TILECTL _MMIO(0x101000) 1547 #define TILECTL_SWZCTL (1 << 0) 1548 #define TILECTL_TLBPF (1 << 1) 1549 #define TILECTL_TLB_PREFETCH_DIS (1 << 2) 1550 #define TILECTL_BACKSNOOP_DIS (1 << 3) 1551 1552 /* 1553 * Instruction and interrupt control regs 1554 */ 1555 #define PGTBL_CTL _MMIO(0x02020) 1556 #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */ 1557 #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */ 1558 #define PGTBL_ER _MMIO(0x02024) 1559 #define PRB0_BASE (0x2030-0x30) 1560 #define PRB1_BASE (0x2040-0x30) /* 830,gen3 */ 1561 #define PRB2_BASE (0x2050-0x30) /* gen3 */ 1562 #define SRB0_BASE (0x2100-0x30) /* gen2 */ 1563 #define SRB1_BASE (0x2110-0x30) /* gen2 */ 1564 #define SRB2_BASE (0x2120-0x30) /* 830 */ 1565 #define SRB3_BASE (0x2130-0x30) /* 830 */ 1566 #define RENDER_RING_BASE 0x02000 1567 #define BSD_RING_BASE 0x04000 1568 #define GEN6_BSD_RING_BASE 0x12000 1569 #define GEN8_BSD2_RING_BASE 0x1c000 1570 #define VEBOX_RING_BASE 0x1a000 1571 #define BLT_RING_BASE 0x22000 1572 #define RING_TAIL(base) _MMIO((base)+0x30) 1573 #define RING_HEAD(base) _MMIO((base)+0x34) 1574 #define RING_START(base) _MMIO((base)+0x38) 1575 #define RING_CTL(base) _MMIO((base)+0x3c) 1576 #define RING_SYNC_0(base) _MMIO((base)+0x40) 1577 #define RING_SYNC_1(base) _MMIO((base)+0x44) 1578 #define RING_SYNC_2(base) _MMIO((base)+0x48) 1579 #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE)) 1580 #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE)) 1581 #define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE)) 1582 #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE)) 1583 #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE)) 1584 #define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE)) 1585 #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE)) 1586 #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE)) 1587 #define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE)) 1588 #define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE)) 1589 #define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE)) 1590 #define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE)) 1591 #define GEN6_NOSYNC INVALID_MMIO_REG 1592 #define RING_PSMI_CTL(base) _MMIO((base)+0x50) 1593 #define RING_MAX_IDLE(base) _MMIO((base)+0x54) 1594 #define RING_HWS_PGA(base) _MMIO((base)+0x80) 1595 #define RING_HWS_PGA_GEN6(base) _MMIO((base)+0x2080) 1596 #define RING_RESET_CTL(base) _MMIO((base)+0xd0) 1597 #define RESET_CTL_REQUEST_RESET (1 << 0) 1598 #define RESET_CTL_READY_TO_RESET (1 << 1) 1599 1600 #define HSW_GTT_CACHE_EN _MMIO(0x4024) 1601 #define GTT_CACHE_EN_ALL 0xF0007FFF 1602 #define GEN7_WR_WATERMARK _MMIO(0x4028) 1603 #define GEN7_GFX_PRIO_CTRL _MMIO(0x402C) 1604 #define ARB_MODE _MMIO(0x4030) 1605 #define ARB_MODE_SWIZZLE_SNB (1<<4) 1606 #define ARB_MODE_SWIZZLE_IVB (1<<5) 1607 #define GEN7_GFX_PEND_TLB0 _MMIO(0x4034) 1608 #define GEN7_GFX_PEND_TLB1 _MMIO(0x4038) 1609 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */ 1610 #define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4) 1611 #define GEN7_LRA_LIMITS_REG_NUM 13 1612 #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070) 1613 #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074) 1614 1615 #define GAMTARBMODE _MMIO(0x04a08) 1616 #define ARB_MODE_BWGTLB_DISABLE (1<<9) 1617 #define ARB_MODE_SWIZZLE_BDW (1<<1) 1618 #define RENDER_HWS_PGA_GEN7 _MMIO(0x04080) 1619 #define RING_FAULT_REG(ring) _MMIO(0x4094 + 0x100*(ring)->id) 1620 #define RING_FAULT_GTTSEL_MASK (1<<11) 1621 #define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff) 1622 #define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3) 1623 #define RING_FAULT_VALID (1<<0) 1624 #define DONE_REG _MMIO(0x40b0) 1625 #define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0) 1626 #define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4) 1627 #define BSD_HWS_PGA_GEN7 _MMIO(0x04180) 1628 #define BLT_HWS_PGA_GEN7 _MMIO(0x04280) 1629 #define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380) 1630 #define RING_ACTHD(base) _MMIO((base)+0x74) 1631 #define RING_ACTHD_UDW(base) _MMIO((base)+0x5c) 1632 #define RING_NOPID(base) _MMIO((base)+0x94) 1633 #define RING_IMR(base) _MMIO((base)+0xa8) 1634 #define RING_HWSTAM(base) _MMIO((base)+0x98) 1635 #define RING_TIMESTAMP(base) _MMIO((base)+0x358) 1636 #define RING_TIMESTAMP_UDW(base) _MMIO((base)+0x358 + 4) 1637 #define TAIL_ADDR 0x001FFFF8 1638 #define HEAD_WRAP_COUNT 0xFFE00000 1639 #define HEAD_WRAP_ONE 0x00200000 1640 #define HEAD_ADDR 0x001FFFFC 1641 #define RING_NR_PAGES 0x001FF000 1642 #define RING_REPORT_MASK 0x00000006 1643 #define RING_REPORT_64K 0x00000002 1644 #define RING_REPORT_128K 0x00000004 1645 #define RING_NO_REPORT 0x00000000 1646 #define RING_VALID_MASK 0x00000001 1647 #define RING_VALID 0x00000001 1648 #define RING_INVALID 0x00000000 1649 #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */ 1650 #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */ 1651 #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */ 1652 1653 #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base)+0x4D0) + (i)*4) 1654 #define RING_MAX_NONPRIV_SLOTS 12 1655 1656 #define GEN7_TLB_RD_ADDR _MMIO(0x4700) 1657 1658 #if 0 1659 #define PRB0_TAIL _MMIO(0x2030) 1660 #define PRB0_HEAD _MMIO(0x2034) 1661 #define PRB0_START _MMIO(0x2038) 1662 #define PRB0_CTL _MMIO(0x203c) 1663 #define PRB1_TAIL _MMIO(0x2040) /* 915+ only */ 1664 #define PRB1_HEAD _MMIO(0x2044) /* 915+ only */ 1665 #define PRB1_START _MMIO(0x2048) /* 915+ only */ 1666 #define PRB1_CTL _MMIO(0x204c) /* 915+ only */ 1667 #endif 1668 #define IPEIR_I965 _MMIO(0x2064) 1669 #define IPEHR_I965 _MMIO(0x2068) 1670 #define GEN7_SC_INSTDONE _MMIO(0x7100) 1671 #define GEN7_SAMPLER_INSTDONE _MMIO(0xe160) 1672 #define GEN7_ROW_INSTDONE _MMIO(0xe164) 1673 #define I915_NUM_INSTDONE_REG 4 1674 #define RING_IPEIR(base) _MMIO((base)+0x64) 1675 #define RING_IPEHR(base) _MMIO((base)+0x68) 1676 /* 1677 * On GEN4, only the render ring INSTDONE exists and has a different 1678 * layout than the GEN7+ version. 1679 * The GEN2 counterpart of this register is GEN2_INSTDONE. 1680 */ 1681 #define RING_INSTDONE(base) _MMIO((base)+0x6c) 1682 #define RING_INSTPS(base) _MMIO((base)+0x70) 1683 #define RING_DMA_FADD(base) _MMIO((base)+0x78) 1684 #define RING_DMA_FADD_UDW(base) _MMIO((base)+0x60) /* gen8+ */ 1685 #define RING_INSTPM(base) _MMIO((base)+0xc0) 1686 #define RING_MI_MODE(base) _MMIO((base)+0x9c) 1687 #define INSTPS _MMIO(0x2070) /* 965+ only */ 1688 #define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */ 1689 #define ACTHD_I965 _MMIO(0x2074) 1690 #define HWS_PGA _MMIO(0x2080) 1691 #define HWS_ADDRESS_MASK 0xfffff000 1692 #define HWS_START_ADDRESS_SHIFT 4 1693 #define PWRCTXA _MMIO(0x2088) /* 965GM+ only */ 1694 #define PWRCTX_EN (1<<0) 1695 #define IPEIR _MMIO(0x2088) 1696 #define IPEHR _MMIO(0x208c) 1697 #define GEN2_INSTDONE _MMIO(0x2090) 1698 #define NOPID _MMIO(0x2094) 1699 #define HWSTAM _MMIO(0x2098) 1700 #define DMA_FADD_I8XX _MMIO(0x20d0) 1701 #define RING_BBSTATE(base) _MMIO((base)+0x110) 1702 #define RING_BB_PPGTT (1 << 5) 1703 #define RING_SBBADDR(base) _MMIO((base)+0x114) /* hsw+ */ 1704 #define RING_SBBSTATE(base) _MMIO((base)+0x118) /* hsw+ */ 1705 #define RING_SBBADDR_UDW(base) _MMIO((base)+0x11c) /* gen8+ */ 1706 #define RING_BBADDR(base) _MMIO((base)+0x140) 1707 #define RING_BBADDR_UDW(base) _MMIO((base)+0x168) /* gen8+ */ 1708 #define RING_BB_PER_CTX_PTR(base) _MMIO((base)+0x1c0) /* gen8+ */ 1709 #define RING_INDIRECT_CTX(base) _MMIO((base)+0x1c4) /* gen8+ */ 1710 #define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base)+0x1c8) /* gen8+ */ 1711 #define RING_CTX_TIMESTAMP(base) _MMIO((base)+0x3a8) /* gen8+ */ 1712 1713 #define ERROR_GEN6 _MMIO(0x40a0) 1714 #define GEN7_ERR_INT _MMIO(0x44040) 1715 #define ERR_INT_POISON (1<<31) 1716 #define ERR_INT_MMIO_UNCLAIMED (1<<13) 1717 #define ERR_INT_PIPE_CRC_DONE_C (1<<8) 1718 #define ERR_INT_FIFO_UNDERRUN_C (1<<6) 1719 #define ERR_INT_PIPE_CRC_DONE_B (1<<5) 1720 #define ERR_INT_FIFO_UNDERRUN_B (1<<3) 1721 #define ERR_INT_PIPE_CRC_DONE_A (1<<2) 1722 #define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + (pipe)*3)) 1723 #define ERR_INT_FIFO_UNDERRUN_A (1<<0) 1724 #define ERR_INT_FIFO_UNDERRUN(pipe) (1<<((pipe)*3)) 1725 1726 #define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10) 1727 #define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14) 1728 1729 #define FPGA_DBG _MMIO(0x42300) 1730 #define FPGA_DBG_RM_NOCLAIM (1<<31) 1731 1732 #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028) 1733 #define CLAIM_ER_CLR (1 << 31) 1734 #define CLAIM_ER_OVERFLOW (1 << 16) 1735 #define CLAIM_ER_CTR_MASK 0xffff 1736 1737 #define DERRMR _MMIO(0x44050) 1738 /* Note that HBLANK events are reserved on bdw+ */ 1739 #define DERRMR_PIPEA_SCANLINE (1<<0) 1740 #define DERRMR_PIPEA_PRI_FLIP_DONE (1<<1) 1741 #define DERRMR_PIPEA_SPR_FLIP_DONE (1<<2) 1742 #define DERRMR_PIPEA_VBLANK (1<<3) 1743 #define DERRMR_PIPEA_HBLANK (1<<5) 1744 #define DERRMR_PIPEB_SCANLINE (1<<8) 1745 #define DERRMR_PIPEB_PRI_FLIP_DONE (1<<9) 1746 #define DERRMR_PIPEB_SPR_FLIP_DONE (1<<10) 1747 #define DERRMR_PIPEB_VBLANK (1<<11) 1748 #define DERRMR_PIPEB_HBLANK (1<<13) 1749 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */ 1750 #define DERRMR_PIPEC_SCANLINE (1<<14) 1751 #define DERRMR_PIPEC_PRI_FLIP_DONE (1<<15) 1752 #define DERRMR_PIPEC_SPR_FLIP_DONE (1<<20) 1753 #define DERRMR_PIPEC_VBLANK (1<<21) 1754 #define DERRMR_PIPEC_HBLANK (1<<22) 1755 1756 1757 /* GM45+ chicken bits -- debug workaround bits that may be required 1758 * for various sorts of correct behavior. The top 16 bits of each are 1759 * the enables for writing to the corresponding low bit. 1760 */ 1761 #define _3D_CHICKEN _MMIO(0x2084) 1762 #define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10) 1763 #define _3D_CHICKEN2 _MMIO(0x208c) 1764 /* Disables pipelining of read flushes past the SF-WIZ interface. 1765 * Required on all Ironlake steppings according to the B-Spec, but the 1766 * particular danger of not doing so is not specified. 1767 */ 1768 # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) 1769 #define _3D_CHICKEN3 _MMIO(0x2090) 1770 #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10) 1771 #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5) 1772 #define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ */ 1773 #define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */ 1774 1775 #define MI_MODE _MMIO(0x209c) 1776 # define VS_TIMER_DISPATCH (1 << 6) 1777 # define MI_FLUSH_ENABLE (1 << 12) 1778 # define ASYNC_FLIP_PERF_DISABLE (1 << 14) 1779 # define MODE_IDLE (1 << 9) 1780 # define STOP_RING (1 << 8) 1781 1782 #define GEN6_GT_MODE _MMIO(0x20d0) 1783 #define GEN7_GT_MODE _MMIO(0x7008) 1784 #define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7)) 1785 #define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0) 1786 #define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1) 1787 #define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0) 1788 #define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1) 1789 #define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5) 1790 #define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2)) 1791 #define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2)) 1792 1793 /* WaClearTdlStateAckDirtyBits */ 1794 #define GEN8_STATE_ACK _MMIO(0x20F0) 1795 #define GEN9_STATE_ACK_SLICE1 _MMIO(0x20F8) 1796 #define GEN9_STATE_ACK_SLICE2 _MMIO(0x2100) 1797 #define GEN9_STATE_ACK_TDL0 (1 << 12) 1798 #define GEN9_STATE_ACK_TDL1 (1 << 13) 1799 #define GEN9_STATE_ACK_TDL2 (1 << 14) 1800 #define GEN9_STATE_ACK_TDL3 (1 << 15) 1801 #define GEN9_SUBSLICE_TDL_ACK_BITS \ 1802 (GEN9_STATE_ACK_TDL3 | GEN9_STATE_ACK_TDL2 | \ 1803 GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0) 1804 1805 #define GFX_MODE _MMIO(0x2520) 1806 #define GFX_MODE_GEN7 _MMIO(0x229c) 1807 #define RING_MODE_GEN7(ring) _MMIO((ring)->mmio_base+0x29c) 1808 #define GFX_RUN_LIST_ENABLE (1<<15) 1809 #define GFX_INTERRUPT_STEERING (1<<14) 1810 #define GFX_TLB_INVALIDATE_EXPLICIT (1<<13) 1811 #define GFX_SURFACE_FAULT_ENABLE (1<<12) 1812 #define GFX_REPLAY_MODE (1<<11) 1813 #define GFX_PSMI_GRANULARITY (1<<10) 1814 #define GFX_PPGTT_ENABLE (1<<9) 1815 #define GEN8_GFX_PPGTT_48B (1<<7) 1816 1817 #define GFX_FORWARD_VBLANK_MASK (3<<5) 1818 #define GFX_FORWARD_VBLANK_NEVER (0<<5) 1819 #define GFX_FORWARD_VBLANK_ALWAYS (1<<5) 1820 #define GFX_FORWARD_VBLANK_COND (2<<5) 1821 1822 #define VLV_DISPLAY_BASE 0x180000 1823 #define VLV_MIPI_BASE VLV_DISPLAY_BASE 1824 #define BXT_MIPI_BASE 0x60000 1825 1826 #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030) 1827 #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034) 1828 #define SCPD0 _MMIO(0x209c) /* 915+ only */ 1829 #define IER _MMIO(0x20a0) 1830 #define IIR _MMIO(0x20a4) 1831 #define IMR _MMIO(0x20a8) 1832 #define ISR _MMIO(0x20ac) 1833 #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060) 1834 #define GINT_DIS (1<<22) 1835 #define GCFG_DIS (1<<8) 1836 #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064) 1837 #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084) 1838 #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0) 1839 #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4) 1840 #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8) 1841 #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac) 1842 #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120) 1843 #define VLV_PCBR_ADDR_SHIFT 12 1844 1845 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */ 1846 #define EIR _MMIO(0x20b0) 1847 #define EMR _MMIO(0x20b4) 1848 #define ESR _MMIO(0x20b8) 1849 #define GM45_ERROR_PAGE_TABLE (1<<5) 1850 #define GM45_ERROR_MEM_PRIV (1<<4) 1851 #define I915_ERROR_PAGE_TABLE (1<<4) 1852 #define GM45_ERROR_CP_PRIV (1<<3) 1853 #define I915_ERROR_MEMORY_REFRESH (1<<1) 1854 #define I915_ERROR_INSTRUCTION (1<<0) 1855 #define INSTPM _MMIO(0x20c0) 1856 #define INSTPM_SELF_EN (1<<12) /* 915GM only */ 1857 #define INSTPM_AGPBUSY_INT_EN (1<<11) /* gen3: when disabled, pending interrupts 1858 will not assert AGPBUSY# and will only 1859 be delivered when out of C3. */ 1860 #define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */ 1861 #define INSTPM_TLB_INVALIDATE (1<<9) 1862 #define INSTPM_SYNC_FLUSH (1<<5) 1863 #define ACTHD _MMIO(0x20c8) 1864 #define MEM_MODE _MMIO(0x20cc) 1865 #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1<<3) /* 830 only */ 1866 #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1<<2) /* 830/845 only */ 1867 #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1<<2) /* 85x only */ 1868 #define FW_BLC _MMIO(0x20d8) 1869 #define FW_BLC2 _MMIO(0x20dc) 1870 #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */ 1871 #define FW_BLC_SELF_EN_MASK (1<<31) 1872 #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ 1873 #define FW_BLC_SELF_EN (1<<15) /* 945 only */ 1874 #define MM_BURST_LENGTH 0x00700000 1875 #define MM_FIFO_WATERMARK 0x0001F000 1876 #define LM_BURST_LENGTH 0x00000700 1877 #define LM_FIFO_WATERMARK 0x0000001F 1878 #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */ 1879 1880 /* Make render/texture TLB fetches lower priorty than associated data 1881 * fetches. This is not turned on by default 1882 */ 1883 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) 1884 1885 /* Isoch request wait on GTT enable (Display A/B/C streams). 1886 * Make isoch requests stall on the TLB update. May cause 1887 * display underruns (test mode only) 1888 */ 1889 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14) 1890 1891 /* Block grant count for isoch requests when block count is 1892 * set to a finite value. 1893 */ 1894 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12) 1895 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ 1896 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ 1897 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ 1898 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ 1899 1900 /* Enable render writes to complete in C2/C3/C4 power states. 1901 * If this isn't enabled, render writes are prevented in low 1902 * power states. That seems bad to me. 1903 */ 1904 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) 1905 1906 /* This acknowledges an async flip immediately instead 1907 * of waiting for 2TLB fetches. 1908 */ 1909 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) 1910 1911 /* Enables non-sequential data reads through arbiter 1912 */ 1913 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) 1914 1915 /* Disable FSB snooping of cacheable write cycles from binner/render 1916 * command stream 1917 */ 1918 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) 1919 1920 /* Arbiter time slice for non-isoch streams */ 1921 #define MI_ARB_TIME_SLICE_MASK (7 << 5) 1922 #define MI_ARB_TIME_SLICE_1 (0 << 5) 1923 #define MI_ARB_TIME_SLICE_2 (1 << 5) 1924 #define MI_ARB_TIME_SLICE_4 (2 << 5) 1925 #define MI_ARB_TIME_SLICE_6 (3 << 5) 1926 #define MI_ARB_TIME_SLICE_8 (4 << 5) 1927 #define MI_ARB_TIME_SLICE_10 (5 << 5) 1928 #define MI_ARB_TIME_SLICE_14 (6 << 5) 1929 #define MI_ARB_TIME_SLICE_16 (7 << 5) 1930 1931 /* Low priority grace period page size */ 1932 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ 1933 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) 1934 1935 /* Disable display A/B trickle feed */ 1936 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) 1937 1938 /* Set display plane priority */ 1939 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ 1940 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ 1941 1942 #define MI_STATE _MMIO(0x20e4) /* gen2 only */ 1943 #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */ 1944 #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */ 1945 1946 #define CACHE_MODE_0 _MMIO(0x2120) /* 915+ only */ 1947 #define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8) 1948 #define CM0_IZ_OPT_DISABLE (1<<6) 1949 #define CM0_ZR_OPT_DISABLE (1<<5) 1950 #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5) 1951 #define CM0_DEPTH_EVICT_DISABLE (1<<4) 1952 #define CM0_COLOR_EVICT_DISABLE (1<<3) 1953 #define CM0_DEPTH_WRITE_DISABLE (1<<1) 1954 #define CM0_RC_OP_FLUSH_DISABLE (1<<0) 1955 #define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */ 1956 #define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008) 1957 #define GFX_FLSH_CNTL_EN (1<<0) 1958 #define ECOSKPD _MMIO(0x21d0) 1959 #define ECO_GATING_CX_ONLY (1<<3) 1960 #define ECO_FLIP_DONE (1<<0) 1961 1962 #define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */ 1963 #define RC_OP_FLUSH_ENABLE (1<<0) 1964 #define HIZ_RAW_STALL_OPT_DISABLE (1<<2) 1965 #define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */ 1966 #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6) 1967 #define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6) 1968 #define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1<<1) 1969 1970 #define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0) 1971 #define GEN6_BLITTER_LOCK_SHIFT 16 1972 #define GEN6_BLITTER_FBC_NOTIFY (1<<3) 1973 1974 #define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050) 1975 #define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0) 1976 #define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12) 1977 #define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10) 1978 1979 /* Fuse readout registers for GT */ 1980 #define CHV_FUSE_GT _MMIO(VLV_DISPLAY_BASE + 0x2168) 1981 #define CHV_FGT_DISABLE_SS0 (1 << 10) 1982 #define CHV_FGT_DISABLE_SS1 (1 << 11) 1983 #define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16 1984 #define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT) 1985 #define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20 1986 #define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT) 1987 #define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24 1988 #define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT) 1989 #define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28 1990 #define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT) 1991 1992 #define GEN8_FUSE2 _MMIO(0x9120) 1993 #define GEN8_F2_SS_DIS_SHIFT 21 1994 #define GEN8_F2_SS_DIS_MASK (0x7 << GEN8_F2_SS_DIS_SHIFT) 1995 #define GEN8_F2_S_ENA_SHIFT 25 1996 #define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT) 1997 1998 #define GEN9_F2_SS_DIS_SHIFT 20 1999 #define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT) 2000 2001 #define GEN8_EU_DISABLE0 _MMIO(0x9134) 2002 #define GEN8_EU_DIS0_S0_MASK 0xffffff 2003 #define GEN8_EU_DIS0_S1_SHIFT 24 2004 #define GEN8_EU_DIS0_S1_MASK (0xff << GEN8_EU_DIS0_S1_SHIFT) 2005 2006 #define GEN8_EU_DISABLE1 _MMIO(0x9138) 2007 #define GEN8_EU_DIS1_S1_MASK 0xffff 2008 #define GEN8_EU_DIS1_S2_SHIFT 16 2009 #define GEN8_EU_DIS1_S2_MASK (0xffff << GEN8_EU_DIS1_S2_SHIFT) 2010 2011 #define GEN8_EU_DISABLE2 _MMIO(0x913c) 2012 #define GEN8_EU_DIS2_S2_MASK 0xff 2013 2014 #define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice)*0x4) 2015 2016 #define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050) 2017 #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0) 2018 #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2) 2019 #define GEN6_BSD_SLEEP_INDICATOR (1 << 3) 2020 #define GEN6_BSD_GO_INDICATOR (1 << 4) 2021 2022 /* On modern GEN architectures interrupt control consists of two sets 2023 * of registers. The first set pertains to the ring generating the 2024 * interrupt. The second control is for the functional block generating the 2025 * interrupt. These are PM, GT, DE, etc. 2026 * 2027 * Luckily *knocks on wood* all the ring interrupt bits match up with the 2028 * GT interrupt bits, so we don't need to duplicate the defines. 2029 * 2030 * These defines should cover us well from SNB->HSW with minor exceptions 2031 * it can also work on ILK. 2032 */ 2033 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) 2034 #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25) 2035 #define GT_BLT_USER_INTERRUPT (1 << 22) 2036 #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15) 2037 #define GT_BSD_USER_INTERRUPT (1 << 12) 2038 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */ 2039 #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8) 2040 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */ 2041 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4) 2042 #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3) 2043 #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2) 2044 #define GT_RENDER_DEBUG_INTERRUPT (1 << 1) 2045 #define GT_RENDER_USER_INTERRUPT (1 << 0) 2046 2047 #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */ 2048 #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */ 2049 2050 #define GT_PARITY_ERROR(dev) \ 2051 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \ 2052 (IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0)) 2053 2054 /* These are all the "old" interrupts */ 2055 #define ILK_BSD_USER_INTERRUPT (1<<5) 2056 2057 #define I915_PM_INTERRUPT (1<<31) 2058 #define I915_ISP_INTERRUPT (1<<22) 2059 #define I915_LPE_PIPE_B_INTERRUPT (1<<21) 2060 #define I915_LPE_PIPE_A_INTERRUPT (1<<20) 2061 #define I915_MIPIC_INTERRUPT (1<<19) 2062 #define I915_MIPIA_INTERRUPT (1<<18) 2063 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) 2064 #define I915_DISPLAY_PORT_INTERRUPT (1<<17) 2065 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1<<16) 2066 #define I915_MASTER_ERROR_INTERRUPT (1<<15) 2067 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) 2068 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1<<14) 2069 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ 2070 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1<<13) 2071 #define I915_HWB_OOM_INTERRUPT (1<<13) 2072 #define I915_LPE_PIPE_C_INTERRUPT (1<<12) 2073 #define I915_SYNC_STATUS_INTERRUPT (1<<12) 2074 #define I915_MISC_INTERRUPT (1<<11) 2075 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) 2076 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1<<10) 2077 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) 2078 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1<<9) 2079 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) 2080 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1<<8) 2081 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) 2082 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) 2083 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) 2084 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) 2085 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) 2086 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1<<3) 2087 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1<<2) 2088 #define I915_DEBUG_INTERRUPT (1<<2) 2089 #define I915_WINVALID_INTERRUPT (1<<1) 2090 #define I915_USER_INTERRUPT (1<<1) 2091 #define I915_ASLE_INTERRUPT (1<<0) 2092 #define I915_BSD_USER_INTERRUPT (1<<25) 2093 2094 #define GEN6_BSD_RNCID _MMIO(0x12198) 2095 2096 #define GEN7_FF_THREAD_MODE _MMIO(0x20a0) 2097 #define GEN7_FF_SCHED_MASK 0x0077070 2098 #define GEN8_FF_DS_REF_CNT_FFME (1 << 19) 2099 #define GEN7_FF_TS_SCHED_HS1 (0x5<<16) 2100 #define GEN7_FF_TS_SCHED_HS0 (0x3<<16) 2101 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16) 2102 #define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */ 2103 #define GEN7_FF_VS_REF_CNT_FFME (1 << 15) 2104 #define GEN7_FF_VS_SCHED_HS1 (0x5<<12) 2105 #define GEN7_FF_VS_SCHED_HS0 (0x3<<12) 2106 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */ 2107 #define GEN7_FF_VS_SCHED_HW (0x0<<12) 2108 #define GEN7_FF_DS_SCHED_HS1 (0x5<<4) 2109 #define GEN7_FF_DS_SCHED_HS0 (0x3<<4) 2110 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */ 2111 #define GEN7_FF_DS_SCHED_HW (0x0<<4) 2112 2113 /* 2114 * Framebuffer compression (915+ only) 2115 */ 2116 2117 #define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */ 2118 #define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */ 2119 #define FBC_CONTROL _MMIO(0x3208) 2120 #define FBC_CTL_EN (1<<31) 2121 #define FBC_CTL_PERIODIC (1<<30) 2122 #define FBC_CTL_INTERVAL_SHIFT (16) 2123 #define FBC_CTL_UNCOMPRESSIBLE (1<<14) 2124 #define FBC_CTL_C3_IDLE (1<<13) 2125 #define FBC_CTL_STRIDE_SHIFT (5) 2126 #define FBC_CTL_FENCENO_SHIFT (0) 2127 #define FBC_COMMAND _MMIO(0x320c) 2128 #define FBC_CMD_COMPRESS (1<<0) 2129 #define FBC_STATUS _MMIO(0x3210) 2130 #define FBC_STAT_COMPRESSING (1<<31) 2131 #define FBC_STAT_COMPRESSED (1<<30) 2132 #define FBC_STAT_MODIFIED (1<<29) 2133 #define FBC_STAT_CURRENT_LINE_SHIFT (0) 2134 #define FBC_CONTROL2 _MMIO(0x3214) 2135 #define FBC_CTL_FENCE_DBL (0<<4) 2136 #define FBC_CTL_IDLE_IMM (0<<2) 2137 #define FBC_CTL_IDLE_FULL (1<<2) 2138 #define FBC_CTL_IDLE_LINE (2<<2) 2139 #define FBC_CTL_IDLE_DEBUG (3<<2) 2140 #define FBC_CTL_CPU_FENCE (1<<1) 2141 #define FBC_CTL_PLANE(plane) ((plane)<<0) 2142 #define FBC_FENCE_OFF _MMIO(0x3218) /* BSpec typo has 321Bh */ 2143 #define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) 2144 2145 #define FBC_STATUS2 _MMIO(0x43214) 2146 #define FBC_COMPRESSION_MASK 0x7ff 2147 2148 #define FBC_LL_SIZE (1536) 2149 2150 /* Framebuffer compression for GM45+ */ 2151 #define DPFC_CB_BASE _MMIO(0x3200) 2152 #define DPFC_CONTROL _MMIO(0x3208) 2153 #define DPFC_CTL_EN (1<<31) 2154 #define DPFC_CTL_PLANE(plane) ((plane)<<30) 2155 #define IVB_DPFC_CTL_PLANE(plane) ((plane)<<29) 2156 #define DPFC_CTL_FENCE_EN (1<<29) 2157 #define IVB_DPFC_CTL_FENCE_EN (1<<28) 2158 #define DPFC_CTL_PERSISTENT_MODE (1<<25) 2159 #define DPFC_SR_EN (1<<10) 2160 #define DPFC_CTL_LIMIT_1X (0<<6) 2161 #define DPFC_CTL_LIMIT_2X (1<<6) 2162 #define DPFC_CTL_LIMIT_4X (2<<6) 2163 #define DPFC_RECOMP_CTL _MMIO(0x320c) 2164 #define DPFC_RECOMP_STALL_EN (1<<27) 2165 #define DPFC_RECOMP_STALL_WM_SHIFT (16) 2166 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) 2167 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) 2168 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) 2169 #define DPFC_STATUS _MMIO(0x3210) 2170 #define DPFC_INVAL_SEG_SHIFT (16) 2171 #define DPFC_INVAL_SEG_MASK (0x07ff0000) 2172 #define DPFC_COMP_SEG_SHIFT (0) 2173 #define DPFC_COMP_SEG_MASK (0x000003ff) 2174 #define DPFC_STATUS2 _MMIO(0x3214) 2175 #define DPFC_FENCE_YOFF _MMIO(0x3218) 2176 #define DPFC_CHICKEN _MMIO(0x3224) 2177 #define DPFC_HT_MODIFY (1<<31) 2178 2179 /* Framebuffer compression for Ironlake */ 2180 #define ILK_DPFC_CB_BASE _MMIO(0x43200) 2181 #define ILK_DPFC_CONTROL _MMIO(0x43208) 2182 #define FBC_CTL_FALSE_COLOR (1<<10) 2183 /* The bit 28-8 is reserved */ 2184 #define DPFC_RESERVED (0x1FFFFF00) 2185 #define ILK_DPFC_RECOMP_CTL _MMIO(0x4320c) 2186 #define ILK_DPFC_STATUS _MMIO(0x43210) 2187 #define ILK_DPFC_FENCE_YOFF _MMIO(0x43218) 2188 #define ILK_DPFC_CHICKEN _MMIO(0x43224) 2189 #define ILK_FBC_RT_BASE _MMIO(0x2128) 2190 #define ILK_FBC_RT_VALID (1<<0) 2191 #define SNB_FBC_FRONT_BUFFER (1<<1) 2192 2193 #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000) 2194 #define ILK_FBCQ_DIS (1<<22) 2195 #define ILK_PABSTRETCH_DIS (1<<21) 2196 2197 2198 /* 2199 * Framebuffer compression for Sandybridge 2200 * 2201 * The following two registers are of type GTTMMADR 2202 */ 2203 #define SNB_DPFC_CTL_SA _MMIO(0x100100) 2204 #define SNB_CPU_FENCE_ENABLE (1<<29) 2205 #define DPFC_CPU_FENCE_OFFSET _MMIO(0x100104) 2206 2207 /* Framebuffer compression for Ivybridge */ 2208 #define IVB_FBC_RT_BASE _MMIO(0x7020) 2209 2210 #define IPS_CTL _MMIO(0x43408) 2211 #define IPS_ENABLE (1 << 31) 2212 2213 #define MSG_FBC_REND_STATE _MMIO(0x50380) 2214 #define FBC_REND_NUKE (1<<2) 2215 #define FBC_REND_CACHE_CLEAN (1<<1) 2216 2217 /* 2218 * GPIO regs 2219 */ 2220 #define GPIOA _MMIO(0x5010) 2221 #define GPIOB _MMIO(0x5014) 2222 #define GPIOC _MMIO(0x5018) 2223 #define GPIOD _MMIO(0x501c) 2224 #define GPIOE _MMIO(0x5020) 2225 #define GPIOF _MMIO(0x5024) 2226 #define GPIOG _MMIO(0x5028) 2227 #define GPIOH _MMIO(0x502c) 2228 # define GPIO_CLOCK_DIR_MASK (1 << 0) 2229 # define GPIO_CLOCK_DIR_IN (0 << 1) 2230 # define GPIO_CLOCK_DIR_OUT (1 << 1) 2231 # define GPIO_CLOCK_VAL_MASK (1 << 2) 2232 # define GPIO_CLOCK_VAL_OUT (1 << 3) 2233 # define GPIO_CLOCK_VAL_IN (1 << 4) 2234 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) 2235 # define GPIO_DATA_DIR_MASK (1 << 8) 2236 # define GPIO_DATA_DIR_IN (0 << 9) 2237 # define GPIO_DATA_DIR_OUT (1 << 9) 2238 # define GPIO_DATA_VAL_MASK (1 << 10) 2239 # define GPIO_DATA_VAL_OUT (1 << 11) 2240 # define GPIO_DATA_VAL_IN (1 << 12) 2241 # define GPIO_DATA_PULLUP_DISABLE (1 << 13) 2242 2243 #define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */ 2244 #define GMBUS_RATE_100KHZ (0<<8) 2245 #define GMBUS_RATE_50KHZ (1<<8) 2246 #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ 2247 #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */ 2248 #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */ 2249 #define GMBUS_PIN_DISABLED 0 2250 #define GMBUS_PIN_SSC 1 2251 #define GMBUS_PIN_VGADDC 2 2252 #define GMBUS_PIN_PANEL 3 2253 #define GMBUS_PIN_DPD_CHV 3 /* HDMID_CHV */ 2254 #define GMBUS_PIN_DPC 4 /* HDMIC */ 2255 #define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */ 2256 #define GMBUS_PIN_DPD 6 /* HDMID */ 2257 #define GMBUS_PIN_RESERVED 7 /* 7 reserved */ 2258 #define GMBUS_PIN_1_BXT 1 2259 #define GMBUS_PIN_2_BXT 2 2260 #define GMBUS_PIN_3_BXT 3 2261 #define GMBUS_NUM_PINS 7 /* including 0 */ 2262 #define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */ 2263 #define GMBUS_SW_CLR_INT (1<<31) 2264 #define GMBUS_SW_RDY (1<<30) 2265 #define GMBUS_ENT (1<<29) /* enable timeout */ 2266 #define GMBUS_CYCLE_NONE (0<<25) 2267 #define GMBUS_CYCLE_WAIT (1<<25) 2268 #define GMBUS_CYCLE_INDEX (2<<25) 2269 #define GMBUS_CYCLE_STOP (4<<25) 2270 #define GMBUS_BYTE_COUNT_SHIFT 16 2271 #define GMBUS_BYTE_COUNT_MAX 256U 2272 #define GMBUS_SLAVE_INDEX_SHIFT 8 2273 #define GMBUS_SLAVE_ADDR_SHIFT 1 2274 #define GMBUS_SLAVE_READ (1<<0) 2275 #define GMBUS_SLAVE_WRITE (0<<0) 2276 #define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */ 2277 #define GMBUS_INUSE (1<<15) 2278 #define GMBUS_HW_WAIT_PHASE (1<<14) 2279 #define GMBUS_STALL_TIMEOUT (1<<13) 2280 #define GMBUS_INT (1<<12) 2281 #define GMBUS_HW_RDY (1<<11) 2282 #define GMBUS_SATOER (1<<10) 2283 #define GMBUS_ACTIVE (1<<9) 2284 #define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */ 2285 #define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */ 2286 #define GMBUS_SLAVE_TIMEOUT_EN (1<<4) 2287 #define GMBUS_NAK_EN (1<<3) 2288 #define GMBUS_IDLE_EN (1<<2) 2289 #define GMBUS_HW_WAIT_EN (1<<1) 2290 #define GMBUS_HW_RDY_EN (1<<0) 2291 #define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */ 2292 #define GMBUS_2BYTE_INDEX_EN (1<<31) 2293 2294 /* 2295 * Clock control & power management 2296 */ 2297 #define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014) 2298 #define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018) 2299 #define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030) 2300 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) 2301 2302 #define VGA0 _MMIO(0x6000) 2303 #define VGA1 _MMIO(0x6004) 2304 #define VGA_PD _MMIO(0x6010) 2305 #define VGA0_PD_P2_DIV_4 (1 << 7) 2306 #define VGA0_PD_P1_DIV_2 (1 << 5) 2307 #define VGA0_PD_P1_SHIFT 0 2308 #define VGA0_PD_P1_MASK (0x1f << 0) 2309 #define VGA1_PD_P2_DIV_4 (1 << 15) 2310 #define VGA1_PD_P1_DIV_2 (1 << 13) 2311 #define VGA1_PD_P1_SHIFT 8 2312 #define VGA1_PD_P1_MASK (0x1f << 8) 2313 #define DPLL_VCO_ENABLE (1 << 31) 2314 #define DPLL_SDVO_HIGH_SPEED (1 << 30) 2315 #define DPLL_DVO_2X_MODE (1 << 30) 2316 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) 2317 #define DPLL_SYNCLOCK_ENABLE (1 << 29) 2318 #define DPLL_REF_CLK_ENABLE_VLV (1 << 29) 2319 #define DPLL_VGA_MODE_DIS (1 << 28) 2320 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 2321 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 2322 #define DPLL_MODE_MASK (3 << 26) 2323 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 2324 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 2325 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 2326 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 2327 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 2328 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 2329 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ 2330 #define DPLL_LOCK_VLV (1<<15) 2331 #define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14) 2332 #define DPLL_INTEGRATED_REF_CLK_VLV (1<<13) 2333 #define DPLL_SSC_REF_CLK_CHV (1<<13) 2334 #define DPLL_PORTC_READY_MASK (0xf << 4) 2335 #define DPLL_PORTB_READY_MASK (0xf) 2336 2337 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 2338 2339 /* Additional CHV pll/phy registers */ 2340 #define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240) 2341 #define DPLL_PORTD_READY_MASK (0xf) 2342 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100) 2343 #define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2*(phy)+(ch)+27)) 2344 #define PHY_LDO_DELAY_0NS 0x0 2345 #define PHY_LDO_DELAY_200NS 0x1 2346 #define PHY_LDO_DELAY_600NS 0x2 2347 #define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2*(phy)+23)) 2348 #define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8*(phy)+4*(ch)+11)) 2349 #define PHY_CH_SU_PSR 0x1 2350 #define PHY_CH_DEEP_PSR 0x7 2351 #define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6*(phy)+3*(ch)+2)) 2352 #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy)) 2353 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104) 2354 #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1<<31) : (1<<30)) 2355 #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6-(6*(phy)+3*(ch)))) 2356 #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8-(6*(phy)+3*(ch)+(spline)))) 2357 2358 /* 2359 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 2360 * this field (only one bit may be set). 2361 */ 2362 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 2363 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 2364 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 2365 /* i830, required in DVO non-gang */ 2366 #define PLL_P2_DIVIDE_BY_4 (1 << 23) 2367 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 2368 #define PLL_REF_INPUT_DREFCLK (0 << 13) 2369 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 2370 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 2371 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 2372 #define PLL_REF_INPUT_MASK (3 << 13) 2373 #define PLL_LOAD_PULSE_PHASE_SHIFT 9 2374 /* Ironlake */ 2375 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 2376 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) 2377 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9) 2378 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 2379 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff 2380 2381 /* 2382 * Parallel to Serial Load Pulse phase selection. 2383 * Selects the phase for the 10X DPLL clock for the PCIe 2384 * digital display port. The range is 4 to 13; 10 or more 2385 * is just a flip delay. The default is 6 2386 */ 2387 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 2388 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 2389 /* 2390 * SDVO multiplier for 945G/GM. Not used on 965. 2391 */ 2392 #define SDVO_MULTIPLIER_MASK 0x000000ff 2393 #define SDVO_MULTIPLIER_SHIFT_HIRES 4 2394 #define SDVO_MULTIPLIER_SHIFT_VGA 0 2395 2396 #define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c) 2397 #define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020) 2398 #define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c) 2399 #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD) 2400 2401 /* 2402 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 2403 * 2404 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 2405 */ 2406 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 2407 #define DPLL_MD_UDI_DIVIDER_SHIFT 24 2408 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 2409 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 2410 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 2411 /* 2412 * SDVO/UDI pixel multiplier. 2413 * 2414 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 2415 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 2416 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 2417 * dummy bytes in the datastream at an increased clock rate, with both sides of 2418 * the link knowing how many bytes are fill. 2419 * 2420 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 2421 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 2422 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 2423 * through an SDVO command. 2424 * 2425 * This register field has values of multiplication factor minus 1, with 2426 * a maximum multiplier of 5 for SDVO. 2427 */ 2428 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 2429 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 2430 /* 2431 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 2432 * This best be set to the default value (3) or the CRT won't work. No, 2433 * I don't entirely understand what this does... 2434 */ 2435 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 2436 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 2437 2438 #define _FPA0 0x6040 2439 #define _FPA1 0x6044 2440 #define _FPB0 0x6048 2441 #define _FPB1 0x604c 2442 #define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0) 2443 #define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1) 2444 #define FP_N_DIV_MASK 0x003f0000 2445 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 2446 #define FP_N_DIV_SHIFT 16 2447 #define FP_M1_DIV_MASK 0x00003f00 2448 #define FP_M1_DIV_SHIFT 8 2449 #define FP_M2_DIV_MASK 0x0000003f 2450 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff 2451 #define FP_M2_DIV_SHIFT 0 2452 #define DPLL_TEST _MMIO(0x606c) 2453 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 2454 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 2455 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 2456 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 2457 #define DPLLB_TEST_N_BYPASS (1 << 19) 2458 #define DPLLB_TEST_M_BYPASS (1 << 18) 2459 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 2460 #define DPLLA_TEST_N_BYPASS (1 << 3) 2461 #define DPLLA_TEST_M_BYPASS (1 << 2) 2462 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 2463 #define D_STATE _MMIO(0x6104) 2464 #define DSTATE_GFX_RESET_I830 (1<<6) 2465 #define DSTATE_PLL_D3_OFF (1<<3) 2466 #define DSTATE_GFX_CLOCK_GATING (1<<1) 2467 #define DSTATE_DOT_CLOCK_GATING (1<<0) 2468 #define DSPCLK_GATE_D _MMIO(dev_priv->info.display_mmio_offset + 0x6200) 2469 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ 2470 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ 2471 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ 2472 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ 2473 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ 2474 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ 2475 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ 2476 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ 2477 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ 2478 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ 2479 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ 2480 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ 2481 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ 2482 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ 2483 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ 2484 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ 2485 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ 2486 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ 2487 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ 2488 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) 2489 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) 2490 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) 2491 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) 2492 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ 2493 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ 2494 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ 2495 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) 2496 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) 2497 /* 2498 * This bit must be set on the 830 to prevent hangs when turning off the 2499 * overlay scaler. 2500 */ 2501 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) 2502 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) 2503 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) 2504 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ 2505 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ 2506 2507 #define RENCLK_GATE_D1 _MMIO(0x6204) 2508 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ 2509 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ 2510 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) 2511 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) 2512 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) 2513 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) 2514 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) 2515 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) 2516 # define MAG_CLOCK_GATE_DISABLE (1 << 5) 2517 /* This bit must be unset on 855,865 */ 2518 # define MECI_CLOCK_GATE_DISABLE (1 << 4) 2519 # define DCMP_CLOCK_GATE_DISABLE (1 << 3) 2520 # define MEC_CLOCK_GATE_DISABLE (1 << 2) 2521 # define MECO_CLOCK_GATE_DISABLE (1 << 1) 2522 /* This bit must be set on 855,865. */ 2523 # define SV_CLOCK_GATE_DISABLE (1 << 0) 2524 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) 2525 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) 2526 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) 2527 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) 2528 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) 2529 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) 2530 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) 2531 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) 2532 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) 2533 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) 2534 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) 2535 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) 2536 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) 2537 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) 2538 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) 2539 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) 2540 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) 2541 2542 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) 2543 /* This bit must always be set on 965G/965GM */ 2544 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) 2545 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) 2546 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) 2547 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) 2548 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) 2549 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) 2550 /* This bit must always be set on 965G */ 2551 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) 2552 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) 2553 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) 2554 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) 2555 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) 2556 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) 2557 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) 2558 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) 2559 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) 2560 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) 2561 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) 2562 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) 2563 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) 2564 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) 2565 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) 2566 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) 2567 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) 2568 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) 2569 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) 2570 2571 #define RENCLK_GATE_D2 _MMIO(0x6208) 2572 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) 2573 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) 2574 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) 2575 2576 #define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */ 2577 #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4) 2578 2579 #define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */ 2580 #define DEUC _MMIO(0x6214) /* CRL only */ 2581 2582 #define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500) 2583 #define FW_CSPWRDWNEN (1<<15) 2584 2585 #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504) 2586 2587 #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508) 2588 #define CDCLK_FREQ_SHIFT 4 2589 #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT) 2590 #define CZCLK_FREQ_MASK 0xf 2591 2592 #define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C) 2593 #define PFI_CREDIT_63 (9 << 28) /* chv only */ 2594 #define PFI_CREDIT_31 (8 << 28) /* chv only */ 2595 #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */ 2596 #define PFI_CREDIT_RESEND (1 << 27) 2597 #define VGA_FAST_MODE_DISABLE (1 << 14) 2598 2599 #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510) 2600 2601 /* 2602 * Palette regs 2603 */ 2604 #define PALETTE_A_OFFSET 0xa000 2605 #define PALETTE_B_OFFSET 0xa800 2606 #define CHV_PALETTE_C_OFFSET 0xc000 2607 #define PALETTE(pipe, i) _MMIO(dev_priv->info.palette_offsets[pipe] + \ 2608 dev_priv->info.display_mmio_offset + (i) * 4) 2609 2610 /* MCH MMIO space */ 2611 2612 /* 2613 * MCHBAR mirror. 2614 * 2615 * This mirrors the MCHBAR MMIO space whose location is determined by 2616 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in 2617 * every way. It is not accessible from the CP register read instructions. 2618 * 2619 * Starting from Haswell, you can't write registers using the MCHBAR mirror, 2620 * just read. 2621 */ 2622 #define MCHBAR_MIRROR_BASE 0x10000 2623 2624 #define MCHBAR_MIRROR_BASE_SNB 0x140000 2625 2626 #define CTG_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x34) 2627 #define ELK_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x48) 2628 #define G4X_STOLEN_RESERVED_ADDR1_MASK (0xFFFF << 16) 2629 #define G4X_STOLEN_RESERVED_ADDR2_MASK (0xFFF << 4) 2630 2631 /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */ 2632 #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04) 2633 2634 /* 915-945 and GM965 MCH register controlling DRAM channel access */ 2635 #define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200) 2636 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) 2637 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) 2638 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) 2639 #define DCC_ADDRESSING_MODE_MASK (3 << 0) 2640 #define DCC_CHANNEL_XOR_DISABLE (1 << 10) 2641 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9) 2642 #define DCC2 _MMIO(MCHBAR_MIRROR_BASE + 0x204) 2643 #define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20) 2644 2645 /* Pineview MCH register contains DDR3 setting */ 2646 #define CSHRDDR3CTL _MMIO(MCHBAR_MIRROR_BASE + 0x1a8) 2647 #define CSHRDDR3CTL_DDR3 (1 << 2) 2648 2649 /* 965 MCH register controlling DRAM channel configuration */ 2650 #define C0DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x206) 2651 #define C1DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x606) 2652 2653 /* snb MCH registers for reading the DRAM channel configuration */ 2654 #define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004) 2655 #define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008) 2656 #define MAD_DIMM_C2 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C) 2657 #define MAD_DIMM_ECC_MASK (0x3 << 24) 2658 #define MAD_DIMM_ECC_OFF (0x0 << 24) 2659 #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24) 2660 #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24) 2661 #define MAD_DIMM_ECC_ON (0x3 << 24) 2662 #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22) 2663 #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21) 2664 #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */ 2665 #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */ 2666 #define MAD_DIMM_B_DUAL_RANK (0x1 << 18) 2667 #define MAD_DIMM_A_DUAL_RANK (0x1 << 17) 2668 #define MAD_DIMM_A_SELECT (0x1 << 16) 2669 /* DIMM sizes are in multiples of 256mb. */ 2670 #define MAD_DIMM_B_SIZE_SHIFT 8 2671 #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT) 2672 #define MAD_DIMM_A_SIZE_SHIFT 0 2673 #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT) 2674 2675 /* snb MCH registers for priority tuning */ 2676 #define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10) 2677 #define MCH_SSKPD_WM0_MASK 0x3f 2678 #define MCH_SSKPD_WM0_VAL 0xc 2679 2680 #define MCH_SECP_NRG_STTS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x592c) 2681 2682 /* Clocking configuration register */ 2683 #define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00) 2684 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */ 2685 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */ 2686 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */ 2687 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */ 2688 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */ 2689 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */ 2690 /* Note, below two are guess */ 2691 #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */ 2692 #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */ 2693 #define CLKCFG_FSB_MASK (7 << 0) 2694 #define CLKCFG_MEM_533 (1 << 4) 2695 #define CLKCFG_MEM_667 (2 << 4) 2696 #define CLKCFG_MEM_800 (3 << 4) 2697 #define CLKCFG_MEM_MASK (7 << 4) 2698 2699 #define HPLLVCO _MMIO(MCHBAR_MIRROR_BASE + 0xc38) 2700 #define HPLLVCO_MOBILE _MMIO(MCHBAR_MIRROR_BASE + 0xc0f) 2701 2702 #define TSC1 _MMIO(0x11001) 2703 #define TSE (1<<0) 2704 #define TR1 _MMIO(0x11006) 2705 #define TSFS _MMIO(0x11020) 2706 #define TSFS_SLOPE_MASK 0x0000ff00 2707 #define TSFS_SLOPE_SHIFT 8 2708 #define TSFS_INTR_MASK 0x000000ff 2709 2710 #define CRSTANDVID _MMIO(0x11100) 2711 #define PXVFREQ(fstart) _MMIO(0x11110 + (fstart) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ 2712 #define PXVFREQ_PX_MASK 0x7f000000 2713 #define PXVFREQ_PX_SHIFT 24 2714 #define VIDFREQ_BASE _MMIO(0x11110) 2715 #define VIDFREQ1 _MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */ 2716 #define VIDFREQ2 _MMIO(0x11114) 2717 #define VIDFREQ3 _MMIO(0x11118) 2718 #define VIDFREQ4 _MMIO(0x1111c) 2719 #define VIDFREQ_P0_MASK 0x1f000000 2720 #define VIDFREQ_P0_SHIFT 24 2721 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000 2722 #define VIDFREQ_P0_CSCLK_SHIFT 20 2723 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000 2724 #define VIDFREQ_P0_CRCLK_SHIFT 16 2725 #define VIDFREQ_P1_MASK 0x00001f00 2726 #define VIDFREQ_P1_SHIFT 8 2727 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0 2728 #define VIDFREQ_P1_CSCLK_SHIFT 4 2729 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f 2730 #define INTTOEXT_BASE_ILK _MMIO(0x11300) 2731 #define INTTOEXT_BASE _MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */ 2732 #define INTTOEXT_MAP3_SHIFT 24 2733 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) 2734 #define INTTOEXT_MAP2_SHIFT 16 2735 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) 2736 #define INTTOEXT_MAP1_SHIFT 8 2737 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) 2738 #define INTTOEXT_MAP0_SHIFT 0 2739 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) 2740 #define MEMSWCTL _MMIO(0x11170) /* Ironlake only */ 2741 #define MEMCTL_CMD_MASK 0xe000 2742 #define MEMCTL_CMD_SHIFT 13 2743 #define MEMCTL_CMD_RCLK_OFF 0 2744 #define MEMCTL_CMD_RCLK_ON 1 2745 #define MEMCTL_CMD_CHFREQ 2 2746 #define MEMCTL_CMD_CHVID 3 2747 #define MEMCTL_CMD_VMMOFF 4 2748 #define MEMCTL_CMD_VMMON 5 2749 #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears 2750 when command complete */ 2751 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ 2752 #define MEMCTL_FREQ_SHIFT 8 2753 #define MEMCTL_SFCAVM (1<<7) 2754 #define MEMCTL_TGT_VID_MASK 0x007f 2755 #define MEMIHYST _MMIO(0x1117c) 2756 #define MEMINTREN _MMIO(0x11180) /* 16 bits */ 2757 #define MEMINT_RSEXIT_EN (1<<8) 2758 #define MEMINT_CX_SUPR_EN (1<<7) 2759 #define MEMINT_CONT_BUSY_EN (1<<6) 2760 #define MEMINT_AVG_BUSY_EN (1<<5) 2761 #define MEMINT_EVAL_CHG_EN (1<<4) 2762 #define MEMINT_MON_IDLE_EN (1<<3) 2763 #define MEMINT_UP_EVAL_EN (1<<2) 2764 #define MEMINT_DOWN_EVAL_EN (1<<1) 2765 #define MEMINT_SW_CMD_EN (1<<0) 2766 #define MEMINTRSTR _MMIO(0x11182) /* 16 bits */ 2767 #define MEM_RSEXIT_MASK 0xc000 2768 #define MEM_RSEXIT_SHIFT 14 2769 #define MEM_CONT_BUSY_MASK 0x3000 2770 #define MEM_CONT_BUSY_SHIFT 12 2771 #define MEM_AVG_BUSY_MASK 0x0c00 2772 #define MEM_AVG_BUSY_SHIFT 10 2773 #define MEM_EVAL_CHG_MASK 0x0300 2774 #define MEM_EVAL_BUSY_SHIFT 8 2775 #define MEM_MON_IDLE_MASK 0x00c0 2776 #define MEM_MON_IDLE_SHIFT 6 2777 #define MEM_UP_EVAL_MASK 0x0030 2778 #define MEM_UP_EVAL_SHIFT 4 2779 #define MEM_DOWN_EVAL_MASK 0x000c 2780 #define MEM_DOWN_EVAL_SHIFT 2 2781 #define MEM_SW_CMD_MASK 0x0003 2782 #define MEM_INT_STEER_GFX 0 2783 #define MEM_INT_STEER_CMR 1 2784 #define MEM_INT_STEER_SMI 2 2785 #define MEM_INT_STEER_SCI 3 2786 #define MEMINTRSTS _MMIO(0x11184) 2787 #define MEMINT_RSEXIT (1<<7) 2788 #define MEMINT_CONT_BUSY (1<<6) 2789 #define MEMINT_AVG_BUSY (1<<5) 2790 #define MEMINT_EVAL_CHG (1<<4) 2791 #define MEMINT_MON_IDLE (1<<3) 2792 #define MEMINT_UP_EVAL (1<<2) 2793 #define MEMINT_DOWN_EVAL (1<<1) 2794 #define MEMINT_SW_CMD (1<<0) 2795 #define MEMMODECTL _MMIO(0x11190) 2796 #define MEMMODE_BOOST_EN (1<<31) 2797 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ 2798 #define MEMMODE_BOOST_FREQ_SHIFT 24 2799 #define MEMMODE_IDLE_MODE_MASK 0x00030000 2800 #define MEMMODE_IDLE_MODE_SHIFT 16 2801 #define MEMMODE_IDLE_MODE_EVAL 0 2802 #define MEMMODE_IDLE_MODE_CONT 1 2803 #define MEMMODE_HWIDLE_EN (1<<15) 2804 #define MEMMODE_SWMODE_EN (1<<14) 2805 #define MEMMODE_RCLK_GATE (1<<13) 2806 #define MEMMODE_HW_UPDATE (1<<12) 2807 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ 2808 #define MEMMODE_FSTART_SHIFT 8 2809 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ 2810 #define MEMMODE_FMAX_SHIFT 4 2811 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ 2812 #define RCBMAXAVG _MMIO(0x1119c) 2813 #define MEMSWCTL2 _MMIO(0x1119e) /* Cantiga only */ 2814 #define SWMEMCMD_RENDER_OFF (0 << 13) 2815 #define SWMEMCMD_RENDER_ON (1 << 13) 2816 #define SWMEMCMD_SWFREQ (2 << 13) 2817 #define SWMEMCMD_TARVID (3 << 13) 2818 #define SWMEMCMD_VRM_OFF (4 << 13) 2819 #define SWMEMCMD_VRM_ON (5 << 13) 2820 #define CMDSTS (1<<12) 2821 #define SFCAVM (1<<11) 2822 #define SWFREQ_MASK 0x0380 /* P0-7 */ 2823 #define SWFREQ_SHIFT 7 2824 #define TARVID_MASK 0x001f 2825 #define MEMSTAT_CTG _MMIO(0x111a0) 2826 #define RCBMINAVG _MMIO(0x111a0) 2827 #define RCUPEI _MMIO(0x111b0) 2828 #define RCDNEI _MMIO(0x111b4) 2829 #define RSTDBYCTL _MMIO(0x111b8) 2830 #define RS1EN (1<<31) 2831 #define RS2EN (1<<30) 2832 #define RS3EN (1<<29) 2833 #define D3RS3EN (1<<28) /* Display D3 imlies RS3 */ 2834 #define SWPROMORSX (1<<27) /* RSx promotion timers ignored */ 2835 #define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */ 2836 #define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */ 2837 #define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */ 2838 #define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */ 2839 #define RSX_STATUS_MASK (7<<20) 2840 #define RSX_STATUS_ON (0<<20) 2841 #define RSX_STATUS_RC1 (1<<20) 2842 #define RSX_STATUS_RC1E (2<<20) 2843 #define RSX_STATUS_RS1 (3<<20) 2844 #define RSX_STATUS_RS2 (4<<20) /* aka rc6 */ 2845 #define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */ 2846 #define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */ 2847 #define RSX_STATUS_RSVD2 (7<<20) 2848 #define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */ 2849 #define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */ 2850 #define JRSC (1<<17) /* rsx coupled to cpu c-state */ 2851 #define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */ 2852 #define RS1CONTSAV_MASK (3<<14) 2853 #define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */ 2854 #define RS1CONTSAV_RSVD (1<<14) 2855 #define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */ 2856 #define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */ 2857 #define NORMSLEXLAT_MASK (3<<12) 2858 #define SLOW_RS123 (0<<12) 2859 #define SLOW_RS23 (1<<12) 2860 #define SLOW_RS3 (2<<12) 2861 #define NORMAL_RS123 (3<<12) 2862 #define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */ 2863 #define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */ 2864 #define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */ 2865 #define STATELOCK (1<<7) /* locked to rs_cstate if 0 */ 2866 #define RS_CSTATE_MASK (3<<4) 2867 #define RS_CSTATE_C367_RS1 (0<<4) 2868 #define RS_CSTATE_C36_RS1_C7_RS2 (1<<4) 2869 #define RS_CSTATE_RSVD (2<<4) 2870 #define RS_CSTATE_C367_RS2 (3<<4) 2871 #define REDSAVES (1<<3) /* no context save if was idle during rs0 */ 2872 #define REDRESTORES (1<<2) /* no restore if was idle during rs0 */ 2873 #define VIDCTL _MMIO(0x111c0) 2874 #define VIDSTS _MMIO(0x111c8) 2875 #define VIDSTART _MMIO(0x111cc) /* 8 bits */ 2876 #define MEMSTAT_ILK _MMIO(0x111f8) 2877 #define MEMSTAT_VID_MASK 0x7f00 2878 #define MEMSTAT_VID_SHIFT 8 2879 #define MEMSTAT_PSTATE_MASK 0x00f8 2880 #define MEMSTAT_PSTATE_SHIFT 3 2881 #define MEMSTAT_MON_ACTV (1<<2) 2882 #define MEMSTAT_SRC_CTL_MASK 0x0003 2883 #define MEMSTAT_SRC_CTL_CORE 0 2884 #define MEMSTAT_SRC_CTL_TRB 1 2885 #define MEMSTAT_SRC_CTL_THM 2 2886 #define MEMSTAT_SRC_CTL_STDBY 3 2887 #define RCPREVBSYTUPAVG _MMIO(0x113b8) 2888 #define RCPREVBSYTDNAVG _MMIO(0x113bc) 2889 #define PMMISC _MMIO(0x11214) 2890 #define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */ 2891 #define SDEW _MMIO(0x1124c) 2892 #define CSIEW0 _MMIO(0x11250) 2893 #define CSIEW1 _MMIO(0x11254) 2894 #define CSIEW2 _MMIO(0x11258) 2895 #define PEW(i) _MMIO(0x1125c + (i) * 4) /* 5 registers */ 2896 #define DEW(i) _MMIO(0x11270 + (i) * 4) /* 3 registers */ 2897 #define MCHAFE _MMIO(0x112c0) 2898 #define CSIEC _MMIO(0x112e0) 2899 #define DMIEC _MMIO(0x112e4) 2900 #define DDREC _MMIO(0x112e8) 2901 #define PEG0EC _MMIO(0x112ec) 2902 #define PEG1EC _MMIO(0x112f0) 2903 #define GFXEC _MMIO(0x112f4) 2904 #define RPPREVBSYTUPAVG _MMIO(0x113b8) 2905 #define RPPREVBSYTDNAVG _MMIO(0x113bc) 2906 #define ECR _MMIO(0x11600) 2907 #define ECR_GPFE (1<<31) 2908 #define ECR_IMONE (1<<30) 2909 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */ 2910 #define OGW0 _MMIO(0x11608) 2911 #define OGW1 _MMIO(0x1160c) 2912 #define EG0 _MMIO(0x11610) 2913 #define EG1 _MMIO(0x11614) 2914 #define EG2 _MMIO(0x11618) 2915 #define EG3 _MMIO(0x1161c) 2916 #define EG4 _MMIO(0x11620) 2917 #define EG5 _MMIO(0x11624) 2918 #define EG6 _MMIO(0x11628) 2919 #define EG7 _MMIO(0x1162c) 2920 #define PXW(i) _MMIO(0x11664 + (i) * 4) /* 4 registers */ 2921 #define PXWL(i) _MMIO(0x11680 + (i) * 8) /* 8 registers */ 2922 #define LCFUSE02 _MMIO(0x116c0) 2923 #define LCFUSE_HIV_MASK 0x000000ff 2924 #define CSIPLL0 _MMIO(0x12c10) 2925 #define DDRMPLL1 _MMIO(0X12c20) 2926 #define PEG_BAND_GAP_DATA _MMIO(0x14d68) 2927 2928 #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c) 2929 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7 2930 2931 #define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948) 2932 #define BXT_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070) 2933 #define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994) 2934 #define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998) 2935 #define BXT_RP_STATE_CAP _MMIO(0x138170) 2936 2937 #define INTERVAL_1_28_US(us) (((us) * 100) >> 7) 2938 #define INTERVAL_1_33_US(us) (((us) * 3) >> 2) 2939 #define INTERVAL_0_833_US(us) (((us) * 6) / 5) 2940 #define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \ 2941 (IS_BROXTON(dev_priv) ? \ 2942 INTERVAL_0_833_US(us) : \ 2943 INTERVAL_1_33_US(us)) : \ 2944 INTERVAL_1_28_US(us)) 2945 2946 /* 2947 * Logical Context regs 2948 */ 2949 #define CCID _MMIO(0x2180) 2950 #define CCID_EN (1<<0) 2951 /* 2952 * Notes on SNB/IVB/VLV context size: 2953 * - Power context is saved elsewhere (LLC or stolen) 2954 * - Ring/execlist context is saved on SNB, not on IVB 2955 * - Extended context size already includes render context size 2956 * - We always need to follow the extended context size. 2957 * SNB BSpec has comments indicating that we should use the 2958 * render context size instead if execlists are disabled, but 2959 * based on empirical testing that's just nonsense. 2960 * - Pipelined/VF state is saved on SNB/IVB respectively 2961 * - GT1 size just indicates how much of render context 2962 * doesn't need saving on GT1 2963 */ 2964 #define CXT_SIZE _MMIO(0x21a0) 2965 #define GEN6_CXT_POWER_SIZE(cxt_reg) (((cxt_reg) >> 24) & 0x3f) 2966 #define GEN6_CXT_RING_SIZE(cxt_reg) (((cxt_reg) >> 18) & 0x3f) 2967 #define GEN6_CXT_RENDER_SIZE(cxt_reg) (((cxt_reg) >> 12) & 0x3f) 2968 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) (((cxt_reg) >> 6) & 0x3f) 2969 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) (((cxt_reg) >> 0) & 0x3f) 2970 #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \ 2971 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \ 2972 GEN6_CXT_PIPELINE_SIZE(cxt_reg)) 2973 #define GEN7_CXT_SIZE _MMIO(0x21a8) 2974 #define GEN7_CXT_POWER_SIZE(ctx_reg) (((ctx_reg) >> 25) & 0x7f) 2975 #define GEN7_CXT_RING_SIZE(ctx_reg) (((ctx_reg) >> 22) & 0x7) 2976 #define GEN7_CXT_RENDER_SIZE(ctx_reg) (((ctx_reg) >> 16) & 0x3f) 2977 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) (((ctx_reg) >> 9) & 0x7f) 2978 #define GEN7_CXT_GT1_SIZE(ctx_reg) (((ctx_reg) >> 6) & 0x7) 2979 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) (((ctx_reg) >> 0) & 0x3f) 2980 #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \ 2981 GEN7_CXT_VFSTATE_SIZE(ctx_reg)) 2982 /* Haswell does have the CXT_SIZE register however it does not appear to be 2983 * valid. Now, docs explain in dwords what is in the context object. The full 2984 * size is 70720 bytes, however, the power context and execlist context will 2985 * never be saved (power context is stored elsewhere, and execlists don't work 2986 * on HSW) - so the final size, including the extra state required for the 2987 * Resource Streamer, is 66944 bytes, which rounds to 17 pages. 2988 */ 2989 #define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE) 2990 /* Same as Haswell, but 72064 bytes now. */ 2991 #define GEN8_CXT_TOTAL_SIZE (18 * PAGE_SIZE) 2992 2993 #define CHV_CLK_CTL1 _MMIO(0x101100) 2994 #define VLV_CLK_CTL2 _MMIO(0x101104) 2995 #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28 2996 2997 /* 2998 * Overlay regs 2999 */ 3000 3001 #define OVADD _MMIO(0x30000) 3002 #define DOVSTA _MMIO(0x30008) 3003 #define OC_BUF (0x3<<20) 3004 #define OGAMC5 _MMIO(0x30010) 3005 #define OGAMC4 _MMIO(0x30014) 3006 #define OGAMC3 _MMIO(0x30018) 3007 #define OGAMC2 _MMIO(0x3001c) 3008 #define OGAMC1 _MMIO(0x30020) 3009 #define OGAMC0 _MMIO(0x30024) 3010 3011 /* 3012 * GEN9 clock gating regs 3013 */ 3014 #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530) 3015 #define PWM2_GATING_DIS (1 << 14) 3016 #define PWM1_GATING_DIS (1 << 13) 3017 3018 /* 3019 * Display engine regs 3020 */ 3021 3022 /* Pipe A CRC regs */ 3023 #define _PIPE_CRC_CTL_A 0x60050 3024 #define PIPE_CRC_ENABLE (1 << 31) 3025 /* ivb+ source selection */ 3026 #define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29) 3027 #define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29) 3028 #define PIPE_CRC_SOURCE_PF_IVB (2 << 29) 3029 /* ilk+ source selection */ 3030 #define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28) 3031 #define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28) 3032 #define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28) 3033 /* embedded DP port on the north display block, reserved on ivb */ 3034 #define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28) 3035 #define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */ 3036 /* vlv source selection */ 3037 #define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27) 3038 #define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27) 3039 #define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27) 3040 /* with DP port the pipe source is invalid */ 3041 #define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27) 3042 #define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27) 3043 #define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27) 3044 /* gen3+ source selection */ 3045 #define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28) 3046 #define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28) 3047 #define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28) 3048 /* with DP/TV port the pipe source is invalid */ 3049 #define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28) 3050 #define PIPE_CRC_SOURCE_TV_PRE (4 << 28) 3051 #define PIPE_CRC_SOURCE_TV_POST (5 << 28) 3052 #define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28) 3053 #define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28) 3054 /* gen2 doesn't have source selection bits */ 3055 #define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30) 3056 3057 #define _PIPE_CRC_RES_1_A_IVB 0x60064 3058 #define _PIPE_CRC_RES_2_A_IVB 0x60068 3059 #define _PIPE_CRC_RES_3_A_IVB 0x6006c 3060 #define _PIPE_CRC_RES_4_A_IVB 0x60070 3061 #define _PIPE_CRC_RES_5_A_IVB 0x60074 3062 3063 #define _PIPE_CRC_RES_RED_A 0x60060 3064 #define _PIPE_CRC_RES_GREEN_A 0x60064 3065 #define _PIPE_CRC_RES_BLUE_A 0x60068 3066 #define _PIPE_CRC_RES_RES1_A_I915 0x6006c 3067 #define _PIPE_CRC_RES_RES2_A_G4X 0x60080 3068 3069 /* Pipe B CRC regs */ 3070 #define _PIPE_CRC_RES_1_B_IVB 0x61064 3071 #define _PIPE_CRC_RES_2_B_IVB 0x61068 3072 #define _PIPE_CRC_RES_3_B_IVB 0x6106c 3073 #define _PIPE_CRC_RES_4_B_IVB 0x61070 3074 #define _PIPE_CRC_RES_5_B_IVB 0x61074 3075 3076 #define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A) 3077 #define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB) 3078 #define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB) 3079 #define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB) 3080 #define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB) 3081 #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB) 3082 3083 #define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A) 3084 #define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A) 3085 #define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A) 3086 #define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915) 3087 #define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X) 3088 3089 /* Pipe A timing regs */ 3090 #define _HTOTAL_A 0x60000 3091 #define _HBLANK_A 0x60004 3092 #define _HSYNC_A 0x60008 3093 #define _VTOTAL_A 0x6000c 3094 #define _VBLANK_A 0x60010 3095 #define _VSYNC_A 0x60014 3096 #define _PIPEASRC 0x6001c 3097 #define _BCLRPAT_A 0x60020 3098 #define _VSYNCSHIFT_A 0x60028 3099 #define _PIPE_MULT_A 0x6002c 3100 3101 /* Pipe B timing regs */ 3102 #define _HTOTAL_B 0x61000 3103 #define _HBLANK_B 0x61004 3104 #define _HSYNC_B 0x61008 3105 #define _VTOTAL_B 0x6100c 3106 #define _VBLANK_B 0x61010 3107 #define _VSYNC_B 0x61014 3108 #define _PIPEBSRC 0x6101c 3109 #define _BCLRPAT_B 0x61020 3110 #define _VSYNCSHIFT_B 0x61028 3111 #define _PIPE_MULT_B 0x6102c 3112 3113 #define TRANSCODER_A_OFFSET 0x60000 3114 #define TRANSCODER_B_OFFSET 0x61000 3115 #define TRANSCODER_C_OFFSET 0x62000 3116 #define CHV_TRANSCODER_C_OFFSET 0x63000 3117 #define TRANSCODER_EDP_OFFSET 0x6f000 3118 3119 #define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \ 3120 dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \ 3121 dev_priv->info.display_mmio_offset) 3122 3123 #define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A) 3124 #define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A) 3125 #define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A) 3126 #define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A) 3127 #define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A) 3128 #define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A) 3129 #define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A) 3130 #define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A) 3131 #define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC) 3132 #define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A) 3133 3134 /* VLV eDP PSR registers */ 3135 #define _PSRCTLA (VLV_DISPLAY_BASE + 0x60090) 3136 #define _PSRCTLB (VLV_DISPLAY_BASE + 0x61090) 3137 #define VLV_EDP_PSR_ENABLE (1<<0) 3138 #define VLV_EDP_PSR_RESET (1<<1) 3139 #define VLV_EDP_PSR_MODE_MASK (7<<2) 3140 #define VLV_EDP_PSR_MODE_HW_TIMER (1<<3) 3141 #define VLV_EDP_PSR_MODE_SW_TIMER (1<<2) 3142 #define VLV_EDP_PSR_SINGLE_FRAME_UPDATE (1<<7) 3143 #define VLV_EDP_PSR_ACTIVE_ENTRY (1<<8) 3144 #define VLV_EDP_PSR_SRC_TRANSMITTER_STATE (1<<9) 3145 #define VLV_EDP_PSR_DBL_FRAME (1<<10) 3146 #define VLV_EDP_PSR_FRAME_COUNT_MASK (0xff<<16) 3147 #define VLV_EDP_PSR_IDLE_FRAME_SHIFT 16 3148 #define VLV_PSRCTL(pipe) _MMIO_PIPE(pipe, _PSRCTLA, _PSRCTLB) 3149 3150 #define _VSCSDPA (VLV_DISPLAY_BASE + 0x600a0) 3151 #define _VSCSDPB (VLV_DISPLAY_BASE + 0x610a0) 3152 #define VLV_EDP_PSR_SDP_FREQ_MASK (3<<30) 3153 #define VLV_EDP_PSR_SDP_FREQ_ONCE (1<<31) 3154 #define VLV_EDP_PSR_SDP_FREQ_EVFRAME (1<<30) 3155 #define VLV_VSCSDP(pipe) _MMIO_PIPE(pipe, _VSCSDPA, _VSCSDPB) 3156 3157 #define _PSRSTATA (VLV_DISPLAY_BASE + 0x60094) 3158 #define _PSRSTATB (VLV_DISPLAY_BASE + 0x61094) 3159 #define VLV_EDP_PSR_LAST_STATE_MASK (7<<3) 3160 #define VLV_EDP_PSR_CURR_STATE_MASK 7 3161 #define VLV_EDP_PSR_DISABLED (0<<0) 3162 #define VLV_EDP_PSR_INACTIVE (1<<0) 3163 #define VLV_EDP_PSR_IN_TRANS_TO_ACTIVE (2<<0) 3164 #define VLV_EDP_PSR_ACTIVE_NORFB_UP (3<<0) 3165 #define VLV_EDP_PSR_ACTIVE_SF_UPDATE (4<<0) 3166 #define VLV_EDP_PSR_EXIT (5<<0) 3167 #define VLV_EDP_PSR_IN_TRANS (1<<7) 3168 #define VLV_PSRSTAT(pipe) _MMIO_PIPE(pipe, _PSRSTATA, _PSRSTATB) 3169 3170 /* HSW+ eDP PSR registers */ 3171 #define HSW_EDP_PSR_BASE 0x64800 3172 #define BDW_EDP_PSR_BASE 0x6f800 3173 #define EDP_PSR_CTL _MMIO(dev_priv->psr_mmio_base + 0) 3174 #define EDP_PSR_ENABLE (1<<31) 3175 #define BDW_PSR_SINGLE_FRAME (1<<30) 3176 #define EDP_PSR_LINK_STANDBY (1<<27) 3177 #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25) 3178 #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25) 3179 #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25) 3180 #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25) 3181 #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25) 3182 #define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20 3183 #define EDP_PSR_SKIP_AUX_EXIT (1<<12) 3184 #define EDP_PSR_TP1_TP2_SEL (0<<11) 3185 #define EDP_PSR_TP1_TP3_SEL (1<<11) 3186 #define EDP_PSR_TP2_TP3_TIME_500us (0<<8) 3187 #define EDP_PSR_TP2_TP3_TIME_100us (1<<8) 3188 #define EDP_PSR_TP2_TP3_TIME_2500us (2<<8) 3189 #define EDP_PSR_TP2_TP3_TIME_0us (3<<8) 3190 #define EDP_PSR_TP1_TIME_500us (0<<4) 3191 #define EDP_PSR_TP1_TIME_100us (1<<4) 3192 #define EDP_PSR_TP1_TIME_2500us (2<<4) 3193 #define EDP_PSR_TP1_TIME_0us (3<<4) 3194 #define EDP_PSR_IDLE_FRAME_SHIFT 0 3195 3196 #define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr_mmio_base + 0x10) 3197 #define EDP_PSR_AUX_DATA(i) _MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */ 3198 3199 #define EDP_PSR_STATUS_CTL _MMIO(dev_priv->psr_mmio_base + 0x40) 3200 #define EDP_PSR_STATUS_STATE_MASK (7<<29) 3201 #define EDP_PSR_STATUS_STATE_IDLE (0<<29) 3202 #define EDP_PSR_STATUS_STATE_SRDONACK (1<<29) 3203 #define EDP_PSR_STATUS_STATE_SRDENT (2<<29) 3204 #define EDP_PSR_STATUS_STATE_BUFOFF (3<<29) 3205 #define EDP_PSR_STATUS_STATE_BUFON (4<<29) 3206 #define EDP_PSR_STATUS_STATE_AUXACK (5<<29) 3207 #define EDP_PSR_STATUS_STATE_SRDOFFACK (6<<29) 3208 #define EDP_PSR_STATUS_LINK_MASK (3<<26) 3209 #define EDP_PSR_STATUS_LINK_FULL_OFF (0<<26) 3210 #define EDP_PSR_STATUS_LINK_FULL_ON (1<<26) 3211 #define EDP_PSR_STATUS_LINK_STANDBY (2<<26) 3212 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20 3213 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f 3214 #define EDP_PSR_STATUS_COUNT_SHIFT 16 3215 #define EDP_PSR_STATUS_COUNT_MASK 0xf 3216 #define EDP_PSR_STATUS_AUX_ERROR (1<<15) 3217 #define EDP_PSR_STATUS_AUX_SENDING (1<<12) 3218 #define EDP_PSR_STATUS_SENDING_IDLE (1<<9) 3219 #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8) 3220 #define EDP_PSR_STATUS_SENDING_TP1 (1<<4) 3221 #define EDP_PSR_STATUS_IDLE_MASK 0xf 3222 3223 #define EDP_PSR_PERF_CNT _MMIO(dev_priv->psr_mmio_base + 0x44) 3224 #define EDP_PSR_PERF_CNT_MASK 0xffffff 3225 3226 #define EDP_PSR_DEBUG_CTL _MMIO(dev_priv->psr_mmio_base + 0x60) 3227 #define EDP_PSR_DEBUG_MASK_LPSP (1<<27) 3228 #define EDP_PSR_DEBUG_MASK_MEMUP (1<<26) 3229 #define EDP_PSR_DEBUG_MASK_HPD (1<<25) 3230 3231 #define EDP_PSR2_CTL _MMIO(0x6f900) 3232 #define EDP_PSR2_ENABLE (1<<31) 3233 #define EDP_SU_TRACK_ENABLE (1<<30) 3234 #define EDP_MAX_SU_DISABLE_TIME(t) ((t)<<20) 3235 #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f<<20) 3236 #define EDP_PSR2_TP2_TIME_500 (0<<8) 3237 #define EDP_PSR2_TP2_TIME_100 (1<<8) 3238 #define EDP_PSR2_TP2_TIME_2500 (2<<8) 3239 #define EDP_PSR2_TP2_TIME_50 (3<<8) 3240 #define EDP_PSR2_TP2_TIME_MASK (3<<8) 3241 #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 3242 #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4) 3243 #define EDP_PSR2_IDLE_MASK 0xf 3244 3245 /* VGA port control */ 3246 #define ADPA _MMIO(0x61100) 3247 #define PCH_ADPA _MMIO(0xe1100) 3248 #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100) 3249 3250 #define ADPA_DAC_ENABLE (1<<31) 3251 #define ADPA_DAC_DISABLE 0 3252 #define ADPA_PIPE_SELECT_MASK (1<<30) 3253 #define ADPA_PIPE_A_SELECT 0 3254 #define ADPA_PIPE_B_SELECT (1<<30) 3255 #define ADPA_PIPE_SELECT(pipe) ((pipe) << 30) 3256 /* CPT uses bits 29:30 for pch transcoder select */ 3257 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ 3258 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24) 3259 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24) 3260 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24) 3261 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24) 3262 #define ADPA_CRT_HOTPLUG_ENABLE (1<<23) 3263 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) 3264 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) 3265 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) 3266 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) 3267 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) 3268 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) 3269 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) 3270 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) 3271 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) 3272 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) 3273 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17) 3274 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17) 3275 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16) 3276 #define ADPA_USE_VGA_HVPOLARITY (1<<15) 3277 #define ADPA_SETS_HVPOLARITY 0 3278 #define ADPA_VSYNC_CNTL_DISABLE (1<<10) 3279 #define ADPA_VSYNC_CNTL_ENABLE 0 3280 #define ADPA_HSYNC_CNTL_DISABLE (1<<11) 3281 #define ADPA_HSYNC_CNTL_ENABLE 0 3282 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4) 3283 #define ADPA_VSYNC_ACTIVE_LOW 0 3284 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3) 3285 #define ADPA_HSYNC_ACTIVE_LOW 0 3286 #define ADPA_DPMS_MASK (~(3<<10)) 3287 #define ADPA_DPMS_ON (0<<10) 3288 #define ADPA_DPMS_SUSPEND (1<<10) 3289 #define ADPA_DPMS_STANDBY (2<<10) 3290 #define ADPA_DPMS_OFF (3<<10) 3291 3292 3293 /* Hotplug control (945+ only) */ 3294 #define PORT_HOTPLUG_EN _MMIO(dev_priv->info.display_mmio_offset + 0x61110) 3295 #define PORTB_HOTPLUG_INT_EN (1 << 29) 3296 #define PORTC_HOTPLUG_INT_EN (1 << 28) 3297 #define PORTD_HOTPLUG_INT_EN (1 << 27) 3298 #define SDVOB_HOTPLUG_INT_EN (1 << 26) 3299 #define SDVOC_HOTPLUG_INT_EN (1 << 25) 3300 #define TV_HOTPLUG_INT_EN (1 << 18) 3301 #define CRT_HOTPLUG_INT_EN (1 << 9) 3302 #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \ 3303 PORTC_HOTPLUG_INT_EN | \ 3304 PORTD_HOTPLUG_INT_EN | \ 3305 SDVOC_HOTPLUG_INT_EN | \ 3306 SDVOB_HOTPLUG_INT_EN | \ 3307 CRT_HOTPLUG_INT_EN) 3308 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 3309 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) 3310 /* must use period 64 on GM45 according to docs */ 3311 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) 3312 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) 3313 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) 3314 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) 3315 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) 3316 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) 3317 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) 3318 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) 3319 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) 3320 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) 3321 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) 3322 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 3323 3324 #define PORT_HOTPLUG_STAT _MMIO(dev_priv->info.display_mmio_offset + 0x61114) 3325 /* 3326 * HDMI/DP bits are g4x+ 3327 * 3328 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused. 3329 * Please check the detailed lore in the commit message for for experimental 3330 * evidence. 3331 */ 3332 /* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */ 3333 #define PORTD_HOTPLUG_LIVE_STATUS_GM45 (1 << 29) 3334 #define PORTC_HOTPLUG_LIVE_STATUS_GM45 (1 << 28) 3335 #define PORTB_HOTPLUG_LIVE_STATUS_GM45 (1 << 27) 3336 /* G4X/VLV/CHV DP/HDMI bits again match Bspec */ 3337 #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27) 3338 #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28) 3339 #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29) 3340 #define PORTD_HOTPLUG_INT_STATUS (3 << 21) 3341 #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21) 3342 #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21) 3343 #define PORTC_HOTPLUG_INT_STATUS (3 << 19) 3344 #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19) 3345 #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19) 3346 #define PORTB_HOTPLUG_INT_STATUS (3 << 17) 3347 #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17) 3348 #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17) 3349 /* CRT/TV common between gen3+ */ 3350 #define CRT_HOTPLUG_INT_STATUS (1 << 11) 3351 #define TV_HOTPLUG_INT_STATUS (1 << 10) 3352 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 3353 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 3354 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 3355 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 3356 #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6) 3357 #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5) 3358 #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4) 3359 #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4) 3360 3361 /* SDVO is different across gen3/4 */ 3362 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) 3363 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) 3364 /* 3365 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm, 3366 * since reality corrobates that they're the same as on gen3. But keep these 3367 * bits here (and the comment!) to help any other lost wanderers back onto the 3368 * right tracks. 3369 */ 3370 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4) 3371 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) 3372 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) 3373 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) 3374 #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \ 3375 SDVOB_HOTPLUG_INT_STATUS_G4X | \ 3376 SDVOC_HOTPLUG_INT_STATUS_G4X | \ 3377 PORTB_HOTPLUG_INT_STATUS | \ 3378 PORTC_HOTPLUG_INT_STATUS | \ 3379 PORTD_HOTPLUG_INT_STATUS) 3380 3381 #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \ 3382 SDVOB_HOTPLUG_INT_STATUS_I915 | \ 3383 SDVOC_HOTPLUG_INT_STATUS_I915 | \ 3384 PORTB_HOTPLUG_INT_STATUS | \ 3385 PORTC_HOTPLUG_INT_STATUS | \ 3386 PORTD_HOTPLUG_INT_STATUS) 3387 3388 /* SDVO and HDMI port control. 3389 * The same register may be used for SDVO or HDMI */ 3390 #define _GEN3_SDVOB 0x61140 3391 #define _GEN3_SDVOC 0x61160 3392 #define GEN3_SDVOB _MMIO(_GEN3_SDVOB) 3393 #define GEN3_SDVOC _MMIO(_GEN3_SDVOC) 3394 #define GEN4_HDMIB GEN3_SDVOB 3395 #define GEN4_HDMIC GEN3_SDVOC 3396 #define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140) 3397 #define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160) 3398 #define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C) 3399 #define PCH_SDVOB _MMIO(0xe1140) 3400 #define PCH_HDMIB PCH_SDVOB 3401 #define PCH_HDMIC _MMIO(0xe1150) 3402 #define PCH_HDMID _MMIO(0xe1160) 3403 3404 #define PORT_DFT_I9XX _MMIO(0x61150) 3405 #define DC_BALANCE_RESET (1 << 25) 3406 #define PORT_DFT2_G4X _MMIO(dev_priv->info.display_mmio_offset + 0x61154) 3407 #define DC_BALANCE_RESET_VLV (1 << 31) 3408 #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0)) 3409 #define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */ 3410 #define PIPE_B_SCRAMBLE_RESET (1 << 1) 3411 #define PIPE_A_SCRAMBLE_RESET (1 << 0) 3412 3413 /* Gen 3 SDVO bits: */ 3414 #define SDVO_ENABLE (1 << 31) 3415 #define SDVO_PIPE_SEL(pipe) ((pipe) << 30) 3416 #define SDVO_PIPE_SEL_MASK (1 << 30) 3417 #define SDVO_PIPE_B_SELECT (1 << 30) 3418 #define SDVO_STALL_SELECT (1 << 29) 3419 #define SDVO_INTERRUPT_ENABLE (1 << 26) 3420 /* 3421 * 915G/GM SDVO pixel multiplier. 3422 * Programmed value is multiplier - 1, up to 5x. 3423 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 3424 */ 3425 #define SDVO_PORT_MULTIPLY_MASK (7 << 23) 3426 #define SDVO_PORT_MULTIPLY_SHIFT 23 3427 #define SDVO_PHASE_SELECT_MASK (15 << 19) 3428 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 3429 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 3430 #define SDVOC_GANG_MODE (1 << 16) /* Port C only */ 3431 #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */ 3432 #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */ 3433 #define SDVO_DETECTED (1 << 2) 3434 /* Bits to be preserved when writing */ 3435 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \ 3436 SDVO_INTERRUPT_ENABLE) 3437 #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE) 3438 3439 /* Gen 4 SDVO/HDMI bits: */ 3440 #define SDVO_COLOR_FORMAT_8bpc (0 << 26) 3441 #define SDVO_COLOR_FORMAT_MASK (7 << 26) 3442 #define SDVO_ENCODING_SDVO (0 << 10) 3443 #define SDVO_ENCODING_HDMI (2 << 10) 3444 #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */ 3445 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */ 3446 #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */ 3447 #define SDVO_AUDIO_ENABLE (1 << 6) 3448 /* VSYNC/HSYNC bits new with 965, default is to be set */ 3449 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) 3450 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) 3451 3452 /* Gen 5 (IBX) SDVO/HDMI bits: */ 3453 #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */ 3454 #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */ 3455 3456 /* Gen 6 (CPT) SDVO/HDMI bits: */ 3457 #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29) 3458 #define SDVO_PIPE_SEL_MASK_CPT (3 << 29) 3459 3460 /* CHV SDVO/HDMI bits: */ 3461 #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24) 3462 #define SDVO_PIPE_SEL_MASK_CHV (3 << 24) 3463 3464 3465 /* DVO port control */ 3466 #define _DVOA 0x61120 3467 #define DVOA _MMIO(_DVOA) 3468 #define _DVOB 0x61140 3469 #define DVOB _MMIO(_DVOB) 3470 #define _DVOC 0x61160 3471 #define DVOC _MMIO(_DVOC) 3472 #define DVO_ENABLE (1 << 31) 3473 #define DVO_PIPE_B_SELECT (1 << 30) 3474 #define DVO_PIPE_STALL_UNUSED (0 << 28) 3475 #define DVO_PIPE_STALL (1 << 28) 3476 #define DVO_PIPE_STALL_TV (2 << 28) 3477 #define DVO_PIPE_STALL_MASK (3 << 28) 3478 #define DVO_USE_VGA_SYNC (1 << 15) 3479 #define DVO_DATA_ORDER_I740 (0 << 14) 3480 #define DVO_DATA_ORDER_FP (1 << 14) 3481 #define DVO_VSYNC_DISABLE (1 << 11) 3482 #define DVO_HSYNC_DISABLE (1 << 10) 3483 #define DVO_VSYNC_TRISTATE (1 << 9) 3484 #define DVO_HSYNC_TRISTATE (1 << 8) 3485 #define DVO_BORDER_ENABLE (1 << 7) 3486 #define DVO_DATA_ORDER_GBRG (1 << 6) 3487 #define DVO_DATA_ORDER_RGGB (0 << 6) 3488 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) 3489 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) 3490 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4) 3491 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3) 3492 #define DVO_BLANK_ACTIVE_HIGH (1 << 2) 3493 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ 3494 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ 3495 #define DVO_PRESERVE_MASK (0x7<<24) 3496 #define DVOA_SRCDIM _MMIO(0x61124) 3497 #define DVOB_SRCDIM _MMIO(0x61144) 3498 #define DVOC_SRCDIM _MMIO(0x61164) 3499 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12 3500 #define DVO_SRCDIM_VERTICAL_SHIFT 0 3501 3502 /* LVDS port control */ 3503 #define LVDS _MMIO(0x61180) 3504 /* 3505 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 3506 * the DPLL semantics change when the LVDS is assigned to that pipe. 3507 */ 3508 #define LVDS_PORT_EN (1 << 31) 3509 /* Selects pipe B for LVDS data. Must be set on pre-965. */ 3510 #define LVDS_PIPEB_SELECT (1 << 30) 3511 #define LVDS_PIPE_MASK (1 << 30) 3512 #define LVDS_PIPE(pipe) ((pipe) << 30) 3513 /* LVDS dithering flag on 965/g4x platform */ 3514 #define LVDS_ENABLE_DITHER (1 << 25) 3515 /* LVDS sync polarity flags. Set to invert (i.e. negative) */ 3516 #define LVDS_VSYNC_POLARITY (1 << 21) 3517 #define LVDS_HSYNC_POLARITY (1 << 20) 3518 3519 /* Enable border for unscaled (or aspect-scaled) display */ 3520 #define LVDS_BORDER_ENABLE (1 << 15) 3521 /* 3522 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 3523 * pixel. 3524 */ 3525 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) 3526 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) 3527 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 3528 /* 3529 * Controls the A3 data pair, which contains the additional LSBs for 24 bit 3530 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be 3531 * on. 3532 */ 3533 #define LVDS_A3_POWER_MASK (3 << 6) 3534 #define LVDS_A3_POWER_DOWN (0 << 6) 3535 #define LVDS_A3_POWER_UP (3 << 6) 3536 /* 3537 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP 3538 * is set. 3539 */ 3540 #define LVDS_CLKB_POWER_MASK (3 << 4) 3541 #define LVDS_CLKB_POWER_DOWN (0 << 4) 3542 #define LVDS_CLKB_POWER_UP (3 << 4) 3543 /* 3544 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 3545 * setting for whether we are in dual-channel mode. The B3 pair will 3546 * additionally only be powered up when LVDS_A3_POWER_UP is set. 3547 */ 3548 #define LVDS_B0B3_POWER_MASK (3 << 2) 3549 #define LVDS_B0B3_POWER_DOWN (0 << 2) 3550 #define LVDS_B0B3_POWER_UP (3 << 2) 3551 3552 /* Video Data Island Packet control */ 3553 #define VIDEO_DIP_DATA _MMIO(0x61178) 3554 /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC 3555 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte 3556 * of the infoframe structure specified by CEA-861. */ 3557 #define VIDEO_DIP_DATA_SIZE 32 3558 #define VIDEO_DIP_VSC_DATA_SIZE 36 3559 #define VIDEO_DIP_CTL _MMIO(0x61170) 3560 /* Pre HSW: */ 3561 #define VIDEO_DIP_ENABLE (1 << 31) 3562 #define VIDEO_DIP_PORT(port) ((port) << 29) 3563 #define VIDEO_DIP_PORT_MASK (3 << 29) 3564 #define VIDEO_DIP_ENABLE_GCP (1 << 25) 3565 #define VIDEO_DIP_ENABLE_AVI (1 << 21) 3566 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) 3567 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21) 3568 #define VIDEO_DIP_ENABLE_SPD (8 << 21) 3569 #define VIDEO_DIP_SELECT_AVI (0 << 19) 3570 #define VIDEO_DIP_SELECT_VENDOR (1 << 19) 3571 #define VIDEO_DIP_SELECT_SPD (3 << 19) 3572 #define VIDEO_DIP_SELECT_MASK (3 << 19) 3573 #define VIDEO_DIP_FREQ_ONCE (0 << 16) 3574 #define VIDEO_DIP_FREQ_VSYNC (1 << 16) 3575 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) 3576 #define VIDEO_DIP_FREQ_MASK (3 << 16) 3577 /* HSW and later: */ 3578 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) 3579 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) 3580 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) 3581 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) 3582 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) 3583 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) 3584 3585 /* Panel power sequencing */ 3586 #define PP_STATUS _MMIO(0x61200) 3587 #define PP_ON (1 << 31) 3588 /* 3589 * Indicates that all dependencies of the panel are on: 3590 * 3591 * - PLL enabled 3592 * - pipe enabled 3593 * - LVDS/DVOB/DVOC on 3594 */ 3595 #define PP_READY (1 << 30) 3596 #define PP_SEQUENCE_NONE (0 << 28) 3597 #define PP_SEQUENCE_POWER_UP (1 << 28) 3598 #define PP_SEQUENCE_POWER_DOWN (2 << 28) 3599 #define PP_SEQUENCE_MASK (3 << 28) 3600 #define PP_SEQUENCE_SHIFT 28 3601 #define PP_CYCLE_DELAY_ACTIVE (1 << 27) 3602 #define PP_SEQUENCE_STATE_MASK 0x0000000f 3603 #define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0) 3604 #define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0) 3605 #define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0) 3606 #define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0) 3607 #define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0) 3608 #define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0) 3609 #define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0) 3610 #define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0) 3611 #define PP_SEQUENCE_STATE_RESET (0xf << 0) 3612 #define PP_CONTROL _MMIO(0x61204) 3613 #define POWER_TARGET_ON (1 << 0) 3614 #define PP_ON_DELAYS _MMIO(0x61208) 3615 #define PP_OFF_DELAYS _MMIO(0x6120c) 3616 #define PP_DIVISOR _MMIO(0x61210) 3617 3618 /* Panel fitting */ 3619 #define PFIT_CONTROL _MMIO(dev_priv->info.display_mmio_offset + 0x61230) 3620 #define PFIT_ENABLE (1 << 31) 3621 #define PFIT_PIPE_MASK (3 << 29) 3622 #define PFIT_PIPE_SHIFT 29 3623 #define VERT_INTERP_DISABLE (0 << 10) 3624 #define VERT_INTERP_BILINEAR (1 << 10) 3625 #define VERT_INTERP_MASK (3 << 10) 3626 #define VERT_AUTO_SCALE (1 << 9) 3627 #define HORIZ_INTERP_DISABLE (0 << 6) 3628 #define HORIZ_INTERP_BILINEAR (1 << 6) 3629 #define HORIZ_INTERP_MASK (3 << 6) 3630 #define HORIZ_AUTO_SCALE (1 << 5) 3631 #define PANEL_8TO6_DITHER_ENABLE (1 << 3) 3632 #define PFIT_FILTER_FUZZY (0 << 24) 3633 #define PFIT_SCALING_AUTO (0 << 26) 3634 #define PFIT_SCALING_PROGRAMMED (1 << 26) 3635 #define PFIT_SCALING_PILLAR (2 << 26) 3636 #define PFIT_SCALING_LETTER (3 << 26) 3637 #define PFIT_PGM_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61234) 3638 /* Pre-965 */ 3639 #define PFIT_VERT_SCALE_SHIFT 20 3640 #define PFIT_VERT_SCALE_MASK 0xfff00000 3641 #define PFIT_HORIZ_SCALE_SHIFT 4 3642 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 3643 /* 965+ */ 3644 #define PFIT_VERT_SCALE_SHIFT_965 16 3645 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000 3646 #define PFIT_HORIZ_SCALE_SHIFT_965 0 3647 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff 3648 3649 #define PFIT_AUTO_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61238) 3650 3651 #define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250) 3652 #define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350) 3653 #define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \ 3654 _VLV_BLC_PWM_CTL2_B) 3655 3656 #define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254) 3657 #define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354) 3658 #define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \ 3659 _VLV_BLC_PWM_CTL_B) 3660 3661 #define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260) 3662 #define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360) 3663 #define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \ 3664 _VLV_BLC_HIST_CTL_B) 3665 3666 /* Backlight control */ 3667 #define BLC_PWM_CTL2 _MMIO(dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */ 3668 #define BLM_PWM_ENABLE (1 << 31) 3669 #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */ 3670 #define BLM_PIPE_SELECT (1 << 29) 3671 #define BLM_PIPE_SELECT_IVB (3 << 29) 3672 #define BLM_PIPE_A (0 << 29) 3673 #define BLM_PIPE_B (1 << 29) 3674 #define BLM_PIPE_C (2 << 29) /* ivb + */ 3675 #define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */ 3676 #define BLM_TRANSCODER_B BLM_PIPE_B 3677 #define BLM_TRANSCODER_C BLM_PIPE_C 3678 #define BLM_TRANSCODER_EDP (3 << 29) 3679 #define BLM_PIPE(pipe) ((pipe) << 29) 3680 #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */ 3681 #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26) 3682 #define BLM_PHASE_IN_ENABLE (1 << 25) 3683 #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24) 3684 #define BLM_PHASE_IN_TIME_BASE_SHIFT (16) 3685 #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16) 3686 #define BLM_PHASE_IN_COUNT_SHIFT (8) 3687 #define BLM_PHASE_IN_COUNT_MASK (0xff << 8) 3688 #define BLM_PHASE_IN_INCR_SHIFT (0) 3689 #define BLM_PHASE_IN_INCR_MASK (0xff << 0) 3690 #define BLC_PWM_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61254) 3691 /* 3692 * This is the most significant 15 bits of the number of backlight cycles in a 3693 * complete cycle of the modulated backlight control. 3694 * 3695 * The actual value is this field multiplied by two. 3696 */ 3697 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) 3698 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) 3699 #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */ 3700 /* 3701 * This is the number of cycles out of the backlight modulation cycle for which 3702 * the backlight is on. 3703 * 3704 * This field must be no greater than the number of cycles in the complete 3705 * backlight modulation cycle. 3706 */ 3707 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) 3708 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) 3709 #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe) 3710 #define BLM_POLARITY_PNV (1 << 0) /* pnv only */ 3711 3712 #define BLC_HIST_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61260) 3713 #define BLM_HISTOGRAM_ENABLE (1 << 31) 3714 3715 /* New registers for PCH-split platforms. Safe where new bits show up, the 3716 * register layout machtes with gen4 BLC_PWM_CTL[12]. */ 3717 #define BLC_PWM_CPU_CTL2 _MMIO(0x48250) 3718 #define BLC_PWM_CPU_CTL _MMIO(0x48254) 3719 3720 #define HSW_BLC_PWM2_CTL _MMIO(0x48350) 3721 3722 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is 3723 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */ 3724 #define BLC_PWM_PCH_CTL1 _MMIO(0xc8250) 3725 #define BLM_PCH_PWM_ENABLE (1 << 31) 3726 #define BLM_PCH_OVERRIDE_ENABLE (1 << 30) 3727 #define BLM_PCH_POLARITY (1 << 29) 3728 #define BLC_PWM_PCH_CTL2 _MMIO(0xc8254) 3729 3730 #define UTIL_PIN_CTL _MMIO(0x48400) 3731 #define UTIL_PIN_ENABLE (1 << 31) 3732 3733 #define UTIL_PIN_PIPE(x) ((x) << 29) 3734 #define UTIL_PIN_PIPE_MASK (3 << 29) 3735 #define UTIL_PIN_MODE_PWM (1 << 24) 3736 #define UTIL_PIN_MODE_MASK (0xf << 24) 3737 #define UTIL_PIN_POLARITY (1 << 22) 3738 3739 /* BXT backlight register definition. */ 3740 #define _BXT_BLC_PWM_CTL1 0xC8250 3741 #define BXT_BLC_PWM_ENABLE (1 << 31) 3742 #define BXT_BLC_PWM_POLARITY (1 << 29) 3743 #define _BXT_BLC_PWM_FREQ1 0xC8254 3744 #define _BXT_BLC_PWM_DUTY1 0xC8258 3745 3746 #define _BXT_BLC_PWM_CTL2 0xC8350 3747 #define _BXT_BLC_PWM_FREQ2 0xC8354 3748 #define _BXT_BLC_PWM_DUTY2 0xC8358 3749 3750 #define BXT_BLC_PWM_CTL(controller) _MMIO_PIPE(controller, \ 3751 _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2) 3752 #define BXT_BLC_PWM_FREQ(controller) _MMIO_PIPE(controller, \ 3753 _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2) 3754 #define BXT_BLC_PWM_DUTY(controller) _MMIO_PIPE(controller, \ 3755 _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2) 3756 3757 #define PCH_GTC_CTL _MMIO(0xe7000) 3758 #define PCH_GTC_ENABLE (1 << 31) 3759 3760 /* TV port control */ 3761 #define TV_CTL _MMIO(0x68000) 3762 /* Enables the TV encoder */ 3763 # define TV_ENC_ENABLE (1 << 31) 3764 /* Sources the TV encoder input from pipe B instead of A. */ 3765 # define TV_ENC_PIPEB_SELECT (1 << 30) 3766 /* Outputs composite video (DAC A only) */ 3767 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28) 3768 /* Outputs SVideo video (DAC B/C) */ 3769 # define TV_ENC_OUTPUT_SVIDEO (1 << 28) 3770 /* Outputs Component video (DAC A/B/C) */ 3771 # define TV_ENC_OUTPUT_COMPONENT (2 << 28) 3772 /* Outputs Composite and SVideo (DAC A/B/C) */ 3773 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) 3774 # define TV_TRILEVEL_SYNC (1 << 21) 3775 /* Enables slow sync generation (945GM only) */ 3776 # define TV_SLOW_SYNC (1 << 20) 3777 /* Selects 4x oversampling for 480i and 576p */ 3778 # define TV_OVERSAMPLE_4X (0 << 18) 3779 /* Selects 2x oversampling for 720p and 1080i */ 3780 # define TV_OVERSAMPLE_2X (1 << 18) 3781 /* Selects no oversampling for 1080p */ 3782 # define TV_OVERSAMPLE_NONE (2 << 18) 3783 /* Selects 8x oversampling */ 3784 # define TV_OVERSAMPLE_8X (3 << 18) 3785 /* Selects progressive mode rather than interlaced */ 3786 # define TV_PROGRESSIVE (1 << 17) 3787 /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */ 3788 # define TV_PAL_BURST (1 << 16) 3789 /* Field for setting delay of Y compared to C */ 3790 # define TV_YC_SKEW_MASK (7 << 12) 3791 /* Enables a fix for 480p/576p standard definition modes on the 915GM only */ 3792 # define TV_ENC_SDP_FIX (1 << 11) 3793 /* 3794 * Enables a fix for the 915GM only. 3795 * 3796 * Not sure what it does. 3797 */ 3798 # define TV_ENC_C0_FIX (1 << 10) 3799 /* Bits that must be preserved by software */ 3800 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) 3801 # define TV_FUSE_STATE_MASK (3 << 4) 3802 /* Read-only state that reports all features enabled */ 3803 # define TV_FUSE_STATE_ENABLED (0 << 4) 3804 /* Read-only state that reports that Macrovision is disabled in hardware*/ 3805 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4) 3806 /* Read-only state that reports that TV-out is disabled in hardware. */ 3807 # define TV_FUSE_STATE_DISABLED (2 << 4) 3808 /* Normal operation */ 3809 # define TV_TEST_MODE_NORMAL (0 << 0) 3810 /* Encoder test pattern 1 - combo pattern */ 3811 # define TV_TEST_MODE_PATTERN_1 (1 << 0) 3812 /* Encoder test pattern 2 - full screen vertical 75% color bars */ 3813 # define TV_TEST_MODE_PATTERN_2 (2 << 0) 3814 /* Encoder test pattern 3 - full screen horizontal 75% color bars */ 3815 # define TV_TEST_MODE_PATTERN_3 (3 << 0) 3816 /* Encoder test pattern 4 - random noise */ 3817 # define TV_TEST_MODE_PATTERN_4 (4 << 0) 3818 /* Encoder test pattern 5 - linear color ramps */ 3819 # define TV_TEST_MODE_PATTERN_5 (5 << 0) 3820 /* 3821 * This test mode forces the DACs to 50% of full output. 3822 * 3823 * This is used for load detection in combination with TVDAC_SENSE_MASK 3824 */ 3825 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0) 3826 # define TV_TEST_MODE_MASK (7 << 0) 3827 3828 #define TV_DAC _MMIO(0x68004) 3829 # define TV_DAC_SAVE 0x00ffff00 3830 /* 3831 * Reports that DAC state change logic has reported change (RO). 3832 * 3833 * This gets cleared when TV_DAC_STATE_EN is cleared 3834 */ 3835 # define TVDAC_STATE_CHG (1 << 31) 3836 # define TVDAC_SENSE_MASK (7 << 28) 3837 /* Reports that DAC A voltage is above the detect threshold */ 3838 # define TVDAC_A_SENSE (1 << 30) 3839 /* Reports that DAC B voltage is above the detect threshold */ 3840 # define TVDAC_B_SENSE (1 << 29) 3841 /* Reports that DAC C voltage is above the detect threshold */ 3842 # define TVDAC_C_SENSE (1 << 28) 3843 /* 3844 * Enables DAC state detection logic, for load-based TV detection. 3845 * 3846 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set 3847 * to off, for load detection to work. 3848 */ 3849 # define TVDAC_STATE_CHG_EN (1 << 27) 3850 /* Sets the DAC A sense value to high */ 3851 # define TVDAC_A_SENSE_CTL (1 << 26) 3852 /* Sets the DAC B sense value to high */ 3853 # define TVDAC_B_SENSE_CTL (1 << 25) 3854 /* Sets the DAC C sense value to high */ 3855 # define TVDAC_C_SENSE_CTL (1 << 24) 3856 /* Overrides the ENC_ENABLE and DAC voltage levels */ 3857 # define DAC_CTL_OVERRIDE (1 << 7) 3858 /* Sets the slew rate. Must be preserved in software */ 3859 # define ENC_TVDAC_SLEW_FAST (1 << 6) 3860 # define DAC_A_1_3_V (0 << 4) 3861 # define DAC_A_1_1_V (1 << 4) 3862 # define DAC_A_0_7_V (2 << 4) 3863 # define DAC_A_MASK (3 << 4) 3864 # define DAC_B_1_3_V (0 << 2) 3865 # define DAC_B_1_1_V (1 << 2) 3866 # define DAC_B_0_7_V (2 << 2) 3867 # define DAC_B_MASK (3 << 2) 3868 # define DAC_C_1_3_V (0 << 0) 3869 # define DAC_C_1_1_V (1 << 0) 3870 # define DAC_C_0_7_V (2 << 0) 3871 # define DAC_C_MASK (3 << 0) 3872 3873 /* 3874 * CSC coefficients are stored in a floating point format with 9 bits of 3875 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, 3876 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with 3877 * -1 (0x3) being the only legal negative value. 3878 */ 3879 #define TV_CSC_Y _MMIO(0x68010) 3880 # define TV_RY_MASK 0x07ff0000 3881 # define TV_RY_SHIFT 16 3882 # define TV_GY_MASK 0x00000fff 3883 # define TV_GY_SHIFT 0 3884 3885 #define TV_CSC_Y2 _MMIO(0x68014) 3886 # define TV_BY_MASK 0x07ff0000 3887 # define TV_BY_SHIFT 16 3888 /* 3889 * Y attenuation for component video. 3890 * 3891 * Stored in 1.9 fixed point. 3892 */ 3893 # define TV_AY_MASK 0x000003ff 3894 # define TV_AY_SHIFT 0 3895 3896 #define TV_CSC_U _MMIO(0x68018) 3897 # define TV_RU_MASK 0x07ff0000 3898 # define TV_RU_SHIFT 16 3899 # define TV_GU_MASK 0x000007ff 3900 # define TV_GU_SHIFT 0 3901 3902 #define TV_CSC_U2 _MMIO(0x6801c) 3903 # define TV_BU_MASK 0x07ff0000 3904 # define TV_BU_SHIFT 16 3905 /* 3906 * U attenuation for component video. 3907 * 3908 * Stored in 1.9 fixed point. 3909 */ 3910 # define TV_AU_MASK 0x000003ff 3911 # define TV_AU_SHIFT 0 3912 3913 #define TV_CSC_V _MMIO(0x68020) 3914 # define TV_RV_MASK 0x0fff0000 3915 # define TV_RV_SHIFT 16 3916 # define TV_GV_MASK 0x000007ff 3917 # define TV_GV_SHIFT 0 3918 3919 #define TV_CSC_V2 _MMIO(0x68024) 3920 # define TV_BV_MASK 0x07ff0000 3921 # define TV_BV_SHIFT 16 3922 /* 3923 * V attenuation for component video. 3924 * 3925 * Stored in 1.9 fixed point. 3926 */ 3927 # define TV_AV_MASK 0x000007ff 3928 # define TV_AV_SHIFT 0 3929 3930 #define TV_CLR_KNOBS _MMIO(0x68028) 3931 /* 2s-complement brightness adjustment */ 3932 # define TV_BRIGHTNESS_MASK 0xff000000 3933 # define TV_BRIGHTNESS_SHIFT 24 3934 /* Contrast adjustment, as a 2.6 unsigned floating point number */ 3935 # define TV_CONTRAST_MASK 0x00ff0000 3936 # define TV_CONTRAST_SHIFT 16 3937 /* Saturation adjustment, as a 2.6 unsigned floating point number */ 3938 # define TV_SATURATION_MASK 0x0000ff00 3939 # define TV_SATURATION_SHIFT 8 3940 /* Hue adjustment, as an integer phase angle in degrees */ 3941 # define TV_HUE_MASK 0x000000ff 3942 # define TV_HUE_SHIFT 0 3943 3944 #define TV_CLR_LEVEL _MMIO(0x6802c) 3945 /* Controls the DAC level for black */ 3946 # define TV_BLACK_LEVEL_MASK 0x01ff0000 3947 # define TV_BLACK_LEVEL_SHIFT 16 3948 /* Controls the DAC level for blanking */ 3949 # define TV_BLANK_LEVEL_MASK 0x000001ff 3950 # define TV_BLANK_LEVEL_SHIFT 0 3951 3952 #define TV_H_CTL_1 _MMIO(0x68030) 3953 /* Number of pixels in the hsync. */ 3954 # define TV_HSYNC_END_MASK 0x1fff0000 3955 # define TV_HSYNC_END_SHIFT 16 3956 /* Total number of pixels minus one in the line (display and blanking). */ 3957 # define TV_HTOTAL_MASK 0x00001fff 3958 # define TV_HTOTAL_SHIFT 0 3959 3960 #define TV_H_CTL_2 _MMIO(0x68034) 3961 /* Enables the colorburst (needed for non-component color) */ 3962 # define TV_BURST_ENA (1 << 31) 3963 /* Offset of the colorburst from the start of hsync, in pixels minus one. */ 3964 # define TV_HBURST_START_SHIFT 16 3965 # define TV_HBURST_START_MASK 0x1fff0000 3966 /* Length of the colorburst */ 3967 # define TV_HBURST_LEN_SHIFT 0 3968 # define TV_HBURST_LEN_MASK 0x0001fff 3969 3970 #define TV_H_CTL_3 _MMIO(0x68038) 3971 /* End of hblank, measured in pixels minus one from start of hsync */ 3972 # define TV_HBLANK_END_SHIFT 16 3973 # define TV_HBLANK_END_MASK 0x1fff0000 3974 /* Start of hblank, measured in pixels minus one from start of hsync */ 3975 # define TV_HBLANK_START_SHIFT 0 3976 # define TV_HBLANK_START_MASK 0x0001fff 3977 3978 #define TV_V_CTL_1 _MMIO(0x6803c) 3979 /* XXX */ 3980 # define TV_NBR_END_SHIFT 16 3981 # define TV_NBR_END_MASK 0x07ff0000 3982 /* XXX */ 3983 # define TV_VI_END_F1_SHIFT 8 3984 # define TV_VI_END_F1_MASK 0x00003f00 3985 /* XXX */ 3986 # define TV_VI_END_F2_SHIFT 0 3987 # define TV_VI_END_F2_MASK 0x0000003f 3988 3989 #define TV_V_CTL_2 _MMIO(0x68040) 3990 /* Length of vsync, in half lines */ 3991 # define TV_VSYNC_LEN_MASK 0x07ff0000 3992 # define TV_VSYNC_LEN_SHIFT 16 3993 /* Offset of the start of vsync in field 1, measured in one less than the 3994 * number of half lines. 3995 */ 3996 # define TV_VSYNC_START_F1_MASK 0x00007f00 3997 # define TV_VSYNC_START_F1_SHIFT 8 3998 /* 3999 * Offset of the start of vsync in field 2, measured in one less than the 4000 * number of half lines. 4001 */ 4002 # define TV_VSYNC_START_F2_MASK 0x0000007f 4003 # define TV_VSYNC_START_F2_SHIFT 0 4004 4005 #define TV_V_CTL_3 _MMIO(0x68044) 4006 /* Enables generation of the equalization signal */ 4007 # define TV_EQUAL_ENA (1 << 31) 4008 /* Length of vsync, in half lines */ 4009 # define TV_VEQ_LEN_MASK 0x007f0000 4010 # define TV_VEQ_LEN_SHIFT 16 4011 /* Offset of the start of equalization in field 1, measured in one less than 4012 * the number of half lines. 4013 */ 4014 # define TV_VEQ_START_F1_MASK 0x0007f00 4015 # define TV_VEQ_START_F1_SHIFT 8 4016 /* 4017 * Offset of the start of equalization in field 2, measured in one less than 4018 * the number of half lines. 4019 */ 4020 # define TV_VEQ_START_F2_MASK 0x000007f 4021 # define TV_VEQ_START_F2_SHIFT 0 4022 4023 #define TV_V_CTL_4 _MMIO(0x68048) 4024 /* 4025 * Offset to start of vertical colorburst, measured in one less than the 4026 * number of lines from vertical start. 4027 */ 4028 # define TV_VBURST_START_F1_MASK 0x003f0000 4029 # define TV_VBURST_START_F1_SHIFT 16 4030 /* 4031 * Offset to the end of vertical colorburst, measured in one less than the 4032 * number of lines from the start of NBR. 4033 */ 4034 # define TV_VBURST_END_F1_MASK 0x000000ff 4035 # define TV_VBURST_END_F1_SHIFT 0 4036 4037 #define TV_V_CTL_5 _MMIO(0x6804c) 4038 /* 4039 * Offset to start of vertical colorburst, measured in one less than the 4040 * number of lines from vertical start. 4041 */ 4042 # define TV_VBURST_START_F2_MASK 0x003f0000 4043 # define TV_VBURST_START_F2_SHIFT 16 4044 /* 4045 * Offset to the end of vertical colorburst, measured in one less than the 4046 * number of lines from the start of NBR. 4047 */ 4048 # define TV_VBURST_END_F2_MASK 0x000000ff 4049 # define TV_VBURST_END_F2_SHIFT 0 4050 4051 #define TV_V_CTL_6 _MMIO(0x68050) 4052 /* 4053 * Offset to start of vertical colorburst, measured in one less than the 4054 * number of lines from vertical start. 4055 */ 4056 # define TV_VBURST_START_F3_MASK 0x003f0000 4057 # define TV_VBURST_START_F3_SHIFT 16 4058 /* 4059 * Offset to the end of vertical colorburst, measured in one less than the 4060 * number of lines from the start of NBR. 4061 */ 4062 # define TV_VBURST_END_F3_MASK 0x000000ff 4063 # define TV_VBURST_END_F3_SHIFT 0 4064 4065 #define TV_V_CTL_7 _MMIO(0x68054) 4066 /* 4067 * Offset to start of vertical colorburst, measured in one less than the 4068 * number of lines from vertical start. 4069 */ 4070 # define TV_VBURST_START_F4_MASK 0x003f0000 4071 # define TV_VBURST_START_F4_SHIFT 16 4072 /* 4073 * Offset to the end of vertical colorburst, measured in one less than the 4074 * number of lines from the start of NBR. 4075 */ 4076 # define TV_VBURST_END_F4_MASK 0x000000ff 4077 # define TV_VBURST_END_F4_SHIFT 0 4078 4079 #define TV_SC_CTL_1 _MMIO(0x68060) 4080 /* Turns on the first subcarrier phase generation DDA */ 4081 # define TV_SC_DDA1_EN (1 << 31) 4082 /* Turns on the first subcarrier phase generation DDA */ 4083 # define TV_SC_DDA2_EN (1 << 30) 4084 /* Turns on the first subcarrier phase generation DDA */ 4085 # define TV_SC_DDA3_EN (1 << 29) 4086 /* Sets the subcarrier DDA to reset frequency every other field */ 4087 # define TV_SC_RESET_EVERY_2 (0 << 24) 4088 /* Sets the subcarrier DDA to reset frequency every fourth field */ 4089 # define TV_SC_RESET_EVERY_4 (1 << 24) 4090 /* Sets the subcarrier DDA to reset frequency every eighth field */ 4091 # define TV_SC_RESET_EVERY_8 (2 << 24) 4092 /* Sets the subcarrier DDA to never reset the frequency */ 4093 # define TV_SC_RESET_NEVER (3 << 24) 4094 /* Sets the peak amplitude of the colorburst.*/ 4095 # define TV_BURST_LEVEL_MASK 0x00ff0000 4096 # define TV_BURST_LEVEL_SHIFT 16 4097 /* Sets the increment of the first subcarrier phase generation DDA */ 4098 # define TV_SCDDA1_INC_MASK 0x00000fff 4099 # define TV_SCDDA1_INC_SHIFT 0 4100 4101 #define TV_SC_CTL_2 _MMIO(0x68064) 4102 /* Sets the rollover for the second subcarrier phase generation DDA */ 4103 # define TV_SCDDA2_SIZE_MASK 0x7fff0000 4104 # define TV_SCDDA2_SIZE_SHIFT 16 4105 /* Sets the increent of the second subcarrier phase generation DDA */ 4106 # define TV_SCDDA2_INC_MASK 0x00007fff 4107 # define TV_SCDDA2_INC_SHIFT 0 4108 4109 #define TV_SC_CTL_3 _MMIO(0x68068) 4110 /* Sets the rollover for the third subcarrier phase generation DDA */ 4111 # define TV_SCDDA3_SIZE_MASK 0x7fff0000 4112 # define TV_SCDDA3_SIZE_SHIFT 16 4113 /* Sets the increent of the third subcarrier phase generation DDA */ 4114 # define TV_SCDDA3_INC_MASK 0x00007fff 4115 # define TV_SCDDA3_INC_SHIFT 0 4116 4117 #define TV_WIN_POS _MMIO(0x68070) 4118 /* X coordinate of the display from the start of horizontal active */ 4119 # define TV_XPOS_MASK 0x1fff0000 4120 # define TV_XPOS_SHIFT 16 4121 /* Y coordinate of the display from the start of vertical active (NBR) */ 4122 # define TV_YPOS_MASK 0x00000fff 4123 # define TV_YPOS_SHIFT 0 4124 4125 #define TV_WIN_SIZE _MMIO(0x68074) 4126 /* Horizontal size of the display window, measured in pixels*/ 4127 # define TV_XSIZE_MASK 0x1fff0000 4128 # define TV_XSIZE_SHIFT 16 4129 /* 4130 * Vertical size of the display window, measured in pixels. 4131 * 4132 * Must be even for interlaced modes. 4133 */ 4134 # define TV_YSIZE_MASK 0x00000fff 4135 # define TV_YSIZE_SHIFT 0 4136 4137 #define TV_FILTER_CTL_1 _MMIO(0x68080) 4138 /* 4139 * Enables automatic scaling calculation. 4140 * 4141 * If set, the rest of the registers are ignored, and the calculated values can 4142 * be read back from the register. 4143 */ 4144 # define TV_AUTO_SCALE (1 << 31) 4145 /* 4146 * Disables the vertical filter. 4147 * 4148 * This is required on modes more than 1024 pixels wide */ 4149 # define TV_V_FILTER_BYPASS (1 << 29) 4150 /* Enables adaptive vertical filtering */ 4151 # define TV_VADAPT (1 << 28) 4152 # define TV_VADAPT_MODE_MASK (3 << 26) 4153 /* Selects the least adaptive vertical filtering mode */ 4154 # define TV_VADAPT_MODE_LEAST (0 << 26) 4155 /* Selects the moderately adaptive vertical filtering mode */ 4156 # define TV_VADAPT_MODE_MODERATE (1 << 26) 4157 /* Selects the most adaptive vertical filtering mode */ 4158 # define TV_VADAPT_MODE_MOST (3 << 26) 4159 /* 4160 * Sets the horizontal scaling factor. 4161 * 4162 * This should be the fractional part of the horizontal scaling factor divided 4163 * by the oversampling rate. TV_HSCALE should be less than 1, and set to: 4164 * 4165 * (src width - 1) / ((oversample * dest width) - 1) 4166 */ 4167 # define TV_HSCALE_FRAC_MASK 0x00003fff 4168 # define TV_HSCALE_FRAC_SHIFT 0 4169 4170 #define TV_FILTER_CTL_2 _MMIO(0x68084) 4171 /* 4172 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 4173 * 4174 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) 4175 */ 4176 # define TV_VSCALE_INT_MASK 0x00038000 4177 # define TV_VSCALE_INT_SHIFT 15 4178 /* 4179 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 4180 * 4181 * \sa TV_VSCALE_INT_MASK 4182 */ 4183 # define TV_VSCALE_FRAC_MASK 0x00007fff 4184 # define TV_VSCALE_FRAC_SHIFT 0 4185 4186 #define TV_FILTER_CTL_3 _MMIO(0x68088) 4187 /* 4188 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 4189 * 4190 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) 4191 * 4192 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 4193 */ 4194 # define TV_VSCALE_IP_INT_MASK 0x00038000 4195 # define TV_VSCALE_IP_INT_SHIFT 15 4196 /* 4197 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 4198 * 4199 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 4200 * 4201 * \sa TV_VSCALE_IP_INT_MASK 4202 */ 4203 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff 4204 # define TV_VSCALE_IP_FRAC_SHIFT 0 4205 4206 #define TV_CC_CONTROL _MMIO(0x68090) 4207 # define TV_CC_ENABLE (1 << 31) 4208 /* 4209 * Specifies which field to send the CC data in. 4210 * 4211 * CC data is usually sent in field 0. 4212 */ 4213 # define TV_CC_FID_MASK (1 << 27) 4214 # define TV_CC_FID_SHIFT 27 4215 /* Sets the horizontal position of the CC data. Usually 135. */ 4216 # define TV_CC_HOFF_MASK 0x03ff0000 4217 # define TV_CC_HOFF_SHIFT 16 4218 /* Sets the vertical position of the CC data. Usually 21 */ 4219 # define TV_CC_LINE_MASK 0x0000003f 4220 # define TV_CC_LINE_SHIFT 0 4221 4222 #define TV_CC_DATA _MMIO(0x68094) 4223 # define TV_CC_RDY (1 << 31) 4224 /* Second word of CC data to be transmitted. */ 4225 # define TV_CC_DATA_2_MASK 0x007f0000 4226 # define TV_CC_DATA_2_SHIFT 16 4227 /* First word of CC data to be transmitted. */ 4228 # define TV_CC_DATA_1_MASK 0x0000007f 4229 # define TV_CC_DATA_1_SHIFT 0 4230 4231 #define TV_H_LUMA(i) _MMIO(0x68100 + (i) * 4) /* 60 registers */ 4232 #define TV_H_CHROMA(i) _MMIO(0x68200 + (i) * 4) /* 60 registers */ 4233 #define TV_V_LUMA(i) _MMIO(0x68300 + (i) * 4) /* 43 registers */ 4234 #define TV_V_CHROMA(i) _MMIO(0x68400 + (i) * 4) /* 43 registers */ 4235 4236 /* Display Port */ 4237 #define DP_A _MMIO(0x64000) /* eDP */ 4238 #define DP_B _MMIO(0x64100) 4239 #define DP_C _MMIO(0x64200) 4240 #define DP_D _MMIO(0x64300) 4241 4242 #define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100) 4243 #define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200) 4244 #define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300) 4245 4246 #define DP_PORT_EN (1 << 31) 4247 #define DP_PIPEB_SELECT (1 << 30) 4248 #define DP_PIPE_MASK (1 << 30) 4249 #define DP_PIPE_SELECT_CHV(pipe) ((pipe) << 16) 4250 #define DP_PIPE_MASK_CHV (3 << 16) 4251 4252 /* Link training mode - select a suitable mode for each stage */ 4253 #define DP_LINK_TRAIN_PAT_1 (0 << 28) 4254 #define DP_LINK_TRAIN_PAT_2 (1 << 28) 4255 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) 4256 #define DP_LINK_TRAIN_OFF (3 << 28) 4257 #define DP_LINK_TRAIN_MASK (3 << 28) 4258 #define DP_LINK_TRAIN_SHIFT 28 4259 #define DP_LINK_TRAIN_PAT_3_CHV (1 << 14) 4260 #define DP_LINK_TRAIN_MASK_CHV ((3 << 28)|(1<<14)) 4261 4262 /* CPT Link training mode */ 4263 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) 4264 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) 4265 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) 4266 #define DP_LINK_TRAIN_OFF_CPT (3 << 8) 4267 #define DP_LINK_TRAIN_MASK_CPT (7 << 8) 4268 #define DP_LINK_TRAIN_SHIFT_CPT 8 4269 4270 /* Signal voltages. These are mostly controlled by the other end */ 4271 #define DP_VOLTAGE_0_4 (0 << 25) 4272 #define DP_VOLTAGE_0_6 (1 << 25) 4273 #define DP_VOLTAGE_0_8 (2 << 25) 4274 #define DP_VOLTAGE_1_2 (3 << 25) 4275 #define DP_VOLTAGE_MASK (7 << 25) 4276 #define DP_VOLTAGE_SHIFT 25 4277 4278 /* Signal pre-emphasis levels, like voltages, the other end tells us what 4279 * they want 4280 */ 4281 #define DP_PRE_EMPHASIS_0 (0 << 22) 4282 #define DP_PRE_EMPHASIS_3_5 (1 << 22) 4283 #define DP_PRE_EMPHASIS_6 (2 << 22) 4284 #define DP_PRE_EMPHASIS_9_5 (3 << 22) 4285 #define DP_PRE_EMPHASIS_MASK (7 << 22) 4286 #define DP_PRE_EMPHASIS_SHIFT 22 4287 4288 /* How many wires to use. I guess 3 was too hard */ 4289 #define DP_PORT_WIDTH(width) (((width) - 1) << 19) 4290 #define DP_PORT_WIDTH_MASK (7 << 19) 4291 #define DP_PORT_WIDTH_SHIFT 19 4292 4293 /* Mystic DPCD version 1.1 special mode */ 4294 #define DP_ENHANCED_FRAMING (1 << 18) 4295 4296 /* eDP */ 4297 #define DP_PLL_FREQ_270MHZ (0 << 16) 4298 #define DP_PLL_FREQ_162MHZ (1 << 16) 4299 #define DP_PLL_FREQ_MASK (3 << 16) 4300 4301 /* locked once port is enabled */ 4302 #define DP_PORT_REVERSAL (1 << 15) 4303 4304 /* eDP */ 4305 #define DP_PLL_ENABLE (1 << 14) 4306 4307 /* sends the clock on lane 15 of the PEG for debug */ 4308 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) 4309 4310 #define DP_SCRAMBLING_DISABLE (1 << 12) 4311 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) 4312 4313 /* limit RGB values to avoid confusing TVs */ 4314 #define DP_COLOR_RANGE_16_235 (1 << 8) 4315 4316 /* Turn on the audio link */ 4317 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) 4318 4319 /* vs and hs sync polarity */ 4320 #define DP_SYNC_VS_HIGH (1 << 4) 4321 #define DP_SYNC_HS_HIGH (1 << 3) 4322 4323 /* A fantasy */ 4324 #define DP_DETECTED (1 << 2) 4325 4326 /* The aux channel provides a way to talk to the 4327 * signal sink for DDC etc. Max packet size supported 4328 * is 20 bytes in each direction, hence the 5 fixed 4329 * data registers 4330 */ 4331 #define _DPA_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64010) 4332 #define _DPA_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64014) 4333 #define _DPA_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64018) 4334 #define _DPA_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6401c) 4335 #define _DPA_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64020) 4336 #define _DPA_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64024) 4337 4338 #define _DPB_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64110) 4339 #define _DPB_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64114) 4340 #define _DPB_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64118) 4341 #define _DPB_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6411c) 4342 #define _DPB_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64120) 4343 #define _DPB_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64124) 4344 4345 #define _DPC_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64210) 4346 #define _DPC_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64214) 4347 #define _DPC_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64218) 4348 #define _DPC_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6421c) 4349 #define _DPC_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64220) 4350 #define _DPC_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64224) 4351 4352 #define _DPD_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64310) 4353 #define _DPD_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64314) 4354 #define _DPD_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64318) 4355 #define _DPD_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6431c) 4356 #define _DPD_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64320) 4357 #define _DPD_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64324) 4358 4359 #define DP_AUX_CH_CTL(port) _MMIO_PORT(port, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL) 4360 #define DP_AUX_CH_DATA(port, i) _MMIO(_PORT(port, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ 4361 4362 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) 4363 #define DP_AUX_CH_CTL_DONE (1 << 30) 4364 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) 4365 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) 4366 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) 4367 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) 4368 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) 4369 #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26) 4370 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) 4371 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) 4372 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) 4373 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 4374 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) 4375 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 4376 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) 4377 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) 4378 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) 4379 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) 4380 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) 4381 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) 4382 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 4383 #define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14) 4384 #define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13) 4385 #define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12) 4386 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5) 4387 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5) 4388 #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1) 4389 4390 /* 4391 * Computing GMCH M and N values for the Display Port link 4392 * 4393 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes 4394 * 4395 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) 4396 * 4397 * The GMCH value is used internally 4398 * 4399 * bytes_per_pixel is the number of bytes coming out of the plane, 4400 * which is after the LUTs, so we want the bytes for our color format. 4401 * For our current usage, this is always 3, one byte for R, G and B. 4402 */ 4403 #define _PIPEA_DATA_M_G4X 0x70050 4404 #define _PIPEB_DATA_M_G4X 0x71050 4405 4406 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ 4407 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ 4408 #define TU_SIZE_SHIFT 25 4409 #define TU_SIZE_MASK (0x3f << 25) 4410 4411 #define DATA_LINK_M_N_MASK (0xffffff) 4412 #define DATA_LINK_N_MAX (0x800000) 4413 4414 #define _PIPEA_DATA_N_G4X 0x70054 4415 #define _PIPEB_DATA_N_G4X 0x71054 4416 #define PIPE_GMCH_DATA_N_MASK (0xffffff) 4417 4418 /* 4419 * Computing Link M and N values for the Display Port link 4420 * 4421 * Link M / N = pixel_clock / ls_clk 4422 * 4423 * (the DP spec calls pixel_clock the 'strm_clk') 4424 * 4425 * The Link value is transmitted in the Main Stream 4426 * Attributes and VB-ID. 4427 */ 4428 4429 #define _PIPEA_LINK_M_G4X 0x70060 4430 #define _PIPEB_LINK_M_G4X 0x71060 4431 #define PIPEA_DP_LINK_M_MASK (0xffffff) 4432 4433 #define _PIPEA_LINK_N_G4X 0x70064 4434 #define _PIPEB_LINK_N_G4X 0x71064 4435 #define PIPEA_DP_LINK_N_MASK (0xffffff) 4436 4437 #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X) 4438 #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X) 4439 #define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X) 4440 #define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X) 4441 4442 /* Display & cursor control */ 4443 4444 /* Pipe A */ 4445 #define _PIPEADSL 0x70000 4446 #define DSL_LINEMASK_GEN2 0x00000fff 4447 #define DSL_LINEMASK_GEN3 0x00001fff 4448 #define _PIPEACONF 0x70008 4449 #define PIPECONF_ENABLE (1<<31) 4450 #define PIPECONF_DISABLE 0 4451 #define PIPECONF_DOUBLE_WIDE (1<<30) 4452 #define I965_PIPECONF_ACTIVE (1<<30) 4453 #define PIPECONF_DSI_PLL_LOCKED (1<<29) /* vlv & pipe A only */ 4454 #define PIPECONF_FRAME_START_DELAY_MASK (3<<27) 4455 #define PIPECONF_SINGLE_WIDE 0 4456 #define PIPECONF_PIPE_UNLOCKED 0 4457 #define PIPECONF_PIPE_LOCKED (1<<25) 4458 #define PIPECONF_PALETTE 0 4459 #define PIPECONF_GAMMA (1<<24) 4460 #define PIPECONF_FORCE_BORDER (1<<25) 4461 #define PIPECONF_INTERLACE_MASK (7 << 21) 4462 #define PIPECONF_INTERLACE_MASK_HSW (3 << 21) 4463 /* Note that pre-gen3 does not support interlaced display directly. Panel 4464 * fitting must be disabled on pre-ilk for interlaced. */ 4465 #define PIPECONF_PROGRESSIVE (0 << 21) 4466 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */ 4467 #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */ 4468 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 4469 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */ 4470 /* Ironlake and later have a complete new set of values for interlaced. PFIT 4471 * means panel fitter required, PF means progressive fetch, DBL means power 4472 * saving pixel doubling. */ 4473 #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21) 4474 #define PIPECONF_INTERLACED_ILK (3 << 21) 4475 #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ 4476 #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ 4477 #define PIPECONF_INTERLACE_MODE_MASK (7 << 21) 4478 #define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20) 4479 #define PIPECONF_CXSR_DOWNCLOCK (1<<16) 4480 #define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14) 4481 #define PIPECONF_COLOR_RANGE_SELECT (1 << 13) 4482 #define PIPECONF_BPC_MASK (0x7 << 5) 4483 #define PIPECONF_8BPC (0<<5) 4484 #define PIPECONF_10BPC (1<<5) 4485 #define PIPECONF_6BPC (2<<5) 4486 #define PIPECONF_12BPC (3<<5) 4487 #define PIPECONF_DITHER_EN (1<<4) 4488 #define PIPECONF_DITHER_TYPE_MASK (0x0000000c) 4489 #define PIPECONF_DITHER_TYPE_SP (0<<2) 4490 #define PIPECONF_DITHER_TYPE_ST1 (1<<2) 4491 #define PIPECONF_DITHER_TYPE_ST2 (2<<2) 4492 #define PIPECONF_DITHER_TYPE_TEMP (3<<2) 4493 #define _PIPEASTAT 0x70024 4494 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) 4495 #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL<<30) 4496 #define PIPE_CRC_ERROR_ENABLE (1UL<<29) 4497 #define PIPE_CRC_DONE_ENABLE (1UL<<28) 4498 #define PERF_COUNTER2_INTERRUPT_EN (1UL<<27) 4499 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) 4500 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26) 4501 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) 4502 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) 4503 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) 4504 #define PIPE_DPST_EVENT_ENABLE (1UL<<23) 4505 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<22) 4506 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) 4507 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) 4508 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) 4509 #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL<<19) 4510 #define PERF_COUNTER_INTERRUPT_EN (1UL<<19) 4511 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ 4512 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ 4513 #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL<<17) 4514 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) 4515 #define PIPEA_HBLANK_INT_EN_VLV (1UL<<16) 4516 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) 4517 #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL<<15) 4518 #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL<<14) 4519 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) 4520 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) 4521 #define PERF_COUNTER2_INTERRUPT_STATUS (1UL<<11) 4522 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) 4523 #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL<<10) 4524 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) 4525 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) 4526 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) 4527 #define PIPE_DPST_EVENT_STATUS (1UL<<7) 4528 #define PIPE_A_PSR_STATUS_VLV (1UL<<6) 4529 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) 4530 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) 4531 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) 4532 #define PIPE_B_PSR_STATUS_VLV (1UL<<3) 4533 #define PERF_COUNTER_INTERRUPT_STATUS (1UL<<3) 4534 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ 4535 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ 4536 #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL<<1) 4537 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) 4538 #define PIPE_HBLANK_INT_STATUS (1UL<<0) 4539 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) 4540 4541 #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000 4542 #define PIPESTAT_INT_STATUS_MASK 0x0000ffff 4543 4544 #define PIPE_A_OFFSET 0x70000 4545 #define PIPE_B_OFFSET 0x71000 4546 #define PIPE_C_OFFSET 0x72000 4547 #define CHV_PIPE_C_OFFSET 0x74000 4548 /* 4549 * There's actually no pipe EDP. Some pipe registers have 4550 * simply shifted from the pipe to the transcoder, while 4551 * keeping their original offset. Thus we need PIPE_EDP_OFFSET 4552 * to access such registers in transcoder EDP. 4553 */ 4554 #define PIPE_EDP_OFFSET 0x7f000 4555 4556 #define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \ 4557 dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \ 4558 dev_priv->info.display_mmio_offset) 4559 4560 #define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF) 4561 #define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL) 4562 #define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH) 4563 #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL) 4564 #define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT) 4565 4566 #define _PIPE_MISC_A 0x70030 4567 #define _PIPE_MISC_B 0x71030 4568 #define PIPEMISC_DITHER_BPC_MASK (7<<5) 4569 #define PIPEMISC_DITHER_8_BPC (0<<5) 4570 #define PIPEMISC_DITHER_10_BPC (1<<5) 4571 #define PIPEMISC_DITHER_6_BPC (2<<5) 4572 #define PIPEMISC_DITHER_12_BPC (3<<5) 4573 #define PIPEMISC_DITHER_ENABLE (1<<4) 4574 #define PIPEMISC_DITHER_TYPE_MASK (3<<2) 4575 #define PIPEMISC_DITHER_TYPE_SP (0<<2) 4576 #define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A) 4577 4578 #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028) 4579 #define PIPEB_LINE_COMPARE_INT_EN (1<<29) 4580 #define PIPEB_HLINE_INT_EN (1<<28) 4581 #define PIPEB_VBLANK_INT_EN (1<<27) 4582 #define SPRITED_FLIP_DONE_INT_EN (1<<26) 4583 #define SPRITEC_FLIP_DONE_INT_EN (1<<25) 4584 #define PLANEB_FLIP_DONE_INT_EN (1<<24) 4585 #define PIPE_PSR_INT_EN (1<<22) 4586 #define PIPEA_LINE_COMPARE_INT_EN (1<<21) 4587 #define PIPEA_HLINE_INT_EN (1<<20) 4588 #define PIPEA_VBLANK_INT_EN (1<<19) 4589 #define SPRITEB_FLIP_DONE_INT_EN (1<<18) 4590 #define SPRITEA_FLIP_DONE_INT_EN (1<<17) 4591 #define PLANEA_FLIPDONE_INT_EN (1<<16) 4592 #define PIPEC_LINE_COMPARE_INT_EN (1<<13) 4593 #define PIPEC_HLINE_INT_EN (1<<12) 4594 #define PIPEC_VBLANK_INT_EN (1<<11) 4595 #define SPRITEF_FLIPDONE_INT_EN (1<<10) 4596 #define SPRITEE_FLIPDONE_INT_EN (1<<9) 4597 #define PLANEC_FLIPDONE_INT_EN (1<<8) 4598 4599 #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */ 4600 #define SPRITEF_INVALID_GTT_INT_EN (1<<27) 4601 #define SPRITEE_INVALID_GTT_INT_EN (1<<26) 4602 #define PLANEC_INVALID_GTT_INT_EN (1<<25) 4603 #define CURSORC_INVALID_GTT_INT_EN (1<<24) 4604 #define CURSORB_INVALID_GTT_INT_EN (1<<23) 4605 #define CURSORA_INVALID_GTT_INT_EN (1<<22) 4606 #define SPRITED_INVALID_GTT_INT_EN (1<<21) 4607 #define SPRITEC_INVALID_GTT_INT_EN (1<<20) 4608 #define PLANEB_INVALID_GTT_INT_EN (1<<19) 4609 #define SPRITEB_INVALID_GTT_INT_EN (1<<18) 4610 #define SPRITEA_INVALID_GTT_INT_EN (1<<17) 4611 #define PLANEA_INVALID_GTT_INT_EN (1<<16) 4612 #define DPINVGTT_EN_MASK 0xff0000 4613 #define DPINVGTT_EN_MASK_CHV 0xfff0000 4614 #define SPRITEF_INVALID_GTT_STATUS (1<<11) 4615 #define SPRITEE_INVALID_GTT_STATUS (1<<10) 4616 #define PLANEC_INVALID_GTT_STATUS (1<<9) 4617 #define CURSORC_INVALID_GTT_STATUS (1<<8) 4618 #define CURSORB_INVALID_GTT_STATUS (1<<7) 4619 #define CURSORA_INVALID_GTT_STATUS (1<<6) 4620 #define SPRITED_INVALID_GTT_STATUS (1<<5) 4621 #define SPRITEC_INVALID_GTT_STATUS (1<<4) 4622 #define PLANEB_INVALID_GTT_STATUS (1<<3) 4623 #define SPRITEB_INVALID_GTT_STATUS (1<<2) 4624 #define SPRITEA_INVALID_GTT_STATUS (1<<1) 4625 #define PLANEA_INVALID_GTT_STATUS (1<<0) 4626 #define DPINVGTT_STATUS_MASK 0xff 4627 #define DPINVGTT_STATUS_MASK_CHV 0xfff 4628 4629 #define DSPARB _MMIO(dev_priv->info.display_mmio_offset + 0x70030) 4630 #define DSPARB_CSTART_MASK (0x7f << 7) 4631 #define DSPARB_CSTART_SHIFT 7 4632 #define DSPARB_BSTART_MASK (0x7f) 4633 #define DSPARB_BSTART_SHIFT 0 4634 #define DSPARB_BEND_SHIFT 9 /* on 855 */ 4635 #define DSPARB_AEND_SHIFT 0 4636 #define DSPARB_SPRITEA_SHIFT_VLV 0 4637 #define DSPARB_SPRITEA_MASK_VLV (0xff << 0) 4638 #define DSPARB_SPRITEB_SHIFT_VLV 8 4639 #define DSPARB_SPRITEB_MASK_VLV (0xff << 8) 4640 #define DSPARB_SPRITEC_SHIFT_VLV 16 4641 #define DSPARB_SPRITEC_MASK_VLV (0xff << 16) 4642 #define DSPARB_SPRITED_SHIFT_VLV 24 4643 #define DSPARB_SPRITED_MASK_VLV (0xff << 24) 4644 #define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */ 4645 #define DSPARB_SPRITEA_HI_SHIFT_VLV 0 4646 #define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0) 4647 #define DSPARB_SPRITEB_HI_SHIFT_VLV 4 4648 #define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4) 4649 #define DSPARB_SPRITEC_HI_SHIFT_VLV 8 4650 #define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8) 4651 #define DSPARB_SPRITED_HI_SHIFT_VLV 12 4652 #define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12) 4653 #define DSPARB_SPRITEE_HI_SHIFT_VLV 16 4654 #define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16) 4655 #define DSPARB_SPRITEF_HI_SHIFT_VLV 20 4656 #define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20) 4657 #define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */ 4658 #define DSPARB_SPRITEE_SHIFT_VLV 0 4659 #define DSPARB_SPRITEE_MASK_VLV (0xff << 0) 4660 #define DSPARB_SPRITEF_SHIFT_VLV 8 4661 #define DSPARB_SPRITEF_MASK_VLV (0xff << 8) 4662 4663 /* pnv/gen4/g4x/vlv/chv */ 4664 #define DSPFW1 _MMIO(dev_priv->info.display_mmio_offset + 0x70034) 4665 #define DSPFW_SR_SHIFT 23 4666 #define DSPFW_SR_MASK (0x1ff<<23) 4667 #define DSPFW_CURSORB_SHIFT 16 4668 #define DSPFW_CURSORB_MASK (0x3f<<16) 4669 #define DSPFW_PLANEB_SHIFT 8 4670 #define DSPFW_PLANEB_MASK (0x7f<<8) 4671 #define DSPFW_PLANEB_MASK_VLV (0xff<<8) /* vlv/chv */ 4672 #define DSPFW_PLANEA_SHIFT 0 4673 #define DSPFW_PLANEA_MASK (0x7f<<0) 4674 #define DSPFW_PLANEA_MASK_VLV (0xff<<0) /* vlv/chv */ 4675 #define DSPFW2 _MMIO(dev_priv->info.display_mmio_offset + 0x70038) 4676 #define DSPFW_FBC_SR_EN (1<<31) /* g4x */ 4677 #define DSPFW_FBC_SR_SHIFT 28 4678 #define DSPFW_FBC_SR_MASK (0x7<<28) /* g4x */ 4679 #define DSPFW_FBC_HPLL_SR_SHIFT 24 4680 #define DSPFW_FBC_HPLL_SR_MASK (0xf<<24) /* g4x */ 4681 #define DSPFW_SPRITEB_SHIFT (16) 4682 #define DSPFW_SPRITEB_MASK (0x7f<<16) /* g4x */ 4683 #define DSPFW_SPRITEB_MASK_VLV (0xff<<16) /* vlv/chv */ 4684 #define DSPFW_CURSORA_SHIFT 8 4685 #define DSPFW_CURSORA_MASK (0x3f<<8) 4686 #define DSPFW_PLANEC_OLD_SHIFT 0 4687 #define DSPFW_PLANEC_OLD_MASK (0x7f<<0) /* pre-gen4 sprite C */ 4688 #define DSPFW_SPRITEA_SHIFT 0 4689 #define DSPFW_SPRITEA_MASK (0x7f<<0) /* g4x */ 4690 #define DSPFW_SPRITEA_MASK_VLV (0xff<<0) /* vlv/chv */ 4691 #define DSPFW3 _MMIO(dev_priv->info.display_mmio_offset + 0x7003c) 4692 #define DSPFW_HPLL_SR_EN (1<<31) 4693 #define PINEVIEW_SELF_REFRESH_EN (1<<30) 4694 #define DSPFW_CURSOR_SR_SHIFT 24 4695 #define DSPFW_CURSOR_SR_MASK (0x3f<<24) 4696 #define DSPFW_HPLL_CURSOR_SHIFT 16 4697 #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) 4698 #define DSPFW_HPLL_SR_SHIFT 0 4699 #define DSPFW_HPLL_SR_MASK (0x1ff<<0) 4700 4701 /* vlv/chv */ 4702 #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070) 4703 #define DSPFW_SPRITEB_WM1_SHIFT 16 4704 #define DSPFW_SPRITEB_WM1_MASK (0xff<<16) 4705 #define DSPFW_CURSORA_WM1_SHIFT 8 4706 #define DSPFW_CURSORA_WM1_MASK (0x3f<<8) 4707 #define DSPFW_SPRITEA_WM1_SHIFT 0 4708 #define DSPFW_SPRITEA_WM1_MASK (0xff<<0) 4709 #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074) 4710 #define DSPFW_PLANEB_WM1_SHIFT 24 4711 #define DSPFW_PLANEB_WM1_MASK (0xff<<24) 4712 #define DSPFW_PLANEA_WM1_SHIFT 16 4713 #define DSPFW_PLANEA_WM1_MASK (0xff<<16) 4714 #define DSPFW_CURSORB_WM1_SHIFT 8 4715 #define DSPFW_CURSORB_WM1_MASK (0x3f<<8) 4716 #define DSPFW_CURSOR_SR_WM1_SHIFT 0 4717 #define DSPFW_CURSOR_SR_WM1_MASK (0x3f<<0) 4718 #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078) 4719 #define DSPFW_SR_WM1_SHIFT 0 4720 #define DSPFW_SR_WM1_MASK (0x1ff<<0) 4721 #define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c) 4722 #define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */ 4723 #define DSPFW_SPRITED_WM1_SHIFT 24 4724 #define DSPFW_SPRITED_WM1_MASK (0xff<<24) 4725 #define DSPFW_SPRITED_SHIFT 16 4726 #define DSPFW_SPRITED_MASK_VLV (0xff<<16) 4727 #define DSPFW_SPRITEC_WM1_SHIFT 8 4728 #define DSPFW_SPRITEC_WM1_MASK (0xff<<8) 4729 #define DSPFW_SPRITEC_SHIFT 0 4730 #define DSPFW_SPRITEC_MASK_VLV (0xff<<0) 4731 #define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8) 4732 #define DSPFW_SPRITEF_WM1_SHIFT 24 4733 #define DSPFW_SPRITEF_WM1_MASK (0xff<<24) 4734 #define DSPFW_SPRITEF_SHIFT 16 4735 #define DSPFW_SPRITEF_MASK_VLV (0xff<<16) 4736 #define DSPFW_SPRITEE_WM1_SHIFT 8 4737 #define DSPFW_SPRITEE_WM1_MASK (0xff<<8) 4738 #define DSPFW_SPRITEE_SHIFT 0 4739 #define DSPFW_SPRITEE_MASK_VLV (0xff<<0) 4740 #define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */ 4741 #define DSPFW_PLANEC_WM1_SHIFT 24 4742 #define DSPFW_PLANEC_WM1_MASK (0xff<<24) 4743 #define DSPFW_PLANEC_SHIFT 16 4744 #define DSPFW_PLANEC_MASK_VLV (0xff<<16) 4745 #define DSPFW_CURSORC_WM1_SHIFT 8 4746 #define DSPFW_CURSORC_WM1_MASK (0x3f<<16) 4747 #define DSPFW_CURSORC_SHIFT 0 4748 #define DSPFW_CURSORC_MASK (0x3f<<0) 4749 4750 /* vlv/chv high order bits */ 4751 #define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064) 4752 #define DSPFW_SR_HI_SHIFT 24 4753 #define DSPFW_SR_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */ 4754 #define DSPFW_SPRITEF_HI_SHIFT 23 4755 #define DSPFW_SPRITEF_HI_MASK (1<<23) 4756 #define DSPFW_SPRITEE_HI_SHIFT 22 4757 #define DSPFW_SPRITEE_HI_MASK (1<<22) 4758 #define DSPFW_PLANEC_HI_SHIFT 21 4759 #define DSPFW_PLANEC_HI_MASK (1<<21) 4760 #define DSPFW_SPRITED_HI_SHIFT 20 4761 #define DSPFW_SPRITED_HI_MASK (1<<20) 4762 #define DSPFW_SPRITEC_HI_SHIFT 16 4763 #define DSPFW_SPRITEC_HI_MASK (1<<16) 4764 #define DSPFW_PLANEB_HI_SHIFT 12 4765 #define DSPFW_PLANEB_HI_MASK (1<<12) 4766 #define DSPFW_SPRITEB_HI_SHIFT 8 4767 #define DSPFW_SPRITEB_HI_MASK (1<<8) 4768 #define DSPFW_SPRITEA_HI_SHIFT 4 4769 #define DSPFW_SPRITEA_HI_MASK (1<<4) 4770 #define DSPFW_PLANEA_HI_SHIFT 0 4771 #define DSPFW_PLANEA_HI_MASK (1<<0) 4772 #define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068) 4773 #define DSPFW_SR_WM1_HI_SHIFT 24 4774 #define DSPFW_SR_WM1_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */ 4775 #define DSPFW_SPRITEF_WM1_HI_SHIFT 23 4776 #define DSPFW_SPRITEF_WM1_HI_MASK (1<<23) 4777 #define DSPFW_SPRITEE_WM1_HI_SHIFT 22 4778 #define DSPFW_SPRITEE_WM1_HI_MASK (1<<22) 4779 #define DSPFW_PLANEC_WM1_HI_SHIFT 21 4780 #define DSPFW_PLANEC_WM1_HI_MASK (1<<21) 4781 #define DSPFW_SPRITED_WM1_HI_SHIFT 20 4782 #define DSPFW_SPRITED_WM1_HI_MASK (1<<20) 4783 #define DSPFW_SPRITEC_WM1_HI_SHIFT 16 4784 #define DSPFW_SPRITEC_WM1_HI_MASK (1<<16) 4785 #define DSPFW_PLANEB_WM1_HI_SHIFT 12 4786 #define DSPFW_PLANEB_WM1_HI_MASK (1<<12) 4787 #define DSPFW_SPRITEB_WM1_HI_SHIFT 8 4788 #define DSPFW_SPRITEB_WM1_HI_MASK (1<<8) 4789 #define DSPFW_SPRITEA_WM1_HI_SHIFT 4 4790 #define DSPFW_SPRITEA_WM1_HI_MASK (1<<4) 4791 #define DSPFW_PLANEA_WM1_HI_SHIFT 0 4792 #define DSPFW_PLANEA_WM1_HI_MASK (1<<0) 4793 4794 /* drain latency register values*/ 4795 #define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe)) 4796 #define DDL_CURSOR_SHIFT 24 4797 #define DDL_SPRITE_SHIFT(sprite) (8+8*(sprite)) 4798 #define DDL_PLANE_SHIFT 0 4799 #define DDL_PRECISION_HIGH (1<<7) 4800 #define DDL_PRECISION_LOW (0<<7) 4801 #define DRAIN_LATENCY_MASK 0x7f 4802 4803 #define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400) 4804 #define CBR_PND_DEADLINE_DISABLE (1<<31) 4805 #define CBR_PWM_CLOCK_MUX_SELECT (1<<30) 4806 4807 #define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450) 4808 #define CBR_DPLLBMD_PIPE_C (1<<29) 4809 #define CBR_DPLLBMD_PIPE_B (1<<18) 4810 4811 /* FIFO watermark sizes etc */ 4812 #define G4X_FIFO_LINE_SIZE 64 4813 #define I915_FIFO_LINE_SIZE 64 4814 #define I830_FIFO_LINE_SIZE 32 4815 4816 #define VALLEYVIEW_FIFO_SIZE 255 4817 #define G4X_FIFO_SIZE 127 4818 #define I965_FIFO_SIZE 512 4819 #define I945_FIFO_SIZE 127 4820 #define I915_FIFO_SIZE 95 4821 #define I855GM_FIFO_SIZE 127 /* In cachelines */ 4822 #define I830_FIFO_SIZE 95 4823 4824 #define VALLEYVIEW_MAX_WM 0xff 4825 #define G4X_MAX_WM 0x3f 4826 #define I915_MAX_WM 0x3f 4827 4828 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ 4829 #define PINEVIEW_FIFO_LINE_SIZE 64 4830 #define PINEVIEW_MAX_WM 0x1ff 4831 #define PINEVIEW_DFT_WM 0x3f 4832 #define PINEVIEW_DFT_HPLLOFF_WM 0 4833 #define PINEVIEW_GUARD_WM 10 4834 #define PINEVIEW_CURSOR_FIFO 64 4835 #define PINEVIEW_CURSOR_MAX_WM 0x3f 4836 #define PINEVIEW_CURSOR_DFT_WM 0 4837 #define PINEVIEW_CURSOR_GUARD_WM 5 4838 4839 #define VALLEYVIEW_CURSOR_MAX_WM 64 4840 #define I965_CURSOR_FIFO 64 4841 #define I965_CURSOR_MAX_WM 32 4842 #define I965_CURSOR_DFT_WM 8 4843 4844 /* Watermark register definitions for SKL */ 4845 #define _CUR_WM_A_0 0x70140 4846 #define _CUR_WM_B_0 0x71140 4847 #define _PLANE_WM_1_A_0 0x70240 4848 #define _PLANE_WM_1_B_0 0x71240 4849 #define _PLANE_WM_2_A_0 0x70340 4850 #define _PLANE_WM_2_B_0 0x71340 4851 #define _PLANE_WM_TRANS_1_A_0 0x70268 4852 #define _PLANE_WM_TRANS_1_B_0 0x71268 4853 #define _PLANE_WM_TRANS_2_A_0 0x70368 4854 #define _PLANE_WM_TRANS_2_B_0 0x71368 4855 #define _CUR_WM_TRANS_A_0 0x70168 4856 #define _CUR_WM_TRANS_B_0 0x71168 4857 #define PLANE_WM_EN (1 << 31) 4858 #define PLANE_WM_LINES_SHIFT 14 4859 #define PLANE_WM_LINES_MASK 0x1f 4860 #define PLANE_WM_BLOCKS_MASK 0x3ff 4861 4862 #define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0) 4863 #define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level))) 4864 #define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0) 4865 4866 #define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0) 4867 #define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0) 4868 #define _PLANE_WM_BASE(pipe, plane) \ 4869 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe)) 4870 #define PLANE_WM(pipe, plane, level) \ 4871 _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level))) 4872 #define _PLANE_WM_TRANS_1(pipe) \ 4873 _PIPE(pipe, _PLANE_WM_TRANS_1_A_0, _PLANE_WM_TRANS_1_B_0) 4874 #define _PLANE_WM_TRANS_2(pipe) \ 4875 _PIPE(pipe, _PLANE_WM_TRANS_2_A_0, _PLANE_WM_TRANS_2_B_0) 4876 #define PLANE_WM_TRANS(pipe, plane) \ 4877 _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe))) 4878 4879 /* define the Watermark register on Ironlake */ 4880 #define WM0_PIPEA_ILK _MMIO(0x45100) 4881 #define WM0_PIPE_PLANE_MASK (0xffff<<16) 4882 #define WM0_PIPE_PLANE_SHIFT 16 4883 #define WM0_PIPE_SPRITE_MASK (0xff<<8) 4884 #define WM0_PIPE_SPRITE_SHIFT 8 4885 #define WM0_PIPE_CURSOR_MASK (0xff) 4886 4887 #define WM0_PIPEB_ILK _MMIO(0x45104) 4888 #define WM0_PIPEC_IVB _MMIO(0x45200) 4889 #define WM1_LP_ILK _MMIO(0x45108) 4890 #define WM1_LP_SR_EN (1<<31) 4891 #define WM1_LP_LATENCY_SHIFT 24 4892 #define WM1_LP_LATENCY_MASK (0x7f<<24) 4893 #define WM1_LP_FBC_MASK (0xf<<20) 4894 #define WM1_LP_FBC_SHIFT 20 4895 #define WM1_LP_FBC_SHIFT_BDW 19 4896 #define WM1_LP_SR_MASK (0x7ff<<8) 4897 #define WM1_LP_SR_SHIFT 8 4898 #define WM1_LP_CURSOR_MASK (0xff) 4899 #define WM2_LP_ILK _MMIO(0x4510c) 4900 #define WM2_LP_EN (1<<31) 4901 #define WM3_LP_ILK _MMIO(0x45110) 4902 #define WM3_LP_EN (1<<31) 4903 #define WM1S_LP_ILK _MMIO(0x45120) 4904 #define WM2S_LP_IVB _MMIO(0x45124) 4905 #define WM3S_LP_IVB _MMIO(0x45128) 4906 #define WM1S_LP_EN (1<<31) 4907 4908 #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \ 4909 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \ 4910 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur)) 4911 4912 /* Memory latency timer register */ 4913 #define MLTR_ILK _MMIO(0x11222) 4914 #define MLTR_WM1_SHIFT 0 4915 #define MLTR_WM2_SHIFT 8 4916 /* the unit of memory self-refresh latency time is 0.5us */ 4917 #define ILK_SRLT_MASK 0x3f 4918 4919 4920 /* the address where we get all kinds of latency value */ 4921 #define SSKPD _MMIO(0x5d10) 4922 #define SSKPD_WM_MASK 0x3f 4923 #define SSKPD_WM0_SHIFT 0 4924 #define SSKPD_WM1_SHIFT 8 4925 #define SSKPD_WM2_SHIFT 16 4926 #define SSKPD_WM3_SHIFT 24 4927 4928 /* 4929 * The two pipe frame counter registers are not synchronized, so 4930 * reading a stable value is somewhat tricky. The following code 4931 * should work: 4932 * 4933 * do { 4934 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 4935 * PIPE_FRAME_HIGH_SHIFT; 4936 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> 4937 * PIPE_FRAME_LOW_SHIFT); 4938 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 4939 * PIPE_FRAME_HIGH_SHIFT); 4940 * } while (high1 != high2); 4941 * frame = (high1 << 8) | low1; 4942 */ 4943 #define _PIPEAFRAMEHIGH 0x70040 4944 #define PIPE_FRAME_HIGH_MASK 0x0000ffff 4945 #define PIPE_FRAME_HIGH_SHIFT 0 4946 #define _PIPEAFRAMEPIXEL 0x70044 4947 #define PIPE_FRAME_LOW_MASK 0xff000000 4948 #define PIPE_FRAME_LOW_SHIFT 24 4949 #define PIPE_PIXEL_MASK 0x00ffffff 4950 #define PIPE_PIXEL_SHIFT 0 4951 /* GM45+ just has to be different */ 4952 #define _PIPEA_FRMCOUNT_G4X 0x70040 4953 #define _PIPEA_FLIPCOUNT_G4X 0x70044 4954 #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X) 4955 #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X) 4956 4957 /* Cursor A & B regs */ 4958 #define _CURACNTR 0x70080 4959 /* Old style CUR*CNTR flags (desktop 8xx) */ 4960 #define CURSOR_ENABLE 0x80000000 4961 #define CURSOR_GAMMA_ENABLE 0x40000000 4962 #define CURSOR_STRIDE_SHIFT 28 4963 #define CURSOR_STRIDE(x) ((ffs(x)-9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */ 4964 #define CURSOR_PIPE_CSC_ENABLE (1<<24) 4965 #define CURSOR_FORMAT_SHIFT 24 4966 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) 4967 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) 4968 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) 4969 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) 4970 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) 4971 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) 4972 /* New style CUR*CNTR flags */ 4973 #define CURSOR_MODE 0x27 4974 #define CURSOR_MODE_DISABLE 0x00 4975 #define CURSOR_MODE_128_32B_AX 0x02 4976 #define CURSOR_MODE_256_32B_AX 0x03 4977 #define CURSOR_MODE_64_32B_AX 0x07 4978 #define CURSOR_MODE_128_ARGB_AX ((1 << 5) | CURSOR_MODE_128_32B_AX) 4979 #define CURSOR_MODE_256_ARGB_AX ((1 << 5) | CURSOR_MODE_256_32B_AX) 4980 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) 4981 #define MCURSOR_PIPE_SELECT (1 << 28) 4982 #define MCURSOR_PIPE_A 0x00 4983 #define MCURSOR_PIPE_B (1 << 28) 4984 #define MCURSOR_GAMMA_ENABLE (1 << 26) 4985 #define CURSOR_ROTATE_180 (1<<15) 4986 #define CURSOR_TRICKLE_FEED_DISABLE (1 << 14) 4987 #define _CURABASE 0x70084 4988 #define _CURAPOS 0x70088 4989 #define CURSOR_POS_MASK 0x007FF 4990 #define CURSOR_POS_SIGN 0x8000 4991 #define CURSOR_X_SHIFT 0 4992 #define CURSOR_Y_SHIFT 16 4993 #define CURSIZE _MMIO(0x700a0) 4994 #define _CURBCNTR 0x700c0 4995 #define _CURBBASE 0x700c4 4996 #define _CURBPOS 0x700c8 4997 4998 #define _CURBCNTR_IVB 0x71080 4999 #define _CURBBASE_IVB 0x71084 5000 #define _CURBPOS_IVB 0x71088 5001 5002 #define _CURSOR2(pipe, reg) _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \ 5003 dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \ 5004 dev_priv->info.display_mmio_offset) 5005 5006 #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR) 5007 #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE) 5008 #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS) 5009 5010 #define CURSOR_A_OFFSET 0x70080 5011 #define CURSOR_B_OFFSET 0x700c0 5012 #define CHV_CURSOR_C_OFFSET 0x700e0 5013 #define IVB_CURSOR_B_OFFSET 0x71080 5014 #define IVB_CURSOR_C_OFFSET 0x72080 5015 5016 /* Display A control */ 5017 #define _DSPACNTR 0x70180 5018 #define DISPLAY_PLANE_ENABLE (1<<31) 5019 #define DISPLAY_PLANE_DISABLE 0 5020 #define DISPPLANE_GAMMA_ENABLE (1<<30) 5021 #define DISPPLANE_GAMMA_DISABLE 0 5022 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26) 5023 #define DISPPLANE_YUV422 (0x0<<26) 5024 #define DISPPLANE_8BPP (0x2<<26) 5025 #define DISPPLANE_BGRA555 (0x3<<26) 5026 #define DISPPLANE_BGRX555 (0x4<<26) 5027 #define DISPPLANE_BGRX565 (0x5<<26) 5028 #define DISPPLANE_BGRX888 (0x6<<26) 5029 #define DISPPLANE_BGRA888 (0x7<<26) 5030 #define DISPPLANE_RGBX101010 (0x8<<26) 5031 #define DISPPLANE_RGBA101010 (0x9<<26) 5032 #define DISPPLANE_BGRX101010 (0xa<<26) 5033 #define DISPPLANE_RGBX161616 (0xc<<26) 5034 #define DISPPLANE_RGBX888 (0xe<<26) 5035 #define DISPPLANE_RGBA888 (0xf<<26) 5036 #define DISPPLANE_STEREO_ENABLE (1<<25) 5037 #define DISPPLANE_STEREO_DISABLE 0 5038 #define DISPPLANE_PIPE_CSC_ENABLE (1<<24) 5039 #define DISPPLANE_SEL_PIPE_SHIFT 24 5040 #define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT) 5041 #define DISPPLANE_SEL_PIPE_A 0 5042 #define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT) 5043 #define DISPPLANE_SRC_KEY_ENABLE (1<<22) 5044 #define DISPPLANE_SRC_KEY_DISABLE 0 5045 #define DISPPLANE_LINE_DOUBLE (1<<20) 5046 #define DISPPLANE_NO_LINE_DOUBLE 0 5047 #define DISPPLANE_STEREO_POLARITY_FIRST 0 5048 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) 5049 #define DISPPLANE_ALPHA_PREMULTIPLY (1<<16) /* CHV pipe B */ 5050 #define DISPPLANE_ROTATE_180 (1<<15) 5051 #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ 5052 #define DISPPLANE_TILED (1<<10) 5053 #define DISPPLANE_MIRROR (1<<8) /* CHV pipe B */ 5054 #define _DSPAADDR 0x70184 5055 #define _DSPASTRIDE 0x70188 5056 #define _DSPAPOS 0x7018C /* reserved */ 5057 #define _DSPASIZE 0x70190 5058 #define _DSPASURF 0x7019C /* 965+ only */ 5059 #define _DSPATILEOFF 0x701A4 /* 965+ only */ 5060 #define _DSPAOFFSET 0x701A4 /* HSW */ 5061 #define _DSPASURFLIVE 0x701AC 5062 5063 #define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR) 5064 #define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR) 5065 #define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE) 5066 #define DSPPOS(plane) _MMIO_PIPE2(plane, _DSPAPOS) 5067 #define DSPSIZE(plane) _MMIO_PIPE2(plane, _DSPASIZE) 5068 #define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF) 5069 #define DSPTILEOFF(plane) _MMIO_PIPE2(plane, _DSPATILEOFF) 5070 #define DSPLINOFF(plane) DSPADDR(plane) 5071 #define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET) 5072 #define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE) 5073 5074 /* CHV pipe B blender and primary plane */ 5075 #define _CHV_BLEND_A 0x60a00 5076 #define CHV_BLEND_LEGACY (0<<30) 5077 #define CHV_BLEND_ANDROID (1<<30) 5078 #define CHV_BLEND_MPO (2<<30) 5079 #define CHV_BLEND_MASK (3<<30) 5080 #define _CHV_CANVAS_A 0x60a04 5081 #define _PRIMPOS_A 0x60a08 5082 #define _PRIMSIZE_A 0x60a0c 5083 #define _PRIMCNSTALPHA_A 0x60a10 5084 #define PRIM_CONST_ALPHA_ENABLE (1<<31) 5085 5086 #define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A) 5087 #define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A) 5088 #define PRIMPOS(plane) _MMIO_TRANS2(plane, _PRIMPOS_A) 5089 #define PRIMSIZE(plane) _MMIO_TRANS2(plane, _PRIMSIZE_A) 5090 #define PRIMCNSTALPHA(plane) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A) 5091 5092 /* Display/Sprite base address macros */ 5093 #define DISP_BASEADDR_MASK (0xfffff000) 5094 #define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK) 5095 #define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK) 5096 5097 /* 5098 * VBIOS flags 5099 * gen2: 5100 * [00:06] alm,mgm 5101 * [10:16] all 5102 * [30:32] alm,mgm 5103 * gen3+: 5104 * [00:0f] all 5105 * [10:1f] all 5106 * [30:32] all 5107 */ 5108 #define SWF0(i) _MMIO(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4) 5109 #define SWF1(i) _MMIO(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4) 5110 #define SWF3(i) _MMIO(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4) 5111 #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4) 5112 5113 /* Pipe B */ 5114 #define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000) 5115 #define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008) 5116 #define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024) 5117 #define _PIPEBFRAMEHIGH 0x71040 5118 #define _PIPEBFRAMEPIXEL 0x71044 5119 #define _PIPEB_FRMCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71040) 5120 #define _PIPEB_FLIPCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71044) 5121 5122 5123 /* Display B control */ 5124 #define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180) 5125 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) 5126 #define DISPPLANE_ALPHA_TRANS_DISABLE 0 5127 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 5128 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 5129 #define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184) 5130 #define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188) 5131 #define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C) 5132 #define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190) 5133 #define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C) 5134 #define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4) 5135 #define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4) 5136 #define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC) 5137 5138 /* Sprite A control */ 5139 #define _DVSACNTR 0x72180 5140 #define DVS_ENABLE (1<<31) 5141 #define DVS_GAMMA_ENABLE (1<<30) 5142 #define DVS_PIXFORMAT_MASK (3<<25) 5143 #define DVS_FORMAT_YUV422 (0<<25) 5144 #define DVS_FORMAT_RGBX101010 (1<<25) 5145 #define DVS_FORMAT_RGBX888 (2<<25) 5146 #define DVS_FORMAT_RGBX161616 (3<<25) 5147 #define DVS_PIPE_CSC_ENABLE (1<<24) 5148 #define DVS_SOURCE_KEY (1<<22) 5149 #define DVS_RGB_ORDER_XBGR (1<<20) 5150 #define DVS_YUV_BYTE_ORDER_MASK (3<<16) 5151 #define DVS_YUV_ORDER_YUYV (0<<16) 5152 #define DVS_YUV_ORDER_UYVY (1<<16) 5153 #define DVS_YUV_ORDER_YVYU (2<<16) 5154 #define DVS_YUV_ORDER_VYUY (3<<16) 5155 #define DVS_ROTATE_180 (1<<15) 5156 #define DVS_DEST_KEY (1<<2) 5157 #define DVS_TRICKLE_FEED_DISABLE (1<<14) 5158 #define DVS_TILED (1<<10) 5159 #define _DVSALINOFF 0x72184 5160 #define _DVSASTRIDE 0x72188 5161 #define _DVSAPOS 0x7218c 5162 #define _DVSASIZE 0x72190 5163 #define _DVSAKEYVAL 0x72194 5164 #define _DVSAKEYMSK 0x72198 5165 #define _DVSASURF 0x7219c 5166 #define _DVSAKEYMAXVAL 0x721a0 5167 #define _DVSATILEOFF 0x721a4 5168 #define _DVSASURFLIVE 0x721ac 5169 #define _DVSASCALE 0x72204 5170 #define DVS_SCALE_ENABLE (1<<31) 5171 #define DVS_FILTER_MASK (3<<29) 5172 #define DVS_FILTER_MEDIUM (0<<29) 5173 #define DVS_FILTER_ENHANCING (1<<29) 5174 #define DVS_FILTER_SOFTENING (2<<29) 5175 #define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ 5176 #define DVS_VERTICAL_OFFSET_ENABLE (1<<27) 5177 #define _DVSAGAMC 0x72300 5178 5179 #define _DVSBCNTR 0x73180 5180 #define _DVSBLINOFF 0x73184 5181 #define _DVSBSTRIDE 0x73188 5182 #define _DVSBPOS 0x7318c 5183 #define _DVSBSIZE 0x73190 5184 #define _DVSBKEYVAL 0x73194 5185 #define _DVSBKEYMSK 0x73198 5186 #define _DVSBSURF 0x7319c 5187 #define _DVSBKEYMAXVAL 0x731a0 5188 #define _DVSBTILEOFF 0x731a4 5189 #define _DVSBSURFLIVE 0x731ac 5190 #define _DVSBSCALE 0x73204 5191 #define _DVSBGAMC 0x73300 5192 5193 #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR) 5194 #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) 5195 #define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) 5196 #define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS) 5197 #define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF) 5198 #define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) 5199 #define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE) 5200 #define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE) 5201 #define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) 5202 #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) 5203 #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) 5204 #define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) 5205 5206 #define _SPRA_CTL 0x70280 5207 #define SPRITE_ENABLE (1<<31) 5208 #define SPRITE_GAMMA_ENABLE (1<<30) 5209 #define SPRITE_PIXFORMAT_MASK (7<<25) 5210 #define SPRITE_FORMAT_YUV422 (0<<25) 5211 #define SPRITE_FORMAT_RGBX101010 (1<<25) 5212 #define SPRITE_FORMAT_RGBX888 (2<<25) 5213 #define SPRITE_FORMAT_RGBX161616 (3<<25) 5214 #define SPRITE_FORMAT_YUV444 (4<<25) 5215 #define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */ 5216 #define SPRITE_PIPE_CSC_ENABLE (1<<24) 5217 #define SPRITE_SOURCE_KEY (1<<22) 5218 #define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */ 5219 #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19) 5220 #define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */ 5221 #define SPRITE_YUV_BYTE_ORDER_MASK (3<<16) 5222 #define SPRITE_YUV_ORDER_YUYV (0<<16) 5223 #define SPRITE_YUV_ORDER_UYVY (1<<16) 5224 #define SPRITE_YUV_ORDER_YVYU (2<<16) 5225 #define SPRITE_YUV_ORDER_VYUY (3<<16) 5226 #define SPRITE_ROTATE_180 (1<<15) 5227 #define SPRITE_TRICKLE_FEED_DISABLE (1<<14) 5228 #define SPRITE_INT_GAMMA_ENABLE (1<<13) 5229 #define SPRITE_TILED (1<<10) 5230 #define SPRITE_DEST_KEY (1<<2) 5231 #define _SPRA_LINOFF 0x70284 5232 #define _SPRA_STRIDE 0x70288 5233 #define _SPRA_POS 0x7028c 5234 #define _SPRA_SIZE 0x70290 5235 #define _SPRA_KEYVAL 0x70294 5236 #define _SPRA_KEYMSK 0x70298 5237 #define _SPRA_SURF 0x7029c 5238 #define _SPRA_KEYMAX 0x702a0 5239 #define _SPRA_TILEOFF 0x702a4 5240 #define _SPRA_OFFSET 0x702a4 5241 #define _SPRA_SURFLIVE 0x702ac 5242 #define _SPRA_SCALE 0x70304 5243 #define SPRITE_SCALE_ENABLE (1<<31) 5244 #define SPRITE_FILTER_MASK (3<<29) 5245 #define SPRITE_FILTER_MEDIUM (0<<29) 5246 #define SPRITE_FILTER_ENHANCING (1<<29) 5247 #define SPRITE_FILTER_SOFTENING (2<<29) 5248 #define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ 5249 #define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27) 5250 #define _SPRA_GAMC 0x70400 5251 5252 #define _SPRB_CTL 0x71280 5253 #define _SPRB_LINOFF 0x71284 5254 #define _SPRB_STRIDE 0x71288 5255 #define _SPRB_POS 0x7128c 5256 #define _SPRB_SIZE 0x71290 5257 #define _SPRB_KEYVAL 0x71294 5258 #define _SPRB_KEYMSK 0x71298 5259 #define _SPRB_SURF 0x7129c 5260 #define _SPRB_KEYMAX 0x712a0 5261 #define _SPRB_TILEOFF 0x712a4 5262 #define _SPRB_OFFSET 0x712a4 5263 #define _SPRB_SURFLIVE 0x712ac 5264 #define _SPRB_SCALE 0x71304 5265 #define _SPRB_GAMC 0x71400 5266 5267 #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL) 5268 #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) 5269 #define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) 5270 #define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS) 5271 #define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) 5272 #define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) 5273 #define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) 5274 #define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF) 5275 #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) 5276 #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) 5277 #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) 5278 #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) 5279 #define SPRGAMC(pipe) _MMIO_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) 5280 #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) 5281 5282 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180) 5283 #define SP_ENABLE (1<<31) 5284 #define SP_GAMMA_ENABLE (1<<30) 5285 #define SP_PIXFORMAT_MASK (0xf<<26) 5286 #define SP_FORMAT_YUV422 (0<<26) 5287 #define SP_FORMAT_BGR565 (5<<26) 5288 #define SP_FORMAT_BGRX8888 (6<<26) 5289 #define SP_FORMAT_BGRA8888 (7<<26) 5290 #define SP_FORMAT_RGBX1010102 (8<<26) 5291 #define SP_FORMAT_RGBA1010102 (9<<26) 5292 #define SP_FORMAT_RGBX8888 (0xe<<26) 5293 #define SP_FORMAT_RGBA8888 (0xf<<26) 5294 #define SP_ALPHA_PREMULTIPLY (1<<23) /* CHV pipe B */ 5295 #define SP_SOURCE_KEY (1<<22) 5296 #define SP_YUV_BYTE_ORDER_MASK (3<<16) 5297 #define SP_YUV_ORDER_YUYV (0<<16) 5298 #define SP_YUV_ORDER_UYVY (1<<16) 5299 #define SP_YUV_ORDER_YVYU (2<<16) 5300 #define SP_YUV_ORDER_VYUY (3<<16) 5301 #define SP_ROTATE_180 (1<<15) 5302 #define SP_TILED (1<<10) 5303 #define SP_MIRROR (1<<8) /* CHV pipe B */ 5304 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184) 5305 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188) 5306 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c) 5307 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190) 5308 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194) 5309 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198) 5310 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c) 5311 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0) 5312 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4) 5313 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8) 5314 #define SP_CONST_ALPHA_ENABLE (1<<31) 5315 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4) 5316 5317 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280) 5318 #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284) 5319 #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288) 5320 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c) 5321 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290) 5322 #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294) 5323 #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298) 5324 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c) 5325 #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0) 5326 #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4) 5327 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8) 5328 #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4) 5329 5330 #define SPCNTR(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPACNTR, _SPBCNTR) 5331 #define SPLINOFF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPALINOFF, _SPBLINOFF) 5332 #define SPSTRIDE(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPASTRIDE, _SPBSTRIDE) 5333 #define SPPOS(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAPOS, _SPBPOS) 5334 #define SPSIZE(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPASIZE, _SPBSIZE) 5335 #define SPKEYMINVAL(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAKEYMINVAL, _SPBKEYMINVAL) 5336 #define SPKEYMSK(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAKEYMSK, _SPBKEYMSK) 5337 #define SPSURF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPASURF, _SPBSURF) 5338 #define SPKEYMAXVAL(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAKEYMAXVAL, _SPBKEYMAXVAL) 5339 #define SPTILEOFF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPATILEOFF, _SPBTILEOFF) 5340 #define SPCONSTALPHA(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPACONSTALPHA, _SPBCONSTALPHA) 5341 #define SPGAMC(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAGAMC, _SPBGAMC) 5342 5343 /* 5344 * CHV pipe B sprite CSC 5345 * 5346 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff| 5347 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff| 5348 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff| 5349 */ 5350 #define SPCSCYGOFF(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d900 + (sprite) * 0x1000) 5351 #define SPCSCCBOFF(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d904 + (sprite) * 0x1000) 5352 #define SPCSCCROFF(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d908 + (sprite) * 0x1000) 5353 #define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */ 5354 #define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */ 5355 5356 #define SPCSCC01(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d90c + (sprite) * 0x1000) 5357 #define SPCSCC23(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d910 + (sprite) * 0x1000) 5358 #define SPCSCC45(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d914 + (sprite) * 0x1000) 5359 #define SPCSCC67(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d918 + (sprite) * 0x1000) 5360 #define SPCSCC8(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d91c + (sprite) * 0x1000) 5361 #define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */ 5362 #define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */ 5363 5364 #define SPCSCYGICLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d920 + (sprite) * 0x1000) 5365 #define SPCSCCBICLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d924 + (sprite) * 0x1000) 5366 #define SPCSCCRICLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d928 + (sprite) * 0x1000) 5367 #define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */ 5368 #define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */ 5369 5370 #define SPCSCYGOCLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d92c + (sprite) * 0x1000) 5371 #define SPCSCCBOCLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d930 + (sprite) * 0x1000) 5372 #define SPCSCCROCLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d934 + (sprite) * 0x1000) 5373 #define SPCSC_OMAX(x) ((x) << 16) /* u10 */ 5374 #define SPCSC_OMIN(x) ((x) << 0) /* u10 */ 5375 5376 /* Skylake plane registers */ 5377 5378 #define _PLANE_CTL_1_A 0x70180 5379 #define _PLANE_CTL_2_A 0x70280 5380 #define _PLANE_CTL_3_A 0x70380 5381 #define PLANE_CTL_ENABLE (1 << 31) 5382 #define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30) 5383 #define PLANE_CTL_FORMAT_MASK (0xf << 24) 5384 #define PLANE_CTL_FORMAT_YUV422 ( 0 << 24) 5385 #define PLANE_CTL_FORMAT_NV12 ( 1 << 24) 5386 #define PLANE_CTL_FORMAT_XRGB_2101010 ( 2 << 24) 5387 #define PLANE_CTL_FORMAT_XRGB_8888 ( 4 << 24) 5388 #define PLANE_CTL_FORMAT_XRGB_16161616F ( 6 << 24) 5389 #define PLANE_CTL_FORMAT_AYUV ( 8 << 24) 5390 #define PLANE_CTL_FORMAT_INDEXED ( 12 << 24) 5391 #define PLANE_CTL_FORMAT_RGB_565 ( 14 << 24) 5392 #define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) 5393 #define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21) 5394 #define PLANE_CTL_KEY_ENABLE_SOURCE ( 1 << 21) 5395 #define PLANE_CTL_KEY_ENABLE_DESTINATION ( 2 << 21) 5396 #define PLANE_CTL_ORDER_BGRX (0 << 20) 5397 #define PLANE_CTL_ORDER_RGBX (1 << 20) 5398 #define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16) 5399 #define PLANE_CTL_YUV422_YUYV ( 0 << 16) 5400 #define PLANE_CTL_YUV422_UYVY ( 1 << 16) 5401 #define PLANE_CTL_YUV422_YVYU ( 2 << 16) 5402 #define PLANE_CTL_YUV422_VYUY ( 3 << 16) 5403 #define PLANE_CTL_DECOMPRESSION_ENABLE (1 << 15) 5404 #define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14) 5405 #define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) 5406 #define PLANE_CTL_TILED_MASK (0x7 << 10) 5407 #define PLANE_CTL_TILED_LINEAR ( 0 << 10) 5408 #define PLANE_CTL_TILED_X ( 1 << 10) 5409 #define PLANE_CTL_TILED_Y ( 4 << 10) 5410 #define PLANE_CTL_TILED_YF ( 5 << 10) 5411 #define PLANE_CTL_ALPHA_MASK (0x3 << 4) 5412 #define PLANE_CTL_ALPHA_DISABLE ( 0 << 4) 5413 #define PLANE_CTL_ALPHA_SW_PREMULTIPLY ( 2 << 4) 5414 #define PLANE_CTL_ALPHA_HW_PREMULTIPLY ( 3 << 4) 5415 #define PLANE_CTL_ROTATE_MASK 0x3 5416 #define PLANE_CTL_ROTATE_0 0x0 5417 #define PLANE_CTL_ROTATE_90 0x1 5418 #define PLANE_CTL_ROTATE_180 0x2 5419 #define PLANE_CTL_ROTATE_270 0x3 5420 #define _PLANE_STRIDE_1_A 0x70188 5421 #define _PLANE_STRIDE_2_A 0x70288 5422 #define _PLANE_STRIDE_3_A 0x70388 5423 #define _PLANE_POS_1_A 0x7018c 5424 #define _PLANE_POS_2_A 0x7028c 5425 #define _PLANE_POS_3_A 0x7038c 5426 #define _PLANE_SIZE_1_A 0x70190 5427 #define _PLANE_SIZE_2_A 0x70290 5428 #define _PLANE_SIZE_3_A 0x70390 5429 #define _PLANE_SURF_1_A 0x7019c 5430 #define _PLANE_SURF_2_A 0x7029c 5431 #define _PLANE_SURF_3_A 0x7039c 5432 #define _PLANE_OFFSET_1_A 0x701a4 5433 #define _PLANE_OFFSET_2_A 0x702a4 5434 #define _PLANE_OFFSET_3_A 0x703a4 5435 #define _PLANE_KEYVAL_1_A 0x70194 5436 #define _PLANE_KEYVAL_2_A 0x70294 5437 #define _PLANE_KEYMSK_1_A 0x70198 5438 #define _PLANE_KEYMSK_2_A 0x70298 5439 #define _PLANE_KEYMAX_1_A 0x701a0 5440 #define _PLANE_KEYMAX_2_A 0x702a0 5441 #define _PLANE_BUF_CFG_1_A 0x7027c 5442 #define _PLANE_BUF_CFG_2_A 0x7037c 5443 #define _PLANE_NV12_BUF_CFG_1_A 0x70278 5444 #define _PLANE_NV12_BUF_CFG_2_A 0x70378 5445 5446 #define _PLANE_CTL_1_B 0x71180 5447 #define _PLANE_CTL_2_B 0x71280 5448 #define _PLANE_CTL_3_B 0x71380 5449 #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B) 5450 #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B) 5451 #define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B) 5452 #define PLANE_CTL(pipe, plane) \ 5453 _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) 5454 5455 #define _PLANE_STRIDE_1_B 0x71188 5456 #define _PLANE_STRIDE_2_B 0x71288 5457 #define _PLANE_STRIDE_3_B 0x71388 5458 #define _PLANE_STRIDE_1(pipe) \ 5459 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B) 5460 #define _PLANE_STRIDE_2(pipe) \ 5461 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) 5462 #define _PLANE_STRIDE_3(pipe) \ 5463 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B) 5464 #define PLANE_STRIDE(pipe, plane) \ 5465 _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) 5466 5467 #define _PLANE_POS_1_B 0x7118c 5468 #define _PLANE_POS_2_B 0x7128c 5469 #define _PLANE_POS_3_B 0x7138c 5470 #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B) 5471 #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B) 5472 #define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B) 5473 #define PLANE_POS(pipe, plane) \ 5474 _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) 5475 5476 #define _PLANE_SIZE_1_B 0x71190 5477 #define _PLANE_SIZE_2_B 0x71290 5478 #define _PLANE_SIZE_3_B 0x71390 5479 #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B) 5480 #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) 5481 #define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B) 5482 #define PLANE_SIZE(pipe, plane) \ 5483 _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) 5484 5485 #define _PLANE_SURF_1_B 0x7119c 5486 #define _PLANE_SURF_2_B 0x7129c 5487 #define _PLANE_SURF_3_B 0x7139c 5488 #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B) 5489 #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B) 5490 #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B) 5491 #define PLANE_SURF(pipe, plane) \ 5492 _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe)) 5493 5494 #define _PLANE_OFFSET_1_B 0x711a4 5495 #define _PLANE_OFFSET_2_B 0x712a4 5496 #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B) 5497 #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B) 5498 #define PLANE_OFFSET(pipe, plane) \ 5499 _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe)) 5500 5501 #define _PLANE_KEYVAL_1_B 0x71194 5502 #define _PLANE_KEYVAL_2_B 0x71294 5503 #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B) 5504 #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B) 5505 #define PLANE_KEYVAL(pipe, plane) \ 5506 _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe)) 5507 5508 #define _PLANE_KEYMSK_1_B 0x71198 5509 #define _PLANE_KEYMSK_2_B 0x71298 5510 #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B) 5511 #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B) 5512 #define PLANE_KEYMSK(pipe, plane) \ 5513 _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe)) 5514 5515 #define _PLANE_KEYMAX_1_B 0x711a0 5516 #define _PLANE_KEYMAX_2_B 0x712a0 5517 #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B) 5518 #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B) 5519 #define PLANE_KEYMAX(pipe, plane) \ 5520 _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe)) 5521 5522 #define _PLANE_BUF_CFG_1_B 0x7127c 5523 #define _PLANE_BUF_CFG_2_B 0x7137c 5524 #define _PLANE_BUF_CFG_1(pipe) \ 5525 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B) 5526 #define _PLANE_BUF_CFG_2(pipe) \ 5527 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B) 5528 #define PLANE_BUF_CFG(pipe, plane) \ 5529 _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe)) 5530 5531 #define _PLANE_NV12_BUF_CFG_1_B 0x71278 5532 #define _PLANE_NV12_BUF_CFG_2_B 0x71378 5533 #define _PLANE_NV12_BUF_CFG_1(pipe) \ 5534 _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B) 5535 #define _PLANE_NV12_BUF_CFG_2(pipe) \ 5536 _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B) 5537 #define PLANE_NV12_BUF_CFG(pipe, plane) \ 5538 _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe)) 5539 5540 /* SKL new cursor registers */ 5541 #define _CUR_BUF_CFG_A 0x7017c 5542 #define _CUR_BUF_CFG_B 0x7117c 5543 #define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B) 5544 5545 /* VBIOS regs */ 5546 #define VGACNTRL _MMIO(0x71400) 5547 # define VGA_DISP_DISABLE (1 << 31) 5548 # define VGA_2X_MODE (1 << 30) 5549 # define VGA_PIPE_B_SELECT (1 << 29) 5550 5551 #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400) 5552 5553 /* Ironlake */ 5554 5555 #define CPU_VGACNTRL _MMIO(0x41000) 5556 5557 #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030) 5558 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) 5559 #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */ 5560 #define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */ 5561 #define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */ 5562 #define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */ 5563 #define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */ 5564 #define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0) 5565 #define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0) 5566 #define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0) 5567 #define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0) 5568 5569 /* refresh rate hardware control */ 5570 #define RR_HW_CTL _MMIO(0x45300) 5571 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff 5572 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 5573 5574 #define FDI_PLL_BIOS_0 _MMIO(0x46000) 5575 #define FDI_PLL_FB_CLOCK_MASK 0xff 5576 #define FDI_PLL_BIOS_1 _MMIO(0x46004) 5577 #define FDI_PLL_BIOS_2 _MMIO(0x46008) 5578 #define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c) 5579 #define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010) 5580 #define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014) 5581 5582 #define PCH_3DCGDIS0 _MMIO(0x46020) 5583 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) 5584 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) 5585 5586 #define PCH_3DCGDIS1 _MMIO(0x46024) 5587 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) 5588 5589 #define FDI_PLL_FREQ_CTL _MMIO(0x46030) 5590 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) 5591 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 5592 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff 5593 5594 5595 #define _PIPEA_DATA_M1 0x60030 5596 #define PIPE_DATA_M1_OFFSET 0 5597 #define _PIPEA_DATA_N1 0x60034 5598 #define PIPE_DATA_N1_OFFSET 0 5599 5600 #define _PIPEA_DATA_M2 0x60038 5601 #define PIPE_DATA_M2_OFFSET 0 5602 #define _PIPEA_DATA_N2 0x6003c 5603 #define PIPE_DATA_N2_OFFSET 0 5604 5605 #define _PIPEA_LINK_M1 0x60040 5606 #define PIPE_LINK_M1_OFFSET 0 5607 #define _PIPEA_LINK_N1 0x60044 5608 #define PIPE_LINK_N1_OFFSET 0 5609 5610 #define _PIPEA_LINK_M2 0x60048 5611 #define PIPE_LINK_M2_OFFSET 0 5612 #define _PIPEA_LINK_N2 0x6004c 5613 #define PIPE_LINK_N2_OFFSET 0 5614 5615 /* PIPEB timing regs are same start from 0x61000 */ 5616 5617 #define _PIPEB_DATA_M1 0x61030 5618 #define _PIPEB_DATA_N1 0x61034 5619 #define _PIPEB_DATA_M2 0x61038 5620 #define _PIPEB_DATA_N2 0x6103c 5621 #define _PIPEB_LINK_M1 0x61040 5622 #define _PIPEB_LINK_N1 0x61044 5623 #define _PIPEB_LINK_M2 0x61048 5624 #define _PIPEB_LINK_N2 0x6104c 5625 5626 #define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1) 5627 #define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1) 5628 #define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2) 5629 #define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2) 5630 #define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1) 5631 #define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1) 5632 #define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2) 5633 #define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2) 5634 5635 /* CPU panel fitter */ 5636 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ 5637 #define _PFA_CTL_1 0x68080 5638 #define _PFB_CTL_1 0x68880 5639 #define PF_ENABLE (1<<31) 5640 #define PF_PIPE_SEL_MASK_IVB (3<<29) 5641 #define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29) 5642 #define PF_FILTER_MASK (3<<23) 5643 #define PF_FILTER_PROGRAMMED (0<<23) 5644 #define PF_FILTER_MED_3x3 (1<<23) 5645 #define PF_FILTER_EDGE_ENHANCE (2<<23) 5646 #define PF_FILTER_EDGE_SOFTEN (3<<23) 5647 #define _PFA_WIN_SZ 0x68074 5648 #define _PFB_WIN_SZ 0x68874 5649 #define _PFA_WIN_POS 0x68070 5650 #define _PFB_WIN_POS 0x68870 5651 #define _PFA_VSCALE 0x68084 5652 #define _PFB_VSCALE 0x68884 5653 #define _PFA_HSCALE 0x68090 5654 #define _PFB_HSCALE 0x68890 5655 5656 #define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) 5657 #define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) 5658 #define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) 5659 #define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) 5660 #define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) 5661 5662 #define _PSA_CTL 0x68180 5663 #define _PSB_CTL 0x68980 5664 #define PS_ENABLE (1<<31) 5665 #define _PSA_WIN_SZ 0x68174 5666 #define _PSB_WIN_SZ 0x68974 5667 #define _PSA_WIN_POS 0x68170 5668 #define _PSB_WIN_POS 0x68970 5669 5670 #define PS_CTL(pipe) _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL) 5671 #define PS_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ) 5672 #define PS_WIN_POS(pipe) _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS) 5673 5674 /* 5675 * Skylake scalers 5676 */ 5677 #define _PS_1A_CTRL 0x68180 5678 #define _PS_2A_CTRL 0x68280 5679 #define _PS_1B_CTRL 0x68980 5680 #define _PS_2B_CTRL 0x68A80 5681 #define _PS_1C_CTRL 0x69180 5682 #define PS_SCALER_EN (1 << 31) 5683 #define PS_SCALER_MODE_MASK (3 << 28) 5684 #define PS_SCALER_MODE_DYN (0 << 28) 5685 #define PS_SCALER_MODE_HQ (1 << 28) 5686 #define PS_PLANE_SEL_MASK (7 << 25) 5687 #define PS_PLANE_SEL(plane) (((plane) + 1) << 25) 5688 #define PS_FILTER_MASK (3 << 23) 5689 #define PS_FILTER_MEDIUM (0 << 23) 5690 #define PS_FILTER_EDGE_ENHANCE (2 << 23) 5691 #define PS_FILTER_BILINEAR (3 << 23) 5692 #define PS_VERT3TAP (1 << 21) 5693 #define PS_VERT_INT_INVERT_FIELD1 (0 << 20) 5694 #define PS_VERT_INT_INVERT_FIELD0 (1 << 20) 5695 #define PS_PWRUP_PROGRESS (1 << 17) 5696 #define PS_V_FILTER_BYPASS (1 << 8) 5697 #define PS_VADAPT_EN (1 << 7) 5698 #define PS_VADAPT_MODE_MASK (3 << 5) 5699 #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5) 5700 #define PS_VADAPT_MODE_MOD_ADAPT (1 << 5) 5701 #define PS_VADAPT_MODE_MOST_ADAPT (3 << 5) 5702 5703 #define _PS_PWR_GATE_1A 0x68160 5704 #define _PS_PWR_GATE_2A 0x68260 5705 #define _PS_PWR_GATE_1B 0x68960 5706 #define _PS_PWR_GATE_2B 0x68A60 5707 #define _PS_PWR_GATE_1C 0x69160 5708 #define PS_PWR_GATE_DIS_OVERRIDE (1 << 31) 5709 #define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3) 5710 #define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3) 5711 #define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3) 5712 #define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3) 5713 #define PS_PWR_GATE_SLPEN_8 0 5714 #define PS_PWR_GATE_SLPEN_16 1 5715 #define PS_PWR_GATE_SLPEN_24 2 5716 #define PS_PWR_GATE_SLPEN_32 3 5717 5718 #define _PS_WIN_POS_1A 0x68170 5719 #define _PS_WIN_POS_2A 0x68270 5720 #define _PS_WIN_POS_1B 0x68970 5721 #define _PS_WIN_POS_2B 0x68A70 5722 #define _PS_WIN_POS_1C 0x69170 5723 5724 #define _PS_WIN_SZ_1A 0x68174 5725 #define _PS_WIN_SZ_2A 0x68274 5726 #define _PS_WIN_SZ_1B 0x68974 5727 #define _PS_WIN_SZ_2B 0x68A74 5728 #define _PS_WIN_SZ_1C 0x69174 5729 5730 #define _PS_VSCALE_1A 0x68184 5731 #define _PS_VSCALE_2A 0x68284 5732 #define _PS_VSCALE_1B 0x68984 5733 #define _PS_VSCALE_2B 0x68A84 5734 #define _PS_VSCALE_1C 0x69184 5735 5736 #define _PS_HSCALE_1A 0x68190 5737 #define _PS_HSCALE_2A 0x68290 5738 #define _PS_HSCALE_1B 0x68990 5739 #define _PS_HSCALE_2B 0x68A90 5740 #define _PS_HSCALE_1C 0x69190 5741 5742 #define _PS_VPHASE_1A 0x68188 5743 #define _PS_VPHASE_2A 0x68288 5744 #define _PS_VPHASE_1B 0x68988 5745 #define _PS_VPHASE_2B 0x68A88 5746 #define _PS_VPHASE_1C 0x69188 5747 5748 #define _PS_HPHASE_1A 0x68194 5749 #define _PS_HPHASE_2A 0x68294 5750 #define _PS_HPHASE_1B 0x68994 5751 #define _PS_HPHASE_2B 0x68A94 5752 #define _PS_HPHASE_1C 0x69194 5753 5754 #define _PS_ECC_STAT_1A 0x681D0 5755 #define _PS_ECC_STAT_2A 0x682D0 5756 #define _PS_ECC_STAT_1B 0x689D0 5757 #define _PS_ECC_STAT_2B 0x68AD0 5758 #define _PS_ECC_STAT_1C 0x691D0 5759 5760 #define _ID(id, a, b) ((a) + (id)*((b)-(a))) 5761 #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \ 5762 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \ 5763 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL)) 5764 #define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \ 5765 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \ 5766 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B)) 5767 #define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \ 5768 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \ 5769 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B)) 5770 #define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \ 5771 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \ 5772 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B)) 5773 #define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \ 5774 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \ 5775 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B)) 5776 #define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \ 5777 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \ 5778 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B)) 5779 #define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \ 5780 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \ 5781 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B)) 5782 #define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \ 5783 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \ 5784 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B)) 5785 #define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \ 5786 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \ 5787 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)) 5788 5789 /* legacy palette */ 5790 #define _LGC_PALETTE_A 0x4a000 5791 #define _LGC_PALETTE_B 0x4a800 5792 #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4) 5793 5794 #define _GAMMA_MODE_A 0x4a480 5795 #define _GAMMA_MODE_B 0x4ac80 5796 #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) 5797 #define GAMMA_MODE_MODE_MASK (3 << 0) 5798 #define GAMMA_MODE_MODE_8BIT (0 << 0) 5799 #define GAMMA_MODE_MODE_10BIT (1 << 0) 5800 #define GAMMA_MODE_MODE_12BIT (2 << 0) 5801 #define GAMMA_MODE_MODE_SPLIT (3 << 0) 5802 5803 /* DMC/CSR */ 5804 #define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4) 5805 #define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0 5806 #define CSR_HTP_ADDR_SKL 0x00500034 5807 #define CSR_SSP_BASE _MMIO(0x8F074) 5808 #define CSR_HTP_SKL _MMIO(0x8F004) 5809 #define CSR_LAST_WRITE _MMIO(0x8F034) 5810 #define CSR_LAST_WRITE_VALUE 0xc003b400 5811 /* MMIO address range for CSR program (0x80000 - 0x82FFF) */ 5812 #define CSR_MMIO_START_RANGE 0x80000 5813 #define CSR_MMIO_END_RANGE 0x8FFFF 5814 #define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030) 5815 #define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C) 5816 #define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038) 5817 5818 /* interrupts */ 5819 #define DE_MASTER_IRQ_CONTROL (1 << 31) 5820 #define DE_SPRITEB_FLIP_DONE (1 << 29) 5821 #define DE_SPRITEA_FLIP_DONE (1 << 28) 5822 #define DE_PLANEB_FLIP_DONE (1 << 27) 5823 #define DE_PLANEA_FLIP_DONE (1 << 26) 5824 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane))) 5825 #define DE_PCU_EVENT (1 << 25) 5826 #define DE_GTT_FAULT (1 << 24) 5827 #define DE_POISON (1 << 23) 5828 #define DE_PERFORM_COUNTER (1 << 22) 5829 #define DE_PCH_EVENT (1 << 21) 5830 #define DE_AUX_CHANNEL_A (1 << 20) 5831 #define DE_DP_A_HOTPLUG (1 << 19) 5832 #define DE_GSE (1 << 18) 5833 #define DE_PIPEB_VBLANK (1 << 15) 5834 #define DE_PIPEB_EVEN_FIELD (1 << 14) 5835 #define DE_PIPEB_ODD_FIELD (1 << 13) 5836 #define DE_PIPEB_LINE_COMPARE (1 << 12) 5837 #define DE_PIPEB_VSYNC (1 << 11) 5838 #define DE_PIPEB_CRC_DONE (1 << 10) 5839 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) 5840 #define DE_PIPEA_VBLANK (1 << 7) 5841 #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8*(pipe))) 5842 #define DE_PIPEA_EVEN_FIELD (1 << 6) 5843 #define DE_PIPEA_ODD_FIELD (1 << 5) 5844 #define DE_PIPEA_LINE_COMPARE (1 << 4) 5845 #define DE_PIPEA_VSYNC (1 << 3) 5846 #define DE_PIPEA_CRC_DONE (1 << 2) 5847 #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8*(pipe))) 5848 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) 5849 #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8*(pipe))) 5850 5851 /* More Ivybridge lolz */ 5852 #define DE_ERR_INT_IVB (1<<30) 5853 #define DE_GSE_IVB (1<<29) 5854 #define DE_PCH_EVENT_IVB (1<<28) 5855 #define DE_DP_A_HOTPLUG_IVB (1<<27) 5856 #define DE_AUX_CHANNEL_A_IVB (1<<26) 5857 #define DE_SPRITEC_FLIP_DONE_IVB (1<<14) 5858 #define DE_PLANEC_FLIP_DONE_IVB (1<<13) 5859 #define DE_PIPEC_VBLANK_IVB (1<<10) 5860 #define DE_SPRITEB_FLIP_DONE_IVB (1<<9) 5861 #define DE_PLANEB_FLIP_DONE_IVB (1<<8) 5862 #define DE_PIPEB_VBLANK_IVB (1<<5) 5863 #define DE_SPRITEA_FLIP_DONE_IVB (1<<4) 5864 #define DE_PLANEA_FLIP_DONE_IVB (1<<3) 5865 #define DE_PLANE_FLIP_DONE_IVB(plane) (1<< (3 + 5*(plane))) 5866 #define DE_PIPEA_VBLANK_IVB (1<<0) 5867 #define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5)) 5868 5869 #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */ 5870 #define MASTER_INTERRUPT_ENABLE (1<<31) 5871 5872 #define DEISR _MMIO(0x44000) 5873 #define DEIMR _MMIO(0x44004) 5874 #define DEIIR _MMIO(0x44008) 5875 #define DEIER _MMIO(0x4400c) 5876 5877 #define GTISR _MMIO(0x44010) 5878 #define GTIMR _MMIO(0x44014) 5879 #define GTIIR _MMIO(0x44018) 5880 #define GTIER _MMIO(0x4401c) 5881 5882 #define GEN8_MASTER_IRQ _MMIO(0x44200) 5883 #define GEN8_MASTER_IRQ_CONTROL (1<<31) 5884 #define GEN8_PCU_IRQ (1<<30) 5885 #define GEN8_DE_PCH_IRQ (1<<23) 5886 #define GEN8_DE_MISC_IRQ (1<<22) 5887 #define GEN8_DE_PORT_IRQ (1<<20) 5888 #define GEN8_DE_PIPE_C_IRQ (1<<18) 5889 #define GEN8_DE_PIPE_B_IRQ (1<<17) 5890 #define GEN8_DE_PIPE_A_IRQ (1<<16) 5891 #define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+(pipe))) 5892 #define GEN8_GT_VECS_IRQ (1<<6) 5893 #define GEN8_GT_PM_IRQ (1<<4) 5894 #define GEN8_GT_VCS2_IRQ (1<<3) 5895 #define GEN8_GT_VCS1_IRQ (1<<2) 5896 #define GEN8_GT_BCS_IRQ (1<<1) 5897 #define GEN8_GT_RCS_IRQ (1<<0) 5898 5899 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which))) 5900 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which))) 5901 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which))) 5902 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which))) 5903 5904 #define GEN8_RCS_IRQ_SHIFT 0 5905 #define GEN8_BCS_IRQ_SHIFT 16 5906 #define GEN8_VCS1_IRQ_SHIFT 0 5907 #define GEN8_VCS2_IRQ_SHIFT 16 5908 #define GEN8_VECS_IRQ_SHIFT 0 5909 #define GEN8_WD_IRQ_SHIFT 16 5910 5911 #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe))) 5912 #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe))) 5913 #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe))) 5914 #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe))) 5915 #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31) 5916 #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29) 5917 #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28) 5918 #define GEN8_PIPE_CURSOR_FAULT (1 << 10) 5919 #define GEN8_PIPE_SPRITE_FAULT (1 << 9) 5920 #define GEN8_PIPE_PRIMARY_FAULT (1 << 8) 5921 #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5) 5922 #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4) 5923 #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) 5924 #define GEN8_PIPE_VSYNC (1 << 1) 5925 #define GEN8_PIPE_VBLANK (1 << 0) 5926 #define GEN9_PIPE_CURSOR_FAULT (1 << 11) 5927 #define GEN9_PIPE_PLANE4_FAULT (1 << 10) 5928 #define GEN9_PIPE_PLANE3_FAULT (1 << 9) 5929 #define GEN9_PIPE_PLANE2_FAULT (1 << 8) 5930 #define GEN9_PIPE_PLANE1_FAULT (1 << 7) 5931 #define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6) 5932 #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5) 5933 #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4) 5934 #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3) 5935 #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p))) 5936 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ 5937 (GEN8_PIPE_CURSOR_FAULT | \ 5938 GEN8_PIPE_SPRITE_FAULT | \ 5939 GEN8_PIPE_PRIMARY_FAULT) 5940 #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \ 5941 (GEN9_PIPE_CURSOR_FAULT | \ 5942 GEN9_PIPE_PLANE4_FAULT | \ 5943 GEN9_PIPE_PLANE3_FAULT | \ 5944 GEN9_PIPE_PLANE2_FAULT | \ 5945 GEN9_PIPE_PLANE1_FAULT) 5946 5947 #define GEN8_DE_PORT_ISR _MMIO(0x44440) 5948 #define GEN8_DE_PORT_IMR _MMIO(0x44444) 5949 #define GEN8_DE_PORT_IIR _MMIO(0x44448) 5950 #define GEN8_DE_PORT_IER _MMIO(0x4444c) 5951 #define GEN9_AUX_CHANNEL_D (1 << 27) 5952 #define GEN9_AUX_CHANNEL_C (1 << 26) 5953 #define GEN9_AUX_CHANNEL_B (1 << 25) 5954 #define BXT_DE_PORT_HP_DDIC (1 << 5) 5955 #define BXT_DE_PORT_HP_DDIB (1 << 4) 5956 #define BXT_DE_PORT_HP_DDIA (1 << 3) 5957 #define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDIA | \ 5958 BXT_DE_PORT_HP_DDIB | \ 5959 BXT_DE_PORT_HP_DDIC) 5960 #define GEN8_PORT_DP_A_HOTPLUG (1 << 3) 5961 #define BXT_DE_PORT_GMBUS (1 << 1) 5962 #define GEN8_AUX_CHANNEL_A (1 << 0) 5963 5964 #define GEN8_DE_MISC_ISR _MMIO(0x44460) 5965 #define GEN8_DE_MISC_IMR _MMIO(0x44464) 5966 #define GEN8_DE_MISC_IIR _MMIO(0x44468) 5967 #define GEN8_DE_MISC_IER _MMIO(0x4446c) 5968 #define GEN8_DE_MISC_GSE (1 << 27) 5969 5970 #define GEN8_PCU_ISR _MMIO(0x444e0) 5971 #define GEN8_PCU_IMR _MMIO(0x444e4) 5972 #define GEN8_PCU_IIR _MMIO(0x444e8) 5973 #define GEN8_PCU_IER _MMIO(0x444ec) 5974 5975 #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004) 5976 /* Required on all Ironlake and Sandybridge according to the B-Spec. */ 5977 #define ILK_ELPIN_409_SELECT (1 << 25) 5978 #define ILK_DPARB_GATE (1<<22) 5979 #define ILK_VSDPFD_FULL (1<<21) 5980 #define FUSE_STRAP _MMIO(0x42014) 5981 #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31) 5982 #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30) 5983 #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29) 5984 #define IVB_PIPE_C_DISABLE (1 << 28) 5985 #define ILK_HDCP_DISABLE (1 << 25) 5986 #define ILK_eDP_A_DISABLE (1 << 24) 5987 #define HSW_CDCLK_LIMIT (1 << 24) 5988 #define ILK_DESKTOP (1 << 23) 5989 5990 #define ILK_DSPCLK_GATE_D _MMIO(0x42020) 5991 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) 5992 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) 5993 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8) 5994 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7) 5995 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5) 5996 5997 #define IVB_CHICKEN3 _MMIO(0x4200c) 5998 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) 5999 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) 6000 6001 #define CHICKEN_PAR1_1 _MMIO(0x42080) 6002 #define DPA_MASK_VBLANK_SRD (1 << 15) 6003 #define FORCE_ARB_IDLE_PLANES (1 << 14) 6004 6005 #define _CHICKEN_PIPESL_1_A 0x420b0 6006 #define _CHICKEN_PIPESL_1_B 0x420b4 6007 #define HSW_FBCQ_DIS (1 << 22) 6008 #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0) 6009 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) 6010 6011 #define DISP_ARB_CTL _MMIO(0x45000) 6012 #define DISP_TILE_SURFACE_SWIZZLING (1<<13) 6013 #define DISP_FBC_WM_DIS (1<<15) 6014 #define DISP_ARB_CTL2 _MMIO(0x45004) 6015 #define DISP_DATA_PARTITION_5_6 (1<<6) 6016 #define DBUF_CTL _MMIO(0x45008) 6017 #define DBUF_POWER_REQUEST (1<<31) 6018 #define DBUF_POWER_STATE (1<<30) 6019 #define GEN7_MSG_CTL _MMIO(0x45010) 6020 #define WAIT_FOR_PCH_RESET_ACK (1<<1) 6021 #define WAIT_FOR_PCH_FLR_ACK (1<<0) 6022 #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) 6023 #define RESET_PCH_HANDSHAKE_ENABLE (1<<4) 6024 6025 #define SKL_DFSM _MMIO(0x51000) 6026 #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23) 6027 #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23) 6028 #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23) 6029 #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23) 6030 #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23) 6031 #define SKL_DFSM_PIPE_A_DISABLE (1 << 30) 6032 #define SKL_DFSM_PIPE_B_DISABLE (1 << 21) 6033 #define SKL_DFSM_PIPE_C_DISABLE (1 << 28) 6034 6035 #define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0) 6036 #define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1<<14) 6037 6038 #define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4) 6039 #define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8) 6040 6041 #define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec) 6042 #define GEN8_CS_CHICKEN1 _MMIO(0x2580) 6043 6044 /* GEN7 chicken */ 6045 #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010) 6046 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26)) 6047 # define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14) 6048 #define COMMON_SLICE_CHICKEN2 _MMIO(0x7014) 6049 # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0) 6050 6051 #define HIZ_CHICKEN _MMIO(0x7018) 6052 # define CHV_HZ_8X8_MODE_IN_1X (1<<15) 6053 # define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE (1<<3) 6054 6055 #define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308) 6056 #define DISABLE_PIXEL_MASK_CAMMING (1<<14) 6057 6058 #define GEN7_L3SQCREG1 _MMIO(0xB010) 6059 #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000 6060 6061 #define GEN8_L3SQCREG1 _MMIO(0xB100) 6062 #define BDW_WA_L3SQCREG1_DEFAULT 0x784000 6063 6064 #define GEN7_L3CNTLREG1 _MMIO(0xB01C) 6065 #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C 6066 #define GEN7_L3AGDIS (1<<19) 6067 #define GEN7_L3CNTLREG2 _MMIO(0xB020) 6068 #define GEN7_L3CNTLREG3 _MMIO(0xB024) 6069 6070 #define GEN7_L3_CHICKEN_MODE_REGISTER _MMIO(0xB030) 6071 #define GEN7_WA_L3_CHICKEN_MODE 0x20000000 6072 6073 #define GEN7_L3SQCREG4 _MMIO(0xb034) 6074 #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27) 6075 6076 #define GEN8_L3SQCREG4 _MMIO(0xb118) 6077 #define GEN8_LQSC_RO_PERF_DIS (1<<27) 6078 #define GEN8_LQSC_FLUSH_COHERENT_LINES (1<<21) 6079 6080 /* GEN8 chicken */ 6081 #define HDC_CHICKEN0 _MMIO(0x7300) 6082 #define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15) 6083 #define HDC_FENCE_DEST_SLM_DISABLE (1<<14) 6084 #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11) 6085 #define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1<<5) 6086 #define HDC_FORCE_NON_COHERENT (1<<4) 6087 #define HDC_BARRIER_PERFORMANCE_DISABLE (1<<10) 6088 6089 #define GEN8_HDC_CHICKEN1 _MMIO(0x7304) 6090 6091 /* GEN9 chicken */ 6092 #define SLICE_ECO_CHICKEN0 _MMIO(0x7308) 6093 #define PIXEL_MASK_CAMMING_DISABLE (1 << 14) 6094 6095 /* WaCatErrorRejectionIssue */ 6096 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030) 6097 #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11) 6098 6099 #define HSW_SCRATCH1 _MMIO(0xb038) 6100 #define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27) 6101 6102 #define BDW_SCRATCH1 _MMIO(0xb11c) 6103 #define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1<<2) 6104 6105 /* PCH */ 6106 6107 /* south display engine interrupt: IBX */ 6108 #define SDE_AUDIO_POWER_D (1 << 27) 6109 #define SDE_AUDIO_POWER_C (1 << 26) 6110 #define SDE_AUDIO_POWER_B (1 << 25) 6111 #define SDE_AUDIO_POWER_SHIFT (25) 6112 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) 6113 #define SDE_GMBUS (1 << 24) 6114 #define SDE_AUDIO_HDCP_TRANSB (1 << 23) 6115 #define SDE_AUDIO_HDCP_TRANSA (1 << 22) 6116 #define SDE_AUDIO_HDCP_MASK (3 << 22) 6117 #define SDE_AUDIO_TRANSB (1 << 21) 6118 #define SDE_AUDIO_TRANSA (1 << 20) 6119 #define SDE_AUDIO_TRANS_MASK (3 << 20) 6120 #define SDE_POISON (1 << 19) 6121 /* 18 reserved */ 6122 #define SDE_FDI_RXB (1 << 17) 6123 #define SDE_FDI_RXA (1 << 16) 6124 #define SDE_FDI_MASK (3 << 16) 6125 #define SDE_AUXD (1 << 15) 6126 #define SDE_AUXC (1 << 14) 6127 #define SDE_AUXB (1 << 13) 6128 #define SDE_AUX_MASK (7 << 13) 6129 /* 12 reserved */ 6130 #define SDE_CRT_HOTPLUG (1 << 11) 6131 #define SDE_PORTD_HOTPLUG (1 << 10) 6132 #define SDE_PORTC_HOTPLUG (1 << 9) 6133 #define SDE_PORTB_HOTPLUG (1 << 8) 6134 #define SDE_SDVOB_HOTPLUG (1 << 6) 6135 #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \ 6136 SDE_SDVOB_HOTPLUG | \ 6137 SDE_PORTB_HOTPLUG | \ 6138 SDE_PORTC_HOTPLUG | \ 6139 SDE_PORTD_HOTPLUG) 6140 #define SDE_TRANSB_CRC_DONE (1 << 5) 6141 #define SDE_TRANSB_CRC_ERR (1 << 4) 6142 #define SDE_TRANSB_FIFO_UNDER (1 << 3) 6143 #define SDE_TRANSA_CRC_DONE (1 << 2) 6144 #define SDE_TRANSA_CRC_ERR (1 << 1) 6145 #define SDE_TRANSA_FIFO_UNDER (1 << 0) 6146 #define SDE_TRANS_MASK (0x3f) 6147 6148 /* south display engine interrupt: CPT/PPT */ 6149 #define SDE_AUDIO_POWER_D_CPT (1 << 31) 6150 #define SDE_AUDIO_POWER_C_CPT (1 << 30) 6151 #define SDE_AUDIO_POWER_B_CPT (1 << 29) 6152 #define SDE_AUDIO_POWER_SHIFT_CPT 29 6153 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29) 6154 #define SDE_AUXD_CPT (1 << 27) 6155 #define SDE_AUXC_CPT (1 << 26) 6156 #define SDE_AUXB_CPT (1 << 25) 6157 #define SDE_AUX_MASK_CPT (7 << 25) 6158 #define SDE_PORTE_HOTPLUG_SPT (1 << 25) 6159 #define SDE_PORTA_HOTPLUG_SPT (1 << 24) 6160 #define SDE_PORTD_HOTPLUG_CPT (1 << 23) 6161 #define SDE_PORTC_HOTPLUG_CPT (1 << 22) 6162 #define SDE_PORTB_HOTPLUG_CPT (1 << 21) 6163 #define SDE_CRT_HOTPLUG_CPT (1 << 19) 6164 #define SDE_SDVOB_HOTPLUG_CPT (1 << 18) 6165 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ 6166 SDE_SDVOB_HOTPLUG_CPT | \ 6167 SDE_PORTD_HOTPLUG_CPT | \ 6168 SDE_PORTC_HOTPLUG_CPT | \ 6169 SDE_PORTB_HOTPLUG_CPT) 6170 #define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \ 6171 SDE_PORTD_HOTPLUG_CPT | \ 6172 SDE_PORTC_HOTPLUG_CPT | \ 6173 SDE_PORTB_HOTPLUG_CPT | \ 6174 SDE_PORTA_HOTPLUG_SPT) 6175 #define SDE_GMBUS_CPT (1 << 17) 6176 #define SDE_ERROR_CPT (1 << 16) 6177 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10) 6178 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9) 6179 #define SDE_FDI_RXC_CPT (1 << 8) 6180 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6) 6181 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5) 6182 #define SDE_FDI_RXB_CPT (1 << 4) 6183 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2) 6184 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1) 6185 #define SDE_FDI_RXA_CPT (1 << 0) 6186 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \ 6187 SDE_AUDIO_CP_REQ_B_CPT | \ 6188 SDE_AUDIO_CP_REQ_A_CPT) 6189 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \ 6190 SDE_AUDIO_CP_CHG_B_CPT | \ 6191 SDE_AUDIO_CP_CHG_A_CPT) 6192 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \ 6193 SDE_FDI_RXB_CPT | \ 6194 SDE_FDI_RXA_CPT) 6195 6196 #define SDEISR _MMIO(0xc4000) 6197 #define SDEIMR _MMIO(0xc4004) 6198 #define SDEIIR _MMIO(0xc4008) 6199 #define SDEIER _MMIO(0xc400c) 6200 6201 #define SERR_INT _MMIO(0xc4040) 6202 #define SERR_INT_POISON (1<<31) 6203 #define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6) 6204 #define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3) 6205 #define SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0) 6206 #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<((pipe)*3)) 6207 6208 /* digital port hotplug */ 6209 #define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */ 6210 #define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */ 6211 #define BXT_DDIA_HPD_INVERT (1 << 27) 6212 #define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */ 6213 #define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */ 6214 #define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */ 6215 #define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */ 6216 #define PORTD_HOTPLUG_ENABLE (1 << 20) 6217 #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */ 6218 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */ 6219 #define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */ 6220 #define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */ 6221 #define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */ 6222 #define PORTD_HOTPLUG_STATUS_MASK (3 << 16) 6223 #define PORTD_HOTPLUG_NO_DETECT (0 << 16) 6224 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) 6225 #define PORTD_HOTPLUG_LONG_DETECT (2 << 16) 6226 #define PORTC_HOTPLUG_ENABLE (1 << 12) 6227 #define BXT_DDIC_HPD_INVERT (1 << 11) 6228 #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */ 6229 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */ 6230 #define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */ 6231 #define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */ 6232 #define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */ 6233 #define PORTC_HOTPLUG_STATUS_MASK (3 << 8) 6234 #define PORTC_HOTPLUG_NO_DETECT (0 << 8) 6235 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) 6236 #define PORTC_HOTPLUG_LONG_DETECT (2 << 8) 6237 #define PORTB_HOTPLUG_ENABLE (1 << 4) 6238 #define BXT_DDIB_HPD_INVERT (1 << 3) 6239 #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */ 6240 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */ 6241 #define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */ 6242 #define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */ 6243 #define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */ 6244 #define PORTB_HOTPLUG_STATUS_MASK (3 << 0) 6245 #define PORTB_HOTPLUG_NO_DETECT (0 << 0) 6246 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) 6247 #define PORTB_HOTPLUG_LONG_DETECT (2 << 0) 6248 #define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \ 6249 BXT_DDIB_HPD_INVERT | \ 6250 BXT_DDIC_HPD_INVERT) 6251 6252 #define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */ 6253 #define PORTE_HOTPLUG_ENABLE (1 << 4) 6254 #define PORTE_HOTPLUG_STATUS_MASK (3 << 0) 6255 #define PORTE_HOTPLUG_NO_DETECT (0 << 0) 6256 #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0) 6257 #define PORTE_HOTPLUG_LONG_DETECT (2 << 0) 6258 6259 #define PCH_GPIOA _MMIO(0xc5010) 6260 #define PCH_GPIOB _MMIO(0xc5014) 6261 #define PCH_GPIOC _MMIO(0xc5018) 6262 #define PCH_GPIOD _MMIO(0xc501c) 6263 #define PCH_GPIOE _MMIO(0xc5020) 6264 #define PCH_GPIOF _MMIO(0xc5024) 6265 6266 #define PCH_GMBUS0 _MMIO(0xc5100) 6267 #define PCH_GMBUS1 _MMIO(0xc5104) 6268 #define PCH_GMBUS2 _MMIO(0xc5108) 6269 #define PCH_GMBUS3 _MMIO(0xc510c) 6270 #define PCH_GMBUS4 _MMIO(0xc5110) 6271 #define PCH_GMBUS5 _MMIO(0xc5120) 6272 6273 #define _PCH_DPLL_A 0xc6014 6274 #define _PCH_DPLL_B 0xc6018 6275 #define PCH_DPLL(pll) _MMIO(pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) 6276 6277 #define _PCH_FPA0 0xc6040 6278 #define FP_CB_TUNE (0x3<<22) 6279 #define _PCH_FPA1 0xc6044 6280 #define _PCH_FPB0 0xc6048 6281 #define _PCH_FPB1 0xc604c 6282 #define PCH_FP0(pll) _MMIO(pll == 0 ? _PCH_FPA0 : _PCH_FPB0) 6283 #define PCH_FP1(pll) _MMIO(pll == 0 ? _PCH_FPA1 : _PCH_FPB1) 6284 6285 #define PCH_DPLL_TEST _MMIO(0xc606c) 6286 6287 #define PCH_DREF_CONTROL _MMIO(0xC6200) 6288 #define DREF_CONTROL_MASK 0x7fc3 6289 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13) 6290 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13) 6291 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13) 6292 #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13) 6293 #define DREF_SSC_SOURCE_DISABLE (0<<11) 6294 #define DREF_SSC_SOURCE_ENABLE (2<<11) 6295 #define DREF_SSC_SOURCE_MASK (3<<11) 6296 #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) 6297 #define DREF_NONSPREAD_CK505_ENABLE (1<<9) 6298 #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) 6299 #define DREF_NONSPREAD_SOURCE_MASK (3<<9) 6300 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) 6301 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) 6302 #define DREF_SUPERSPREAD_SOURCE_MASK (3<<7) 6303 #define DREF_SSC4_DOWNSPREAD (0<<6) 6304 #define DREF_SSC4_CENTERSPREAD (1<<6) 6305 #define DREF_SSC1_DISABLE (0<<1) 6306 #define DREF_SSC1_ENABLE (1<<1) 6307 #define DREF_SSC4_DISABLE (0) 6308 #define DREF_SSC4_ENABLE (1) 6309 6310 #define PCH_RAWCLK_FREQ _MMIO(0xc6204) 6311 #define FDL_TP1_TIMER_SHIFT 12 6312 #define FDL_TP1_TIMER_MASK (3<<12) 6313 #define FDL_TP2_TIMER_SHIFT 10 6314 #define FDL_TP2_TIMER_MASK (3<<10) 6315 #define RAWCLK_FREQ_MASK 0x3ff 6316 6317 #define PCH_DPLL_TMR_CFG _MMIO(0xc6208) 6318 6319 #define PCH_SSC4_PARMS _MMIO(0xc6210) 6320 #define PCH_SSC4_AUX_PARMS _MMIO(0xc6214) 6321 6322 #define PCH_DPLL_SEL _MMIO(0xc7000) 6323 #define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4)) 6324 #define TRANS_DPLLA_SEL(pipe) 0 6325 #define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3)) 6326 6327 /* transcoder */ 6328 6329 #define _PCH_TRANS_HTOTAL_A 0xe0000 6330 #define TRANS_HTOTAL_SHIFT 16 6331 #define TRANS_HACTIVE_SHIFT 0 6332 #define _PCH_TRANS_HBLANK_A 0xe0004 6333 #define TRANS_HBLANK_END_SHIFT 16 6334 #define TRANS_HBLANK_START_SHIFT 0 6335 #define _PCH_TRANS_HSYNC_A 0xe0008 6336 #define TRANS_HSYNC_END_SHIFT 16 6337 #define TRANS_HSYNC_START_SHIFT 0 6338 #define _PCH_TRANS_VTOTAL_A 0xe000c 6339 #define TRANS_VTOTAL_SHIFT 16 6340 #define TRANS_VACTIVE_SHIFT 0 6341 #define _PCH_TRANS_VBLANK_A 0xe0010 6342 #define TRANS_VBLANK_END_SHIFT 16 6343 #define TRANS_VBLANK_START_SHIFT 0 6344 #define _PCH_TRANS_VSYNC_A 0xe0014 6345 #define TRANS_VSYNC_END_SHIFT 16 6346 #define TRANS_VSYNC_START_SHIFT 0 6347 #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028 6348 6349 #define _PCH_TRANSA_DATA_M1 0xe0030 6350 #define _PCH_TRANSA_DATA_N1 0xe0034 6351 #define _PCH_TRANSA_DATA_M2 0xe0038 6352 #define _PCH_TRANSA_DATA_N2 0xe003c 6353 #define _PCH_TRANSA_LINK_M1 0xe0040 6354 #define _PCH_TRANSA_LINK_N1 0xe0044 6355 #define _PCH_TRANSA_LINK_M2 0xe0048 6356 #define _PCH_TRANSA_LINK_N2 0xe004c 6357 6358 /* Per-transcoder DIP controls (PCH) */ 6359 #define _VIDEO_DIP_CTL_A 0xe0200 6360 #define _VIDEO_DIP_DATA_A 0xe0208 6361 #define _VIDEO_DIP_GCP_A 0xe0210 6362 #define GCP_COLOR_INDICATION (1 << 2) 6363 #define GCP_DEFAULT_PHASE_ENABLE (1 << 1) 6364 #define GCP_AV_MUTE (1 << 0) 6365 6366 #define _VIDEO_DIP_CTL_B 0xe1200 6367 #define _VIDEO_DIP_DATA_B 0xe1208 6368 #define _VIDEO_DIP_GCP_B 0xe1210 6369 6370 #define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) 6371 #define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) 6372 #define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) 6373 6374 /* Per-transcoder DIP controls (VLV) */ 6375 #define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200) 6376 #define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208) 6377 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210) 6378 6379 #define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170) 6380 #define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174) 6381 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178) 6382 6383 #define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0) 6384 #define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4) 6385 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8) 6386 6387 #define VLV_TVIDEO_DIP_CTL(pipe) \ 6388 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \ 6389 _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C) 6390 #define VLV_TVIDEO_DIP_DATA(pipe) \ 6391 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \ 6392 _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C) 6393 #define VLV_TVIDEO_DIP_GCP(pipe) \ 6394 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \ 6395 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C) 6396 6397 /* Haswell DIP controls */ 6398 6399 #define _HSW_VIDEO_DIP_CTL_A 0x60200 6400 #define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220 6401 #define _HSW_VIDEO_DIP_VS_DATA_A 0x60260 6402 #define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 6403 #define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 6404 #define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320 6405 #define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240 6406 #define _HSW_VIDEO_DIP_VS_ECC_A 0x60280 6407 #define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 6408 #define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300 6409 #define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344 6410 #define _HSW_VIDEO_DIP_GCP_A 0x60210 6411 6412 #define _HSW_VIDEO_DIP_CTL_B 0x61200 6413 #define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220 6414 #define _HSW_VIDEO_DIP_VS_DATA_B 0x61260 6415 #define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 6416 #define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 6417 #define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320 6418 #define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240 6419 #define _HSW_VIDEO_DIP_VS_ECC_B 0x61280 6420 #define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 6421 #define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300 6422 #define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344 6423 #define _HSW_VIDEO_DIP_GCP_B 0x61210 6424 6425 #define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A) 6426 #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4) 6427 #define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4) 6428 #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4) 6429 #define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A) 6430 #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4) 6431 6432 #define _HSW_STEREO_3D_CTL_A 0x70020 6433 #define S3D_ENABLE (1<<31) 6434 #define _HSW_STEREO_3D_CTL_B 0x71020 6435 6436 #define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A) 6437 6438 #define _PCH_TRANS_HTOTAL_B 0xe1000 6439 #define _PCH_TRANS_HBLANK_B 0xe1004 6440 #define _PCH_TRANS_HSYNC_B 0xe1008 6441 #define _PCH_TRANS_VTOTAL_B 0xe100c 6442 #define _PCH_TRANS_VBLANK_B 0xe1010 6443 #define _PCH_TRANS_VSYNC_B 0xe1014 6444 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028 6445 6446 #define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B) 6447 #define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B) 6448 #define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B) 6449 #define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B) 6450 #define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B) 6451 #define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B) 6452 #define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B) 6453 6454 #define _PCH_TRANSB_DATA_M1 0xe1030 6455 #define _PCH_TRANSB_DATA_N1 0xe1034 6456 #define _PCH_TRANSB_DATA_M2 0xe1038 6457 #define _PCH_TRANSB_DATA_N2 0xe103c 6458 #define _PCH_TRANSB_LINK_M1 0xe1040 6459 #define _PCH_TRANSB_LINK_N1 0xe1044 6460 #define _PCH_TRANSB_LINK_M2 0xe1048 6461 #define _PCH_TRANSB_LINK_N2 0xe104c 6462 6463 #define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1) 6464 #define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1) 6465 #define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2) 6466 #define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2) 6467 #define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1) 6468 #define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1) 6469 #define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2) 6470 #define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2) 6471 6472 #define _PCH_TRANSACONF 0xf0008 6473 #define _PCH_TRANSBCONF 0xf1008 6474 #define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF) 6475 #define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */ 6476 #define TRANS_DISABLE (0<<31) 6477 #define TRANS_ENABLE (1<<31) 6478 #define TRANS_STATE_MASK (1<<30) 6479 #define TRANS_STATE_DISABLE (0<<30) 6480 #define TRANS_STATE_ENABLE (1<<30) 6481 #define TRANS_FSYNC_DELAY_HB1 (0<<27) 6482 #define TRANS_FSYNC_DELAY_HB2 (1<<27) 6483 #define TRANS_FSYNC_DELAY_HB3 (2<<27) 6484 #define TRANS_FSYNC_DELAY_HB4 (3<<27) 6485 #define TRANS_INTERLACE_MASK (7<<21) 6486 #define TRANS_PROGRESSIVE (0<<21) 6487 #define TRANS_INTERLACED (3<<21) 6488 #define TRANS_LEGACY_INTERLACED_ILK (2<<21) 6489 #define TRANS_8BPC (0<<5) 6490 #define TRANS_10BPC (1<<5) 6491 #define TRANS_6BPC (2<<5) 6492 #define TRANS_12BPC (3<<5) 6493 6494 #define _TRANSA_CHICKEN1 0xf0060 6495 #define _TRANSB_CHICKEN1 0xf1060 6496 #define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) 6497 #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE (1<<10) 6498 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4) 6499 #define _TRANSA_CHICKEN2 0xf0064 6500 #define _TRANSB_CHICKEN2 0xf1064 6501 #define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) 6502 #define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31) 6503 #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29) 6504 #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27) 6505 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26) 6506 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25) 6507 6508 #define SOUTH_CHICKEN1 _MMIO(0xc2000) 6509 #define FDIA_PHASE_SYNC_SHIFT_OVR 19 6510 #define FDIA_PHASE_SYNC_SHIFT_EN 18 6511 #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) 6512 #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) 6513 #define FDI_BC_BIFURCATION_SELECT (1 << 12) 6514 #define SPT_PWM_GRANULARITY (1<<0) 6515 #define SOUTH_CHICKEN2 _MMIO(0xc2004) 6516 #define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13) 6517 #define FDI_MPHY_IOSFSB_RESET_CTL (1<<12) 6518 #define LPT_PWM_GRANULARITY (1<<5) 6519 #define DPLS_EDP_PPS_FIX_DIS (1<<0) 6520 6521 #define _FDI_RXA_CHICKEN 0xc200c 6522 #define _FDI_RXB_CHICKEN 0xc2010 6523 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1) 6524 #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0) 6525 #define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) 6526 6527 #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020) 6528 #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30) 6529 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29) 6530 #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14) 6531 #define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12) 6532 6533 /* CPU: FDI_TX */ 6534 #define _FDI_TXA_CTL 0x60100 6535 #define _FDI_TXB_CTL 0x61100 6536 #define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) 6537 #define FDI_TX_DISABLE (0<<31) 6538 #define FDI_TX_ENABLE (1<<31) 6539 #define FDI_LINK_TRAIN_PATTERN_1 (0<<28) 6540 #define FDI_LINK_TRAIN_PATTERN_2 (1<<28) 6541 #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28) 6542 #define FDI_LINK_TRAIN_NONE (3<<28) 6543 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25) 6544 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25) 6545 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25) 6546 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25) 6547 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22) 6548 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22) 6549 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22) 6550 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22) 6551 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. 6552 SNB has different settings. */ 6553 /* SNB A-stepping */ 6554 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) 6555 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) 6556 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) 6557 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) 6558 /* SNB B-stepping */ 6559 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22) 6560 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22) 6561 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22) 6562 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22) 6563 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22) 6564 #define FDI_DP_PORT_WIDTH_SHIFT 19 6565 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT) 6566 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT) 6567 #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) 6568 /* Ironlake: hardwired to 1 */ 6569 #define FDI_TX_PLL_ENABLE (1<<14) 6570 6571 /* Ivybridge has different bits for lolz */ 6572 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8) 6573 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8) 6574 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8) 6575 #define FDI_LINK_TRAIN_NONE_IVB (3<<8) 6576 6577 /* both Tx and Rx */ 6578 #define FDI_COMPOSITE_SYNC (1<<11) 6579 #define FDI_LINK_TRAIN_AUTO (1<<10) 6580 #define FDI_SCRAMBLING_ENABLE (0<<7) 6581 #define FDI_SCRAMBLING_DISABLE (1<<7) 6582 6583 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */ 6584 #define _FDI_RXA_CTL 0xf000c 6585 #define _FDI_RXB_CTL 0xf100c 6586 #define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) 6587 #define FDI_RX_ENABLE (1<<31) 6588 /* train, dp width same as FDI_TX */ 6589 #define FDI_FS_ERRC_ENABLE (1<<27) 6590 #define FDI_FE_ERRC_ENABLE (1<<26) 6591 #define FDI_RX_POLARITY_REVERSED_LPT (1<<16) 6592 #define FDI_8BPC (0<<16) 6593 #define FDI_10BPC (1<<16) 6594 #define FDI_6BPC (2<<16) 6595 #define FDI_12BPC (3<<16) 6596 #define FDI_RX_LINK_REVERSAL_OVERRIDE (1<<15) 6597 #define FDI_DMI_LINK_REVERSE_MASK (1<<14) 6598 #define FDI_RX_PLL_ENABLE (1<<13) 6599 #define FDI_FS_ERR_CORRECT_ENABLE (1<<11) 6600 #define FDI_FE_ERR_CORRECT_ENABLE (1<<10) 6601 #define FDI_FS_ERR_REPORT_ENABLE (1<<9) 6602 #define FDI_FE_ERR_REPORT_ENABLE (1<<8) 6603 #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) 6604 #define FDI_PCDCLK (1<<4) 6605 /* CPT */ 6606 #define FDI_AUTO_TRAINING (1<<10) 6607 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8) 6608 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8) 6609 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8) 6610 #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8) 6611 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8) 6612 6613 #define _FDI_RXA_MISC 0xf0010 6614 #define _FDI_RXB_MISC 0xf1010 6615 #define FDI_RX_PWRDN_LANE1_MASK (3<<26) 6616 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26) 6617 #define FDI_RX_PWRDN_LANE0_MASK (3<<24) 6618 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24) 6619 #define FDI_RX_TP1_TO_TP2_48 (2<<20) 6620 #define FDI_RX_TP1_TO_TP2_64 (3<<20) 6621 #define FDI_RX_FDI_DELAY_90 (0x90<<0) 6622 #define FDI_RX_MISC(pipe) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) 6623 6624 #define _FDI_RXA_TUSIZE1 0xf0030 6625 #define _FDI_RXA_TUSIZE2 0xf0038 6626 #define _FDI_RXB_TUSIZE1 0xf1030 6627 #define _FDI_RXB_TUSIZE2 0xf1038 6628 #define FDI_RX_TUSIZE1(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) 6629 #define FDI_RX_TUSIZE2(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) 6630 6631 /* FDI_RX interrupt register format */ 6632 #define FDI_RX_INTER_LANE_ALIGN (1<<10) 6633 #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */ 6634 #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */ 6635 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7) 6636 #define FDI_RX_FS_CODE_ERR (1<<6) 6637 #define FDI_RX_FE_CODE_ERR (1<<5) 6638 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4) 6639 #define FDI_RX_HDCP_LINK_FAIL (1<<3) 6640 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2) 6641 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) 6642 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) 6643 6644 #define _FDI_RXA_IIR 0xf0014 6645 #define _FDI_RXA_IMR 0xf0018 6646 #define _FDI_RXB_IIR 0xf1014 6647 #define _FDI_RXB_IMR 0xf1018 6648 #define FDI_RX_IIR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) 6649 #define FDI_RX_IMR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR) 6650 6651 #define FDI_PLL_CTL_1 _MMIO(0xfe000) 6652 #define FDI_PLL_CTL_2 _MMIO(0xfe004) 6653 6654 #define PCH_LVDS _MMIO(0xe1180) 6655 #define LVDS_DETECTED (1 << 1) 6656 6657 /* vlv has 2 sets of panel control regs. */ 6658 #define _PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200) 6659 #define _PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204) 6660 #define _PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208) 6661 #define PANEL_PORT_SELECT_VLV(port) ((port) << 30) 6662 #define _PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c) 6663 #define _PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210) 6664 6665 #define _PIPEB_PP_STATUS (VLV_DISPLAY_BASE + 0x61300) 6666 #define _PIPEB_PP_CONTROL (VLV_DISPLAY_BASE + 0x61304) 6667 #define _PIPEB_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61308) 6668 #define _PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c) 6669 #define _PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310) 6670 6671 #define VLV_PIPE_PP_STATUS(pipe) _MMIO_PIPE(pipe, _PIPEA_PP_STATUS, _PIPEB_PP_STATUS) 6672 #define VLV_PIPE_PP_CONTROL(pipe) _MMIO_PIPE(pipe, _PIPEA_PP_CONTROL, _PIPEB_PP_CONTROL) 6673 #define VLV_PIPE_PP_ON_DELAYS(pipe) _MMIO_PIPE(pipe, _PIPEA_PP_ON_DELAYS, _PIPEB_PP_ON_DELAYS) 6674 #define VLV_PIPE_PP_OFF_DELAYS(pipe) _MMIO_PIPE(pipe, _PIPEA_PP_OFF_DELAYS, _PIPEB_PP_OFF_DELAYS) 6675 #define VLV_PIPE_PP_DIVISOR(pipe) _MMIO_PIPE(pipe, _PIPEA_PP_DIVISOR, _PIPEB_PP_DIVISOR) 6676 6677 #define _PCH_PP_STATUS 0xc7200 6678 #define _PCH_PP_CONTROL 0xc7204 6679 #define PANEL_UNLOCK_REGS (0xabcd << 16) 6680 #define PANEL_UNLOCK_MASK (0xffff << 16) 6681 #define BXT_POWER_CYCLE_DELAY_MASK (0x1f0) 6682 #define BXT_POWER_CYCLE_DELAY_SHIFT 4 6683 #define EDP_FORCE_VDD (1 << 3) 6684 #define EDP_BLC_ENABLE (1 << 2) 6685 #define PANEL_POWER_RESET (1 << 1) 6686 #define PANEL_POWER_OFF (0 << 0) 6687 #define PANEL_POWER_ON (1 << 0) 6688 #define _PCH_PP_ON_DELAYS 0xc7208 6689 #define PANEL_PORT_SELECT_MASK (3 << 30) 6690 #define PANEL_PORT_SELECT_LVDS (0 << 30) 6691 #define PANEL_PORT_SELECT_DPA (1 << 30) 6692 #define PANEL_PORT_SELECT_DPC (2 << 30) 6693 #define PANEL_PORT_SELECT_DPD (3 << 30) 6694 #define PANEL_POWER_UP_DELAY_MASK (0x1fff0000) 6695 #define PANEL_POWER_UP_DELAY_SHIFT 16 6696 #define PANEL_LIGHT_ON_DELAY_MASK (0x1fff) 6697 #define PANEL_LIGHT_ON_DELAY_SHIFT 0 6698 6699 #define _PCH_PP_OFF_DELAYS 0xc720c 6700 #define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000) 6701 #define PANEL_POWER_DOWN_DELAY_SHIFT 16 6702 #define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff) 6703 #define PANEL_LIGHT_OFF_DELAY_SHIFT 0 6704 6705 #define _PCH_PP_DIVISOR 0xc7210 6706 #define PP_REFERENCE_DIVIDER_MASK (0xffffff00) 6707 #define PP_REFERENCE_DIVIDER_SHIFT 8 6708 #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f) 6709 #define PANEL_POWER_CYCLE_DELAY_SHIFT 0 6710 6711 #define PCH_PP_STATUS _MMIO(_PCH_PP_STATUS) 6712 #define PCH_PP_CONTROL _MMIO(_PCH_PP_CONTROL) 6713 #define PCH_PP_ON_DELAYS _MMIO(_PCH_PP_ON_DELAYS) 6714 #define PCH_PP_OFF_DELAYS _MMIO(_PCH_PP_OFF_DELAYS) 6715 #define PCH_PP_DIVISOR _MMIO(_PCH_PP_DIVISOR) 6716 6717 /* BXT PPS changes - 2nd set of PPS registers */ 6718 #define _BXT_PP_STATUS2 0xc7300 6719 #define _BXT_PP_CONTROL2 0xc7304 6720 #define _BXT_PP_ON_DELAYS2 0xc7308 6721 #define _BXT_PP_OFF_DELAYS2 0xc730c 6722 6723 #define BXT_PP_STATUS(n) _MMIO_PIPE(n, _PCH_PP_STATUS, _BXT_PP_STATUS2) 6724 #define BXT_PP_CONTROL(n) _MMIO_PIPE(n, _PCH_PP_CONTROL, _BXT_PP_CONTROL2) 6725 #define BXT_PP_ON_DELAYS(n) _MMIO_PIPE(n, _PCH_PP_ON_DELAYS, _BXT_PP_ON_DELAYS2) 6726 #define BXT_PP_OFF_DELAYS(n) _MMIO_PIPE(n, _PCH_PP_OFF_DELAYS, _BXT_PP_OFF_DELAYS2) 6727 6728 #define _PCH_DP_B 0xe4100 6729 #define PCH_DP_B _MMIO(_PCH_DP_B) 6730 #define _PCH_DPB_AUX_CH_CTL 0xe4110 6731 #define _PCH_DPB_AUX_CH_DATA1 0xe4114 6732 #define _PCH_DPB_AUX_CH_DATA2 0xe4118 6733 #define _PCH_DPB_AUX_CH_DATA3 0xe411c 6734 #define _PCH_DPB_AUX_CH_DATA4 0xe4120 6735 #define _PCH_DPB_AUX_CH_DATA5 0xe4124 6736 6737 #define _PCH_DP_C 0xe4200 6738 #define PCH_DP_C _MMIO(_PCH_DP_C) 6739 #define _PCH_DPC_AUX_CH_CTL 0xe4210 6740 #define _PCH_DPC_AUX_CH_DATA1 0xe4214 6741 #define _PCH_DPC_AUX_CH_DATA2 0xe4218 6742 #define _PCH_DPC_AUX_CH_DATA3 0xe421c 6743 #define _PCH_DPC_AUX_CH_DATA4 0xe4220 6744 #define _PCH_DPC_AUX_CH_DATA5 0xe4224 6745 6746 #define _PCH_DP_D 0xe4300 6747 #define PCH_DP_D _MMIO(_PCH_DP_D) 6748 #define _PCH_DPD_AUX_CH_CTL 0xe4310 6749 #define _PCH_DPD_AUX_CH_DATA1 0xe4314 6750 #define _PCH_DPD_AUX_CH_DATA2 0xe4318 6751 #define _PCH_DPD_AUX_CH_DATA3 0xe431c 6752 #define _PCH_DPD_AUX_CH_DATA4 0xe4320 6753 #define _PCH_DPD_AUX_CH_DATA5 0xe4324 6754 6755 #define PCH_DP_AUX_CH_CTL(port) _MMIO_PORT((port) - PORT_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL) 6756 #define PCH_DP_AUX_CH_DATA(port, i) _MMIO(_PORT((port) - PORT_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ 6757 6758 /* CPT */ 6759 #define PORT_TRANS_A_SEL_CPT 0 6760 #define PORT_TRANS_B_SEL_CPT (1<<29) 6761 #define PORT_TRANS_C_SEL_CPT (2<<29) 6762 #define PORT_TRANS_SEL_MASK (3<<29) 6763 #define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29) 6764 #define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30) 6765 #define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29) 6766 #define SDVO_PORT_TO_PIPE_CHV(val) (((val) & (3<<24)) >> 24) 6767 #define DP_PORT_TO_PIPE_CHV(val) (((val) & (3<<16)) >> 16) 6768 6769 #define _TRANS_DP_CTL_A 0xe0300 6770 #define _TRANS_DP_CTL_B 0xe1300 6771 #define _TRANS_DP_CTL_C 0xe2300 6772 #define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B) 6773 #define TRANS_DP_OUTPUT_ENABLE (1<<31) 6774 #define TRANS_DP_PORT_SEL_B (0<<29) 6775 #define TRANS_DP_PORT_SEL_C (1<<29) 6776 #define TRANS_DP_PORT_SEL_D (2<<29) 6777 #define TRANS_DP_PORT_SEL_NONE (3<<29) 6778 #define TRANS_DP_PORT_SEL_MASK (3<<29) 6779 #define TRANS_DP_PIPE_TO_PORT(val) ((((val) & TRANS_DP_PORT_SEL_MASK) >> 29) + PORT_B) 6780 #define TRANS_DP_AUDIO_ONLY (1<<26) 6781 #define TRANS_DP_ENH_FRAMING (1<<18) 6782 #define TRANS_DP_8BPC (0<<9) 6783 #define TRANS_DP_10BPC (1<<9) 6784 #define TRANS_DP_6BPC (2<<9) 6785 #define TRANS_DP_12BPC (3<<9) 6786 #define TRANS_DP_BPC_MASK (3<<9) 6787 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4) 6788 #define TRANS_DP_VSYNC_ACTIVE_LOW 0 6789 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3) 6790 #define TRANS_DP_HSYNC_ACTIVE_LOW 0 6791 #define TRANS_DP_SYNC_MASK (3<<3) 6792 6793 /* SNB eDP training params */ 6794 /* SNB A-stepping */ 6795 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) 6796 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) 6797 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) 6798 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) 6799 /* SNB B-stepping */ 6800 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22) 6801 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22) 6802 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22) 6803 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22) 6804 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22) 6805 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22) 6806 6807 /* IVB */ 6808 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22) 6809 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22) 6810 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22) 6811 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22) 6812 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22) 6813 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22) 6814 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e <<22) 6815 6816 /* legacy values */ 6817 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22) 6818 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22) 6819 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22) 6820 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22) 6821 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22) 6822 6823 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22) 6824 6825 #define VLV_PMWGICZ _MMIO(0x1300a4) 6826 6827 #define RC6_LOCATION _MMIO(0xD40) 6828 #define RC6_CTX_IN_DRAM (1 << 0) 6829 #define RC6_CTX_BASE _MMIO(0xD48) 6830 #define RC6_CTX_BASE_MASK 0xFFFFFFF0 6831 #define PWRCTX_MAXCNT_RCSUNIT _MMIO(0x2054) 6832 #define PWRCTX_MAXCNT_VCSUNIT0 _MMIO(0x12054) 6833 #define PWRCTX_MAXCNT_BCSUNIT _MMIO(0x22054) 6834 #define PWRCTX_MAXCNT_VECSUNIT _MMIO(0x1A054) 6835 #define PWRCTX_MAXCNT_VCSUNIT1 _MMIO(0x1C054) 6836 #define IDLE_TIME_MASK 0xFFFFF 6837 #define FORCEWAKE _MMIO(0xA18C) 6838 #define FORCEWAKE_VLV _MMIO(0x1300b0) 6839 #define FORCEWAKE_ACK_VLV _MMIO(0x1300b4) 6840 #define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8) 6841 #define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc) 6842 #define FORCEWAKE_ACK_HSW _MMIO(0x130044) 6843 #define FORCEWAKE_ACK _MMIO(0x130090) 6844 #define VLV_GTLC_WAKE_CTRL _MMIO(0x130090) 6845 #define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25) 6846 #define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24) 6847 #define VLV_GTLC_ALLOWWAKEREQ (1 << 0) 6848 6849 #define VLV_GTLC_PW_STATUS _MMIO(0x130094) 6850 #define VLV_GTLC_ALLOWWAKEACK (1 << 0) 6851 #define VLV_GTLC_ALLOWWAKEERR (1 << 1) 6852 #define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5) 6853 #define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7) 6854 #define FORCEWAKE_MT _MMIO(0xa188) /* multi-threaded */ 6855 #define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270) 6856 #define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278) 6857 #define FORCEWAKE_BLITTER_GEN9 _MMIO(0xa188) 6858 #define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0x0D88) 6859 #define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0x0D84) 6860 #define FORCEWAKE_ACK_BLITTER_GEN9 _MMIO(0x130044) 6861 #define FORCEWAKE_KERNEL 0x1 6862 #define FORCEWAKE_USER 0x2 6863 #define FORCEWAKE_MT_ACK _MMIO(0x130040) 6864 #define ECOBUS _MMIO(0xa180) 6865 #define FORCEWAKE_MT_ENABLE (1<<5) 6866 #define VLV_SPAREG2H _MMIO(0xA194) 6867 6868 #define GTFIFODBG _MMIO(0x120000) 6869 #define GT_FIFO_SBDROPERR (1<<6) 6870 #define GT_FIFO_BLOBDROPERR (1<<5) 6871 #define GT_FIFO_SB_READ_ABORTERR (1<<4) 6872 #define GT_FIFO_DROPERR (1<<3) 6873 #define GT_FIFO_OVFERR (1<<2) 6874 #define GT_FIFO_IAWRERR (1<<1) 6875 #define GT_FIFO_IARDERR (1<<0) 6876 6877 #define GTFIFOCTL _MMIO(0x120008) 6878 #define GT_FIFO_FREE_ENTRIES_MASK 0x7f 6879 #define GT_FIFO_NUM_RESERVED_ENTRIES 20 6880 #define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12) 6881 #define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11) 6882 6883 #define HSW_IDICR _MMIO(0x9008) 6884 #define IDIHASHMSK(x) (((x) & 0x3f) << 16) 6885 #define HSW_EDRAM_PRESENT _MMIO(0x120010) 6886 #define EDRAM_ENABLED 0x1 6887 6888 #define GEN6_UCGCTL1 _MMIO(0x9400) 6889 # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16) 6890 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) 6891 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7) 6892 6893 #define GEN6_UCGCTL2 _MMIO(0x9404) 6894 # define GEN6_VFUNIT_CLOCK_GATE_DISABLE (1 << 31) 6895 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30) 6896 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22) 6897 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13) 6898 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12) 6899 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11) 6900 6901 #define GEN6_UCGCTL3 _MMIO(0x9408) 6902 6903 #define GEN7_UCGCTL4 _MMIO(0x940c) 6904 #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25) 6905 6906 #define GEN6_RCGCTL1 _MMIO(0x9410) 6907 #define GEN6_RCGCTL2 _MMIO(0x9414) 6908 #define GEN6_RSTCTL _MMIO(0x9420) 6909 6910 #define GEN8_UCGCTL6 _MMIO(0x9430) 6911 #define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1<<24) 6912 #define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14) 6913 #define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1<<28) 6914 6915 #define GEN6_GFXPAUSE _MMIO(0xA000) 6916 #define GEN6_RPNSWREQ _MMIO(0xA008) 6917 #define GEN6_TURBO_DISABLE (1<<31) 6918 #define GEN6_FREQUENCY(x) ((x)<<25) 6919 #define HSW_FREQUENCY(x) ((x)<<24) 6920 #define GEN9_FREQUENCY(x) ((x)<<23) 6921 #define GEN6_OFFSET(x) ((x)<<19) 6922 #define GEN6_AGGRESSIVE_TURBO (0<<15) 6923 #define GEN6_RC_VIDEO_FREQ _MMIO(0xA00C) 6924 #define GEN6_RC_CONTROL _MMIO(0xA090) 6925 #define GEN6_RC_CTL_RC6pp_ENABLE (1<<16) 6926 #define GEN6_RC_CTL_RC6p_ENABLE (1<<17) 6927 #define GEN6_RC_CTL_RC6_ENABLE (1<<18) 6928 #define GEN6_RC_CTL_RC1e_ENABLE (1<<20) 6929 #define GEN6_RC_CTL_RC7_ENABLE (1<<22) 6930 #define VLV_RC_CTL_CTX_RST_PARALLEL (1<<24) 6931 #define GEN7_RC_CTL_TO_MODE (1<<28) 6932 #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27) 6933 #define GEN6_RC_CTL_HW_ENABLE (1<<31) 6934 #define GEN6_RP_DOWN_TIMEOUT _MMIO(0xA010) 6935 #define GEN6_RP_INTERRUPT_LIMITS _MMIO(0xA014) 6936 #define GEN6_RPSTAT1 _MMIO(0xA01C) 6937 #define GEN6_CAGF_SHIFT 8 6938 #define HSW_CAGF_SHIFT 7 6939 #define GEN9_CAGF_SHIFT 23 6940 #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) 6941 #define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT) 6942 #define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT) 6943 #define GEN6_RP_CONTROL _MMIO(0xA024) 6944 #define GEN6_RP_MEDIA_TURBO (1<<11) 6945 #define GEN6_RP_MEDIA_MODE_MASK (3<<9) 6946 #define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9) 6947 #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9) 6948 #define GEN6_RP_MEDIA_HW_MODE (1<<9) 6949 #define GEN6_RP_MEDIA_SW_MODE (0<<9) 6950 #define GEN6_RP_MEDIA_IS_GFX (1<<8) 6951 #define GEN6_RP_ENABLE (1<<7) 6952 #define GEN6_RP_UP_IDLE_MIN (0x1<<3) 6953 #define GEN6_RP_UP_BUSY_AVG (0x2<<3) 6954 #define GEN6_RP_UP_BUSY_CONT (0x4<<3) 6955 #define GEN6_RP_DOWN_IDLE_AVG (0x2<<0) 6956 #define GEN6_RP_DOWN_IDLE_CONT (0x1<<0) 6957 #define GEN6_RP_UP_THRESHOLD _MMIO(0xA02C) 6958 #define GEN6_RP_DOWN_THRESHOLD _MMIO(0xA030) 6959 #define GEN6_RP_CUR_UP_EI _MMIO(0xA050) 6960 #define GEN6_CURICONT_MASK 0xffffff 6961 #define GEN6_RP_CUR_UP _MMIO(0xA054) 6962 #define GEN6_CURBSYTAVG_MASK 0xffffff 6963 #define GEN6_RP_PREV_UP _MMIO(0xA058) 6964 #define GEN6_RP_CUR_DOWN_EI _MMIO(0xA05C) 6965 #define GEN6_CURIAVG_MASK 0xffffff 6966 #define GEN6_RP_CUR_DOWN _MMIO(0xA060) 6967 #define GEN6_RP_PREV_DOWN _MMIO(0xA064) 6968 #define GEN6_RP_UP_EI _MMIO(0xA068) 6969 #define GEN6_RP_DOWN_EI _MMIO(0xA06C) 6970 #define GEN6_RP_IDLE_HYSTERSIS _MMIO(0xA070) 6971 #define GEN6_RPDEUHWTC _MMIO(0xA080) 6972 #define GEN6_RPDEUC _MMIO(0xA084) 6973 #define GEN6_RPDEUCSW _MMIO(0xA088) 6974 #define GEN6_RC_STATE _MMIO(0xA094) 6975 #define RC6_STATE (1 << 18) 6976 #define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xA098) 6977 #define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xA09C) 6978 #define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xA0A0) 6979 #define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xA0A8) 6980 #define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xA0AC) 6981 #define GEN6_RC_SLEEP _MMIO(0xA0B0) 6982 #define GEN6_RCUBMABDTMR _MMIO(0xA0B0) 6983 #define GEN6_RC1e_THRESHOLD _MMIO(0xA0B4) 6984 #define GEN6_RC6_THRESHOLD _MMIO(0xA0B8) 6985 #define GEN6_RC6p_THRESHOLD _MMIO(0xA0BC) 6986 #define VLV_RCEDATA _MMIO(0xA0BC) 6987 #define GEN6_RC6pp_THRESHOLD _MMIO(0xA0C0) 6988 #define GEN6_PMINTRMSK _MMIO(0xA168) 6989 #define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31) 6990 #define VLV_PWRDWNUPCTL _MMIO(0xA294) 6991 #define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xA0C4) 6992 #define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xA0C8) 6993 #define GEN9_PG_ENABLE _MMIO(0xA210) 6994 #define GEN9_RENDER_PG_ENABLE (1<<0) 6995 #define GEN9_MEDIA_PG_ENABLE (1<<1) 6996 6997 #define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C) 6998 #define PIXEL_OVERLAP_CNT_MASK (3 << 30) 6999 #define PIXEL_OVERLAP_CNT_SHIFT 30 7000 7001 #define GEN6_PMISR _MMIO(0x44020) 7002 #define GEN6_PMIMR _MMIO(0x44024) /* rps_lock */ 7003 #define GEN6_PMIIR _MMIO(0x44028) 7004 #define GEN6_PMIER _MMIO(0x4402C) 7005 #define GEN6_PM_MBOX_EVENT (1<<25) 7006 #define GEN6_PM_THERMAL_EVENT (1<<24) 7007 #define GEN6_PM_RP_DOWN_TIMEOUT (1<<6) 7008 #define GEN6_PM_RP_UP_THRESHOLD (1<<5) 7009 #define GEN6_PM_RP_DOWN_THRESHOLD (1<<4) 7010 #define GEN6_PM_RP_UP_EI_EXPIRED (1<<2) 7011 #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1) 7012 #define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \ 7013 GEN6_PM_RP_DOWN_THRESHOLD | \ 7014 GEN6_PM_RP_DOWN_TIMEOUT) 7015 7016 #define GEN7_GT_SCRATCH(i) _MMIO(0x4F100 + (i) * 4) 7017 #define GEN7_GT_SCRATCH_REG_NUM 8 7018 7019 #define VLV_GTLC_SURVIVABILITY_REG _MMIO(0x130098) 7020 #define VLV_GFX_CLK_STATUS_BIT (1<<3) 7021 #define VLV_GFX_CLK_FORCE_ON_BIT (1<<2) 7022 7023 #define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104) 7024 #define VLV_COUNTER_CONTROL _MMIO(0x138104) 7025 #define VLV_COUNT_RANGE_HIGH (1<<15) 7026 #define VLV_MEDIA_RC0_COUNT_EN (1<<5) 7027 #define VLV_RENDER_RC0_COUNT_EN (1<<4) 7028 #define VLV_MEDIA_RC6_COUNT_EN (1<<1) 7029 #define VLV_RENDER_RC6_COUNT_EN (1<<0) 7030 #define GEN6_GT_GFX_RC6 _MMIO(0x138108) 7031 #define VLV_GT_RENDER_RC6 _MMIO(0x138108) 7032 #define VLV_GT_MEDIA_RC6 _MMIO(0x13810C) 7033 7034 #define GEN6_GT_GFX_RC6p _MMIO(0x13810C) 7035 #define GEN6_GT_GFX_RC6pp _MMIO(0x138110) 7036 #define VLV_RENDER_C0_COUNT _MMIO(0x138118) 7037 #define VLV_MEDIA_C0_COUNT _MMIO(0x13811C) 7038 7039 #define GEN6_PCODE_MAILBOX _MMIO(0x138124) 7040 #define GEN6_PCODE_READY (1<<31) 7041 #define GEN6_PCODE_WRITE_RC6VIDS 0x4 7042 #define GEN6_PCODE_READ_RC6VIDS 0x5 7043 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) 7044 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) 7045 #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18 7046 #define GEN9_PCODE_READ_MEM_LATENCY 0x6 7047 #define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF 7048 #define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8 7049 #define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16 7050 #define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24 7051 #define SKL_PCODE_CDCLK_CONTROL 0x7 7052 #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3 7053 #define SKL_CDCLK_READY_FOR_CHANGE 0x1 7054 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 7055 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 7056 #define GEN6_READ_OC_PARAMS 0xc 7057 #define GEN6_PCODE_READ_D_COMP 0x10 7058 #define GEN6_PCODE_WRITE_D_COMP 0x11 7059 #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17 7060 #define DISPLAY_IPS_CONTROL 0x19 7061 #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A 7062 #define GEN6_PCODE_DATA _MMIO(0x138128) 7063 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 7064 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 7065 #define GEN6_PCODE_DATA1 _MMIO(0x13812C) 7066 7067 #define GEN6_GT_CORE_STATUS _MMIO(0x138060) 7068 #define GEN6_CORE_CPD_STATE_MASK (7<<4) 7069 #define GEN6_RCn_MASK 7 7070 #define GEN6_RC0 0 7071 #define GEN6_RC3 2 7072 #define GEN6_RC6 3 7073 #define GEN6_RC7 4 7074 7075 #define GEN8_GT_SLICE_INFO _MMIO(0x138064) 7076 #define GEN8_LSLICESTAT_MASK 0x7 7077 7078 #define CHV_POWER_SS0_SIG1 _MMIO(0xa720) 7079 #define CHV_POWER_SS1_SIG1 _MMIO(0xa728) 7080 #define CHV_SS_PG_ENABLE (1<<1) 7081 #define CHV_EU08_PG_ENABLE (1<<9) 7082 #define CHV_EU19_PG_ENABLE (1<<17) 7083 #define CHV_EU210_PG_ENABLE (1<<25) 7084 7085 #define CHV_POWER_SS0_SIG2 _MMIO(0xa724) 7086 #define CHV_POWER_SS1_SIG2 _MMIO(0xa72c) 7087 #define CHV_EU311_PG_ENABLE (1<<1) 7088 7089 #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice)*0x4) 7090 #define GEN9_PGCTL_SLICE_ACK (1 << 0) 7091 #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice)*2)) 7092 7093 #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice)*0x8) 7094 #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice)*0x8) 7095 #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0) 7096 #define GEN9_PGCTL_SSA_EU19_ACK (1 << 2) 7097 #define GEN9_PGCTL_SSA_EU210_ACK (1 << 4) 7098 #define GEN9_PGCTL_SSA_EU311_ACK (1 << 6) 7099 #define GEN9_PGCTL_SSB_EU08_ACK (1 << 8) 7100 #define GEN9_PGCTL_SSB_EU19_ACK (1 << 10) 7101 #define GEN9_PGCTL_SSB_EU210_ACK (1 << 12) 7102 #define GEN9_PGCTL_SSB_EU311_ACK (1 << 14) 7103 7104 #define GEN7_MISCCPCTL _MMIO(0x9424) 7105 #define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0) 7106 #define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1<<2) 7107 #define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1<<4) 7108 #define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1<<6) 7109 7110 #define GEN8_GARBCNTL _MMIO(0xB004) 7111 #define GEN9_GAPS_TSV_CREDIT_DISABLE (1<<7) 7112 7113 /* IVYBRIDGE DPF */ 7114 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */ 7115 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14) 7116 #define GEN7_PARITY_ERROR_VALID (1<<13) 7117 #define GEN7_L3CDERRST1_BANK_MASK (3<<11) 7118 #define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8) 7119 #define GEN7_PARITY_ERROR_ROW(reg) \ 7120 ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14) 7121 #define GEN7_PARITY_ERROR_BANK(reg) \ 7122 ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11) 7123 #define GEN7_PARITY_ERROR_SUBBANK(reg) \ 7124 ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) 7125 #define GEN7_L3CDERRST1_ENABLE (1<<7) 7126 7127 #define GEN7_L3LOG(slice, i) _MMIO(0xB070 + (slice) * 0x200 + (i) * 4) 7128 #define GEN7_L3LOG_SIZE 0x80 7129 7130 #define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */ 7131 #define GEN7_HALF_SLICE_CHICKEN1_GT2 _MMIO(0xf100) 7132 #define GEN7_MAX_PS_THREAD_DEP (8<<12) 7133 #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10) 7134 #define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1<<4) 7135 #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3) 7136 7137 #define GEN9_HALF_SLICE_CHICKEN5 _MMIO(0xe188) 7138 #define GEN9_DG_MIRROR_FIX_ENABLE (1<<5) 7139 #define GEN9_CCS_TLB_PREFETCH_ENABLE (1<<3) 7140 7141 #define GEN8_ROW_CHICKEN _MMIO(0xe4f0) 7142 #define FLOW_CONTROL_ENABLE (1<<15) 7143 #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8) 7144 #define STALL_DOP_GATING_DISABLE (1<<5) 7145 7146 #define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4) 7147 #define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4) 7148 #define DOP_CLOCK_GATING_DISABLE (1<<0) 7149 7150 #define HSW_ROW_CHICKEN3 _MMIO(0xe49c) 7151 #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) 7152 7153 #define HALF_SLICE_CHICKEN2 _MMIO(0xe180) 7154 #define GEN8_ST_PO_DISABLE (1<<13) 7155 7156 #define HALF_SLICE_CHICKEN3 _MMIO(0xe184) 7157 #define HSW_SAMPLE_C_PERFORMANCE (1<<9) 7158 #define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8) 7159 #define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1<<5) 7160 #define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1) 7161 7162 #define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194) 7163 #define GEN9_ENABLE_YV12_BUGFIX (1<<4) 7164 7165 /* Audio */ 7166 #define G4X_AUD_VID_DID _MMIO(dev_priv->info.display_mmio_offset + 0x62020) 7167 #define INTEL_AUDIO_DEVCL 0x808629FB 7168 #define INTEL_AUDIO_DEVBLC 0x80862801 7169 #define INTEL_AUDIO_DEVCTG 0x80862802 7170 7171 #define G4X_AUD_CNTL_ST _MMIO(0x620B4) 7172 #define G4X_ELDV_DEVCL_DEVBLC (1 << 13) 7173 #define G4X_ELDV_DEVCTG (1 << 14) 7174 #define G4X_ELD_ADDR_MASK (0xf << 5) 7175 #define G4X_ELD_ACK (1 << 4) 7176 #define G4X_HDMIW_HDMIEDID _MMIO(0x6210C) 7177 7178 #define _IBX_HDMIW_HDMIEDID_A 0xE2050 7179 #define _IBX_HDMIW_HDMIEDID_B 0xE2150 7180 #define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \ 7181 _IBX_HDMIW_HDMIEDID_B) 7182 #define _IBX_AUD_CNTL_ST_A 0xE20B4 7183 #define _IBX_AUD_CNTL_ST_B 0xE21B4 7184 #define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \ 7185 _IBX_AUD_CNTL_ST_B) 7186 #define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10) 7187 #define IBX_ELD_ADDRESS_MASK (0x1f << 5) 7188 #define IBX_ELD_ACK (1 << 4) 7189 #define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0) 7190 #define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4)) 7191 #define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4)) 7192 7193 #define _CPT_HDMIW_HDMIEDID_A 0xE5050 7194 #define _CPT_HDMIW_HDMIEDID_B 0xE5150 7195 #define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B) 7196 #define _CPT_AUD_CNTL_ST_A 0xE50B4 7197 #define _CPT_AUD_CNTL_ST_B 0xE51B4 7198 #define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B) 7199 #define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0) 7200 7201 #define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050) 7202 #define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150) 7203 #define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B) 7204 #define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4) 7205 #define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4) 7206 #define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B) 7207 #define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0) 7208 7209 /* These are the 4 32-bit write offset registers for each stream 7210 * output buffer. It determines the offset from the 7211 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. 7212 */ 7213 #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4) 7214 7215 #define _IBX_AUD_CONFIG_A 0xe2000 7216 #define _IBX_AUD_CONFIG_B 0xe2100 7217 #define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B) 7218 #define _CPT_AUD_CONFIG_A 0xe5000 7219 #define _CPT_AUD_CONFIG_B 0xe5100 7220 #define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B) 7221 #define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000) 7222 #define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100) 7223 #define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B) 7224 7225 #define AUD_CONFIG_N_VALUE_INDEX (1 << 29) 7226 #define AUD_CONFIG_N_PROG_ENABLE (1 << 28) 7227 #define AUD_CONFIG_UPPER_N_SHIFT 20 7228 #define AUD_CONFIG_UPPER_N_MASK (0xff << 20) 7229 #define AUD_CONFIG_LOWER_N_SHIFT 4 7230 #define AUD_CONFIG_LOWER_N_MASK (0xfff << 4) 7231 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 7232 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16) 7233 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16) 7234 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16) 7235 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16) 7236 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16) 7237 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16) 7238 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16) 7239 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16) 7240 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16) 7241 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16) 7242 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16) 7243 #define AUD_CONFIG_DISABLE_NCTS (1 << 3) 7244 7245 /* HSW Audio */ 7246 #define _HSW_AUD_CONFIG_A 0x65000 7247 #define _HSW_AUD_CONFIG_B 0x65100 7248 #define HSW_AUD_CFG(pipe) _MMIO_PIPE(pipe, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B) 7249 7250 #define _HSW_AUD_MISC_CTRL_A 0x65010 7251 #define _HSW_AUD_MISC_CTRL_B 0x65110 7252 #define HSW_AUD_MISC_CTRL(pipe) _MMIO_PIPE(pipe, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B) 7253 7254 #define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 7255 #define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 7256 #define HSW_AUD_DIP_ELD_CTRL(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B) 7257 7258 /* Audio Digital Converter */ 7259 #define _HSW_AUD_DIG_CNVT_1 0x65080 7260 #define _HSW_AUD_DIG_CNVT_2 0x65180 7261 #define AUD_DIG_CNVT(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2) 7262 #define DIP_PORT_SEL_MASK 0x3 7263 7264 #define _HSW_AUD_EDID_DATA_A 0x65050 7265 #define _HSW_AUD_EDID_DATA_B 0x65150 7266 #define HSW_AUD_EDID_DATA(pipe) _MMIO_PIPE(pipe, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B) 7267 7268 #define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c) 7269 #define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0) 7270 #define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4)) 7271 #define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4)) 7272 #define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4)) 7273 #define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4)) 7274 7275 #define HSW_AUD_CHICKENBIT _MMIO(0x65f10) 7276 #define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15) 7277 7278 /* HSW Power Wells */ 7279 #define HSW_PWR_WELL_BIOS _MMIO(0x45400) /* CTL1 */ 7280 #define HSW_PWR_WELL_DRIVER _MMIO(0x45404) /* CTL2 */ 7281 #define HSW_PWR_WELL_KVMR _MMIO(0x45408) /* CTL3 */ 7282 #define HSW_PWR_WELL_DEBUG _MMIO(0x4540C) /* CTL4 */ 7283 #define HSW_PWR_WELL_ENABLE_REQUEST (1<<31) 7284 #define HSW_PWR_WELL_STATE_ENABLED (1<<30) 7285 #define HSW_PWR_WELL_CTL5 _MMIO(0x45410) 7286 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31) 7287 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20) 7288 #define HSW_PWR_WELL_FORCE_ON (1<<19) 7289 #define HSW_PWR_WELL_CTL6 _MMIO(0x45414) 7290 7291 /* SKL Fuse Status */ 7292 #define SKL_FUSE_STATUS _MMIO(0x42000) 7293 #define SKL_FUSE_DOWNLOAD_STATUS (1<<31) 7294 #define SKL_FUSE_PG0_DIST_STATUS (1<<27) 7295 #define SKL_FUSE_PG1_DIST_STATUS (1<<26) 7296 #define SKL_FUSE_PG2_DIST_STATUS (1<<25) 7297 7298 /* Per-pipe DDI Function Control */ 7299 #define _TRANS_DDI_FUNC_CTL_A 0x60400 7300 #define _TRANS_DDI_FUNC_CTL_B 0x61400 7301 #define _TRANS_DDI_FUNC_CTL_C 0x62400 7302 #define _TRANS_DDI_FUNC_CTL_EDP 0x6F400 7303 #define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A) 7304 7305 #define TRANS_DDI_FUNC_ENABLE (1<<31) 7306 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ 7307 #define TRANS_DDI_PORT_MASK (7<<28) 7308 #define TRANS_DDI_PORT_SHIFT 28 7309 #define TRANS_DDI_SELECT_PORT(x) ((x)<<28) 7310 #define TRANS_DDI_PORT_NONE (0<<28) 7311 #define TRANS_DDI_MODE_SELECT_MASK (7<<24) 7312 #define TRANS_DDI_MODE_SELECT_HDMI (0<<24) 7313 #define TRANS_DDI_MODE_SELECT_DVI (1<<24) 7314 #define TRANS_DDI_MODE_SELECT_DP_SST (2<<24) 7315 #define TRANS_DDI_MODE_SELECT_DP_MST (3<<24) 7316 #define TRANS_DDI_MODE_SELECT_FDI (4<<24) 7317 #define TRANS_DDI_BPC_MASK (7<<20) 7318 #define TRANS_DDI_BPC_8 (0<<20) 7319 #define TRANS_DDI_BPC_10 (1<<20) 7320 #define TRANS_DDI_BPC_6 (2<<20) 7321 #define TRANS_DDI_BPC_12 (3<<20) 7322 #define TRANS_DDI_PVSYNC (1<<17) 7323 #define TRANS_DDI_PHSYNC (1<<16) 7324 #define TRANS_DDI_EDP_INPUT_MASK (7<<12) 7325 #define TRANS_DDI_EDP_INPUT_A_ON (0<<12) 7326 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12) 7327 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12) 7328 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12) 7329 #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1<<8) 7330 #define TRANS_DDI_BFI_ENABLE (1<<4) 7331 7332 /* DisplayPort Transport Control */ 7333 #define _DP_TP_CTL_A 0x64040 7334 #define _DP_TP_CTL_B 0x64140 7335 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B) 7336 #define DP_TP_CTL_ENABLE (1<<31) 7337 #define DP_TP_CTL_MODE_SST (0<<27) 7338 #define DP_TP_CTL_MODE_MST (1<<27) 7339 #define DP_TP_CTL_FORCE_ACT (1<<25) 7340 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18) 7341 #define DP_TP_CTL_FDI_AUTOTRAIN (1<<15) 7342 #define DP_TP_CTL_LINK_TRAIN_MASK (7<<8) 7343 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8) 7344 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8) 7345 #define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8) 7346 #define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8) 7347 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8) 7348 #define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7) 7349 7350 /* DisplayPort Transport Status */ 7351 #define _DP_TP_STATUS_A 0x64044 7352 #define _DP_TP_STATUS_B 0x64144 7353 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B) 7354 #define DP_TP_STATUS_IDLE_DONE (1<<25) 7355 #define DP_TP_STATUS_ACT_SENT (1<<24) 7356 #define DP_TP_STATUS_MODE_STATUS_MST (1<<23) 7357 #define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12) 7358 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8) 7359 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4) 7360 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0) 7361 7362 /* DDI Buffer Control */ 7363 #define _DDI_BUF_CTL_A 0x64000 7364 #define _DDI_BUF_CTL_B 0x64100 7365 #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B) 7366 #define DDI_BUF_CTL_ENABLE (1<<31) 7367 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24) 7368 #define DDI_BUF_EMP_MASK (0xf<<24) 7369 #define DDI_BUF_PORT_REVERSAL (1<<16) 7370 #define DDI_BUF_IS_IDLE (1<<7) 7371 #define DDI_A_4_LANES (1<<4) 7372 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) 7373 #define DDI_PORT_WIDTH_MASK (7 << 1) 7374 #define DDI_PORT_WIDTH_SHIFT 1 7375 #define DDI_INIT_DISPLAY_DETECTED (1<<0) 7376 7377 /* DDI Buffer Translations */ 7378 #define _DDI_BUF_TRANS_A 0x64E00 7379 #define _DDI_BUF_TRANS_B 0x64E60 7380 #define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8) 7381 #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4) 7382 7383 /* Sideband Interface (SBI) is programmed indirectly, via 7384 * SBI_ADDR, which contains the register offset; and SBI_DATA, 7385 * which contains the payload */ 7386 #define SBI_ADDR _MMIO(0xC6000) 7387 #define SBI_DATA _MMIO(0xC6004) 7388 #define SBI_CTL_STAT _MMIO(0xC6008) 7389 #define SBI_CTL_DEST_ICLK (0x0<<16) 7390 #define SBI_CTL_DEST_MPHY (0x1<<16) 7391 #define SBI_CTL_OP_IORD (0x2<<8) 7392 #define SBI_CTL_OP_IOWR (0x3<<8) 7393 #define SBI_CTL_OP_CRRD (0x6<<8) 7394 #define SBI_CTL_OP_CRWR (0x7<<8) 7395 #define SBI_RESPONSE_FAIL (0x1<<1) 7396 #define SBI_RESPONSE_SUCCESS (0x0<<1) 7397 #define SBI_BUSY (0x1<<0) 7398 #define SBI_READY (0x0<<0) 7399 7400 /* SBI offsets */ 7401 #define SBI_SSCDIVINTPHASE 0x0200 7402 #define SBI_SSCDIVINTPHASE6 0x0600 7403 #define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1 7404 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f<<1) 7405 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1) 7406 #define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8 7407 #define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f<<8) 7408 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8) 7409 #define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15) 7410 #define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0) 7411 #define SBI_SSCDITHPHASE 0x0204 7412 #define SBI_SSCCTL 0x020c 7413 #define SBI_SSCCTL6 0x060C 7414 #define SBI_SSCCTL_PATHALT (1<<3) 7415 #define SBI_SSCCTL_DISABLE (1<<0) 7416 #define SBI_SSCAUXDIV6 0x0610 7417 #define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4 7418 #define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1<<4) 7419 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4) 7420 #define SBI_DBUFF0 0x2a00 7421 #define SBI_GEN0 0x1f00 7422 #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1<<0) 7423 7424 /* LPT PIXCLK_GATE */ 7425 #define PIXCLK_GATE _MMIO(0xC6020) 7426 #define PIXCLK_GATE_UNGATE (1<<0) 7427 #define PIXCLK_GATE_GATE (0<<0) 7428 7429 /* SPLL */ 7430 #define SPLL_CTL _MMIO(0x46020) 7431 #define SPLL_PLL_ENABLE (1<<31) 7432 #define SPLL_PLL_SSC (1<<28) 7433 #define SPLL_PLL_NON_SSC (2<<28) 7434 #define SPLL_PLL_LCPLL (3<<28) 7435 #define SPLL_PLL_REF_MASK (3<<28) 7436 #define SPLL_PLL_FREQ_810MHz (0<<26) 7437 #define SPLL_PLL_FREQ_1350MHz (1<<26) 7438 #define SPLL_PLL_FREQ_2700MHz (2<<26) 7439 #define SPLL_PLL_FREQ_MASK (3<<26) 7440 7441 /* WRPLL */ 7442 #define _WRPLL_CTL1 0x46040 7443 #define _WRPLL_CTL2 0x46060 7444 #define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2) 7445 #define WRPLL_PLL_ENABLE (1<<31) 7446 #define WRPLL_PLL_SSC (1<<28) 7447 #define WRPLL_PLL_NON_SSC (2<<28) 7448 #define WRPLL_PLL_LCPLL (3<<28) 7449 #define WRPLL_PLL_REF_MASK (3<<28) 7450 /* WRPLL divider programming */ 7451 #define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0) 7452 #define WRPLL_DIVIDER_REF_MASK (0xff) 7453 #define WRPLL_DIVIDER_POST(x) ((x)<<8) 7454 #define WRPLL_DIVIDER_POST_MASK (0x3f<<8) 7455 #define WRPLL_DIVIDER_POST_SHIFT 8 7456 #define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16) 7457 #define WRPLL_DIVIDER_FB_SHIFT 16 7458 #define WRPLL_DIVIDER_FB_MASK (0xff<<16) 7459 7460 /* Port clock selection */ 7461 #define _PORT_CLK_SEL_A 0x46100 7462 #define _PORT_CLK_SEL_B 0x46104 7463 #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B) 7464 #define PORT_CLK_SEL_LCPLL_2700 (0<<29) 7465 #define PORT_CLK_SEL_LCPLL_1350 (1<<29) 7466 #define PORT_CLK_SEL_LCPLL_810 (2<<29) 7467 #define PORT_CLK_SEL_SPLL (3<<29) 7468 #define PORT_CLK_SEL_WRPLL(pll) (((pll)+4)<<29) 7469 #define PORT_CLK_SEL_WRPLL1 (4<<29) 7470 #define PORT_CLK_SEL_WRPLL2 (5<<29) 7471 #define PORT_CLK_SEL_NONE (7<<29) 7472 #define PORT_CLK_SEL_MASK (7<<29) 7473 7474 /* Transcoder clock selection */ 7475 #define _TRANS_CLK_SEL_A 0x46140 7476 #define _TRANS_CLK_SEL_B 0x46144 7477 #define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B) 7478 /* For each transcoder, we need to select the corresponding port clock */ 7479 #define TRANS_CLK_SEL_DISABLED (0x0<<29) 7480 #define TRANS_CLK_SEL_PORT(x) (((x)+1)<<29) 7481 7482 #define _TRANSA_MSA_MISC 0x60410 7483 #define _TRANSB_MSA_MISC 0x61410 7484 #define _TRANSC_MSA_MISC 0x62410 7485 #define _TRANS_EDP_MSA_MISC 0x6f410 7486 #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC) 7487 7488 #define TRANS_MSA_SYNC_CLK (1<<0) 7489 #define TRANS_MSA_6_BPC (0<<5) 7490 #define TRANS_MSA_8_BPC (1<<5) 7491 #define TRANS_MSA_10_BPC (2<<5) 7492 #define TRANS_MSA_12_BPC (3<<5) 7493 #define TRANS_MSA_16_BPC (4<<5) 7494 7495 /* LCPLL Control */ 7496 #define LCPLL_CTL _MMIO(0x130040) 7497 #define LCPLL_PLL_DISABLE (1<<31) 7498 #define LCPLL_PLL_LOCK (1<<30) 7499 #define LCPLL_CLK_FREQ_MASK (3<<26) 7500 #define LCPLL_CLK_FREQ_450 (0<<26) 7501 #define LCPLL_CLK_FREQ_54O_BDW (1<<26) 7502 #define LCPLL_CLK_FREQ_337_5_BDW (2<<26) 7503 #define LCPLL_CLK_FREQ_675_BDW (3<<26) 7504 #define LCPLL_CD_CLOCK_DISABLE (1<<25) 7505 #define LCPLL_ROOT_CD_CLOCK_DISABLE (1<<24) 7506 #define LCPLL_CD2X_CLOCK_DISABLE (1<<23) 7507 #define LCPLL_POWER_DOWN_ALLOW (1<<22) 7508 #define LCPLL_CD_SOURCE_FCLK (1<<21) 7509 #define LCPLL_CD_SOURCE_FCLK_DONE (1<<19) 7510 7511 /* 7512 * SKL Clocks 7513 */ 7514 7515 /* CDCLK_CTL */ 7516 #define CDCLK_CTL _MMIO(0x46000) 7517 #define CDCLK_FREQ_SEL_MASK (3<<26) 7518 #define CDCLK_FREQ_450_432 (0<<26) 7519 #define CDCLK_FREQ_540 (1<<26) 7520 #define CDCLK_FREQ_337_308 (2<<26) 7521 #define CDCLK_FREQ_675_617 (3<<26) 7522 #define CDCLK_FREQ_DECIMAL_MASK (0x7ff) 7523 7524 #define BXT_CDCLK_CD2X_DIV_SEL_MASK (3<<22) 7525 #define BXT_CDCLK_CD2X_DIV_SEL_1 (0<<22) 7526 #define BXT_CDCLK_CD2X_DIV_SEL_1_5 (1<<22) 7527 #define BXT_CDCLK_CD2X_DIV_SEL_2 (2<<22) 7528 #define BXT_CDCLK_CD2X_DIV_SEL_4 (3<<22) 7529 #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16) 7530 7531 /* LCPLL_CTL */ 7532 #define LCPLL1_CTL _MMIO(0x46010) 7533 #define LCPLL2_CTL _MMIO(0x46014) 7534 #define LCPLL_PLL_ENABLE (1<<31) 7535 7536 /* DPLL control1 */ 7537 #define DPLL_CTRL1 _MMIO(0x6C058) 7538 #define DPLL_CTRL1_HDMI_MODE(id) (1<<((id)*6+5)) 7539 #define DPLL_CTRL1_SSC(id) (1<<((id)*6+4)) 7540 #define DPLL_CTRL1_LINK_RATE_MASK(id) (7<<((id)*6+1)) 7541 #define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id)*6+1) 7542 #define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate)<<((id)*6+1)) 7543 #define DPLL_CTRL1_OVERRIDE(id) (1<<((id)*6)) 7544 #define DPLL_CTRL1_LINK_RATE_2700 0 7545 #define DPLL_CTRL1_LINK_RATE_1350 1 7546 #define DPLL_CTRL1_LINK_RATE_810 2 7547 #define DPLL_CTRL1_LINK_RATE_1620 3 7548 #define DPLL_CTRL1_LINK_RATE_1080 4 7549 #define DPLL_CTRL1_LINK_RATE_2160 5 7550 7551 /* DPLL control2 */ 7552 #define DPLL_CTRL2 _MMIO(0x6C05C) 7553 #define DPLL_CTRL2_DDI_CLK_OFF(port) (1<<((port)+15)) 7554 #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3<<((port)*3+1)) 7555 #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port)*3+1) 7556 #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk)<<((port)*3+1)) 7557 #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1<<((port)*3)) 7558 7559 /* DPLL Status */ 7560 #define DPLL_STATUS _MMIO(0x6C060) 7561 #define DPLL_LOCK(id) (1<<((id)*8)) 7562 7563 /* DPLL cfg */ 7564 #define _DPLL1_CFGCR1 0x6C040 7565 #define _DPLL2_CFGCR1 0x6C048 7566 #define _DPLL3_CFGCR1 0x6C050 7567 #define DPLL_CFGCR1_FREQ_ENABLE (1<<31) 7568 #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff<<9) 7569 #define DPLL_CFGCR1_DCO_FRACTION(x) ((x)<<9) 7570 #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff) 7571 7572 #define _DPLL1_CFGCR2 0x6C044 7573 #define _DPLL2_CFGCR2 0x6C04C 7574 #define _DPLL3_CFGCR2 0x6C054 7575 #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff<<8) 7576 #define DPLL_CFGCR2_QDIV_RATIO(x) ((x)<<8) 7577 #define DPLL_CFGCR2_QDIV_MODE(x) ((x)<<7) 7578 #define DPLL_CFGCR2_KDIV_MASK (3<<5) 7579 #define DPLL_CFGCR2_KDIV(x) ((x)<<5) 7580 #define DPLL_CFGCR2_KDIV_5 (0<<5) 7581 #define DPLL_CFGCR2_KDIV_2 (1<<5) 7582 #define DPLL_CFGCR2_KDIV_3 (2<<5) 7583 #define DPLL_CFGCR2_KDIV_1 (3<<5) 7584 #define DPLL_CFGCR2_PDIV_MASK (7<<2) 7585 #define DPLL_CFGCR2_PDIV(x) ((x)<<2) 7586 #define DPLL_CFGCR2_PDIV_1 (0<<2) 7587 #define DPLL_CFGCR2_PDIV_2 (1<<2) 7588 #define DPLL_CFGCR2_PDIV_3 (2<<2) 7589 #define DPLL_CFGCR2_PDIV_7 (4<<2) 7590 #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3) 7591 7592 #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1) 7593 #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2) 7594 7595 /* BXT display engine PLL */ 7596 #define BXT_DE_PLL_CTL _MMIO(0x6d000) 7597 #define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */ 7598 #define BXT_DE_PLL_RATIO_MASK 0xff 7599 7600 #define BXT_DE_PLL_ENABLE _MMIO(0x46070) 7601 #define BXT_DE_PLL_PLL_ENABLE (1 << 31) 7602 #define BXT_DE_PLL_LOCK (1 << 30) 7603 7604 /* GEN9 DC */ 7605 #define DC_STATE_EN _MMIO(0x45504) 7606 #define DC_STATE_DISABLE 0 7607 #define DC_STATE_EN_UPTO_DC5 (1<<0) 7608 #define DC_STATE_EN_DC9 (1<<3) 7609 #define DC_STATE_EN_UPTO_DC6 (2<<0) 7610 #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3 7611 7612 #define DC_STATE_DEBUG _MMIO(0x45520) 7613 #define DC_STATE_DEBUG_MASK_CORES (1<<0) 7614 #define DC_STATE_DEBUG_MASK_MEMORY_UP (1<<1) 7615 7616 /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register, 7617 * since on HSW we can't write to it using I915_WRITE. */ 7618 #define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C) 7619 #define D_COMP_BDW _MMIO(0x138144) 7620 #define D_COMP_RCOMP_IN_PROGRESS (1<<9) 7621 #define D_COMP_COMP_FORCE (1<<8) 7622 #define D_COMP_COMP_DISABLE (1<<0) 7623 7624 /* Pipe WM_LINETIME - watermark line time */ 7625 #define _PIPE_WM_LINETIME_A 0x45270 7626 #define _PIPE_WM_LINETIME_B 0x45274 7627 #define PIPE_WM_LINETIME(pipe) _MMIO_PIPE(pipe, _PIPE_WM_LINETIME_A, _PIPE_WM_LINETIME_B) 7628 #define PIPE_WM_LINETIME_MASK (0x1ff) 7629 #define PIPE_WM_LINETIME_TIME(x) ((x)) 7630 #define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16) 7631 #define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16) 7632 7633 /* SFUSE_STRAP */ 7634 #define SFUSE_STRAP _MMIO(0xc2014) 7635 #define SFUSE_STRAP_FUSE_LOCK (1<<13) 7636 #define SFUSE_STRAP_DISPLAY_DISABLED (1<<7) 7637 #define SFUSE_STRAP_CRT_DISABLED (1<<6) 7638 #define SFUSE_STRAP_DDIB_DETECTED (1<<2) 7639 #define SFUSE_STRAP_DDIC_DETECTED (1<<1) 7640 #define SFUSE_STRAP_DDID_DETECTED (1<<0) 7641 7642 #define WM_MISC _MMIO(0x45260) 7643 #define WM_MISC_DATA_PARTITION_5_6 (1 << 0) 7644 7645 #define WM_DBG _MMIO(0x45280) 7646 #define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0) 7647 #define WM_DBG_DISALLOW_MAXFIFO (1<<1) 7648 #define WM_DBG_DISALLOW_SPRITE (1<<2) 7649 7650 /* pipe CSC */ 7651 #define _PIPE_A_CSC_COEFF_RY_GY 0x49010 7652 #define _PIPE_A_CSC_COEFF_BY 0x49014 7653 #define _PIPE_A_CSC_COEFF_RU_GU 0x49018 7654 #define _PIPE_A_CSC_COEFF_BU 0x4901c 7655 #define _PIPE_A_CSC_COEFF_RV_GV 0x49020 7656 #define _PIPE_A_CSC_COEFF_BV 0x49024 7657 #define _PIPE_A_CSC_MODE 0x49028 7658 #define CSC_BLACK_SCREEN_OFFSET (1 << 2) 7659 #define CSC_POSITION_BEFORE_GAMMA (1 << 1) 7660 #define CSC_MODE_YUV_TO_RGB (1 << 0) 7661 #define _PIPE_A_CSC_PREOFF_HI 0x49030 7662 #define _PIPE_A_CSC_PREOFF_ME 0x49034 7663 #define _PIPE_A_CSC_PREOFF_LO 0x49038 7664 #define _PIPE_A_CSC_POSTOFF_HI 0x49040 7665 #define _PIPE_A_CSC_POSTOFF_ME 0x49044 7666 #define _PIPE_A_CSC_POSTOFF_LO 0x49048 7667 7668 #define _PIPE_B_CSC_COEFF_RY_GY 0x49110 7669 #define _PIPE_B_CSC_COEFF_BY 0x49114 7670 #define _PIPE_B_CSC_COEFF_RU_GU 0x49118 7671 #define _PIPE_B_CSC_COEFF_BU 0x4911c 7672 #define _PIPE_B_CSC_COEFF_RV_GV 0x49120 7673 #define _PIPE_B_CSC_COEFF_BV 0x49124 7674 #define _PIPE_B_CSC_MODE 0x49128 7675 #define _PIPE_B_CSC_PREOFF_HI 0x49130 7676 #define _PIPE_B_CSC_PREOFF_ME 0x49134 7677 #define _PIPE_B_CSC_PREOFF_LO 0x49138 7678 #define _PIPE_B_CSC_POSTOFF_HI 0x49140 7679 #define _PIPE_B_CSC_POSTOFF_ME 0x49144 7680 #define _PIPE_B_CSC_POSTOFF_LO 0x49148 7681 7682 #define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY) 7683 #define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY) 7684 #define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU) 7685 #define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU) 7686 #define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV) 7687 #define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV) 7688 #define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE) 7689 #define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI) 7690 #define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME) 7691 #define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO) 7692 #define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI) 7693 #define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME) 7694 #define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) 7695 7696 /* pipe degamma/gamma LUTs on IVB+ */ 7697 #define _PAL_PREC_INDEX_A 0x4A400 7698 #define _PAL_PREC_INDEX_B 0x4AC00 7699 #define _PAL_PREC_INDEX_C 0x4B400 7700 #define PAL_PREC_10_12_BIT (0 << 31) 7701 #define PAL_PREC_SPLIT_MODE (1 << 31) 7702 #define PAL_PREC_AUTO_INCREMENT (1 << 15) 7703 #define _PAL_PREC_DATA_A 0x4A404 7704 #define _PAL_PREC_DATA_B 0x4AC04 7705 #define _PAL_PREC_DATA_C 0x4B404 7706 #define _PAL_PREC_GC_MAX_A 0x4A410 7707 #define _PAL_PREC_GC_MAX_B 0x4AC10 7708 #define _PAL_PREC_GC_MAX_C 0x4B410 7709 #define _PAL_PREC_EXT_GC_MAX_A 0x4A420 7710 #define _PAL_PREC_EXT_GC_MAX_B 0x4AC20 7711 #define _PAL_PREC_EXT_GC_MAX_C 0x4B420 7712 7713 #define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B) 7714 #define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B) 7715 #define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4) 7716 #define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4) 7717 7718 /* pipe CSC & degamma/gamma LUTs on CHV */ 7719 #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900) 7720 #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904) 7721 #define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908) 7722 #define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C) 7723 #define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910) 7724 #define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000) 7725 #define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000) 7726 #define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00) 7727 #define CGM_PIPE_MODE_GAMMA (1 << 2) 7728 #define CGM_PIPE_MODE_CSC (1 << 1) 7729 #define CGM_PIPE_MODE_DEGAMMA (1 << 0) 7730 7731 #define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900) 7732 #define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904) 7733 #define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908) 7734 #define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C) 7735 #define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910) 7736 #define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000) 7737 #define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000) 7738 #define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00) 7739 7740 #define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01) 7741 #define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23) 7742 #define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45) 7743 #define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67) 7744 #define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8) 7745 #define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4) 7746 #define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4) 7747 #define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE) 7748 7749 /* MIPI DSI registers */ 7750 7751 #define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */ 7752 #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c)) 7753 7754 /* BXT MIPI clock controls */ 7755 #define BXT_MAX_VAR_OUTPUT_KHZ 39500 7756 7757 #define BXT_MIPI_CLOCK_CTL _MMIO(0x46090) 7758 #define BXT_MIPI1_DIV_SHIFT 26 7759 #define BXT_MIPI2_DIV_SHIFT 10 7760 #define BXT_MIPI_DIV_SHIFT(port) \ 7761 _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \ 7762 BXT_MIPI2_DIV_SHIFT) 7763 7764 /* TX control divider to select actual TX clock output from (8x/var) */ 7765 #define BXT_MIPI1_TX_ESCLK_SHIFT 26 7766 #define BXT_MIPI2_TX_ESCLK_SHIFT 10 7767 #define BXT_MIPI_TX_ESCLK_SHIFT(port) \ 7768 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \ 7769 BXT_MIPI2_TX_ESCLK_SHIFT) 7770 #define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (0x3F << 26) 7771 #define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (0x3F << 10) 7772 #define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \ 7773 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \ 7774 BXT_MIPI2_TX_ESCLK_FIXDIV_MASK) 7775 #define BXT_MIPI_TX_ESCLK_DIVIDER(port, val) \ 7776 ((val & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port)) 7777 /* RX upper control divider to select actual RX clock output from 8x */ 7778 #define BXT_MIPI1_RX_ESCLK_UPPER_SHIFT 21 7779 #define BXT_MIPI2_RX_ESCLK_UPPER_SHIFT 5 7780 #define BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port) \ 7781 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \ 7782 BXT_MIPI2_RX_ESCLK_UPPER_SHIFT) 7783 #define BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 21) 7784 #define BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 5) 7785 #define BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port) \ 7786 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK, \ 7787 BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK) 7788 #define BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val) \ 7789 ((val & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port)) 7790 /* 8/3X divider to select the actual 8/3X clock output from 8x */ 7791 #define BXT_MIPI1_8X_BY3_SHIFT 19 7792 #define BXT_MIPI2_8X_BY3_SHIFT 3 7793 #define BXT_MIPI_8X_BY3_SHIFT(port) \ 7794 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \ 7795 BXT_MIPI2_8X_BY3_SHIFT) 7796 #define BXT_MIPI1_8X_BY3_DIVIDER_MASK (3 << 19) 7797 #define BXT_MIPI2_8X_BY3_DIVIDER_MASK (3 << 3) 7798 #define BXT_MIPI_8X_BY3_DIVIDER_MASK(port) \ 7799 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \ 7800 BXT_MIPI2_8X_BY3_DIVIDER_MASK) 7801 #define BXT_MIPI_8X_BY3_DIVIDER(port, val) \ 7802 ((val & 3) << BXT_MIPI_8X_BY3_SHIFT(port)) 7803 /* RX lower control divider to select actual RX clock output from 8x */ 7804 #define BXT_MIPI1_RX_ESCLK_LOWER_SHIFT 16 7805 #define BXT_MIPI2_RX_ESCLK_LOWER_SHIFT 0 7806 #define BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port) \ 7807 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \ 7808 BXT_MIPI2_RX_ESCLK_LOWER_SHIFT) 7809 #define BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 16) 7810 #define BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 0) 7811 #define BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port) \ 7812 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \ 7813 BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK) 7814 #define BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val) \ 7815 ((val & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port)) 7816 7817 #define RX_DIVIDER_BIT_1_2 0x3 7818 #define RX_DIVIDER_BIT_3_4 0xC 7819 7820 /* BXT MIPI mode configure */ 7821 #define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8 7822 #define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8 7823 #define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(tc, \ 7824 _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE) 7825 7826 #define _BXT_MIPIA_TRANS_VACTIVE 0x6B0FC 7827 #define _BXT_MIPIC_TRANS_VACTIVE 0x6B8FC 7828 #define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(tc, \ 7829 _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE) 7830 7831 #define _BXT_MIPIA_TRANS_VTOTAL 0x6B100 7832 #define _BXT_MIPIC_TRANS_VTOTAL 0x6B900 7833 #define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(tc, \ 7834 _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL) 7835 7836 #define BXT_DSI_PLL_CTL _MMIO(0x161000) 7837 #define BXT_DSI_PLL_PVD_RATIO_SHIFT 16 7838 #define BXT_DSI_PLL_PVD_RATIO_MASK (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT) 7839 #define BXT_DSI_PLL_PVD_RATIO_1 (1 << BXT_DSI_PLL_PVD_RATIO_SHIFT) 7840 #define BXT_DSIC_16X_BY2 (1 << 10) 7841 #define BXT_DSIC_16X_BY3 (2 << 10) 7842 #define BXT_DSIC_16X_BY4 (3 << 10) 7843 #define BXT_DSIC_16X_MASK (3 << 10) 7844 #define BXT_DSIA_16X_BY2 (1 << 8) 7845 #define BXT_DSIA_16X_BY3 (2 << 8) 7846 #define BXT_DSIA_16X_BY4 (3 << 8) 7847 #define BXT_DSIA_16X_MASK (3 << 8) 7848 #define BXT_DSI_FREQ_SEL_SHIFT 8 7849 #define BXT_DSI_FREQ_SEL_MASK (0xF << BXT_DSI_FREQ_SEL_SHIFT) 7850 7851 #define BXT_DSI_PLL_RATIO_MAX 0x7D 7852 #define BXT_DSI_PLL_RATIO_MIN 0x22 7853 #define BXT_DSI_PLL_RATIO_MASK 0xFF 7854 #define BXT_REF_CLOCK_KHZ 19200 7855 7856 #define BXT_DSI_PLL_ENABLE _MMIO(0x46080) 7857 #define BXT_DSI_PLL_DO_ENABLE (1 << 31) 7858 #define BXT_DSI_PLL_LOCKED (1 << 30) 7859 7860 #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) 7861 #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) 7862 #define MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL) 7863 7864 /* BXT port control */ 7865 #define _BXT_MIPIA_PORT_CTRL 0x6B0C0 7866 #define _BXT_MIPIC_PORT_CTRL 0x6B8C0 7867 #define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL) 7868 7869 #define DPI_ENABLE (1 << 31) /* A + C */ 7870 #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27 7871 #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27) 7872 #define DUAL_LINK_MODE_SHIFT 26 7873 #define DUAL_LINK_MODE_MASK (1 << 26) 7874 #define DUAL_LINK_MODE_FRONT_BACK (0 << 26) 7875 #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26) 7876 #define DITHERING_ENABLE (1 << 25) /* A + C */ 7877 #define FLOPPED_HSTX (1 << 23) 7878 #define DE_INVERT (1 << 19) /* XXX */ 7879 #define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18 7880 #define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18) 7881 #define AFE_LATCHOUT (1 << 17) 7882 #define LP_OUTPUT_HOLD (1 << 16) 7883 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15 7884 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15) 7885 #define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11 7886 #define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11) 7887 #define CSB_SHIFT 9 7888 #define CSB_MASK (3 << 9) 7889 #define CSB_20MHZ (0 << 9) 7890 #define CSB_10MHZ (1 << 9) 7891 #define CSB_40MHZ (2 << 9) 7892 #define BANDGAP_MASK (1 << 8) 7893 #define BANDGAP_PNW_CIRCUIT (0 << 8) 7894 #define BANDGAP_LNC_CIRCUIT (1 << 8) 7895 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5 7896 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5) 7897 #define TEARING_EFFECT_DELAY (1 << 4) /* A + C */ 7898 #define TEARING_EFFECT_SHIFT 2 /* A + C */ 7899 #define TEARING_EFFECT_MASK (3 << 2) 7900 #define TEARING_EFFECT_OFF (0 << 2) 7901 #define TEARING_EFFECT_DSI (1 << 2) 7902 #define TEARING_EFFECT_GPIO (2 << 2) 7903 #define LANE_CONFIGURATION_SHIFT 0 7904 #define LANE_CONFIGURATION_MASK (3 << 0) 7905 #define LANE_CONFIGURATION_4LANE (0 << 0) 7906 #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0) 7907 #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0) 7908 7909 #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194) 7910 #define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) 7911 #define MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL) 7912 #define TEARING_EFFECT_DELAY_SHIFT 0 7913 #define TEARING_EFFECT_DELAY_MASK (0xffff << 0) 7914 7915 /* XXX: all bits reserved */ 7916 #define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0) 7917 7918 /* MIPI DSI Controller and D-PHY registers */ 7919 7920 #define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000) 7921 #define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800) 7922 #define MIPI_DEVICE_READY(port) _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY) 7923 #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */ 7924 #define ULPS_STATE_MASK (3 << 1) 7925 #define ULPS_STATE_ENTER (2 << 1) 7926 #define ULPS_STATE_EXIT (1 << 1) 7927 #define ULPS_STATE_NORMAL_OPERATION (0 << 1) 7928 #define DEVICE_READY (1 << 0) 7929 7930 #define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004) 7931 #define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804) 7932 #define MIPI_INTR_STAT(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT) 7933 #define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008) 7934 #define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808) 7935 #define MIPI_INTR_EN(port) _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN) 7936 #define TEARING_EFFECT (1 << 31) 7937 #define SPL_PKT_SENT_INTERRUPT (1 << 30) 7938 #define GEN_READ_DATA_AVAIL (1 << 29) 7939 #define LP_GENERIC_WR_FIFO_FULL (1 << 28) 7940 #define HS_GENERIC_WR_FIFO_FULL (1 << 27) 7941 #define RX_PROT_VIOLATION (1 << 26) 7942 #define RX_INVALID_TX_LENGTH (1 << 25) 7943 #define ACK_WITH_NO_ERROR (1 << 24) 7944 #define TURN_AROUND_ACK_TIMEOUT (1 << 23) 7945 #define LP_RX_TIMEOUT (1 << 22) 7946 #define HS_TX_TIMEOUT (1 << 21) 7947 #define DPI_FIFO_UNDERRUN (1 << 20) 7948 #define LOW_CONTENTION (1 << 19) 7949 #define HIGH_CONTENTION (1 << 18) 7950 #define TXDSI_VC_ID_INVALID (1 << 17) 7951 #define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16) 7952 #define TXCHECKSUM_ERROR (1 << 15) 7953 #define TXECC_MULTIBIT_ERROR (1 << 14) 7954 #define TXECC_SINGLE_BIT_ERROR (1 << 13) 7955 #define TXFALSE_CONTROL_ERROR (1 << 12) 7956 #define RXDSI_VC_ID_INVALID (1 << 11) 7957 #define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10) 7958 #define RXCHECKSUM_ERROR (1 << 9) 7959 #define RXECC_MULTIBIT_ERROR (1 << 8) 7960 #define RXECC_SINGLE_BIT_ERROR (1 << 7) 7961 #define RXFALSE_CONTROL_ERROR (1 << 6) 7962 #define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5) 7963 #define RX_LP_TX_SYNC_ERROR (1 << 4) 7964 #define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3) 7965 #define RXEOT_SYNC_ERROR (1 << 2) 7966 #define RXSOT_SYNC_ERROR (1 << 1) 7967 #define RXSOT_ERROR (1 << 0) 7968 7969 #define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c) 7970 #define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c) 7971 #define MIPI_DSI_FUNC_PRG(port) _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG) 7972 #define CMD_MODE_DATA_WIDTH_MASK (7 << 13) 7973 #define CMD_MODE_NOT_SUPPORTED (0 << 13) 7974 #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13) 7975 #define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13) 7976 #define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13) 7977 #define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13) 7978 #define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13) 7979 #define VID_MODE_FORMAT_MASK (0xf << 7) 7980 #define VID_MODE_NOT_SUPPORTED (0 << 7) 7981 #define VID_MODE_FORMAT_RGB565 (1 << 7) 7982 #define VID_MODE_FORMAT_RGB666_PACKED (2 << 7) 7983 #define VID_MODE_FORMAT_RGB666 (3 << 7) 7984 #define VID_MODE_FORMAT_RGB888 (4 << 7) 7985 #define CMD_MODE_CHANNEL_NUMBER_SHIFT 5 7986 #define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5) 7987 #define VID_MODE_CHANNEL_NUMBER_SHIFT 3 7988 #define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3) 7989 #define DATA_LANES_PRG_REG_SHIFT 0 7990 #define DATA_LANES_PRG_REG_MASK (7 << 0) 7991 7992 #define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010) 7993 #define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810) 7994 #define MIPI_HS_TX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT) 7995 #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff 7996 7997 #define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014) 7998 #define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814) 7999 #define MIPI_LP_RX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT) 8000 #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff 8001 8002 #define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018) 8003 #define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818) 8004 #define MIPI_TURN_AROUND_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT) 8005 #define TURN_AROUND_TIMEOUT_MASK 0x3f 8006 8007 #define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c) 8008 #define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c) 8009 #define MIPI_DEVICE_RESET_TIMER(port) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER) 8010 #define DEVICE_RESET_TIMER_MASK 0xffff 8011 8012 #define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020) 8013 #define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820) 8014 #define MIPI_DPI_RESOLUTION(port) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION) 8015 #define VERTICAL_ADDRESS_SHIFT 16 8016 #define VERTICAL_ADDRESS_MASK (0xffff << 16) 8017 #define HORIZONTAL_ADDRESS_SHIFT 0 8018 #define HORIZONTAL_ADDRESS_MASK 0xffff 8019 8020 #define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024) 8021 #define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824) 8022 #define MIPI_DBI_FIFO_THROTTLE(port) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE) 8023 #define DBI_FIFO_EMPTY_HALF (0 << 0) 8024 #define DBI_FIFO_EMPTY_QUARTER (1 << 0) 8025 #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0) 8026 8027 /* regs below are bits 15:0 */ 8028 #define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028) 8029 #define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828) 8030 #define MIPI_HSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT) 8031 8032 #define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c) 8033 #define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c) 8034 #define MIPI_HBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT) 8035 8036 #define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030) 8037 #define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830) 8038 #define MIPI_HFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT) 8039 8040 #define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034) 8041 #define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834) 8042 #define MIPI_HACTIVE_AREA_COUNT(port) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT) 8043 8044 #define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038) 8045 #define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838) 8046 #define MIPI_VSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT) 8047 8048 #define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c) 8049 #define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c) 8050 #define MIPI_VBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT) 8051 8052 #define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040) 8053 #define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840) 8054 #define MIPI_VFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT) 8055 8056 #define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044) 8057 #define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844) 8058 #define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT) 8059 8060 /* regs above are bits 15:0 */ 8061 8062 #define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048) 8063 #define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848) 8064 #define MIPI_DPI_CONTROL(port) _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL) 8065 #define DPI_LP_MODE (1 << 6) 8066 #define BACKLIGHT_OFF (1 << 5) 8067 #define BACKLIGHT_ON (1 << 4) 8068 #define COLOR_MODE_OFF (1 << 3) 8069 #define COLOR_MODE_ON (1 << 2) 8070 #define TURN_ON (1 << 1) 8071 #define SHUTDOWN (1 << 0) 8072 8073 #define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c) 8074 #define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c) 8075 #define MIPI_DPI_DATA(port) _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA) 8076 #define COMMAND_BYTE_SHIFT 0 8077 #define COMMAND_BYTE_MASK (0x3f << 0) 8078 8079 #define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050) 8080 #define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850) 8081 #define MIPI_INIT_COUNT(port) _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT) 8082 #define MASTER_INIT_TIMER_SHIFT 0 8083 #define MASTER_INIT_TIMER_MASK (0xffff << 0) 8084 8085 #define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054) 8086 #define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854) 8087 #define MIPI_MAX_RETURN_PKT_SIZE(port) _MMIO_MIPI(port, \ 8088 _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE) 8089 #define MAX_RETURN_PKT_SIZE_SHIFT 0 8090 #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0) 8091 8092 #define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058) 8093 #define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858) 8094 #define MIPI_VIDEO_MODE_FORMAT(port) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT) 8095 #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4) 8096 #define DISABLE_VIDEO_BTA (1 << 3) 8097 #define IP_TG_CONFIG (1 << 2) 8098 #define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0) 8099 #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0) 8100 #define VIDEO_MODE_BURST (3 << 0) 8101 8102 #define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c) 8103 #define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c) 8104 #define MIPI_EOT_DISABLE(port) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE) 8105 #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7) 8106 #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6) 8107 #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5) 8108 #define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4) 8109 #define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3) 8110 #define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2) 8111 #define CLOCKSTOP (1 << 1) 8112 #define EOT_DISABLE (1 << 0) 8113 8114 #define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060) 8115 #define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860) 8116 #define MIPI_LP_BYTECLK(port) _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK) 8117 #define LP_BYTECLK_SHIFT 0 8118 #define LP_BYTECLK_MASK (0xffff << 0) 8119 8120 /* bits 31:0 */ 8121 #define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064) 8122 #define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864) 8123 #define MIPI_LP_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA) 8124 8125 /* bits 31:0 */ 8126 #define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068) 8127 #define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868) 8128 #define MIPI_HS_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA) 8129 8130 #define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c) 8131 #define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c) 8132 #define MIPI_LP_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL) 8133 #define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070) 8134 #define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870) 8135 #define MIPI_HS_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL) 8136 #define LONG_PACKET_WORD_COUNT_SHIFT 8 8137 #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8) 8138 #define SHORT_PACKET_PARAM_SHIFT 8 8139 #define SHORT_PACKET_PARAM_MASK (0xffff << 8) 8140 #define VIRTUAL_CHANNEL_SHIFT 6 8141 #define VIRTUAL_CHANNEL_MASK (3 << 6) 8142 #define DATA_TYPE_SHIFT 0 8143 #define DATA_TYPE_MASK (0x3f << 0) 8144 /* data type values, see include/video/mipi_display.h */ 8145 8146 #define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074) 8147 #define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874) 8148 #define MIPI_GEN_FIFO_STAT(port) _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT) 8149 #define DPI_FIFO_EMPTY (1 << 28) 8150 #define DBI_FIFO_EMPTY (1 << 27) 8151 #define LP_CTRL_FIFO_EMPTY (1 << 26) 8152 #define LP_CTRL_FIFO_HALF_EMPTY (1 << 25) 8153 #define LP_CTRL_FIFO_FULL (1 << 24) 8154 #define HS_CTRL_FIFO_EMPTY (1 << 18) 8155 #define HS_CTRL_FIFO_HALF_EMPTY (1 << 17) 8156 #define HS_CTRL_FIFO_FULL (1 << 16) 8157 #define LP_DATA_FIFO_EMPTY (1 << 10) 8158 #define LP_DATA_FIFO_HALF_EMPTY (1 << 9) 8159 #define LP_DATA_FIFO_FULL (1 << 8) 8160 #define HS_DATA_FIFO_EMPTY (1 << 2) 8161 #define HS_DATA_FIFO_HALF_EMPTY (1 << 1) 8162 #define HS_DATA_FIFO_FULL (1 << 0) 8163 8164 #define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078) 8165 #define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878) 8166 #define MIPI_HS_LP_DBI_ENABLE(port) _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE) 8167 #define DBI_HS_LP_MODE_MASK (1 << 0) 8168 #define DBI_LP_MODE (1 << 0) 8169 #define DBI_HS_MODE (0 << 0) 8170 8171 #define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080) 8172 #define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880) 8173 #define MIPI_DPHY_PARAM(port) _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM) 8174 #define EXIT_ZERO_COUNT_SHIFT 24 8175 #define EXIT_ZERO_COUNT_MASK (0x3f << 24) 8176 #define TRAIL_COUNT_SHIFT 16 8177 #define TRAIL_COUNT_MASK (0x1f << 16) 8178 #define CLK_ZERO_COUNT_SHIFT 8 8179 #define CLK_ZERO_COUNT_MASK (0xff << 8) 8180 #define PREPARE_COUNT_SHIFT 0 8181 #define PREPARE_COUNT_MASK (0x3f << 0) 8182 8183 /* bits 31:0 */ 8184 #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084) 8185 #define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884) 8186 #define MIPI_DBI_BW_CTRL(port) _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL) 8187 8188 #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb088) 8189 #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb888) 8190 #define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT) 8191 #define LP_HS_SSW_CNT_SHIFT 16 8192 #define LP_HS_SSW_CNT_MASK (0xffff << 16) 8193 #define HS_LP_PWR_SW_CNT_SHIFT 0 8194 #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0) 8195 8196 #define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c) 8197 #define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c) 8198 #define MIPI_STOP_STATE_STALL(port) _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL) 8199 #define STOP_STATE_STALL_COUNTER_SHIFT 0 8200 #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0) 8201 8202 #define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090) 8203 #define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890) 8204 #define MIPI_INTR_STAT_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1) 8205 #define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094) 8206 #define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894) 8207 #define MIPI_INTR_EN_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1) 8208 #define RX_CONTENTION_DETECTED (1 << 0) 8209 8210 /* XXX: only pipe A ?!? */ 8211 #define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100) 8212 #define DBI_TYPEC_ENABLE (1 << 31) 8213 #define DBI_TYPEC_WIP (1 << 30) 8214 #define DBI_TYPEC_OPTION_SHIFT 28 8215 #define DBI_TYPEC_OPTION_MASK (3 << 28) 8216 #define DBI_TYPEC_FREQ_SHIFT 24 8217 #define DBI_TYPEC_FREQ_MASK (0xf << 24) 8218 #define DBI_TYPEC_OVERRIDE (1 << 8) 8219 #define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0 8220 #define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0) 8221 8222 8223 /* MIPI adapter registers */ 8224 8225 #define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104) 8226 #define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904) 8227 #define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL) 8228 #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */ 8229 #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5) 8230 #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5) 8231 #define ESCAPE_CLOCK_DIVIDER_2 (1 << 5) 8232 #define ESCAPE_CLOCK_DIVIDER_4 (2 << 5) 8233 #define READ_REQUEST_PRIORITY_SHIFT 3 8234 #define READ_REQUEST_PRIORITY_MASK (3 << 3) 8235 #define READ_REQUEST_PRIORITY_LOW (0 << 3) 8236 #define READ_REQUEST_PRIORITY_HIGH (3 << 3) 8237 #define RGB_FLIP_TO_BGR (1 << 2) 8238 8239 #define BXT_PIPE_SELECT_SHIFT 7 8240 #define BXT_PIPE_SELECT_MASK (7 << 7) 8241 #define BXT_PIPE_SELECT(pipe) ((pipe) << 7) 8242 8243 #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108) 8244 #define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908) 8245 #define MIPI_DATA_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS) 8246 #define DATA_MEM_ADDRESS_SHIFT 5 8247 #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5) 8248 #define DATA_VALID (1 << 0) 8249 8250 #define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c) 8251 #define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c) 8252 #define MIPI_DATA_LENGTH(port) _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH) 8253 #define DATA_LENGTH_SHIFT 0 8254 #define DATA_LENGTH_MASK (0xfffff << 0) 8255 8256 #define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110) 8257 #define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910) 8258 #define MIPI_COMMAND_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS) 8259 #define COMMAND_MEM_ADDRESS_SHIFT 5 8260 #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5) 8261 #define AUTO_PWG_ENABLE (1 << 2) 8262 #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1) 8263 #define COMMAND_VALID (1 << 0) 8264 8265 #define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114) 8266 #define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914) 8267 #define MIPI_COMMAND_LENGTH(port) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH) 8268 #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */ 8269 #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n))) 8270 8271 #define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118) 8272 #define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918) 8273 #define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */ 8274 8275 #define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138) 8276 #define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938) 8277 #define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID) 8278 #define READ_DATA_VALID(n) (1 << (n)) 8279 8280 /* For UMS only (deprecated): */ 8281 #define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000) 8282 #define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800) 8283 8284 /* MOCS (Memory Object Control State) registers */ 8285 #define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */ 8286 8287 #define GEN9_GFX_MOCS(i) _MMIO(0xc800 + (i) * 4) /* Graphics MOCS registers */ 8288 #define GEN9_MFX0_MOCS(i) _MMIO(0xc900 + (i) * 4) /* Media 0 MOCS registers */ 8289 #define GEN9_MFX1_MOCS(i) _MMIO(0xca00 + (i) * 4) /* Media 1 MOCS registers */ 8290 #define GEN9_VEBOX_MOCS(i) _MMIO(0xcb00 + (i) * 4) /* Video MOCS registers */ 8291 #define GEN9_BLT_MOCS(i) _MMIO(0xcc00 + (i) * 4) /* Blitter MOCS registers */ 8292 8293 /* gamt regs */ 8294 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4) 8295 #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */ 8296 #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF /* max/min for LRA1/2 */ 8297 #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL 0x67F1427F /* " " */ 8298 #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT 0x5FF101FF /* " " */ 8299 8300 #endif /* _I915_REG_H_ */ 8301