1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 2 * All Rights Reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef _I915_REG_H_ 26 #define _I915_REG_H_ 27 28 #include "i915_reg_defs.h" 29 30 /** 31 * DOC: The i915 register macro definition style guide 32 * 33 * Follow the style described here for new macros, and while changing existing 34 * macros. Do **not** mass change existing definitions just to update the style. 35 * 36 * File Layout 37 * ~~~~~~~~~~~ 38 * 39 * Keep helper macros near the top. For example, _PIPE() and friends. 40 * 41 * Prefix macros that generally should not be used outside of this file with 42 * underscore '_'. For example, _PIPE() and friends, single instances of 43 * registers that are defined solely for the use by function-like macros. 44 * 45 * Avoid using the underscore prefixed macros outside of this file. There are 46 * exceptions, but keep them to a minimum. 47 * 48 * There are two basic types of register definitions: Single registers and 49 * register groups. Register groups are registers which have two or more 50 * instances, for example one per pipe, port, transcoder, etc. Register groups 51 * should be defined using function-like macros. 52 * 53 * For single registers, define the register offset first, followed by register 54 * contents. 55 * 56 * For register groups, define the register instance offsets first, prefixed 57 * with underscore, followed by a function-like macro choosing the right 58 * instance based on the parameter, followed by register contents. 59 * 60 * Define the register contents (i.e. bit and bit field macros) from most 61 * significant to least significant bit. Indent the register content macros 62 * using two extra spaces between ``#define`` and the macro name. 63 * 64 * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents 65 * using ``REG_FIELD_PREP(mask, value)``. This will define the values already 66 * shifted in place, so they can be directly OR'd together. For convenience, 67 * function-like macros may be used to define bit fields, but do note that the 68 * macros may be needed to read as well as write the register contents. 69 * 70 * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name. 71 * 72 * Group the register and its contents together without blank lines, separate 73 * from other registers and their contents with one blank line. 74 * 75 * Indent macro values from macro names using TABs. Align values vertically. Use 76 * braces in macro values as needed to avoid unintended precedence after macro 77 * substitution. Use spaces in macro values according to kernel coding 78 * style. Use lower case in hexadecimal values. 79 * 80 * Naming 81 * ~~~~~~ 82 * 83 * Try to name registers according to the specs. If the register name changes in 84 * the specs from platform to another, stick to the original name. 85 * 86 * Try to re-use existing register macro definitions. Only add new macros for 87 * new register offsets, or when the register contents have changed enough to 88 * warrant a full redefinition. 89 * 90 * When a register macro changes for a new platform, prefix the new macro using 91 * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The 92 * prefix signifies the start platform/generation using the register. 93 * 94 * When a bit (field) macro changes or gets added for a new platform, while 95 * retaining the existing register macro, add a platform acronym or generation 96 * suffix to the name. For example, ``_SKL`` or ``_GEN8``. 97 * 98 * Examples 99 * ~~~~~~~~ 100 * 101 * (Note that the values in the example are indented using spaces instead of 102 * TABs to avoid misalignment in generated documentation. Use TABs in the 103 * definitions.):: 104 * 105 * #define _FOO_A 0xf000 106 * #define _FOO_B 0xf001 107 * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B) 108 * #define FOO_ENABLE REG_BIT(31) 109 * #define FOO_MODE_MASK REG_GENMASK(19, 16) 110 * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0) 111 * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1) 112 * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2) 113 * 114 * #define BAR _MMIO(0xb000) 115 * #define GEN8_BAR _MMIO(0xb888) 116 */ 117 118 #define DISPLAY_MMIO_BASE(dev_priv) (INTEL_INFO(dev_priv)->display.mmio_offset) 119 120 /* 121 * Given the first two numbers __a and __b of arbitrarily many evenly spaced 122 * numbers, pick the 0-based __index'th value. 123 * 124 * Always prefer this over _PICK() if the numbers are evenly spaced. 125 */ 126 #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a))) 127 128 /* 129 * Given the arbitrary numbers in varargs, pick the 0-based __index'th number. 130 * 131 * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced. 132 */ 133 #define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index]) 134 135 /* 136 * Named helper wrappers around _PICK_EVEN() and _PICK(). 137 */ 138 #define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b) 139 #define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b) 140 #define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b) 141 #define _PORT(port, a, b) _PICK_EVEN(port, a, b) 142 #define _PLL(pll, a, b) _PICK_EVEN(pll, a, b) 143 #define _PHY(phy, a, b) _PICK_EVEN(phy, a, b) 144 145 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) 146 #define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b)) 147 #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b)) 148 #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b)) 149 #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b)) 150 #define _MMIO_PHY(phy, a, b) _MMIO(_PHY(phy, a, b)) 151 152 #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__) 153 154 #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) 155 #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) 156 #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c)) 157 #define _MMIO_PLL3(pll, ...) _MMIO(_PICK(pll, __VA_ARGS__)) 158 159 160 /* 161 * Device info offset array based helpers for groups of registers with unevenly 162 * spaced base offsets. 163 */ 164 #define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->display.pipe_offsets[(pipe)] - \ 165 INTEL_INFO(dev_priv)->display.pipe_offsets[PIPE_A] + \ 166 DISPLAY_MMIO_BASE(dev_priv) + (reg)) 167 #define _MMIO_TRANS2(tran, reg) _MMIO(INTEL_INFO(dev_priv)->display.trans_offsets[(tran)] - \ 168 INTEL_INFO(dev_priv)->display.trans_offsets[TRANSCODER_A] + \ 169 DISPLAY_MMIO_BASE(dev_priv) + (reg)) 170 #define _MMIO_CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->display.cursor_offsets[(pipe)] - \ 171 INTEL_INFO(dev_priv)->display.cursor_offsets[PIPE_A] + \ 172 DISPLAY_MMIO_BASE(dev_priv) + (reg)) 173 174 #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value)) 175 #define _MASKED_FIELD(mask, value) ({ \ 176 if (__builtin_constant_p(mask)) \ 177 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \ 178 if (__builtin_constant_p(value)) \ 179 BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \ 180 if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \ 181 BUILD_BUG_ON_MSG((value) & ~(mask), \ 182 "Incorrect value for mask"); \ 183 __MASKED_FIELD(mask, value); }) 184 #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) 185 #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0)) 186 187 #define GU_CNTL _MMIO(0x101010) 188 #define LMEM_INIT REG_BIT(7) 189 #define DRIVERFLR REG_BIT(31) 190 #define GU_DEBUG _MMIO(0x101018) 191 #define DRIVERFLR_STATUS REG_BIT(31) 192 193 #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0) 194 #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20) 195 #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18) 196 #define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4) 197 #define GEN6_STOLEN_RESERVED_1M (0 << 4) 198 #define GEN6_STOLEN_RESERVED_512K (1 << 4) 199 #define GEN6_STOLEN_RESERVED_256K (2 << 4) 200 #define GEN6_STOLEN_RESERVED_128K (3 << 4) 201 #define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5) 202 #define GEN7_STOLEN_RESERVED_1M (0 << 5) 203 #define GEN7_STOLEN_RESERVED_256K (1 << 5) 204 #define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7) 205 #define GEN8_STOLEN_RESERVED_1M (0 << 7) 206 #define GEN8_STOLEN_RESERVED_2M (1 << 7) 207 #define GEN8_STOLEN_RESERVED_4M (2 << 7) 208 #define GEN8_STOLEN_RESERVED_8M (3 << 7) 209 #define GEN6_STOLEN_RESERVED_ENABLE (1 << 0) 210 #define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20) 211 212 #define _VGA_MSR_WRITE _MMIO(0x3c2) 213 214 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 215 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068 216 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL) 217 218 /* 219 * Reset registers 220 */ 221 #define DEBUG_RESET_I830 _MMIO(0x6070) 222 #define DEBUG_RESET_FULL (1 << 7) 223 #define DEBUG_RESET_RENDER (1 << 8) 224 #define DEBUG_RESET_DISPLAY (1 << 9) 225 226 /* 227 * IOSF sideband 228 */ 229 #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100) 230 #define IOSF_DEVFN_SHIFT 24 231 #define IOSF_OPCODE_SHIFT 16 232 #define IOSF_PORT_SHIFT 8 233 #define IOSF_BYTE_ENABLES_SHIFT 4 234 #define IOSF_BAR_SHIFT 1 235 #define IOSF_SB_BUSY (1 << 0) 236 #define IOSF_PORT_BUNIT 0x03 237 #define IOSF_PORT_PUNIT 0x04 238 #define IOSF_PORT_NC 0x11 239 #define IOSF_PORT_DPIO 0x12 240 #define IOSF_PORT_GPIO_NC 0x13 241 #define IOSF_PORT_CCK 0x14 242 #define IOSF_PORT_DPIO_2 0x1a 243 #define IOSF_PORT_FLISDSI 0x1b 244 #define IOSF_PORT_GPIO_SC 0x48 245 #define IOSF_PORT_GPIO_SUS 0xa8 246 #define IOSF_PORT_CCU 0xa9 247 #define CHV_IOSF_PORT_GPIO_N 0x13 248 #define CHV_IOSF_PORT_GPIO_SE 0x48 249 #define CHV_IOSF_PORT_GPIO_E 0xa8 250 #define CHV_IOSF_PORT_GPIO_SW 0xb2 251 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104) 252 #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108) 253 254 /* DPIO registers */ 255 #define DPIO_DEVFN 0 256 257 #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110) 258 #define DPIO_MODSEL1 (1 << 3) /* if ref clk b == 27 */ 259 #define DPIO_MODSEL0 (1 << 2) /* if ref clk a == 27 */ 260 #define DPIO_SFR_BYPASS (1 << 1) 261 #define DPIO_CMNRST (1 << 0) 262 263 #define DPIO_PHY(pipe) ((pipe) >> 1) 264 265 /* 266 * Per pipe/PLL DPIO regs 267 */ 268 #define _VLV_PLL_DW3_CH0 0x800c 269 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ 270 #define DPIO_POST_DIV_DAC 0 271 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ 272 #define DPIO_POST_DIV_LVDS1 2 273 #define DPIO_POST_DIV_LVDS2 3 274 #define DPIO_K_SHIFT (24) /* 4 bits */ 275 #define DPIO_P1_SHIFT (21) /* 3 bits */ 276 #define DPIO_P2_SHIFT (16) /* 5 bits */ 277 #define DPIO_N_SHIFT (12) /* 4 bits */ 278 #define DPIO_ENABLE_CALIBRATION (1 << 11) 279 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */ 280 #define DPIO_M2DIV_MASK 0xff 281 #define _VLV_PLL_DW3_CH1 0x802c 282 #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1) 283 284 #define _VLV_PLL_DW5_CH0 0x8014 285 #define DPIO_REFSEL_OVERRIDE 27 286 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ 287 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ 288 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ 289 #define DPIO_PLL_REFCLK_SEL_MASK 3 290 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ 291 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ 292 #define _VLV_PLL_DW5_CH1 0x8034 293 #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1) 294 295 #define _VLV_PLL_DW7_CH0 0x801c 296 #define _VLV_PLL_DW7_CH1 0x803c 297 #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1) 298 299 #define _VLV_PLL_DW8_CH0 0x8040 300 #define _VLV_PLL_DW8_CH1 0x8060 301 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1) 302 303 #define VLV_PLL_DW9_BCAST 0xc044 304 #define _VLV_PLL_DW9_CH0 0x8044 305 #define _VLV_PLL_DW9_CH1 0x8064 306 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1) 307 308 #define _VLV_PLL_DW10_CH0 0x8048 309 #define _VLV_PLL_DW10_CH1 0x8068 310 #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1) 311 312 #define _VLV_PLL_DW11_CH0 0x804c 313 #define _VLV_PLL_DW11_CH1 0x806c 314 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1) 315 316 /* Spec for ref block start counts at DW10 */ 317 #define VLV_REF_DW13 0x80ac 318 319 #define VLV_CMN_DW0 0x8100 320 321 /* 322 * Per DDI channel DPIO regs 323 */ 324 325 #define _VLV_PCS_DW0_CH0 0x8200 326 #define _VLV_PCS_DW0_CH1 0x8400 327 #define DPIO_PCS_TX_LANE2_RESET (1 << 16) 328 #define DPIO_PCS_TX_LANE1_RESET (1 << 7) 329 #define DPIO_LEFT_TXFIFO_RST_MASTER2 (1 << 4) 330 #define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3) 331 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1) 332 333 #define _VLV_PCS01_DW0_CH0 0x200 334 #define _VLV_PCS23_DW0_CH0 0x400 335 #define _VLV_PCS01_DW0_CH1 0x2600 336 #define _VLV_PCS23_DW0_CH1 0x2800 337 #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1) 338 #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1) 339 340 #define _VLV_PCS_DW1_CH0 0x8204 341 #define _VLV_PCS_DW1_CH1 0x8404 342 #define CHV_PCS_REQ_SOFTRESET_EN (1 << 23) 343 #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22) 344 #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21) 345 #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6) 346 #define DPIO_PCS_CLK_SOFT_RESET (1 << 5) 347 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1) 348 349 #define _VLV_PCS01_DW1_CH0 0x204 350 #define _VLV_PCS23_DW1_CH0 0x404 351 #define _VLV_PCS01_DW1_CH1 0x2604 352 #define _VLV_PCS23_DW1_CH1 0x2804 353 #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1) 354 #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1) 355 356 #define _VLV_PCS_DW8_CH0 0x8220 357 #define _VLV_PCS_DW8_CH1 0x8420 358 #define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20) 359 #define CHV_PCS_USEDCLKCHANNEL (1 << 21) 360 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1) 361 362 #define _VLV_PCS01_DW8_CH0 0x0220 363 #define _VLV_PCS23_DW8_CH0 0x0420 364 #define _VLV_PCS01_DW8_CH1 0x2620 365 #define _VLV_PCS23_DW8_CH1 0x2820 366 #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1) 367 #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1) 368 369 #define _VLV_PCS_DW9_CH0 0x8224 370 #define _VLV_PCS_DW9_CH1 0x8424 371 #define DPIO_PCS_TX2MARGIN_MASK (0x7 << 13) 372 #define DPIO_PCS_TX2MARGIN_000 (0 << 13) 373 #define DPIO_PCS_TX2MARGIN_101 (1 << 13) 374 #define DPIO_PCS_TX1MARGIN_MASK (0x7 << 10) 375 #define DPIO_PCS_TX1MARGIN_000 (0 << 10) 376 #define DPIO_PCS_TX1MARGIN_101 (1 << 10) 377 #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1) 378 379 #define _VLV_PCS01_DW9_CH0 0x224 380 #define _VLV_PCS23_DW9_CH0 0x424 381 #define _VLV_PCS01_DW9_CH1 0x2624 382 #define _VLV_PCS23_DW9_CH1 0x2824 383 #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1) 384 #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1) 385 386 #define _CHV_PCS_DW10_CH0 0x8228 387 #define _CHV_PCS_DW10_CH1 0x8428 388 #define DPIO_PCS_SWING_CALC_TX0_TX2 (1 << 30) 389 #define DPIO_PCS_SWING_CALC_TX1_TX3 (1 << 31) 390 #define DPIO_PCS_TX2DEEMP_MASK (0xf << 24) 391 #define DPIO_PCS_TX2DEEMP_9P5 (0 << 24) 392 #define DPIO_PCS_TX2DEEMP_6P0 (2 << 24) 393 #define DPIO_PCS_TX1DEEMP_MASK (0xf << 16) 394 #define DPIO_PCS_TX1DEEMP_9P5 (0 << 16) 395 #define DPIO_PCS_TX1DEEMP_6P0 (2 << 16) 396 #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1) 397 398 #define _VLV_PCS01_DW10_CH0 0x0228 399 #define _VLV_PCS23_DW10_CH0 0x0428 400 #define _VLV_PCS01_DW10_CH1 0x2628 401 #define _VLV_PCS23_DW10_CH1 0x2828 402 #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1) 403 #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1) 404 405 #define _VLV_PCS_DW11_CH0 0x822c 406 #define _VLV_PCS_DW11_CH1 0x842c 407 #define DPIO_TX2_STAGGER_MASK(x) ((x) << 24) 408 #define DPIO_LANEDESKEW_STRAP_OVRD (1 << 3) 409 #define DPIO_LEFT_TXFIFO_RST_MASTER (1 << 1) 410 #define DPIO_RIGHT_TXFIFO_RST_MASTER (1 << 0) 411 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1) 412 413 #define _VLV_PCS01_DW11_CH0 0x022c 414 #define _VLV_PCS23_DW11_CH0 0x042c 415 #define _VLV_PCS01_DW11_CH1 0x262c 416 #define _VLV_PCS23_DW11_CH1 0x282c 417 #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1) 418 #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1) 419 420 #define _VLV_PCS01_DW12_CH0 0x0230 421 #define _VLV_PCS23_DW12_CH0 0x0430 422 #define _VLV_PCS01_DW12_CH1 0x2630 423 #define _VLV_PCS23_DW12_CH1 0x2830 424 #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1) 425 #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1) 426 427 #define _VLV_PCS_DW12_CH0 0x8230 428 #define _VLV_PCS_DW12_CH1 0x8430 429 #define DPIO_TX2_STAGGER_MULT(x) ((x) << 20) 430 #define DPIO_TX1_STAGGER_MULT(x) ((x) << 16) 431 #define DPIO_TX1_STAGGER_MASK(x) ((x) << 8) 432 #define DPIO_LANESTAGGER_STRAP_OVRD (1 << 6) 433 #define DPIO_LANESTAGGER_STRAP(x) ((x) << 0) 434 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1) 435 436 #define _VLV_PCS_DW14_CH0 0x8238 437 #define _VLV_PCS_DW14_CH1 0x8438 438 #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1) 439 440 #define _VLV_PCS_DW23_CH0 0x825c 441 #define _VLV_PCS_DW23_CH1 0x845c 442 #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1) 443 444 #define _VLV_TX_DW2_CH0 0x8288 445 #define _VLV_TX_DW2_CH1 0x8488 446 #define DPIO_SWING_MARGIN000_SHIFT 16 447 #define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT) 448 #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8 449 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1) 450 451 #define _VLV_TX_DW3_CH0 0x828c 452 #define _VLV_TX_DW3_CH1 0x848c 453 /* The following bit for CHV phy */ 454 #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1 << 27) 455 #define DPIO_SWING_MARGIN101_SHIFT 16 456 #define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT) 457 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1) 458 459 #define _VLV_TX_DW4_CH0 0x8290 460 #define _VLV_TX_DW4_CH1 0x8490 461 #define DPIO_SWING_DEEMPH9P5_SHIFT 24 462 #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT) 463 #define DPIO_SWING_DEEMPH6P0_SHIFT 16 464 #define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT) 465 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1) 466 467 #define _VLV_TX3_DW4_CH0 0x690 468 #define _VLV_TX3_DW4_CH1 0x2a90 469 #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1) 470 471 #define _VLV_TX_DW5_CH0 0x8294 472 #define _VLV_TX_DW5_CH1 0x8494 473 #define DPIO_TX_OCALINIT_EN (1 << 31) 474 #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1) 475 476 #define _VLV_TX_DW11_CH0 0x82ac 477 #define _VLV_TX_DW11_CH1 0x84ac 478 #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1) 479 480 #define _VLV_TX_DW14_CH0 0x82b8 481 #define _VLV_TX_DW14_CH1 0x84b8 482 #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1) 483 484 /* CHV dpPhy registers */ 485 #define _CHV_PLL_DW0_CH0 0x8000 486 #define _CHV_PLL_DW0_CH1 0x8180 487 #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1) 488 489 #define _CHV_PLL_DW1_CH0 0x8004 490 #define _CHV_PLL_DW1_CH1 0x8184 491 #define DPIO_CHV_N_DIV_SHIFT 8 492 #define DPIO_CHV_M1_DIV_BY_2 (0 << 0) 493 #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1) 494 495 #define _CHV_PLL_DW2_CH0 0x8008 496 #define _CHV_PLL_DW2_CH1 0x8188 497 #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1) 498 499 #define _CHV_PLL_DW3_CH0 0x800c 500 #define _CHV_PLL_DW3_CH1 0x818c 501 #define DPIO_CHV_FRAC_DIV_EN (1 << 16) 502 #define DPIO_CHV_FIRST_MOD (0 << 8) 503 #define DPIO_CHV_SECOND_MOD (1 << 8) 504 #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0 505 #define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0) 506 #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1) 507 508 #define _CHV_PLL_DW6_CH0 0x8018 509 #define _CHV_PLL_DW6_CH1 0x8198 510 #define DPIO_CHV_GAIN_CTRL_SHIFT 16 511 #define DPIO_CHV_INT_COEFF_SHIFT 8 512 #define DPIO_CHV_PROP_COEFF_SHIFT 0 513 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1) 514 515 #define _CHV_PLL_DW8_CH0 0x8020 516 #define _CHV_PLL_DW8_CH1 0x81A0 517 #define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0 518 #define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0) 519 #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1) 520 521 #define _CHV_PLL_DW9_CH0 0x8024 522 #define _CHV_PLL_DW9_CH1 0x81A4 523 #define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */ 524 #define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1) 525 #define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */ 526 #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1) 527 528 #define _CHV_CMN_DW0_CH0 0x8100 529 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19 530 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18 531 #define DPIO_ALLDL_POWERDOWN (1 << 1) 532 #define DPIO_ANYDL_POWERDOWN (1 << 0) 533 534 #define _CHV_CMN_DW5_CH0 0x8114 535 #define CHV_BUFRIGHTENA1_DISABLE (0 << 20) 536 #define CHV_BUFRIGHTENA1_NORMAL (1 << 20) 537 #define CHV_BUFRIGHTENA1_FORCE (3 << 20) 538 #define CHV_BUFRIGHTENA1_MASK (3 << 20) 539 #define CHV_BUFLEFTENA1_DISABLE (0 << 22) 540 #define CHV_BUFLEFTENA1_NORMAL (1 << 22) 541 #define CHV_BUFLEFTENA1_FORCE (3 << 22) 542 #define CHV_BUFLEFTENA1_MASK (3 << 22) 543 544 #define _CHV_CMN_DW13_CH0 0x8134 545 #define _CHV_CMN_DW0_CH1 0x8080 546 #define DPIO_CHV_S1_DIV_SHIFT 21 547 #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */ 548 #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */ 549 #define DPIO_CHV_K_DIV_SHIFT 4 550 #define DPIO_PLL_FREQLOCK (1 << 1) 551 #define DPIO_PLL_LOCK (1 << 0) 552 #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1) 553 554 #define _CHV_CMN_DW14_CH0 0x8138 555 #define _CHV_CMN_DW1_CH1 0x8084 556 #define DPIO_AFC_RECAL (1 << 14) 557 #define DPIO_DCLKP_EN (1 << 13) 558 #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */ 559 #define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */ 560 #define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */ 561 #define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */ 562 #define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */ 563 #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */ 564 #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */ 565 #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */ 566 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1) 567 568 #define _CHV_CMN_DW19_CH0 0x814c 569 #define _CHV_CMN_DW6_CH1 0x8098 570 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */ 571 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */ 572 #define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */ 573 #define CHV_CMN_USEDCLKCHANNEL (1 << 13) 574 575 #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1) 576 577 #define CHV_CMN_DW28 0x8170 578 #define DPIO_CL1POWERDOWNEN (1 << 23) 579 #define DPIO_DYNPWRDOWNEN_CH0 (1 << 22) 580 #define DPIO_SUS_CLK_CONFIG_ON (0 << 0) 581 #define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0) 582 #define DPIO_SUS_CLK_CONFIG_GATE (2 << 0) 583 #define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0) 584 585 #define CHV_CMN_DW30 0x8178 586 #define DPIO_CL2_LDOFUSE_PWRENB (1 << 6) 587 #define DPIO_LRC_BYPASS (1 << 3) 588 589 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \ 590 (lane) * 0x200 + (offset)) 591 592 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80) 593 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84) 594 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88) 595 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c) 596 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90) 597 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94) 598 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98) 599 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c) 600 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0) 601 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4) 602 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8) 603 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac) 604 #define DPIO_FRC_LATENCY_SHFIT 8 605 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8) 606 #define DPIO_UPAR_SHIFT 30 607 608 /* BXT PHY registers */ 609 #define _BXT_PHY0_BASE 0x6C000 610 #define _BXT_PHY1_BASE 0x162000 611 #define _BXT_PHY2_BASE 0x163000 612 #define BXT_PHY_BASE(phy) _PHY3((phy), _BXT_PHY0_BASE, \ 613 _BXT_PHY1_BASE, \ 614 _BXT_PHY2_BASE) 615 616 #define _BXT_PHY(phy, reg) \ 617 _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg)) 618 619 #define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \ 620 (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \ 621 (reg_ch1) - _BXT_PHY0_BASE)) 622 #define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \ 623 _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1)) 624 625 #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090) 626 #define MIPIO_RST_CTRL (1 << 2) 627 628 #define _BXT_PHY_CTL_DDI_A 0x64C00 629 #define _BXT_PHY_CTL_DDI_B 0x64C10 630 #define _BXT_PHY_CTL_DDI_C 0x64C20 631 #define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10) 632 #define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9) 633 #define BXT_PHY_LANE_ENABLED (1 << 8) 634 #define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \ 635 _BXT_PHY_CTL_DDI_B) 636 637 #define _PHY_CTL_FAMILY_EDP 0x64C80 638 #define _PHY_CTL_FAMILY_DDI 0x64C90 639 #define _PHY_CTL_FAMILY_DDI_C 0x64CA0 640 #define COMMON_RESET_DIS (1 << 31) 641 #define BXT_PHY_CTL_FAMILY(phy) _MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \ 642 _PHY_CTL_FAMILY_EDP, \ 643 _PHY_CTL_FAMILY_DDI_C) 644 645 /* BXT PHY PLL registers */ 646 #define _PORT_PLL_A 0x46074 647 #define _PORT_PLL_B 0x46078 648 #define _PORT_PLL_C 0x4607c 649 #define PORT_PLL_ENABLE REG_BIT(31) 650 #define PORT_PLL_LOCK REG_BIT(30) 651 #define PORT_PLL_REF_SEL REG_BIT(27) 652 #define PORT_PLL_POWER_ENABLE REG_BIT(26) 653 #define PORT_PLL_POWER_STATE REG_BIT(25) 654 #define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B) 655 656 #define _PORT_PLL_EBB_0_A 0x162034 657 #define _PORT_PLL_EBB_0_B 0x6C034 658 #define _PORT_PLL_EBB_0_C 0x6C340 659 #define PORT_PLL_P1_MASK REG_GENMASK(15, 13) 660 #define PORT_PLL_P1(p1) REG_FIELD_PREP(PORT_PLL_P1_MASK, (p1)) 661 #define PORT_PLL_P2_MASK REG_GENMASK(12, 8) 662 #define PORT_PLL_P2(p2) REG_FIELD_PREP(PORT_PLL_P2_MASK, (p2)) 663 #define BXT_PORT_PLL_EBB_0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 664 _PORT_PLL_EBB_0_B, \ 665 _PORT_PLL_EBB_0_C) 666 667 #define _PORT_PLL_EBB_4_A 0x162038 668 #define _PORT_PLL_EBB_4_B 0x6C038 669 #define _PORT_PLL_EBB_4_C 0x6C344 670 #define PORT_PLL_RECALIBRATE REG_BIT(14) 671 #define PORT_PLL_10BIT_CLK_ENABLE REG_BIT(13) 672 #define BXT_PORT_PLL_EBB_4(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 673 _PORT_PLL_EBB_4_B, \ 674 _PORT_PLL_EBB_4_C) 675 676 #define _PORT_PLL_0_A 0x162100 677 #define _PORT_PLL_0_B 0x6C100 678 #define _PORT_PLL_0_C 0x6C380 679 /* PORT_PLL_0_A */ 680 #define PORT_PLL_M2_INT_MASK REG_GENMASK(7, 0) 681 #define PORT_PLL_M2_INT(m2_int) REG_FIELD_PREP(PORT_PLL_M2_INT_MASK, (m2_int)) 682 /* PORT_PLL_1_A */ 683 #define PORT_PLL_N_MASK REG_GENMASK(11, 8) 684 #define PORT_PLL_N(n) REG_FIELD_PREP(PORT_PLL_N_MASK, (n)) 685 /* PORT_PLL_2_A */ 686 #define PORT_PLL_M2_FRAC_MASK REG_GENMASK(21, 0) 687 #define PORT_PLL_M2_FRAC(m2_frac) REG_FIELD_PREP(PORT_PLL_M2_FRAC_MASK, (m2_frac)) 688 /* PORT_PLL_3_A */ 689 #define PORT_PLL_M2_FRAC_ENABLE REG_BIT(16) 690 /* PORT_PLL_6_A */ 691 #define PORT_PLL_GAIN_CTL_MASK REG_GENMASK(18, 16) 692 #define PORT_PLL_GAIN_CTL(x) REG_FIELD_PREP(PORT_PLL_GAIN_CTL_MASK, (x)) 693 #define PORT_PLL_INT_COEFF_MASK REG_GENMASK(12, 8) 694 #define PORT_PLL_INT_COEFF(x) REG_FIELD_PREP(PORT_PLL_INT_COEFF_MASK, (x)) 695 #define PORT_PLL_PROP_COEFF_MASK REG_GENMASK(3, 0) 696 #define PORT_PLL_PROP_COEFF(x) REG_FIELD_PREP(PORT_PLL_PROP_COEFF_MASK, (x)) 697 /* PORT_PLL_8_A */ 698 #define PORT_PLL_TARGET_CNT_MASK REG_GENMASK(9, 0) 699 #define PORT_PLL_TARGET_CNT(x) REG_FIELD_PREP(PORT_PLL_TARGET_CNT_MASK, (x)) 700 /* PORT_PLL_9_A */ 701 #define PORT_PLL_LOCK_THRESHOLD_MASK REG_GENMASK(3, 1) 702 #define PORT_PLL_LOCK_THRESHOLD(x) REG_FIELD_PREP(PORT_PLL_LOCK_THRESHOLD_MASK, (x)) 703 /* PORT_PLL_10_A */ 704 #define PORT_PLL_DCO_AMP_OVR_EN_H REG_BIT(27) 705 #define PORT_PLL_DCO_AMP_MASK REG_GENMASK(13, 10) 706 #define PORT_PLL_DCO_AMP(x) REG_FIELD_PREP(PORT_PLL_DCO_AMP_MASK, (x)) 707 #define _PORT_PLL_BASE(phy, ch) _BXT_PHY_CH(phy, ch, \ 708 _PORT_PLL_0_B, \ 709 _PORT_PLL_0_C) 710 #define BXT_PORT_PLL(phy, ch, idx) _MMIO(_PORT_PLL_BASE(phy, ch) + \ 711 (idx) * 4) 712 713 /* BXT PHY common lane registers */ 714 #define _PORT_CL1CM_DW0_A 0x162000 715 #define _PORT_CL1CM_DW0_BC 0x6C000 716 #define PHY_POWER_GOOD (1 << 16) 717 #define PHY_RESERVED (1 << 7) 718 #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC) 719 720 #define _PORT_CL1CM_DW9_A 0x162024 721 #define _PORT_CL1CM_DW9_BC 0x6C024 722 #define IREF0RC_OFFSET_SHIFT 8 723 #define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT) 724 #define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC) 725 726 #define _PORT_CL1CM_DW10_A 0x162028 727 #define _PORT_CL1CM_DW10_BC 0x6C028 728 #define IREF1RC_OFFSET_SHIFT 8 729 #define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT) 730 #define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC) 731 732 #define _PORT_CL1CM_DW28_A 0x162070 733 #define _PORT_CL1CM_DW28_BC 0x6C070 734 #define OCL1_POWER_DOWN_EN (1 << 23) 735 #define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22) 736 #define SUS_CLK_CONFIG 0x3 737 #define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC) 738 739 #define _PORT_CL1CM_DW30_A 0x162078 740 #define _PORT_CL1CM_DW30_BC 0x6C078 741 #define OCL2_LDOFUSE_PWR_DIS (1 << 6) 742 #define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC) 743 744 /* The spec defines this only for BXT PHY0, but lets assume that this 745 * would exist for PHY1 too if it had a second channel. 746 */ 747 #define _PORT_CL2CM_DW6_A 0x162358 748 #define _PORT_CL2CM_DW6_BC 0x6C358 749 #define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC) 750 #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28) 751 752 /* BXT PHY Ref registers */ 753 #define _PORT_REF_DW3_A 0x16218C 754 #define _PORT_REF_DW3_BC 0x6C18C 755 #define GRC_DONE (1 << 22) 756 #define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC) 757 758 #define _PORT_REF_DW6_A 0x162198 759 #define _PORT_REF_DW6_BC 0x6C198 760 #define GRC_CODE_SHIFT 24 761 #define GRC_CODE_MASK (0xFF << GRC_CODE_SHIFT) 762 #define GRC_CODE_FAST_SHIFT 16 763 #define GRC_CODE_FAST_MASK (0xFF << GRC_CODE_FAST_SHIFT) 764 #define GRC_CODE_SLOW_SHIFT 8 765 #define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT) 766 #define GRC_CODE_NOM_MASK 0xFF 767 #define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC) 768 769 #define _PORT_REF_DW8_A 0x1621A0 770 #define _PORT_REF_DW8_BC 0x6C1A0 771 #define GRC_DIS (1 << 15) 772 #define GRC_RDY_OVRD (1 << 1) 773 #define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC) 774 775 /* BXT PHY PCS registers */ 776 #define _PORT_PCS_DW10_LN01_A 0x162428 777 #define _PORT_PCS_DW10_LN01_B 0x6C428 778 #define _PORT_PCS_DW10_LN01_C 0x6C828 779 #define _PORT_PCS_DW10_GRP_A 0x162C28 780 #define _PORT_PCS_DW10_GRP_B 0x6CC28 781 #define _PORT_PCS_DW10_GRP_C 0x6CE28 782 #define BXT_PORT_PCS_DW10_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 783 _PORT_PCS_DW10_LN01_B, \ 784 _PORT_PCS_DW10_LN01_C) 785 #define BXT_PORT_PCS_DW10_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 786 _PORT_PCS_DW10_GRP_B, \ 787 _PORT_PCS_DW10_GRP_C) 788 789 #define TX2_SWING_CALC_INIT (1 << 31) 790 #define TX1_SWING_CALC_INIT (1 << 30) 791 792 #define _PORT_PCS_DW12_LN01_A 0x162430 793 #define _PORT_PCS_DW12_LN01_B 0x6C430 794 #define _PORT_PCS_DW12_LN01_C 0x6C830 795 #define _PORT_PCS_DW12_LN23_A 0x162630 796 #define _PORT_PCS_DW12_LN23_B 0x6C630 797 #define _PORT_PCS_DW12_LN23_C 0x6CA30 798 #define _PORT_PCS_DW12_GRP_A 0x162c30 799 #define _PORT_PCS_DW12_GRP_B 0x6CC30 800 #define _PORT_PCS_DW12_GRP_C 0x6CE30 801 #define LANESTAGGER_STRAP_OVRD (1 << 6) 802 #define LANE_STAGGER_MASK 0x1F 803 #define BXT_PORT_PCS_DW12_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 804 _PORT_PCS_DW12_LN01_B, \ 805 _PORT_PCS_DW12_LN01_C) 806 #define BXT_PORT_PCS_DW12_LN23(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 807 _PORT_PCS_DW12_LN23_B, \ 808 _PORT_PCS_DW12_LN23_C) 809 #define BXT_PORT_PCS_DW12_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 810 _PORT_PCS_DW12_GRP_B, \ 811 _PORT_PCS_DW12_GRP_C) 812 813 /* BXT PHY TX registers */ 814 #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \ 815 ((lane) & 1) * 0x80) 816 817 #define _PORT_TX_DW2_LN0_A 0x162508 818 #define _PORT_TX_DW2_LN0_B 0x6C508 819 #define _PORT_TX_DW2_LN0_C 0x6C908 820 #define _PORT_TX_DW2_GRP_A 0x162D08 821 #define _PORT_TX_DW2_GRP_B 0x6CD08 822 #define _PORT_TX_DW2_GRP_C 0x6CF08 823 #define BXT_PORT_TX_DW2_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 824 _PORT_TX_DW2_LN0_B, \ 825 _PORT_TX_DW2_LN0_C) 826 #define BXT_PORT_TX_DW2_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 827 _PORT_TX_DW2_GRP_B, \ 828 _PORT_TX_DW2_GRP_C) 829 #define MARGIN_000_SHIFT 16 830 #define MARGIN_000 (0xFF << MARGIN_000_SHIFT) 831 #define UNIQ_TRANS_SCALE_SHIFT 8 832 #define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT) 833 834 #define _PORT_TX_DW3_LN0_A 0x16250C 835 #define _PORT_TX_DW3_LN0_B 0x6C50C 836 #define _PORT_TX_DW3_LN0_C 0x6C90C 837 #define _PORT_TX_DW3_GRP_A 0x162D0C 838 #define _PORT_TX_DW3_GRP_B 0x6CD0C 839 #define _PORT_TX_DW3_GRP_C 0x6CF0C 840 #define BXT_PORT_TX_DW3_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 841 _PORT_TX_DW3_LN0_B, \ 842 _PORT_TX_DW3_LN0_C) 843 #define BXT_PORT_TX_DW3_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 844 _PORT_TX_DW3_GRP_B, \ 845 _PORT_TX_DW3_GRP_C) 846 #define SCALE_DCOMP_METHOD (1 << 26) 847 #define UNIQUE_TRANGE_EN_METHOD (1 << 27) 848 849 #define _PORT_TX_DW4_LN0_A 0x162510 850 #define _PORT_TX_DW4_LN0_B 0x6C510 851 #define _PORT_TX_DW4_LN0_C 0x6C910 852 #define _PORT_TX_DW4_GRP_A 0x162D10 853 #define _PORT_TX_DW4_GRP_B 0x6CD10 854 #define _PORT_TX_DW4_GRP_C 0x6CF10 855 #define BXT_PORT_TX_DW4_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 856 _PORT_TX_DW4_LN0_B, \ 857 _PORT_TX_DW4_LN0_C) 858 #define BXT_PORT_TX_DW4_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 859 _PORT_TX_DW4_GRP_B, \ 860 _PORT_TX_DW4_GRP_C) 861 #define DEEMPH_SHIFT 24 862 #define DE_EMPHASIS (0xFF << DEEMPH_SHIFT) 863 864 #define _PORT_TX_DW5_LN0_A 0x162514 865 #define _PORT_TX_DW5_LN0_B 0x6C514 866 #define _PORT_TX_DW5_LN0_C 0x6C914 867 #define _PORT_TX_DW5_GRP_A 0x162D14 868 #define _PORT_TX_DW5_GRP_B 0x6CD14 869 #define _PORT_TX_DW5_GRP_C 0x6CF14 870 #define BXT_PORT_TX_DW5_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 871 _PORT_TX_DW5_LN0_B, \ 872 _PORT_TX_DW5_LN0_C) 873 #define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 874 _PORT_TX_DW5_GRP_B, \ 875 _PORT_TX_DW5_GRP_C) 876 #define DCC_DELAY_RANGE_1 (1 << 9) 877 #define DCC_DELAY_RANGE_2 (1 << 8) 878 879 #define _PORT_TX_DW14_LN0_A 0x162538 880 #define _PORT_TX_DW14_LN0_B 0x6C538 881 #define _PORT_TX_DW14_LN0_C 0x6C938 882 #define LATENCY_OPTIM_SHIFT 30 883 #define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT) 884 #define BXT_PORT_TX_DW14_LN(phy, ch, lane) \ 885 _MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B, \ 886 _PORT_TX_DW14_LN0_C) + \ 887 _BXT_LANE_OFFSET(lane)) 888 889 /* UAIMI scratch pad register 1 */ 890 #define UAIMI_SPR1 _MMIO(0x4F074) 891 /* SKL VccIO mask */ 892 #define SKL_VCCIO_MASK 0x1 893 /* SKL balance leg register */ 894 #define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C) 895 /* I_boost values */ 896 #define BALANCE_LEG_SHIFT(port) (8 + 3 * (port)) 897 #define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port))) 898 /* Balance leg disable bits */ 899 #define BALANCE_LEG_DISABLE_SHIFT 23 900 #define BALANCE_LEG_DISABLE(port) (1 << (23 + (port))) 901 902 /* 903 * Fence registers 904 * [0-7] @ 0x2000 gen2,gen3 905 * [8-15] @ 0x3000 945,g33,pnv 906 * 907 * [0-15] @ 0x3000 gen4,gen5 908 * 909 * [0-15] @ 0x100000 gen6,vlv,chv 910 * [0-31] @ 0x100000 gen7+ 911 */ 912 #define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4) 913 #define I830_FENCE_START_MASK 0x07f80000 914 #define I830_FENCE_TILING_Y_SHIFT 12 915 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) 916 #define I830_FENCE_PITCH_SHIFT 4 917 #define I830_FENCE_REG_VALID (1 << 0) 918 #define I915_FENCE_MAX_PITCH_VAL 4 919 #define I830_FENCE_MAX_PITCH_VAL 6 920 #define I830_FENCE_MAX_SIZE_VAL (1 << 8) 921 922 #define I915_FENCE_START_MASK 0x0ff00000 923 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) 924 925 #define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8) 926 #define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4) 927 #define I965_FENCE_PITCH_SHIFT 2 928 #define I965_FENCE_TILING_Y_SHIFT 1 929 #define I965_FENCE_REG_VALID (1 << 0) 930 #define I965_FENCE_MAX_PITCH_VAL 0x0400 931 932 #define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8) 933 #define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4) 934 #define GEN6_FENCE_PITCH_SHIFT 32 935 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800 936 937 938 /* control register for cpu gtt access */ 939 #define TILECTL _MMIO(0x101000) 940 #define TILECTL_SWZCTL (1 << 0) 941 #define TILECTL_TLBPF (1 << 1) 942 #define TILECTL_TLB_PREFETCH_DIS (1 << 2) 943 #define TILECTL_BACKSNOOP_DIS (1 << 3) 944 945 /* 946 * Instruction and interrupt control regs 947 */ 948 #define PGTBL_CTL _MMIO(0x02020) 949 #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */ 950 #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */ 951 #define PGTBL_ER _MMIO(0x02024) 952 #define PRB0_BASE (0x2030 - 0x30) 953 #define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */ 954 #define PRB2_BASE (0x2050 - 0x30) /* gen3 */ 955 #define SRB0_BASE (0x2100 - 0x30) /* gen2 */ 956 #define SRB1_BASE (0x2110 - 0x30) /* gen2 */ 957 #define SRB2_BASE (0x2120 - 0x30) /* 830 */ 958 #define SRB3_BASE (0x2130 - 0x30) /* 830 */ 959 #define RENDER_RING_BASE 0x02000 960 #define BSD_RING_BASE 0x04000 961 #define GEN6_BSD_RING_BASE 0x12000 962 #define GEN8_BSD2_RING_BASE 0x1c000 963 #define GEN11_BSD_RING_BASE 0x1c0000 964 #define GEN11_BSD2_RING_BASE 0x1c4000 965 #define GEN11_BSD3_RING_BASE 0x1d0000 966 #define GEN11_BSD4_RING_BASE 0x1d4000 967 #define XEHP_BSD5_RING_BASE 0x1e0000 968 #define XEHP_BSD6_RING_BASE 0x1e4000 969 #define XEHP_BSD7_RING_BASE 0x1f0000 970 #define XEHP_BSD8_RING_BASE 0x1f4000 971 #define VEBOX_RING_BASE 0x1a000 972 #define GEN11_VEBOX_RING_BASE 0x1c8000 973 #define GEN11_VEBOX2_RING_BASE 0x1d8000 974 #define XEHP_VEBOX3_RING_BASE 0x1e8000 975 #define XEHP_VEBOX4_RING_BASE 0x1f8000 976 #define MTL_GSC_RING_BASE 0x11a000 977 #define GEN12_COMPUTE0_RING_BASE 0x1a000 978 #define GEN12_COMPUTE1_RING_BASE 0x1c000 979 #define GEN12_COMPUTE2_RING_BASE 0x1e000 980 #define GEN12_COMPUTE3_RING_BASE 0x26000 981 #define BLT_RING_BASE 0x22000 982 #define XEHPC_BCS1_RING_BASE 0x3e0000 983 #define XEHPC_BCS2_RING_BASE 0x3e2000 984 #define XEHPC_BCS3_RING_BASE 0x3e4000 985 #define XEHPC_BCS4_RING_BASE 0x3e6000 986 #define XEHPC_BCS5_RING_BASE 0x3e8000 987 #define XEHPC_BCS6_RING_BASE 0x3ea000 988 #define XEHPC_BCS7_RING_BASE 0x3ec000 989 #define XEHPC_BCS8_RING_BASE 0x3ee000 990 #define DG1_GSC_HECI1_BASE 0x00258000 991 #define DG1_GSC_HECI2_BASE 0x00259000 992 #define DG2_GSC_HECI1_BASE 0x00373000 993 #define DG2_GSC_HECI2_BASE 0x00374000 994 995 996 997 #define HSW_GTT_CACHE_EN _MMIO(0x4024) 998 #define GTT_CACHE_EN_ALL 0xF0007FFF 999 #define GEN7_WR_WATERMARK _MMIO(0x4028) 1000 #define GEN7_GFX_PRIO_CTRL _MMIO(0x402C) 1001 #define ARB_MODE _MMIO(0x4030) 1002 #define ARB_MODE_SWIZZLE_SNB (1 << 4) 1003 #define ARB_MODE_SWIZZLE_IVB (1 << 5) 1004 #define GEN7_GFX_PEND_TLB0 _MMIO(0x4034) 1005 #define GEN7_GFX_PEND_TLB1 _MMIO(0x4038) 1006 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */ 1007 #define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4) 1008 #define GEN7_LRA_LIMITS_REG_NUM 13 1009 #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070) 1010 #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074) 1011 1012 #define GEN7_ERR_INT _MMIO(0x44040) 1013 #define ERR_INT_POISON (1 << 31) 1014 #define ERR_INT_MMIO_UNCLAIMED (1 << 13) 1015 #define ERR_INT_PIPE_CRC_DONE_C (1 << 8) 1016 #define ERR_INT_FIFO_UNDERRUN_C (1 << 6) 1017 #define ERR_INT_PIPE_CRC_DONE_B (1 << 5) 1018 #define ERR_INT_FIFO_UNDERRUN_B (1 << 3) 1019 #define ERR_INT_PIPE_CRC_DONE_A (1 << 2) 1020 #define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3)) 1021 #define ERR_INT_FIFO_UNDERRUN_A (1 << 0) 1022 #define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) 1023 1024 #define FPGA_DBG _MMIO(0x42300) 1025 #define FPGA_DBG_RM_NOCLAIM REG_BIT(31) 1026 1027 #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028) 1028 #define CLAIM_ER_CLR REG_BIT(31) 1029 #define CLAIM_ER_OVERFLOW REG_BIT(16) 1030 #define CLAIM_ER_CTR_MASK REG_GENMASK(15, 0) 1031 1032 #define DERRMR _MMIO(0x44050) 1033 /* Note that HBLANK events are reserved on bdw+ */ 1034 #define DERRMR_PIPEA_SCANLINE (1 << 0) 1035 #define DERRMR_PIPEA_PRI_FLIP_DONE (1 << 1) 1036 #define DERRMR_PIPEA_SPR_FLIP_DONE (1 << 2) 1037 #define DERRMR_PIPEA_VBLANK (1 << 3) 1038 #define DERRMR_PIPEA_HBLANK (1 << 5) 1039 #define DERRMR_PIPEB_SCANLINE (1 << 8) 1040 #define DERRMR_PIPEB_PRI_FLIP_DONE (1 << 9) 1041 #define DERRMR_PIPEB_SPR_FLIP_DONE (1 << 10) 1042 #define DERRMR_PIPEB_VBLANK (1 << 11) 1043 #define DERRMR_PIPEB_HBLANK (1 << 13) 1044 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */ 1045 #define DERRMR_PIPEC_SCANLINE (1 << 14) 1046 #define DERRMR_PIPEC_PRI_FLIP_DONE (1 << 15) 1047 #define DERRMR_PIPEC_SPR_FLIP_DONE (1 << 20) 1048 #define DERRMR_PIPEC_VBLANK (1 << 21) 1049 #define DERRMR_PIPEC_HBLANK (1 << 22) 1050 1051 #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030) 1052 #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034) 1053 #define SCPD0 _MMIO(0x209c) /* 915+ only */ 1054 #define SCPD_FBC_IGNORE_3D (1 << 6) 1055 #define CSTATE_RENDER_CLOCK_GATE_DISABLE (1 << 5) 1056 #define GEN2_IER _MMIO(0x20a0) 1057 #define GEN2_IIR _MMIO(0x20a4) 1058 #define GEN2_IMR _MMIO(0x20a8) 1059 #define GEN2_ISR _MMIO(0x20ac) 1060 #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060) 1061 #define GINT_DIS (1 << 22) 1062 #define GCFG_DIS (1 << 8) 1063 #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064) 1064 #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084) 1065 #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0) 1066 #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4) 1067 #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8) 1068 #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac) 1069 #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120) 1070 #define VLV_PCBR_ADDR_SHIFT 12 1071 1072 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */ 1073 #define EIR _MMIO(0x20b0) 1074 #define EMR _MMIO(0x20b4) 1075 #define ESR _MMIO(0x20b8) 1076 #define GM45_ERROR_PAGE_TABLE (1 << 5) 1077 #define GM45_ERROR_MEM_PRIV (1 << 4) 1078 #define I915_ERROR_PAGE_TABLE (1 << 4) 1079 #define GM45_ERROR_CP_PRIV (1 << 3) 1080 #define I915_ERROR_MEMORY_REFRESH (1 << 1) 1081 #define I915_ERROR_INSTRUCTION (1 << 0) 1082 #define INSTPM _MMIO(0x20c0) 1083 #define INSTPM_SELF_EN (1 << 12) /* 915GM only */ 1084 #define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts 1085 will not assert AGPBUSY# and will only 1086 be delivered when out of C3. */ 1087 #define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */ 1088 #define INSTPM_TLB_INVALIDATE (1 << 9) 1089 #define INSTPM_SYNC_FLUSH (1 << 5) 1090 #define MEM_MODE _MMIO(0x20cc) 1091 #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */ 1092 #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */ 1093 #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */ 1094 #define FW_BLC _MMIO(0x20d8) 1095 #define FW_BLC2 _MMIO(0x20dc) 1096 #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */ 1097 #define FW_BLC_SELF_EN_MASK (1 << 31) 1098 #define FW_BLC_SELF_FIFO_MASK (1 << 16) /* 945 only */ 1099 #define FW_BLC_SELF_EN (1 << 15) /* 945 only */ 1100 #define MM_BURST_LENGTH 0x00700000 1101 #define MM_FIFO_WATERMARK 0x0001F000 1102 #define LM_BURST_LENGTH 0x00000700 1103 #define LM_FIFO_WATERMARK 0x0000001F 1104 #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */ 1105 1106 #define _MBUS_ABOX0_CTL 0x45038 1107 #define _MBUS_ABOX1_CTL 0x45048 1108 #define _MBUS_ABOX2_CTL 0x4504C 1109 #define MBUS_ABOX_CTL(x) _MMIO(_PICK(x, _MBUS_ABOX0_CTL, \ 1110 _MBUS_ABOX1_CTL, \ 1111 _MBUS_ABOX2_CTL)) 1112 #define MBUS_ABOX_BW_CREDIT_MASK (3 << 20) 1113 #define MBUS_ABOX_BW_CREDIT(x) ((x) << 20) 1114 #define MBUS_ABOX_B_CREDIT_MASK (0xF << 16) 1115 #define MBUS_ABOX_B_CREDIT(x) ((x) << 16) 1116 #define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8) 1117 #define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8) 1118 #define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0) 1119 #define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0) 1120 1121 #define _PIPEA_MBUS_DBOX_CTL 0x7003C 1122 #define _PIPEB_MBUS_DBOX_CTL 0x7103C 1123 #define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \ 1124 _PIPEB_MBUS_DBOX_CTL) 1125 #define MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK REG_GENMASK(24, 20) /* tgl+ */ 1126 #define MBUS_DBOX_B2B_TRANSACTIONS_MAX(x) REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK, x) 1127 #define MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK REG_GENMASK(19, 17) /* tgl+ */ 1128 #define MBUS_DBOX_B2B_TRANSACTIONS_DELAY(x) REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK, x) 1129 #define MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN REG_BIT(16) /* tgl+ */ 1130 #define MBUS_DBOX_BW_CREDIT_MASK REG_GENMASK(15, 14) 1131 #define MBUS_DBOX_BW_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, x) 1132 #define MBUS_DBOX_BW_4CREDITS_MTL REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, 0x2) 1133 #define MBUS_DBOX_BW_8CREDITS_MTL REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, 0x3) 1134 #define MBUS_DBOX_B_CREDIT_MASK REG_GENMASK(12, 8) 1135 #define MBUS_DBOX_B_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_B_CREDIT_MASK, x) 1136 #define MBUS_DBOX_I_CREDIT_MASK REG_GENMASK(7, 5) 1137 #define MBUS_DBOX_I_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_I_CREDIT_MASK, x) 1138 #define MBUS_DBOX_A_CREDIT_MASK REG_GENMASK(3, 0) 1139 #define MBUS_DBOX_A_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_A_CREDIT_MASK, x) 1140 1141 #define MBUS_UBOX_CTL _MMIO(0x4503C) 1142 #define MBUS_BBOX_CTL_S1 _MMIO(0x45040) 1143 #define MBUS_BBOX_CTL_S2 _MMIO(0x45044) 1144 1145 #define MBUS_CTL _MMIO(0x4438C) 1146 #define MBUS_JOIN REG_BIT(31) 1147 #define MBUS_HASHING_MODE_MASK REG_BIT(30) 1148 #define MBUS_HASHING_MODE_2x2 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 0) 1149 #define MBUS_HASHING_MODE_1x4 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 1) 1150 #define MBUS_JOIN_PIPE_SELECT_MASK REG_GENMASK(28, 26) 1151 #define MBUS_JOIN_PIPE_SELECT(pipe) REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe) 1152 #define MBUS_JOIN_PIPE_SELECT_NONE MBUS_JOIN_PIPE_SELECT(7) 1153 1154 #define HDPORT_STATE _MMIO(0x45050) 1155 #define HDPORT_DPLL_USED_MASK REG_GENMASK(15, 12) 1156 #define HDPORT_DDI_USED(phy) REG_BIT(2 * (phy) + 1) 1157 #define HDPORT_ENABLED REG_BIT(0) 1158 1159 /* Make render/texture TLB fetches lower priorty than associated data 1160 * fetches. This is not turned on by default 1161 */ 1162 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) 1163 1164 /* Isoch request wait on GTT enable (Display A/B/C streams). 1165 * Make isoch requests stall on the TLB update. May cause 1166 * display underruns (test mode only) 1167 */ 1168 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14) 1169 1170 /* Block grant count for isoch requests when block count is 1171 * set to a finite value. 1172 */ 1173 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12) 1174 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ 1175 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ 1176 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ 1177 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ 1178 1179 /* Enable render writes to complete in C2/C3/C4 power states. 1180 * If this isn't enabled, render writes are prevented in low 1181 * power states. That seems bad to me. 1182 */ 1183 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) 1184 1185 /* This acknowledges an async flip immediately instead 1186 * of waiting for 2TLB fetches. 1187 */ 1188 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) 1189 1190 /* Enables non-sequential data reads through arbiter 1191 */ 1192 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) 1193 1194 /* Disable FSB snooping of cacheable write cycles from binner/render 1195 * command stream 1196 */ 1197 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) 1198 1199 /* Arbiter time slice for non-isoch streams */ 1200 #define MI_ARB_TIME_SLICE_MASK (7 << 5) 1201 #define MI_ARB_TIME_SLICE_1 (0 << 5) 1202 #define MI_ARB_TIME_SLICE_2 (1 << 5) 1203 #define MI_ARB_TIME_SLICE_4 (2 << 5) 1204 #define MI_ARB_TIME_SLICE_6 (3 << 5) 1205 #define MI_ARB_TIME_SLICE_8 (4 << 5) 1206 #define MI_ARB_TIME_SLICE_10 (5 << 5) 1207 #define MI_ARB_TIME_SLICE_14 (6 << 5) 1208 #define MI_ARB_TIME_SLICE_16 (7 << 5) 1209 1210 /* Low priority grace period page size */ 1211 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ 1212 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) 1213 1214 /* Disable display A/B trickle feed */ 1215 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) 1216 1217 /* Set display plane priority */ 1218 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ 1219 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ 1220 1221 #define MI_STATE _MMIO(0x20e4) /* gen2 only */ 1222 #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */ 1223 #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */ 1224 1225 /* On modern GEN architectures interrupt control consists of two sets 1226 * of registers. The first set pertains to the ring generating the 1227 * interrupt. The second control is for the functional block generating the 1228 * interrupt. These are PM, GT, DE, etc. 1229 * 1230 * Luckily *knocks on wood* all the ring interrupt bits match up with the 1231 * GT interrupt bits, so we don't need to duplicate the defines. 1232 * 1233 * These defines should cover us well from SNB->HSW with minor exceptions 1234 * it can also work on ILK. 1235 */ 1236 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) 1237 #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25) 1238 #define GT_BLT_USER_INTERRUPT (1 << 22) 1239 #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15) 1240 #define GT_BSD_USER_INTERRUPT (1 << 12) 1241 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */ 1242 #define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) /* bdw+ */ 1243 #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8) 1244 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */ 1245 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4) 1246 #define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3) 1247 #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2) 1248 #define GT_RENDER_DEBUG_INTERRUPT (1 << 1) 1249 #define GT_RENDER_USER_INTERRUPT (1 << 0) 1250 1251 #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */ 1252 #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */ 1253 1254 #define GT_PARITY_ERROR(dev_priv) \ 1255 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \ 1256 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0)) 1257 1258 /* These are all the "old" interrupts */ 1259 #define ILK_BSD_USER_INTERRUPT (1 << 5) 1260 1261 #define I915_PM_INTERRUPT (1 << 31) 1262 #define I915_ISP_INTERRUPT (1 << 22) 1263 #define I915_LPE_PIPE_B_INTERRUPT (1 << 21) 1264 #define I915_LPE_PIPE_A_INTERRUPT (1 << 20) 1265 #define I915_MIPIC_INTERRUPT (1 << 19) 1266 #define I915_MIPIA_INTERRUPT (1 << 18) 1267 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18) 1268 #define I915_DISPLAY_PORT_INTERRUPT (1 << 17) 1269 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16) 1270 #define I915_MASTER_ERROR_INTERRUPT (1 << 15) 1271 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14) 1272 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */ 1273 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13) 1274 #define I915_HWB_OOM_INTERRUPT (1 << 13) 1275 #define I915_LPE_PIPE_C_INTERRUPT (1 << 12) 1276 #define I915_SYNC_STATUS_INTERRUPT (1 << 12) 1277 #define I915_MISC_INTERRUPT (1 << 11) 1278 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11) 1279 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10) 1280 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10) 1281 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9) 1282 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9) 1283 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8) 1284 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8) 1285 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7) 1286 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6) 1287 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5) 1288 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4) 1289 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3) 1290 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2) 1291 #define I915_DEBUG_INTERRUPT (1 << 2) 1292 #define I915_WINVALID_INTERRUPT (1 << 1) 1293 #define I915_USER_INTERRUPT (1 << 1) 1294 #define I915_ASLE_INTERRUPT (1 << 0) 1295 #define I915_BSD_USER_INTERRUPT (1 << 25) 1296 1297 #define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000) 1298 #define I915_HDMI_LPE_AUDIO_SIZE 0x1000 1299 1300 /* DisplayPort Audio w/ LPE */ 1301 #define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38) 1302 #define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0) 1303 1304 #define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62F20) 1305 #define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62F30) 1306 #define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62F34) 1307 #define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \ 1308 _VLV_AUD_PORT_EN_B_DBG, \ 1309 _VLV_AUD_PORT_EN_C_DBG, \ 1310 _VLV_AUD_PORT_EN_D_DBG) 1311 #define VLV_AMP_MUTE (1 << 1) 1312 1313 #define GEN6_BSD_RNCID _MMIO(0x12198) 1314 1315 #define GEN7_FF_THREAD_MODE _MMIO(0x20a0) 1316 #define GEN7_FF_SCHED_MASK 0x0077070 1317 #define GEN8_FF_DS_REF_CNT_FFME (1 << 19) 1318 #define GEN12_FF_TESSELATION_DOP_GATE_DISABLE BIT(19) 1319 #define GEN7_FF_TS_SCHED_HS1 (0x5 << 16) 1320 #define GEN7_FF_TS_SCHED_HS0 (0x3 << 16) 1321 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16) 1322 #define GEN7_FF_TS_SCHED_HW (0x0 << 16) /* Default */ 1323 #define GEN7_FF_VS_REF_CNT_FFME (1 << 15) 1324 #define GEN7_FF_VS_SCHED_HS1 (0x5 << 12) 1325 #define GEN7_FF_VS_SCHED_HS0 (0x3 << 12) 1326 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12) /* Default */ 1327 #define GEN7_FF_VS_SCHED_HW (0x0 << 12) 1328 #define GEN7_FF_DS_SCHED_HS1 (0x5 << 4) 1329 #define GEN7_FF_DS_SCHED_HS0 (0x3 << 4) 1330 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */ 1331 #define GEN7_FF_DS_SCHED_HW (0x0 << 4) 1332 1333 /* 1334 * Framebuffer compression (915+ only) 1335 */ 1336 1337 #define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */ 1338 #define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */ 1339 #define FBC_CONTROL _MMIO(0x3208) 1340 #define FBC_CTL_EN REG_BIT(31) 1341 #define FBC_CTL_PERIODIC REG_BIT(30) 1342 #define FBC_CTL_INTERVAL_MASK REG_GENMASK(29, 16) 1343 #define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x)) 1344 #define FBC_CTL_STOP_ON_MOD REG_BIT(15) 1345 #define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */ 1346 #define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm only */ 1347 #define FBC_CTL_STRIDE_MASK REG_GENMASK(12, 5) 1348 #define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x)) 1349 #define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0) 1350 #define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x)) 1351 #define FBC_COMMAND _MMIO(0x320c) 1352 #define FBC_CMD_COMPRESS REG_BIT(0) 1353 #define FBC_STATUS _MMIO(0x3210) 1354 #define FBC_STAT_COMPRESSING REG_BIT(31) 1355 #define FBC_STAT_COMPRESSED REG_BIT(30) 1356 #define FBC_STAT_MODIFIED REG_BIT(29) 1357 #define FBC_STAT_CURRENT_LINE_MASK REG_GENMASK(10, 0) 1358 #define FBC_CONTROL2 _MMIO(0x3214) /* i965gm only */ 1359 #define FBC_CTL_FENCE_DBL REG_BIT(4) 1360 #define FBC_CTL_IDLE_MASK REG_GENMASK(3, 2) 1361 #define FBC_CTL_IDLE_IMM REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 0) 1362 #define FBC_CTL_IDLE_FULL REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 1) 1363 #define FBC_CTL_IDLE_LINE REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 2) 1364 #define FBC_CTL_IDLE_DEBUG REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 3) 1365 #define FBC_CTL_CPU_FENCE_EN REG_BIT(1) 1366 #define FBC_CTL_PLANE_MASK REG_GENMASK(1, 0) 1367 #define FBC_CTL_PLANE(i9xx_plane) REG_FIELD_PREP(FBC_CTL_PLANE_MASK, (i9xx_plane)) 1368 #define FBC_FENCE_OFF _MMIO(0x3218) /* i965gm only, BSpec typo has 321Bh */ 1369 #define FBC_MOD_NUM _MMIO(0x3220) /* i965gm only */ 1370 #define FBC_MOD_NUM_MASK REG_GENMASK(31, 1) 1371 #define FBC_MOD_NUM_VALID REG_BIT(0) 1372 #define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) /* 49 reisters */ 1373 #define FBC_TAG_MASK REG_GENMASK(1, 0) /* 16 tags per register */ 1374 #define FBC_TAG_MODIFIED REG_FIELD_PREP(FBC_TAG_MASK, 0) 1375 #define FBC_TAG_UNCOMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 1) 1376 #define FBC_TAG_UNCOMPRESSIBLE REG_FIELD_PREP(FBC_TAG_MASK, 2) 1377 #define FBC_TAG_COMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 3) 1378 1379 #define FBC_LL_SIZE (1536) 1380 1381 /* Framebuffer compression for GM45+ */ 1382 #define DPFC_CB_BASE _MMIO(0x3200) 1383 #define ILK_DPFC_CB_BASE(fbc_id) _MMIO_PIPE((fbc_id), 0x43200, 0x43240) 1384 #define DPFC_CONTROL _MMIO(0x3208) 1385 #define ILK_DPFC_CONTROL(fbc_id) _MMIO_PIPE((fbc_id), 0x43208, 0x43248) 1386 #define DPFC_CTL_EN REG_BIT(31) 1387 #define DPFC_CTL_PLANE_MASK_G4X REG_BIT(30) /* g4x-snb */ 1388 #define DPFC_CTL_PLANE_G4X(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane)) 1389 #define DPFC_CTL_FENCE_EN_G4X REG_BIT(29) /* g4x-snb */ 1390 #define DPFC_CTL_PLANE_MASK_IVB REG_GENMASK(30, 29) /* ivb only */ 1391 #define DPFC_CTL_PLANE_IVB(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_IVB, (i9xx_plane)) 1392 #define DPFC_CTL_FENCE_EN_IVB REG_BIT(28) /* ivb+ */ 1393 #define DPFC_CTL_PERSISTENT_MODE REG_BIT(25) /* g4x-snb */ 1394 #define DPFC_CTL_FALSE_COLOR REG_BIT(10) /* ivb+ */ 1395 #define DPFC_CTL_SR_EN REG_BIT(10) /* g4x only */ 1396 #define DPFC_CTL_SR_EXIT_DIS REG_BIT(9) /* g4x only */ 1397 #define DPFC_CTL_LIMIT_MASK REG_GENMASK(7, 6) 1398 #define DPFC_CTL_LIMIT_1X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 0) 1399 #define DPFC_CTL_LIMIT_2X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 1) 1400 #define DPFC_CTL_LIMIT_4X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 2) 1401 #define DPFC_CTL_FENCENO_MASK REG_GENMASK(3, 0) 1402 #define DPFC_CTL_FENCENO(fence) REG_FIELD_PREP(DPFC_CTL_FENCENO_MASK, (fence)) 1403 #define DPFC_RECOMP_CTL _MMIO(0x320c) 1404 #define ILK_DPFC_RECOMP_CTL(fbc_id) _MMIO_PIPE((fbc_id), 0x4320c, 0x4324c) 1405 #define DPFC_RECOMP_STALL_EN REG_BIT(27) 1406 #define DPFC_RECOMP_STALL_WM_MASK REG_GENMASK(26, 16) 1407 #define DPFC_RECOMP_TIMER_COUNT_MASK REG_GENMASK(5, 0) 1408 #define DPFC_STATUS _MMIO(0x3210) 1409 #define ILK_DPFC_STATUS(fbc_id) _MMIO_PIPE((fbc_id), 0x43210, 0x43250) 1410 #define DPFC_INVAL_SEG_MASK REG_GENMASK(26, 16) 1411 #define DPFC_COMP_SEG_MASK REG_GENMASK(10, 0) 1412 #define DPFC_STATUS2 _MMIO(0x3214) 1413 #define ILK_DPFC_STATUS2(fbc_id) _MMIO_PIPE((fbc_id), 0x43214, 0x43254) 1414 #define DPFC_COMP_SEG_MASK_IVB REG_GENMASK(11, 0) 1415 #define DPFC_FENCE_YOFF _MMIO(0x3218) 1416 #define ILK_DPFC_FENCE_YOFF(fbc_id) _MMIO_PIPE((fbc_id), 0x43218, 0x43258) 1417 #define DPFC_CHICKEN _MMIO(0x3224) 1418 #define ILK_DPFC_CHICKEN(fbc_id) _MMIO_PIPE((fbc_id), 0x43224, 0x43264) 1419 #define DPFC_HT_MODIFY REG_BIT(31) /* pre-ivb */ 1420 #define DPFC_NUKE_ON_ANY_MODIFICATION REG_BIT(23) /* bdw+ */ 1421 #define DPFC_CHICKEN_COMP_DUMMY_PIXEL REG_BIT(14) /* glk+ */ 1422 #define DPFC_CHICKEN_FORCE_SLB_INVALIDATION REG_BIT(13) /* icl+ */ 1423 #define DPFC_DISABLE_DUMMY0 REG_BIT(8) /* ivb+ */ 1424 1425 #define GLK_FBC_STRIDE(fbc_id) _MMIO_PIPE((fbc_id), 0x43228, 0x43268) 1426 #define FBC_STRIDE_OVERRIDE REG_BIT(15) 1427 #define FBC_STRIDE_MASK REG_GENMASK(14, 0) 1428 #define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x)) 1429 1430 #define ILK_FBC_RT_BASE _MMIO(0x2128) 1431 #define ILK_FBC_RT_VALID REG_BIT(0) 1432 #define SNB_FBC_FRONT_BUFFER REG_BIT(1) 1433 1434 #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000) 1435 #define ILK_FBCQ_DIS (1 << 22) 1436 #define ILK_PABSTRETCH_DIS REG_BIT(21) 1437 #define ILK_SABSTRETCH_DIS REG_BIT(20) 1438 #define IVB_PRI_STRETCH_MAX_MASK REG_GENMASK(21, 20) 1439 #define IVB_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0) 1440 #define IVB_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1) 1441 #define IVB_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 2) 1442 #define IVB_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 3) 1443 #define IVB_SPR_STRETCH_MAX_MASK REG_GENMASK(19, 18) 1444 #define IVB_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0) 1445 #define IVB_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 1) 1446 #define IVB_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2) 1447 #define IVB_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3) 1448 1449 1450 /* 1451 * Framebuffer compression for Sandybridge 1452 * 1453 * The following two registers are of type GTTMMADR 1454 */ 1455 #define SNB_DPFC_CTL_SA _MMIO(0x100100) 1456 #define SNB_DPFC_FENCE_EN REG_BIT(29) 1457 #define SNB_DPFC_FENCENO_MASK REG_GENMASK(4, 0) 1458 #define SNB_DPFC_FENCENO(fence) REG_FIELD_PREP(SNB_DPFC_FENCENO_MASK, (fence)) 1459 #define SNB_DPFC_CPU_FENCE_OFFSET _MMIO(0x100104) 1460 1461 /* Framebuffer compression for Ivybridge */ 1462 #define IVB_FBC_RT_BASE _MMIO(0x7020) 1463 #define IVB_FBC_RT_BASE_UPPER _MMIO(0x7024) 1464 1465 #define IPS_CTL _MMIO(0x43408) 1466 #define IPS_ENABLE (1 << 31) 1467 1468 #define MSG_FBC_REND_STATE(fbc_id) _MMIO_PIPE((fbc_id), 0x50380, 0x50384) 1469 #define FBC_REND_NUKE REG_BIT(2) 1470 #define FBC_REND_CACHE_CLEAN REG_BIT(1) 1471 1472 /* 1473 * Clock control & power management 1474 */ 1475 #define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014) 1476 #define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018) 1477 #define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030) 1478 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) 1479 1480 #define VGA0 _MMIO(0x6000) 1481 #define VGA1 _MMIO(0x6004) 1482 #define VGA_PD _MMIO(0x6010) 1483 #define VGA0_PD_P2_DIV_4 (1 << 7) 1484 #define VGA0_PD_P1_DIV_2 (1 << 5) 1485 #define VGA0_PD_P1_SHIFT 0 1486 #define VGA0_PD_P1_MASK (0x1f << 0) 1487 #define VGA1_PD_P2_DIV_4 (1 << 15) 1488 #define VGA1_PD_P1_DIV_2 (1 << 13) 1489 #define VGA1_PD_P1_SHIFT 8 1490 #define VGA1_PD_P1_MASK (0x1f << 8) 1491 #define DPLL_VCO_ENABLE (1 << 31) 1492 #define DPLL_SDVO_HIGH_SPEED (1 << 30) 1493 #define DPLL_DVO_2X_MODE (1 << 30) 1494 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) 1495 #define DPLL_SYNCLOCK_ENABLE (1 << 29) 1496 #define DPLL_REF_CLK_ENABLE_VLV (1 << 29) 1497 #define DPLL_VGA_MODE_DIS (1 << 28) 1498 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 1499 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 1500 #define DPLL_MODE_MASK (3 << 26) 1501 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 1502 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 1503 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 1504 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 1505 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 1506 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 1507 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ 1508 #define DPLL_LOCK_VLV (1 << 15) 1509 #define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14) 1510 #define DPLL_INTEGRATED_REF_CLK_VLV (1 << 13) 1511 #define DPLL_SSC_REF_CLK_CHV (1 << 13) 1512 #define DPLL_PORTC_READY_MASK (0xf << 4) 1513 #define DPLL_PORTB_READY_MASK (0xf) 1514 1515 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 1516 1517 /* Additional CHV pll/phy registers */ 1518 #define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240) 1519 #define DPLL_PORTD_READY_MASK (0xf) 1520 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100) 1521 #define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2 * (phy) + (ch) + 27)) 1522 #define PHY_LDO_DELAY_0NS 0x0 1523 #define PHY_LDO_DELAY_200NS 0x1 1524 #define PHY_LDO_DELAY_600NS 0x2 1525 #define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2 * (phy) + 23)) 1526 #define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11)) 1527 #define PHY_CH_SU_PSR 0x1 1528 #define PHY_CH_DEEP_PSR 0x7 1529 #define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6 * (phy) + 3 * (ch) + 2)) 1530 #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy)) 1531 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104) 1532 #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30)) 1533 #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch)))) 1534 #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline)))) 1535 1536 /* 1537 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 1538 * this field (only one bit may be set). 1539 */ 1540 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 1541 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 1542 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 1543 /* i830, required in DVO non-gang */ 1544 #define PLL_P2_DIVIDE_BY_4 (1 << 23) 1545 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 1546 #define PLL_REF_INPUT_DREFCLK (0 << 13) 1547 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 1548 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 1549 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 1550 #define PLL_REF_INPUT_MASK (3 << 13) 1551 #define PLL_LOAD_PULSE_PHASE_SHIFT 9 1552 /* Ironlake */ 1553 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 1554 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) 1555 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9) 1556 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 1557 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff 1558 1559 /* 1560 * Parallel to Serial Load Pulse phase selection. 1561 * Selects the phase for the 10X DPLL clock for the PCIe 1562 * digital display port. The range is 4 to 13; 10 or more 1563 * is just a flip delay. The default is 6 1564 */ 1565 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 1566 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 1567 /* 1568 * SDVO multiplier for 945G/GM. Not used on 965. 1569 */ 1570 #define SDVO_MULTIPLIER_MASK 0x000000ff 1571 #define SDVO_MULTIPLIER_SHIFT_HIRES 4 1572 #define SDVO_MULTIPLIER_SHIFT_VGA 0 1573 1574 #define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c) 1575 #define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020) 1576 #define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c) 1577 #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD) 1578 1579 /* 1580 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 1581 * 1582 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 1583 */ 1584 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 1585 #define DPLL_MD_UDI_DIVIDER_SHIFT 24 1586 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 1587 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 1588 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 1589 /* 1590 * SDVO/UDI pixel multiplier. 1591 * 1592 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 1593 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 1594 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 1595 * dummy bytes in the datastream at an increased clock rate, with both sides of 1596 * the link knowing how many bytes are fill. 1597 * 1598 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 1599 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 1600 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 1601 * through an SDVO command. 1602 * 1603 * This register field has values of multiplication factor minus 1, with 1604 * a maximum multiplier of 5 for SDVO. 1605 */ 1606 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 1607 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 1608 /* 1609 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 1610 * This best be set to the default value (3) or the CRT won't work. No, 1611 * I don't entirely understand what this does... 1612 */ 1613 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 1614 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 1615 1616 #define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024) 1617 1618 #define _FPA0 0x6040 1619 #define _FPA1 0x6044 1620 #define _FPB0 0x6048 1621 #define _FPB1 0x604c 1622 #define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0) 1623 #define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1) 1624 #define FP_N_DIV_MASK 0x003f0000 1625 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 1626 #define FP_N_DIV_SHIFT 16 1627 #define FP_M1_DIV_MASK 0x00003f00 1628 #define FP_M1_DIV_SHIFT 8 1629 #define FP_M2_DIV_MASK 0x0000003f 1630 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff 1631 #define FP_M2_DIV_SHIFT 0 1632 #define DPLL_TEST _MMIO(0x606c) 1633 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 1634 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 1635 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 1636 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 1637 #define DPLLB_TEST_N_BYPASS (1 << 19) 1638 #define DPLLB_TEST_M_BYPASS (1 << 18) 1639 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 1640 #define DPLLA_TEST_N_BYPASS (1 << 3) 1641 #define DPLLA_TEST_M_BYPASS (1 << 2) 1642 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 1643 #define D_STATE _MMIO(0x6104) 1644 #define DSTATE_GFX_RESET_I830 (1 << 6) 1645 #define DSTATE_PLL_D3_OFF (1 << 3) 1646 #define DSTATE_GFX_CLOCK_GATING (1 << 1) 1647 #define DSTATE_DOT_CLOCK_GATING (1 << 0) 1648 #define DSPCLK_GATE_D(__i915) _MMIO(DISPLAY_MMIO_BASE(__i915) + 0x6200) 1649 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ 1650 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ 1651 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ 1652 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ 1653 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ 1654 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ 1655 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ 1656 # define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */ 1657 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ 1658 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ 1659 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ 1660 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ 1661 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ 1662 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ 1663 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ 1664 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ 1665 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ 1666 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ 1667 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ 1668 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ 1669 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) 1670 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) 1671 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) 1672 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) 1673 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ 1674 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ 1675 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ 1676 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) 1677 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) 1678 /* 1679 * This bit must be set on the 830 to prevent hangs when turning off the 1680 * overlay scaler. 1681 */ 1682 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) 1683 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) 1684 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) 1685 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ 1686 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ 1687 1688 #define RENCLK_GATE_D1 _MMIO(0x6204) 1689 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ 1690 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ 1691 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) 1692 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) 1693 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) 1694 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) 1695 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) 1696 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) 1697 # define MAG_CLOCK_GATE_DISABLE (1 << 5) 1698 /* This bit must be unset on 855,865 */ 1699 # define MECI_CLOCK_GATE_DISABLE (1 << 4) 1700 # define DCMP_CLOCK_GATE_DISABLE (1 << 3) 1701 # define MEC_CLOCK_GATE_DISABLE (1 << 2) 1702 # define MECO_CLOCK_GATE_DISABLE (1 << 1) 1703 /* This bit must be set on 855,865. */ 1704 # define SV_CLOCK_GATE_DISABLE (1 << 0) 1705 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) 1706 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) 1707 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) 1708 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) 1709 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) 1710 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) 1711 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) 1712 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) 1713 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) 1714 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) 1715 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) 1716 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) 1717 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) 1718 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) 1719 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) 1720 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) 1721 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) 1722 1723 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) 1724 /* This bit must always be set on 965G/965GM */ 1725 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) 1726 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) 1727 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) 1728 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) 1729 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) 1730 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) 1731 /* This bit must always be set on 965G */ 1732 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) 1733 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) 1734 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) 1735 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) 1736 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) 1737 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) 1738 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) 1739 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) 1740 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) 1741 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) 1742 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) 1743 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) 1744 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) 1745 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) 1746 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) 1747 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) 1748 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) 1749 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) 1750 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) 1751 1752 #define RENCLK_GATE_D2 _MMIO(0x6208) 1753 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) 1754 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) 1755 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) 1756 1757 #define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */ 1758 #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4) 1759 1760 #define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */ 1761 #define DEUC _MMIO(0x6214) /* CRL only */ 1762 1763 #define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500) 1764 #define FW_CSPWRDWNEN (1 << 15) 1765 1766 #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504) 1767 1768 #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508) 1769 #define CDCLK_FREQ_SHIFT 4 1770 #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT) 1771 #define CZCLK_FREQ_MASK 0xf 1772 1773 #define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C) 1774 #define PFI_CREDIT_63 (9 << 28) /* chv only */ 1775 #define PFI_CREDIT_31 (8 << 28) /* chv only */ 1776 #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */ 1777 #define PFI_CREDIT_RESEND (1 << 27) 1778 #define VGA_FAST_MODE_DISABLE (1 << 14) 1779 1780 #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510) 1781 1782 /* 1783 * Palette regs 1784 */ 1785 #define _PALETTE_A 0xa000 1786 #define _PALETTE_B 0xa800 1787 #define _CHV_PALETTE_C 0xc000 1788 #define PALETTE_RED_MASK REG_GENMASK(23, 16) 1789 #define PALETTE_GREEN_MASK REG_GENMASK(15, 8) 1790 #define PALETTE_BLUE_MASK REG_GENMASK(7, 0) 1791 #define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \ 1792 _PICK((pipe), _PALETTE_A, \ 1793 _PALETTE_B, _CHV_PALETTE_C) + \ 1794 (i) * 4) 1795 1796 #define PEG_BAND_GAP_DATA _MMIO(0x14d68) 1797 1798 #define BXT_RP_STATE_CAP _MMIO(0x138170) 1799 #define GEN9_RP_STATE_LIMITS _MMIO(0x138148) 1800 #define XEHPSDV_RP_STATE_CAP _MMIO(0x250014) 1801 #define PVC_RP_STATE_CAP _MMIO(0x281014) 1802 1803 #define MTL_RP_STATE_CAP _MMIO(0x138000) 1804 #define MTL_MEDIAP_STATE_CAP _MMIO(0x138020) 1805 #define MTL_RP0_CAP_MASK REG_GENMASK(8, 0) 1806 #define MTL_RPN_CAP_MASK REG_GENMASK(24, 16) 1807 1808 #define MTL_GT_RPE_FREQUENCY _MMIO(0x13800c) 1809 #define MTL_MPE_FREQUENCY _MMIO(0x13802c) 1810 #define MTL_RPE_MASK REG_GENMASK(8, 0) 1811 1812 #define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8) 1813 #define GT0_PERF_LIMIT_REASONS_MASK 0xde3 1814 #define PROCHOT_MASK REG_BIT(0) 1815 #define THERMAL_LIMIT_MASK REG_BIT(1) 1816 #define RATL_MASK REG_BIT(5) 1817 #define VR_THERMALERT_MASK REG_BIT(6) 1818 #define VR_TDC_MASK REG_BIT(7) 1819 #define POWER_LIMIT_4_MASK REG_BIT(8) 1820 #define POWER_LIMIT_1_MASK REG_BIT(10) 1821 #define POWER_LIMIT_2_MASK REG_BIT(11) 1822 #define GT0_PERF_LIMIT_REASONS_LOG_MASK REG_GENMASK(31, 16) 1823 #define MTL_MEDIA_PERF_LIMIT_REASONS _MMIO(0x138030) 1824 1825 #define CHV_CLK_CTL1 _MMIO(0x101100) 1826 #define VLV_CLK_CTL2 _MMIO(0x101104) 1827 #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28 1828 1829 /* 1830 * Overlay regs 1831 */ 1832 1833 #define OVADD _MMIO(0x30000) 1834 #define DOVSTA _MMIO(0x30008) 1835 #define OC_BUF (0x3 << 20) 1836 #define OGAMC5 _MMIO(0x30010) 1837 #define OGAMC4 _MMIO(0x30014) 1838 #define OGAMC3 _MMIO(0x30018) 1839 #define OGAMC2 _MMIO(0x3001c) 1840 #define OGAMC1 _MMIO(0x30020) 1841 #define OGAMC0 _MMIO(0x30024) 1842 1843 /* 1844 * GEN9 clock gating regs 1845 */ 1846 #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530) 1847 #define DARBF_GATING_DIS (1 << 27) 1848 #define PWM2_GATING_DIS (1 << 14) 1849 #define PWM1_GATING_DIS (1 << 13) 1850 1851 #define GEN9_CLKGATE_DIS_3 _MMIO(0x46538) 1852 #define TGL_VRH_GATING_DIS REG_BIT(31) 1853 #define DPT_GATING_DIS REG_BIT(22) 1854 1855 #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C) 1856 #define BXT_GMBUS_GATING_DIS (1 << 14) 1857 1858 #define GEN9_CLKGATE_DIS_5 _MMIO(0x46540) 1859 #define DPCE_GATING_DIS REG_BIT(17) 1860 1861 #define _CLKGATE_DIS_PSL_A 0x46520 1862 #define _CLKGATE_DIS_PSL_B 0x46524 1863 #define _CLKGATE_DIS_PSL_C 0x46528 1864 #define DUPS1_GATING_DIS (1 << 15) 1865 #define DUPS2_GATING_DIS (1 << 19) 1866 #define DUPS3_GATING_DIS (1 << 23) 1867 #define CURSOR_GATING_DIS REG_BIT(28) 1868 #define DPF_GATING_DIS (1 << 10) 1869 #define DPF_RAM_GATING_DIS (1 << 9) 1870 #define DPFR_GATING_DIS (1 << 8) 1871 1872 #define CLKGATE_DIS_PSL(pipe) \ 1873 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B) 1874 1875 #define _CLKGATE_DIS_PSL_EXT_A 0x4654C 1876 #define _CLKGATE_DIS_PSL_EXT_B 0x46550 1877 #define PIPEDMC_GATING_DIS REG_BIT(12) 1878 1879 #define CLKGATE_DIS_PSL_EXT(pipe) \ 1880 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_EXT_A, _CLKGATE_DIS_PSL_EXT_B) 1881 1882 /* 1883 * Display engine regs 1884 */ 1885 1886 /* Pipe A CRC regs */ 1887 #define _PIPE_CRC_CTL_A 0x60050 1888 #define PIPE_CRC_ENABLE REG_BIT(31) 1889 /* skl+ source selection */ 1890 #define PIPE_CRC_SOURCE_MASK_SKL REG_GENMASK(30, 28) 1891 #define PIPE_CRC_SOURCE_PLANE_1_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 0) 1892 #define PIPE_CRC_SOURCE_PLANE_2_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 2) 1893 #define PIPE_CRC_SOURCE_DMUX_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 4) 1894 #define PIPE_CRC_SOURCE_PLANE_3_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 6) 1895 #define PIPE_CRC_SOURCE_PLANE_4_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 7) 1896 #define PIPE_CRC_SOURCE_PLANE_5_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 5) 1897 #define PIPE_CRC_SOURCE_PLANE_6_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 3) 1898 #define PIPE_CRC_SOURCE_PLANE_7_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 1) 1899 /* ivb+ source selection */ 1900 #define PIPE_CRC_SOURCE_MASK_IVB REG_GENMASK(30, 29) 1901 #define PIPE_CRC_SOURCE_PRIMARY_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 0) 1902 #define PIPE_CRC_SOURCE_SPRITE_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 1) 1903 #define PIPE_CRC_SOURCE_PF_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 2) 1904 /* ilk+ source selection */ 1905 #define PIPE_CRC_SOURCE_MASK_ILK REG_GENMASK(30, 28) 1906 #define PIPE_CRC_SOURCE_PRIMARY_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 0) 1907 #define PIPE_CRC_SOURCE_SPRITE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 1) 1908 #define PIPE_CRC_SOURCE_PIPE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 2) 1909 /* embedded DP port on the north display block */ 1910 #define PIPE_CRC_SOURCE_PORT_A_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 4) 1911 #define PIPE_CRC_SOURCE_FDI_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 5) 1912 /* vlv source selection */ 1913 #define PIPE_CRC_SOURCE_MASK_VLV REG_GENMASK(30, 27) 1914 #define PIPE_CRC_SOURCE_PIPE_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 0) 1915 #define PIPE_CRC_SOURCE_HDMIB_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 1) 1916 #define PIPE_CRC_SOURCE_HDMIC_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 2) 1917 /* with DP port the pipe source is invalid */ 1918 #define PIPE_CRC_SOURCE_DP_D_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 3) 1919 #define PIPE_CRC_SOURCE_DP_B_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 6) 1920 #define PIPE_CRC_SOURCE_DP_C_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 7) 1921 /* gen3+ source selection */ 1922 #define PIPE_CRC_SOURCE_MASK_I9XX REG_GENMASK(30, 28) 1923 #define PIPE_CRC_SOURCE_PIPE_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 0) 1924 #define PIPE_CRC_SOURCE_SDVOB_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 1) 1925 #define PIPE_CRC_SOURCE_SDVOC_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 2) 1926 /* with DP/TV port the pipe source is invalid */ 1927 #define PIPE_CRC_SOURCE_DP_D_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 3) 1928 #define PIPE_CRC_SOURCE_TV_PRE REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 4) 1929 #define PIPE_CRC_SOURCE_TV_POST REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 5) 1930 #define PIPE_CRC_SOURCE_DP_B_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 6) 1931 #define PIPE_CRC_SOURCE_DP_C_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 7) 1932 /* gen2 doesn't have source selection bits */ 1933 #define PIPE_CRC_INCLUDE_BORDER_I8XX REG_BIT(30) 1934 1935 #define _PIPE_CRC_RES_1_A_IVB 0x60064 1936 #define _PIPE_CRC_RES_2_A_IVB 0x60068 1937 #define _PIPE_CRC_RES_3_A_IVB 0x6006c 1938 #define _PIPE_CRC_RES_4_A_IVB 0x60070 1939 #define _PIPE_CRC_RES_5_A_IVB 0x60074 1940 1941 #define _PIPE_CRC_RES_RED_A 0x60060 1942 #define _PIPE_CRC_RES_GREEN_A 0x60064 1943 #define _PIPE_CRC_RES_BLUE_A 0x60068 1944 #define _PIPE_CRC_RES_RES1_A_I915 0x6006c 1945 #define _PIPE_CRC_RES_RES2_A_G4X 0x60080 1946 1947 /* Pipe B CRC regs */ 1948 #define _PIPE_CRC_RES_1_B_IVB 0x61064 1949 #define _PIPE_CRC_RES_2_B_IVB 0x61068 1950 #define _PIPE_CRC_RES_3_B_IVB 0x6106c 1951 #define _PIPE_CRC_RES_4_B_IVB 0x61070 1952 #define _PIPE_CRC_RES_5_B_IVB 0x61074 1953 1954 #define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A) 1955 #define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB) 1956 #define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB) 1957 #define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB) 1958 #define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB) 1959 #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB) 1960 1961 #define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A) 1962 #define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A) 1963 #define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A) 1964 #define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915) 1965 #define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X) 1966 1967 /* Pipe A timing regs */ 1968 #define _HTOTAL_A 0x60000 1969 #define _HBLANK_A 0x60004 1970 #define _HSYNC_A 0x60008 1971 #define _VTOTAL_A 0x6000c 1972 #define _VBLANK_A 0x60010 1973 #define _VSYNC_A 0x60014 1974 #define _EXITLINE_A 0x60018 1975 #define _PIPEASRC 0x6001c 1976 #define PIPESRC_WIDTH_MASK REG_GENMASK(31, 16) 1977 #define PIPESRC_WIDTH(w) REG_FIELD_PREP(PIPESRC_WIDTH_MASK, (w)) 1978 #define PIPESRC_HEIGHT_MASK REG_GENMASK(15, 0) 1979 #define PIPESRC_HEIGHT(h) REG_FIELD_PREP(PIPESRC_HEIGHT_MASK, (h)) 1980 #define _BCLRPAT_A 0x60020 1981 #define _VSYNCSHIFT_A 0x60028 1982 #define _PIPE_MULT_A 0x6002c 1983 1984 /* Pipe B timing regs */ 1985 #define _HTOTAL_B 0x61000 1986 #define _HBLANK_B 0x61004 1987 #define _HSYNC_B 0x61008 1988 #define _VTOTAL_B 0x6100c 1989 #define _VBLANK_B 0x61010 1990 #define _VSYNC_B 0x61014 1991 #define _PIPEBSRC 0x6101c 1992 #define _BCLRPAT_B 0x61020 1993 #define _VSYNCSHIFT_B 0x61028 1994 #define _PIPE_MULT_B 0x6102c 1995 1996 /* DSI 0 timing regs */ 1997 #define _HTOTAL_DSI0 0x6b000 1998 #define _HSYNC_DSI0 0x6b008 1999 #define _VTOTAL_DSI0 0x6b00c 2000 #define _VSYNC_DSI0 0x6b014 2001 #define _VSYNCSHIFT_DSI0 0x6b028 2002 2003 /* DSI 1 timing regs */ 2004 #define _HTOTAL_DSI1 0x6b800 2005 #define _HSYNC_DSI1 0x6b808 2006 #define _VTOTAL_DSI1 0x6b80c 2007 #define _VSYNC_DSI1 0x6b814 2008 #define _VSYNCSHIFT_DSI1 0x6b828 2009 2010 #define TRANSCODER_A_OFFSET 0x60000 2011 #define TRANSCODER_B_OFFSET 0x61000 2012 #define TRANSCODER_C_OFFSET 0x62000 2013 #define CHV_TRANSCODER_C_OFFSET 0x63000 2014 #define TRANSCODER_D_OFFSET 0x63000 2015 #define TRANSCODER_EDP_OFFSET 0x6f000 2016 #define TRANSCODER_DSI0_OFFSET 0x6b000 2017 #define TRANSCODER_DSI1_OFFSET 0x6b800 2018 2019 #define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A) 2020 #define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A) 2021 #define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A) 2022 #define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A) 2023 #define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A) 2024 #define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A) 2025 #define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A) 2026 #define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A) 2027 #define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC) 2028 #define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A) 2029 2030 #define EXITLINE(trans) _MMIO_TRANS2(trans, _EXITLINE_A) 2031 #define EXITLINE_ENABLE REG_BIT(31) 2032 #define EXITLINE_MASK REG_GENMASK(12, 0) 2033 #define EXITLINE_SHIFT 0 2034 2035 /* VRR registers */ 2036 #define _TRANS_VRR_CTL_A 0x60420 2037 #define _TRANS_VRR_CTL_B 0x61420 2038 #define _TRANS_VRR_CTL_C 0x62420 2039 #define _TRANS_VRR_CTL_D 0x63420 2040 #define TRANS_VRR_CTL(trans) _MMIO_TRANS2(trans, _TRANS_VRR_CTL_A) 2041 #define VRR_CTL_VRR_ENABLE REG_BIT(31) 2042 #define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30) 2043 #define VRR_CTL_FLIP_LINE_EN REG_BIT(29) 2044 #define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3) 2045 #define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x)) 2046 #define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0) 2047 #define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0) 2048 #define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x)) 2049 2050 #define _TRANS_VRR_VMAX_A 0x60424 2051 #define _TRANS_VRR_VMAX_B 0x61424 2052 #define _TRANS_VRR_VMAX_C 0x62424 2053 #define _TRANS_VRR_VMAX_D 0x63424 2054 #define TRANS_VRR_VMAX(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMAX_A) 2055 #define VRR_VMAX_MASK REG_GENMASK(19, 0) 2056 2057 #define _TRANS_VRR_VMIN_A 0x60434 2058 #define _TRANS_VRR_VMIN_B 0x61434 2059 #define _TRANS_VRR_VMIN_C 0x62434 2060 #define _TRANS_VRR_VMIN_D 0x63434 2061 #define TRANS_VRR_VMIN(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMIN_A) 2062 #define VRR_VMIN_MASK REG_GENMASK(15, 0) 2063 2064 #define _TRANS_VRR_VMAXSHIFT_A 0x60428 2065 #define _TRANS_VRR_VMAXSHIFT_B 0x61428 2066 #define _TRANS_VRR_VMAXSHIFT_C 0x62428 2067 #define _TRANS_VRR_VMAXSHIFT_D 0x63428 2068 #define TRANS_VRR_VMAXSHIFT(trans) _MMIO_TRANS2(trans, \ 2069 _TRANS_VRR_VMAXSHIFT_A) 2070 #define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16) 2071 #define VRR_VMAXSHIFT_DEC REG_BIT(16) 2072 #define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0) 2073 2074 #define _TRANS_VRR_STATUS_A 0x6042C 2075 #define _TRANS_VRR_STATUS_B 0x6142C 2076 #define _TRANS_VRR_STATUS_C 0x6242C 2077 #define _TRANS_VRR_STATUS_D 0x6342C 2078 #define TRANS_VRR_STATUS(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS_A) 2079 #define VRR_STATUS_VMAX_REACHED REG_BIT(31) 2080 #define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30) 2081 #define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29) 2082 #define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28) 2083 #define VRR_STATUS_VRR_EN_LIVE REG_BIT(27) 2084 #define VRR_STATUS_FLIPS_SERVICED REG_BIT(26) 2085 #define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20) 2086 #define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0) 2087 #define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1) 2088 #define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2) 2089 #define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3) 2090 #define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4) 2091 #define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5) 2092 #define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6) 2093 2094 #define _TRANS_VRR_VTOTAL_PREV_A 0x60480 2095 #define _TRANS_VRR_VTOTAL_PREV_B 0x61480 2096 #define _TRANS_VRR_VTOTAL_PREV_C 0x62480 2097 #define _TRANS_VRR_VTOTAL_PREV_D 0x63480 2098 #define TRANS_VRR_VTOTAL_PREV(trans) _MMIO_TRANS2(trans, \ 2099 _TRANS_VRR_VTOTAL_PREV_A) 2100 #define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31) 2101 #define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30) 2102 #define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29) 2103 #define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0) 2104 2105 #define _TRANS_VRR_FLIPLINE_A 0x60438 2106 #define _TRANS_VRR_FLIPLINE_B 0x61438 2107 #define _TRANS_VRR_FLIPLINE_C 0x62438 2108 #define _TRANS_VRR_FLIPLINE_D 0x63438 2109 #define TRANS_VRR_FLIPLINE(trans) _MMIO_TRANS2(trans, \ 2110 _TRANS_VRR_FLIPLINE_A) 2111 #define VRR_FLIPLINE_MASK REG_GENMASK(19, 0) 2112 2113 #define _TRANS_VRR_STATUS2_A 0x6043C 2114 #define _TRANS_VRR_STATUS2_B 0x6143C 2115 #define _TRANS_VRR_STATUS2_C 0x6243C 2116 #define _TRANS_VRR_STATUS2_D 0x6343C 2117 #define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A) 2118 #define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0) 2119 2120 #define _TRANS_PUSH_A 0x60A70 2121 #define _TRANS_PUSH_B 0x61A70 2122 #define _TRANS_PUSH_C 0x62A70 2123 #define _TRANS_PUSH_D 0x63A70 2124 #define TRANS_PUSH(trans) _MMIO_TRANS2(trans, _TRANS_PUSH_A) 2125 #define TRANS_PUSH_EN REG_BIT(31) 2126 #define TRANS_PUSH_SEND REG_BIT(30) 2127 2128 /* 2129 * HSW+ eDP PSR registers 2130 * 2131 * HSW PSR registers are relative to DDIA(_DDI_BUF_CTL_A + 0x800) with just one 2132 * instance of it 2133 */ 2134 #define _SRD_CTL_A 0x60800 2135 #define _SRD_CTL_EDP 0x6f800 2136 #define EDP_PSR_CTL(tran) _MMIO_TRANS2(tran, _SRD_CTL_A) 2137 #define EDP_PSR_ENABLE (1 << 31) 2138 #define BDW_PSR_SINGLE_FRAME (1 << 30) 2139 #define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1 << 29) /* SW can't modify */ 2140 #define EDP_PSR_LINK_STANDBY (1 << 27) 2141 #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3 << 25) 2142 #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0 << 25) 2143 #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1 << 25) 2144 #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2 << 25) 2145 #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3 << 25) 2146 #define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20 2147 #define EDP_PSR_SKIP_AUX_EXIT (1 << 12) 2148 #define EDP_PSR_TP1_TP2_SEL (0 << 11) 2149 #define EDP_PSR_TP1_TP3_SEL (1 << 11) 2150 #define EDP_PSR_CRC_ENABLE (1 << 10) /* BDW+ */ 2151 #define EDP_PSR_TP2_TP3_TIME_500us (0 << 8) 2152 #define EDP_PSR_TP2_TP3_TIME_100us (1 << 8) 2153 #define EDP_PSR_TP2_TP3_TIME_2500us (2 << 8) 2154 #define EDP_PSR_TP2_TP3_TIME_0us (3 << 8) 2155 #define EDP_PSR_TP4_TIME_0US (3 << 6) /* ICL+ */ 2156 #define EDP_PSR_TP1_TIME_500us (0 << 4) 2157 #define EDP_PSR_TP1_TIME_100us (1 << 4) 2158 #define EDP_PSR_TP1_TIME_2500us (2 << 4) 2159 #define EDP_PSR_TP1_TIME_0us (3 << 4) 2160 #define EDP_PSR_IDLE_FRAME_SHIFT 0 2161 2162 /* 2163 * Until TGL, IMR/IIR are fixed at 0x648xx. On TGL+ those registers are relative 2164 * to transcoder and bits defined for each one as if using no shift (i.e. as if 2165 * it was for TRANSCODER_EDP) 2166 */ 2167 #define EDP_PSR_IMR _MMIO(0x64834) 2168 #define EDP_PSR_IIR _MMIO(0x64838) 2169 #define _PSR_IMR_A 0x60814 2170 #define _PSR_IIR_A 0x60818 2171 #define TRANS_PSR_IMR(tran) _MMIO_TRANS2(tran, _PSR_IMR_A) 2172 #define TRANS_PSR_IIR(tran) _MMIO_TRANS2(tran, _PSR_IIR_A) 2173 #define _EDP_PSR_TRANS_SHIFT(trans) ((trans) == TRANSCODER_EDP ? \ 2174 0 : ((trans) - TRANSCODER_A + 1) * 8) 2175 #define TGL_PSR_MASK REG_GENMASK(2, 0) 2176 #define TGL_PSR_ERROR REG_BIT(2) 2177 #define TGL_PSR_POST_EXIT REG_BIT(1) 2178 #define TGL_PSR_PRE_ENTRY REG_BIT(0) 2179 #define EDP_PSR_MASK(trans) (TGL_PSR_MASK << \ 2180 _EDP_PSR_TRANS_SHIFT(trans)) 2181 #define EDP_PSR_ERROR(trans) (TGL_PSR_ERROR << \ 2182 _EDP_PSR_TRANS_SHIFT(trans)) 2183 #define EDP_PSR_POST_EXIT(trans) (TGL_PSR_POST_EXIT << \ 2184 _EDP_PSR_TRANS_SHIFT(trans)) 2185 #define EDP_PSR_PRE_ENTRY(trans) (TGL_PSR_PRE_ENTRY << \ 2186 _EDP_PSR_TRANS_SHIFT(trans)) 2187 2188 #define _SRD_AUX_DATA_A 0x60814 2189 #define _SRD_AUX_DATA_EDP 0x6f814 2190 #define EDP_PSR_AUX_DATA(tran, i) _MMIO_TRANS2(tran, _SRD_AUX_DATA_A + (i) + 4) /* 5 registers */ 2191 2192 #define _SRD_STATUS_A 0x60840 2193 #define _SRD_STATUS_EDP 0x6f840 2194 #define EDP_PSR_STATUS(tran) _MMIO_TRANS2(tran, _SRD_STATUS_A) 2195 #define EDP_PSR_STATUS_STATE_MASK (7 << 29) 2196 #define EDP_PSR_STATUS_STATE_SHIFT 29 2197 #define EDP_PSR_STATUS_STATE_IDLE (0 << 29) 2198 #define EDP_PSR_STATUS_STATE_SRDONACK (1 << 29) 2199 #define EDP_PSR_STATUS_STATE_SRDENT (2 << 29) 2200 #define EDP_PSR_STATUS_STATE_BUFOFF (3 << 29) 2201 #define EDP_PSR_STATUS_STATE_BUFON (4 << 29) 2202 #define EDP_PSR_STATUS_STATE_AUXACK (5 << 29) 2203 #define EDP_PSR_STATUS_STATE_SRDOFFACK (6 << 29) 2204 #define EDP_PSR_STATUS_LINK_MASK (3 << 26) 2205 #define EDP_PSR_STATUS_LINK_FULL_OFF (0 << 26) 2206 #define EDP_PSR_STATUS_LINK_FULL_ON (1 << 26) 2207 #define EDP_PSR_STATUS_LINK_STANDBY (2 << 26) 2208 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20 2209 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f 2210 #define EDP_PSR_STATUS_COUNT_SHIFT 16 2211 #define EDP_PSR_STATUS_COUNT_MASK 0xf 2212 #define EDP_PSR_STATUS_AUX_ERROR (1 << 15) 2213 #define EDP_PSR_STATUS_AUX_SENDING (1 << 12) 2214 #define EDP_PSR_STATUS_SENDING_IDLE (1 << 9) 2215 #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1 << 8) 2216 #define EDP_PSR_STATUS_SENDING_TP1 (1 << 4) 2217 #define EDP_PSR_STATUS_IDLE_MASK 0xf 2218 2219 #define _SRD_PERF_CNT_A 0x60844 2220 #define _SRD_PERF_CNT_EDP 0x6f844 2221 #define EDP_PSR_PERF_CNT(tran) _MMIO_TRANS2(tran, _SRD_PERF_CNT_A) 2222 #define EDP_PSR_PERF_CNT_MASK 0xffffff 2223 2224 /* PSR_MASK on SKL+ */ 2225 #define _SRD_DEBUG_A 0x60860 2226 #define _SRD_DEBUG_EDP 0x6f860 2227 #define EDP_PSR_DEBUG(tran) _MMIO_TRANS2(tran, _SRD_DEBUG_A) 2228 #define EDP_PSR_DEBUG_MASK_MAX_SLEEP (1 << 28) 2229 #define EDP_PSR_DEBUG_MASK_LPSP (1 << 27) 2230 #define EDP_PSR_DEBUG_MASK_MEMUP (1 << 26) 2231 #define EDP_PSR_DEBUG_MASK_HPD (1 << 25) 2232 #define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) /* Reserved in ICL+ */ 2233 #define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */ 2234 2235 #define _PSR2_CTL_A 0x60900 2236 #define _PSR2_CTL_EDP 0x6f900 2237 #define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A) 2238 #define EDP_PSR2_ENABLE (1 << 31) 2239 #define EDP_SU_TRACK_ENABLE (1 << 30) /* up to adl-p */ 2240 #define TGL_EDP_PSR2_BLOCK_COUNT_NUM_2 (0 << 28) 2241 #define TGL_EDP_PSR2_BLOCK_COUNT_NUM_3 (1 << 28) 2242 #define EDP_Y_COORDINATE_ENABLE REG_BIT(25) /* display 10, 11 and 12 */ 2243 #define EDP_PSR2_SU_SDP_SCANLINE REG_BIT(25) /* display 13+ */ 2244 #define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20) 2245 #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20) 2246 #define EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES 8 2247 #define EDP_PSR2_IO_BUFFER_WAKE(lines) ((EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines)) << 13) 2248 #define EDP_PSR2_IO_BUFFER_WAKE_MASK (3 << 13) 2249 #define TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5 2250 #define TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT 13 2251 #define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) (((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT) 2252 #define TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK (7 << 13) 2253 #define EDP_PSR2_FAST_WAKE_MAX_LINES 8 2254 #define EDP_PSR2_FAST_WAKE(lines) ((EDP_PSR2_FAST_WAKE_MAX_LINES - (lines)) << 11) 2255 #define EDP_PSR2_FAST_WAKE_MASK (3 << 11) 2256 #define TGL_EDP_PSR2_FAST_WAKE_MIN_LINES 5 2257 #define TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT 10 2258 #define TGL_EDP_PSR2_FAST_WAKE(lines) (((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT) 2259 #define TGL_EDP_PSR2_FAST_WAKE_MASK (7 << 10) 2260 #define EDP_PSR2_TP2_TIME_500us (0 << 8) 2261 #define EDP_PSR2_TP2_TIME_100us (1 << 8) 2262 #define EDP_PSR2_TP2_TIME_2500us (2 << 8) 2263 #define EDP_PSR2_TP2_TIME_50us (3 << 8) 2264 #define EDP_PSR2_TP2_TIME_MASK (3 << 8) 2265 #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 2266 #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4) 2267 #define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4) 2268 #define EDP_PSR2_IDLE_FRAME_MASK 0xf 2269 #define EDP_PSR2_IDLE_FRAME_SHIFT 0 2270 2271 #define _PSR_EVENT_TRANS_A 0x60848 2272 #define _PSR_EVENT_TRANS_B 0x61848 2273 #define _PSR_EVENT_TRANS_C 0x62848 2274 #define _PSR_EVENT_TRANS_D 0x63848 2275 #define _PSR_EVENT_TRANS_EDP 0x6f848 2276 #define PSR_EVENT(tran) _MMIO_TRANS2(tran, _PSR_EVENT_TRANS_A) 2277 #define PSR_EVENT_PSR2_WD_TIMER_EXPIRE (1 << 17) 2278 #define PSR_EVENT_PSR2_DISABLED (1 << 16) 2279 #define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN (1 << 15) 2280 #define PSR_EVENT_SU_CRC_FIFO_UNDERRUN (1 << 14) 2281 #define PSR_EVENT_GRAPHICS_RESET (1 << 12) 2282 #define PSR_EVENT_PCH_INTERRUPT (1 << 11) 2283 #define PSR_EVENT_MEMORY_UP (1 << 10) 2284 #define PSR_EVENT_FRONT_BUFFER_MODIFY (1 << 9) 2285 #define PSR_EVENT_WD_TIMER_EXPIRE (1 << 8) 2286 #define PSR_EVENT_PIPE_REGISTERS_UPDATE (1 << 6) 2287 #define PSR_EVENT_REGISTER_UPDATE (1 << 5) /* Reserved in ICL+ */ 2288 #define PSR_EVENT_HDCP_ENABLE (1 << 4) 2289 #define PSR_EVENT_KVMR_SESSION_ENABLE (1 << 3) 2290 #define PSR_EVENT_VBI_ENABLE (1 << 2) 2291 #define PSR_EVENT_LPSP_MODE_EXIT (1 << 1) 2292 #define PSR_EVENT_PSR_DISABLE (1 << 0) 2293 2294 #define _PSR2_STATUS_A 0x60940 2295 #define _PSR2_STATUS_EDP 0x6f940 2296 #define EDP_PSR2_STATUS(tran) _MMIO_TRANS2(tran, _PSR2_STATUS_A) 2297 #define EDP_PSR2_STATUS_STATE_MASK REG_GENMASK(31, 28) 2298 #define EDP_PSR2_STATUS_STATE_DEEP_SLEEP REG_FIELD_PREP(EDP_PSR2_STATUS_STATE_MASK, 0x8) 2299 2300 #define _PSR2_SU_STATUS_A 0x60914 2301 #define _PSR2_SU_STATUS_EDP 0x6f914 2302 #define _PSR2_SU_STATUS(tran, index) _MMIO_TRANS2(tran, _PSR2_SU_STATUS_A + (index) * 4) 2303 #define PSR2_SU_STATUS(tran, frame) (_PSR2_SU_STATUS(tran, (frame) / 3)) 2304 #define PSR2_SU_STATUS_SHIFT(frame) (((frame) % 3) * 10) 2305 #define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame)) 2306 #define PSR2_SU_STATUS_FRAMES 8 2307 2308 #define _PSR2_MAN_TRK_CTL_A 0x60910 2309 #define _PSR2_MAN_TRK_CTL_EDP 0x6f910 2310 #define PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A) 2311 #define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31) 2312 #define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30, 21) 2313 #define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val) 2314 #define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(20, 11) 2315 #define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val) 2316 #define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3) 2317 #define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2) 2318 #define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1) 2319 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(28, 16) 2320 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val) 2321 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(12, 0) 2322 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val) 2323 #define ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(31) 2324 #define ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(14) 2325 #define ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(13) 2326 2327 /* Icelake DSC Rate Control Range Parameter Registers */ 2328 #define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240) 2329 #define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4) 2330 #define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40) 2331 #define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4) 2332 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208) 2333 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4) 2334 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308) 2335 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4) 2336 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408) 2337 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4) 2338 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508) 2339 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4) 2340 #define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2341 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \ 2342 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC) 2343 #define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2344 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \ 2345 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC) 2346 #define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2347 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \ 2348 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC) 2349 #define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2350 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \ 2351 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC) 2352 #define RC_BPG_OFFSET_SHIFT 10 2353 #define RC_MAX_QP_SHIFT 5 2354 #define RC_MIN_QP_SHIFT 0 2355 2356 #define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248) 2357 #define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4) 2358 #define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48) 2359 #define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4) 2360 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210) 2361 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4) 2362 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310) 2363 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4) 2364 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410) 2365 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4) 2366 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510) 2367 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4) 2368 #define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2369 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \ 2370 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC) 2371 #define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2372 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \ 2373 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC) 2374 #define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2375 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \ 2376 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC) 2377 #define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2378 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \ 2379 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC) 2380 2381 #define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250) 2382 #define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4) 2383 #define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50) 2384 #define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4) 2385 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218) 2386 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4) 2387 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318) 2388 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4) 2389 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418) 2390 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4) 2391 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518) 2392 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4) 2393 #define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2394 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \ 2395 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC) 2396 #define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2397 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \ 2398 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC) 2399 #define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2400 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \ 2401 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC) 2402 #define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2403 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \ 2404 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC) 2405 2406 #define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258) 2407 #define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4) 2408 #define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58) 2409 #define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4) 2410 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220) 2411 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4) 2412 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320) 2413 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4) 2414 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420) 2415 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4) 2416 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520) 2417 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4) 2418 #define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2419 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \ 2420 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC) 2421 #define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2422 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \ 2423 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC) 2424 #define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2425 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \ 2426 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC) 2427 #define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2428 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \ 2429 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC) 2430 2431 /* VGA port control */ 2432 #define ADPA _MMIO(0x61100) 2433 #define PCH_ADPA _MMIO(0xe1100) 2434 #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100) 2435 2436 #define ADPA_DAC_ENABLE (1 << 31) 2437 #define ADPA_DAC_DISABLE 0 2438 #define ADPA_PIPE_SEL_SHIFT 30 2439 #define ADPA_PIPE_SEL_MASK (1 << 30) 2440 #define ADPA_PIPE_SEL(pipe) ((pipe) << 30) 2441 #define ADPA_PIPE_SEL_SHIFT_CPT 29 2442 #define ADPA_PIPE_SEL_MASK_CPT (3 << 29) 2443 #define ADPA_PIPE_SEL_CPT(pipe) ((pipe) << 29) 2444 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ 2445 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0 << 24) 2446 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3 << 24) 2447 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3 << 24) 2448 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2 << 24) 2449 #define ADPA_CRT_HOTPLUG_ENABLE (1 << 23) 2450 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0 << 22) 2451 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1 << 22) 2452 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0 << 21) 2453 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1 << 21) 2454 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0 << 20) 2455 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1 << 20) 2456 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0 << 18) 2457 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1 << 18) 2458 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2 << 18) 2459 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3 << 18) 2460 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0 << 17) 2461 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1 << 17) 2462 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1 << 16) 2463 #define ADPA_USE_VGA_HVPOLARITY (1 << 15) 2464 #define ADPA_SETS_HVPOLARITY 0 2465 #define ADPA_VSYNC_CNTL_DISABLE (1 << 10) 2466 #define ADPA_VSYNC_CNTL_ENABLE 0 2467 #define ADPA_HSYNC_CNTL_DISABLE (1 << 11) 2468 #define ADPA_HSYNC_CNTL_ENABLE 0 2469 #define ADPA_VSYNC_ACTIVE_HIGH (1 << 4) 2470 #define ADPA_VSYNC_ACTIVE_LOW 0 2471 #define ADPA_HSYNC_ACTIVE_HIGH (1 << 3) 2472 #define ADPA_HSYNC_ACTIVE_LOW 0 2473 #define ADPA_DPMS_MASK (~(3 << 10)) 2474 #define ADPA_DPMS_ON (0 << 10) 2475 #define ADPA_DPMS_SUSPEND (1 << 10) 2476 #define ADPA_DPMS_STANDBY (2 << 10) 2477 #define ADPA_DPMS_OFF (3 << 10) 2478 2479 2480 /* Hotplug control (945+ only) */ 2481 #define PORT_HOTPLUG_EN _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110) 2482 #define PORTB_HOTPLUG_INT_EN (1 << 29) 2483 #define PORTC_HOTPLUG_INT_EN (1 << 28) 2484 #define PORTD_HOTPLUG_INT_EN (1 << 27) 2485 #define SDVOB_HOTPLUG_INT_EN (1 << 26) 2486 #define SDVOC_HOTPLUG_INT_EN (1 << 25) 2487 #define TV_HOTPLUG_INT_EN (1 << 18) 2488 #define CRT_HOTPLUG_INT_EN (1 << 9) 2489 #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \ 2490 PORTC_HOTPLUG_INT_EN | \ 2491 PORTD_HOTPLUG_INT_EN | \ 2492 SDVOC_HOTPLUG_INT_EN | \ 2493 SDVOB_HOTPLUG_INT_EN | \ 2494 CRT_HOTPLUG_INT_EN) 2495 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 2496 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) 2497 /* must use period 64 on GM45 according to docs */ 2498 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) 2499 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) 2500 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) 2501 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) 2502 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) 2503 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) 2504 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) 2505 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) 2506 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) 2507 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) 2508 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) 2509 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 2510 2511 #define PORT_HOTPLUG_STAT _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114) 2512 /* 2513 * HDMI/DP bits are g4x+ 2514 * 2515 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused. 2516 * Please check the detailed lore in the commit message for for experimental 2517 * evidence. 2518 */ 2519 /* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */ 2520 #define PORTD_HOTPLUG_LIVE_STATUS_GM45 (1 << 29) 2521 #define PORTC_HOTPLUG_LIVE_STATUS_GM45 (1 << 28) 2522 #define PORTB_HOTPLUG_LIVE_STATUS_GM45 (1 << 27) 2523 /* G4X/VLV/CHV DP/HDMI bits again match Bspec */ 2524 #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27) 2525 #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28) 2526 #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29) 2527 #define PORTD_HOTPLUG_INT_STATUS (3 << 21) 2528 #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21) 2529 #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21) 2530 #define PORTC_HOTPLUG_INT_STATUS (3 << 19) 2531 #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19) 2532 #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19) 2533 #define PORTB_HOTPLUG_INT_STATUS (3 << 17) 2534 #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17) 2535 #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17) 2536 /* CRT/TV common between gen3+ */ 2537 #define CRT_HOTPLUG_INT_STATUS (1 << 11) 2538 #define TV_HOTPLUG_INT_STATUS (1 << 10) 2539 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 2540 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 2541 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 2542 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 2543 #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6) 2544 #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5) 2545 #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4) 2546 #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4) 2547 2548 /* SDVO is different across gen3/4 */ 2549 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) 2550 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) 2551 /* 2552 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm, 2553 * since reality corrobates that they're the same as on gen3. But keep these 2554 * bits here (and the comment!) to help any other lost wanderers back onto the 2555 * right tracks. 2556 */ 2557 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4) 2558 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) 2559 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) 2560 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) 2561 #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \ 2562 SDVOB_HOTPLUG_INT_STATUS_G4X | \ 2563 SDVOC_HOTPLUG_INT_STATUS_G4X | \ 2564 PORTB_HOTPLUG_INT_STATUS | \ 2565 PORTC_HOTPLUG_INT_STATUS | \ 2566 PORTD_HOTPLUG_INT_STATUS) 2567 2568 #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \ 2569 SDVOB_HOTPLUG_INT_STATUS_I915 | \ 2570 SDVOC_HOTPLUG_INT_STATUS_I915 | \ 2571 PORTB_HOTPLUG_INT_STATUS | \ 2572 PORTC_HOTPLUG_INT_STATUS | \ 2573 PORTD_HOTPLUG_INT_STATUS) 2574 2575 /* SDVO and HDMI port control. 2576 * The same register may be used for SDVO or HDMI */ 2577 #define _GEN3_SDVOB 0x61140 2578 #define _GEN3_SDVOC 0x61160 2579 #define GEN3_SDVOB _MMIO(_GEN3_SDVOB) 2580 #define GEN3_SDVOC _MMIO(_GEN3_SDVOC) 2581 #define GEN4_HDMIB GEN3_SDVOB 2582 #define GEN4_HDMIC GEN3_SDVOC 2583 #define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140) 2584 #define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160) 2585 #define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C) 2586 #define PCH_SDVOB _MMIO(0xe1140) 2587 #define PCH_HDMIB PCH_SDVOB 2588 #define PCH_HDMIC _MMIO(0xe1150) 2589 #define PCH_HDMID _MMIO(0xe1160) 2590 2591 #define PORT_DFT_I9XX _MMIO(0x61150) 2592 #define DC_BALANCE_RESET (1 << 25) 2593 #define PORT_DFT2_G4X _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154) 2594 #define DC_BALANCE_RESET_VLV (1 << 31) 2595 #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0)) 2596 #define PIPE_C_SCRAMBLE_RESET REG_BIT(14) /* chv */ 2597 #define PIPE_B_SCRAMBLE_RESET REG_BIT(1) 2598 #define PIPE_A_SCRAMBLE_RESET REG_BIT(0) 2599 2600 /* Gen 3 SDVO bits: */ 2601 #define SDVO_ENABLE (1 << 31) 2602 #define SDVO_PIPE_SEL_SHIFT 30 2603 #define SDVO_PIPE_SEL_MASK (1 << 30) 2604 #define SDVO_PIPE_SEL(pipe) ((pipe) << 30) 2605 #define SDVO_STALL_SELECT (1 << 29) 2606 #define SDVO_INTERRUPT_ENABLE (1 << 26) 2607 /* 2608 * 915G/GM SDVO pixel multiplier. 2609 * Programmed value is multiplier - 1, up to 5x. 2610 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 2611 */ 2612 #define SDVO_PORT_MULTIPLY_MASK (7 << 23) 2613 #define SDVO_PORT_MULTIPLY_SHIFT 23 2614 #define SDVO_PHASE_SELECT_MASK (15 << 19) 2615 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 2616 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 2617 #define SDVOC_GANG_MODE (1 << 16) /* Port C only */ 2618 #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */ 2619 #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */ 2620 #define SDVO_DETECTED (1 << 2) 2621 /* Bits to be preserved when writing */ 2622 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \ 2623 SDVO_INTERRUPT_ENABLE) 2624 #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE) 2625 2626 /* Gen 4 SDVO/HDMI bits: */ 2627 #define SDVO_COLOR_FORMAT_8bpc (0 << 26) 2628 #define SDVO_COLOR_FORMAT_MASK (7 << 26) 2629 #define SDVO_ENCODING_SDVO (0 << 10) 2630 #define SDVO_ENCODING_HDMI (2 << 10) 2631 #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */ 2632 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */ 2633 #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */ 2634 #define HDMI_AUDIO_ENABLE (1 << 6) /* HDMI only */ 2635 /* VSYNC/HSYNC bits new with 965, default is to be set */ 2636 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) 2637 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) 2638 2639 /* Gen 5 (IBX) SDVO/HDMI bits: */ 2640 #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */ 2641 #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */ 2642 2643 /* Gen 6 (CPT) SDVO/HDMI bits: */ 2644 #define SDVO_PIPE_SEL_SHIFT_CPT 29 2645 #define SDVO_PIPE_SEL_MASK_CPT (3 << 29) 2646 #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29) 2647 2648 /* CHV SDVO/HDMI bits: */ 2649 #define SDVO_PIPE_SEL_SHIFT_CHV 24 2650 #define SDVO_PIPE_SEL_MASK_CHV (3 << 24) 2651 #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24) 2652 2653 2654 /* DVO port control */ 2655 #define _DVOA 0x61120 2656 #define DVOA _MMIO(_DVOA) 2657 #define _DVOB 0x61140 2658 #define DVOB _MMIO(_DVOB) 2659 #define _DVOC 0x61160 2660 #define DVOC _MMIO(_DVOC) 2661 #define DVO_ENABLE (1 << 31) 2662 #define DVO_PIPE_SEL_SHIFT 30 2663 #define DVO_PIPE_SEL_MASK (1 << 30) 2664 #define DVO_PIPE_SEL(pipe) ((pipe) << 30) 2665 #define DVO_PIPE_STALL_UNUSED (0 << 28) 2666 #define DVO_PIPE_STALL (1 << 28) 2667 #define DVO_PIPE_STALL_TV (2 << 28) 2668 #define DVO_PIPE_STALL_MASK (3 << 28) 2669 #define DVO_USE_VGA_SYNC (1 << 15) 2670 #define DVO_DATA_ORDER_I740 (0 << 14) 2671 #define DVO_DATA_ORDER_FP (1 << 14) 2672 #define DVO_VSYNC_DISABLE (1 << 11) 2673 #define DVO_HSYNC_DISABLE (1 << 10) 2674 #define DVO_VSYNC_TRISTATE (1 << 9) 2675 #define DVO_HSYNC_TRISTATE (1 << 8) 2676 #define DVO_BORDER_ENABLE (1 << 7) 2677 #define DVO_DATA_ORDER_GBRG (1 << 6) 2678 #define DVO_DATA_ORDER_RGGB (0 << 6) 2679 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) 2680 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) 2681 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4) 2682 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3) 2683 #define DVO_BLANK_ACTIVE_HIGH (1 << 2) 2684 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ 2685 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ 2686 #define DVO_PRESERVE_MASK (0x7 << 24) 2687 #define DVOA_SRCDIM _MMIO(0x61124) 2688 #define DVOB_SRCDIM _MMIO(0x61144) 2689 #define DVOC_SRCDIM _MMIO(0x61164) 2690 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12 2691 #define DVO_SRCDIM_VERTICAL_SHIFT 0 2692 2693 /* LVDS port control */ 2694 #define LVDS _MMIO(0x61180) 2695 /* 2696 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 2697 * the DPLL semantics change when the LVDS is assigned to that pipe. 2698 */ 2699 #define LVDS_PORT_EN (1 << 31) 2700 /* Selects pipe B for LVDS data. Must be set on pre-965. */ 2701 #define LVDS_PIPE_SEL_SHIFT 30 2702 #define LVDS_PIPE_SEL_MASK (1 << 30) 2703 #define LVDS_PIPE_SEL(pipe) ((pipe) << 30) 2704 #define LVDS_PIPE_SEL_SHIFT_CPT 29 2705 #define LVDS_PIPE_SEL_MASK_CPT (3 << 29) 2706 #define LVDS_PIPE_SEL_CPT(pipe) ((pipe) << 29) 2707 /* LVDS dithering flag on 965/g4x platform */ 2708 #define LVDS_ENABLE_DITHER (1 << 25) 2709 /* LVDS sync polarity flags. Set to invert (i.e. negative) */ 2710 #define LVDS_VSYNC_POLARITY (1 << 21) 2711 #define LVDS_HSYNC_POLARITY (1 << 20) 2712 2713 /* Enable border for unscaled (or aspect-scaled) display */ 2714 #define LVDS_BORDER_ENABLE (1 << 15) 2715 /* 2716 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 2717 * pixel. 2718 */ 2719 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) 2720 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) 2721 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 2722 /* 2723 * Controls the A3 data pair, which contains the additional LSBs for 24 bit 2724 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be 2725 * on. 2726 */ 2727 #define LVDS_A3_POWER_MASK (3 << 6) 2728 #define LVDS_A3_POWER_DOWN (0 << 6) 2729 #define LVDS_A3_POWER_UP (3 << 6) 2730 /* 2731 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP 2732 * is set. 2733 */ 2734 #define LVDS_CLKB_POWER_MASK (3 << 4) 2735 #define LVDS_CLKB_POWER_DOWN (0 << 4) 2736 #define LVDS_CLKB_POWER_UP (3 << 4) 2737 /* 2738 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 2739 * setting for whether we are in dual-channel mode. The B3 pair will 2740 * additionally only be powered up when LVDS_A3_POWER_UP is set. 2741 */ 2742 #define LVDS_B0B3_POWER_MASK (3 << 2) 2743 #define LVDS_B0B3_POWER_DOWN (0 << 2) 2744 #define LVDS_B0B3_POWER_UP (3 << 2) 2745 2746 /* Video Data Island Packet control */ 2747 #define VIDEO_DIP_DATA _MMIO(0x61178) 2748 /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC 2749 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte 2750 * of the infoframe structure specified by CEA-861. */ 2751 #define VIDEO_DIP_DATA_SIZE 32 2752 #define VIDEO_DIP_GMP_DATA_SIZE 36 2753 #define VIDEO_DIP_VSC_DATA_SIZE 36 2754 #define VIDEO_DIP_PPS_DATA_SIZE 132 2755 #define VIDEO_DIP_CTL _MMIO(0x61170) 2756 /* Pre HSW: */ 2757 #define VIDEO_DIP_ENABLE (1 << 31) 2758 #define VIDEO_DIP_PORT(port) ((port) << 29) 2759 #define VIDEO_DIP_PORT_MASK (3 << 29) 2760 #define VIDEO_DIP_ENABLE_GCP (1 << 25) /* ilk+ */ 2761 #define VIDEO_DIP_ENABLE_AVI (1 << 21) 2762 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) 2763 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21) /* ilk+ */ 2764 #define VIDEO_DIP_ENABLE_SPD (8 << 21) 2765 #define VIDEO_DIP_SELECT_AVI (0 << 19) 2766 #define VIDEO_DIP_SELECT_VENDOR (1 << 19) 2767 #define VIDEO_DIP_SELECT_GAMUT (2 << 19) 2768 #define VIDEO_DIP_SELECT_SPD (3 << 19) 2769 #define VIDEO_DIP_SELECT_MASK (3 << 19) 2770 #define VIDEO_DIP_FREQ_ONCE (0 << 16) 2771 #define VIDEO_DIP_FREQ_VSYNC (1 << 16) 2772 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) 2773 #define VIDEO_DIP_FREQ_MASK (3 << 16) 2774 /* HSW and later: */ 2775 #define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28) 2776 #define PSR_VSC_BIT_7_SET (1 << 27) 2777 #define VSC_SELECT_MASK (0x3 << 25) 2778 #define VSC_SELECT_SHIFT 25 2779 #define VSC_DIP_HW_HEA_DATA (0 << 25) 2780 #define VSC_DIP_HW_HEA_SW_DATA (1 << 25) 2781 #define VSC_DIP_HW_DATA_SW_HEA (2 << 25) 2782 #define VSC_DIP_SW_HEA_DATA (3 << 25) 2783 #define VDIP_ENABLE_PPS (1 << 24) 2784 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) 2785 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) 2786 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) 2787 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) 2788 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) 2789 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) 2790 2791 /* Panel power sequencing */ 2792 #define PPS_BASE 0x61200 2793 #define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE) 2794 #define PCH_PPS_BASE 0xC7200 2795 2796 #define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->display.pps.mmio_base - \ 2797 PPS_BASE + (reg) + \ 2798 (pps_idx) * 0x100) 2799 2800 #define _PP_STATUS 0x61200 2801 #define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS) 2802 #define PP_ON REG_BIT(31) 2803 /* 2804 * Indicates that all dependencies of the panel are on: 2805 * 2806 * - PLL enabled 2807 * - pipe enabled 2808 * - LVDS/DVOB/DVOC on 2809 */ 2810 #define PP_READY REG_BIT(30) 2811 #define PP_SEQUENCE_MASK REG_GENMASK(29, 28) 2812 #define PP_SEQUENCE_NONE REG_FIELD_PREP(PP_SEQUENCE_MASK, 0) 2813 #define PP_SEQUENCE_POWER_UP REG_FIELD_PREP(PP_SEQUENCE_MASK, 1) 2814 #define PP_SEQUENCE_POWER_DOWN REG_FIELD_PREP(PP_SEQUENCE_MASK, 2) 2815 #define PP_CYCLE_DELAY_ACTIVE REG_BIT(27) 2816 #define PP_SEQUENCE_STATE_MASK REG_GENMASK(3, 0) 2817 #define PP_SEQUENCE_STATE_OFF_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0) 2818 #define PP_SEQUENCE_STATE_OFF_S0_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1) 2819 #define PP_SEQUENCE_STATE_OFF_S0_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2) 2820 #define PP_SEQUENCE_STATE_OFF_S0_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3) 2821 #define PP_SEQUENCE_STATE_ON_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8) 2822 #define PP_SEQUENCE_STATE_ON_S1_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9) 2823 #define PP_SEQUENCE_STATE_ON_S1_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xa) 2824 #define PP_SEQUENCE_STATE_ON_S1_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xb) 2825 #define PP_SEQUENCE_STATE_RESET REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf) 2826 2827 #define _PP_CONTROL 0x61204 2828 #define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL) 2829 #define PANEL_UNLOCK_MASK REG_GENMASK(31, 16) 2830 #define PANEL_UNLOCK_REGS REG_FIELD_PREP(PANEL_UNLOCK_MASK, 0xabcd) 2831 #define BXT_POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4) 2832 #define EDP_FORCE_VDD REG_BIT(3) 2833 #define EDP_BLC_ENABLE REG_BIT(2) 2834 #define PANEL_POWER_RESET REG_BIT(1) 2835 #define PANEL_POWER_ON REG_BIT(0) 2836 2837 #define _PP_ON_DELAYS 0x61208 2838 #define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS) 2839 #define PANEL_PORT_SELECT_MASK REG_GENMASK(31, 30) 2840 #define PANEL_PORT_SELECT_LVDS REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 0) 2841 #define PANEL_PORT_SELECT_DPA REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 1) 2842 #define PANEL_PORT_SELECT_DPC REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 2) 2843 #define PANEL_PORT_SELECT_DPD REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 3) 2844 #define PANEL_PORT_SELECT_VLV(port) REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, port) 2845 #define PANEL_POWER_UP_DELAY_MASK REG_GENMASK(28, 16) 2846 #define PANEL_LIGHT_ON_DELAY_MASK REG_GENMASK(12, 0) 2847 2848 #define _PP_OFF_DELAYS 0x6120C 2849 #define PP_OFF_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_OFF_DELAYS) 2850 #define PANEL_POWER_DOWN_DELAY_MASK REG_GENMASK(28, 16) 2851 #define PANEL_LIGHT_OFF_DELAY_MASK REG_GENMASK(12, 0) 2852 2853 #define _PP_DIVISOR 0x61210 2854 #define PP_DIVISOR(pps_idx) _MMIO_PPS(pps_idx, _PP_DIVISOR) 2855 #define PP_REFERENCE_DIVIDER_MASK REG_GENMASK(31, 8) 2856 #define PANEL_POWER_CYCLE_DELAY_MASK REG_GENMASK(4, 0) 2857 2858 /* Panel fitting */ 2859 #define PFIT_CONTROL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230) 2860 #define PFIT_ENABLE (1 << 31) 2861 #define PFIT_PIPE_MASK (3 << 29) 2862 #define PFIT_PIPE_SHIFT 29 2863 #define PFIT_PIPE(pipe) ((pipe) << 29) 2864 #define VERT_INTERP_DISABLE (0 << 10) 2865 #define VERT_INTERP_BILINEAR (1 << 10) 2866 #define VERT_INTERP_MASK (3 << 10) 2867 #define VERT_AUTO_SCALE (1 << 9) 2868 #define HORIZ_INTERP_DISABLE (0 << 6) 2869 #define HORIZ_INTERP_BILINEAR (1 << 6) 2870 #define HORIZ_INTERP_MASK (3 << 6) 2871 #define HORIZ_AUTO_SCALE (1 << 5) 2872 #define PANEL_8TO6_DITHER_ENABLE (1 << 3) 2873 #define PFIT_FILTER_FUZZY (0 << 24) 2874 #define PFIT_SCALING_AUTO (0 << 26) 2875 #define PFIT_SCALING_PROGRAMMED (1 << 26) 2876 #define PFIT_SCALING_PILLAR (2 << 26) 2877 #define PFIT_SCALING_LETTER (3 << 26) 2878 #define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234) 2879 /* Pre-965 */ 2880 #define PFIT_VERT_SCALE_SHIFT 20 2881 #define PFIT_VERT_SCALE_MASK 0xfff00000 2882 #define PFIT_HORIZ_SCALE_SHIFT 4 2883 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 2884 /* 965+ */ 2885 #define PFIT_VERT_SCALE_SHIFT_965 16 2886 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000 2887 #define PFIT_HORIZ_SCALE_SHIFT_965 0 2888 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff 2889 2890 #define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238) 2891 2892 #define PCH_GTC_CTL _MMIO(0xe7000) 2893 #define PCH_GTC_ENABLE (1 << 31) 2894 2895 /* TV port control */ 2896 #define TV_CTL _MMIO(0x68000) 2897 /* Enables the TV encoder */ 2898 # define TV_ENC_ENABLE (1 << 31) 2899 /* Sources the TV encoder input from pipe B instead of A. */ 2900 # define TV_ENC_PIPE_SEL_SHIFT 30 2901 # define TV_ENC_PIPE_SEL_MASK (1 << 30) 2902 # define TV_ENC_PIPE_SEL(pipe) ((pipe) << 30) 2903 /* Outputs composite video (DAC A only) */ 2904 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28) 2905 /* Outputs SVideo video (DAC B/C) */ 2906 # define TV_ENC_OUTPUT_SVIDEO (1 << 28) 2907 /* Outputs Component video (DAC A/B/C) */ 2908 # define TV_ENC_OUTPUT_COMPONENT (2 << 28) 2909 /* Outputs Composite and SVideo (DAC A/B/C) */ 2910 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) 2911 # define TV_TRILEVEL_SYNC (1 << 21) 2912 /* Enables slow sync generation (945GM only) */ 2913 # define TV_SLOW_SYNC (1 << 20) 2914 /* Selects 4x oversampling for 480i and 576p */ 2915 # define TV_OVERSAMPLE_4X (0 << 18) 2916 /* Selects 2x oversampling for 720p and 1080i */ 2917 # define TV_OVERSAMPLE_2X (1 << 18) 2918 /* Selects no oversampling for 1080p */ 2919 # define TV_OVERSAMPLE_NONE (2 << 18) 2920 /* Selects 8x oversampling */ 2921 # define TV_OVERSAMPLE_8X (3 << 18) 2922 # define TV_OVERSAMPLE_MASK (3 << 18) 2923 /* Selects progressive mode rather than interlaced */ 2924 # define TV_PROGRESSIVE (1 << 17) 2925 /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */ 2926 # define TV_PAL_BURST (1 << 16) 2927 /* Field for setting delay of Y compared to C */ 2928 # define TV_YC_SKEW_MASK (7 << 12) 2929 /* Enables a fix for 480p/576p standard definition modes on the 915GM only */ 2930 # define TV_ENC_SDP_FIX (1 << 11) 2931 /* 2932 * Enables a fix for the 915GM only. 2933 * 2934 * Not sure what it does. 2935 */ 2936 # define TV_ENC_C0_FIX (1 << 10) 2937 /* Bits that must be preserved by software */ 2938 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) 2939 # define TV_FUSE_STATE_MASK (3 << 4) 2940 /* Read-only state that reports all features enabled */ 2941 # define TV_FUSE_STATE_ENABLED (0 << 4) 2942 /* Read-only state that reports that Macrovision is disabled in hardware*/ 2943 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4) 2944 /* Read-only state that reports that TV-out is disabled in hardware. */ 2945 # define TV_FUSE_STATE_DISABLED (2 << 4) 2946 /* Normal operation */ 2947 # define TV_TEST_MODE_NORMAL (0 << 0) 2948 /* Encoder test pattern 1 - combo pattern */ 2949 # define TV_TEST_MODE_PATTERN_1 (1 << 0) 2950 /* Encoder test pattern 2 - full screen vertical 75% color bars */ 2951 # define TV_TEST_MODE_PATTERN_2 (2 << 0) 2952 /* Encoder test pattern 3 - full screen horizontal 75% color bars */ 2953 # define TV_TEST_MODE_PATTERN_3 (3 << 0) 2954 /* Encoder test pattern 4 - random noise */ 2955 # define TV_TEST_MODE_PATTERN_4 (4 << 0) 2956 /* Encoder test pattern 5 - linear color ramps */ 2957 # define TV_TEST_MODE_PATTERN_5 (5 << 0) 2958 /* 2959 * This test mode forces the DACs to 50% of full output. 2960 * 2961 * This is used for load detection in combination with TVDAC_SENSE_MASK 2962 */ 2963 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0) 2964 # define TV_TEST_MODE_MASK (7 << 0) 2965 2966 #define TV_DAC _MMIO(0x68004) 2967 # define TV_DAC_SAVE 0x00ffff00 2968 /* 2969 * Reports that DAC state change logic has reported change (RO). 2970 * 2971 * This gets cleared when TV_DAC_STATE_EN is cleared 2972 */ 2973 # define TVDAC_STATE_CHG (1 << 31) 2974 # define TVDAC_SENSE_MASK (7 << 28) 2975 /* Reports that DAC A voltage is above the detect threshold */ 2976 # define TVDAC_A_SENSE (1 << 30) 2977 /* Reports that DAC B voltage is above the detect threshold */ 2978 # define TVDAC_B_SENSE (1 << 29) 2979 /* Reports that DAC C voltage is above the detect threshold */ 2980 # define TVDAC_C_SENSE (1 << 28) 2981 /* 2982 * Enables DAC state detection logic, for load-based TV detection. 2983 * 2984 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set 2985 * to off, for load detection to work. 2986 */ 2987 # define TVDAC_STATE_CHG_EN (1 << 27) 2988 /* Sets the DAC A sense value to high */ 2989 # define TVDAC_A_SENSE_CTL (1 << 26) 2990 /* Sets the DAC B sense value to high */ 2991 # define TVDAC_B_SENSE_CTL (1 << 25) 2992 /* Sets the DAC C sense value to high */ 2993 # define TVDAC_C_SENSE_CTL (1 << 24) 2994 /* Overrides the ENC_ENABLE and DAC voltage levels */ 2995 # define DAC_CTL_OVERRIDE (1 << 7) 2996 /* Sets the slew rate. Must be preserved in software */ 2997 # define ENC_TVDAC_SLEW_FAST (1 << 6) 2998 # define DAC_A_1_3_V (0 << 4) 2999 # define DAC_A_1_1_V (1 << 4) 3000 # define DAC_A_0_7_V (2 << 4) 3001 # define DAC_A_MASK (3 << 4) 3002 # define DAC_B_1_3_V (0 << 2) 3003 # define DAC_B_1_1_V (1 << 2) 3004 # define DAC_B_0_7_V (2 << 2) 3005 # define DAC_B_MASK (3 << 2) 3006 # define DAC_C_1_3_V (0 << 0) 3007 # define DAC_C_1_1_V (1 << 0) 3008 # define DAC_C_0_7_V (2 << 0) 3009 # define DAC_C_MASK (3 << 0) 3010 3011 /* 3012 * CSC coefficients are stored in a floating point format with 9 bits of 3013 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, 3014 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with 3015 * -1 (0x3) being the only legal negative value. 3016 */ 3017 #define TV_CSC_Y _MMIO(0x68010) 3018 # define TV_RY_MASK 0x07ff0000 3019 # define TV_RY_SHIFT 16 3020 # define TV_GY_MASK 0x00000fff 3021 # define TV_GY_SHIFT 0 3022 3023 #define TV_CSC_Y2 _MMIO(0x68014) 3024 # define TV_BY_MASK 0x07ff0000 3025 # define TV_BY_SHIFT 16 3026 /* 3027 * Y attenuation for component video. 3028 * 3029 * Stored in 1.9 fixed point. 3030 */ 3031 # define TV_AY_MASK 0x000003ff 3032 # define TV_AY_SHIFT 0 3033 3034 #define TV_CSC_U _MMIO(0x68018) 3035 # define TV_RU_MASK 0x07ff0000 3036 # define TV_RU_SHIFT 16 3037 # define TV_GU_MASK 0x000007ff 3038 # define TV_GU_SHIFT 0 3039 3040 #define TV_CSC_U2 _MMIO(0x6801c) 3041 # define TV_BU_MASK 0x07ff0000 3042 # define TV_BU_SHIFT 16 3043 /* 3044 * U attenuation for component video. 3045 * 3046 * Stored in 1.9 fixed point. 3047 */ 3048 # define TV_AU_MASK 0x000003ff 3049 # define TV_AU_SHIFT 0 3050 3051 #define TV_CSC_V _MMIO(0x68020) 3052 # define TV_RV_MASK 0x0fff0000 3053 # define TV_RV_SHIFT 16 3054 # define TV_GV_MASK 0x000007ff 3055 # define TV_GV_SHIFT 0 3056 3057 #define TV_CSC_V2 _MMIO(0x68024) 3058 # define TV_BV_MASK 0x07ff0000 3059 # define TV_BV_SHIFT 16 3060 /* 3061 * V attenuation for component video. 3062 * 3063 * Stored in 1.9 fixed point. 3064 */ 3065 # define TV_AV_MASK 0x000007ff 3066 # define TV_AV_SHIFT 0 3067 3068 #define TV_CLR_KNOBS _MMIO(0x68028) 3069 /* 2s-complement brightness adjustment */ 3070 # define TV_BRIGHTNESS_MASK 0xff000000 3071 # define TV_BRIGHTNESS_SHIFT 24 3072 /* Contrast adjustment, as a 2.6 unsigned floating point number */ 3073 # define TV_CONTRAST_MASK 0x00ff0000 3074 # define TV_CONTRAST_SHIFT 16 3075 /* Saturation adjustment, as a 2.6 unsigned floating point number */ 3076 # define TV_SATURATION_MASK 0x0000ff00 3077 # define TV_SATURATION_SHIFT 8 3078 /* Hue adjustment, as an integer phase angle in degrees */ 3079 # define TV_HUE_MASK 0x000000ff 3080 # define TV_HUE_SHIFT 0 3081 3082 #define TV_CLR_LEVEL _MMIO(0x6802c) 3083 /* Controls the DAC level for black */ 3084 # define TV_BLACK_LEVEL_MASK 0x01ff0000 3085 # define TV_BLACK_LEVEL_SHIFT 16 3086 /* Controls the DAC level for blanking */ 3087 # define TV_BLANK_LEVEL_MASK 0x000001ff 3088 # define TV_BLANK_LEVEL_SHIFT 0 3089 3090 #define TV_H_CTL_1 _MMIO(0x68030) 3091 /* Number of pixels in the hsync. */ 3092 # define TV_HSYNC_END_MASK 0x1fff0000 3093 # define TV_HSYNC_END_SHIFT 16 3094 /* Total number of pixels minus one in the line (display and blanking). */ 3095 # define TV_HTOTAL_MASK 0x00001fff 3096 # define TV_HTOTAL_SHIFT 0 3097 3098 #define TV_H_CTL_2 _MMIO(0x68034) 3099 /* Enables the colorburst (needed for non-component color) */ 3100 # define TV_BURST_ENA (1 << 31) 3101 /* Offset of the colorburst from the start of hsync, in pixels minus one. */ 3102 # define TV_HBURST_START_SHIFT 16 3103 # define TV_HBURST_START_MASK 0x1fff0000 3104 /* Length of the colorburst */ 3105 # define TV_HBURST_LEN_SHIFT 0 3106 # define TV_HBURST_LEN_MASK 0x0001fff 3107 3108 #define TV_H_CTL_3 _MMIO(0x68038) 3109 /* End of hblank, measured in pixels minus one from start of hsync */ 3110 # define TV_HBLANK_END_SHIFT 16 3111 # define TV_HBLANK_END_MASK 0x1fff0000 3112 /* Start of hblank, measured in pixels minus one from start of hsync */ 3113 # define TV_HBLANK_START_SHIFT 0 3114 # define TV_HBLANK_START_MASK 0x0001fff 3115 3116 #define TV_V_CTL_1 _MMIO(0x6803c) 3117 /* XXX */ 3118 # define TV_NBR_END_SHIFT 16 3119 # define TV_NBR_END_MASK 0x07ff0000 3120 /* XXX */ 3121 # define TV_VI_END_F1_SHIFT 8 3122 # define TV_VI_END_F1_MASK 0x00003f00 3123 /* XXX */ 3124 # define TV_VI_END_F2_SHIFT 0 3125 # define TV_VI_END_F2_MASK 0x0000003f 3126 3127 #define TV_V_CTL_2 _MMIO(0x68040) 3128 /* Length of vsync, in half lines */ 3129 # define TV_VSYNC_LEN_MASK 0x07ff0000 3130 # define TV_VSYNC_LEN_SHIFT 16 3131 /* Offset of the start of vsync in field 1, measured in one less than the 3132 * number of half lines. 3133 */ 3134 # define TV_VSYNC_START_F1_MASK 0x00007f00 3135 # define TV_VSYNC_START_F1_SHIFT 8 3136 /* 3137 * Offset of the start of vsync in field 2, measured in one less than the 3138 * number of half lines. 3139 */ 3140 # define TV_VSYNC_START_F2_MASK 0x0000007f 3141 # define TV_VSYNC_START_F2_SHIFT 0 3142 3143 #define TV_V_CTL_3 _MMIO(0x68044) 3144 /* Enables generation of the equalization signal */ 3145 # define TV_EQUAL_ENA (1 << 31) 3146 /* Length of vsync, in half lines */ 3147 # define TV_VEQ_LEN_MASK 0x007f0000 3148 # define TV_VEQ_LEN_SHIFT 16 3149 /* Offset of the start of equalization in field 1, measured in one less than 3150 * the number of half lines. 3151 */ 3152 # define TV_VEQ_START_F1_MASK 0x0007f00 3153 # define TV_VEQ_START_F1_SHIFT 8 3154 /* 3155 * Offset of the start of equalization in field 2, measured in one less than 3156 * the number of half lines. 3157 */ 3158 # define TV_VEQ_START_F2_MASK 0x000007f 3159 # define TV_VEQ_START_F2_SHIFT 0 3160 3161 #define TV_V_CTL_4 _MMIO(0x68048) 3162 /* 3163 * Offset to start of vertical colorburst, measured in one less than the 3164 * number of lines from vertical start. 3165 */ 3166 # define TV_VBURST_START_F1_MASK 0x003f0000 3167 # define TV_VBURST_START_F1_SHIFT 16 3168 /* 3169 * Offset to the end of vertical colorburst, measured in one less than the 3170 * number of lines from the start of NBR. 3171 */ 3172 # define TV_VBURST_END_F1_MASK 0x000000ff 3173 # define TV_VBURST_END_F1_SHIFT 0 3174 3175 #define TV_V_CTL_5 _MMIO(0x6804c) 3176 /* 3177 * Offset to start of vertical colorburst, measured in one less than the 3178 * number of lines from vertical start. 3179 */ 3180 # define TV_VBURST_START_F2_MASK 0x003f0000 3181 # define TV_VBURST_START_F2_SHIFT 16 3182 /* 3183 * Offset to the end of vertical colorburst, measured in one less than the 3184 * number of lines from the start of NBR. 3185 */ 3186 # define TV_VBURST_END_F2_MASK 0x000000ff 3187 # define TV_VBURST_END_F2_SHIFT 0 3188 3189 #define TV_V_CTL_6 _MMIO(0x68050) 3190 /* 3191 * Offset to start of vertical colorburst, measured in one less than the 3192 * number of lines from vertical start. 3193 */ 3194 # define TV_VBURST_START_F3_MASK 0x003f0000 3195 # define TV_VBURST_START_F3_SHIFT 16 3196 /* 3197 * Offset to the end of vertical colorburst, measured in one less than the 3198 * number of lines from the start of NBR. 3199 */ 3200 # define TV_VBURST_END_F3_MASK 0x000000ff 3201 # define TV_VBURST_END_F3_SHIFT 0 3202 3203 #define TV_V_CTL_7 _MMIO(0x68054) 3204 /* 3205 * Offset to start of vertical colorburst, measured in one less than the 3206 * number of lines from vertical start. 3207 */ 3208 # define TV_VBURST_START_F4_MASK 0x003f0000 3209 # define TV_VBURST_START_F4_SHIFT 16 3210 /* 3211 * Offset to the end of vertical colorburst, measured in one less than the 3212 * number of lines from the start of NBR. 3213 */ 3214 # define TV_VBURST_END_F4_MASK 0x000000ff 3215 # define TV_VBURST_END_F4_SHIFT 0 3216 3217 #define TV_SC_CTL_1 _MMIO(0x68060) 3218 /* Turns on the first subcarrier phase generation DDA */ 3219 # define TV_SC_DDA1_EN (1 << 31) 3220 /* Turns on the first subcarrier phase generation DDA */ 3221 # define TV_SC_DDA2_EN (1 << 30) 3222 /* Turns on the first subcarrier phase generation DDA */ 3223 # define TV_SC_DDA3_EN (1 << 29) 3224 /* Sets the subcarrier DDA to reset frequency every other field */ 3225 # define TV_SC_RESET_EVERY_2 (0 << 24) 3226 /* Sets the subcarrier DDA to reset frequency every fourth field */ 3227 # define TV_SC_RESET_EVERY_4 (1 << 24) 3228 /* Sets the subcarrier DDA to reset frequency every eighth field */ 3229 # define TV_SC_RESET_EVERY_8 (2 << 24) 3230 /* Sets the subcarrier DDA to never reset the frequency */ 3231 # define TV_SC_RESET_NEVER (3 << 24) 3232 /* Sets the peak amplitude of the colorburst.*/ 3233 # define TV_BURST_LEVEL_MASK 0x00ff0000 3234 # define TV_BURST_LEVEL_SHIFT 16 3235 /* Sets the increment of the first subcarrier phase generation DDA */ 3236 # define TV_SCDDA1_INC_MASK 0x00000fff 3237 # define TV_SCDDA1_INC_SHIFT 0 3238 3239 #define TV_SC_CTL_2 _MMIO(0x68064) 3240 /* Sets the rollover for the second subcarrier phase generation DDA */ 3241 # define TV_SCDDA2_SIZE_MASK 0x7fff0000 3242 # define TV_SCDDA2_SIZE_SHIFT 16 3243 /* Sets the increent of the second subcarrier phase generation DDA */ 3244 # define TV_SCDDA2_INC_MASK 0x00007fff 3245 # define TV_SCDDA2_INC_SHIFT 0 3246 3247 #define TV_SC_CTL_3 _MMIO(0x68068) 3248 /* Sets the rollover for the third subcarrier phase generation DDA */ 3249 # define TV_SCDDA3_SIZE_MASK 0x7fff0000 3250 # define TV_SCDDA3_SIZE_SHIFT 16 3251 /* Sets the increent of the third subcarrier phase generation DDA */ 3252 # define TV_SCDDA3_INC_MASK 0x00007fff 3253 # define TV_SCDDA3_INC_SHIFT 0 3254 3255 #define TV_WIN_POS _MMIO(0x68070) 3256 /* X coordinate of the display from the start of horizontal active */ 3257 # define TV_XPOS_MASK 0x1fff0000 3258 # define TV_XPOS_SHIFT 16 3259 /* Y coordinate of the display from the start of vertical active (NBR) */ 3260 # define TV_YPOS_MASK 0x00000fff 3261 # define TV_YPOS_SHIFT 0 3262 3263 #define TV_WIN_SIZE _MMIO(0x68074) 3264 /* Horizontal size of the display window, measured in pixels*/ 3265 # define TV_XSIZE_MASK 0x1fff0000 3266 # define TV_XSIZE_SHIFT 16 3267 /* 3268 * Vertical size of the display window, measured in pixels. 3269 * 3270 * Must be even for interlaced modes. 3271 */ 3272 # define TV_YSIZE_MASK 0x00000fff 3273 # define TV_YSIZE_SHIFT 0 3274 3275 #define TV_FILTER_CTL_1 _MMIO(0x68080) 3276 /* 3277 * Enables automatic scaling calculation. 3278 * 3279 * If set, the rest of the registers are ignored, and the calculated values can 3280 * be read back from the register. 3281 */ 3282 # define TV_AUTO_SCALE (1 << 31) 3283 /* 3284 * Disables the vertical filter. 3285 * 3286 * This is required on modes more than 1024 pixels wide */ 3287 # define TV_V_FILTER_BYPASS (1 << 29) 3288 /* Enables adaptive vertical filtering */ 3289 # define TV_VADAPT (1 << 28) 3290 # define TV_VADAPT_MODE_MASK (3 << 26) 3291 /* Selects the least adaptive vertical filtering mode */ 3292 # define TV_VADAPT_MODE_LEAST (0 << 26) 3293 /* Selects the moderately adaptive vertical filtering mode */ 3294 # define TV_VADAPT_MODE_MODERATE (1 << 26) 3295 /* Selects the most adaptive vertical filtering mode */ 3296 # define TV_VADAPT_MODE_MOST (3 << 26) 3297 /* 3298 * Sets the horizontal scaling factor. 3299 * 3300 * This should be the fractional part of the horizontal scaling factor divided 3301 * by the oversampling rate. TV_HSCALE should be less than 1, and set to: 3302 * 3303 * (src width - 1) / ((oversample * dest width) - 1) 3304 */ 3305 # define TV_HSCALE_FRAC_MASK 0x00003fff 3306 # define TV_HSCALE_FRAC_SHIFT 0 3307 3308 #define TV_FILTER_CTL_2 _MMIO(0x68084) 3309 /* 3310 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 3311 * 3312 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) 3313 */ 3314 # define TV_VSCALE_INT_MASK 0x00038000 3315 # define TV_VSCALE_INT_SHIFT 15 3316 /* 3317 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 3318 * 3319 * \sa TV_VSCALE_INT_MASK 3320 */ 3321 # define TV_VSCALE_FRAC_MASK 0x00007fff 3322 # define TV_VSCALE_FRAC_SHIFT 0 3323 3324 #define TV_FILTER_CTL_3 _MMIO(0x68088) 3325 /* 3326 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 3327 * 3328 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) 3329 * 3330 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 3331 */ 3332 # define TV_VSCALE_IP_INT_MASK 0x00038000 3333 # define TV_VSCALE_IP_INT_SHIFT 15 3334 /* 3335 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 3336 * 3337 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 3338 * 3339 * \sa TV_VSCALE_IP_INT_MASK 3340 */ 3341 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff 3342 # define TV_VSCALE_IP_FRAC_SHIFT 0 3343 3344 #define TV_CC_CONTROL _MMIO(0x68090) 3345 # define TV_CC_ENABLE (1 << 31) 3346 /* 3347 * Specifies which field to send the CC data in. 3348 * 3349 * CC data is usually sent in field 0. 3350 */ 3351 # define TV_CC_FID_MASK (1 << 27) 3352 # define TV_CC_FID_SHIFT 27 3353 /* Sets the horizontal position of the CC data. Usually 135. */ 3354 # define TV_CC_HOFF_MASK 0x03ff0000 3355 # define TV_CC_HOFF_SHIFT 16 3356 /* Sets the vertical position of the CC data. Usually 21 */ 3357 # define TV_CC_LINE_MASK 0x0000003f 3358 # define TV_CC_LINE_SHIFT 0 3359 3360 #define TV_CC_DATA _MMIO(0x68094) 3361 # define TV_CC_RDY (1 << 31) 3362 /* Second word of CC data to be transmitted. */ 3363 # define TV_CC_DATA_2_MASK 0x007f0000 3364 # define TV_CC_DATA_2_SHIFT 16 3365 /* First word of CC data to be transmitted. */ 3366 # define TV_CC_DATA_1_MASK 0x0000007f 3367 # define TV_CC_DATA_1_SHIFT 0 3368 3369 #define TV_H_LUMA(i) _MMIO(0x68100 + (i) * 4) /* 60 registers */ 3370 #define TV_H_CHROMA(i) _MMIO(0x68200 + (i) * 4) /* 60 registers */ 3371 #define TV_V_LUMA(i) _MMIO(0x68300 + (i) * 4) /* 43 registers */ 3372 #define TV_V_CHROMA(i) _MMIO(0x68400 + (i) * 4) /* 43 registers */ 3373 3374 /* Display Port */ 3375 #define DP_A _MMIO(0x64000) /* eDP */ 3376 #define DP_B _MMIO(0x64100) 3377 #define DP_C _MMIO(0x64200) 3378 #define DP_D _MMIO(0x64300) 3379 3380 #define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100) 3381 #define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200) 3382 #define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300) 3383 3384 #define DP_PORT_EN (1 << 31) 3385 #define DP_PIPE_SEL_SHIFT 30 3386 #define DP_PIPE_SEL_MASK (1 << 30) 3387 #define DP_PIPE_SEL(pipe) ((pipe) << 30) 3388 #define DP_PIPE_SEL_SHIFT_IVB 29 3389 #define DP_PIPE_SEL_MASK_IVB (3 << 29) 3390 #define DP_PIPE_SEL_IVB(pipe) ((pipe) << 29) 3391 #define DP_PIPE_SEL_SHIFT_CHV 16 3392 #define DP_PIPE_SEL_MASK_CHV (3 << 16) 3393 #define DP_PIPE_SEL_CHV(pipe) ((pipe) << 16) 3394 3395 /* Link training mode - select a suitable mode for each stage */ 3396 #define DP_LINK_TRAIN_PAT_1 (0 << 28) 3397 #define DP_LINK_TRAIN_PAT_2 (1 << 28) 3398 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) 3399 #define DP_LINK_TRAIN_OFF (3 << 28) 3400 #define DP_LINK_TRAIN_MASK (3 << 28) 3401 #define DP_LINK_TRAIN_SHIFT 28 3402 3403 /* CPT Link training mode */ 3404 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) 3405 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) 3406 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) 3407 #define DP_LINK_TRAIN_OFF_CPT (3 << 8) 3408 #define DP_LINK_TRAIN_MASK_CPT (7 << 8) 3409 #define DP_LINK_TRAIN_SHIFT_CPT 8 3410 3411 /* Signal voltages. These are mostly controlled by the other end */ 3412 #define DP_VOLTAGE_0_4 (0 << 25) 3413 #define DP_VOLTAGE_0_6 (1 << 25) 3414 #define DP_VOLTAGE_0_8 (2 << 25) 3415 #define DP_VOLTAGE_1_2 (3 << 25) 3416 #define DP_VOLTAGE_MASK (7 << 25) 3417 #define DP_VOLTAGE_SHIFT 25 3418 3419 /* Signal pre-emphasis levels, like voltages, the other end tells us what 3420 * they want 3421 */ 3422 #define DP_PRE_EMPHASIS_0 (0 << 22) 3423 #define DP_PRE_EMPHASIS_3_5 (1 << 22) 3424 #define DP_PRE_EMPHASIS_6 (2 << 22) 3425 #define DP_PRE_EMPHASIS_9_5 (3 << 22) 3426 #define DP_PRE_EMPHASIS_MASK (7 << 22) 3427 #define DP_PRE_EMPHASIS_SHIFT 22 3428 3429 /* How many wires to use. I guess 3 was too hard */ 3430 #define DP_PORT_WIDTH(width) (((width) - 1) << 19) 3431 #define DP_PORT_WIDTH_MASK (7 << 19) 3432 #define DP_PORT_WIDTH_SHIFT 19 3433 3434 /* Mystic DPCD version 1.1 special mode */ 3435 #define DP_ENHANCED_FRAMING (1 << 18) 3436 3437 /* eDP */ 3438 #define DP_PLL_FREQ_270MHZ (0 << 16) 3439 #define DP_PLL_FREQ_162MHZ (1 << 16) 3440 #define DP_PLL_FREQ_MASK (3 << 16) 3441 3442 /* locked once port is enabled */ 3443 #define DP_PORT_REVERSAL (1 << 15) 3444 3445 /* eDP */ 3446 #define DP_PLL_ENABLE (1 << 14) 3447 3448 /* sends the clock on lane 15 of the PEG for debug */ 3449 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) 3450 3451 #define DP_SCRAMBLING_DISABLE (1 << 12) 3452 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) 3453 3454 /* limit RGB values to avoid confusing TVs */ 3455 #define DP_COLOR_RANGE_16_235 (1 << 8) 3456 3457 /* Turn on the audio link */ 3458 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) 3459 3460 /* vs and hs sync polarity */ 3461 #define DP_SYNC_VS_HIGH (1 << 4) 3462 #define DP_SYNC_HS_HIGH (1 << 3) 3463 3464 /* A fantasy */ 3465 #define DP_DETECTED (1 << 2) 3466 3467 /* The aux channel provides a way to talk to the 3468 * signal sink for DDC etc. Max packet size supported 3469 * is 20 bytes in each direction, hence the 5 fixed 3470 * data registers 3471 */ 3472 #define _DPA_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64010) 3473 #define _DPA_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64014) 3474 3475 #define _DPB_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64110) 3476 #define _DPB_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64114) 3477 3478 #define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL) 3479 #define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ 3480 3481 #define _XELPDP_USBC1_AUX_CH_CTL 0x16F210 3482 #define _XELPDP_USBC2_AUX_CH_CTL 0x16F410 3483 #define _XELPDP_USBC3_AUX_CH_CTL 0x16F610 3484 #define _XELPDP_USBC4_AUX_CH_CTL 0x16F810 3485 3486 #define XELPDP_DP_AUX_CH_CTL(aux_ch) _MMIO(_PICK(aux_ch, \ 3487 _DPA_AUX_CH_CTL, \ 3488 _DPB_AUX_CH_CTL, \ 3489 0, /* port/aux_ch C is non-existent */ \ 3490 _XELPDP_USBC1_AUX_CH_CTL, \ 3491 _XELPDP_USBC2_AUX_CH_CTL, \ 3492 _XELPDP_USBC3_AUX_CH_CTL, \ 3493 _XELPDP_USBC4_AUX_CH_CTL)) 3494 3495 #define _XELPDP_USBC1_AUX_CH_DATA1 0x16F214 3496 #define _XELPDP_USBC2_AUX_CH_DATA1 0x16F414 3497 #define _XELPDP_USBC3_AUX_CH_DATA1 0x16F614 3498 #define _XELPDP_USBC4_AUX_CH_DATA1 0x16F814 3499 3500 #define XELPDP_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PICK(aux_ch, \ 3501 _DPA_AUX_CH_DATA1, \ 3502 _DPB_AUX_CH_DATA1, \ 3503 0, /* port/aux_ch C is non-existent */ \ 3504 _XELPDP_USBC1_AUX_CH_DATA1, \ 3505 _XELPDP_USBC2_AUX_CH_DATA1, \ 3506 _XELPDP_USBC3_AUX_CH_DATA1, \ 3507 _XELPDP_USBC4_AUX_CH_DATA1) + (i) * 4) 3508 3509 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) 3510 #define DP_AUX_CH_CTL_DONE (1 << 30) 3511 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) 3512 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) 3513 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) 3514 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) 3515 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) 3516 #define DP_AUX_CH_CTL_TIME_OUT_MAX (3 << 26) /* Varies per platform */ 3517 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) 3518 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) 3519 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) 3520 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 3521 #define XELPDP_DP_AUX_CH_CTL_POWER_REQUEST REG_BIT(19) 3522 #define XELPDP_DP_AUX_CH_CTL_POWER_STATUS REG_BIT(18) 3523 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) 3524 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 3525 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) 3526 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) 3527 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) 3528 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) 3529 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) 3530 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) 3531 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 3532 #define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14) 3533 #define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13) 3534 #define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12) 3535 #define DP_AUX_CH_CTL_TBT_IO (1 << 11) 3536 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5) 3537 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5) 3538 #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1) 3539 3540 /* 3541 * Computing GMCH M and N values for the Display Port link 3542 * 3543 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes 3544 * 3545 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) 3546 * 3547 * The GMCH value is used internally 3548 * 3549 * bytes_per_pixel is the number of bytes coming out of the plane, 3550 * which is after the LUTs, so we want the bytes for our color format. 3551 * For our current usage, this is always 3, one byte for R, G and B. 3552 */ 3553 #define _PIPEA_DATA_M_G4X 0x70050 3554 #define _PIPEB_DATA_M_G4X 0x71050 3555 3556 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ 3557 #define TU_SIZE_MASK REG_GENMASK(30, 25) 3558 #define TU_SIZE(x) REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /* default size 64 */ 3559 3560 #define DATA_LINK_M_N_MASK REG_GENMASK(23, 0) 3561 #define DATA_LINK_N_MAX (0x800000) 3562 3563 #define _PIPEA_DATA_N_G4X 0x70054 3564 #define _PIPEB_DATA_N_G4X 0x71054 3565 3566 /* 3567 * Computing Link M and N values for the Display Port link 3568 * 3569 * Link M / N = pixel_clock / ls_clk 3570 * 3571 * (the DP spec calls pixel_clock the 'strm_clk') 3572 * 3573 * The Link value is transmitted in the Main Stream 3574 * Attributes and VB-ID. 3575 */ 3576 3577 #define _PIPEA_LINK_M_G4X 0x70060 3578 #define _PIPEB_LINK_M_G4X 0x71060 3579 #define _PIPEA_LINK_N_G4X 0x70064 3580 #define _PIPEB_LINK_N_G4X 0x71064 3581 3582 #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X) 3583 #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X) 3584 #define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X) 3585 #define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X) 3586 3587 /* Display & cursor control */ 3588 3589 /* Pipe A */ 3590 #define _PIPEADSL 0x70000 3591 #define PIPEDSL_CURR_FIELD REG_BIT(31) /* ctg+ */ 3592 #define PIPEDSL_LINE_MASK REG_GENMASK(19, 0) 3593 #define _PIPEACONF 0x70008 3594 #define PIPECONF_ENABLE REG_BIT(31) 3595 #define PIPECONF_DOUBLE_WIDE REG_BIT(30) /* pre-i965 */ 3596 #define PIPECONF_STATE_ENABLE REG_BIT(30) /* i965+ */ 3597 #define PIPECONF_DSI_PLL_LOCKED REG_BIT(29) /* vlv & pipe A only */ 3598 #define PIPECONF_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* pre-hsw */ 3599 #define PIPECONF_FRAME_START_DELAY(x) REG_FIELD_PREP(PIPECONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */ 3600 #define PIPECONF_PIPE_LOCKED REG_BIT(25) 3601 #define PIPECONF_FORCE_BORDER REG_BIT(25) 3602 #define PIPECONF_GAMMA_MODE_MASK_I9XX REG_BIT(24) /* gmch */ 3603 #define PIPECONF_GAMMA_MODE_MASK_ILK REG_GENMASK(25, 24) /* ilk-ivb */ 3604 #define PIPECONF_GAMMA_MODE_8BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK, 0) 3605 #define PIPECONF_GAMMA_MODE_10BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK, 1) 3606 #define PIPECONF_GAMMA_MODE_12BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */ 3607 #define PIPECONF_GAMMA_MODE_SPLIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */ 3608 #define PIPECONF_GAMMA_MODE(x) REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, (x)) /* pass in GAMMA_MODE_MODE_* */ 3609 #define PIPECONF_INTERLACE_MASK REG_GENMASK(23, 21) /* gen3+ */ 3610 #define PIPECONF_INTERLACE_PROGRESSIVE REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 0) 3611 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 4) /* gen4 only */ 3612 #define PIPECONF_INTERLACE_W_SYNC_SHIFT REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 5) /* gen4 only */ 3613 #define PIPECONF_INTERLACE_W_FIELD_INDICATION REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 6) 3614 #define PIPECONF_INTERLACE_FIELD_0_ONLY REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 7) /* gen3 only */ 3615 /* 3616 * ilk+: PF/D=progressive fetch/display, IF/D=interlaced fetch/display, 3617 * DBL=power saving pixel doubling, PF-ID* requires panel fitter 3618 */ 3619 #define PIPECONF_INTERLACE_MASK_ILK REG_GENMASK(23, 21) /* ilk+ */ 3620 #define PIPECONF_INTERLACE_MASK_HSW REG_GENMASK(22, 21) /* hsw+ */ 3621 #define PIPECONF_INTERLACE_PF_PD_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 0) 3622 #define PIPECONF_INTERLACE_PF_ID_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 1) 3623 #define PIPECONF_INTERLACE_IF_ID_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 3) 3624 #define PIPECONF_INTERLACE_IF_ID_DBL_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */ 3625 #define PIPECONF_INTERLACE_PF_ID_DBL_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */ 3626 #define PIPECONF_REFRESH_RATE_ALT_ILK REG_BIT(20) 3627 #define PIPECONF_MSA_TIMING_DELAY_MASK REG_GENMASK(19, 18) /* ilk/snb/ivb */ 3628 #define PIPECONF_MSA_TIMING_DELAY(x) REG_FIELD_PREP(PIPECONF_MSA_TIMING_DELAY_MASK, (x)) 3629 #define PIPECONF_CXSR_DOWNCLOCK REG_BIT(16) 3630 #define PIPECONF_REFRESH_RATE_ALT_VLV REG_BIT(14) 3631 #define PIPECONF_COLOR_RANGE_SELECT REG_BIT(13) 3632 #define PIPECONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /* ilk-ivb */ 3633 #define PIPECONF_OUTPUT_COLORSPACE_RGB REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */ 3634 #define PIPECONF_OUTPUT_COLORSPACE_YUV601 REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */ 3635 #define PIPECONF_OUTPUT_COLORSPACE_YUV709 REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */ 3636 #define PIPECONF_OUTPUT_COLORSPACE_YUV_HSW REG_BIT(11) /* hsw only */ 3637 #define PIPECONF_BPC_MASK REG_GENMASK(7, 5) /* ctg-ivb */ 3638 #define PIPECONF_BPC_8 REG_FIELD_PREP(PIPECONF_BPC_MASK, 0) 3639 #define PIPECONF_BPC_10 REG_FIELD_PREP(PIPECONF_BPC_MASK, 1) 3640 #define PIPECONF_BPC_6 REG_FIELD_PREP(PIPECONF_BPC_MASK, 2) 3641 #define PIPECONF_BPC_12 REG_FIELD_PREP(PIPECONF_BPC_MASK, 3) 3642 #define PIPECONF_DITHER_EN REG_BIT(4) 3643 #define PIPECONF_DITHER_TYPE_MASK REG_GENMASK(3, 2) 3644 #define PIPECONF_DITHER_TYPE_SP REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 0) 3645 #define PIPECONF_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 1) 3646 #define PIPECONF_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 2) 3647 #define PIPECONF_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 3) 3648 #define _PIPEASTAT 0x70024 3649 #define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31) 3650 #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30) 3651 #define PIPE_CRC_ERROR_ENABLE (1UL << 29) 3652 #define PIPE_CRC_DONE_ENABLE (1UL << 28) 3653 #define PERF_COUNTER2_INTERRUPT_EN (1UL << 27) 3654 #define PIPE_GMBUS_EVENT_ENABLE (1UL << 27) 3655 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL << 26) 3656 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26) 3657 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25) 3658 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24) 3659 #define PIPE_DPST_EVENT_ENABLE (1UL << 23) 3660 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22) 3661 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22) 3662 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21) 3663 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL << 20) 3664 #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL << 19) 3665 #define PERF_COUNTER_INTERRUPT_EN (1UL << 19) 3666 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */ 3667 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18) /* 965 or later */ 3668 #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL << 17) 3669 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17) 3670 #define PIPEA_HBLANK_INT_EN_VLV (1UL << 16) 3671 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL << 16) 3672 #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL << 15) 3673 #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL << 14) 3674 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL << 13) 3675 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL << 12) 3676 #define PERF_COUNTER2_INTERRUPT_STATUS (1UL << 11) 3677 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL << 11) 3678 #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL << 10) 3679 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10) 3680 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9) 3681 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8) 3682 #define PIPE_DPST_EVENT_STATUS (1UL << 7) 3683 #define PIPE_A_PSR_STATUS_VLV (1UL << 6) 3684 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6) 3685 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5) 3686 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL << 4) 3687 #define PIPE_B_PSR_STATUS_VLV (1UL << 3) 3688 #define PERF_COUNTER_INTERRUPT_STATUS (1UL << 3) 3689 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */ 3690 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2) /* 965 or later */ 3691 #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL << 1) 3692 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1) 3693 #define PIPE_HBLANK_INT_STATUS (1UL << 0) 3694 #define PIPE_OVERLAY_UPDATED_STATUS (1UL << 0) 3695 3696 #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000 3697 #define PIPESTAT_INT_STATUS_MASK 0x0000ffff 3698 3699 #define PIPE_A_OFFSET 0x70000 3700 #define PIPE_B_OFFSET 0x71000 3701 #define PIPE_C_OFFSET 0x72000 3702 #define PIPE_D_OFFSET 0x73000 3703 #define CHV_PIPE_C_OFFSET 0x74000 3704 /* 3705 * There's actually no pipe EDP. Some pipe registers have 3706 * simply shifted from the pipe to the transcoder, while 3707 * keeping their original offset. Thus we need PIPE_EDP_OFFSET 3708 * to access such registers in transcoder EDP. 3709 */ 3710 #define PIPE_EDP_OFFSET 0x7f000 3711 3712 /* ICL DSI 0 and 1 */ 3713 #define PIPE_DSI0_OFFSET 0x7b000 3714 #define PIPE_DSI1_OFFSET 0x7b800 3715 3716 #define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF) 3717 #define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL) 3718 #define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH) 3719 #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL) 3720 #define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT) 3721 3722 #define _PIPEAGCMAX 0x70010 3723 #define _PIPEBGCMAX 0x71010 3724 #define PIPEGCMAX(pipe, i) _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4) 3725 3726 #define _PIPE_ARB_CTL_A 0x70028 /* icl+ */ 3727 #define PIPE_ARB_CTL(pipe) _MMIO_PIPE2(pipe, _PIPE_ARB_CTL_A) 3728 #define PIPE_ARB_USE_PROG_SLOTS REG_BIT(13) 3729 3730 #define _PIPE_MISC_A 0x70030 3731 #define _PIPE_MISC_B 0x71030 3732 #define PIPEMISC_YUV420_ENABLE REG_BIT(27) /* glk+ */ 3733 #define PIPEMISC_YUV420_MODE_FULL_BLEND REG_BIT(26) /* glk+ */ 3734 #define PIPEMISC_HDR_MODE_PRECISION REG_BIT(23) /* icl+ */ 3735 #define PIPEMISC_OUTPUT_COLORSPACE_YUV REG_BIT(11) 3736 #define PIPEMISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */ 3737 /* 3738 * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with 3739 * valid values of: 6, 8, 10 BPC. 3740 * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of: 3741 * 6, 8, 10, 12 BPC. 3742 */ 3743 #define PIPEMISC_BPC_MASK REG_GENMASK(7, 5) 3744 #define PIPEMISC_BPC_8 REG_FIELD_PREP(PIPEMISC_BPC_MASK, 0) 3745 #define PIPEMISC_BPC_10 REG_FIELD_PREP(PIPEMISC_BPC_MASK, 1) 3746 #define PIPEMISC_BPC_6 REG_FIELD_PREP(PIPEMISC_BPC_MASK, 2) 3747 #define PIPEMISC_BPC_12_ADLP REG_FIELD_PREP(PIPEMISC_BPC_MASK, 4) /* adlp+ */ 3748 #define PIPEMISC_DITHER_ENABLE REG_BIT(4) 3749 #define PIPEMISC_DITHER_TYPE_MASK REG_GENMASK(3, 2) 3750 #define PIPEMISC_DITHER_TYPE_SP REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 0) 3751 #define PIPEMISC_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 1) 3752 #define PIPEMISC_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 2) 3753 #define PIPEMISC_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 3) 3754 #define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A) 3755 3756 #define _PIPE_MISC2_A 0x7002C 3757 #define _PIPE_MISC2_B 0x7102C 3758 #define PIPE_MISC2_BUBBLE_COUNTER_MASK REG_GENMASK(31, 24) 3759 #define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 80) 3760 #define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 20) 3761 #define PIPE_MISC2(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC2_A) 3762 3763 /* Skylake+ pipe bottom (background) color */ 3764 #define _SKL_BOTTOM_COLOR_A 0x70034 3765 #define SKL_BOTTOM_COLOR_GAMMA_ENABLE REG_BIT(31) 3766 #define SKL_BOTTOM_COLOR_CSC_ENABLE REG_BIT(30) 3767 #define SKL_BOTTOM_COLOR(pipe) _MMIO_PIPE2(pipe, _SKL_BOTTOM_COLOR_A) 3768 3769 #define _ICL_PIPE_A_STATUS 0x70058 3770 #define ICL_PIPESTATUS(pipe) _MMIO_PIPE2(pipe, _ICL_PIPE_A_STATUS) 3771 #define PIPE_STATUS_UNDERRUN REG_BIT(31) 3772 #define PIPE_STATUS_SOFT_UNDERRUN_XELPD REG_BIT(28) 3773 #define PIPE_STATUS_HARD_UNDERRUN_XELPD REG_BIT(27) 3774 #define PIPE_STATUS_PORT_UNDERRUN_XELPD REG_BIT(26) 3775 3776 #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028) 3777 #define PIPEB_LINE_COMPARE_INT_EN REG_BIT(29) 3778 #define PIPEB_HLINE_INT_EN REG_BIT(28) 3779 #define PIPEB_VBLANK_INT_EN REG_BIT(27) 3780 #define SPRITED_FLIP_DONE_INT_EN REG_BIT(26) 3781 #define SPRITEC_FLIP_DONE_INT_EN REG_BIT(25) 3782 #define PLANEB_FLIP_DONE_INT_EN REG_BIT(24) 3783 #define PIPE_PSR_INT_EN REG_BIT(22) 3784 #define PIPEA_LINE_COMPARE_INT_EN REG_BIT(21) 3785 #define PIPEA_HLINE_INT_EN REG_BIT(20) 3786 #define PIPEA_VBLANK_INT_EN REG_BIT(19) 3787 #define SPRITEB_FLIP_DONE_INT_EN REG_BIT(18) 3788 #define SPRITEA_FLIP_DONE_INT_EN REG_BIT(17) 3789 #define PLANEA_FLIPDONE_INT_EN REG_BIT(16) 3790 #define PIPEC_LINE_COMPARE_INT_EN REG_BIT(13) 3791 #define PIPEC_HLINE_INT_EN REG_BIT(12) 3792 #define PIPEC_VBLANK_INT_EN REG_BIT(11) 3793 #define SPRITEF_FLIPDONE_INT_EN REG_BIT(10) 3794 #define SPRITEE_FLIPDONE_INT_EN REG_BIT(9) 3795 #define PLANEC_FLIPDONE_INT_EN REG_BIT(8) 3796 3797 #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */ 3798 #define DPINVGTT_EN_MASK_CHV REG_GENMASK(27, 16) 3799 #define DPINVGTT_EN_MASK_VLV REG_GENMASK(23, 16) 3800 #define SPRITEF_INVALID_GTT_INT_EN REG_BIT(27) 3801 #define SPRITEE_INVALID_GTT_INT_EN REG_BIT(26) 3802 #define PLANEC_INVALID_GTT_INT_EN REG_BIT(25) 3803 #define CURSORC_INVALID_GTT_INT_EN REG_BIT(24) 3804 #define CURSORB_INVALID_GTT_INT_EN REG_BIT(23) 3805 #define CURSORA_INVALID_GTT_INT_EN REG_BIT(22) 3806 #define SPRITED_INVALID_GTT_INT_EN REG_BIT(21) 3807 #define SPRITEC_INVALID_GTT_INT_EN REG_BIT(20) 3808 #define PLANEB_INVALID_GTT_INT_EN REG_BIT(19) 3809 #define SPRITEB_INVALID_GTT_INT_EN REG_BIT(18) 3810 #define SPRITEA_INVALID_GTT_INT_EN REG_BIT(17) 3811 #define PLANEA_INVALID_GTT_INT_EN REG_BIT(16) 3812 #define DPINVGTT_STATUS_MASK_CHV REG_GENMASK(11, 0) 3813 #define DPINVGTT_STATUS_MASK_VLV REG_GENMASK(7, 0) 3814 #define SPRITEF_INVALID_GTT_STATUS REG_BIT(11) 3815 #define SPRITEE_INVALID_GTT_STATUS REG_BIT(10) 3816 #define PLANEC_INVALID_GTT_STATUS REG_BIT(9) 3817 #define CURSORC_INVALID_GTT_STATUS REG_BIT(8) 3818 #define CURSORB_INVALID_GTT_STATUS REG_BIT(7) 3819 #define CURSORA_INVALID_GTT_STATUS REG_BIT(6) 3820 #define SPRITED_INVALID_GTT_STATUS REG_BIT(5) 3821 #define SPRITEC_INVALID_GTT_STATUS REG_BIT(4) 3822 #define PLANEB_INVALID_GTT_STATUS REG_BIT(3) 3823 #define SPRITEB_INVALID_GTT_STATUS REG_BIT(2) 3824 #define SPRITEA_INVALID_GTT_STATUS REG_BIT(1) 3825 #define PLANEA_INVALID_GTT_STATUS REG_BIT(0) 3826 3827 #define DSPARB _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030) 3828 #define DSPARB_CSTART_MASK (0x7f << 7) 3829 #define DSPARB_CSTART_SHIFT 7 3830 #define DSPARB_BSTART_MASK (0x7f) 3831 #define DSPARB_BSTART_SHIFT 0 3832 #define DSPARB_BEND_SHIFT 9 /* on 855 */ 3833 #define DSPARB_AEND_SHIFT 0 3834 #define DSPARB_SPRITEA_SHIFT_VLV 0 3835 #define DSPARB_SPRITEA_MASK_VLV (0xff << 0) 3836 #define DSPARB_SPRITEB_SHIFT_VLV 8 3837 #define DSPARB_SPRITEB_MASK_VLV (0xff << 8) 3838 #define DSPARB_SPRITEC_SHIFT_VLV 16 3839 #define DSPARB_SPRITEC_MASK_VLV (0xff << 16) 3840 #define DSPARB_SPRITED_SHIFT_VLV 24 3841 #define DSPARB_SPRITED_MASK_VLV (0xff << 24) 3842 #define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */ 3843 #define DSPARB_SPRITEA_HI_SHIFT_VLV 0 3844 #define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0) 3845 #define DSPARB_SPRITEB_HI_SHIFT_VLV 4 3846 #define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4) 3847 #define DSPARB_SPRITEC_HI_SHIFT_VLV 8 3848 #define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8) 3849 #define DSPARB_SPRITED_HI_SHIFT_VLV 12 3850 #define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12) 3851 #define DSPARB_SPRITEE_HI_SHIFT_VLV 16 3852 #define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16) 3853 #define DSPARB_SPRITEF_HI_SHIFT_VLV 20 3854 #define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20) 3855 #define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */ 3856 #define DSPARB_SPRITEE_SHIFT_VLV 0 3857 #define DSPARB_SPRITEE_MASK_VLV (0xff << 0) 3858 #define DSPARB_SPRITEF_SHIFT_VLV 8 3859 #define DSPARB_SPRITEF_MASK_VLV (0xff << 8) 3860 3861 /* pnv/gen4/g4x/vlv/chv */ 3862 #define DSPFW1 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034) 3863 #define DSPFW_SR_SHIFT 23 3864 #define DSPFW_SR_MASK (0x1ff << 23) 3865 #define DSPFW_CURSORB_SHIFT 16 3866 #define DSPFW_CURSORB_MASK (0x3f << 16) 3867 #define DSPFW_PLANEB_SHIFT 8 3868 #define DSPFW_PLANEB_MASK (0x7f << 8) 3869 #define DSPFW_PLANEB_MASK_VLV (0xff << 8) /* vlv/chv */ 3870 #define DSPFW_PLANEA_SHIFT 0 3871 #define DSPFW_PLANEA_MASK (0x7f << 0) 3872 #define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */ 3873 #define DSPFW2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038) 3874 #define DSPFW_FBC_SR_EN (1 << 31) /* g4x */ 3875 #define DSPFW_FBC_SR_SHIFT 28 3876 #define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */ 3877 #define DSPFW_FBC_HPLL_SR_SHIFT 24 3878 #define DSPFW_FBC_HPLL_SR_MASK (0xf << 24) /* g4x */ 3879 #define DSPFW_SPRITEB_SHIFT (16) 3880 #define DSPFW_SPRITEB_MASK (0x7f << 16) /* g4x */ 3881 #define DSPFW_SPRITEB_MASK_VLV (0xff << 16) /* vlv/chv */ 3882 #define DSPFW_CURSORA_SHIFT 8 3883 #define DSPFW_CURSORA_MASK (0x3f << 8) 3884 #define DSPFW_PLANEC_OLD_SHIFT 0 3885 #define DSPFW_PLANEC_OLD_MASK (0x7f << 0) /* pre-gen4 sprite C */ 3886 #define DSPFW_SPRITEA_SHIFT 0 3887 #define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */ 3888 #define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */ 3889 #define DSPFW3 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c) 3890 #define DSPFW_HPLL_SR_EN (1 << 31) 3891 #define PINEVIEW_SELF_REFRESH_EN (1 << 30) 3892 #define DSPFW_CURSOR_SR_SHIFT 24 3893 #define DSPFW_CURSOR_SR_MASK (0x3f << 24) 3894 #define DSPFW_HPLL_CURSOR_SHIFT 16 3895 #define DSPFW_HPLL_CURSOR_MASK (0x3f << 16) 3896 #define DSPFW_HPLL_SR_SHIFT 0 3897 #define DSPFW_HPLL_SR_MASK (0x1ff << 0) 3898 3899 /* vlv/chv */ 3900 #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070) 3901 #define DSPFW_SPRITEB_WM1_SHIFT 16 3902 #define DSPFW_SPRITEB_WM1_MASK (0xff << 16) 3903 #define DSPFW_CURSORA_WM1_SHIFT 8 3904 #define DSPFW_CURSORA_WM1_MASK (0x3f << 8) 3905 #define DSPFW_SPRITEA_WM1_SHIFT 0 3906 #define DSPFW_SPRITEA_WM1_MASK (0xff << 0) 3907 #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074) 3908 #define DSPFW_PLANEB_WM1_SHIFT 24 3909 #define DSPFW_PLANEB_WM1_MASK (0xff << 24) 3910 #define DSPFW_PLANEA_WM1_SHIFT 16 3911 #define DSPFW_PLANEA_WM1_MASK (0xff << 16) 3912 #define DSPFW_CURSORB_WM1_SHIFT 8 3913 #define DSPFW_CURSORB_WM1_MASK (0x3f << 8) 3914 #define DSPFW_CURSOR_SR_WM1_SHIFT 0 3915 #define DSPFW_CURSOR_SR_WM1_MASK (0x3f << 0) 3916 #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078) 3917 #define DSPFW_SR_WM1_SHIFT 0 3918 #define DSPFW_SR_WM1_MASK (0x1ff << 0) 3919 #define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c) 3920 #define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */ 3921 #define DSPFW_SPRITED_WM1_SHIFT 24 3922 #define DSPFW_SPRITED_WM1_MASK (0xff << 24) 3923 #define DSPFW_SPRITED_SHIFT 16 3924 #define DSPFW_SPRITED_MASK_VLV (0xff << 16) 3925 #define DSPFW_SPRITEC_WM1_SHIFT 8 3926 #define DSPFW_SPRITEC_WM1_MASK (0xff << 8) 3927 #define DSPFW_SPRITEC_SHIFT 0 3928 #define DSPFW_SPRITEC_MASK_VLV (0xff << 0) 3929 #define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8) 3930 #define DSPFW_SPRITEF_WM1_SHIFT 24 3931 #define DSPFW_SPRITEF_WM1_MASK (0xff << 24) 3932 #define DSPFW_SPRITEF_SHIFT 16 3933 #define DSPFW_SPRITEF_MASK_VLV (0xff << 16) 3934 #define DSPFW_SPRITEE_WM1_SHIFT 8 3935 #define DSPFW_SPRITEE_WM1_MASK (0xff << 8) 3936 #define DSPFW_SPRITEE_SHIFT 0 3937 #define DSPFW_SPRITEE_MASK_VLV (0xff << 0) 3938 #define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */ 3939 #define DSPFW_PLANEC_WM1_SHIFT 24 3940 #define DSPFW_PLANEC_WM1_MASK (0xff << 24) 3941 #define DSPFW_PLANEC_SHIFT 16 3942 #define DSPFW_PLANEC_MASK_VLV (0xff << 16) 3943 #define DSPFW_CURSORC_WM1_SHIFT 8 3944 #define DSPFW_CURSORC_WM1_MASK (0x3f << 16) 3945 #define DSPFW_CURSORC_SHIFT 0 3946 #define DSPFW_CURSORC_MASK (0x3f << 0) 3947 3948 /* vlv/chv high order bits */ 3949 #define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064) 3950 #define DSPFW_SR_HI_SHIFT 24 3951 #define DSPFW_SR_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */ 3952 #define DSPFW_SPRITEF_HI_SHIFT 23 3953 #define DSPFW_SPRITEF_HI_MASK (1 << 23) 3954 #define DSPFW_SPRITEE_HI_SHIFT 22 3955 #define DSPFW_SPRITEE_HI_MASK (1 << 22) 3956 #define DSPFW_PLANEC_HI_SHIFT 21 3957 #define DSPFW_PLANEC_HI_MASK (1 << 21) 3958 #define DSPFW_SPRITED_HI_SHIFT 20 3959 #define DSPFW_SPRITED_HI_MASK (1 << 20) 3960 #define DSPFW_SPRITEC_HI_SHIFT 16 3961 #define DSPFW_SPRITEC_HI_MASK (1 << 16) 3962 #define DSPFW_PLANEB_HI_SHIFT 12 3963 #define DSPFW_PLANEB_HI_MASK (1 << 12) 3964 #define DSPFW_SPRITEB_HI_SHIFT 8 3965 #define DSPFW_SPRITEB_HI_MASK (1 << 8) 3966 #define DSPFW_SPRITEA_HI_SHIFT 4 3967 #define DSPFW_SPRITEA_HI_MASK (1 << 4) 3968 #define DSPFW_PLANEA_HI_SHIFT 0 3969 #define DSPFW_PLANEA_HI_MASK (1 << 0) 3970 #define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068) 3971 #define DSPFW_SR_WM1_HI_SHIFT 24 3972 #define DSPFW_SR_WM1_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */ 3973 #define DSPFW_SPRITEF_WM1_HI_SHIFT 23 3974 #define DSPFW_SPRITEF_WM1_HI_MASK (1 << 23) 3975 #define DSPFW_SPRITEE_WM1_HI_SHIFT 22 3976 #define DSPFW_SPRITEE_WM1_HI_MASK (1 << 22) 3977 #define DSPFW_PLANEC_WM1_HI_SHIFT 21 3978 #define DSPFW_PLANEC_WM1_HI_MASK (1 << 21) 3979 #define DSPFW_SPRITED_WM1_HI_SHIFT 20 3980 #define DSPFW_SPRITED_WM1_HI_MASK (1 << 20) 3981 #define DSPFW_SPRITEC_WM1_HI_SHIFT 16 3982 #define DSPFW_SPRITEC_WM1_HI_MASK (1 << 16) 3983 #define DSPFW_PLANEB_WM1_HI_SHIFT 12 3984 #define DSPFW_PLANEB_WM1_HI_MASK (1 << 12) 3985 #define DSPFW_SPRITEB_WM1_HI_SHIFT 8 3986 #define DSPFW_SPRITEB_WM1_HI_MASK (1 << 8) 3987 #define DSPFW_SPRITEA_WM1_HI_SHIFT 4 3988 #define DSPFW_SPRITEA_WM1_HI_MASK (1 << 4) 3989 #define DSPFW_PLANEA_WM1_HI_SHIFT 0 3990 #define DSPFW_PLANEA_WM1_HI_MASK (1 << 0) 3991 3992 /* drain latency register values*/ 3993 #define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe)) 3994 #define DDL_CURSOR_SHIFT 24 3995 #define DDL_SPRITE_SHIFT(sprite) (8 + 8 * (sprite)) 3996 #define DDL_PLANE_SHIFT 0 3997 #define DDL_PRECISION_HIGH (1 << 7) 3998 #define DDL_PRECISION_LOW (0 << 7) 3999 #define DRAIN_LATENCY_MASK 0x7f 4000 4001 #define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400) 4002 #define CBR_PND_DEADLINE_DISABLE (1 << 31) 4003 #define CBR_PWM_CLOCK_MUX_SELECT (1 << 30) 4004 4005 #define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450) 4006 #define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11)) /* pipes B and C */ 4007 4008 /* FIFO watermark sizes etc */ 4009 #define G4X_FIFO_LINE_SIZE 64 4010 #define I915_FIFO_LINE_SIZE 64 4011 #define I830_FIFO_LINE_SIZE 32 4012 4013 #define VALLEYVIEW_FIFO_SIZE 255 4014 #define G4X_FIFO_SIZE 127 4015 #define I965_FIFO_SIZE 512 4016 #define I945_FIFO_SIZE 127 4017 #define I915_FIFO_SIZE 95 4018 #define I855GM_FIFO_SIZE 127 /* In cachelines */ 4019 #define I830_FIFO_SIZE 95 4020 4021 #define VALLEYVIEW_MAX_WM 0xff 4022 #define G4X_MAX_WM 0x3f 4023 #define I915_MAX_WM 0x3f 4024 4025 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ 4026 #define PINEVIEW_FIFO_LINE_SIZE 64 4027 #define PINEVIEW_MAX_WM 0x1ff 4028 #define PINEVIEW_DFT_WM 0x3f 4029 #define PINEVIEW_DFT_HPLLOFF_WM 0 4030 #define PINEVIEW_GUARD_WM 10 4031 #define PINEVIEW_CURSOR_FIFO 64 4032 #define PINEVIEW_CURSOR_MAX_WM 0x3f 4033 #define PINEVIEW_CURSOR_DFT_WM 0 4034 #define PINEVIEW_CURSOR_GUARD_WM 5 4035 4036 #define VALLEYVIEW_CURSOR_MAX_WM 64 4037 #define I965_CURSOR_FIFO 64 4038 #define I965_CURSOR_MAX_WM 32 4039 #define I965_CURSOR_DFT_WM 8 4040 4041 /* Watermark register definitions for SKL */ 4042 #define _CUR_WM_A_0 0x70140 4043 #define _CUR_WM_B_0 0x71140 4044 #define _CUR_WM_SAGV_A 0x70158 4045 #define _CUR_WM_SAGV_B 0x71158 4046 #define _CUR_WM_SAGV_TRANS_A 0x7015C 4047 #define _CUR_WM_SAGV_TRANS_B 0x7115C 4048 #define _CUR_WM_TRANS_A 0x70168 4049 #define _CUR_WM_TRANS_B 0x71168 4050 #define _PLANE_WM_1_A_0 0x70240 4051 #define _PLANE_WM_1_B_0 0x71240 4052 #define _PLANE_WM_2_A_0 0x70340 4053 #define _PLANE_WM_2_B_0 0x71340 4054 #define _PLANE_WM_SAGV_1_A 0x70258 4055 #define _PLANE_WM_SAGV_1_B 0x71258 4056 #define _PLANE_WM_SAGV_2_A 0x70358 4057 #define _PLANE_WM_SAGV_2_B 0x71358 4058 #define _PLANE_WM_SAGV_TRANS_1_A 0x7025C 4059 #define _PLANE_WM_SAGV_TRANS_1_B 0x7125C 4060 #define _PLANE_WM_SAGV_TRANS_2_A 0x7035C 4061 #define _PLANE_WM_SAGV_TRANS_2_B 0x7135C 4062 #define _PLANE_WM_TRANS_1_A 0x70268 4063 #define _PLANE_WM_TRANS_1_B 0x71268 4064 #define _PLANE_WM_TRANS_2_A 0x70368 4065 #define _PLANE_WM_TRANS_2_B 0x71368 4066 #define PLANE_WM_EN (1 << 31) 4067 #define PLANE_WM_IGNORE_LINES (1 << 30) 4068 #define PLANE_WM_LINES_MASK REG_GENMASK(26, 14) 4069 #define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0) 4070 4071 #define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0) 4072 #define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level))) 4073 #define CUR_WM_SAGV(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_A, _CUR_WM_SAGV_B) 4074 #define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B) 4075 #define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A, _CUR_WM_TRANS_B) 4076 #define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0) 4077 #define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0) 4078 #define _PLANE_WM_BASE(pipe, plane) \ 4079 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe)) 4080 #define PLANE_WM(pipe, plane, level) \ 4081 _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level))) 4082 #define _PLANE_WM_SAGV_1(pipe) \ 4083 _PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B) 4084 #define _PLANE_WM_SAGV_2(pipe) \ 4085 _PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B) 4086 #define PLANE_WM_SAGV(pipe, plane) \ 4087 _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe))) 4088 #define _PLANE_WM_SAGV_TRANS_1(pipe) \ 4089 _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B) 4090 #define _PLANE_WM_SAGV_TRANS_2(pipe) \ 4091 _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B) 4092 #define PLANE_WM_SAGV_TRANS(pipe, plane) \ 4093 _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe))) 4094 #define _PLANE_WM_TRANS_1(pipe) \ 4095 _PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B) 4096 #define _PLANE_WM_TRANS_2(pipe) \ 4097 _PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B) 4098 #define PLANE_WM_TRANS(pipe, plane) \ 4099 _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe))) 4100 4101 /* define the Watermark register on Ironlake */ 4102 #define _WM0_PIPEA_ILK 0x45100 4103 #define _WM0_PIPEB_ILK 0x45104 4104 #define _WM0_PIPEC_IVB 0x45200 4105 #define WM0_PIPE_ILK(pipe) _MMIO_PIPE3((pipe), _WM0_PIPEA_ILK, \ 4106 _WM0_PIPEB_ILK, _WM0_PIPEC_IVB) 4107 #define WM0_PIPE_PRIMARY_MASK REG_GENMASK(31, 16) 4108 #define WM0_PIPE_SPRITE_MASK REG_GENMASK(15, 8) 4109 #define WM0_PIPE_CURSOR_MASK REG_GENMASK(7, 0) 4110 #define WM0_PIPE_PRIMARY(x) REG_FIELD_PREP(WM0_PIPE_PRIMARY_MASK, (x)) 4111 #define WM0_PIPE_SPRITE(x) REG_FIELD_PREP(WM0_PIPE_SPRITE_MASK, (x)) 4112 #define WM0_PIPE_CURSOR(x) REG_FIELD_PREP(WM0_PIPE_CURSOR_MASK, (x)) 4113 #define WM1_LP_ILK _MMIO(0x45108) 4114 #define WM2_LP_ILK _MMIO(0x4510c) 4115 #define WM3_LP_ILK _MMIO(0x45110) 4116 #define WM_LP_ENABLE REG_BIT(31) 4117 #define WM_LP_LATENCY_MASK REG_GENMASK(30, 24) 4118 #define WM_LP_FBC_MASK_BDW REG_GENMASK(23, 19) 4119 #define WM_LP_FBC_MASK_ILK REG_GENMASK(23, 20) 4120 #define WM_LP_PRIMARY_MASK REG_GENMASK(18, 8) 4121 #define WM_LP_CURSOR_MASK REG_GENMASK(7, 0) 4122 #define WM_LP_LATENCY(x) REG_FIELD_PREP(WM_LP_LATENCY_MASK, (x)) 4123 #define WM_LP_FBC_BDW(x) REG_FIELD_PREP(WM_LP_FBC_MASK_BDW, (x)) 4124 #define WM_LP_FBC_ILK(x) REG_FIELD_PREP(WM_LP_FBC_MASK_ILK, (x)) 4125 #define WM_LP_PRIMARY(x) REG_FIELD_PREP(WM_LP_PRIMARY_MASK, (x)) 4126 #define WM_LP_CURSOR(x) REG_FIELD_PREP(WM_LP_CURSOR_MASK, (x)) 4127 #define WM1S_LP_ILK _MMIO(0x45120) 4128 #define WM2S_LP_IVB _MMIO(0x45124) 4129 #define WM3S_LP_IVB _MMIO(0x45128) 4130 #define WM_LP_SPRITE_ENABLE REG_BIT(31) /* ilk/snb WM1S only */ 4131 #define WM_LP_SPRITE_MASK REG_GENMASK(10, 0) 4132 #define WM_LP_SPRITE(x) REG_FIELD_PREP(WM_LP_SPRITE_MASK, (x)) 4133 4134 /* 4135 * The two pipe frame counter registers are not synchronized, so 4136 * reading a stable value is somewhat tricky. The following code 4137 * should work: 4138 * 4139 * do { 4140 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 4141 * PIPE_FRAME_HIGH_SHIFT; 4142 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> 4143 * PIPE_FRAME_LOW_SHIFT); 4144 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 4145 * PIPE_FRAME_HIGH_SHIFT); 4146 * } while (high1 != high2); 4147 * frame = (high1 << 8) | low1; 4148 */ 4149 #define _PIPEAFRAMEHIGH 0x70040 4150 #define PIPE_FRAME_HIGH_MASK 0x0000ffff 4151 #define PIPE_FRAME_HIGH_SHIFT 0 4152 #define _PIPEAFRAMEPIXEL 0x70044 4153 #define PIPE_FRAME_LOW_MASK 0xff000000 4154 #define PIPE_FRAME_LOW_SHIFT 24 4155 #define PIPE_PIXEL_MASK 0x00ffffff 4156 #define PIPE_PIXEL_SHIFT 0 4157 /* GM45+ just has to be different */ 4158 #define _PIPEA_FRMCOUNT_G4X 0x70040 4159 #define _PIPEA_FLIPCOUNT_G4X 0x70044 4160 #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X) 4161 #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X) 4162 4163 /* Cursor A & B regs */ 4164 #define _CURACNTR 0x70080 4165 /* Old style CUR*CNTR flags (desktop 8xx) */ 4166 #define CURSOR_ENABLE REG_BIT(31) 4167 #define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30) 4168 #define CURSOR_STRIDE_MASK REG_GENMASK(29, 28) 4169 #define CURSOR_STRIDE(stride) REG_FIELD_PREP(CURSOR_STRIDE_MASK, ffs(stride) - 9) /* 256,512,1k,2k */ 4170 #define CURSOR_FORMAT_MASK REG_GENMASK(26, 24) 4171 #define CURSOR_FORMAT_2C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 0) 4172 #define CURSOR_FORMAT_3C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 1) 4173 #define CURSOR_FORMAT_4C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 2) 4174 #define CURSOR_FORMAT_ARGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 4) 4175 #define CURSOR_FORMAT_XRGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 5) 4176 /* New style CUR*CNTR flags */ 4177 #define MCURSOR_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ 4178 #define MCURSOR_ARB_SLOTS(x) REG_FIELD_PREP(MCURSOR_ARB_SLOTS_MASK, (x)) /* icl+ */ 4179 #define MCURSOR_PIPE_SEL_MASK REG_GENMASK(29, 28) 4180 #define MCURSOR_PIPE_SEL(pipe) REG_FIELD_PREP(MCURSOR_PIPE_SEL_MASK, (pipe)) 4181 #define MCURSOR_PIPE_GAMMA_ENABLE REG_BIT(26) 4182 #define MCURSOR_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */ 4183 #define MCURSOR_ROTATE_180 REG_BIT(15) 4184 #define MCURSOR_TRICKLE_FEED_DISABLE REG_BIT(14) 4185 #define MCURSOR_MODE_MASK 0x27 4186 #define MCURSOR_MODE_DISABLE 0x00 4187 #define MCURSOR_MODE_128_32B_AX 0x02 4188 #define MCURSOR_MODE_256_32B_AX 0x03 4189 #define MCURSOR_MODE_64_32B_AX 0x07 4190 #define MCURSOR_MODE_128_ARGB_AX (0x20 | MCURSOR_MODE_128_32B_AX) 4191 #define MCURSOR_MODE_256_ARGB_AX (0x20 | MCURSOR_MODE_256_32B_AX) 4192 #define MCURSOR_MODE_64_ARGB_AX (0x20 | MCURSOR_MODE_64_32B_AX) 4193 #define _CURABASE 0x70084 4194 #define _CURAPOS 0x70088 4195 #define CURSOR_POS_Y_SIGN REG_BIT(31) 4196 #define CURSOR_POS_Y_MASK REG_GENMASK(30, 16) 4197 #define CURSOR_POS_Y(y) REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y)) 4198 #define CURSOR_POS_X_SIGN REG_BIT(15) 4199 #define CURSOR_POS_X_MASK REG_GENMASK(14, 0) 4200 #define CURSOR_POS_X(x) REG_FIELD_PREP(CURSOR_POS_X_MASK, (x)) 4201 #define _CURASIZE 0x700a0 /* 845/865 */ 4202 #define CURSOR_HEIGHT_MASK REG_GENMASK(21, 12) 4203 #define CURSOR_HEIGHT(h) REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h)) 4204 #define CURSOR_WIDTH_MASK REG_GENMASK(9, 0) 4205 #define CURSOR_WIDTH(w) REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w)) 4206 #define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */ 4207 #define CUR_FBC_EN REG_BIT(31) 4208 #define CUR_FBC_HEIGHT_MASK REG_GENMASK(7, 0) 4209 #define CUR_FBC_HEIGHT(h) REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h)) 4210 #define _CURASURFLIVE 0x700ac /* g4x+ */ 4211 #define _CURBCNTR 0x700c0 4212 #define _CURBBASE 0x700c4 4213 #define _CURBPOS 0x700c8 4214 4215 #define _CURBCNTR_IVB 0x71080 4216 #define _CURBBASE_IVB 0x71084 4217 #define _CURBPOS_IVB 0x71088 4218 4219 #define CURCNTR(pipe) _MMIO_CURSOR2(pipe, _CURACNTR) 4220 #define CURBASE(pipe) _MMIO_CURSOR2(pipe, _CURABASE) 4221 #define CURPOS(pipe) _MMIO_CURSOR2(pipe, _CURAPOS) 4222 #define CURSIZE(pipe) _MMIO_CURSOR2(pipe, _CURASIZE) 4223 #define CUR_FBC_CTL(pipe) _MMIO_CURSOR2(pipe, _CUR_FBC_CTL_A) 4224 #define CURSURFLIVE(pipe) _MMIO_CURSOR2(pipe, _CURASURFLIVE) 4225 4226 #define CURSOR_A_OFFSET 0x70080 4227 #define CURSOR_B_OFFSET 0x700c0 4228 #define CHV_CURSOR_C_OFFSET 0x700e0 4229 #define IVB_CURSOR_B_OFFSET 0x71080 4230 #define IVB_CURSOR_C_OFFSET 0x72080 4231 #define TGL_CURSOR_D_OFFSET 0x73080 4232 4233 /* Display A control */ 4234 #define _DSPAADDR_VLV 0x7017C /* vlv/chv */ 4235 #define _DSPACNTR 0x70180 4236 #define DISP_ENABLE REG_BIT(31) 4237 #define DISP_PIPE_GAMMA_ENABLE REG_BIT(30) 4238 #define DISP_FORMAT_MASK REG_GENMASK(29, 26) 4239 #define DISP_FORMAT_8BPP REG_FIELD_PREP(DISP_FORMAT_MASK, 2) 4240 #define DISP_FORMAT_BGRA555 REG_FIELD_PREP(DISP_FORMAT_MASK, 3) 4241 #define DISP_FORMAT_BGRX555 REG_FIELD_PREP(DISP_FORMAT_MASK, 4) 4242 #define DISP_FORMAT_BGRX565 REG_FIELD_PREP(DISP_FORMAT_MASK, 5) 4243 #define DISP_FORMAT_BGRX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 6) 4244 #define DISP_FORMAT_BGRA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 7) 4245 #define DISP_FORMAT_RGBX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 8) 4246 #define DISP_FORMAT_RGBA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 9) 4247 #define DISP_FORMAT_BGRX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 10) 4248 #define DISP_FORMAT_BGRA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 11) 4249 #define DISP_FORMAT_RGBX161616 REG_FIELD_PREP(DISP_FORMAT_MASK, 12) 4250 #define DISP_FORMAT_RGBX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 14) 4251 #define DISP_FORMAT_RGBA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 15) 4252 #define DISP_STEREO_ENABLE REG_BIT(25) 4253 #define DISP_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */ 4254 #define DISP_PIPE_SEL_MASK REG_GENMASK(25, 24) 4255 #define DISP_PIPE_SEL(pipe) REG_FIELD_PREP(DISP_PIPE_SEL_MASK, (pipe)) 4256 #define DISP_SRC_KEY_ENABLE REG_BIT(22) 4257 #define DISP_LINE_DOUBLE REG_BIT(20) 4258 #define DISP_STEREO_POLARITY_SECOND REG_BIT(18) 4259 #define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */ 4260 #define DISP_ROTATE_180 REG_BIT(15) 4261 #define DISP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */ 4262 #define DISP_TILED REG_BIT(10) 4263 #define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */ 4264 #define DISP_MIRROR REG_BIT(8) /* CHV pipe B */ 4265 #define _DSPAADDR 0x70184 4266 #define _DSPASTRIDE 0x70188 4267 #define _DSPAPOS 0x7018C /* reserved */ 4268 #define DISP_POS_Y_MASK REG_GENMASK(31, 16) 4269 #define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y)) 4270 #define DISP_POS_X_MASK REG_GENMASK(15, 0) 4271 #define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x)) 4272 #define _DSPASIZE 0x70190 4273 #define DISP_HEIGHT_MASK REG_GENMASK(31, 16) 4274 #define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h)) 4275 #define DISP_WIDTH_MASK REG_GENMASK(15, 0) 4276 #define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w)) 4277 #define _DSPASURF 0x7019C /* 965+ only */ 4278 #define DISP_ADDR_MASK REG_GENMASK(31, 12) 4279 #define _DSPATILEOFF 0x701A4 /* 965+ only */ 4280 #define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16) 4281 #define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y)) 4282 #define DISP_OFFSET_X_MASK REG_GENMASK(15, 0) 4283 #define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x)) 4284 #define _DSPAOFFSET 0x701A4 /* HSW */ 4285 #define _DSPASURFLIVE 0x701AC 4286 #define _DSPAGAMC 0x701E0 4287 4288 #define DSPADDR_VLV(plane) _MMIO_PIPE2(plane, _DSPAADDR_VLV) 4289 #define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR) 4290 #define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR) 4291 #define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE) 4292 #define DSPPOS(plane) _MMIO_PIPE2(plane, _DSPAPOS) 4293 #define DSPSIZE(plane) _MMIO_PIPE2(plane, _DSPASIZE) 4294 #define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF) 4295 #define DSPTILEOFF(plane) _MMIO_PIPE2(plane, _DSPATILEOFF) 4296 #define DSPLINOFF(plane) DSPADDR(plane) 4297 #define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET) 4298 #define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE) 4299 #define DSPGAMC(plane, i) _MMIO_PIPE2(plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ 4300 4301 /* CHV pipe B blender and primary plane */ 4302 #define _CHV_BLEND_A 0x60a00 4303 #define CHV_BLEND_MASK REG_GENMASK(31, 30) 4304 #define CHV_BLEND_LEGACY REG_FIELD_PREP(CHV_BLEND_MASK, 0) 4305 #define CHV_BLEND_ANDROID REG_FIELD_PREP(CHV_BLEND_MASK, 1) 4306 #define CHV_BLEND_MPO REG_FIELD_PREP(CHV_BLEND_MASK, 2) 4307 #define _CHV_CANVAS_A 0x60a04 4308 #define CHV_CANVAS_RED_MASK REG_GENMASK(29, 20) 4309 #define CHV_CANVAS_GREEN_MASK REG_GENMASK(19, 10) 4310 #define CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0) 4311 #define _PRIMPOS_A 0x60a08 4312 #define PRIM_POS_Y_MASK REG_GENMASK(31, 16) 4313 #define PRIM_POS_Y(y) REG_FIELD_PREP(PRIM_POS_Y_MASK, (y)) 4314 #define PRIM_POS_X_MASK REG_GENMASK(15, 0) 4315 #define PRIM_POS_X(x) REG_FIELD_PREP(PRIM_POS_X_MASK, (x)) 4316 #define _PRIMSIZE_A 0x60a0c 4317 #define PRIM_HEIGHT_MASK REG_GENMASK(31, 16) 4318 #define PRIM_HEIGHT(h) REG_FIELD_PREP(PRIM_HEIGHT_MASK, (h)) 4319 #define PRIM_WIDTH_MASK REG_GENMASK(15, 0) 4320 #define PRIM_WIDTH(w) REG_FIELD_PREP(PRIM_WIDTH_MASK, (w)) 4321 #define _PRIMCNSTALPHA_A 0x60a10 4322 #define PRIM_CONST_ALPHA_ENABLE REG_BIT(31) 4323 #define PRIM_CONST_ALPHA_MASK REG_GENMASK(7, 0) 4324 #define PRIM_CONST_ALPHA(alpha) REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha)) 4325 4326 #define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A) 4327 #define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A) 4328 #define PRIMPOS(plane) _MMIO_TRANS2(plane, _PRIMPOS_A) 4329 #define PRIMSIZE(plane) _MMIO_TRANS2(plane, _PRIMSIZE_A) 4330 #define PRIMCNSTALPHA(plane) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A) 4331 4332 /* Display/Sprite base address macros */ 4333 #define DISP_BASEADDR_MASK (0xfffff000) 4334 #define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK) 4335 #define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK) 4336 4337 /* 4338 * VBIOS flags 4339 * gen2: 4340 * [00:06] alm,mgm 4341 * [10:16] all 4342 * [30:32] alm,mgm 4343 * gen3+: 4344 * [00:0f] all 4345 * [10:1f] all 4346 * [30:32] all 4347 */ 4348 #define SWF0(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4) 4349 #define SWF1(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4) 4350 #define SWF3(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4) 4351 #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4) 4352 4353 /* Pipe B */ 4354 #define _PIPEBDSL (DISPLAY_MMIO_BASE(dev_priv) + 0x71000) 4355 #define _PIPEBCONF (DISPLAY_MMIO_BASE(dev_priv) + 0x71008) 4356 #define _PIPEBSTAT (DISPLAY_MMIO_BASE(dev_priv) + 0x71024) 4357 #define _PIPEBFRAMEHIGH 0x71040 4358 #define _PIPEBFRAMEPIXEL 0x71044 4359 #define _PIPEB_FRMCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71040) 4360 #define _PIPEB_FLIPCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71044) 4361 4362 4363 /* Display B control */ 4364 #define _DSPBCNTR (DISPLAY_MMIO_BASE(dev_priv) + 0x71180) 4365 #define DISP_ALPHA_TRANS_ENABLE REG_BIT(15) 4366 #define DISP_SPRITE_ABOVE_OVERLAY REG_BIT(0) 4367 #define _DSPBADDR (DISPLAY_MMIO_BASE(dev_priv) + 0x71184) 4368 #define _DSPBSTRIDE (DISPLAY_MMIO_BASE(dev_priv) + 0x71188) 4369 #define _DSPBPOS (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C) 4370 #define _DSPBSIZE (DISPLAY_MMIO_BASE(dev_priv) + 0x71190) 4371 #define _DSPBSURF (DISPLAY_MMIO_BASE(dev_priv) + 0x7119C) 4372 #define _DSPBTILEOFF (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4) 4373 #define _DSPBOFFSET (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4) 4374 #define _DSPBSURFLIVE (DISPLAY_MMIO_BASE(dev_priv) + 0x711AC) 4375 4376 /* ICL DSI 0 and 1 */ 4377 #define _PIPEDSI0CONF 0x7b008 4378 #define _PIPEDSI1CONF 0x7b808 4379 4380 /* Sprite A control */ 4381 #define _DVSACNTR 0x72180 4382 #define DVS_ENABLE REG_BIT(31) 4383 #define DVS_PIPE_GAMMA_ENABLE REG_BIT(30) 4384 #define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27) 4385 #define DVS_FORMAT_MASK REG_GENMASK(26, 25) 4386 #define DVS_FORMAT_YUV422 REG_FIELD_PREP(DVS_FORMAT_MASK, 0) 4387 #define DVS_FORMAT_RGBX101010 REG_FIELD_PREP(DVS_FORMAT_MASK, 1) 4388 #define DVS_FORMAT_RGBX888 REG_FIELD_PREP(DVS_FORMAT_MASK, 2) 4389 #define DVS_FORMAT_RGBX161616 REG_FIELD_PREP(DVS_FORMAT_MASK, 3) 4390 #define DVS_PIPE_CSC_ENABLE REG_BIT(24) 4391 #define DVS_SOURCE_KEY REG_BIT(22) 4392 #define DVS_RGB_ORDER_XBGR REG_BIT(20) 4393 #define DVS_YUV_FORMAT_BT709 REG_BIT(18) 4394 #define DVS_YUV_ORDER_MASK REG_GENMASK(17, 16) 4395 #define DVS_YUV_ORDER_YUYV REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 0) 4396 #define DVS_YUV_ORDER_UYVY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 1) 4397 #define DVS_YUV_ORDER_YVYU REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 2) 4398 #define DVS_YUV_ORDER_VYUY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 3) 4399 #define DVS_ROTATE_180 REG_BIT(15) 4400 #define DVS_TRICKLE_FEED_DISABLE REG_BIT(14) 4401 #define DVS_TILED REG_BIT(10) 4402 #define DVS_DEST_KEY REG_BIT(2) 4403 #define _DVSALINOFF 0x72184 4404 #define _DVSASTRIDE 0x72188 4405 #define _DVSAPOS 0x7218c 4406 #define DVS_POS_Y_MASK REG_GENMASK(31, 16) 4407 #define DVS_POS_Y(y) REG_FIELD_PREP(DVS_POS_Y_MASK, (y)) 4408 #define DVS_POS_X_MASK REG_GENMASK(15, 0) 4409 #define DVS_POS_X(x) REG_FIELD_PREP(DVS_POS_X_MASK, (x)) 4410 #define _DVSASIZE 0x72190 4411 #define DVS_HEIGHT_MASK REG_GENMASK(31, 16) 4412 #define DVS_HEIGHT(h) REG_FIELD_PREP(DVS_HEIGHT_MASK, (h)) 4413 #define DVS_WIDTH_MASK REG_GENMASK(15, 0) 4414 #define DVS_WIDTH(w) REG_FIELD_PREP(DVS_WIDTH_MASK, (w)) 4415 #define _DVSAKEYVAL 0x72194 4416 #define _DVSAKEYMSK 0x72198 4417 #define _DVSASURF 0x7219c 4418 #define DVS_ADDR_MASK REG_GENMASK(31, 12) 4419 #define _DVSAKEYMAXVAL 0x721a0 4420 #define _DVSATILEOFF 0x721a4 4421 #define DVS_OFFSET_Y_MASK REG_GENMASK(31, 16) 4422 #define DVS_OFFSET_Y(y) REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y)) 4423 #define DVS_OFFSET_X_MASK REG_GENMASK(15, 0) 4424 #define DVS_OFFSET_X(x) REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x)) 4425 #define _DVSASURFLIVE 0x721ac 4426 #define _DVSAGAMC_G4X 0x721e0 /* g4x */ 4427 #define _DVSASCALE 0x72204 4428 #define DVS_SCALE_ENABLE REG_BIT(31) 4429 #define DVS_FILTER_MASK REG_GENMASK(30, 29) 4430 #define DVS_FILTER_MEDIUM REG_FIELD_PREP(DVS_FILTER_MASK, 0) 4431 #define DVS_FILTER_ENHANCING REG_FIELD_PREP(DVS_FILTER_MASK, 1) 4432 #define DVS_FILTER_SOFTENING REG_FIELD_PREP(DVS_FILTER_MASK, 2) 4433 #define DVS_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */ 4434 #define DVS_VERTICAL_OFFSET_ENABLE REG_BIT(27) 4435 #define DVS_SRC_WIDTH_MASK REG_GENMASK(26, 16) 4436 #define DVS_SRC_WIDTH(w) REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w)) 4437 #define DVS_SRC_HEIGHT_MASK REG_GENMASK(10, 0) 4438 #define DVS_SRC_HEIGHT(h) REG_FIELD_PREP(DVS_SRC_HEIGHT_MASK, (h)) 4439 #define _DVSAGAMC_ILK 0x72300 /* ilk/snb */ 4440 #define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */ 4441 4442 #define _DVSBCNTR 0x73180 4443 #define _DVSBLINOFF 0x73184 4444 #define _DVSBSTRIDE 0x73188 4445 #define _DVSBPOS 0x7318c 4446 #define _DVSBSIZE 0x73190 4447 #define _DVSBKEYVAL 0x73194 4448 #define _DVSBKEYMSK 0x73198 4449 #define _DVSBSURF 0x7319c 4450 #define _DVSBKEYMAXVAL 0x731a0 4451 #define _DVSBTILEOFF 0x731a4 4452 #define _DVSBSURFLIVE 0x731ac 4453 #define _DVSBGAMC_G4X 0x731e0 /* g4x */ 4454 #define _DVSBSCALE 0x73204 4455 #define _DVSBGAMC_ILK 0x73300 /* ilk/snb */ 4456 #define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */ 4457 4458 #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR) 4459 #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) 4460 #define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) 4461 #define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS) 4462 #define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF) 4463 #define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) 4464 #define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE) 4465 #define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE) 4466 #define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) 4467 #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) 4468 #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) 4469 #define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) 4470 #define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */ 4471 #define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */ 4472 #define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */ 4473 4474 #define _SPRA_CTL 0x70280 4475 #define SPRITE_ENABLE REG_BIT(31) 4476 #define SPRITE_PIPE_GAMMA_ENABLE REG_BIT(30) 4477 #define SPRITE_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) 4478 #define SPRITE_FORMAT_MASK REG_GENMASK(27, 25) 4479 #define SPRITE_FORMAT_YUV422 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 0) 4480 #define SPRITE_FORMAT_RGBX101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 1) 4481 #define SPRITE_FORMAT_RGBX888 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 2) 4482 #define SPRITE_FORMAT_RGBX161616 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 3) 4483 #define SPRITE_FORMAT_YUV444 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 4) 4484 #define SPRITE_FORMAT_XR_BGR101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 5) /* Extended range */ 4485 #define SPRITE_PIPE_CSC_ENABLE REG_BIT(24) 4486 #define SPRITE_SOURCE_KEY REG_BIT(22) 4487 #define SPRITE_RGB_ORDER_RGBX REG_BIT(20) /* only for 888 and 161616 */ 4488 #define SPRITE_YUV_TO_RGB_CSC_DISABLE REG_BIT(19) 4489 #define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) /* 0 is BT601 */ 4490 #define SPRITE_YUV_ORDER_MASK REG_GENMASK(17, 16) 4491 #define SPRITE_YUV_ORDER_YUYV REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 0) 4492 #define SPRITE_YUV_ORDER_UYVY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 1) 4493 #define SPRITE_YUV_ORDER_YVYU REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 2) 4494 #define SPRITE_YUV_ORDER_VYUY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 3) 4495 #define SPRITE_ROTATE_180 REG_BIT(15) 4496 #define SPRITE_TRICKLE_FEED_DISABLE REG_BIT(14) 4497 #define SPRITE_PLANE_GAMMA_DISABLE REG_BIT(13) 4498 #define SPRITE_TILED REG_BIT(10) 4499 #define SPRITE_DEST_KEY REG_BIT(2) 4500 #define _SPRA_LINOFF 0x70284 4501 #define _SPRA_STRIDE 0x70288 4502 #define _SPRA_POS 0x7028c 4503 #define SPRITE_POS_Y_MASK REG_GENMASK(31, 16) 4504 #define SPRITE_POS_Y(y) REG_FIELD_PREP(SPRITE_POS_Y_MASK, (y)) 4505 #define SPRITE_POS_X_MASK REG_GENMASK(15, 0) 4506 #define SPRITE_POS_X(x) REG_FIELD_PREP(SPRITE_POS_X_MASK, (x)) 4507 #define _SPRA_SIZE 0x70290 4508 #define SPRITE_HEIGHT_MASK REG_GENMASK(31, 16) 4509 #define SPRITE_HEIGHT(h) REG_FIELD_PREP(SPRITE_HEIGHT_MASK, (h)) 4510 #define SPRITE_WIDTH_MASK REG_GENMASK(15, 0) 4511 #define SPRITE_WIDTH(w) REG_FIELD_PREP(SPRITE_WIDTH_MASK, (w)) 4512 #define _SPRA_KEYVAL 0x70294 4513 #define _SPRA_KEYMSK 0x70298 4514 #define _SPRA_SURF 0x7029c 4515 #define SPRITE_ADDR_MASK REG_GENMASK(31, 12) 4516 #define _SPRA_KEYMAX 0x702a0 4517 #define _SPRA_TILEOFF 0x702a4 4518 #define SPRITE_OFFSET_Y_MASK REG_GENMASK(31, 16) 4519 #define SPRITE_OFFSET_Y(y) REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y)) 4520 #define SPRITE_OFFSET_X_MASK REG_GENMASK(15, 0) 4521 #define SPRITE_OFFSET_X(x) REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x)) 4522 #define _SPRA_OFFSET 0x702a4 4523 #define _SPRA_SURFLIVE 0x702ac 4524 #define _SPRA_SCALE 0x70304 4525 #define SPRITE_SCALE_ENABLE REG_BIT(31) 4526 #define SPRITE_FILTER_MASK REG_GENMASK(30, 29) 4527 #define SPRITE_FILTER_MEDIUM REG_FIELD_PREP(SPRITE_FILTER_MASK, 0) 4528 #define SPRITE_FILTER_ENHANCING REG_FIELD_PREP(SPRITE_FILTER_MASK, 1) 4529 #define SPRITE_FILTER_SOFTENING REG_FIELD_PREP(SPRITE_FILTER_MASK, 2) 4530 #define SPRITE_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */ 4531 #define SPRITE_VERTICAL_OFFSET_ENABLE REG_BIT(27) 4532 #define SPRITE_SRC_WIDTH_MASK REG_GENMASK(26, 16) 4533 #define SPRITE_SRC_WIDTH(w) REG_FIELD_PREP(SPRITE_SRC_WIDTH_MASK, (w)) 4534 #define SPRITE_SRC_HEIGHT_MASK REG_GENMASK(10, 0) 4535 #define SPRITE_SRC_HEIGHT(h) REG_FIELD_PREP(SPRITE_SRC_HEIGHT_MASK, (h)) 4536 #define _SPRA_GAMC 0x70400 4537 #define _SPRA_GAMC16 0x70440 4538 #define _SPRA_GAMC17 0x7044c 4539 4540 #define _SPRB_CTL 0x71280 4541 #define _SPRB_LINOFF 0x71284 4542 #define _SPRB_STRIDE 0x71288 4543 #define _SPRB_POS 0x7128c 4544 #define _SPRB_SIZE 0x71290 4545 #define _SPRB_KEYVAL 0x71294 4546 #define _SPRB_KEYMSK 0x71298 4547 #define _SPRB_SURF 0x7129c 4548 #define _SPRB_KEYMAX 0x712a0 4549 #define _SPRB_TILEOFF 0x712a4 4550 #define _SPRB_OFFSET 0x712a4 4551 #define _SPRB_SURFLIVE 0x712ac 4552 #define _SPRB_SCALE 0x71304 4553 #define _SPRB_GAMC 0x71400 4554 #define _SPRB_GAMC16 0x71440 4555 #define _SPRB_GAMC17 0x7144c 4556 4557 #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL) 4558 #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) 4559 #define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) 4560 #define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS) 4561 #define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) 4562 #define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) 4563 #define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) 4564 #define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF) 4565 #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) 4566 #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) 4567 #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) 4568 #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) 4569 #define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */ 4570 #define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */ 4571 #define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */ 4572 #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) 4573 4574 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180) 4575 #define SP_ENABLE REG_BIT(31) 4576 #define SP_PIPE_GAMMA_ENABLE REG_BIT(30) 4577 #define SP_FORMAT_MASK REG_GENMASK(29, 26) 4578 #define SP_FORMAT_YUV422 REG_FIELD_PREP(SP_FORMAT_MASK, 0) 4579 #define SP_FORMAT_8BPP REG_FIELD_PREP(SP_FORMAT_MASK, 2) 4580 #define SP_FORMAT_BGR565 REG_FIELD_PREP(SP_FORMAT_MASK, 5) 4581 #define SP_FORMAT_BGRX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 6) 4582 #define SP_FORMAT_BGRA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 7) 4583 #define SP_FORMAT_RGBX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 8) 4584 #define SP_FORMAT_RGBA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 9) 4585 #define SP_FORMAT_BGRX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 10) /* CHV pipe B */ 4586 #define SP_FORMAT_BGRA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 11) /* CHV pipe B */ 4587 #define SP_FORMAT_RGBX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 14) 4588 #define SP_FORMAT_RGBA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 15) 4589 #define SP_ALPHA_PREMULTIPLY REG_BIT(23) /* CHV pipe B */ 4590 #define SP_SOURCE_KEY REG_BIT(22) 4591 #define SP_YUV_FORMAT_BT709 REG_BIT(18) 4592 #define SP_YUV_ORDER_MASK REG_GENMASK(17, 16) 4593 #define SP_YUV_ORDER_YUYV REG_FIELD_PREP(SP_YUV_ORDER_MASK, 0) 4594 #define SP_YUV_ORDER_UYVY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 1) 4595 #define SP_YUV_ORDER_YVYU REG_FIELD_PREP(SP_YUV_ORDER_MASK, 2) 4596 #define SP_YUV_ORDER_VYUY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 3) 4597 #define SP_ROTATE_180 REG_BIT(15) 4598 #define SP_TILED REG_BIT(10) 4599 #define SP_MIRROR REG_BIT(8) /* CHV pipe B */ 4600 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184) 4601 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188) 4602 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c) 4603 #define SP_POS_Y_MASK REG_GENMASK(31, 16) 4604 #define SP_POS_Y(y) REG_FIELD_PREP(SP_POS_Y_MASK, (y)) 4605 #define SP_POS_X_MASK REG_GENMASK(15, 0) 4606 #define SP_POS_X(x) REG_FIELD_PREP(SP_POS_X_MASK, (x)) 4607 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190) 4608 #define SP_HEIGHT_MASK REG_GENMASK(31, 16) 4609 #define SP_HEIGHT(h) REG_FIELD_PREP(SP_HEIGHT_MASK, (h)) 4610 #define SP_WIDTH_MASK REG_GENMASK(15, 0) 4611 #define SP_WIDTH(w) REG_FIELD_PREP(SP_WIDTH_MASK, (w)) 4612 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194) 4613 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198) 4614 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c) 4615 #define SP_ADDR_MASK REG_GENMASK(31, 12) 4616 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0) 4617 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4) 4618 #define SP_OFFSET_Y_MASK REG_GENMASK(31, 16) 4619 #define SP_OFFSET_Y(y) REG_FIELD_PREP(SP_OFFSET_Y_MASK, (y)) 4620 #define SP_OFFSET_X_MASK REG_GENMASK(15, 0) 4621 #define SP_OFFSET_X(x) REG_FIELD_PREP(SP_OFFSET_X_MASK, (x)) 4622 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8) 4623 #define SP_CONST_ALPHA_ENABLE REG_BIT(31) 4624 #define SP_CONST_ALPHA_MASK REG_GENMASK(7, 0) 4625 #define SP_CONST_ALPHA(alpha) REG_FIELD_PREP(SP_CONST_ALPHA_MASK, (alpha)) 4626 #define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0) 4627 #define SP_CONTRAST_MASK REG_GENMASK(26, 18) 4628 #define SP_CONTRAST(x) REG_FIELD_PREP(SP_CONTRAST_MASK, (x)) /* u3.6 */ 4629 #define SP_BRIGHTNESS_MASK REG_GENMASK(7, 0) 4630 #define SP_BRIGHTNESS(x) REG_FIELD_PREP(SP_BRIGHTNESS_MASK, (x)) /* s8 */ 4631 #define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4) 4632 #define SP_SH_SIN_MASK REG_GENMASK(26, 16) 4633 #define SP_SH_SIN(x) REG_FIELD_PREP(SP_SH_SIN_MASK, (x)) /* s4.7 */ 4634 #define SP_SH_COS_MASK REG_GENMASK(9, 0) 4635 #define SP_SH_COS(x) REG_FIELD_PREP(SP_SH_COS_MASK, (x)) /* u3.7 */ 4636 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0) 4637 4638 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280) 4639 #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284) 4640 #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288) 4641 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c) 4642 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290) 4643 #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294) 4644 #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298) 4645 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c) 4646 #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0) 4647 #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4) 4648 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8) 4649 #define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0) 4650 #define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4) 4651 #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0) 4652 4653 #define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \ 4654 _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b)) 4655 #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \ 4656 _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b))) 4657 4658 #define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR) 4659 #define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF) 4660 #define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE) 4661 #define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS) 4662 #define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE) 4663 #define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL) 4664 #define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK) 4665 #define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF) 4666 #define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL) 4667 #define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF) 4668 #define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA) 4669 #define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0) 4670 #define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1) 4671 #define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */ 4672 4673 /* 4674 * CHV pipe B sprite CSC 4675 * 4676 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff| 4677 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff| 4678 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff| 4679 */ 4680 #define _MMIO_CHV_SPCSC(plane_id, reg) \ 4681 _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg)) 4682 4683 #define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900) 4684 #define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904) 4685 #define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908) 4686 #define SPCSC_OOFF_MASK REG_GENMASK(26, 16) 4687 #define SPCSC_OOFF(x) REG_FIELD_PREP(SPCSC_OOFF_MASK, (x) & 0x7ff) /* s11 */ 4688 #define SPCSC_IOFF_MASK REG_GENMASK(10, 0) 4689 #define SPCSC_IOFF(x) REG_FIELD_PREP(SPCSC_IOFF_MASK, (x) & 0x7ff) /* s11 */ 4690 4691 #define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c) 4692 #define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910) 4693 #define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914) 4694 #define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918) 4695 #define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c) 4696 #define SPCSC_C1_MASK REG_GENMASK(30, 16) 4697 #define SPCSC_C1(x) REG_FIELD_PREP(SPCSC_C1_MASK, (x) & 0x7fff) /* s3.12 */ 4698 #define SPCSC_C0_MASK REG_GENMASK(14, 0) 4699 #define SPCSC_C0(x) REG_FIELD_PREP(SPCSC_C0_MASK, (x) & 0x7fff) /* s3.12 */ 4700 4701 #define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920) 4702 #define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924) 4703 #define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928) 4704 #define SPCSC_IMAX_MASK REG_GENMASK(26, 16) 4705 #define SPCSC_IMAX(x) REG_FIELD_PREP(SPCSC_IMAX_MASK, (x) & 0x7ff) /* s11 */ 4706 #define SPCSC_IMIN_MASK REG_GENMASK(10, 0) 4707 #define SPCSC_IMIN(x) REG_FIELD_PREP(SPCSC_IMIN_MASK, (x) & 0x7ff) /* s11 */ 4708 4709 #define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c) 4710 #define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930) 4711 #define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934) 4712 #define SPCSC_OMAX_MASK REG_GENMASK(25, 16) 4713 #define SPCSC_OMAX(x) REG_FIELD_PREP(SPCSC_OMAX_MASK, (x)) /* u10 */ 4714 #define SPCSC_OMIN_MASK REG_GENMASK(9, 0) 4715 #define SPCSC_OMIN(x) REG_FIELD_PREP(SPCSC_OMIN_MASK, (x)) /* u10 */ 4716 4717 /* Skylake plane registers */ 4718 4719 #define _PLANE_CTL_1_A 0x70180 4720 #define _PLANE_CTL_2_A 0x70280 4721 #define _PLANE_CTL_3_A 0x70380 4722 #define PLANE_CTL_ENABLE REG_BIT(31) 4723 #define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ 4724 #define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */ 4725 #define PLANE_CTL_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-GLK */ 4726 #define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) 4727 /* 4728 * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition 4729 * expanded to include bit 23 as well. However, the shift-24 based values 4730 * correctly map to the same formats in ICL, as long as bit 23 is set to 0 4731 */ 4732 #define PLANE_CTL_FORMAT_MASK_SKL REG_GENMASK(27, 24) /* pre-icl */ 4733 #define PLANE_CTL_FORMAT_MASK_ICL REG_GENMASK(27, 23) /* icl+ */ 4734 #define PLANE_CTL_FORMAT_YUV422 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 0) 4735 #define PLANE_CTL_FORMAT_NV12 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 1) 4736 #define PLANE_CTL_FORMAT_XRGB_2101010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 2) 4737 #define PLANE_CTL_FORMAT_P010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 3) 4738 #define PLANE_CTL_FORMAT_XRGB_8888 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 4) 4739 #define PLANE_CTL_FORMAT_P012 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 5) 4740 #define PLANE_CTL_FORMAT_XRGB_16161616F REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 6) 4741 #define PLANE_CTL_FORMAT_P016 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 7) 4742 #define PLANE_CTL_FORMAT_XYUV REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 8) 4743 #define PLANE_CTL_FORMAT_INDEXED REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 12) 4744 #define PLANE_CTL_FORMAT_RGB_565 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 14) 4745 #define PLANE_CTL_FORMAT_Y210 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 1) 4746 #define PLANE_CTL_FORMAT_Y212 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 3) 4747 #define PLANE_CTL_FORMAT_Y216 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 5) 4748 #define PLANE_CTL_FORMAT_Y410 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 7) 4749 #define PLANE_CTL_FORMAT_Y412 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 9) 4750 #define PLANE_CTL_FORMAT_Y416 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 11) 4751 #define PLANE_CTL_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-GLK */ 4752 #define PLANE_CTL_KEY_ENABLE_MASK REG_GENMASK(22, 21) 4753 #define PLANE_CTL_KEY_ENABLE_SOURCE REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 1) 4754 #define PLANE_CTL_KEY_ENABLE_DESTINATION REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 2) 4755 #define PLANE_CTL_ORDER_RGBX REG_BIT(20) 4756 #define PLANE_CTL_YUV420_Y_PLANE REG_BIT(19) 4757 #define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) 4758 #define PLANE_CTL_YUV422_ORDER_MASK REG_GENMASK(17, 16) 4759 #define PLANE_CTL_YUV422_ORDER_YUYV REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 0) 4760 #define PLANE_CTL_YUV422_ORDER_UYVY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 1) 4761 #define PLANE_CTL_YUV422_ORDER_YVYU REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 2) 4762 #define PLANE_CTL_YUV422_ORDER_VYUY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 3) 4763 #define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE REG_BIT(15) 4764 #define PLANE_CTL_TRICKLE_FEED_DISABLE REG_BIT(14) 4765 #define PLANE_CTL_CLEAR_COLOR_DISABLE REG_BIT(13) /* TGL+ */ 4766 #define PLANE_CTL_PLANE_GAMMA_DISABLE REG_BIT(13) /* Pre-GLK */ 4767 #define PLANE_CTL_TILED_MASK REG_GENMASK(12, 10) 4768 #define PLANE_CTL_TILED_LINEAR REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 0) 4769 #define PLANE_CTL_TILED_X REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 1) 4770 #define PLANE_CTL_TILED_Y REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 4) 4771 #define PLANE_CTL_TILED_YF REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5) 4772 #define PLANE_CTL_TILED_4 REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5) 4773 #define PLANE_CTL_ASYNC_FLIP REG_BIT(9) 4774 #define PLANE_CTL_FLIP_HORIZONTAL REG_BIT(8) 4775 #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE REG_BIT(4) /* TGL+ */ 4776 #define PLANE_CTL_ALPHA_MASK REG_GENMASK(5, 4) /* Pre-GLK */ 4777 #define PLANE_CTL_ALPHA_DISABLE REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 0) 4778 #define PLANE_CTL_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 2) 4779 #define PLANE_CTL_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 3) 4780 #define PLANE_CTL_ROTATE_MASK REG_GENMASK(1, 0) 4781 #define PLANE_CTL_ROTATE_0 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 0) 4782 #define PLANE_CTL_ROTATE_90 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1) 4783 #define PLANE_CTL_ROTATE_180 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2) 4784 #define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3) 4785 #define _PLANE_STRIDE_1_A 0x70188 4786 #define _PLANE_STRIDE_2_A 0x70288 4787 #define _PLANE_STRIDE_3_A 0x70388 4788 #define PLANE_STRIDE__MASK REG_GENMASK(11, 0) 4789 #define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride)) 4790 #define _PLANE_POS_1_A 0x7018c 4791 #define _PLANE_POS_2_A 0x7028c 4792 #define _PLANE_POS_3_A 0x7038c 4793 #define PLANE_POS_Y_MASK REG_GENMASK(31, 16) 4794 #define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y)) 4795 #define PLANE_POS_X_MASK REG_GENMASK(15, 0) 4796 #define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x)) 4797 #define _PLANE_SIZE_1_A 0x70190 4798 #define _PLANE_SIZE_2_A 0x70290 4799 #define _PLANE_SIZE_3_A 0x70390 4800 #define PLANE_HEIGHT_MASK REG_GENMASK(31, 16) 4801 #define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h)) 4802 #define PLANE_WIDTH_MASK REG_GENMASK(15, 0) 4803 #define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w)) 4804 #define _PLANE_SURF_1_A 0x7019c 4805 #define _PLANE_SURF_2_A 0x7029c 4806 #define _PLANE_SURF_3_A 0x7039c 4807 #define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12) 4808 #define PLANE_SURF_DECRYPT REG_BIT(2) 4809 #define _PLANE_OFFSET_1_A 0x701a4 4810 #define _PLANE_OFFSET_2_A 0x702a4 4811 #define _PLANE_OFFSET_3_A 0x703a4 4812 #define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16) 4813 #define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y)) 4814 #define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0) 4815 #define PLANE_OFFSET_X(x) REG_FIELD_PREP(PLANE_OFFSET_X_MASK, (x)) 4816 #define _PLANE_KEYVAL_1_A 0x70194 4817 #define _PLANE_KEYVAL_2_A 0x70294 4818 #define _PLANE_KEYMSK_1_A 0x70198 4819 #define _PLANE_KEYMSK_2_A 0x70298 4820 #define PLANE_KEYMSK_ALPHA_ENABLE (1 << 31) 4821 #define _PLANE_KEYMAX_1_A 0x701a0 4822 #define _PLANE_KEYMAX_2_A 0x702a0 4823 #define PLANE_KEYMAX_ALPHA(a) ((a) << 24) 4824 #define _PLANE_CC_VAL_1_A 0x701b4 4825 #define _PLANE_CC_VAL_2_A 0x702b4 4826 #define _PLANE_AUX_DIST_1_A 0x701c0 4827 #define PLANE_AUX_DISTANCE_MASK REG_GENMASK(31, 12) 4828 #define PLANE_AUX_STRIDE_MASK REG_GENMASK(11, 0) 4829 #define PLANE_AUX_STRIDE(stride) REG_FIELD_PREP(PLANE_AUX_STRIDE_MASK, (stride)) 4830 #define _PLANE_AUX_DIST_2_A 0x702c0 4831 #define _PLANE_AUX_OFFSET_1_A 0x701c4 4832 #define _PLANE_AUX_OFFSET_2_A 0x702c4 4833 #define _PLANE_CUS_CTL_1_A 0x701c8 4834 #define _PLANE_CUS_CTL_2_A 0x702c8 4835 #define PLANE_CUS_ENABLE REG_BIT(31) 4836 #define PLANE_CUS_Y_PLANE_MASK REG_BIT(30) 4837 #define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0) 4838 #define PLANE_CUS_Y_PLANE_5_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1) 4839 #define PLANE_CUS_Y_PLANE_6_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0) 4840 #define PLANE_CUS_Y_PLANE_7_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1) 4841 #define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19) 4842 #define PLANE_CUS_HPHASE_MASK REG_GENMASK(17, 16) 4843 #define PLANE_CUS_HPHASE_0 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0) 4844 #define PLANE_CUS_HPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1) 4845 #define PLANE_CUS_HPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2) 4846 #define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15) 4847 #define PLANE_CUS_VPHASE_MASK REG_GENMASK(13, 12) 4848 #define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0) 4849 #define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1) 4850 #define PLANE_CUS_VPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2) 4851 #define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */ 4852 #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */ 4853 #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */ 4854 #define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */ 4855 #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) 4856 #define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */ 4857 #define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21) /* ICL+ */ 4858 #define PLANE_COLOR_INPUT_CSC_ENABLE REG_BIT(20) /* ICL+ */ 4859 #define PLANE_COLOR_CSC_MODE_MASK REG_GENMASK(19, 17) 4860 #define PLANE_COLOR_CSC_MODE_BYPASS REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0) 4861 #define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 1) 4862 #define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 2) 4863 #define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 3) 4864 #define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 4) 4865 #define PLANE_COLOR_PLANE_GAMMA_DISABLE REG_BIT(13) 4866 #define PLANE_COLOR_ALPHA_MASK REG_GENMASK(5, 4) 4867 #define PLANE_COLOR_ALPHA_DISABLE REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0) 4868 #define PLANE_COLOR_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 2) 4869 #define PLANE_COLOR_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 3) 4870 #define _PLANE_BUF_CFG_1_A 0x7027c 4871 #define _PLANE_BUF_CFG_2_A 0x7037c 4872 #define _PLANE_NV12_BUF_CFG_1_A 0x70278 4873 #define _PLANE_NV12_BUF_CFG_2_A 0x70378 4874 4875 #define _PLANE_CC_VAL_1_B 0x711b4 4876 #define _PLANE_CC_VAL_2_B 0x712b4 4877 #define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4) 4878 #define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4) 4879 #define PLANE_CC_VAL(pipe, plane, dw) \ 4880 _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw))) 4881 4882 /* Input CSC Register Definitions */ 4883 #define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0 4884 #define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0 4885 4886 #define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0 4887 #define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0 4888 4889 #define _PLANE_INPUT_CSC_RY_GY_1(pipe) \ 4890 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \ 4891 _PLANE_INPUT_CSC_RY_GY_1_B) 4892 #define _PLANE_INPUT_CSC_RY_GY_2(pipe) \ 4893 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \ 4894 _PLANE_INPUT_CSC_RY_GY_2_B) 4895 4896 #define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \ 4897 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \ 4898 _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4) 4899 4900 #define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8 4901 #define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8 4902 4903 #define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8 4904 #define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8 4905 4906 #define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \ 4907 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \ 4908 _PLANE_INPUT_CSC_PREOFF_HI_1_B) 4909 #define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \ 4910 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \ 4911 _PLANE_INPUT_CSC_PREOFF_HI_2_B) 4912 #define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \ 4913 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \ 4914 _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4) 4915 4916 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204 4917 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304 4918 4919 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204 4920 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304 4921 4922 #define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \ 4923 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \ 4924 _PLANE_INPUT_CSC_POSTOFF_HI_1_B) 4925 #define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \ 4926 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \ 4927 _PLANE_INPUT_CSC_POSTOFF_HI_2_B) 4928 #define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \ 4929 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \ 4930 _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4) 4931 4932 #define _PLANE_CTL_1_B 0x71180 4933 #define _PLANE_CTL_2_B 0x71280 4934 #define _PLANE_CTL_3_B 0x71380 4935 #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B) 4936 #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B) 4937 #define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B) 4938 #define PLANE_CTL(pipe, plane) \ 4939 _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) 4940 4941 #define _PLANE_STRIDE_1_B 0x71188 4942 #define _PLANE_STRIDE_2_B 0x71288 4943 #define _PLANE_STRIDE_3_B 0x71388 4944 #define _PLANE_STRIDE_1(pipe) \ 4945 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B) 4946 #define _PLANE_STRIDE_2(pipe) \ 4947 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) 4948 #define _PLANE_STRIDE_3(pipe) \ 4949 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B) 4950 #define PLANE_STRIDE(pipe, plane) \ 4951 _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) 4952 4953 #define _PLANE_POS_1_B 0x7118c 4954 #define _PLANE_POS_2_B 0x7128c 4955 #define _PLANE_POS_3_B 0x7138c 4956 #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B) 4957 #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B) 4958 #define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B) 4959 #define PLANE_POS(pipe, plane) \ 4960 _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) 4961 4962 #define _PLANE_SIZE_1_B 0x71190 4963 #define _PLANE_SIZE_2_B 0x71290 4964 #define _PLANE_SIZE_3_B 0x71390 4965 #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B) 4966 #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) 4967 #define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B) 4968 #define PLANE_SIZE(pipe, plane) \ 4969 _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) 4970 4971 #define _PLANE_SURF_1_B 0x7119c 4972 #define _PLANE_SURF_2_B 0x7129c 4973 #define _PLANE_SURF_3_B 0x7139c 4974 #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B) 4975 #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B) 4976 #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B) 4977 #define PLANE_SURF(pipe, plane) \ 4978 _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe)) 4979 4980 #define _PLANE_OFFSET_1_B 0x711a4 4981 #define _PLANE_OFFSET_2_B 0x712a4 4982 #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B) 4983 #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B) 4984 #define PLANE_OFFSET(pipe, plane) \ 4985 _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe)) 4986 4987 #define _PLANE_KEYVAL_1_B 0x71194 4988 #define _PLANE_KEYVAL_2_B 0x71294 4989 #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B) 4990 #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B) 4991 #define PLANE_KEYVAL(pipe, plane) \ 4992 _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe)) 4993 4994 #define _PLANE_KEYMSK_1_B 0x71198 4995 #define _PLANE_KEYMSK_2_B 0x71298 4996 #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B) 4997 #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B) 4998 #define PLANE_KEYMSK(pipe, plane) \ 4999 _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe)) 5000 5001 #define _PLANE_KEYMAX_1_B 0x711a0 5002 #define _PLANE_KEYMAX_2_B 0x712a0 5003 #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B) 5004 #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B) 5005 #define PLANE_KEYMAX(pipe, plane) \ 5006 _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe)) 5007 5008 #define _PLANE_BUF_CFG_1_B 0x7127c 5009 #define _PLANE_BUF_CFG_2_B 0x7137c 5010 /* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */ 5011 #define PLANE_BUF_END_MASK REG_GENMASK(27, 16) 5012 #define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end)) 5013 #define PLANE_BUF_START_MASK REG_GENMASK(11, 0) 5014 #define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start)) 5015 #define _PLANE_BUF_CFG_1(pipe) \ 5016 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B) 5017 #define _PLANE_BUF_CFG_2(pipe) \ 5018 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B) 5019 #define PLANE_BUF_CFG(pipe, plane) \ 5020 _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe)) 5021 5022 #define _PLANE_NV12_BUF_CFG_1_B 0x71278 5023 #define _PLANE_NV12_BUF_CFG_2_B 0x71378 5024 #define _PLANE_NV12_BUF_CFG_1(pipe) \ 5025 _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B) 5026 #define _PLANE_NV12_BUF_CFG_2(pipe) \ 5027 _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B) 5028 #define PLANE_NV12_BUF_CFG(pipe, plane) \ 5029 _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe)) 5030 5031 #define _PLANE_AUX_DIST_1_B 0x711c0 5032 #define _PLANE_AUX_DIST_2_B 0x712c0 5033 #define _PLANE_AUX_DIST_1(pipe) \ 5034 _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B) 5035 #define _PLANE_AUX_DIST_2(pipe) \ 5036 _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B) 5037 #define PLANE_AUX_DIST(pipe, plane) \ 5038 _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe)) 5039 5040 #define _PLANE_AUX_OFFSET_1_B 0x711c4 5041 #define _PLANE_AUX_OFFSET_2_B 0x712c4 5042 #define _PLANE_AUX_OFFSET_1(pipe) \ 5043 _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B) 5044 #define _PLANE_AUX_OFFSET_2(pipe) \ 5045 _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B) 5046 #define PLANE_AUX_OFFSET(pipe, plane) \ 5047 _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe)) 5048 5049 #define _PLANE_CUS_CTL_1_B 0x711c8 5050 #define _PLANE_CUS_CTL_2_B 0x712c8 5051 #define _PLANE_CUS_CTL_1(pipe) \ 5052 _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B) 5053 #define _PLANE_CUS_CTL_2(pipe) \ 5054 _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B) 5055 #define PLANE_CUS_CTL(pipe, plane) \ 5056 _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe)) 5057 5058 #define _PLANE_COLOR_CTL_1_B 0x711CC 5059 #define _PLANE_COLOR_CTL_2_B 0x712CC 5060 #define _PLANE_COLOR_CTL_3_B 0x713CC 5061 #define _PLANE_COLOR_CTL_1(pipe) \ 5062 _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B) 5063 #define _PLANE_COLOR_CTL_2(pipe) \ 5064 _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B) 5065 #define PLANE_COLOR_CTL(pipe, plane) \ 5066 _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe)) 5067 5068 #define _SEL_FETCH_PLANE_BASE_1_A 0x70890 5069 #define _SEL_FETCH_PLANE_BASE_2_A 0x708B0 5070 #define _SEL_FETCH_PLANE_BASE_3_A 0x708D0 5071 #define _SEL_FETCH_PLANE_BASE_4_A 0x708F0 5072 #define _SEL_FETCH_PLANE_BASE_5_A 0x70920 5073 #define _SEL_FETCH_PLANE_BASE_6_A 0x70940 5074 #define _SEL_FETCH_PLANE_BASE_7_A 0x70960 5075 #define _SEL_FETCH_PLANE_BASE_CUR_A 0x70880 5076 #define _SEL_FETCH_PLANE_BASE_1_B 0x71890 5077 5078 #define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \ 5079 _SEL_FETCH_PLANE_BASE_1_A, \ 5080 _SEL_FETCH_PLANE_BASE_2_A, \ 5081 _SEL_FETCH_PLANE_BASE_3_A, \ 5082 _SEL_FETCH_PLANE_BASE_4_A, \ 5083 _SEL_FETCH_PLANE_BASE_5_A, \ 5084 _SEL_FETCH_PLANE_BASE_6_A, \ 5085 _SEL_FETCH_PLANE_BASE_7_A, \ 5086 _SEL_FETCH_PLANE_BASE_CUR_A) 5087 #define _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe, _SEL_FETCH_PLANE_BASE_1_A, _SEL_FETCH_PLANE_BASE_1_B) 5088 #define _SEL_FETCH_PLANE_BASE(pipe, plane) (_SEL_FETCH_PLANE_BASE_1(pipe) - \ 5089 _SEL_FETCH_PLANE_BASE_1_A + \ 5090 _SEL_FETCH_PLANE_BASE_A(plane)) 5091 5092 #define _SEL_FETCH_PLANE_CTL_1_A 0x70890 5093 #define PLANE_SEL_FETCH_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 5094 _SEL_FETCH_PLANE_CTL_1_A - \ 5095 _SEL_FETCH_PLANE_BASE_1_A) 5096 #define PLANE_SEL_FETCH_CTL_ENABLE REG_BIT(31) 5097 5098 #define _SEL_FETCH_PLANE_POS_1_A 0x70894 5099 #define PLANE_SEL_FETCH_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 5100 _SEL_FETCH_PLANE_POS_1_A - \ 5101 _SEL_FETCH_PLANE_BASE_1_A) 5102 5103 #define _SEL_FETCH_PLANE_SIZE_1_A 0x70898 5104 #define PLANE_SEL_FETCH_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 5105 _SEL_FETCH_PLANE_SIZE_1_A - \ 5106 _SEL_FETCH_PLANE_BASE_1_A) 5107 5108 #define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089C 5109 #define PLANE_SEL_FETCH_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 5110 _SEL_FETCH_PLANE_OFFSET_1_A - \ 5111 _SEL_FETCH_PLANE_BASE_1_A) 5112 5113 /* SKL new cursor registers */ 5114 #define _CUR_BUF_CFG_A 0x7017c 5115 #define _CUR_BUF_CFG_B 0x7117c 5116 #define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B) 5117 5118 /* VBIOS regs */ 5119 #define VGACNTRL _MMIO(0x71400) 5120 # define VGA_DISP_DISABLE (1 << 31) 5121 # define VGA_2X_MODE (1 << 30) 5122 # define VGA_PIPE_B_SELECT (1 << 29) 5123 5124 #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400) 5125 5126 /* Ironlake */ 5127 5128 #define CPU_VGACNTRL _MMIO(0x41000) 5129 5130 #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030) 5131 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) 5132 #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */ 5133 #define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */ 5134 #define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */ 5135 #define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */ 5136 #define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */ 5137 #define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0) 5138 #define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0) 5139 #define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0) 5140 #define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0) 5141 5142 /* refresh rate hardware control */ 5143 #define RR_HW_CTL _MMIO(0x45300) 5144 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff 5145 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 5146 5147 #define FDI_PLL_BIOS_0 _MMIO(0x46000) 5148 #define FDI_PLL_FB_CLOCK_MASK 0xff 5149 #define FDI_PLL_BIOS_1 _MMIO(0x46004) 5150 #define FDI_PLL_BIOS_2 _MMIO(0x46008) 5151 #define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c) 5152 #define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010) 5153 #define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014) 5154 5155 #define PCH_3DCGDIS0 _MMIO(0x46020) 5156 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) 5157 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) 5158 5159 #define PCH_3DCGDIS1 _MMIO(0x46024) 5160 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) 5161 5162 #define FDI_PLL_FREQ_CTL _MMIO(0x46030) 5163 #define FDI_PLL_FREQ_CHANGE_REQUEST (1 << 24) 5164 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 5165 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff 5166 5167 5168 #define _PIPEA_DATA_M1 0x60030 5169 #define _PIPEA_DATA_N1 0x60034 5170 #define _PIPEA_DATA_M2 0x60038 5171 #define _PIPEA_DATA_N2 0x6003c 5172 #define _PIPEA_LINK_M1 0x60040 5173 #define _PIPEA_LINK_N1 0x60044 5174 #define _PIPEA_LINK_M2 0x60048 5175 #define _PIPEA_LINK_N2 0x6004c 5176 5177 /* PIPEB timing regs are same start from 0x61000 */ 5178 5179 #define _PIPEB_DATA_M1 0x61030 5180 #define _PIPEB_DATA_N1 0x61034 5181 #define _PIPEB_DATA_M2 0x61038 5182 #define _PIPEB_DATA_N2 0x6103c 5183 #define _PIPEB_LINK_M1 0x61040 5184 #define _PIPEB_LINK_N1 0x61044 5185 #define _PIPEB_LINK_M2 0x61048 5186 #define _PIPEB_LINK_N2 0x6104c 5187 5188 #define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1) 5189 #define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1) 5190 #define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2) 5191 #define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2) 5192 #define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1) 5193 #define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1) 5194 #define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2) 5195 #define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2) 5196 5197 /* CPU panel fitter */ 5198 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ 5199 #define _PFA_CTL_1 0x68080 5200 #define _PFB_CTL_1 0x68880 5201 #define PF_ENABLE (1 << 31) 5202 #define PF_PIPE_SEL_MASK_IVB (3 << 29) 5203 #define PF_PIPE_SEL_IVB(pipe) ((pipe) << 29) 5204 #define PF_FILTER_MASK (3 << 23) 5205 #define PF_FILTER_PROGRAMMED (0 << 23) 5206 #define PF_FILTER_MED_3x3 (1 << 23) 5207 #define PF_FILTER_EDGE_ENHANCE (2 << 23) 5208 #define PF_FILTER_EDGE_SOFTEN (3 << 23) 5209 #define _PFA_WIN_SZ 0x68074 5210 #define _PFB_WIN_SZ 0x68874 5211 #define _PFA_WIN_POS 0x68070 5212 #define _PFB_WIN_POS 0x68870 5213 #define _PFA_VSCALE 0x68084 5214 #define _PFB_VSCALE 0x68884 5215 #define _PFA_HSCALE 0x68090 5216 #define _PFB_HSCALE 0x68890 5217 5218 #define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) 5219 #define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) 5220 #define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) 5221 #define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) 5222 #define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) 5223 5224 #define _PSA_CTL 0x68180 5225 #define _PSB_CTL 0x68980 5226 #define PS_ENABLE (1 << 31) 5227 #define _PSA_WIN_SZ 0x68174 5228 #define _PSB_WIN_SZ 0x68974 5229 #define _PSA_WIN_POS 0x68170 5230 #define _PSB_WIN_POS 0x68970 5231 5232 #define PS_CTL(pipe) _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL) 5233 #define PS_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ) 5234 #define PS_WIN_POS(pipe) _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS) 5235 5236 /* 5237 * Skylake scalers 5238 */ 5239 #define _PS_1A_CTRL 0x68180 5240 #define _PS_2A_CTRL 0x68280 5241 #define _PS_1B_CTRL 0x68980 5242 #define _PS_2B_CTRL 0x68A80 5243 #define _PS_1C_CTRL 0x69180 5244 #define PS_SCALER_EN (1 << 31) 5245 #define SKL_PS_SCALER_MODE_MASK (3 << 28) 5246 #define SKL_PS_SCALER_MODE_DYN (0 << 28) 5247 #define SKL_PS_SCALER_MODE_HQ (1 << 28) 5248 #define SKL_PS_SCALER_MODE_NV12 (2 << 28) 5249 #define PS_SCALER_MODE_PLANAR (1 << 29) 5250 #define PS_SCALER_MODE_NORMAL (0 << 29) 5251 #define PS_PLANE_SEL_MASK (7 << 25) 5252 #define PS_PLANE_SEL(plane) (((plane) + 1) << 25) 5253 #define PS_FILTER_MASK (3 << 23) 5254 #define PS_FILTER_MEDIUM (0 << 23) 5255 #define PS_FILTER_PROGRAMMED (1 << 23) 5256 #define PS_FILTER_EDGE_ENHANCE (2 << 23) 5257 #define PS_FILTER_BILINEAR (3 << 23) 5258 #define PS_VERT3TAP (1 << 21) 5259 #define PS_VERT_INT_INVERT_FIELD1 (0 << 20) 5260 #define PS_VERT_INT_INVERT_FIELD0 (1 << 20) 5261 #define PS_PWRUP_PROGRESS (1 << 17) 5262 #define PS_V_FILTER_BYPASS (1 << 8) 5263 #define PS_VADAPT_EN (1 << 7) 5264 #define PS_VADAPT_MODE_MASK (3 << 5) 5265 #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5) 5266 #define PS_VADAPT_MODE_MOD_ADAPT (1 << 5) 5267 #define PS_VADAPT_MODE_MOST_ADAPT (3 << 5) 5268 #define PS_PLANE_Y_SEL_MASK (7 << 5) 5269 #define PS_PLANE_Y_SEL(plane) (((plane) + 1) << 5) 5270 #define PS_Y_VERT_FILTER_SELECT(set) ((set) << 4) 5271 #define PS_Y_HORZ_FILTER_SELECT(set) ((set) << 3) 5272 #define PS_UV_VERT_FILTER_SELECT(set) ((set) << 2) 5273 #define PS_UV_HORZ_FILTER_SELECT(set) ((set) << 1) 5274 5275 #define _PS_PWR_GATE_1A 0x68160 5276 #define _PS_PWR_GATE_2A 0x68260 5277 #define _PS_PWR_GATE_1B 0x68960 5278 #define _PS_PWR_GATE_2B 0x68A60 5279 #define _PS_PWR_GATE_1C 0x69160 5280 #define PS_PWR_GATE_DIS_OVERRIDE (1 << 31) 5281 #define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3) 5282 #define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3) 5283 #define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3) 5284 #define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3) 5285 #define PS_PWR_GATE_SLPEN_8 0 5286 #define PS_PWR_GATE_SLPEN_16 1 5287 #define PS_PWR_GATE_SLPEN_24 2 5288 #define PS_PWR_GATE_SLPEN_32 3 5289 5290 #define _PS_WIN_POS_1A 0x68170 5291 #define _PS_WIN_POS_2A 0x68270 5292 #define _PS_WIN_POS_1B 0x68970 5293 #define _PS_WIN_POS_2B 0x68A70 5294 #define _PS_WIN_POS_1C 0x69170 5295 5296 #define _PS_WIN_SZ_1A 0x68174 5297 #define _PS_WIN_SZ_2A 0x68274 5298 #define _PS_WIN_SZ_1B 0x68974 5299 #define _PS_WIN_SZ_2B 0x68A74 5300 #define _PS_WIN_SZ_1C 0x69174 5301 5302 #define _PS_VSCALE_1A 0x68184 5303 #define _PS_VSCALE_2A 0x68284 5304 #define _PS_VSCALE_1B 0x68984 5305 #define _PS_VSCALE_2B 0x68A84 5306 #define _PS_VSCALE_1C 0x69184 5307 5308 #define _PS_HSCALE_1A 0x68190 5309 #define _PS_HSCALE_2A 0x68290 5310 #define _PS_HSCALE_1B 0x68990 5311 #define _PS_HSCALE_2B 0x68A90 5312 #define _PS_HSCALE_1C 0x69190 5313 5314 #define _PS_VPHASE_1A 0x68188 5315 #define _PS_VPHASE_2A 0x68288 5316 #define _PS_VPHASE_1B 0x68988 5317 #define _PS_VPHASE_2B 0x68A88 5318 #define _PS_VPHASE_1C 0x69188 5319 #define PS_Y_PHASE(x) ((x) << 16) 5320 #define PS_UV_RGB_PHASE(x) ((x) << 0) 5321 #define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */ 5322 #define PS_PHASE_TRIP (1 << 0) 5323 5324 #define _PS_HPHASE_1A 0x68194 5325 #define _PS_HPHASE_2A 0x68294 5326 #define _PS_HPHASE_1B 0x68994 5327 #define _PS_HPHASE_2B 0x68A94 5328 #define _PS_HPHASE_1C 0x69194 5329 5330 #define _PS_ECC_STAT_1A 0x681D0 5331 #define _PS_ECC_STAT_2A 0x682D0 5332 #define _PS_ECC_STAT_1B 0x689D0 5333 #define _PS_ECC_STAT_2B 0x68AD0 5334 #define _PS_ECC_STAT_1C 0x691D0 5335 5336 #define _PS_COEF_SET0_INDEX_1A 0x68198 5337 #define _PS_COEF_SET0_INDEX_2A 0x68298 5338 #define _PS_COEF_SET0_INDEX_1B 0x68998 5339 #define _PS_COEF_SET0_INDEX_2B 0x68A98 5340 #define PS_COEE_INDEX_AUTO_INC (1 << 10) 5341 5342 #define _PS_COEF_SET0_DATA_1A 0x6819C 5343 #define _PS_COEF_SET0_DATA_2A 0x6829C 5344 #define _PS_COEF_SET0_DATA_1B 0x6899C 5345 #define _PS_COEF_SET0_DATA_2B 0x68A9C 5346 5347 #define _ID(id, a, b) _PICK_EVEN(id, a, b) 5348 #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \ 5349 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \ 5350 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL)) 5351 #define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \ 5352 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \ 5353 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B)) 5354 #define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \ 5355 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \ 5356 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B)) 5357 #define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \ 5358 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \ 5359 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B)) 5360 #define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \ 5361 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \ 5362 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B)) 5363 #define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \ 5364 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \ 5365 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B)) 5366 #define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \ 5367 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \ 5368 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B)) 5369 #define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \ 5370 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \ 5371 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B)) 5372 #define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \ 5373 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \ 5374 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)) 5375 #define GLK_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe, \ 5376 _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) + (set) * 8, \ 5377 _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) + (set) * 8) 5378 5379 #define GLK_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \ 5380 _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \ 5381 _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8) 5382 /* legacy palette */ 5383 #define _LGC_PALETTE_A 0x4a000 5384 #define _LGC_PALETTE_B 0x4a800 5385 #define LGC_PALETTE_RED_MASK REG_GENMASK(23, 16) 5386 #define LGC_PALETTE_GREEN_MASK REG_GENMASK(15, 8) 5387 #define LGC_PALETTE_BLUE_MASK REG_GENMASK(7, 0) 5388 #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4) 5389 5390 /* ilk/snb precision palette */ 5391 #define _PREC_PALETTE_A 0x4b000 5392 #define _PREC_PALETTE_B 0x4c000 5393 #define PREC_PALETTE_RED_MASK REG_GENMASK(29, 20) 5394 #define PREC_PALETTE_GREEN_MASK REG_GENMASK(19, 10) 5395 #define PREC_PALETTE_BLUE_MASK REG_GENMASK(9, 0) 5396 #define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4) 5397 5398 #define _PREC_PIPEAGCMAX 0x4d000 5399 #define _PREC_PIPEBGCMAX 0x4d010 5400 #define PREC_PIPEGCMAX(pipe, i) _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4) 5401 5402 #define _GAMMA_MODE_A 0x4a480 5403 #define _GAMMA_MODE_B 0x4ac80 5404 #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) 5405 #define PRE_CSC_GAMMA_ENABLE (1 << 31) 5406 #define POST_CSC_GAMMA_ENABLE (1 << 30) 5407 #define GAMMA_MODE_MODE_MASK (3 << 0) 5408 #define GAMMA_MODE_MODE_8BIT (0 << 0) 5409 #define GAMMA_MODE_MODE_10BIT (1 << 0) 5410 #define GAMMA_MODE_MODE_12BIT (2 << 0) 5411 #define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */ 5412 #define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + */ 5413 5414 /* Display Internal Timeout Register */ 5415 #define RM_TIMEOUT _MMIO(0x42060) 5416 #define MMIO_TIMEOUT_US(us) ((us) << 0) 5417 5418 /* interrupts */ 5419 #define DE_MASTER_IRQ_CONTROL (1 << 31) 5420 #define DE_SPRITEB_FLIP_DONE (1 << 29) 5421 #define DE_SPRITEA_FLIP_DONE (1 << 28) 5422 #define DE_PLANEB_FLIP_DONE (1 << 27) 5423 #define DE_PLANEA_FLIP_DONE (1 << 26) 5424 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane))) 5425 #define DE_PCU_EVENT (1 << 25) 5426 #define DE_GTT_FAULT (1 << 24) 5427 #define DE_POISON (1 << 23) 5428 #define DE_PERFORM_COUNTER (1 << 22) 5429 #define DE_PCH_EVENT (1 << 21) 5430 #define DE_AUX_CHANNEL_A (1 << 20) 5431 #define DE_DP_A_HOTPLUG (1 << 19) 5432 #define DE_GSE (1 << 18) 5433 #define DE_PIPEB_VBLANK (1 << 15) 5434 #define DE_PIPEB_EVEN_FIELD (1 << 14) 5435 #define DE_PIPEB_ODD_FIELD (1 << 13) 5436 #define DE_PIPEB_LINE_COMPARE (1 << 12) 5437 #define DE_PIPEB_VSYNC (1 << 11) 5438 #define DE_PIPEB_CRC_DONE (1 << 10) 5439 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) 5440 #define DE_PIPEA_VBLANK (1 << 7) 5441 #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe))) 5442 #define DE_PIPEA_EVEN_FIELD (1 << 6) 5443 #define DE_PIPEA_ODD_FIELD (1 << 5) 5444 #define DE_PIPEA_LINE_COMPARE (1 << 4) 5445 #define DE_PIPEA_VSYNC (1 << 3) 5446 #define DE_PIPEA_CRC_DONE (1 << 2) 5447 #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe))) 5448 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) 5449 #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe))) 5450 5451 /* More Ivybridge lolz */ 5452 #define DE_ERR_INT_IVB (1 << 30) 5453 #define DE_GSE_IVB (1 << 29) 5454 #define DE_PCH_EVENT_IVB (1 << 28) 5455 #define DE_DP_A_HOTPLUG_IVB (1 << 27) 5456 #define DE_AUX_CHANNEL_A_IVB (1 << 26) 5457 #define DE_EDP_PSR_INT_HSW (1 << 19) 5458 #define DE_SPRITEC_FLIP_DONE_IVB (1 << 14) 5459 #define DE_PLANEC_FLIP_DONE_IVB (1 << 13) 5460 #define DE_PIPEC_VBLANK_IVB (1 << 10) 5461 #define DE_SPRITEB_FLIP_DONE_IVB (1 << 9) 5462 #define DE_PLANEB_FLIP_DONE_IVB (1 << 8) 5463 #define DE_PIPEB_VBLANK_IVB (1 << 5) 5464 #define DE_SPRITEA_FLIP_DONE_IVB (1 << 4) 5465 #define DE_PLANEA_FLIP_DONE_IVB (1 << 3) 5466 #define DE_PLANE_FLIP_DONE_IVB(plane) (1 << (3 + 5 * (plane))) 5467 #define DE_PIPEA_VBLANK_IVB (1 << 0) 5468 #define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5)) 5469 5470 #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */ 5471 #define MASTER_INTERRUPT_ENABLE (1 << 31) 5472 5473 #define DEISR _MMIO(0x44000) 5474 #define DEIMR _MMIO(0x44004) 5475 #define DEIIR _MMIO(0x44008) 5476 #define DEIER _MMIO(0x4400c) 5477 5478 #define GTISR _MMIO(0x44010) 5479 #define GTIMR _MMIO(0x44014) 5480 #define GTIIR _MMIO(0x44018) 5481 #define GTIER _MMIO(0x4401c) 5482 5483 #define GEN8_MASTER_IRQ _MMIO(0x44200) 5484 #define GEN8_MASTER_IRQ_CONTROL (1 << 31) 5485 #define GEN8_PCU_IRQ (1 << 30) 5486 #define GEN8_DE_PCH_IRQ (1 << 23) 5487 #define GEN8_DE_MISC_IRQ (1 << 22) 5488 #define GEN8_DE_PORT_IRQ (1 << 20) 5489 #define GEN8_DE_PIPE_C_IRQ (1 << 18) 5490 #define GEN8_DE_PIPE_B_IRQ (1 << 17) 5491 #define GEN8_DE_PIPE_A_IRQ (1 << 16) 5492 #define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe))) 5493 #define GEN8_GT_VECS_IRQ (1 << 6) 5494 #define GEN8_GT_GUC_IRQ (1 << 5) 5495 #define GEN8_GT_PM_IRQ (1 << 4) 5496 #define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */ 5497 #define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */ 5498 #define GEN8_GT_BCS_IRQ (1 << 1) 5499 #define GEN8_GT_RCS_IRQ (1 << 0) 5500 5501 #define XELPD_DISPLAY_ERR_FATAL_MASK _MMIO(0x4421c) 5502 5503 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which))) 5504 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which))) 5505 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which))) 5506 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which))) 5507 5508 #define GEN8_RCS_IRQ_SHIFT 0 5509 #define GEN8_BCS_IRQ_SHIFT 16 5510 #define GEN8_VCS0_IRQ_SHIFT 0 /* NB: VCS1 in bspec! */ 5511 #define GEN8_VCS1_IRQ_SHIFT 16 /* NB: VCS2 in bpsec! */ 5512 #define GEN8_VECS_IRQ_SHIFT 0 5513 #define GEN8_WD_IRQ_SHIFT 16 5514 5515 #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe))) 5516 #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe))) 5517 #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe))) 5518 #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe))) 5519 #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31) 5520 #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29) 5521 #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28) 5522 #define XELPD_PIPE_SOFT_UNDERRUN (1 << 22) 5523 #define XELPD_PIPE_HARD_UNDERRUN (1 << 21) 5524 #define GEN8_PIPE_CURSOR_FAULT (1 << 10) 5525 #define GEN8_PIPE_SPRITE_FAULT (1 << 9) 5526 #define GEN8_PIPE_PRIMARY_FAULT (1 << 8) 5527 #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5) 5528 #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4) 5529 #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) 5530 #define GEN8_PIPE_VSYNC (1 << 1) 5531 #define GEN8_PIPE_VBLANK (1 << 0) 5532 #define GEN9_PIPE_CURSOR_FAULT (1 << 11) 5533 #define GEN11_PIPE_PLANE7_FAULT (1 << 22) 5534 #define GEN11_PIPE_PLANE6_FAULT (1 << 21) 5535 #define GEN11_PIPE_PLANE5_FAULT (1 << 20) 5536 #define GEN9_PIPE_PLANE4_FAULT (1 << 10) 5537 #define GEN9_PIPE_PLANE3_FAULT (1 << 9) 5538 #define GEN9_PIPE_PLANE2_FAULT (1 << 8) 5539 #define GEN9_PIPE_PLANE1_FAULT (1 << 7) 5540 #define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6) 5541 #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5) 5542 #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4) 5543 #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3) 5544 #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p))) 5545 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ 5546 (GEN8_PIPE_CURSOR_FAULT | \ 5547 GEN8_PIPE_SPRITE_FAULT | \ 5548 GEN8_PIPE_PRIMARY_FAULT) 5549 #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \ 5550 (GEN9_PIPE_CURSOR_FAULT | \ 5551 GEN9_PIPE_PLANE4_FAULT | \ 5552 GEN9_PIPE_PLANE3_FAULT | \ 5553 GEN9_PIPE_PLANE2_FAULT | \ 5554 GEN9_PIPE_PLANE1_FAULT) 5555 #define GEN11_DE_PIPE_IRQ_FAULT_ERRORS \ 5556 (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \ 5557 GEN11_PIPE_PLANE7_FAULT | \ 5558 GEN11_PIPE_PLANE6_FAULT | \ 5559 GEN11_PIPE_PLANE5_FAULT) 5560 #define RKL_DE_PIPE_IRQ_FAULT_ERRORS \ 5561 (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \ 5562 GEN11_PIPE_PLANE5_FAULT) 5563 5564 #define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A) 5565 #define _HPD_PIN_TC(hpd_pin) ((hpd_pin) - HPD_PORT_TC1) 5566 5567 #define GEN8_DE_PORT_ISR _MMIO(0x44440) 5568 #define GEN8_DE_PORT_IMR _MMIO(0x44444) 5569 #define GEN8_DE_PORT_IIR _MMIO(0x44448) 5570 #define GEN8_DE_PORT_IER _MMIO(0x4444c) 5571 #define DSI1_NON_TE (1 << 31) 5572 #define DSI0_NON_TE (1 << 30) 5573 #define ICL_AUX_CHANNEL_E (1 << 29) 5574 #define ICL_AUX_CHANNEL_F (1 << 28) 5575 #define GEN9_AUX_CHANNEL_D (1 << 27) 5576 #define GEN9_AUX_CHANNEL_C (1 << 26) 5577 #define GEN9_AUX_CHANNEL_B (1 << 25) 5578 #define DSI1_TE (1 << 24) 5579 #define DSI0_TE (1 << 23) 5580 #define GEN8_DE_PORT_HOTPLUG(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin)) 5581 #define BXT_DE_PORT_HOTPLUG_MASK (GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \ 5582 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \ 5583 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)) 5584 #define BDW_DE_PORT_HOTPLUG_MASK GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) 5585 #define BXT_DE_PORT_GMBUS (1 << 1) 5586 #define GEN8_AUX_CHANNEL_A (1 << 0) 5587 #define TGL_DE_PORT_AUX_USBC6 REG_BIT(13) 5588 #define XELPD_DE_PORT_AUX_DDIE REG_BIT(13) 5589 #define TGL_DE_PORT_AUX_USBC5 REG_BIT(12) 5590 #define XELPD_DE_PORT_AUX_DDID REG_BIT(12) 5591 #define TGL_DE_PORT_AUX_USBC4 REG_BIT(11) 5592 #define TGL_DE_PORT_AUX_USBC3 REG_BIT(10) 5593 #define TGL_DE_PORT_AUX_USBC2 REG_BIT(9) 5594 #define TGL_DE_PORT_AUX_USBC1 REG_BIT(8) 5595 #define TGL_DE_PORT_AUX_DDIC REG_BIT(2) 5596 #define TGL_DE_PORT_AUX_DDIB REG_BIT(1) 5597 #define TGL_DE_PORT_AUX_DDIA REG_BIT(0) 5598 5599 #define GEN8_DE_MISC_ISR _MMIO(0x44460) 5600 #define GEN8_DE_MISC_IMR _MMIO(0x44464) 5601 #define GEN8_DE_MISC_IIR _MMIO(0x44468) 5602 #define GEN8_DE_MISC_IER _MMIO(0x4446c) 5603 #define GEN8_DE_MISC_GSE (1 << 27) 5604 #define GEN8_DE_EDP_PSR (1 << 19) 5605 5606 #define GEN8_PCU_ISR _MMIO(0x444e0) 5607 #define GEN8_PCU_IMR _MMIO(0x444e4) 5608 #define GEN8_PCU_IIR _MMIO(0x444e8) 5609 #define GEN8_PCU_IER _MMIO(0x444ec) 5610 5611 #define GEN11_GU_MISC_ISR _MMIO(0x444f0) 5612 #define GEN11_GU_MISC_IMR _MMIO(0x444f4) 5613 #define GEN11_GU_MISC_IIR _MMIO(0x444f8) 5614 #define GEN11_GU_MISC_IER _MMIO(0x444fc) 5615 #define GEN11_GU_MISC_GSE (1 << 27) 5616 5617 #define GEN11_GFX_MSTR_IRQ _MMIO(0x190010) 5618 #define GEN11_MASTER_IRQ (1 << 31) 5619 #define GEN11_PCU_IRQ (1 << 30) 5620 #define GEN11_GU_MISC_IRQ (1 << 29) 5621 #define GEN11_DISPLAY_IRQ (1 << 16) 5622 #define GEN11_GT_DW_IRQ(x) (1 << (x)) 5623 #define GEN11_GT_DW1_IRQ (1 << 1) 5624 #define GEN11_GT_DW0_IRQ (1 << 0) 5625 5626 #define DG1_MSTR_TILE_INTR _MMIO(0x190008) 5627 #define DG1_MSTR_IRQ REG_BIT(31) 5628 #define DG1_MSTR_TILE(t) REG_BIT(t) 5629 5630 #define GEN11_DISPLAY_INT_CTL _MMIO(0x44200) 5631 #define GEN11_DISPLAY_IRQ_ENABLE (1 << 31) 5632 #define GEN11_AUDIO_CODEC_IRQ (1 << 24) 5633 #define GEN11_DE_PCH_IRQ (1 << 23) 5634 #define GEN11_DE_MISC_IRQ (1 << 22) 5635 #define GEN11_DE_HPD_IRQ (1 << 21) 5636 #define GEN11_DE_PORT_IRQ (1 << 20) 5637 #define GEN11_DE_PIPE_C (1 << 18) 5638 #define GEN11_DE_PIPE_B (1 << 17) 5639 #define GEN11_DE_PIPE_A (1 << 16) 5640 5641 #define GEN11_DE_HPD_ISR _MMIO(0x44470) 5642 #define GEN11_DE_HPD_IMR _MMIO(0x44474) 5643 #define GEN11_DE_HPD_IIR _MMIO(0x44478) 5644 #define GEN11_DE_HPD_IER _MMIO(0x4447c) 5645 #define GEN11_TC_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin)) 5646 #define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(HPD_PORT_TC6) | \ 5647 GEN11_TC_HOTPLUG(HPD_PORT_TC5) | \ 5648 GEN11_TC_HOTPLUG(HPD_PORT_TC4) | \ 5649 GEN11_TC_HOTPLUG(HPD_PORT_TC3) | \ 5650 GEN11_TC_HOTPLUG(HPD_PORT_TC2) | \ 5651 GEN11_TC_HOTPLUG(HPD_PORT_TC1)) 5652 #define GEN11_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin)) 5653 #define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(HPD_PORT_TC6) | \ 5654 GEN11_TBT_HOTPLUG(HPD_PORT_TC5) | \ 5655 GEN11_TBT_HOTPLUG(HPD_PORT_TC4) | \ 5656 GEN11_TBT_HOTPLUG(HPD_PORT_TC3) | \ 5657 GEN11_TBT_HOTPLUG(HPD_PORT_TC2) | \ 5658 GEN11_TBT_HOTPLUG(HPD_PORT_TC1)) 5659 5660 #define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030) 5661 #define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038) 5662 #define GEN11_HOTPLUG_CTL_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4)) 5663 #define GEN11_HOTPLUG_CTL_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4)) 5664 #define GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4)) 5665 #define GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin) (0 << (_HPD_PIN_TC(hpd_pin) * 4)) 5666 5667 #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004) 5668 /* Required on all Ironlake and Sandybridge according to the B-Spec. */ 5669 #define ILK_ELPIN_409_SELECT (1 << 25) 5670 #define ILK_DPARB_GATE (1 << 22) 5671 #define ILK_VSDPFD_FULL (1 << 21) 5672 #define FUSE_STRAP _MMIO(0x42014) 5673 #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31) 5674 #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30) 5675 #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29) 5676 #define IVB_PIPE_C_DISABLE (1 << 28) 5677 #define ILK_HDCP_DISABLE (1 << 25) 5678 #define ILK_eDP_A_DISABLE (1 << 24) 5679 #define HSW_CDCLK_LIMIT (1 << 24) 5680 #define ILK_DESKTOP (1 << 23) 5681 #define HSW_CPU_SSC_ENABLE (1 << 21) 5682 5683 #define FUSE_STRAP3 _MMIO(0x42020) 5684 #define HSW_REF_CLK_SELECT (1 << 1) 5685 5686 #define ILK_DSPCLK_GATE_D _MMIO(0x42020) 5687 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) 5688 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) 5689 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8) 5690 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7) 5691 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5) 5692 5693 #define IVB_CHICKEN3 _MMIO(0x4200c) 5694 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) 5695 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) 5696 5697 #define CHICKEN_PAR1_1 _MMIO(0x42080) 5698 #define IGNORE_KVMR_PIPE_A REG_BIT(23) 5699 #define KBL_ARB_FILL_SPARE_22 REG_BIT(22) 5700 #define DIS_RAM_BYPASS_PSR2_MAN_TRACK (1 << 16) 5701 #define SKL_DE_COMPRESSED_HASH_MODE (1 << 15) 5702 #define DPA_MASK_VBLANK_SRD (1 << 15) 5703 #define FORCE_ARB_IDLE_PLANES (1 << 14) 5704 #define SKL_EDP_PSR_FIX_RDWRAP (1 << 3) 5705 #define IGNORE_PSR2_HW_TRACKING (1 << 1) 5706 5707 #define CHICKEN_PAR2_1 _MMIO(0x42090) 5708 #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14) 5709 5710 #define CHICKEN_MISC_2 _MMIO(0x42084) 5711 #define KBL_ARB_FILL_SPARE_14 REG_BIT(14) 5712 #define KBL_ARB_FILL_SPARE_13 REG_BIT(13) 5713 #define GLK_CL2_PWR_DOWN (1 << 12) 5714 #define GLK_CL1_PWR_DOWN (1 << 11) 5715 #define GLK_CL0_PWR_DOWN (1 << 10) 5716 5717 #define CHICKEN_MISC_4 _MMIO(0x4208c) 5718 #define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13) 5719 #define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0) 5720 #define CHICKEN_FBC_STRIDE(x) REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x)) 5721 5722 #define _CHICKEN_PIPESL_1_A 0x420b0 5723 #define _CHICKEN_PIPESL_1_B 0x420b4 5724 #define HSW_PRI_STRETCH_MAX_MASK REG_GENMASK(28, 27) 5725 #define HSW_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0) 5726 #define HSW_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1) 5727 #define HSW_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2) 5728 #define HSW_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3) 5729 #define HSW_SPR_STRETCH_MAX_MASK REG_GENMASK(26, 25) 5730 #define HSW_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0) 5731 #define HSW_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1) 5732 #define HSW_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2) 5733 #define HSW_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3) 5734 #define HSW_FBCQ_DIS (1 << 22) 5735 #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0) 5736 #define SKL_PLANE1_STRETCH_MAX_MASK REG_GENMASK(1, 0) 5737 #define SKL_PLANE1_STRETCH_MAX_X8 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0) 5738 #define SKL_PLANE1_STRETCH_MAX_X4 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1) 5739 #define SKL_PLANE1_STRETCH_MAX_X2 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2) 5740 #define SKL_PLANE1_STRETCH_MAX_X1 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3) 5741 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) 5742 5743 #define _CHICKEN_TRANS_A 0x420c0 5744 #define _CHICKEN_TRANS_B 0x420c4 5745 #define _CHICKEN_TRANS_C 0x420c8 5746 #define _CHICKEN_TRANS_EDP 0x420cc 5747 #define _CHICKEN_TRANS_D 0x420d8 5748 #define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \ 5749 [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \ 5750 [TRANSCODER_A] = _CHICKEN_TRANS_A, \ 5751 [TRANSCODER_B] = _CHICKEN_TRANS_B, \ 5752 [TRANSCODER_C] = _CHICKEN_TRANS_C, \ 5753 [TRANSCODER_D] = _CHICKEN_TRANS_D)) 5754 5755 #define _MTL_CHICKEN_TRANS_A 0x604e0 5756 #define _MTL_CHICKEN_TRANS_B 0x614e0 5757 #define MTL_CHICKEN_TRANS(trans) _MMIO_TRANS((trans), \ 5758 _MTL_CHICKEN_TRANS_A, \ 5759 _MTL_CHICKEN_TRANS_B) 5760 5761 #define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) 5762 #define HSW_FRAME_START_DELAY(x) REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x) 5763 #define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */ 5764 #define FECSTALL_DIS_DPTSTREAM_DPTTG REG_BIT(23) 5765 #define DDI_TRAINING_OVERRIDE_ENABLE REG_BIT(19) 5766 #define ADLP_1_BASED_X_GRANULARITY REG_BIT(18) 5767 #define DDI_TRAINING_OVERRIDE_VALUE REG_BIT(18) 5768 #define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /* CHICKEN_TRANS_A only */ 5769 #define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */ 5770 #define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15) 5771 #define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12) 5772 5773 #define DISP_ARB_CTL _MMIO(0x45000) 5774 #define DISP_FBC_MEMORY_WAKE (1 << 31) 5775 #define DISP_TILE_SURFACE_SWIZZLING (1 << 13) 5776 #define DISP_FBC_WM_DIS (1 << 15) 5777 #define DISP_ARB_CTL2 _MMIO(0x45004) 5778 #define DISP_DATA_PARTITION_5_6 (1 << 6) 5779 #define DISP_IPC_ENABLE (1 << 3) 5780 5781 /* 5782 * The below are numbered starting from "S1" on gen11/gen12, but starting 5783 * with display 13, the bspec switches to a 0-based numbering scheme 5784 * (although the addresses stay the same so new S0 = old S1, new S1 = old S2). 5785 * We'll just use the 0-based numbering here for all platforms since it's the 5786 * way things will be named by the hardware team going forward, plus it's more 5787 * consistent with how most of the rest of our registers are named. 5788 */ 5789 #define _DBUF_CTL_S0 0x45008 5790 #define _DBUF_CTL_S1 0x44FE8 5791 #define _DBUF_CTL_S2 0x44300 5792 #define _DBUF_CTL_S3 0x44304 5793 #define DBUF_CTL_S(slice) _MMIO(_PICK(slice, \ 5794 _DBUF_CTL_S0, \ 5795 _DBUF_CTL_S1, \ 5796 _DBUF_CTL_S2, \ 5797 _DBUF_CTL_S3)) 5798 #define DBUF_POWER_REQUEST REG_BIT(31) 5799 #define DBUF_POWER_STATE REG_BIT(30) 5800 #define DBUF_TRACKER_STATE_SERVICE_MASK REG_GENMASK(23, 19) 5801 #define DBUF_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_TRACKER_STATE_SERVICE_MASK, x) 5802 #define DBUF_MIN_TRACKER_STATE_SERVICE_MASK REG_GENMASK(18, 16) /* ADL-P+ */ 5803 #define DBUF_MIN_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) /* ADL-P+ */ 5804 5805 #define GEN7_MSG_CTL _MMIO(0x45010) 5806 #define WAIT_FOR_PCH_RESET_ACK (1 << 1) 5807 #define WAIT_FOR_PCH_FLR_ACK (1 << 0) 5808 5809 #define _BW_BUDDY0_CTL 0x45130 5810 #define _BW_BUDDY1_CTL 0x45140 5811 #define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \ 5812 _BW_BUDDY0_CTL, \ 5813 _BW_BUDDY1_CTL)) 5814 #define BW_BUDDY_DISABLE REG_BIT(31) 5815 #define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16) 5816 #define BW_BUDDY_TLB_REQ_TIMER(x) REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, x) 5817 5818 #define _BW_BUDDY0_PAGE_MASK 0x45134 5819 #define _BW_BUDDY1_PAGE_MASK 0x45144 5820 #define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \ 5821 _BW_BUDDY0_PAGE_MASK, \ 5822 _BW_BUDDY1_PAGE_MASK)) 5823 5824 #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) 5825 #define MTL_RESET_PICA_HANDSHAKE_EN REG_BIT(6) 5826 #define RESET_PCH_HANDSHAKE_ENABLE REG_BIT(4) 5827 5828 #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430) 5829 #define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30) 5830 #define LATENCY_REPORTING_REMOVED_PIPE_C REG_BIT(25) 5831 #define LATENCY_REPORTING_REMOVED_PIPE_B REG_BIT(24) 5832 #define LATENCY_REPORTING_REMOVED_PIPE_A REG_BIT(23) 5833 #define ICL_DELAY_PMRSP REG_BIT(22) 5834 #define DISABLE_FLR_SRC REG_BIT(15) 5835 #define MASK_WAKEMEM REG_BIT(13) 5836 #define DDI_CLOCK_REG_ACCESS REG_BIT(7) 5837 5838 #define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434) 5839 #define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27) 5840 #define DCPR_MASK_LPMODE REG_BIT(26) 5841 #define DCPR_SEND_RESP_IMM REG_BIT(25) 5842 #define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24) 5843 5844 #define SKL_DFSM _MMIO(0x51000) 5845 #define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27) 5846 #define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25) 5847 #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23) 5848 #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23) 5849 #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23) 5850 #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23) 5851 #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23) 5852 #define ICL_DFSM_DMC_DISABLE (1 << 23) 5853 #define SKL_DFSM_PIPE_A_DISABLE (1 << 30) 5854 #define SKL_DFSM_PIPE_B_DISABLE (1 << 21) 5855 #define SKL_DFSM_PIPE_C_DISABLE (1 << 28) 5856 #define TGL_DFSM_PIPE_D_DISABLE (1 << 22) 5857 #define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7) 5858 5859 #define SKL_DSSM _MMIO(0x51004) 5860 #define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29) 5861 #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29) 5862 #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29) 5863 #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29) 5864 5865 #define GMD_ID_DISPLAY _MMIO(0x510a0) 5866 #define GMD_ID_ARCH_MASK REG_GENMASK(31, 22) 5867 #define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14) 5868 #define GMD_ID_STEP REG_GENMASK(5, 0) 5869 5870 /*GEN11 chicken */ 5871 #define _PIPEA_CHICKEN 0x70038 5872 #define _PIPEB_CHICKEN 0x71038 5873 #define _PIPEC_CHICKEN 0x72038 5874 #define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\ 5875 _PIPEB_CHICKEN) 5876 #define UNDERRUN_RECOVERY_DISABLE_ADLP REG_BIT(30) 5877 #define UNDERRUN_RECOVERY_ENABLE_DG2 REG_BIT(30) 5878 #define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU REG_BIT(15) 5879 #define DG2_RENDER_CCSTAG_4_3_EN REG_BIT(12) 5880 #define PER_PIXEL_ALPHA_BYPASS_EN REG_BIT(7) 5881 5882 /* PCH */ 5883 5884 #define PCH_DISPLAY_BASE 0xc0000u 5885 5886 /* south display engine interrupt: IBX */ 5887 #define SDE_AUDIO_POWER_D (1 << 27) 5888 #define SDE_AUDIO_POWER_C (1 << 26) 5889 #define SDE_AUDIO_POWER_B (1 << 25) 5890 #define SDE_AUDIO_POWER_SHIFT (25) 5891 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) 5892 #define SDE_GMBUS (1 << 24) 5893 #define SDE_AUDIO_HDCP_TRANSB (1 << 23) 5894 #define SDE_AUDIO_HDCP_TRANSA (1 << 22) 5895 #define SDE_AUDIO_HDCP_MASK (3 << 22) 5896 #define SDE_AUDIO_TRANSB (1 << 21) 5897 #define SDE_AUDIO_TRANSA (1 << 20) 5898 #define SDE_AUDIO_TRANS_MASK (3 << 20) 5899 #define SDE_POISON (1 << 19) 5900 /* 18 reserved */ 5901 #define SDE_FDI_RXB (1 << 17) 5902 #define SDE_FDI_RXA (1 << 16) 5903 #define SDE_FDI_MASK (3 << 16) 5904 #define SDE_AUXD (1 << 15) 5905 #define SDE_AUXC (1 << 14) 5906 #define SDE_AUXB (1 << 13) 5907 #define SDE_AUX_MASK (7 << 13) 5908 /* 12 reserved */ 5909 #define SDE_CRT_HOTPLUG (1 << 11) 5910 #define SDE_PORTD_HOTPLUG (1 << 10) 5911 #define SDE_PORTC_HOTPLUG (1 << 9) 5912 #define SDE_PORTB_HOTPLUG (1 << 8) 5913 #define SDE_SDVOB_HOTPLUG (1 << 6) 5914 #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \ 5915 SDE_SDVOB_HOTPLUG | \ 5916 SDE_PORTB_HOTPLUG | \ 5917 SDE_PORTC_HOTPLUG | \ 5918 SDE_PORTD_HOTPLUG) 5919 #define SDE_TRANSB_CRC_DONE (1 << 5) 5920 #define SDE_TRANSB_CRC_ERR (1 << 4) 5921 #define SDE_TRANSB_FIFO_UNDER (1 << 3) 5922 #define SDE_TRANSA_CRC_DONE (1 << 2) 5923 #define SDE_TRANSA_CRC_ERR (1 << 1) 5924 #define SDE_TRANSA_FIFO_UNDER (1 << 0) 5925 #define SDE_TRANS_MASK (0x3f) 5926 5927 /* south display engine interrupt: CPT - CNP */ 5928 #define SDE_AUDIO_POWER_D_CPT (1 << 31) 5929 #define SDE_AUDIO_POWER_C_CPT (1 << 30) 5930 #define SDE_AUDIO_POWER_B_CPT (1 << 29) 5931 #define SDE_AUDIO_POWER_SHIFT_CPT 29 5932 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29) 5933 #define SDE_AUXD_CPT (1 << 27) 5934 #define SDE_AUXC_CPT (1 << 26) 5935 #define SDE_AUXB_CPT (1 << 25) 5936 #define SDE_AUX_MASK_CPT (7 << 25) 5937 #define SDE_PORTE_HOTPLUG_SPT (1 << 25) 5938 #define SDE_PORTA_HOTPLUG_SPT (1 << 24) 5939 #define SDE_PORTD_HOTPLUG_CPT (1 << 23) 5940 #define SDE_PORTC_HOTPLUG_CPT (1 << 22) 5941 #define SDE_PORTB_HOTPLUG_CPT (1 << 21) 5942 #define SDE_CRT_HOTPLUG_CPT (1 << 19) 5943 #define SDE_SDVOB_HOTPLUG_CPT (1 << 18) 5944 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ 5945 SDE_SDVOB_HOTPLUG_CPT | \ 5946 SDE_PORTD_HOTPLUG_CPT | \ 5947 SDE_PORTC_HOTPLUG_CPT | \ 5948 SDE_PORTB_HOTPLUG_CPT) 5949 #define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \ 5950 SDE_PORTD_HOTPLUG_CPT | \ 5951 SDE_PORTC_HOTPLUG_CPT | \ 5952 SDE_PORTB_HOTPLUG_CPT | \ 5953 SDE_PORTA_HOTPLUG_SPT) 5954 #define SDE_GMBUS_CPT (1 << 17) 5955 #define SDE_ERROR_CPT (1 << 16) 5956 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10) 5957 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9) 5958 #define SDE_FDI_RXC_CPT (1 << 8) 5959 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6) 5960 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5) 5961 #define SDE_FDI_RXB_CPT (1 << 4) 5962 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2) 5963 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1) 5964 #define SDE_FDI_RXA_CPT (1 << 0) 5965 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \ 5966 SDE_AUDIO_CP_REQ_B_CPT | \ 5967 SDE_AUDIO_CP_REQ_A_CPT) 5968 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \ 5969 SDE_AUDIO_CP_CHG_B_CPT | \ 5970 SDE_AUDIO_CP_CHG_A_CPT) 5971 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \ 5972 SDE_FDI_RXB_CPT | \ 5973 SDE_FDI_RXA_CPT) 5974 5975 /* south display engine interrupt: ICP/TGP */ 5976 #define SDE_GMBUS_ICP (1 << 23) 5977 #define SDE_TC_HOTPLUG_ICP(hpd_pin) REG_BIT(24 + _HPD_PIN_TC(hpd_pin)) 5978 #define SDE_TC_HOTPLUG_DG2(hpd_pin) REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /* sigh */ 5979 #define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin)) 5980 #define SDE_DDI_HOTPLUG_MASK_ICP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \ 5981 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \ 5982 SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \ 5983 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A)) 5984 #define SDE_TC_HOTPLUG_MASK_ICP (SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \ 5985 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \ 5986 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \ 5987 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \ 5988 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \ 5989 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1)) 5990 5991 #define SDEISR _MMIO(0xc4000) 5992 #define SDEIMR _MMIO(0xc4004) 5993 #define SDEIIR _MMIO(0xc4008) 5994 #define SDEIER _MMIO(0xc400c) 5995 5996 #define SERR_INT _MMIO(0xc4040) 5997 #define SERR_INT_POISON (1 << 31) 5998 #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) 5999 6000 /* digital port hotplug */ 6001 #define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */ 6002 #define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */ 6003 #define BXT_DDIA_HPD_INVERT (1 << 27) 6004 #define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */ 6005 #define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */ 6006 #define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */ 6007 #define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */ 6008 #define PORTD_HOTPLUG_ENABLE (1 << 20) 6009 #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */ 6010 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */ 6011 #define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */ 6012 #define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */ 6013 #define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */ 6014 #define PORTD_HOTPLUG_STATUS_MASK (3 << 16) 6015 #define PORTD_HOTPLUG_NO_DETECT (0 << 16) 6016 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) 6017 #define PORTD_HOTPLUG_LONG_DETECT (2 << 16) 6018 #define PORTC_HOTPLUG_ENABLE (1 << 12) 6019 #define BXT_DDIC_HPD_INVERT (1 << 11) 6020 #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */ 6021 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */ 6022 #define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */ 6023 #define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */ 6024 #define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */ 6025 #define PORTC_HOTPLUG_STATUS_MASK (3 << 8) 6026 #define PORTC_HOTPLUG_NO_DETECT (0 << 8) 6027 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) 6028 #define PORTC_HOTPLUG_LONG_DETECT (2 << 8) 6029 #define PORTB_HOTPLUG_ENABLE (1 << 4) 6030 #define BXT_DDIB_HPD_INVERT (1 << 3) 6031 #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */ 6032 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */ 6033 #define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */ 6034 #define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */ 6035 #define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */ 6036 #define PORTB_HOTPLUG_STATUS_MASK (3 << 0) 6037 #define PORTB_HOTPLUG_NO_DETECT (0 << 0) 6038 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) 6039 #define PORTB_HOTPLUG_LONG_DETECT (2 << 0) 6040 #define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \ 6041 BXT_DDIB_HPD_INVERT | \ 6042 BXT_DDIC_HPD_INVERT) 6043 6044 #define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */ 6045 #define PORTE_HOTPLUG_ENABLE (1 << 4) 6046 #define PORTE_HOTPLUG_STATUS_MASK (3 << 0) 6047 #define PORTE_HOTPLUG_NO_DETECT (0 << 0) 6048 #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0) 6049 #define PORTE_HOTPLUG_LONG_DETECT (2 << 0) 6050 6051 /* This register is a reuse of PCH_PORT_HOTPLUG register. The 6052 * functionality covered in PCH_PORT_HOTPLUG is split into 6053 * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC. 6054 */ 6055 6056 #define SHOTPLUG_CTL_DDI _MMIO(0xc4030) 6057 #define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) (0x8 << (_HPD_PIN_DDI(hpd_pin) * 4)) 6058 #define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4)) 6059 #define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin) (0x0 << (_HPD_PIN_DDI(hpd_pin) * 4)) 6060 #define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin) (0x1 << (_HPD_PIN_DDI(hpd_pin) * 4)) 6061 #define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin) (0x2 << (_HPD_PIN_DDI(hpd_pin) * 4)) 6062 #define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4)) 6063 6064 #define SHOTPLUG_CTL_TC _MMIO(0xc4034) 6065 #define ICP_TC_HPD_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4)) 6066 #define ICP_TC_HPD_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4)) 6067 #define ICP_TC_HPD_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4)) 6068 6069 #define SHPD_FILTER_CNT _MMIO(0xc4038) 6070 #define SHPD_FILTER_CNT_500_ADJ 0x001D9 6071 6072 #define _PCH_DPLL_A 0xc6014 6073 #define _PCH_DPLL_B 0xc6018 6074 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) 6075 6076 #define _PCH_FPA0 0xc6040 6077 #define FP_CB_TUNE (0x3 << 22) 6078 #define _PCH_FPA1 0xc6044 6079 #define _PCH_FPB0 0xc6048 6080 #define _PCH_FPB1 0xc604c 6081 #define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0) 6082 #define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1) 6083 6084 #define PCH_DPLL_TEST _MMIO(0xc606c) 6085 6086 #define PCH_DREF_CONTROL _MMIO(0xC6200) 6087 #define DREF_CONTROL_MASK 0x7fc3 6088 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13) 6089 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13) 6090 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13) 6091 #define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13) 6092 #define DREF_SSC_SOURCE_DISABLE (0 << 11) 6093 #define DREF_SSC_SOURCE_ENABLE (2 << 11) 6094 #define DREF_SSC_SOURCE_MASK (3 << 11) 6095 #define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9) 6096 #define DREF_NONSPREAD_CK505_ENABLE (1 << 9) 6097 #define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9) 6098 #define DREF_NONSPREAD_SOURCE_MASK (3 << 9) 6099 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7) 6100 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7) 6101 #define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7) 6102 #define DREF_SSC4_DOWNSPREAD (0 << 6) 6103 #define DREF_SSC4_CENTERSPREAD (1 << 6) 6104 #define DREF_SSC1_DISABLE (0 << 1) 6105 #define DREF_SSC1_ENABLE (1 << 1) 6106 #define DREF_SSC4_DISABLE (0) 6107 #define DREF_SSC4_ENABLE (1) 6108 6109 #define PCH_RAWCLK_FREQ _MMIO(0xc6204) 6110 #define FDL_TP1_TIMER_SHIFT 12 6111 #define FDL_TP1_TIMER_MASK (3 << 12) 6112 #define FDL_TP2_TIMER_SHIFT 10 6113 #define FDL_TP2_TIMER_MASK (3 << 10) 6114 #define RAWCLK_FREQ_MASK 0x3ff 6115 #define CNP_RAWCLK_DIV_MASK (0x3ff << 16) 6116 #define CNP_RAWCLK_DIV(div) ((div) << 16) 6117 #define CNP_RAWCLK_FRAC_MASK (0xf << 26) 6118 #define CNP_RAWCLK_DEN(den) ((den) << 26) 6119 #define ICP_RAWCLK_NUM(num) ((num) << 11) 6120 6121 #define PCH_DPLL_TMR_CFG _MMIO(0xc6208) 6122 6123 #define PCH_SSC4_PARMS _MMIO(0xc6210) 6124 #define PCH_SSC4_AUX_PARMS _MMIO(0xc6214) 6125 6126 #define PCH_DPLL_SEL _MMIO(0xc7000) 6127 #define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4)) 6128 #define TRANS_DPLLA_SEL(pipe) 0 6129 #define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3)) 6130 6131 /* transcoder */ 6132 6133 #define _PCH_TRANS_HTOTAL_A 0xe0000 6134 #define TRANS_HTOTAL_SHIFT 16 6135 #define TRANS_HACTIVE_SHIFT 0 6136 #define _PCH_TRANS_HBLANK_A 0xe0004 6137 #define TRANS_HBLANK_END_SHIFT 16 6138 #define TRANS_HBLANK_START_SHIFT 0 6139 #define _PCH_TRANS_HSYNC_A 0xe0008 6140 #define TRANS_HSYNC_END_SHIFT 16 6141 #define TRANS_HSYNC_START_SHIFT 0 6142 #define _PCH_TRANS_VTOTAL_A 0xe000c 6143 #define TRANS_VTOTAL_SHIFT 16 6144 #define TRANS_VACTIVE_SHIFT 0 6145 #define _PCH_TRANS_VBLANK_A 0xe0010 6146 #define TRANS_VBLANK_END_SHIFT 16 6147 #define TRANS_VBLANK_START_SHIFT 0 6148 #define _PCH_TRANS_VSYNC_A 0xe0014 6149 #define TRANS_VSYNC_END_SHIFT 16 6150 #define TRANS_VSYNC_START_SHIFT 0 6151 #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028 6152 6153 #define _PCH_TRANSA_DATA_M1 0xe0030 6154 #define _PCH_TRANSA_DATA_N1 0xe0034 6155 #define _PCH_TRANSA_DATA_M2 0xe0038 6156 #define _PCH_TRANSA_DATA_N2 0xe003c 6157 #define _PCH_TRANSA_LINK_M1 0xe0040 6158 #define _PCH_TRANSA_LINK_N1 0xe0044 6159 #define _PCH_TRANSA_LINK_M2 0xe0048 6160 #define _PCH_TRANSA_LINK_N2 0xe004c 6161 6162 /* Per-transcoder DIP controls (PCH) */ 6163 #define _VIDEO_DIP_CTL_A 0xe0200 6164 #define _VIDEO_DIP_DATA_A 0xe0208 6165 #define _VIDEO_DIP_GCP_A 0xe0210 6166 #define GCP_COLOR_INDICATION (1 << 2) 6167 #define GCP_DEFAULT_PHASE_ENABLE (1 << 1) 6168 #define GCP_AV_MUTE (1 << 0) 6169 6170 #define _VIDEO_DIP_CTL_B 0xe1200 6171 #define _VIDEO_DIP_DATA_B 0xe1208 6172 #define _VIDEO_DIP_GCP_B 0xe1210 6173 6174 #define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) 6175 #define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) 6176 #define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) 6177 6178 /* Per-transcoder DIP controls (VLV) */ 6179 #define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200) 6180 #define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208) 6181 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210) 6182 6183 #define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170) 6184 #define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174) 6185 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178) 6186 6187 #define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0) 6188 #define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4) 6189 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8) 6190 6191 #define VLV_TVIDEO_DIP_CTL(pipe) \ 6192 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \ 6193 _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C) 6194 #define VLV_TVIDEO_DIP_DATA(pipe) \ 6195 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \ 6196 _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C) 6197 #define VLV_TVIDEO_DIP_GCP(pipe) \ 6198 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \ 6199 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C) 6200 6201 /* Haswell DIP controls */ 6202 6203 #define _HSW_VIDEO_DIP_CTL_A 0x60200 6204 #define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220 6205 #define _HSW_VIDEO_DIP_VS_DATA_A 0x60260 6206 #define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 6207 #define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 6208 #define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320 6209 #define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440 6210 #define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240 6211 #define _HSW_VIDEO_DIP_VS_ECC_A 0x60280 6212 #define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 6213 #define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300 6214 #define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344 6215 #define _HSW_VIDEO_DIP_GCP_A 0x60210 6216 6217 #define _HSW_VIDEO_DIP_CTL_B 0x61200 6218 #define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220 6219 #define _HSW_VIDEO_DIP_VS_DATA_B 0x61260 6220 #define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 6221 #define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 6222 #define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320 6223 #define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440 6224 #define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240 6225 #define _HSW_VIDEO_DIP_VS_ECC_B 0x61280 6226 #define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 6227 #define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300 6228 #define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344 6229 #define _HSW_VIDEO_DIP_GCP_B 0x61210 6230 6231 /* Icelake PPS_DATA and _ECC DIP Registers. 6232 * These are available for transcoders B,C and eDP. 6233 * Adding the _A so as to reuse the _MMIO_TRANS2 6234 * definition, with which it offsets to the right location. 6235 */ 6236 6237 #define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350 6238 #define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350 6239 #define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4 6240 #define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4 6241 6242 #define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A) 6243 #define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A) 6244 #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4) 6245 #define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4) 6246 #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4) 6247 #define HSW_TVIDEO_DIP_GMP_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4) 6248 #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4) 6249 #define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4) 6250 #define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4) 6251 #define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4) 6252 6253 #define _HSW_STEREO_3D_CTL_A 0x70020 6254 #define S3D_ENABLE (1 << 31) 6255 #define _HSW_STEREO_3D_CTL_B 0x71020 6256 6257 #define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A) 6258 6259 #define _PCH_TRANS_HTOTAL_B 0xe1000 6260 #define _PCH_TRANS_HBLANK_B 0xe1004 6261 #define _PCH_TRANS_HSYNC_B 0xe1008 6262 #define _PCH_TRANS_VTOTAL_B 0xe100c 6263 #define _PCH_TRANS_VBLANK_B 0xe1010 6264 #define _PCH_TRANS_VSYNC_B 0xe1014 6265 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028 6266 6267 #define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B) 6268 #define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B) 6269 #define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B) 6270 #define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B) 6271 #define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B) 6272 #define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B) 6273 #define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B) 6274 6275 #define _PCH_TRANSB_DATA_M1 0xe1030 6276 #define _PCH_TRANSB_DATA_N1 0xe1034 6277 #define _PCH_TRANSB_DATA_M2 0xe1038 6278 #define _PCH_TRANSB_DATA_N2 0xe103c 6279 #define _PCH_TRANSB_LINK_M1 0xe1040 6280 #define _PCH_TRANSB_LINK_N1 0xe1044 6281 #define _PCH_TRANSB_LINK_M2 0xe1048 6282 #define _PCH_TRANSB_LINK_N2 0xe104c 6283 6284 #define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1) 6285 #define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1) 6286 #define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2) 6287 #define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2) 6288 #define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1) 6289 #define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1) 6290 #define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2) 6291 #define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2) 6292 6293 #define _PCH_TRANSACONF 0xf0008 6294 #define _PCH_TRANSBCONF 0xf1008 6295 #define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF) 6296 #define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */ 6297 #define TRANS_ENABLE REG_BIT(31) 6298 #define TRANS_STATE_ENABLE REG_BIT(30) 6299 #define TRANS_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* ibx */ 6300 #define TRANS_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */ 6301 #define TRANS_INTERLACE_MASK REG_GENMASK(23, 21) 6302 #define TRANS_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0) 6303 #define TRANS_INTERLACE_LEGACY_VSYNC_IBX REG_FIELD_PREP(TRANS_INTERLACE_MASK, 2) /* ibx */ 6304 #define TRANS_INTERLACE_INTERLACED REG_FIELD_PREP(TRANS_INTERLACE_MASK, 3) 6305 #define TRANS_BPC_MASK REG_GENMASK(7, 5) /* ibx */ 6306 #define TRANS_BPC_8 REG_FIELD_PREP(TRANS_BPC_MASK, 0) 6307 #define TRANS_BPC_10 REG_FIELD_PREP(TRANS_BPC_MASK, 1) 6308 #define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK, 2) 6309 #define TRANS_BPC_12 REG_FIELD_PREP(TRANS_BPC_MASK, 3) 6310 #define _TRANSA_CHICKEN1 0xf0060 6311 #define _TRANSB_CHICKEN1 0xf1060 6312 #define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) 6313 #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE (1 << 10) 6314 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1 << 4) 6315 #define _TRANSA_CHICKEN2 0xf0064 6316 #define _TRANSB_CHICKEN2 0xf1064 6317 #define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) 6318 #define TRANS_CHICKEN2_TIMING_OVERRIDE (1 << 31) 6319 #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1 << 29) 6320 #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3 << 27) 6321 #define TRANS_CHICKEN2_FRAME_START_DELAY(x) ((x) << 27) /* 0-3 */ 6322 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1 << 26) 6323 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1 << 25) 6324 6325 #define SOUTH_CHICKEN1 _MMIO(0xc2000) 6326 #define FDIA_PHASE_SYNC_SHIFT_OVR 19 6327 #define FDIA_PHASE_SYNC_SHIFT_EN 18 6328 #define INVERT_DDID_HPD (1 << 18) 6329 #define INVERT_DDIC_HPD (1 << 17) 6330 #define INVERT_DDIB_HPD (1 << 16) 6331 #define INVERT_DDIA_HPD (1 << 15) 6332 #define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) 6333 #define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) 6334 #define FDI_BC_BIFURCATION_SELECT (1 << 12) 6335 #define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8) 6336 #define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8) 6337 #define SBCLK_RUN_REFCLK_DIS (1 << 7) 6338 #define SPT_PWM_GRANULARITY (1 << 0) 6339 #define SOUTH_CHICKEN2 _MMIO(0xc2004) 6340 #define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13) 6341 #define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12) 6342 #define LPT_PWM_GRANULARITY (1 << 5) 6343 #define DPLS_EDP_PPS_FIX_DIS (1 << 0) 6344 6345 #define _FDI_RXA_CHICKEN 0xc200c 6346 #define _FDI_RXB_CHICKEN 0xc2010 6347 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1 << 1) 6348 #define FDI_RX_PHASE_SYNC_POINTER_EN (1 << 0) 6349 #define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) 6350 6351 #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020) 6352 #define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31) 6353 #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30) 6354 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29) 6355 #define PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15) 6356 #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14) 6357 #define CNP_PWM_CGE_GATING_DISABLE (1 << 13) 6358 #define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12) 6359 6360 /* CPU: FDI_TX */ 6361 #define _FDI_TXA_CTL 0x60100 6362 #define _FDI_TXB_CTL 0x61100 6363 #define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) 6364 #define FDI_TX_DISABLE (0 << 31) 6365 #define FDI_TX_ENABLE (1 << 31) 6366 #define FDI_LINK_TRAIN_PATTERN_1 (0 << 28) 6367 #define FDI_LINK_TRAIN_PATTERN_2 (1 << 28) 6368 #define FDI_LINK_TRAIN_PATTERN_IDLE (2 << 28) 6369 #define FDI_LINK_TRAIN_NONE (3 << 28) 6370 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0 << 25) 6371 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1 << 25) 6372 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2 << 25) 6373 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3 << 25) 6374 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22) 6375 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22) 6376 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2 << 22) 6377 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3 << 22) 6378 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. 6379 SNB has different settings. */ 6380 /* SNB A-stepping */ 6381 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) 6382 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22) 6383 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22) 6384 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22) 6385 /* SNB B-stepping */ 6386 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0 << 22) 6387 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a << 22) 6388 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39 << 22) 6389 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38 << 22) 6390 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f << 22) 6391 #define FDI_DP_PORT_WIDTH_SHIFT 19 6392 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT) 6393 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT) 6394 #define FDI_TX_ENHANCE_FRAME_ENABLE (1 << 18) 6395 /* Ironlake: hardwired to 1 */ 6396 #define FDI_TX_PLL_ENABLE (1 << 14) 6397 6398 /* Ivybridge has different bits for lolz */ 6399 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0 << 8) 6400 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1 << 8) 6401 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2 << 8) 6402 #define FDI_LINK_TRAIN_NONE_IVB (3 << 8) 6403 6404 /* both Tx and Rx */ 6405 #define FDI_COMPOSITE_SYNC (1 << 11) 6406 #define FDI_LINK_TRAIN_AUTO (1 << 10) 6407 #define FDI_SCRAMBLING_ENABLE (0 << 7) 6408 #define FDI_SCRAMBLING_DISABLE (1 << 7) 6409 6410 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */ 6411 #define _FDI_RXA_CTL 0xf000c 6412 #define _FDI_RXB_CTL 0xf100c 6413 #define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) 6414 #define FDI_RX_ENABLE (1 << 31) 6415 /* train, dp width same as FDI_TX */ 6416 #define FDI_FS_ERRC_ENABLE (1 << 27) 6417 #define FDI_FE_ERRC_ENABLE (1 << 26) 6418 #define FDI_RX_POLARITY_REVERSED_LPT (1 << 16) 6419 #define FDI_8BPC (0 << 16) 6420 #define FDI_10BPC (1 << 16) 6421 #define FDI_6BPC (2 << 16) 6422 #define FDI_12BPC (3 << 16) 6423 #define FDI_RX_LINK_REVERSAL_OVERRIDE (1 << 15) 6424 #define FDI_DMI_LINK_REVERSE_MASK (1 << 14) 6425 #define FDI_RX_PLL_ENABLE (1 << 13) 6426 #define FDI_FS_ERR_CORRECT_ENABLE (1 << 11) 6427 #define FDI_FE_ERR_CORRECT_ENABLE (1 << 10) 6428 #define FDI_FS_ERR_REPORT_ENABLE (1 << 9) 6429 #define FDI_FE_ERR_REPORT_ENABLE (1 << 8) 6430 #define FDI_RX_ENHANCE_FRAME_ENABLE (1 << 6) 6431 #define FDI_PCDCLK (1 << 4) 6432 /* CPT */ 6433 #define FDI_AUTO_TRAINING (1 << 10) 6434 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0 << 8) 6435 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1 << 8) 6436 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2 << 8) 6437 #define FDI_LINK_TRAIN_NORMAL_CPT (3 << 8) 6438 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3 << 8) 6439 6440 #define _FDI_RXA_MISC 0xf0010 6441 #define _FDI_RXB_MISC 0xf1010 6442 #define FDI_RX_PWRDN_LANE1_MASK (3 << 26) 6443 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x) << 26) 6444 #define FDI_RX_PWRDN_LANE0_MASK (3 << 24) 6445 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x) << 24) 6446 #define FDI_RX_TP1_TO_TP2_48 (2 << 20) 6447 #define FDI_RX_TP1_TO_TP2_64 (3 << 20) 6448 #define FDI_RX_FDI_DELAY_90 (0x90 << 0) 6449 #define FDI_RX_MISC(pipe) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) 6450 6451 #define _FDI_RXA_TUSIZE1 0xf0030 6452 #define _FDI_RXA_TUSIZE2 0xf0038 6453 #define _FDI_RXB_TUSIZE1 0xf1030 6454 #define _FDI_RXB_TUSIZE2 0xf1038 6455 #define FDI_RX_TUSIZE1(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) 6456 #define FDI_RX_TUSIZE2(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) 6457 6458 /* FDI_RX interrupt register format */ 6459 #define FDI_RX_INTER_LANE_ALIGN (1 << 10) 6460 #define FDI_RX_SYMBOL_LOCK (1 << 9) /* train 2 */ 6461 #define FDI_RX_BIT_LOCK (1 << 8) /* train 1 */ 6462 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1 << 7) 6463 #define FDI_RX_FS_CODE_ERR (1 << 6) 6464 #define FDI_RX_FE_CODE_ERR (1 << 5) 6465 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1 << 4) 6466 #define FDI_RX_HDCP_LINK_FAIL (1 << 3) 6467 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1 << 2) 6468 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1 << 1) 6469 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1 << 0) 6470 6471 #define _FDI_RXA_IIR 0xf0014 6472 #define _FDI_RXA_IMR 0xf0018 6473 #define _FDI_RXB_IIR 0xf1014 6474 #define _FDI_RXB_IMR 0xf1018 6475 #define FDI_RX_IIR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) 6476 #define FDI_RX_IMR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR) 6477 6478 #define FDI_PLL_CTL_1 _MMIO(0xfe000) 6479 #define FDI_PLL_CTL_2 _MMIO(0xfe004) 6480 6481 #define PCH_LVDS _MMIO(0xe1180) 6482 #define LVDS_DETECTED (1 << 1) 6483 6484 #define _PCH_DP_B 0xe4100 6485 #define PCH_DP_B _MMIO(_PCH_DP_B) 6486 #define _PCH_DPB_AUX_CH_CTL 0xe4110 6487 #define _PCH_DPB_AUX_CH_DATA1 0xe4114 6488 #define _PCH_DPB_AUX_CH_DATA2 0xe4118 6489 #define _PCH_DPB_AUX_CH_DATA3 0xe411c 6490 #define _PCH_DPB_AUX_CH_DATA4 0xe4120 6491 #define _PCH_DPB_AUX_CH_DATA5 0xe4124 6492 6493 #define _PCH_DP_C 0xe4200 6494 #define PCH_DP_C _MMIO(_PCH_DP_C) 6495 #define _PCH_DPC_AUX_CH_CTL 0xe4210 6496 #define _PCH_DPC_AUX_CH_DATA1 0xe4214 6497 #define _PCH_DPC_AUX_CH_DATA2 0xe4218 6498 #define _PCH_DPC_AUX_CH_DATA3 0xe421c 6499 #define _PCH_DPC_AUX_CH_DATA4 0xe4220 6500 #define _PCH_DPC_AUX_CH_DATA5 0xe4224 6501 6502 #define _PCH_DP_D 0xe4300 6503 #define PCH_DP_D _MMIO(_PCH_DP_D) 6504 #define _PCH_DPD_AUX_CH_CTL 0xe4310 6505 #define _PCH_DPD_AUX_CH_DATA1 0xe4314 6506 #define _PCH_DPD_AUX_CH_DATA2 0xe4318 6507 #define _PCH_DPD_AUX_CH_DATA3 0xe431c 6508 #define _PCH_DPD_AUX_CH_DATA4 0xe4320 6509 #define _PCH_DPD_AUX_CH_DATA5 0xe4324 6510 6511 #define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL) 6512 #define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ 6513 6514 /* CPT */ 6515 #define _TRANS_DP_CTL_A 0xe0300 6516 #define _TRANS_DP_CTL_B 0xe1300 6517 #define _TRANS_DP_CTL_C 0xe2300 6518 #define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B) 6519 #define TRANS_DP_OUTPUT_ENABLE REG_BIT(31) 6520 #define TRANS_DP_PORT_SEL_MASK REG_GENMASK(30, 29) 6521 #define TRANS_DP_PORT_SEL_NONE REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, 3) 6522 #define TRANS_DP_PORT_SEL(port) REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, (port) - PORT_B) 6523 #define TRANS_DP_AUDIO_ONLY REG_BIT(26) 6524 #define TRANS_DP_ENH_FRAMING REG_BIT(18) 6525 #define TRANS_DP_BPC_MASK REG_GENMASK(10, 9) 6526 #define TRANS_DP_BPC_8 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 0) 6527 #define TRANS_DP_BPC_10 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 1) 6528 #define TRANS_DP_BPC_6 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 2) 6529 #define TRANS_DP_BPC_12 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 3) 6530 #define TRANS_DP_VSYNC_ACTIVE_HIGH REG_BIT(4) 6531 #define TRANS_DP_HSYNC_ACTIVE_HIGH REG_BIT(3) 6532 6533 #define _TRANS_DP2_CTL_A 0x600a0 6534 #define _TRANS_DP2_CTL_B 0x610a0 6535 #define _TRANS_DP2_CTL_C 0x620a0 6536 #define _TRANS_DP2_CTL_D 0x630a0 6537 #define TRANS_DP2_CTL(trans) _MMIO_TRANS(trans, _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B) 6538 #define TRANS_DP2_128B132B_CHANNEL_CODING REG_BIT(31) 6539 #define TRANS_DP2_PANEL_REPLAY_ENABLE REG_BIT(30) 6540 #define TRANS_DP2_DEBUG_ENABLE REG_BIT(23) 6541 6542 #define _TRANS_DP2_VFREQHIGH_A 0x600a4 6543 #define _TRANS_DP2_VFREQHIGH_B 0x610a4 6544 #define _TRANS_DP2_VFREQHIGH_C 0x620a4 6545 #define _TRANS_DP2_VFREQHIGH_D 0x630a4 6546 #define TRANS_DP2_VFREQHIGH(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQHIGH_A, _TRANS_DP2_VFREQHIGH_B) 6547 #define TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK REG_GENMASK(31, 8) 6548 #define TRANS_DP2_VFREQ_PIXEL_CLOCK(clk_hz) REG_FIELD_PREP(TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK, (clk_hz)) 6549 6550 #define _TRANS_DP2_VFREQLOW_A 0x600a8 6551 #define _TRANS_DP2_VFREQLOW_B 0x610a8 6552 #define _TRANS_DP2_VFREQLOW_C 0x620a8 6553 #define _TRANS_DP2_VFREQLOW_D 0x630a8 6554 #define TRANS_DP2_VFREQLOW(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQLOW_A, _TRANS_DP2_VFREQLOW_B) 6555 6556 /* SNB eDP training params */ 6557 /* SNB A-stepping */ 6558 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) 6559 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22) 6560 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22) 6561 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22) 6562 /* SNB B-stepping */ 6563 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22) 6564 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22) 6565 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22) 6566 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22) 6567 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22) 6568 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22) 6569 6570 /* IVB */ 6571 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22) 6572 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22) 6573 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22) 6574 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22) 6575 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22) 6576 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22) 6577 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e << 22) 6578 6579 /* legacy values */ 6580 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22) 6581 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22) 6582 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22) 6583 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22) 6584 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22) 6585 6586 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22) 6587 6588 #define VLV_PMWGICZ _MMIO(0x1300a4) 6589 6590 #define HSW_EDRAM_CAP _MMIO(0x120010) 6591 #define EDRAM_ENABLED 0x1 6592 #define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf) 6593 #define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7) 6594 #define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3) 6595 6596 #define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C) 6597 #define PIXEL_OVERLAP_CNT_MASK (3 << 30) 6598 #define PIXEL_OVERLAP_CNT_SHIFT 30 6599 6600 #define GEN6_PCODE_MAILBOX _MMIO(0x138124) 6601 #define GEN6_PCODE_READY (1 << 31) 6602 #define GEN6_PCODE_MB_PARAM2 REG_GENMASK(23, 16) 6603 #define GEN6_PCODE_MB_PARAM1 REG_GENMASK(15, 8) 6604 #define GEN6_PCODE_MB_COMMAND REG_GENMASK(7, 0) 6605 #define GEN6_PCODE_ERROR_MASK 0xFF 6606 #define GEN6_PCODE_SUCCESS 0x0 6607 #define GEN6_PCODE_ILLEGAL_CMD 0x1 6608 #define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2 6609 #define GEN6_PCODE_TIMEOUT 0x3 6610 #define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF 6611 #define GEN7_PCODE_TIMEOUT 0x2 6612 #define GEN7_PCODE_ILLEGAL_DATA 0x3 6613 #define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4 6614 #define GEN11_PCODE_LOCKED 0x6 6615 #define GEN11_PCODE_REJECTED 0x11 6616 #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10 6617 #define GEN6_PCODE_WRITE_RC6VIDS 0x4 6618 #define GEN6_PCODE_READ_RC6VIDS 0x5 6619 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) 6620 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) 6621 #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18 6622 #define GEN9_PCODE_READ_MEM_LATENCY 0x6 6623 #define GEN9_MEM_LATENCY_LEVEL_3_7_MASK REG_GENMASK(31, 24) 6624 #define GEN9_MEM_LATENCY_LEVEL_2_6_MASK REG_GENMASK(23, 16) 6625 #define GEN9_MEM_LATENCY_LEVEL_1_5_MASK REG_GENMASK(15, 8) 6626 #define GEN9_MEM_LATENCY_LEVEL_0_4_MASK REG_GENMASK(7, 0) 6627 #define SKL_PCODE_LOAD_HDCP_KEYS 0x5 6628 #define SKL_PCODE_CDCLK_CONTROL 0x7 6629 #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3 6630 #define SKL_CDCLK_READY_FOR_CHANGE 0x1 6631 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 6632 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 6633 #define GEN6_READ_OC_PARAMS 0xc 6634 #define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd 6635 #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8) 6636 #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8)) 6637 #define ADL_PCODE_MEM_SS_READ_PSF_GV_INFO ((0) | (0x2 << 8)) 6638 #define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe 6639 #define ICL_PCODE_REP_QGV_MASK REG_GENMASK(1, 0) 6640 #define ICL_PCODE_REP_QGV_SAFE REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0) 6641 #define ICL_PCODE_REP_QGV_POLL REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1) 6642 #define ICL_PCODE_REP_QGV_REJECTED REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2) 6643 #define ADLS_PCODE_REP_PSF_MASK REG_GENMASK(3, 2) 6644 #define ADLS_PCODE_REP_PSF_SAFE REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0) 6645 #define ADLS_PCODE_REP_PSF_POLL REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1) 6646 #define ADLS_PCODE_REP_PSF_REJECTED REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2) 6647 #define ICL_PCODE_REQ_QGV_PT_MASK REG_GENMASK(7, 0) 6648 #define ICL_PCODE_REQ_QGV_PT(x) REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x)) 6649 #define ADLS_PCODE_REQ_PSF_PT_MASK REG_GENMASK(10, 8) 6650 #define ADLS_PCODE_REQ_PSF_PT(x) REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x)) 6651 #define GEN6_PCODE_READ_D_COMP 0x10 6652 #define GEN6_PCODE_WRITE_D_COMP 0x11 6653 #define ICL_PCODE_EXIT_TCCOLD 0x12 6654 #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17 6655 #define DISPLAY_IPS_CONTROL 0x19 6656 #define TGL_PCODE_TCCOLD 0x26 6657 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0) 6658 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ 0 6659 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0) 6660 /* See also IPS_CTL */ 6661 #define IPS_PCODE_CONTROL (1 << 30) 6662 #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A 6663 #define GEN9_PCODE_SAGV_CONTROL 0x21 6664 #define GEN9_SAGV_DISABLE 0x0 6665 #define GEN9_SAGV_IS_DISABLED 0x1 6666 #define GEN9_SAGV_ENABLE 0x3 6667 #define DG1_PCODE_STATUS 0x7E 6668 #define DG1_UNCORE_GET_INIT_STATUS 0x0 6669 #define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1 6670 #define PCODE_POWER_SETUP 0x7C 6671 #define POWER_SETUP_SUBCOMMAND_READ_I1 0x4 6672 #define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5 6673 #define POWER_SETUP_I1_WATTS REG_BIT(31) 6674 #define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */ 6675 #define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0) 6676 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23 6677 #define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* xehpsdv, pvc */ 6678 /* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */ 6679 #define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0 6680 #define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1 6681 /* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */ 6682 /* XEHP_PCODE_FREQUENCY_CONFIG param2 */ 6683 #define PCODE_MBOX_DOMAIN_NONE 0x0 6684 #define PCODE_MBOX_DOMAIN_MEDIAFF 0x3 6685 6686 /* Wa_14017210380: mtl */ 6687 #define PCODE_MBOX_GT_STATE 0x50 6688 /* sub-commands (param1) */ 6689 #define PCODE_MBOX_GT_STATE_MEDIA_BUSY 0x1 6690 #define PCODE_MBOX_GT_STATE_MEDIA_NOT_BUSY 0x2 6691 /* param2 */ 6692 #define PCODE_MBOX_GT_STATE_DOMAIN_MEDIA 0x1 6693 6694 #define GEN6_PCODE_DATA _MMIO(0x138128) 6695 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 6696 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 6697 #define GEN6_PCODE_DATA1 _MMIO(0x13812C) 6698 6699 /* IVYBRIDGE DPF */ 6700 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */ 6701 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14) 6702 #define GEN7_PARITY_ERROR_VALID (1 << 13) 6703 #define GEN7_L3CDERRST1_BANK_MASK (3 << 11) 6704 #define GEN7_L3CDERRST1_SUBBANK_MASK (7 << 8) 6705 #define GEN7_PARITY_ERROR_ROW(reg) \ 6706 (((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14) 6707 #define GEN7_PARITY_ERROR_BANK(reg) \ 6708 (((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11) 6709 #define GEN7_PARITY_ERROR_SUBBANK(reg) \ 6710 (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) 6711 #define GEN7_L3CDERRST1_ENABLE (1 << 7) 6712 6713 /* These are the 4 32-bit write offset registers for each stream 6714 * output buffer. It determines the offset from the 6715 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. 6716 */ 6717 #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4) 6718 6719 /* 6720 * HSW - ICL power wells 6721 * 6722 * Platforms have up to 3 power well control register sets, each set 6723 * controlling up to 16 power wells via a request/status HW flag tuple: 6724 * - main (HSW_PWR_WELL_CTL[1-4]) 6725 * - AUX (ICL_PWR_WELL_CTL_AUX[1-4]) 6726 * - DDI (ICL_PWR_WELL_CTL_DDI[1-4]) 6727 * Each control register set consists of up to 4 registers used by different 6728 * sources that can request a power well to be enabled: 6729 * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1) 6730 * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2) 6731 * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set) 6732 * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4) 6733 */ 6734 #define HSW_PWR_WELL_CTL1 _MMIO(0x45400) 6735 #define HSW_PWR_WELL_CTL2 _MMIO(0x45404) 6736 #define HSW_PWR_WELL_CTL3 _MMIO(0x45408) 6737 #define HSW_PWR_WELL_CTL4 _MMIO(0x4540C) 6738 #define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2)) 6739 #define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2)) 6740 6741 /* HSW/BDW power well */ 6742 #define HSW_PW_CTL_IDX_GLOBAL 15 6743 6744 /* SKL/BXT/GLK power wells */ 6745 #define SKL_PW_CTL_IDX_PW_2 15 6746 #define SKL_PW_CTL_IDX_PW_1 14 6747 #define GLK_PW_CTL_IDX_AUX_C 10 6748 #define GLK_PW_CTL_IDX_AUX_B 9 6749 #define GLK_PW_CTL_IDX_AUX_A 8 6750 #define SKL_PW_CTL_IDX_DDI_D 4 6751 #define SKL_PW_CTL_IDX_DDI_C 3 6752 #define SKL_PW_CTL_IDX_DDI_B 2 6753 #define SKL_PW_CTL_IDX_DDI_A_E 1 6754 #define GLK_PW_CTL_IDX_DDI_A 1 6755 #define SKL_PW_CTL_IDX_MISC_IO 0 6756 6757 /* ICL/TGL - power wells */ 6758 #define TGL_PW_CTL_IDX_PW_5 4 6759 #define ICL_PW_CTL_IDX_PW_4 3 6760 #define ICL_PW_CTL_IDX_PW_3 2 6761 #define ICL_PW_CTL_IDX_PW_2 1 6762 #define ICL_PW_CTL_IDX_PW_1 0 6763 6764 /* XE_LPD - power wells */ 6765 #define XELPD_PW_CTL_IDX_PW_D 8 6766 #define XELPD_PW_CTL_IDX_PW_C 7 6767 #define XELPD_PW_CTL_IDX_PW_B 6 6768 #define XELPD_PW_CTL_IDX_PW_A 5 6769 6770 #define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440) 6771 #define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444) 6772 #define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C) 6773 #define TGL_PW_CTL_IDX_AUX_TBT6 14 6774 #define TGL_PW_CTL_IDX_AUX_TBT5 13 6775 #define TGL_PW_CTL_IDX_AUX_TBT4 12 6776 #define ICL_PW_CTL_IDX_AUX_TBT4 11 6777 #define TGL_PW_CTL_IDX_AUX_TBT3 11 6778 #define ICL_PW_CTL_IDX_AUX_TBT3 10 6779 #define TGL_PW_CTL_IDX_AUX_TBT2 10 6780 #define ICL_PW_CTL_IDX_AUX_TBT2 9 6781 #define TGL_PW_CTL_IDX_AUX_TBT1 9 6782 #define ICL_PW_CTL_IDX_AUX_TBT1 8 6783 #define TGL_PW_CTL_IDX_AUX_TC6 8 6784 #define XELPD_PW_CTL_IDX_AUX_E 8 6785 #define TGL_PW_CTL_IDX_AUX_TC5 7 6786 #define XELPD_PW_CTL_IDX_AUX_D 7 6787 #define TGL_PW_CTL_IDX_AUX_TC4 6 6788 #define ICL_PW_CTL_IDX_AUX_F 5 6789 #define TGL_PW_CTL_IDX_AUX_TC3 5 6790 #define ICL_PW_CTL_IDX_AUX_E 4 6791 #define TGL_PW_CTL_IDX_AUX_TC2 4 6792 #define ICL_PW_CTL_IDX_AUX_D 3 6793 #define TGL_PW_CTL_IDX_AUX_TC1 3 6794 #define ICL_PW_CTL_IDX_AUX_C 2 6795 #define ICL_PW_CTL_IDX_AUX_B 1 6796 #define ICL_PW_CTL_IDX_AUX_A 0 6797 6798 #define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450) 6799 #define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454) 6800 #define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C) 6801 #define XELPD_PW_CTL_IDX_DDI_E 8 6802 #define TGL_PW_CTL_IDX_DDI_TC6 8 6803 #define XELPD_PW_CTL_IDX_DDI_D 7 6804 #define TGL_PW_CTL_IDX_DDI_TC5 7 6805 #define TGL_PW_CTL_IDX_DDI_TC4 6 6806 #define ICL_PW_CTL_IDX_DDI_F 5 6807 #define TGL_PW_CTL_IDX_DDI_TC3 5 6808 #define ICL_PW_CTL_IDX_DDI_E 4 6809 #define TGL_PW_CTL_IDX_DDI_TC2 4 6810 #define ICL_PW_CTL_IDX_DDI_D 3 6811 #define TGL_PW_CTL_IDX_DDI_TC1 3 6812 #define ICL_PW_CTL_IDX_DDI_C 2 6813 #define ICL_PW_CTL_IDX_DDI_B 1 6814 #define ICL_PW_CTL_IDX_DDI_A 0 6815 6816 /* HSW - power well misc debug registers */ 6817 #define HSW_PWR_WELL_CTL5 _MMIO(0x45410) 6818 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31) 6819 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20) 6820 #define HSW_PWR_WELL_FORCE_ON (1 << 19) 6821 #define HSW_PWR_WELL_CTL6 _MMIO(0x45414) 6822 6823 /* SKL Fuse Status */ 6824 enum skl_power_gate { 6825 SKL_PG0, 6826 SKL_PG1, 6827 SKL_PG2, 6828 ICL_PG3, 6829 ICL_PG4, 6830 }; 6831 6832 #define SKL_FUSE_STATUS _MMIO(0x42000) 6833 #define SKL_FUSE_DOWNLOAD_STATUS (1 << 31) 6834 /* 6835 * PG0 is HW controlled, so doesn't have a corresponding power well control knob 6836 * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2 6837 */ 6838 #define SKL_PW_CTL_IDX_TO_PG(pw_idx) \ 6839 ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1) 6840 /* 6841 * PG0 is HW controlled, so doesn't have a corresponding power well control knob 6842 * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4 6843 */ 6844 #define ICL_PW_CTL_IDX_TO_PG(pw_idx) \ 6845 ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1) 6846 #define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg))) 6847 6848 #define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A) 6849 #define _ICL_AUX_ANAOVRD1_A 0x162398 6850 #define _ICL_AUX_ANAOVRD1_B 0x6C398 6851 #define ICL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \ 6852 _ICL_AUX_ANAOVRD1_A, \ 6853 _ICL_AUX_ANAOVRD1_B)) 6854 #define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7) 6855 #define ICL_AUX_ANAOVRD1_ENABLE (1 << 0) 6856 6857 /* Per-pipe DDI Function Control */ 6858 #define _TRANS_DDI_FUNC_CTL_A 0x60400 6859 #define _TRANS_DDI_FUNC_CTL_B 0x61400 6860 #define _TRANS_DDI_FUNC_CTL_C 0x62400 6861 #define _TRANS_DDI_FUNC_CTL_D 0x63400 6862 #define _TRANS_DDI_FUNC_CTL_EDP 0x6F400 6863 #define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400 6864 #define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00 6865 #define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A) 6866 6867 #define TRANS_DDI_FUNC_ENABLE (1 << 31) 6868 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ 6869 #define TRANS_DDI_PORT_SHIFT 28 6870 #define TGL_TRANS_DDI_PORT_SHIFT 27 6871 #define TRANS_DDI_PORT_MASK (7 << TRANS_DDI_PORT_SHIFT) 6872 #define TGL_TRANS_DDI_PORT_MASK (0xf << TGL_TRANS_DDI_PORT_SHIFT) 6873 #define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT) 6874 #define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT) 6875 #define TRANS_DDI_MODE_SELECT_MASK (7 << 24) 6876 #define TRANS_DDI_MODE_SELECT_HDMI (0 << 24) 6877 #define TRANS_DDI_MODE_SELECT_DVI (1 << 24) 6878 #define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24) 6879 #define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24) 6880 #define TRANS_DDI_MODE_SELECT_FDI_OR_128B132B (4 << 24) 6881 #define TRANS_DDI_BPC_MASK (7 << 20) 6882 #define TRANS_DDI_BPC_8 (0 << 20) 6883 #define TRANS_DDI_BPC_10 (1 << 20) 6884 #define TRANS_DDI_BPC_6 (2 << 20) 6885 #define TRANS_DDI_BPC_12 (3 << 20) 6886 #define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK REG_GENMASK(19, 18) 6887 #define TRANS_DDI_PORT_SYNC_MASTER_SELECT(x) REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, (x)) 6888 #define TRANS_DDI_PVSYNC (1 << 17) 6889 #define TRANS_DDI_PHSYNC (1 << 16) 6890 #define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15) 6891 #define TRANS_DDI_EDP_INPUT_MASK (7 << 12) 6892 #define TRANS_DDI_EDP_INPUT_A_ON (0 << 12) 6893 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12) 6894 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12) 6895 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12) 6896 #define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12) 6897 #define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10) 6898 #define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \ 6899 REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans) 6900 #define TRANS_DDI_HDCP_SIGNALLING (1 << 9) 6901 #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8) 6902 #define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7) 6903 #define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6) 6904 #define TRANS_DDI_HDCP_SELECT REG_BIT(5) 6905 #define TRANS_DDI_BFI_ENABLE (1 << 4) 6906 #define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4) 6907 #define TRANS_DDI_HDMI_SCRAMBLING (1 << 0) 6908 #define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \ 6909 | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \ 6910 | TRANS_DDI_HDMI_SCRAMBLING) 6911 6912 #define _TRANS_DDI_FUNC_CTL2_A 0x60404 6913 #define _TRANS_DDI_FUNC_CTL2_B 0x61404 6914 #define _TRANS_DDI_FUNC_CTL2_C 0x62404 6915 #define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404 6916 #define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404 6917 #define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04 6918 #define TRANS_DDI_FUNC_CTL2(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL2_A) 6919 #define PORT_SYNC_MODE_ENABLE REG_BIT(4) 6920 #define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0) 6921 #define PORT_SYNC_MODE_MASTER_SELECT(x) REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x)) 6922 6923 #define TRANS_CMTG_CHICKEN _MMIO(0x6fa90) 6924 #define DISABLE_DPT_CLK_GATING REG_BIT(1) 6925 6926 /* DisplayPort Transport Control */ 6927 #define _DP_TP_CTL_A 0x64040 6928 #define _DP_TP_CTL_B 0x64140 6929 #define _TGL_DP_TP_CTL_A 0x60540 6930 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B) 6931 #define TGL_DP_TP_CTL(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_CTL_A) 6932 #define DP_TP_CTL_ENABLE (1 << 31) 6933 #define DP_TP_CTL_FEC_ENABLE (1 << 30) 6934 #define DP_TP_CTL_MODE_SST (0 << 27) 6935 #define DP_TP_CTL_MODE_MST (1 << 27) 6936 #define DP_TP_CTL_FORCE_ACT (1 << 25) 6937 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18) 6938 #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15) 6939 #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8) 6940 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0 << 8) 6941 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1 << 8) 6942 #define DP_TP_CTL_LINK_TRAIN_PAT3 (4 << 8) 6943 #define DP_TP_CTL_LINK_TRAIN_PAT4 (5 << 8) 6944 #define DP_TP_CTL_LINK_TRAIN_IDLE (2 << 8) 6945 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3 << 8) 6946 #define DP_TP_CTL_SCRAMBLE_DISABLE (1 << 7) 6947 6948 /* DisplayPort Transport Status */ 6949 #define _DP_TP_STATUS_A 0x64044 6950 #define _DP_TP_STATUS_B 0x64144 6951 #define _TGL_DP_TP_STATUS_A 0x60544 6952 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B) 6953 #define TGL_DP_TP_STATUS(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_STATUS_A) 6954 #define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28) 6955 #define DP_TP_STATUS_IDLE_DONE (1 << 25) 6956 #define DP_TP_STATUS_ACT_SENT (1 << 24) 6957 #define DP_TP_STATUS_MODE_STATUS_MST (1 << 23) 6958 #define DP_TP_STATUS_AUTOTRAIN_DONE (1 << 12) 6959 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8) 6960 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4) 6961 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0) 6962 6963 /* DDI Buffer Control */ 6964 #define _DDI_BUF_CTL_A 0x64000 6965 #define _DDI_BUF_CTL_B 0x64100 6966 #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B) 6967 #define DDI_BUF_CTL_ENABLE (1 << 31) 6968 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24) 6969 #define DDI_BUF_EMP_MASK (0xf << 24) 6970 #define DDI_BUF_PHY_LINK_RATE(r) ((r) << 20) 6971 #define DDI_BUF_PORT_REVERSAL (1 << 16) 6972 #define DDI_BUF_IS_IDLE (1 << 7) 6973 #define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6) 6974 #define DDI_A_4_LANES (1 << 4) 6975 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) 6976 #define DDI_PORT_WIDTH_MASK (7 << 1) 6977 #define DDI_PORT_WIDTH_SHIFT 1 6978 #define DDI_INIT_DISPLAY_DETECTED (1 << 0) 6979 6980 /* DDI Buffer Translations */ 6981 #define _DDI_BUF_TRANS_A 0x64E00 6982 #define _DDI_BUF_TRANS_B 0x64E60 6983 #define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8) 6984 #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31) 6985 #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4) 6986 6987 /* DDI DP Compliance Control */ 6988 #define _DDI_DP_COMP_CTL_A 0x605F0 6989 #define _DDI_DP_COMP_CTL_B 0x615F0 6990 #define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B) 6991 #define DDI_DP_COMP_CTL_ENABLE (1 << 31) 6992 #define DDI_DP_COMP_CTL_D10_2 (0 << 28) 6993 #define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28) 6994 #define DDI_DP_COMP_CTL_PRBS7 (2 << 28) 6995 #define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28) 6996 #define DDI_DP_COMP_CTL_HBR2 (4 << 28) 6997 #define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28) 6998 #define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0) 6999 7000 /* DDI DP Compliance Pattern */ 7001 #define _DDI_DP_COMP_PAT_A 0x605F4 7002 #define _DDI_DP_COMP_PAT_B 0x615F4 7003 #define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4) 7004 7005 /* Sideband Interface (SBI) is programmed indirectly, via 7006 * SBI_ADDR, which contains the register offset; and SBI_DATA, 7007 * which contains the payload */ 7008 #define SBI_ADDR _MMIO(0xC6000) 7009 #define SBI_DATA _MMIO(0xC6004) 7010 #define SBI_CTL_STAT _MMIO(0xC6008) 7011 #define SBI_CTL_DEST_ICLK (0x0 << 16) 7012 #define SBI_CTL_DEST_MPHY (0x1 << 16) 7013 #define SBI_CTL_OP_IORD (0x2 << 8) 7014 #define SBI_CTL_OP_IOWR (0x3 << 8) 7015 #define SBI_CTL_OP_CRRD (0x6 << 8) 7016 #define SBI_CTL_OP_CRWR (0x7 << 8) 7017 #define SBI_RESPONSE_FAIL (0x1 << 1) 7018 #define SBI_RESPONSE_SUCCESS (0x0 << 1) 7019 #define SBI_BUSY (0x1 << 0) 7020 #define SBI_READY (0x0 << 0) 7021 7022 /* SBI offsets */ 7023 #define SBI_SSCDIVINTPHASE 0x0200 7024 #define SBI_SSCDIVINTPHASE6 0x0600 7025 #define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1 7026 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1) 7027 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1) 7028 #define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8 7029 #define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8) 7030 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8) 7031 #define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15) 7032 #define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0) 7033 #define SBI_SSCDITHPHASE 0x0204 7034 #define SBI_SSCCTL 0x020c 7035 #define SBI_SSCCTL6 0x060C 7036 #define SBI_SSCCTL_PATHALT (1 << 3) 7037 #define SBI_SSCCTL_DISABLE (1 << 0) 7038 #define SBI_SSCAUXDIV6 0x0610 7039 #define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4 7040 #define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4) 7041 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4) 7042 #define SBI_DBUFF0 0x2a00 7043 #define SBI_GEN0 0x1f00 7044 #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0) 7045 7046 /* LPT PIXCLK_GATE */ 7047 #define PIXCLK_GATE _MMIO(0xC6020) 7048 #define PIXCLK_GATE_UNGATE (1 << 0) 7049 #define PIXCLK_GATE_GATE (0 << 0) 7050 7051 /* SPLL */ 7052 #define SPLL_CTL _MMIO(0x46020) 7053 #define SPLL_PLL_ENABLE (1 << 31) 7054 #define SPLL_REF_BCLK (0 << 28) 7055 #define SPLL_REF_MUXED_SSC (1 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */ 7056 #define SPLL_REF_NON_SSC_HSW (2 << 28) 7057 #define SPLL_REF_PCH_SSC_BDW (2 << 28) 7058 #define SPLL_REF_LCPLL (3 << 28) 7059 #define SPLL_REF_MASK (3 << 28) 7060 #define SPLL_FREQ_810MHz (0 << 26) 7061 #define SPLL_FREQ_1350MHz (1 << 26) 7062 #define SPLL_FREQ_2700MHz (2 << 26) 7063 #define SPLL_FREQ_MASK (3 << 26) 7064 7065 /* WRPLL */ 7066 #define _WRPLL_CTL1 0x46040 7067 #define _WRPLL_CTL2 0x46060 7068 #define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2) 7069 #define WRPLL_PLL_ENABLE (1 << 31) 7070 #define WRPLL_REF_BCLK (0 << 28) 7071 #define WRPLL_REF_PCH_SSC (1 << 28) 7072 #define WRPLL_REF_MUXED_SSC_BDW (2 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */ 7073 #define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */ 7074 #define WRPLL_REF_LCPLL (3 << 28) 7075 #define WRPLL_REF_MASK (3 << 28) 7076 /* WRPLL divider programming */ 7077 #define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0) 7078 #define WRPLL_DIVIDER_REF_MASK (0xff) 7079 #define WRPLL_DIVIDER_POST(x) ((x) << 8) 7080 #define WRPLL_DIVIDER_POST_MASK (0x3f << 8) 7081 #define WRPLL_DIVIDER_POST_SHIFT 8 7082 #define WRPLL_DIVIDER_FEEDBACK(x) ((x) << 16) 7083 #define WRPLL_DIVIDER_FB_SHIFT 16 7084 #define WRPLL_DIVIDER_FB_MASK (0xff << 16) 7085 7086 /* Port clock selection */ 7087 #define _PORT_CLK_SEL_A 0x46100 7088 #define _PORT_CLK_SEL_B 0x46104 7089 #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B) 7090 #define PORT_CLK_SEL_MASK REG_GENMASK(31, 29) 7091 #define PORT_CLK_SEL_LCPLL_2700 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 0) 7092 #define PORT_CLK_SEL_LCPLL_1350 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 1) 7093 #define PORT_CLK_SEL_LCPLL_810 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 2) 7094 #define PORT_CLK_SEL_SPLL REG_FIELD_PREP(PORT_CLK_SEL_MASK, 3) 7095 #define PORT_CLK_SEL_WRPLL(pll) REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4 + (pll)) 7096 #define PORT_CLK_SEL_WRPLL1 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4) 7097 #define PORT_CLK_SEL_WRPLL2 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 5) 7098 #define PORT_CLK_SEL_NONE REG_FIELD_PREP(PORT_CLK_SEL_MASK, 7) 7099 7100 /* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */ 7101 #define DDI_CLK_SEL(port) PORT_CLK_SEL(port) 7102 #define DDI_CLK_SEL_MASK REG_GENMASK(31, 28) 7103 #define DDI_CLK_SEL_NONE REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x0) 7104 #define DDI_CLK_SEL_MG REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x8) 7105 #define DDI_CLK_SEL_TBT_162 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xC) 7106 #define DDI_CLK_SEL_TBT_270 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xD) 7107 #define DDI_CLK_SEL_TBT_540 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xE) 7108 #define DDI_CLK_SEL_TBT_810 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xF) 7109 7110 /* Transcoder clock selection */ 7111 #define _TRANS_CLK_SEL_A 0x46140 7112 #define _TRANS_CLK_SEL_B 0x46144 7113 #define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B) 7114 /* For each transcoder, we need to select the corresponding port clock */ 7115 #define TRANS_CLK_SEL_DISABLED (0x0 << 29) 7116 #define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29) 7117 #define TGL_TRANS_CLK_SEL_DISABLED (0x0 << 28) 7118 #define TGL_TRANS_CLK_SEL_PORT(x) (((x) + 1) << 28) 7119 7120 7121 #define CDCLK_FREQ _MMIO(0x46200) 7122 7123 #define _TRANSA_MSA_MISC 0x60410 7124 #define _TRANSB_MSA_MISC 0x61410 7125 #define _TRANSC_MSA_MISC 0x62410 7126 #define _TRANS_EDP_MSA_MISC 0x6f410 7127 #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC) 7128 /* See DP_MSA_MISC_* for the bit definitions */ 7129 7130 #define _TRANS_A_SET_CONTEXT_LATENCY 0x6007C 7131 #define _TRANS_B_SET_CONTEXT_LATENCY 0x6107C 7132 #define _TRANS_C_SET_CONTEXT_LATENCY 0x6207C 7133 #define _TRANS_D_SET_CONTEXT_LATENCY 0x6307C 7134 #define TRANS_SET_CONTEXT_LATENCY(tran) _MMIO_TRANS2(tran, _TRANS_A_SET_CONTEXT_LATENCY) 7135 #define TRANS_SET_CONTEXT_LATENCY_MASK REG_GENMASK(15, 0) 7136 #define TRANS_SET_CONTEXT_LATENCY_VALUE(x) REG_FIELD_PREP(TRANS_SET_CONTEXT_LATENCY_MASK, (x)) 7137 7138 /* LCPLL Control */ 7139 #define LCPLL_CTL _MMIO(0x130040) 7140 #define LCPLL_PLL_DISABLE (1 << 31) 7141 #define LCPLL_PLL_LOCK (1 << 30) 7142 #define LCPLL_REF_NON_SSC (0 << 28) 7143 #define LCPLL_REF_BCLK (2 << 28) 7144 #define LCPLL_REF_PCH_SSC (3 << 28) 7145 #define LCPLL_REF_MASK (3 << 28) 7146 #define LCPLL_CLK_FREQ_MASK (3 << 26) 7147 #define LCPLL_CLK_FREQ_450 (0 << 26) 7148 #define LCPLL_CLK_FREQ_54O_BDW (1 << 26) 7149 #define LCPLL_CLK_FREQ_337_5_BDW (2 << 26) 7150 #define LCPLL_CLK_FREQ_675_BDW (3 << 26) 7151 #define LCPLL_CD_CLOCK_DISABLE (1 << 25) 7152 #define LCPLL_ROOT_CD_CLOCK_DISABLE (1 << 24) 7153 #define LCPLL_CD2X_CLOCK_DISABLE (1 << 23) 7154 #define LCPLL_POWER_DOWN_ALLOW (1 << 22) 7155 #define LCPLL_CD_SOURCE_FCLK (1 << 21) 7156 #define LCPLL_CD_SOURCE_FCLK_DONE (1 << 19) 7157 7158 /* 7159 * SKL Clocks 7160 */ 7161 7162 /* CDCLK_CTL */ 7163 #define CDCLK_CTL _MMIO(0x46000) 7164 #define CDCLK_FREQ_SEL_MASK REG_GENMASK(27, 26) 7165 #define CDCLK_FREQ_450_432 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 0) 7166 #define CDCLK_FREQ_540 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1) 7167 #define CDCLK_FREQ_337_308 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2) 7168 #define CDCLK_FREQ_675_617 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3) 7169 #define BXT_CDCLK_CD2X_DIV_SEL_MASK REG_GENMASK(23, 22) 7170 #define BXT_CDCLK_CD2X_DIV_SEL_1 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0) 7171 #define BXT_CDCLK_CD2X_DIV_SEL_1_5 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1) 7172 #define BXT_CDCLK_CD2X_DIV_SEL_2 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 2) 7173 #define BXT_CDCLK_CD2X_DIV_SEL_4 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 3) 7174 #define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20) 7175 #define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19) 7176 #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3) 7177 #define ICL_CDCLK_CD2X_PIPE(pipe) (_PICK(pipe, 0, 2, 6) << 19) 7178 #define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19) 7179 #define TGL_CDCLK_CD2X_PIPE(pipe) BXT_CDCLK_CD2X_PIPE(pipe) 7180 #define TGL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE_NONE 7181 #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16) 7182 #define CDCLK_FREQ_DECIMAL_MASK (0x7ff) 7183 7184 /* CDCLK_SQUASH_CTL */ 7185 #define CDCLK_SQUASH_CTL _MMIO(0x46008) 7186 #define CDCLK_SQUASH_ENABLE REG_BIT(31) 7187 #define CDCLK_SQUASH_WINDOW_SIZE_MASK REG_GENMASK(27, 24) 7188 #define CDCLK_SQUASH_WINDOW_SIZE(x) REG_FIELD_PREP(CDCLK_SQUASH_WINDOW_SIZE_MASK, (x)) 7189 #define CDCLK_SQUASH_WAVEFORM_MASK REG_GENMASK(15, 0) 7190 #define CDCLK_SQUASH_WAVEFORM(x) REG_FIELD_PREP(CDCLK_SQUASH_WAVEFORM_MASK, (x)) 7191 7192 /* LCPLL_CTL */ 7193 #define LCPLL1_CTL _MMIO(0x46010) 7194 #define LCPLL2_CTL _MMIO(0x46014) 7195 #define LCPLL_PLL_ENABLE (1 << 31) 7196 7197 /* DPLL control1 */ 7198 #define DPLL_CTRL1 _MMIO(0x6C058) 7199 #define DPLL_CTRL1_HDMI_MODE(id) (1 << ((id) * 6 + 5)) 7200 #define DPLL_CTRL1_SSC(id) (1 << ((id) * 6 + 4)) 7201 #define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id) * 6 + 1)) 7202 #define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id) * 6 + 1) 7203 #define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate) << ((id) * 6 + 1)) 7204 #define DPLL_CTRL1_OVERRIDE(id) (1 << ((id) * 6)) 7205 #define DPLL_CTRL1_LINK_RATE_2700 0 7206 #define DPLL_CTRL1_LINK_RATE_1350 1 7207 #define DPLL_CTRL1_LINK_RATE_810 2 7208 #define DPLL_CTRL1_LINK_RATE_1620 3 7209 #define DPLL_CTRL1_LINK_RATE_1080 4 7210 #define DPLL_CTRL1_LINK_RATE_2160 5 7211 7212 /* DPLL control2 */ 7213 #define DPLL_CTRL2 _MMIO(0x6C05C) 7214 #define DPLL_CTRL2_DDI_CLK_OFF(port) (1 << ((port) + 15)) 7215 #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3 << ((port) * 3 + 1)) 7216 #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port) * 3 + 1) 7217 #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port) * 3 + 1)) 7218 #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1 << ((port) * 3)) 7219 7220 /* DPLL Status */ 7221 #define DPLL_STATUS _MMIO(0x6C060) 7222 #define DPLL_LOCK(id) (1 << ((id) * 8)) 7223 7224 /* DPLL cfg */ 7225 #define _DPLL1_CFGCR1 0x6C040 7226 #define _DPLL2_CFGCR1 0x6C048 7227 #define _DPLL3_CFGCR1 0x6C050 7228 #define DPLL_CFGCR1_FREQ_ENABLE (1 << 31) 7229 #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9) 7230 #define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9) 7231 #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff) 7232 7233 #define _DPLL1_CFGCR2 0x6C044 7234 #define _DPLL2_CFGCR2 0x6C04C 7235 #define _DPLL3_CFGCR2 0x6C054 7236 #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8) 7237 #define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8) 7238 #define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7) 7239 #define DPLL_CFGCR2_KDIV_MASK (3 << 5) 7240 #define DPLL_CFGCR2_KDIV(x) ((x) << 5) 7241 #define DPLL_CFGCR2_KDIV_5 (0 << 5) 7242 #define DPLL_CFGCR2_KDIV_2 (1 << 5) 7243 #define DPLL_CFGCR2_KDIV_3 (2 << 5) 7244 #define DPLL_CFGCR2_KDIV_1 (3 << 5) 7245 #define DPLL_CFGCR2_PDIV_MASK (7 << 2) 7246 #define DPLL_CFGCR2_PDIV(x) ((x) << 2) 7247 #define DPLL_CFGCR2_PDIV_1 (0 << 2) 7248 #define DPLL_CFGCR2_PDIV_2 (1 << 2) 7249 #define DPLL_CFGCR2_PDIV_3 (2 << 2) 7250 #define DPLL_CFGCR2_PDIV_7 (4 << 2) 7251 #define DPLL_CFGCR2_PDIV_7_INVALID (5 << 2) 7252 #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3) 7253 7254 #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1) 7255 #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2) 7256 7257 /* ICL Clocks */ 7258 #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280) 7259 #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24, 4, 5)) 7260 #define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10) 7261 #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \ 7262 (tc_port) + 12 : \ 7263 (tc_port) - TC_PORT_4 + 21)) 7264 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2) 7265 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 7266 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 7267 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27) 7268 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \ 7269 (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 7270 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \ 7271 ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 7272 7273 /* 7274 * DG1 Clocks 7275 * First registers controls the first A and B, while the second register 7276 * controls the phy C and D. The bits on these registers are the 7277 * same, but refer to different phys 7278 */ 7279 #define _DG1_DPCLKA_CFGCR0 0x164280 7280 #define _DG1_DPCLKA1_CFGCR0 0x16C280 7281 #define _DG1_DPCLKA_PHY_IDX(phy) ((phy) % 2) 7282 #define _DG1_DPCLKA_PLL_IDX(pll) ((pll) % 2) 7283 #define DG1_DPCLKA_CFGCR0(phy) _MMIO_PHY((phy) / 2, \ 7284 _DG1_DPCLKA_CFGCR0, \ 7285 _DG1_DPCLKA1_CFGCR0) 7286 #define DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT(_DG1_DPCLKA_PHY_IDX(phy) + 10) 7287 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) (_DG1_DPCLKA_PHY_IDX(phy) * 2) 7288 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) (_DG1_DPCLKA_PLL_IDX(pll) << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 7289 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (0x3 << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 7290 7291 /* ADLS Clocks */ 7292 #define _ADLS_DPCLKA_CFGCR0 0x164280 7293 #define _ADLS_DPCLKA_CFGCR1 0x1642BC 7294 #define ADLS_DPCLKA_CFGCR(phy) _MMIO_PHY((phy) / 3, \ 7295 _ADLS_DPCLKA_CFGCR0, \ 7296 _ADLS_DPCLKA_CFGCR1) 7297 #define ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy) (((phy) % 3) * 2) 7298 /* ADLS DPCLKA_CFGCR0 DDI mask */ 7299 #define ADLS_DPCLKA_DDII_SEL_MASK REG_GENMASK(5, 4) 7300 #define ADLS_DPCLKA_DDIB_SEL_MASK REG_GENMASK(3, 2) 7301 #define ADLS_DPCLKA_DDIA_SEL_MASK REG_GENMASK(1, 0) 7302 /* ADLS DPCLKA_CFGCR1 DDI mask */ 7303 #define ADLS_DPCLKA_DDIK_SEL_MASK REG_GENMASK(3, 2) 7304 #define ADLS_DPCLKA_DDIJ_SEL_MASK REG_GENMASK(1, 0) 7305 #define ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy) _PICK((phy), \ 7306 ADLS_DPCLKA_DDIA_SEL_MASK, \ 7307 ADLS_DPCLKA_DDIB_SEL_MASK, \ 7308 ADLS_DPCLKA_DDII_SEL_MASK, \ 7309 ADLS_DPCLKA_DDIJ_SEL_MASK, \ 7310 ADLS_DPCLKA_DDIK_SEL_MASK) 7311 7312 /* ICL PLL */ 7313 #define DPLL0_ENABLE 0x46010 7314 #define DPLL1_ENABLE 0x46014 7315 #define _ADLS_DPLL2_ENABLE 0x46018 7316 #define _ADLS_DPLL3_ENABLE 0x46030 7317 #define PLL_ENABLE (1 << 31) 7318 #define PLL_LOCK (1 << 30) 7319 #define PLL_POWER_ENABLE (1 << 27) 7320 #define PLL_POWER_STATE (1 << 26) 7321 #define ICL_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \ 7322 _ADLS_DPLL2_ENABLE, _ADLS_DPLL3_ENABLE) 7323 7324 #define _DG2_PLL3_ENABLE 0x4601C 7325 7326 #define DG2_PLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \ 7327 _ADLS_DPLL2_ENABLE, _DG2_PLL3_ENABLE) 7328 7329 #define TBT_PLL_ENABLE _MMIO(0x46020) 7330 7331 #define _MG_PLL1_ENABLE 0x46030 7332 #define _MG_PLL2_ENABLE 0x46034 7333 #define _MG_PLL3_ENABLE 0x46038 7334 #define _MG_PLL4_ENABLE 0x4603C 7335 /* Bits are the same as DPLL0_ENABLE */ 7336 #define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \ 7337 _MG_PLL2_ENABLE) 7338 7339 /* DG1 PLL */ 7340 #define DG1_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \ 7341 _MG_PLL1_ENABLE, _MG_PLL2_ENABLE) 7342 7343 /* ADL-P Type C PLL */ 7344 #define PORTTC1_PLL_ENABLE 0x46038 7345 #define PORTTC2_PLL_ENABLE 0x46040 7346 7347 #define ADLP_PORTTC_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), \ 7348 PORTTC1_PLL_ENABLE, \ 7349 PORTTC2_PLL_ENABLE) 7350 7351 #define _ICL_DPLL0_CFGCR0 0x164000 7352 #define _ICL_DPLL1_CFGCR0 0x164080 7353 #define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \ 7354 _ICL_DPLL1_CFGCR0) 7355 #define DPLL_CFGCR0_HDMI_MODE (1 << 30) 7356 #define DPLL_CFGCR0_SSC_ENABLE (1 << 29) 7357 #define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25) 7358 #define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25) 7359 #define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25) 7360 #define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25) 7361 #define DPLL_CFGCR0_LINK_RATE_810 (2 << 25) 7362 #define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25) 7363 #define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25) 7364 #define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25) 7365 #define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25) 7366 #define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25) 7367 #define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10) 7368 #define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10) 7369 #define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10) 7370 #define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff) 7371 7372 #define _ICL_DPLL0_CFGCR1 0x164004 7373 #define _ICL_DPLL1_CFGCR1 0x164084 7374 #define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \ 7375 _ICL_DPLL1_CFGCR1) 7376 #define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10) 7377 #define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10) 7378 #define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10) 7379 #define DPLL_CFGCR1_QDIV_MODE_SHIFT (9) 7380 #define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9) 7381 #define DPLL_CFGCR1_KDIV_MASK (7 << 6) 7382 #define DPLL_CFGCR1_KDIV_SHIFT (6) 7383 #define DPLL_CFGCR1_KDIV(x) ((x) << 6) 7384 #define DPLL_CFGCR1_KDIV_1 (1 << 6) 7385 #define DPLL_CFGCR1_KDIV_2 (2 << 6) 7386 #define DPLL_CFGCR1_KDIV_3 (4 << 6) 7387 #define DPLL_CFGCR1_PDIV_MASK (0xf << 2) 7388 #define DPLL_CFGCR1_PDIV_SHIFT (2) 7389 #define DPLL_CFGCR1_PDIV(x) ((x) << 2) 7390 #define DPLL_CFGCR1_PDIV_2 (1 << 2) 7391 #define DPLL_CFGCR1_PDIV_3 (2 << 2) 7392 #define DPLL_CFGCR1_PDIV_5 (4 << 2) 7393 #define DPLL_CFGCR1_PDIV_7 (8 << 2) 7394 #define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0) 7395 #define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0) 7396 #define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0) 7397 7398 #define _TGL_DPLL0_CFGCR0 0x164284 7399 #define _TGL_DPLL1_CFGCR0 0x16428C 7400 #define _TGL_TBTPLL_CFGCR0 0x16429C 7401 #define TGL_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \ 7402 _TGL_DPLL1_CFGCR0, \ 7403 _TGL_TBTPLL_CFGCR0) 7404 #define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \ 7405 _TGL_DPLL1_CFGCR0) 7406 7407 #define _TGL_DPLL0_DIV0 0x164B00 7408 #define _TGL_DPLL1_DIV0 0x164C00 7409 #define TGL_DPLL0_DIV0(pll) _MMIO_PLL(pll, _TGL_DPLL0_DIV0, _TGL_DPLL1_DIV0) 7410 #define TGL_DPLL0_DIV0_AFC_STARTUP_MASK REG_GENMASK(27, 25) 7411 #define TGL_DPLL0_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(TGL_DPLL0_DIV0_AFC_STARTUP_MASK, (val)) 7412 7413 #define _TGL_DPLL0_CFGCR1 0x164288 7414 #define _TGL_DPLL1_CFGCR1 0x164290 7415 #define _TGL_TBTPLL_CFGCR1 0x1642A0 7416 #define TGL_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ 7417 _TGL_DPLL1_CFGCR1, \ 7418 _TGL_TBTPLL_CFGCR1) 7419 #define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \ 7420 _TGL_DPLL1_CFGCR1) 7421 7422 #define _DG1_DPLL2_CFGCR0 0x16C284 7423 #define _DG1_DPLL3_CFGCR0 0x16C28C 7424 #define DG1_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \ 7425 _TGL_DPLL1_CFGCR0, \ 7426 _DG1_DPLL2_CFGCR0, \ 7427 _DG1_DPLL3_CFGCR0) 7428 7429 #define _DG1_DPLL2_CFGCR1 0x16C288 7430 #define _DG1_DPLL3_CFGCR1 0x16C290 7431 #define DG1_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ 7432 _TGL_DPLL1_CFGCR1, \ 7433 _DG1_DPLL2_CFGCR1, \ 7434 _DG1_DPLL3_CFGCR1) 7435 7436 /* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */ 7437 #define _ADLS_DPLL3_CFGCR0 0x1642C0 7438 #define _ADLS_DPLL4_CFGCR0 0x164294 7439 #define ADLS_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \ 7440 _TGL_DPLL1_CFGCR0, \ 7441 _ADLS_DPLL4_CFGCR0, \ 7442 _ADLS_DPLL3_CFGCR0) 7443 7444 #define _ADLS_DPLL3_CFGCR1 0x1642C4 7445 #define _ADLS_DPLL4_CFGCR1 0x164298 7446 #define ADLS_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ 7447 _TGL_DPLL1_CFGCR1, \ 7448 _ADLS_DPLL4_CFGCR1, \ 7449 _ADLS_DPLL3_CFGCR1) 7450 7451 /* BXT display engine PLL */ 7452 #define BXT_DE_PLL_CTL _MMIO(0x6d000) 7453 #define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */ 7454 #define BXT_DE_PLL_RATIO_MASK 0xff 7455 7456 #define BXT_DE_PLL_ENABLE _MMIO(0x46070) 7457 #define BXT_DE_PLL_PLL_ENABLE (1 << 31) 7458 #define BXT_DE_PLL_LOCK (1 << 30) 7459 #define BXT_DE_PLL_FREQ_REQ (1 << 23) 7460 #define BXT_DE_PLL_FREQ_REQ_ACK (1 << 22) 7461 #define ICL_CDCLK_PLL_RATIO(x) (x) 7462 #define ICL_CDCLK_PLL_RATIO_MASK 0xff 7463 7464 /* GEN9 DC */ 7465 #define DC_STATE_EN _MMIO(0x45504) 7466 #define DC_STATE_DISABLE 0 7467 #define DC_STATE_EN_DC3CO REG_BIT(30) 7468 #define DC_STATE_DC3CO_STATUS REG_BIT(29) 7469 #define DC_STATE_EN_UPTO_DC5 (1 << 0) 7470 #define DC_STATE_EN_DC9 (1 << 3) 7471 #define DC_STATE_EN_UPTO_DC6 (2 << 0) 7472 #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3 7473 7474 #define DC_STATE_DEBUG _MMIO(0x45520) 7475 #define DC_STATE_DEBUG_MASK_CORES (1 << 0) 7476 #define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1) 7477 7478 #define D_COMP_BDW _MMIO(0x138144) 7479 7480 /* Pipe WM_LINETIME - watermark line time */ 7481 #define _WM_LINETIME_A 0x45270 7482 #define _WM_LINETIME_B 0x45274 7483 #define WM_LINETIME(pipe) _MMIO_PIPE(pipe, _WM_LINETIME_A, _WM_LINETIME_B) 7484 #define HSW_LINETIME_MASK REG_GENMASK(8, 0) 7485 #define HSW_LINETIME(x) REG_FIELD_PREP(HSW_LINETIME_MASK, (x)) 7486 #define HSW_IPS_LINETIME_MASK REG_GENMASK(24, 16) 7487 #define HSW_IPS_LINETIME(x) REG_FIELD_PREP(HSW_IPS_LINETIME_MASK, (x)) 7488 7489 /* SFUSE_STRAP */ 7490 #define SFUSE_STRAP _MMIO(0xc2014) 7491 #define SFUSE_STRAP_FUSE_LOCK (1 << 13) 7492 #define SFUSE_STRAP_RAW_FREQUENCY (1 << 8) 7493 #define SFUSE_STRAP_DISPLAY_DISABLED (1 << 7) 7494 #define SFUSE_STRAP_CRT_DISABLED (1 << 6) 7495 #define SFUSE_STRAP_DDIF_DETECTED (1 << 3) 7496 #define SFUSE_STRAP_DDIB_DETECTED (1 << 2) 7497 #define SFUSE_STRAP_DDIC_DETECTED (1 << 1) 7498 #define SFUSE_STRAP_DDID_DETECTED (1 << 0) 7499 7500 #define WM_MISC _MMIO(0x45260) 7501 #define WM_MISC_DATA_PARTITION_5_6 (1 << 0) 7502 7503 #define WM_DBG _MMIO(0x45280) 7504 #define WM_DBG_DISALLOW_MULTIPLE_LP (1 << 0) 7505 #define WM_DBG_DISALLOW_MAXFIFO (1 << 1) 7506 #define WM_DBG_DISALLOW_SPRITE (1 << 2) 7507 7508 /* pipe CSC */ 7509 #define _PIPE_A_CSC_COEFF_RY_GY 0x49010 7510 #define _PIPE_A_CSC_COEFF_BY 0x49014 7511 #define _PIPE_A_CSC_COEFF_RU_GU 0x49018 7512 #define _PIPE_A_CSC_COEFF_BU 0x4901c 7513 #define _PIPE_A_CSC_COEFF_RV_GV 0x49020 7514 #define _PIPE_A_CSC_COEFF_BV 0x49024 7515 7516 #define _PIPE_A_CSC_MODE 0x49028 7517 #define ICL_CSC_ENABLE (1 << 31) /* icl+ */ 7518 #define ICL_OUTPUT_CSC_ENABLE (1 << 30) /* icl+ */ 7519 #define CSC_BLACK_SCREEN_OFFSET (1 << 2) /* ilk/snb */ 7520 #define CSC_POSITION_BEFORE_GAMMA (1 << 1) /* pre-glk */ 7521 #define CSC_MODE_YUV_TO_RGB (1 << 0) /* ilk/snb */ 7522 7523 #define _PIPE_A_CSC_PREOFF_HI 0x49030 7524 #define _PIPE_A_CSC_PREOFF_ME 0x49034 7525 #define _PIPE_A_CSC_PREOFF_LO 0x49038 7526 #define _PIPE_A_CSC_POSTOFF_HI 0x49040 7527 #define _PIPE_A_CSC_POSTOFF_ME 0x49044 7528 #define _PIPE_A_CSC_POSTOFF_LO 0x49048 7529 7530 #define _PIPE_B_CSC_COEFF_RY_GY 0x49110 7531 #define _PIPE_B_CSC_COEFF_BY 0x49114 7532 #define _PIPE_B_CSC_COEFF_RU_GU 0x49118 7533 #define _PIPE_B_CSC_COEFF_BU 0x4911c 7534 #define _PIPE_B_CSC_COEFF_RV_GV 0x49120 7535 #define _PIPE_B_CSC_COEFF_BV 0x49124 7536 #define _PIPE_B_CSC_MODE 0x49128 7537 #define _PIPE_B_CSC_PREOFF_HI 0x49130 7538 #define _PIPE_B_CSC_PREOFF_ME 0x49134 7539 #define _PIPE_B_CSC_PREOFF_LO 0x49138 7540 #define _PIPE_B_CSC_POSTOFF_HI 0x49140 7541 #define _PIPE_B_CSC_POSTOFF_ME 0x49144 7542 #define _PIPE_B_CSC_POSTOFF_LO 0x49148 7543 7544 #define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY) 7545 #define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY) 7546 #define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU) 7547 #define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU) 7548 #define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV) 7549 #define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV) 7550 #define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE) 7551 #define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI) 7552 #define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME) 7553 #define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO) 7554 #define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI) 7555 #define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME) 7556 #define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) 7557 7558 /* Pipe Output CSC */ 7559 #define _PIPE_A_OUTPUT_CSC_COEFF_RY_GY 0x49050 7560 #define _PIPE_A_OUTPUT_CSC_COEFF_BY 0x49054 7561 #define _PIPE_A_OUTPUT_CSC_COEFF_RU_GU 0x49058 7562 #define _PIPE_A_OUTPUT_CSC_COEFF_BU 0x4905c 7563 #define _PIPE_A_OUTPUT_CSC_COEFF_RV_GV 0x49060 7564 #define _PIPE_A_OUTPUT_CSC_COEFF_BV 0x49064 7565 #define _PIPE_A_OUTPUT_CSC_PREOFF_HI 0x49068 7566 #define _PIPE_A_OUTPUT_CSC_PREOFF_ME 0x4906c 7567 #define _PIPE_A_OUTPUT_CSC_PREOFF_LO 0x49070 7568 #define _PIPE_A_OUTPUT_CSC_POSTOFF_HI 0x49074 7569 #define _PIPE_A_OUTPUT_CSC_POSTOFF_ME 0x49078 7570 #define _PIPE_A_OUTPUT_CSC_POSTOFF_LO 0x4907c 7571 7572 #define _PIPE_B_OUTPUT_CSC_COEFF_RY_GY 0x49150 7573 #define _PIPE_B_OUTPUT_CSC_COEFF_BY 0x49154 7574 #define _PIPE_B_OUTPUT_CSC_COEFF_RU_GU 0x49158 7575 #define _PIPE_B_OUTPUT_CSC_COEFF_BU 0x4915c 7576 #define _PIPE_B_OUTPUT_CSC_COEFF_RV_GV 0x49160 7577 #define _PIPE_B_OUTPUT_CSC_COEFF_BV 0x49164 7578 #define _PIPE_B_OUTPUT_CSC_PREOFF_HI 0x49168 7579 #define _PIPE_B_OUTPUT_CSC_PREOFF_ME 0x4916c 7580 #define _PIPE_B_OUTPUT_CSC_PREOFF_LO 0x49170 7581 #define _PIPE_B_OUTPUT_CSC_POSTOFF_HI 0x49174 7582 #define _PIPE_B_OUTPUT_CSC_POSTOFF_ME 0x49178 7583 #define _PIPE_B_OUTPUT_CSC_POSTOFF_LO 0x4917c 7584 7585 #define PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe,\ 7586 _PIPE_A_OUTPUT_CSC_COEFF_RY_GY,\ 7587 _PIPE_B_OUTPUT_CSC_COEFF_RY_GY) 7588 #define PIPE_CSC_OUTPUT_COEFF_BY(pipe) _MMIO_PIPE(pipe, \ 7589 _PIPE_A_OUTPUT_CSC_COEFF_BY, \ 7590 _PIPE_B_OUTPUT_CSC_COEFF_BY) 7591 #define PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, \ 7592 _PIPE_A_OUTPUT_CSC_COEFF_RU_GU, \ 7593 _PIPE_B_OUTPUT_CSC_COEFF_RU_GU) 7594 #define PIPE_CSC_OUTPUT_COEFF_BU(pipe) _MMIO_PIPE(pipe, \ 7595 _PIPE_A_OUTPUT_CSC_COEFF_BU, \ 7596 _PIPE_B_OUTPUT_CSC_COEFF_BU) 7597 #define PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, \ 7598 _PIPE_A_OUTPUT_CSC_COEFF_RV_GV, \ 7599 _PIPE_B_OUTPUT_CSC_COEFF_RV_GV) 7600 #define PIPE_CSC_OUTPUT_COEFF_BV(pipe) _MMIO_PIPE(pipe, \ 7601 _PIPE_A_OUTPUT_CSC_COEFF_BV, \ 7602 _PIPE_B_OUTPUT_CSC_COEFF_BV) 7603 #define PIPE_CSC_OUTPUT_PREOFF_HI(pipe) _MMIO_PIPE(pipe, \ 7604 _PIPE_A_OUTPUT_CSC_PREOFF_HI, \ 7605 _PIPE_B_OUTPUT_CSC_PREOFF_HI) 7606 #define PIPE_CSC_OUTPUT_PREOFF_ME(pipe) _MMIO_PIPE(pipe, \ 7607 _PIPE_A_OUTPUT_CSC_PREOFF_ME, \ 7608 _PIPE_B_OUTPUT_CSC_PREOFF_ME) 7609 #define PIPE_CSC_OUTPUT_PREOFF_LO(pipe) _MMIO_PIPE(pipe, \ 7610 _PIPE_A_OUTPUT_CSC_PREOFF_LO, \ 7611 _PIPE_B_OUTPUT_CSC_PREOFF_LO) 7612 #define PIPE_CSC_OUTPUT_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, \ 7613 _PIPE_A_OUTPUT_CSC_POSTOFF_HI, \ 7614 _PIPE_B_OUTPUT_CSC_POSTOFF_HI) 7615 #define PIPE_CSC_OUTPUT_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, \ 7616 _PIPE_A_OUTPUT_CSC_POSTOFF_ME, \ 7617 _PIPE_B_OUTPUT_CSC_POSTOFF_ME) 7618 #define PIPE_CSC_OUTPUT_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, \ 7619 _PIPE_A_OUTPUT_CSC_POSTOFF_LO, \ 7620 _PIPE_B_OUTPUT_CSC_POSTOFF_LO) 7621 7622 /* pipe degamma/gamma LUTs on IVB+ */ 7623 #define _PAL_PREC_INDEX_A 0x4A400 7624 #define _PAL_PREC_INDEX_B 0x4AC00 7625 #define _PAL_PREC_INDEX_C 0x4B400 7626 #define PAL_PREC_10_12_BIT (0 << 31) 7627 #define PAL_PREC_SPLIT_MODE (1 << 31) 7628 #define PAL_PREC_AUTO_INCREMENT (1 << 15) 7629 #define PAL_PREC_INDEX_VALUE_MASK (0x3ff << 0) 7630 #define PAL_PREC_INDEX_VALUE(x) ((x) << 0) 7631 #define _PAL_PREC_DATA_A 0x4A404 7632 #define _PAL_PREC_DATA_B 0x4AC04 7633 #define _PAL_PREC_DATA_C 0x4B404 7634 #define _PAL_PREC_GC_MAX_A 0x4A410 7635 #define _PAL_PREC_GC_MAX_B 0x4AC10 7636 #define _PAL_PREC_GC_MAX_C 0x4B410 7637 #define PREC_PAL_DATA_RED_MASK REG_GENMASK(29, 20) 7638 #define PREC_PAL_DATA_GREEN_MASK REG_GENMASK(19, 10) 7639 #define PREC_PAL_DATA_BLUE_MASK REG_GENMASK(9, 0) 7640 #define _PAL_PREC_EXT_GC_MAX_A 0x4A420 7641 #define _PAL_PREC_EXT_GC_MAX_B 0x4AC20 7642 #define _PAL_PREC_EXT_GC_MAX_C 0x4B420 7643 #define _PAL_PREC_EXT2_GC_MAX_A 0x4A430 7644 #define _PAL_PREC_EXT2_GC_MAX_B 0x4AC30 7645 #define _PAL_PREC_EXT2_GC_MAX_C 0x4B430 7646 7647 #define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B) 7648 #define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B) 7649 #define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4) 7650 #define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4) 7651 #define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4) 7652 7653 #define _PRE_CSC_GAMC_INDEX_A 0x4A484 7654 #define _PRE_CSC_GAMC_INDEX_B 0x4AC84 7655 #define _PRE_CSC_GAMC_INDEX_C 0x4B484 7656 #define PRE_CSC_GAMC_AUTO_INCREMENT (1 << 10) 7657 #define _PRE_CSC_GAMC_DATA_A 0x4A488 7658 #define _PRE_CSC_GAMC_DATA_B 0x4AC88 7659 #define _PRE_CSC_GAMC_DATA_C 0x4B488 7660 7661 #define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B) 7662 #define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B) 7663 7664 /* ICL Multi segmented gamma */ 7665 #define _PAL_PREC_MULTI_SEG_INDEX_A 0x4A408 7666 #define _PAL_PREC_MULTI_SEG_INDEX_B 0x4AC08 7667 #define PAL_PREC_MULTI_SEGMENT_AUTO_INCREMENT REG_BIT(15) 7668 #define PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK REG_GENMASK(4, 0) 7669 7670 #define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C 7671 #define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C 7672 #define PAL_PREC_MULTI_SEG_RED_LDW_MASK REG_GENMASK(29, 24) 7673 #define PAL_PREC_MULTI_SEG_RED_UDW_MASK REG_GENMASK(29, 20) 7674 #define PAL_PREC_MULTI_SEG_GREEN_LDW_MASK REG_GENMASK(19, 14) 7675 #define PAL_PREC_MULTI_SEG_GREEN_UDW_MASK REG_GENMASK(19, 10) 7676 #define PAL_PREC_MULTI_SEG_BLUE_LDW_MASK REG_GENMASK(9, 4) 7677 #define PAL_PREC_MULTI_SEG_BLUE_UDW_MASK REG_GENMASK(9, 0) 7678 7679 #define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \ 7680 _PAL_PREC_MULTI_SEG_INDEX_A, \ 7681 _PAL_PREC_MULTI_SEG_INDEX_B) 7682 #define PREC_PAL_MULTI_SEG_DATA(pipe) _MMIO_PIPE(pipe, \ 7683 _PAL_PREC_MULTI_SEG_DATA_A, \ 7684 _PAL_PREC_MULTI_SEG_DATA_B) 7685 7686 #define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4) 7687 7688 /* Plane CSC Registers */ 7689 #define _PLANE_CSC_RY_GY_1_A 0x70210 7690 #define _PLANE_CSC_RY_GY_2_A 0x70310 7691 7692 #define _PLANE_CSC_RY_GY_1_B 0x71210 7693 #define _PLANE_CSC_RY_GY_2_B 0x71310 7694 7695 #define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, \ 7696 _PLANE_CSC_RY_GY_1_B) 7697 #define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \ 7698 _PLANE_INPUT_CSC_RY_GY_2_B) 7699 #define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane, \ 7700 _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \ 7701 _PLANE_CSC_RY_GY_2(pipe) + (index) * 4) 7702 7703 #define _PLANE_CSC_PREOFF_HI_1_A 0x70228 7704 #define _PLANE_CSC_PREOFF_HI_2_A 0x70328 7705 7706 #define _PLANE_CSC_PREOFF_HI_1_B 0x71228 7707 #define _PLANE_CSC_PREOFF_HI_2_B 0x71328 7708 7709 #define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, \ 7710 _PLANE_CSC_PREOFF_HI_1_B) 7711 #define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, \ 7712 _PLANE_CSC_PREOFF_HI_2_B) 7713 #define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + \ 7714 (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \ 7715 (index) * 4) 7716 7717 #define _PLANE_CSC_POSTOFF_HI_1_A 0x70234 7718 #define _PLANE_CSC_POSTOFF_HI_2_A 0x70334 7719 7720 #define _PLANE_CSC_POSTOFF_HI_1_B 0x71234 7721 #define _PLANE_CSC_POSTOFF_HI_2_B 0x71334 7722 7723 #define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, \ 7724 _PLANE_CSC_POSTOFF_HI_1_B) 7725 #define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, \ 7726 _PLANE_CSC_POSTOFF_HI_2_B) 7727 #define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + \ 7728 (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \ 7729 (index) * 4) 7730 7731 /* pipe CSC & degamma/gamma LUTs on CHV */ 7732 #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900) 7733 #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904) 7734 #define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908) 7735 #define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C) 7736 #define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910) 7737 #define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000) 7738 #define CGM_PIPE_DEGAMMA_RED_MASK REG_GENMASK(13, 0) 7739 #define CGM_PIPE_DEGAMMA_GREEN_MASK REG_GENMASK(29, 16) 7740 #define CGM_PIPE_DEGAMMA_BLUE_MASK REG_GENMASK(13, 0) 7741 #define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000) 7742 #define CGM_PIPE_GAMMA_RED_MASK REG_GENMASK(9, 0) 7743 #define CGM_PIPE_GAMMA_GREEN_MASK REG_GENMASK(25, 16) 7744 #define CGM_PIPE_GAMMA_BLUE_MASK REG_GENMASK(9, 0) 7745 #define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00) 7746 #define CGM_PIPE_MODE_GAMMA (1 << 2) 7747 #define CGM_PIPE_MODE_CSC (1 << 1) 7748 #define CGM_PIPE_MODE_DEGAMMA (1 << 0) 7749 7750 #define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900) 7751 #define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904) 7752 #define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908) 7753 #define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C) 7754 #define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910) 7755 #define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000) 7756 #define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000) 7757 #define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00) 7758 7759 #define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01) 7760 #define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23) 7761 #define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45) 7762 #define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67) 7763 #define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8) 7764 #define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4) 7765 #define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4) 7766 #define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE) 7767 7768 /* Gen4+ Timestamp and Pipe Frame time stamp registers */ 7769 #define GEN4_TIMESTAMP _MMIO(0x2358) 7770 #define ILK_TIMESTAMP_HI _MMIO(0x70070) 7771 #define IVB_TIMESTAMP_CTR _MMIO(0x44070) 7772 7773 #define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074) 7774 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0 7775 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff 7776 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12 7777 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12) 7778 7779 #define _PIPE_FRMTMSTMP_A 0x70048 7780 #define PIPE_FRMTMSTMP(pipe) \ 7781 _MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A) 7782 7783 /* Display Stream Splitter Control */ 7784 #define DSS_CTL1 _MMIO(0x67400) 7785 #define SPLITTER_ENABLE (1 << 31) 7786 #define JOINER_ENABLE (1 << 30) 7787 #define DUAL_LINK_MODE_INTERLEAVE (1 << 24) 7788 #define DUAL_LINK_MODE_FRONTBACK (0 << 24) 7789 #define OVERLAP_PIXELS_MASK (0xf << 16) 7790 #define OVERLAP_PIXELS(pixels) ((pixels) << 16) 7791 #define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) 7792 #define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) 7793 #define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0 7794 7795 #define DSS_CTL2 _MMIO(0x67404) 7796 #define LEFT_BRANCH_VDSC_ENABLE (1 << 31) 7797 #define RIGHT_BRANCH_VDSC_ENABLE (1 << 15) 7798 #define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) 7799 #define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) 7800 7801 #define _ICL_PIPE_DSS_CTL1_PB 0x78200 7802 #define _ICL_PIPE_DSS_CTL1_PC 0x78400 7803 #define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7804 _ICL_PIPE_DSS_CTL1_PB, \ 7805 _ICL_PIPE_DSS_CTL1_PC) 7806 #define BIG_JOINER_ENABLE (1 << 29) 7807 #define MASTER_BIG_JOINER_ENABLE (1 << 28) 7808 #define VGA_CENTERING_ENABLE (1 << 27) 7809 #define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25) 7810 #define SPLITTER_CONFIGURATION_2_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0) 7811 #define SPLITTER_CONFIGURATION_4_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1) 7812 #define UNCOMPRESSED_JOINER_MASTER (1 << 21) 7813 #define UNCOMPRESSED_JOINER_SLAVE (1 << 20) 7814 7815 #define _ICL_PIPE_DSS_CTL2_PB 0x78204 7816 #define _ICL_PIPE_DSS_CTL2_PC 0x78404 7817 #define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7818 _ICL_PIPE_DSS_CTL2_PB, \ 7819 _ICL_PIPE_DSS_CTL2_PC) 7820 7821 #define GGC _MMIO(0x108040) 7822 #define GMS_MASK REG_GENMASK(15, 8) 7823 #define GGMS_MASK REG_GENMASK(7, 6) 7824 7825 #define GEN12_GSMBASE _MMIO(0x108100) 7826 #define GEN12_DSMBASE _MMIO(0x1080C0) 7827 #define GEN12_BDSM_MASK REG_GENMASK64(63, 20) 7828 7829 #define XEHP_CLOCK_GATE_DIS _MMIO(0x101014) 7830 #define SGSI_SIDECLK_DIS REG_BIT(17) 7831 #define SGGI_DIS REG_BIT(15) 7832 #define SGR_DIS REG_BIT(13) 7833 7834 #define _ICL_PHY_MISC_A 0x64C00 7835 #define _ICL_PHY_MISC_B 0x64C04 7836 #define _DG2_PHY_MISC_TC1 0x64C14 /* TC1="PHY E" but offset as if "PHY F" */ 7837 #define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, _ICL_PHY_MISC_B) 7838 #define DG2_PHY_MISC(port) ((port) == PHY_E ? _MMIO(_DG2_PHY_MISC_TC1) : \ 7839 ICL_PHY_MISC(port)) 7840 #define ICL_PHY_MISC_MUX_DDID (1 << 28) 7841 #define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23) 7842 #define DG2_PHY_DP_TX_ACK_MASK REG_GENMASK(23, 20) 7843 7844 /* Icelake Display Stream Compression Registers */ 7845 #define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200) 7846 #define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00) 7847 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270 7848 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370 7849 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470 7850 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC 0x78570 7851 #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7852 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \ 7853 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC) 7854 #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7855 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \ 7856 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC) 7857 #define DSC_ALT_ICH_SEL (1 << 20) 7858 #define DSC_VBR_ENABLE (1 << 19) 7859 #define DSC_422_ENABLE (1 << 18) 7860 #define DSC_COLOR_SPACE_CONVERSION (1 << 17) 7861 #define DSC_BLOCK_PREDICTION (1 << 16) 7862 #define DSC_LINE_BUF_DEPTH_SHIFT 12 7863 #define DSC_BPC_SHIFT 8 7864 #define DSC_VER_MIN_SHIFT 4 7865 #define DSC_VER_MAJ (0x1 << 0) 7866 7867 #define DSCA_PICTURE_PARAMETER_SET_1 _MMIO(0x6B204) 7868 #define DSCC_PICTURE_PARAMETER_SET_1 _MMIO(0x6BA04) 7869 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB 0x78274 7870 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB 0x78374 7871 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC 0x78474 7872 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC 0x78574 7873 #define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7874 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \ 7875 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC) 7876 #define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7877 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \ 7878 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC) 7879 #define DSC_BPP(bpp) ((bpp) << 0) 7880 7881 #define DSCA_PICTURE_PARAMETER_SET_2 _MMIO(0x6B208) 7882 #define DSCC_PICTURE_PARAMETER_SET_2 _MMIO(0x6BA08) 7883 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB 0x78278 7884 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB 0x78378 7885 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC 0x78478 7886 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC 0x78578 7887 #define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7888 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \ 7889 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC) 7890 #define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7891 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \ 7892 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC) 7893 #define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16) 7894 #define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0) 7895 7896 #define DSCA_PICTURE_PARAMETER_SET_3 _MMIO(0x6B20C) 7897 #define DSCC_PICTURE_PARAMETER_SET_3 _MMIO(0x6BA0C) 7898 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB 0x7827C 7899 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB 0x7837C 7900 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC 0x7847C 7901 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC 0x7857C 7902 #define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7903 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \ 7904 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC) 7905 #define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7906 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \ 7907 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC) 7908 #define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16) 7909 #define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0) 7910 7911 #define DSCA_PICTURE_PARAMETER_SET_4 _MMIO(0x6B210) 7912 #define DSCC_PICTURE_PARAMETER_SET_4 _MMIO(0x6BA10) 7913 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB 0x78280 7914 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB 0x78380 7915 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC 0x78480 7916 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC 0x78580 7917 #define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7918 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \ 7919 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC) 7920 #define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7921 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \ 7922 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC) 7923 #define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16) 7924 #define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0) 7925 7926 #define DSCA_PICTURE_PARAMETER_SET_5 _MMIO(0x6B214) 7927 #define DSCC_PICTURE_PARAMETER_SET_5 _MMIO(0x6BA14) 7928 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB 0x78284 7929 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB 0x78384 7930 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC 0x78484 7931 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC 0x78584 7932 #define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7933 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \ 7934 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC) 7935 #define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7936 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \ 7937 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC) 7938 #define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16) 7939 #define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0) 7940 7941 #define DSCA_PICTURE_PARAMETER_SET_6 _MMIO(0x6B218) 7942 #define DSCC_PICTURE_PARAMETER_SET_6 _MMIO(0x6BA18) 7943 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB 0x78288 7944 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB 0x78388 7945 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC 0x78488 7946 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC 0x78588 7947 #define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7948 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \ 7949 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC) 7950 #define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7951 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \ 7952 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC) 7953 #define DSC_FLATNESS_MAX_QP(max_qp) ((max_qp) << 24) 7954 #define DSC_FLATNESS_MIN_QP(min_qp) ((min_qp) << 16) 7955 #define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8) 7956 #define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0) 7957 7958 #define DSCA_PICTURE_PARAMETER_SET_7 _MMIO(0x6B21C) 7959 #define DSCC_PICTURE_PARAMETER_SET_7 _MMIO(0x6BA1C) 7960 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB 0x7828C 7961 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB 0x7838C 7962 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC 0x7848C 7963 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC 0x7858C 7964 #define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7965 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \ 7966 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC) 7967 #define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7968 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \ 7969 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC) 7970 #define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16) 7971 #define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0) 7972 7973 #define DSCA_PICTURE_PARAMETER_SET_8 _MMIO(0x6B220) 7974 #define DSCC_PICTURE_PARAMETER_SET_8 _MMIO(0x6BA20) 7975 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB 0x78290 7976 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB 0x78390 7977 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC 0x78490 7978 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC 0x78590 7979 #define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7980 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \ 7981 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC) 7982 #define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7983 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \ 7984 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC) 7985 #define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16) 7986 #define DSC_FINAL_OFFSET(final_offset) ((final_offset) << 0) 7987 7988 #define DSCA_PICTURE_PARAMETER_SET_9 _MMIO(0x6B224) 7989 #define DSCC_PICTURE_PARAMETER_SET_9 _MMIO(0x6BA24) 7990 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB 0x78294 7991 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB 0x78394 7992 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC 0x78494 7993 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC 0x78594 7994 #define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7995 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \ 7996 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC) 7997 #define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7998 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \ 7999 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC) 8000 #define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16) 8001 #define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0) 8002 8003 #define DSCA_PICTURE_PARAMETER_SET_10 _MMIO(0x6B228) 8004 #define DSCC_PICTURE_PARAMETER_SET_10 _MMIO(0x6BA28) 8005 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298 8006 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398 8007 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498 8008 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC 0x78598 8009 #define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8010 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \ 8011 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC) 8012 #define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8013 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \ 8014 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC) 8015 #define DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low) ((rc_tgt_off_low) << 20) 8016 #define DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high) ((rc_tgt_off_high) << 16) 8017 #define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8) 8018 #define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0) 8019 8020 #define DSCA_PICTURE_PARAMETER_SET_11 _MMIO(0x6B22C) 8021 #define DSCC_PICTURE_PARAMETER_SET_11 _MMIO(0x6BA2C) 8022 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C 8023 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C 8024 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C 8025 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC 0x7859C 8026 #define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8027 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \ 8028 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC) 8029 #define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8030 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \ 8031 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC) 8032 8033 #define DSCA_PICTURE_PARAMETER_SET_12 _MMIO(0x6B260) 8034 #define DSCC_PICTURE_PARAMETER_SET_12 _MMIO(0x6BA60) 8035 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0 8036 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0 8037 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0 8038 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC 0x785A0 8039 #define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8040 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \ 8041 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC) 8042 #define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8043 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \ 8044 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC) 8045 8046 #define DSCA_PICTURE_PARAMETER_SET_13 _MMIO(0x6B264) 8047 #define DSCC_PICTURE_PARAMETER_SET_13 _MMIO(0x6BA64) 8048 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4 8049 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4 8050 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4 8051 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC 0x785A4 8052 #define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8053 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \ 8054 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC) 8055 #define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8056 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \ 8057 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC) 8058 8059 #define DSCA_PICTURE_PARAMETER_SET_14 _MMIO(0x6B268) 8060 #define DSCC_PICTURE_PARAMETER_SET_14 _MMIO(0x6BA68) 8061 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8 8062 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8 8063 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8 8064 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC 0x785A8 8065 #define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8066 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \ 8067 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC) 8068 #define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8069 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \ 8070 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC) 8071 8072 #define DSCA_PICTURE_PARAMETER_SET_15 _MMIO(0x6B26C) 8073 #define DSCC_PICTURE_PARAMETER_SET_15 _MMIO(0x6BA6C) 8074 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC 8075 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC 8076 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC 8077 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC 0x785AC 8078 #define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8079 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \ 8080 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC) 8081 #define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8082 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \ 8083 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC) 8084 8085 #define DSCA_PICTURE_PARAMETER_SET_16 _MMIO(0x6B270) 8086 #define DSCC_PICTURE_PARAMETER_SET_16 _MMIO(0x6BA70) 8087 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0 8088 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0 8089 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0 8090 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC 0x785B0 8091 #define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8092 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \ 8093 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC) 8094 #define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8095 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \ 8096 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC) 8097 #define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) ((slice_row_per_frame) << 20) 8098 #define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16) 8099 #define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0) 8100 8101 /* Icelake Rate Control Buffer Threshold Registers */ 8102 #define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230) 8103 #define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4) 8104 #define DSCC_RC_BUF_THRESH_0 _MMIO(0x6BA30) 8105 #define DSCC_RC_BUF_THRESH_0_UDW _MMIO(0x6BA30 + 4) 8106 #define _ICL_DSC0_RC_BUF_THRESH_0_PB (0x78254) 8107 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB (0x78254 + 4) 8108 #define _ICL_DSC1_RC_BUF_THRESH_0_PB (0x78354) 8109 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB (0x78354 + 4) 8110 #define _ICL_DSC0_RC_BUF_THRESH_0_PC (0x78454) 8111 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC (0x78454 + 4) 8112 #define _ICL_DSC1_RC_BUF_THRESH_0_PC (0x78554) 8113 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC (0x78554 + 4) 8114 #define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8115 _ICL_DSC0_RC_BUF_THRESH_0_PB, \ 8116 _ICL_DSC0_RC_BUF_THRESH_0_PC) 8117 #define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8118 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \ 8119 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC) 8120 #define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8121 _ICL_DSC1_RC_BUF_THRESH_0_PB, \ 8122 _ICL_DSC1_RC_BUF_THRESH_0_PC) 8123 #define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8124 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \ 8125 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC) 8126 8127 #define DSCA_RC_BUF_THRESH_1 _MMIO(0x6B238) 8128 #define DSCA_RC_BUF_THRESH_1_UDW _MMIO(0x6B238 + 4) 8129 #define DSCC_RC_BUF_THRESH_1 _MMIO(0x6BA38) 8130 #define DSCC_RC_BUF_THRESH_1_UDW _MMIO(0x6BA38 + 4) 8131 #define _ICL_DSC0_RC_BUF_THRESH_1_PB (0x7825C) 8132 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB (0x7825C + 4) 8133 #define _ICL_DSC1_RC_BUF_THRESH_1_PB (0x7835C) 8134 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB (0x7835C + 4) 8135 #define _ICL_DSC0_RC_BUF_THRESH_1_PC (0x7845C) 8136 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC (0x7845C + 4) 8137 #define _ICL_DSC1_RC_BUF_THRESH_1_PC (0x7855C) 8138 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC (0x7855C + 4) 8139 #define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8140 _ICL_DSC0_RC_BUF_THRESH_1_PB, \ 8141 _ICL_DSC0_RC_BUF_THRESH_1_PC) 8142 #define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8143 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \ 8144 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC) 8145 #define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8146 _ICL_DSC1_RC_BUF_THRESH_1_PB, \ 8147 _ICL_DSC1_RC_BUF_THRESH_1_PC) 8148 #define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8149 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \ 8150 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC) 8151 8152 #define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0) 8153 #define MODULAR_FIA_MASK (1 << 4) 8154 #define TC_LIVE_STATE_TBT(idx) (1 << ((idx) * 8 + 6)) 8155 #define TC_LIVE_STATE_TC(idx) (1 << ((idx) * 8 + 5)) 8156 #define DP_LANE_ASSIGNMENT_SHIFT(idx) ((idx) * 8) 8157 #define DP_LANE_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 8)) 8158 #define DP_LANE_ASSIGNMENT(idx, x) ((x) << ((idx) * 8)) 8159 8160 #define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890) 8161 #define DP_PHY_MODE_STATUS_COMPLETED(idx) (1 << (idx)) 8162 8163 #define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894) 8164 #define DP_PHY_MODE_STATUS_NOT_SAFE(idx) (1 << (idx)) 8165 8166 #define PORT_TX_DFLEXPA1(fia) _MMIO_FIA((fia), 0x00880) 8167 #define DP_PIN_ASSIGNMENT_SHIFT(idx) ((idx) * 4) 8168 #define DP_PIN_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 4)) 8169 #define DP_PIN_ASSIGNMENT(idx, x) ((x) << ((idx) * 4)) 8170 8171 #define _TCSS_DDI_STATUS_1 0x161500 8172 #define _TCSS_DDI_STATUS_2 0x161504 8173 #define TCSS_DDI_STATUS(tc) _MMIO(_PICK_EVEN(tc, \ 8174 _TCSS_DDI_STATUS_1, \ 8175 _TCSS_DDI_STATUS_2)) 8176 #define TCSS_DDI_STATUS_READY REG_BIT(2) 8177 #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1) 8178 #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0) 8179 8180 #define PRIMARY_SPI_TRIGGER _MMIO(0x102040) 8181 #define PRIMARY_SPI_ADDRESS _MMIO(0x102080) 8182 #define PRIMARY_SPI_REGIONID _MMIO(0x102084) 8183 #define SPI_STATIC_REGIONS _MMIO(0x102090) 8184 #define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0) 8185 #define OROM_OFFSET _MMIO(0x1020c0) 8186 #define OROM_OFFSET_MASK REG_GENMASK(20, 16) 8187 8188 /* This register controls the Display State Buffer (DSB) engines. */ 8189 #define _DSBSL_INSTANCE_BASE 0x70B00 8190 #define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \ 8191 (pipe) * 0x1000 + (id) * 0x100) 8192 #define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0) 8193 #define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4) 8194 #define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8) 8195 #define DSB_ENABLE (1 << 31) 8196 #define DSB_STATUS (1 << 0) 8197 8198 #define CLKREQ_POLICY _MMIO(0x101038) 8199 #define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1) 8200 8201 #define CLKGATE_DIS_MISC _MMIO(0x46534) 8202 #define CLKGATE_DIS_MISC_DMASC_GATING_DIS REG_BIT(21) 8203 8204 #define GEN12_CULLBIT1 _MMIO(0x6100) 8205 #define GEN12_CULLBIT2 _MMIO(0x7030) 8206 #define GEN12_STATE_ACK_DEBUG _MMIO(0x20BC) 8207 8208 #define _MTL_CLKGATE_DIS_TRANS_A 0x604E8 8209 #define _MTL_CLKGATE_DIS_TRANS_B 0x614E8 8210 #define MTL_CLKGATE_DIS_TRANS(trans) _MMIO_TRANS2(trans, _MTL_CLKGATE_DIS_TRANS_A) 8211 #define MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS REG_BIT(7) 8212 8213 #define MTL_LATENCY_LP0_LP1 _MMIO(0x45780) 8214 #define MTL_LATENCY_LP2_LP3 _MMIO(0x45784) 8215 #define MTL_LATENCY_LP4_LP5 _MMIO(0x45788) 8216 #define MTL_LATENCY_LEVEL_EVEN_MASK REG_GENMASK(12, 0) 8217 #define MTL_LATENCY_LEVEL_ODD_MASK REG_GENMASK(28, 16) 8218 8219 #define MTL_LATENCY_SAGV _MMIO(0x4578b) 8220 #define MTL_LATENCY_QCLK_SAGV REG_GENMASK(12, 0) 8221 8222 #define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700) 8223 #define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8) 8224 #define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4) 8225 #define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0) 8226 8227 #define MTL_MEM_SS_INFO_QGV_POINT_LOW(point) _MMIO(0x45710 + (point) * 2) 8228 #define MTL_TRCD_MASK REG_GENMASK(31, 24) 8229 #define MTL_TRP_MASK REG_GENMASK(23, 16) 8230 #define MTL_DCLK_MASK REG_GENMASK(15, 0) 8231 8232 #define MTL_MEM_SS_INFO_QGV_POINT_HIGH(point) _MMIO(0x45714 + (point) * 2) 8233 #define MTL_TRAS_MASK REG_GENMASK(16, 8) 8234 #define MTL_TRDPRE_MASK REG_GENMASK(7, 0) 8235 8236 #define MTL_MEDIA_GSI_BASE 0x380000 8237 8238 #endif /* _I915_REG_H_ */ 8239