1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 */ 23 24 #ifndef _I915_PVINFO_H_ 25 #define _I915_PVINFO_H_ 26 27 /* The MMIO offset of the shared info between guest and host emulator */ 28 #define VGT_PVINFO_PAGE 0x78000 29 #define VGT_PVINFO_SIZE 0x1000 30 31 /* 32 * The following structure pages are defined in GEN MMIO space 33 * for virtualization. (One page for now) 34 */ 35 #define VGT_MAGIC 0x4776544776544776ULL /* 'vGTvGTvG' */ 36 #define VGT_VERSION_MAJOR 1 37 #define VGT_VERSION_MINOR 0 38 39 /* 40 * notifications from guest to vgpu device model 41 */ 42 enum vgt_g2v_type { 43 VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE = 2, 44 VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY, 45 VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE, 46 VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY, 47 VGT_G2V_EXECLIST_CONTEXT_CREATE, 48 VGT_G2V_EXECLIST_CONTEXT_DESTROY, 49 VGT_G2V_MAX, 50 }; 51 52 /* 53 * VGT capabilities type 54 */ 55 #define VGT_CAPS_FULL_PPGTT BIT(2) 56 #define VGT_CAPS_HWSP_EMULATION BIT(3) 57 #define VGT_CAPS_HUGE_GTT BIT(4) 58 59 struct vgt_if { 60 u64 magic; /* VGT_MAGIC */ 61 u16 version_major; 62 u16 version_minor; 63 u32 vgt_id; /* ID of vGT instance */ 64 u32 vgt_caps; /* VGT capabilities */ 65 u32 rsv1[11]; /* pad to offset 0x40 */ 66 /* 67 * Data structure to describe the balooning info of resources. 68 * Each VM can only have one portion of continuous area for now. 69 * (May support scattered resource in future) 70 * (starting from offset 0x40) 71 */ 72 struct { 73 /* Aperture register balooning */ 74 struct { 75 u32 base; 76 u32 size; 77 } mappable_gmadr; /* aperture */ 78 /* GMADR register balooning */ 79 struct { 80 u32 base; 81 u32 size; 82 } nonmappable_gmadr; /* non aperture */ 83 /* allowed fence registers */ 84 u32 fence_num; 85 u32 rsv2[3]; 86 } avail_rs; /* available/assigned resource */ 87 u32 rsv3[0x200 - 24]; /* pad to half page */ 88 /* 89 * The bottom half page is for response from Gfx driver to hypervisor. 90 */ 91 u32 rsv4; 92 u32 display_ready; /* ready for display owner switch */ 93 94 u32 rsv5[4]; 95 96 u32 g2v_notify; 97 u32 rsv6[5]; 98 99 u32 cursor_x_hot; 100 u32 cursor_y_hot; 101 102 struct { 103 u32 lo; 104 u32 hi; 105 } pdp[4]; 106 107 u32 execlist_context_descriptor_lo; 108 u32 execlist_context_descriptor_hi; 109 110 u32 rsv7[0x200 - 24]; /* pad to one page */ 111 } __packed; 112 113 #define vgtif_reg(x) \ 114 _MMIO((VGT_PVINFO_PAGE + offsetof(struct vgt_if, x))) 115 116 /* vGPU display status to be used by the host side */ 117 #define VGT_DRV_DISPLAY_NOT_READY 0 118 #define VGT_DRV_DISPLAY_READY 1 /* ready for display switch */ 119 120 #endif /* _I915_PVINFO_H_ */ 121