1 /* 2 * Copyright © 2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 #ifndef __I915_PMU_H__ 25 #define __I915_PMU_H__ 26 27 enum { 28 __I915_SAMPLE_FREQ_ACT = 0, 29 __I915_SAMPLE_FREQ_REQ, 30 __I915_NUM_PMU_SAMPLERS 31 }; 32 33 /** 34 * How many different events we track in the global PMU mask. 35 * 36 * It is also used to know to needed number of event reference counters. 37 */ 38 #define I915_PMU_MASK_BITS \ 39 ((1 << I915_PMU_SAMPLE_BITS) + \ 40 (I915_PMU_LAST + 1 - __I915_PMU_OTHER(0))) 41 42 struct i915_pmu_sample { 43 u64 cur; 44 }; 45 46 struct i915_pmu { 47 /** 48 * @node: List node for CPU hotplug handling. 49 */ 50 struct hlist_node node; 51 /** 52 * @base: PMU base. 53 */ 54 struct pmu base; 55 /** 56 * @lock: Lock protecting enable mask and ref count handling. 57 */ 58 spinlock_t lock; 59 /** 60 * @timer: Timer for internal i915 PMU sampling. 61 */ 62 struct hrtimer timer; 63 /** 64 * @enable: Bitmask of all currently enabled events. 65 * 66 * Bits are derived from uAPI event numbers in a way that low 16 bits 67 * correspond to engine event _sample_ _type_ (I915_SAMPLE_QUEUED is 68 * bit 0), and higher bits correspond to other events (for instance 69 * I915_PMU_ACTUAL_FREQUENCY is bit 16 etc). 70 * 71 * In other words, low 16 bits are not per engine but per engine 72 * sampler type, while the upper bits are directly mapped to other 73 * event types. 74 */ 75 u64 enable; 76 /** 77 * @enable_count: Reference counts for the enabled events. 78 * 79 * Array indices are mapped in the same way as bits in the @enable field 80 * and they are used to control sampling on/off when multiple clients 81 * are using the PMU API. 82 */ 83 unsigned int enable_count[I915_PMU_MASK_BITS]; 84 /** 85 * @timer_enabled: Should the internal sampling timer be running. 86 */ 87 bool timer_enabled; 88 /** 89 * @sample: Current and previous (raw) counters for sampling events. 90 * 91 * These counters are updated from the i915 PMU sampling timer. 92 * 93 * Only global counters are held here, while the per-engine ones are in 94 * struct intel_engine_cs. 95 */ 96 struct i915_pmu_sample sample[__I915_NUM_PMU_SAMPLERS]; 97 }; 98 99 #ifdef CONFIG_PERF_EVENTS 100 void i915_pmu_register(struct drm_i915_private *i915); 101 void i915_pmu_unregister(struct drm_i915_private *i915); 102 void i915_pmu_gt_parked(struct drm_i915_private *i915); 103 void i915_pmu_gt_unparked(struct drm_i915_private *i915); 104 #else 105 static inline void i915_pmu_register(struct drm_i915_private *i915) {} 106 static inline void i915_pmu_unregister(struct drm_i915_private *i915) {} 107 static inline void i915_pmu_gt_parked(struct drm_i915_private *i915) {} 108 static inline void i915_pmu_gt_unparked(struct drm_i915_private *i915) {} 109 #endif 110 111 #endif 112