1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/console.h> 26 #include <linux/vgaarb.h> 27 #include <linux/vga_switcheroo.h> 28 29 #include "i915_drv.h" 30 #include "i915_selftest.h" 31 32 #define PLATFORM(x) .platform = (x), .platform_mask = BIT(x) 33 #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1) 34 35 #define GEN_DEFAULT_PIPEOFFSETS \ 36 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ 37 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \ 38 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ 39 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \ 40 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET } 41 42 #define GEN_CHV_PIPEOFFSETS \ 43 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ 44 CHV_PIPE_C_OFFSET }, \ 45 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ 46 CHV_TRANSCODER_C_OFFSET, }, \ 47 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \ 48 CHV_PALETTE_C_OFFSET } 49 50 #define CURSOR_OFFSETS \ 51 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET } 52 53 #define IVB_CURSOR_OFFSETS \ 54 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET } 55 56 #define BDW_COLORS \ 57 .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 } 58 #define CHV_COLORS \ 59 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 } 60 #define GLK_COLORS \ 61 .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 } 62 63 /* Keep in gen based order, and chronological order within a gen */ 64 65 #define GEN_DEFAULT_PAGE_SIZES \ 66 .page_sizes = I915_GTT_PAGE_SIZE_4K 67 68 #define GEN2_FEATURES \ 69 GEN(2), \ 70 .num_pipes = 1, \ 71 .has_overlay = 1, .overlay_needs_physical = 1, \ 72 .has_gmch_display = 1, \ 73 .hws_needs_physical = 1, \ 74 .unfenced_needs_alignment = 1, \ 75 .ring_mask = RENDER_RING, \ 76 .has_snoop = true, \ 77 GEN_DEFAULT_PIPEOFFSETS, \ 78 GEN_DEFAULT_PAGE_SIZES, \ 79 CURSOR_OFFSETS 80 81 static const struct intel_device_info intel_i830_info = { 82 GEN2_FEATURES, 83 PLATFORM(INTEL_I830), 84 .is_mobile = 1, .cursor_needs_physical = 1, 85 .num_pipes = 2, /* legal, last one wins */ 86 }; 87 88 static const struct intel_device_info intel_i845g_info = { 89 GEN2_FEATURES, 90 PLATFORM(INTEL_I845G), 91 }; 92 93 static const struct intel_device_info intel_i85x_info = { 94 GEN2_FEATURES, 95 PLATFORM(INTEL_I85X), 96 .is_mobile = 1, 97 .num_pipes = 2, /* legal, last one wins */ 98 .cursor_needs_physical = 1, 99 .has_fbc = 1, 100 }; 101 102 static const struct intel_device_info intel_i865g_info = { 103 GEN2_FEATURES, 104 PLATFORM(INTEL_I865G), 105 }; 106 107 #define GEN3_FEATURES \ 108 GEN(3), \ 109 .num_pipes = 2, \ 110 .has_gmch_display = 1, \ 111 .ring_mask = RENDER_RING, \ 112 .has_snoop = true, \ 113 GEN_DEFAULT_PIPEOFFSETS, \ 114 GEN_DEFAULT_PAGE_SIZES, \ 115 CURSOR_OFFSETS 116 117 static const struct intel_device_info intel_i915g_info = { 118 GEN3_FEATURES, 119 PLATFORM(INTEL_I915G), 120 .cursor_needs_physical = 1, 121 .has_overlay = 1, .overlay_needs_physical = 1, 122 .hws_needs_physical = 1, 123 .unfenced_needs_alignment = 1, 124 }; 125 126 static const struct intel_device_info intel_i915gm_info = { 127 GEN3_FEATURES, 128 PLATFORM(INTEL_I915GM), 129 .is_mobile = 1, 130 .cursor_needs_physical = 1, 131 .has_overlay = 1, .overlay_needs_physical = 1, 132 .supports_tv = 1, 133 .has_fbc = 1, 134 .hws_needs_physical = 1, 135 .unfenced_needs_alignment = 1, 136 }; 137 138 static const struct intel_device_info intel_i945g_info = { 139 GEN3_FEATURES, 140 PLATFORM(INTEL_I945G), 141 .has_hotplug = 1, .cursor_needs_physical = 1, 142 .has_overlay = 1, .overlay_needs_physical = 1, 143 .hws_needs_physical = 1, 144 .unfenced_needs_alignment = 1, 145 }; 146 147 static const struct intel_device_info intel_i945gm_info = { 148 GEN3_FEATURES, 149 PLATFORM(INTEL_I945GM), 150 .is_mobile = 1, 151 .has_hotplug = 1, .cursor_needs_physical = 1, 152 .has_overlay = 1, .overlay_needs_physical = 1, 153 .supports_tv = 1, 154 .has_fbc = 1, 155 .hws_needs_physical = 1, 156 .unfenced_needs_alignment = 1, 157 }; 158 159 static const struct intel_device_info intel_g33_info = { 160 GEN3_FEATURES, 161 PLATFORM(INTEL_G33), 162 .has_hotplug = 1, 163 .has_overlay = 1, 164 }; 165 166 static const struct intel_device_info intel_pineview_info = { 167 GEN3_FEATURES, 168 PLATFORM(INTEL_PINEVIEW), 169 .is_mobile = 1, 170 .has_hotplug = 1, 171 .has_overlay = 1, 172 }; 173 174 #define GEN4_FEATURES \ 175 GEN(4), \ 176 .num_pipes = 2, \ 177 .has_hotplug = 1, \ 178 .has_gmch_display = 1, \ 179 .ring_mask = RENDER_RING, \ 180 .has_snoop = true, \ 181 GEN_DEFAULT_PIPEOFFSETS, \ 182 GEN_DEFAULT_PAGE_SIZES, \ 183 CURSOR_OFFSETS 184 185 static const struct intel_device_info intel_i965g_info = { 186 GEN4_FEATURES, 187 PLATFORM(INTEL_I965G), 188 .has_overlay = 1, 189 .hws_needs_physical = 1, 190 .has_snoop = false, 191 }; 192 193 static const struct intel_device_info intel_i965gm_info = { 194 GEN4_FEATURES, 195 PLATFORM(INTEL_I965GM), 196 .is_mobile = 1, .has_fbc = 1, 197 .has_overlay = 1, 198 .supports_tv = 1, 199 .hws_needs_physical = 1, 200 .has_snoop = false, 201 }; 202 203 static const struct intel_device_info intel_g45_info = { 204 GEN4_FEATURES, 205 PLATFORM(INTEL_G45), 206 .ring_mask = RENDER_RING | BSD_RING, 207 }; 208 209 static const struct intel_device_info intel_gm45_info = { 210 GEN4_FEATURES, 211 PLATFORM(INTEL_GM45), 212 .is_mobile = 1, .has_fbc = 1, 213 .supports_tv = 1, 214 .ring_mask = RENDER_RING | BSD_RING, 215 }; 216 217 #define GEN5_FEATURES \ 218 GEN(5), \ 219 .num_pipes = 2, \ 220 .has_hotplug = 1, \ 221 .ring_mask = RENDER_RING | BSD_RING, \ 222 .has_snoop = true, \ 223 /* ilk does support rc6, but we do not implement [power] contexts */ \ 224 .has_rc6 = 0, \ 225 GEN_DEFAULT_PIPEOFFSETS, \ 226 GEN_DEFAULT_PAGE_SIZES, \ 227 CURSOR_OFFSETS 228 229 static const struct intel_device_info intel_ironlake_d_info = { 230 GEN5_FEATURES, 231 PLATFORM(INTEL_IRONLAKE), 232 }; 233 234 static const struct intel_device_info intel_ironlake_m_info = { 235 GEN5_FEATURES, 236 PLATFORM(INTEL_IRONLAKE), 237 .is_mobile = 1, .has_fbc = 1, 238 }; 239 240 #define GEN6_FEATURES \ 241 GEN(6), \ 242 .num_pipes = 2, \ 243 .has_hotplug = 1, \ 244 .has_fbc = 1, \ 245 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ 246 .has_llc = 1, \ 247 .has_rc6 = 1, \ 248 .has_rc6p = 1, \ 249 .has_aliasing_ppgtt = 1, \ 250 GEN_DEFAULT_PIPEOFFSETS, \ 251 GEN_DEFAULT_PAGE_SIZES, \ 252 CURSOR_OFFSETS 253 254 #define SNB_D_PLATFORM \ 255 GEN6_FEATURES, \ 256 PLATFORM(INTEL_SANDYBRIDGE) 257 258 static const struct intel_device_info intel_sandybridge_d_gt1_info = { 259 SNB_D_PLATFORM, 260 .gt = 1, 261 }; 262 263 static const struct intel_device_info intel_sandybridge_d_gt2_info = { 264 SNB_D_PLATFORM, 265 .gt = 2, 266 }; 267 268 #define SNB_M_PLATFORM \ 269 GEN6_FEATURES, \ 270 PLATFORM(INTEL_SANDYBRIDGE), \ 271 .is_mobile = 1 272 273 274 static const struct intel_device_info intel_sandybridge_m_gt1_info = { 275 SNB_M_PLATFORM, 276 .gt = 1, 277 }; 278 279 static const struct intel_device_info intel_sandybridge_m_gt2_info = { 280 SNB_M_PLATFORM, 281 .gt = 2, 282 }; 283 284 #define GEN7_FEATURES \ 285 GEN(7), \ 286 .num_pipes = 3, \ 287 .has_hotplug = 1, \ 288 .has_fbc = 1, \ 289 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ 290 .has_llc = 1, \ 291 .has_rc6 = 1, \ 292 .has_rc6p = 1, \ 293 .has_aliasing_ppgtt = 1, \ 294 .has_full_ppgtt = 1, \ 295 GEN_DEFAULT_PIPEOFFSETS, \ 296 GEN_DEFAULT_PAGE_SIZES, \ 297 IVB_CURSOR_OFFSETS 298 299 #define IVB_D_PLATFORM \ 300 GEN7_FEATURES, \ 301 PLATFORM(INTEL_IVYBRIDGE), \ 302 .has_l3_dpf = 1 303 304 static const struct intel_device_info intel_ivybridge_d_gt1_info = { 305 IVB_D_PLATFORM, 306 .gt = 1, 307 }; 308 309 static const struct intel_device_info intel_ivybridge_d_gt2_info = { 310 IVB_D_PLATFORM, 311 .gt = 2, 312 }; 313 314 #define IVB_M_PLATFORM \ 315 GEN7_FEATURES, \ 316 PLATFORM(INTEL_IVYBRIDGE), \ 317 .is_mobile = 1, \ 318 .has_l3_dpf = 1 319 320 static const struct intel_device_info intel_ivybridge_m_gt1_info = { 321 IVB_M_PLATFORM, 322 .gt = 1, 323 }; 324 325 static const struct intel_device_info intel_ivybridge_m_gt2_info = { 326 IVB_M_PLATFORM, 327 .gt = 2, 328 }; 329 330 static const struct intel_device_info intel_ivybridge_q_info = { 331 GEN7_FEATURES, 332 PLATFORM(INTEL_IVYBRIDGE), 333 .gt = 2, 334 .num_pipes = 0, /* legal, last one wins */ 335 .has_l3_dpf = 1, 336 }; 337 338 static const struct intel_device_info intel_valleyview_info = { 339 PLATFORM(INTEL_VALLEYVIEW), 340 GEN(7), 341 .is_lp = 1, 342 .num_pipes = 2, 343 .has_psr = 1, 344 .has_runtime_pm = 1, 345 .has_rc6 = 1, 346 .has_gmch_display = 1, 347 .has_hotplug = 1, 348 .has_aliasing_ppgtt = 1, 349 .has_full_ppgtt = 1, 350 .has_snoop = true, 351 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, 352 .display_mmio_offset = VLV_DISPLAY_BASE, 353 GEN_DEFAULT_PAGE_SIZES, 354 GEN_DEFAULT_PIPEOFFSETS, 355 CURSOR_OFFSETS 356 }; 357 358 #define G75_FEATURES \ 359 GEN7_FEATURES, \ 360 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \ 361 .has_ddi = 1, \ 362 .has_fpga_dbg = 1, \ 363 .has_psr = 1, \ 364 .has_resource_streamer = 1, \ 365 .has_dp_mst = 1, \ 366 .has_rc6p = 0 /* RC6p removed-by HSW */, \ 367 .has_runtime_pm = 1 368 369 #define HSW_PLATFORM \ 370 G75_FEATURES, \ 371 PLATFORM(INTEL_HASWELL), \ 372 .has_l3_dpf = 1 373 374 static const struct intel_device_info intel_haswell_gt1_info = { 375 HSW_PLATFORM, 376 .gt = 1, 377 }; 378 379 static const struct intel_device_info intel_haswell_gt2_info = { 380 HSW_PLATFORM, 381 .gt = 2, 382 }; 383 384 static const struct intel_device_info intel_haswell_gt3_info = { 385 HSW_PLATFORM, 386 .gt = 3, 387 }; 388 389 #define GEN8_FEATURES \ 390 G75_FEATURES, \ 391 GEN(8), \ 392 BDW_COLORS, \ 393 .page_sizes = I915_GTT_PAGE_SIZE_4K | \ 394 I915_GTT_PAGE_SIZE_2M, \ 395 .has_logical_ring_contexts = 1, \ 396 .has_full_48bit_ppgtt = 1, \ 397 .has_64bit_reloc = 1, \ 398 .has_reset_engine = 1 399 400 #define BDW_PLATFORM \ 401 GEN8_FEATURES, \ 402 PLATFORM(INTEL_BROADWELL) 403 404 static const struct intel_device_info intel_broadwell_gt1_info = { 405 BDW_PLATFORM, 406 .gt = 1, 407 }; 408 409 static const struct intel_device_info intel_broadwell_gt2_info = { 410 BDW_PLATFORM, 411 .gt = 2, 412 }; 413 414 static const struct intel_device_info intel_broadwell_rsvd_info = { 415 BDW_PLATFORM, 416 .gt = 3, 417 /* According to the device ID those devices are GT3, they were 418 * previously treated as not GT3, keep it like that. 419 */ 420 }; 421 422 static const struct intel_device_info intel_broadwell_gt3_info = { 423 BDW_PLATFORM, 424 .gt = 3, 425 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 426 }; 427 428 static const struct intel_device_info intel_cherryview_info = { 429 PLATFORM(INTEL_CHERRYVIEW), 430 GEN(8), 431 .num_pipes = 3, 432 .has_hotplug = 1, 433 .is_lp = 1, 434 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, 435 .has_64bit_reloc = 1, 436 .has_psr = 1, 437 .has_runtime_pm = 1, 438 .has_resource_streamer = 1, 439 .has_rc6 = 1, 440 .has_logical_ring_contexts = 1, 441 .has_gmch_display = 1, 442 .has_aliasing_ppgtt = 1, 443 .has_full_ppgtt = 1, 444 .has_reset_engine = 1, 445 .has_snoop = true, 446 .display_mmio_offset = VLV_DISPLAY_BASE, 447 GEN_DEFAULT_PAGE_SIZES, 448 GEN_CHV_PIPEOFFSETS, 449 CURSOR_OFFSETS, 450 CHV_COLORS, 451 }; 452 453 #define GEN9_DEFAULT_PAGE_SIZES \ 454 .page_sizes = I915_GTT_PAGE_SIZE_4K | \ 455 I915_GTT_PAGE_SIZE_64K | \ 456 I915_GTT_PAGE_SIZE_2M 457 458 #define GEN9_FEATURES \ 459 GEN8_FEATURES, \ 460 GEN(9), \ 461 GEN9_DEFAULT_PAGE_SIZES, \ 462 .has_logical_ring_preemption = 1, \ 463 .has_csr = 1, \ 464 .has_guc = 1, \ 465 .has_ipc = 1, \ 466 .ddb_size = 896 467 468 #define SKL_PLATFORM \ 469 GEN9_FEATURES, \ 470 PLATFORM(INTEL_SKYLAKE) 471 472 static const struct intel_device_info intel_skylake_gt1_info = { 473 SKL_PLATFORM, 474 .gt = 1, 475 }; 476 477 static const struct intel_device_info intel_skylake_gt2_info = { 478 SKL_PLATFORM, 479 .gt = 2, 480 }; 481 482 #define SKL_GT3_PLUS_PLATFORM \ 483 SKL_PLATFORM, \ 484 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING 485 486 487 static const struct intel_device_info intel_skylake_gt3_info = { 488 SKL_GT3_PLUS_PLATFORM, 489 .gt = 3, 490 }; 491 492 static const struct intel_device_info intel_skylake_gt4_info = { 493 SKL_GT3_PLUS_PLATFORM, 494 .gt = 4, 495 }; 496 497 #define GEN9_LP_FEATURES \ 498 GEN(9), \ 499 .is_lp = 1, \ 500 .has_hotplug = 1, \ 501 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \ 502 .num_pipes = 3, \ 503 .has_64bit_reloc = 1, \ 504 .has_ddi = 1, \ 505 .has_fpga_dbg = 1, \ 506 .has_fbc = 1, \ 507 .has_psr = 1, \ 508 .has_runtime_pm = 1, \ 509 .has_pooled_eu = 0, \ 510 .has_csr = 1, \ 511 .has_resource_streamer = 1, \ 512 .has_rc6 = 1, \ 513 .has_dp_mst = 1, \ 514 .has_logical_ring_contexts = 1, \ 515 .has_logical_ring_preemption = 1, \ 516 .has_guc = 1, \ 517 .has_aliasing_ppgtt = 1, \ 518 .has_full_ppgtt = 1, \ 519 .has_full_48bit_ppgtt = 1, \ 520 .has_reset_engine = 1, \ 521 .has_snoop = true, \ 522 .has_ipc = 1, \ 523 GEN9_DEFAULT_PAGE_SIZES, \ 524 GEN_DEFAULT_PIPEOFFSETS, \ 525 IVB_CURSOR_OFFSETS, \ 526 BDW_COLORS 527 528 static const struct intel_device_info intel_broxton_info = { 529 GEN9_LP_FEATURES, 530 PLATFORM(INTEL_BROXTON), 531 .ddb_size = 512, 532 }; 533 534 static const struct intel_device_info intel_geminilake_info = { 535 GEN9_LP_FEATURES, 536 PLATFORM(INTEL_GEMINILAKE), 537 .ddb_size = 1024, 538 GLK_COLORS, 539 }; 540 541 #define KBL_PLATFORM \ 542 GEN9_FEATURES, \ 543 PLATFORM(INTEL_KABYLAKE) 544 545 static const struct intel_device_info intel_kabylake_gt1_info = { 546 KBL_PLATFORM, 547 .gt = 1, 548 }; 549 550 static const struct intel_device_info intel_kabylake_gt2_info = { 551 KBL_PLATFORM, 552 .gt = 2, 553 }; 554 555 static const struct intel_device_info intel_kabylake_gt3_info = { 556 KBL_PLATFORM, 557 .gt = 3, 558 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 559 }; 560 561 #define CFL_PLATFORM \ 562 GEN9_FEATURES, \ 563 PLATFORM(INTEL_COFFEELAKE) 564 565 static const struct intel_device_info intel_coffeelake_gt1_info = { 566 CFL_PLATFORM, 567 .gt = 1, 568 }; 569 570 static const struct intel_device_info intel_coffeelake_gt2_info = { 571 CFL_PLATFORM, 572 .gt = 2, 573 }; 574 575 static const struct intel_device_info intel_coffeelake_gt3_info = { 576 CFL_PLATFORM, 577 .gt = 3, 578 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 579 }; 580 581 #define GEN10_FEATURES \ 582 GEN9_FEATURES, \ 583 GEN(10), \ 584 .ddb_size = 1024, \ 585 GLK_COLORS 586 587 static const struct intel_device_info intel_cannonlake_info = { 588 GEN10_FEATURES, 589 PLATFORM(INTEL_CANNONLAKE), 590 .gt = 2, 591 }; 592 593 #define GEN11_FEATURES \ 594 GEN10_FEATURES, \ 595 GEN(11), \ 596 .ddb_size = 2048, \ 597 .has_csr = 0, \ 598 .has_logical_ring_elsq = 1 599 600 static const struct intel_device_info intel_icelake_11_info = { 601 GEN11_FEATURES, 602 PLATFORM(INTEL_ICELAKE), 603 .is_alpha_support = 1, 604 .has_resource_streamer = 0, 605 }; 606 607 #undef GEN 608 #undef PLATFORM 609 610 /* 611 * Make sure any device matches here are from most specific to most 612 * general. For example, since the Quanta match is based on the subsystem 613 * and subvendor IDs, we need it to come before the more general IVB 614 * PCI ID matches, otherwise we'll use the wrong info struct above. 615 */ 616 static const struct pci_device_id pciidlist[] = { 617 INTEL_I830_IDS(&intel_i830_info), 618 INTEL_I845G_IDS(&intel_i845g_info), 619 INTEL_I85X_IDS(&intel_i85x_info), 620 INTEL_I865G_IDS(&intel_i865g_info), 621 INTEL_I915G_IDS(&intel_i915g_info), 622 INTEL_I915GM_IDS(&intel_i915gm_info), 623 INTEL_I945G_IDS(&intel_i945g_info), 624 INTEL_I945GM_IDS(&intel_i945gm_info), 625 INTEL_I965G_IDS(&intel_i965g_info), 626 INTEL_G33_IDS(&intel_g33_info), 627 INTEL_I965GM_IDS(&intel_i965gm_info), 628 INTEL_GM45_IDS(&intel_gm45_info), 629 INTEL_G45_IDS(&intel_g45_info), 630 INTEL_PINEVIEW_IDS(&intel_pineview_info), 631 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), 632 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), 633 INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info), 634 INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info), 635 INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info), 636 INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info), 637 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ 638 INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info), 639 INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info), 640 INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info), 641 INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info), 642 INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info), 643 INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info), 644 INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info), 645 INTEL_VLV_IDS(&intel_valleyview_info), 646 INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info), 647 INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info), 648 INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info), 649 INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info), 650 INTEL_CHV_IDS(&intel_cherryview_info), 651 INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info), 652 INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info), 653 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), 654 INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info), 655 INTEL_BXT_IDS(&intel_broxton_info), 656 INTEL_GLK_IDS(&intel_geminilake_info), 657 INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info), 658 INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info), 659 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info), 660 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info), 661 INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info), 662 INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info), 663 INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info), 664 INTEL_CFL_U_GT1_IDS(&intel_coffeelake_gt1_info), 665 INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info), 666 INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info), 667 INTEL_CNL_IDS(&intel_cannonlake_info), 668 INTEL_ICL_11_IDS(&intel_icelake_11_info), 669 {0, 0, 0} 670 }; 671 MODULE_DEVICE_TABLE(pci, pciidlist); 672 673 static void i915_pci_remove(struct pci_dev *pdev) 674 { 675 struct drm_device *dev = pci_get_drvdata(pdev); 676 677 i915_driver_unload(dev); 678 drm_dev_put(dev); 679 } 680 681 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 682 { 683 struct intel_device_info *intel_info = 684 (struct intel_device_info *) ent->driver_data; 685 int err; 686 687 if (IS_ALPHA_SUPPORT(intel_info) && !i915_modparams.alpha_support) { 688 DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n" 689 "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n" 690 "to enable support in this kernel version, or check for kernel updates.\n"); 691 return -ENODEV; 692 } 693 694 /* Only bind to function 0 of the device. Early generations 695 * used function 1 as a placeholder for multi-head. This causes 696 * us confusion instead, especially on the systems where both 697 * functions have the same PCI-ID! 698 */ 699 if (PCI_FUNC(pdev->devfn)) 700 return -ENODEV; 701 702 /* 703 * apple-gmux is needed on dual GPU MacBook Pro 704 * to probe the panel if we're the inactive GPU. 705 */ 706 if (vga_switcheroo_client_probe_defer(pdev)) 707 return -EPROBE_DEFER; 708 709 err = i915_driver_load(pdev, ent); 710 if (err) 711 return err; 712 713 err = i915_live_selftests(pdev); 714 if (err) { 715 i915_pci_remove(pdev); 716 return err > 0 ? -ENOTTY : err; 717 } 718 719 return 0; 720 } 721 722 static struct pci_driver i915_pci_driver = { 723 .name = DRIVER_NAME, 724 .id_table = pciidlist, 725 .probe = i915_pci_probe, 726 .remove = i915_pci_remove, 727 .driver.pm = &i915_pm_ops, 728 }; 729 730 static int __init i915_init(void) 731 { 732 bool use_kms = true; 733 int err; 734 735 err = i915_mock_selftests(); 736 if (err) 737 return err > 0 ? 0 : err; 738 739 /* 740 * Enable KMS by default, unless explicitly overriden by 741 * either the i915.modeset prarameter or by the 742 * vga_text_mode_force boot option. 743 */ 744 745 if (i915_modparams.modeset == 0) 746 use_kms = false; 747 748 if (vgacon_text_force() && i915_modparams.modeset == -1) 749 use_kms = false; 750 751 if (!use_kms) { 752 /* Silently fail loading to not upset userspace. */ 753 DRM_DEBUG_DRIVER("KMS disabled.\n"); 754 return 0; 755 } 756 757 return pci_register_driver(&i915_pci_driver); 758 } 759 760 static void __exit i915_exit(void) 761 { 762 if (!i915_pci_driver.driver.owner) 763 return; 764 765 pci_unregister_driver(&i915_pci_driver); 766 } 767 768 module_init(i915_init); 769 module_exit(i915_exit); 770 771 MODULE_AUTHOR("Tungsten Graphics, Inc."); 772 MODULE_AUTHOR("Intel Corporation"); 773 774 MODULE_DESCRIPTION(DRIVER_DESC); 775 MODULE_LICENSE("GPL and additional rights"); 776