1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/console.h> 26 #include <linux/vgaarb.h> 27 #include <linux/vga_switcheroo.h> 28 29 #include "i915_drv.h" 30 #include "i915_selftest.h" 31 32 #define GEN_DEFAULT_PIPEOFFSETS \ 33 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ 34 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \ 35 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ 36 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \ 37 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET } 38 39 #define GEN_CHV_PIPEOFFSETS \ 40 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ 41 CHV_PIPE_C_OFFSET }, \ 42 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ 43 CHV_TRANSCODER_C_OFFSET, }, \ 44 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \ 45 CHV_PALETTE_C_OFFSET } 46 47 #define CURSOR_OFFSETS \ 48 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET } 49 50 #define IVB_CURSOR_OFFSETS \ 51 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET } 52 53 #define BDW_COLORS \ 54 .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 } 55 #define CHV_COLORS \ 56 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 } 57 58 /* Keep in gen based order, and chronological order within a gen */ 59 #define GEN2_FEATURES \ 60 .gen = 2, .num_pipes = 1, \ 61 .has_overlay = 1, .overlay_needs_physical = 1, \ 62 .has_gmch_display = 1, \ 63 .hws_needs_physical = 1, \ 64 .ring_mask = RENDER_RING, \ 65 GEN_DEFAULT_PIPEOFFSETS, \ 66 CURSOR_OFFSETS 67 68 static const struct intel_device_info intel_i830_info = { 69 GEN2_FEATURES, 70 .platform = INTEL_I830, 71 .is_mobile = 1, .cursor_needs_physical = 1, 72 .num_pipes = 2, /* legal, last one wins */ 73 }; 74 75 static const struct intel_device_info intel_i845g_info = { 76 GEN2_FEATURES, 77 .platform = INTEL_I845G, 78 }; 79 80 static const struct intel_device_info intel_i85x_info = { 81 GEN2_FEATURES, 82 .platform = INTEL_I85X, .is_mobile = 1, 83 .num_pipes = 2, /* legal, last one wins */ 84 .cursor_needs_physical = 1, 85 .has_fbc = 1, 86 }; 87 88 static const struct intel_device_info intel_i865g_info = { 89 GEN2_FEATURES, 90 .platform = INTEL_I865G, 91 }; 92 93 #define GEN3_FEATURES \ 94 .gen = 3, .num_pipes = 2, \ 95 .has_gmch_display = 1, \ 96 .ring_mask = RENDER_RING, \ 97 GEN_DEFAULT_PIPEOFFSETS, \ 98 CURSOR_OFFSETS 99 100 static const struct intel_device_info intel_i915g_info = { 101 GEN3_FEATURES, 102 .platform = INTEL_I915G, .cursor_needs_physical = 1, 103 .has_overlay = 1, .overlay_needs_physical = 1, 104 .hws_needs_physical = 1, 105 }; 106 107 static const struct intel_device_info intel_i915gm_info = { 108 GEN3_FEATURES, 109 .platform = INTEL_I915GM, 110 .is_mobile = 1, 111 .cursor_needs_physical = 1, 112 .has_overlay = 1, .overlay_needs_physical = 1, 113 .supports_tv = 1, 114 .has_fbc = 1, 115 .hws_needs_physical = 1, 116 }; 117 118 static const struct intel_device_info intel_i945g_info = { 119 GEN3_FEATURES, 120 .platform = INTEL_I945G, 121 .has_hotplug = 1, .cursor_needs_physical = 1, 122 .has_overlay = 1, .overlay_needs_physical = 1, 123 .hws_needs_physical = 1, 124 }; 125 126 static const struct intel_device_info intel_i945gm_info = { 127 GEN3_FEATURES, 128 .platform = INTEL_I945GM, .is_mobile = 1, 129 .has_hotplug = 1, .cursor_needs_physical = 1, 130 .has_overlay = 1, .overlay_needs_physical = 1, 131 .supports_tv = 1, 132 .has_fbc = 1, 133 .hws_needs_physical = 1, 134 }; 135 136 static const struct intel_device_info intel_g33_info = { 137 GEN3_FEATURES, 138 .platform = INTEL_G33, 139 .has_hotplug = 1, 140 .has_overlay = 1, 141 }; 142 143 static const struct intel_device_info intel_pineview_info = { 144 GEN3_FEATURES, 145 .platform = INTEL_PINEVIEW, .is_mobile = 1, 146 .has_hotplug = 1, 147 .has_overlay = 1, 148 }; 149 150 #define GEN4_FEATURES \ 151 .gen = 4, .num_pipes = 2, \ 152 .has_hotplug = 1, \ 153 .has_gmch_display = 1, \ 154 .ring_mask = RENDER_RING, \ 155 GEN_DEFAULT_PIPEOFFSETS, \ 156 CURSOR_OFFSETS 157 158 static const struct intel_device_info intel_i965g_info = { 159 GEN4_FEATURES, 160 .platform = INTEL_I965G, 161 .has_overlay = 1, 162 .hws_needs_physical = 1, 163 }; 164 165 static const struct intel_device_info intel_i965gm_info = { 166 GEN4_FEATURES, 167 .platform = INTEL_I965GM, 168 .is_mobile = 1, .has_fbc = 1, 169 .has_overlay = 1, 170 .supports_tv = 1, 171 .hws_needs_physical = 1, 172 }; 173 174 static const struct intel_device_info intel_g45_info = { 175 GEN4_FEATURES, 176 .platform = INTEL_G45, 177 .has_pipe_cxsr = 1, 178 .ring_mask = RENDER_RING | BSD_RING, 179 }; 180 181 static const struct intel_device_info intel_gm45_info = { 182 GEN4_FEATURES, 183 .platform = INTEL_GM45, 184 .is_mobile = 1, .has_fbc = 1, 185 .has_pipe_cxsr = 1, 186 .supports_tv = 1, 187 .ring_mask = RENDER_RING | BSD_RING, 188 }; 189 190 #define GEN5_FEATURES \ 191 .gen = 5, .num_pipes = 2, \ 192 .has_hotplug = 1, \ 193 .has_gmbus_irq = 1, \ 194 .ring_mask = RENDER_RING | BSD_RING, \ 195 GEN_DEFAULT_PIPEOFFSETS, \ 196 CURSOR_OFFSETS 197 198 static const struct intel_device_info intel_ironlake_d_info = { 199 GEN5_FEATURES, 200 .platform = INTEL_IRONLAKE, 201 }; 202 203 static const struct intel_device_info intel_ironlake_m_info = { 204 GEN5_FEATURES, 205 .platform = INTEL_IRONLAKE, 206 .is_mobile = 1, 207 }; 208 209 #define GEN6_FEATURES \ 210 .gen = 6, .num_pipes = 2, \ 211 .has_hotplug = 1, \ 212 .has_fbc = 1, \ 213 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ 214 .has_llc = 1, \ 215 .has_rc6 = 1, \ 216 .has_rc6p = 1, \ 217 .has_gmbus_irq = 1, \ 218 .has_hw_contexts = 1, \ 219 .has_aliasing_ppgtt = 1, \ 220 GEN_DEFAULT_PIPEOFFSETS, \ 221 CURSOR_OFFSETS 222 223 static const struct intel_device_info intel_sandybridge_d_info = { 224 GEN6_FEATURES, 225 .platform = INTEL_SANDYBRIDGE, 226 }; 227 228 static const struct intel_device_info intel_sandybridge_m_info = { 229 GEN6_FEATURES, 230 .platform = INTEL_SANDYBRIDGE, 231 .is_mobile = 1, 232 }; 233 234 #define GEN7_FEATURES \ 235 .gen = 7, .num_pipes = 3, \ 236 .has_hotplug = 1, \ 237 .has_fbc = 1, \ 238 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ 239 .has_llc = 1, \ 240 .has_rc6 = 1, \ 241 .has_rc6p = 1, \ 242 .has_gmbus_irq = 1, \ 243 .has_hw_contexts = 1, \ 244 .has_aliasing_ppgtt = 1, \ 245 .has_full_ppgtt = 1, \ 246 GEN_DEFAULT_PIPEOFFSETS, \ 247 IVB_CURSOR_OFFSETS 248 249 static const struct intel_device_info intel_ivybridge_d_info = { 250 GEN7_FEATURES, 251 .platform = INTEL_IVYBRIDGE, 252 .has_l3_dpf = 1, 253 }; 254 255 static const struct intel_device_info intel_ivybridge_m_info = { 256 GEN7_FEATURES, 257 .platform = INTEL_IVYBRIDGE, 258 .is_mobile = 1, 259 .has_l3_dpf = 1, 260 }; 261 262 static const struct intel_device_info intel_ivybridge_q_info = { 263 GEN7_FEATURES, 264 .platform = INTEL_IVYBRIDGE, 265 .num_pipes = 0, /* legal, last one wins */ 266 .has_l3_dpf = 1, 267 }; 268 269 static const struct intel_device_info intel_valleyview_info = { 270 .platform = INTEL_VALLEYVIEW, 271 .gen = 7, 272 .is_lp = 1, 273 .num_pipes = 2, 274 .has_psr = 1, 275 .has_runtime_pm = 1, 276 .has_rc6 = 1, 277 .has_gmbus_irq = 1, 278 .has_hw_contexts = 1, 279 .has_gmch_display = 1, 280 .has_hotplug = 1, 281 .has_aliasing_ppgtt = 1, 282 .has_full_ppgtt = 1, 283 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, 284 .display_mmio_offset = VLV_DISPLAY_BASE, 285 GEN_DEFAULT_PIPEOFFSETS, 286 CURSOR_OFFSETS 287 }; 288 289 #define HSW_FEATURES \ 290 GEN7_FEATURES, \ 291 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \ 292 .has_ddi = 1, \ 293 .has_fpga_dbg = 1, \ 294 .has_psr = 1, \ 295 .has_resource_streamer = 1, \ 296 .has_dp_mst = 1, \ 297 .has_rc6p = 0 /* RC6p removed-by HSW */, \ 298 .has_runtime_pm = 1 299 300 static const struct intel_device_info intel_haswell_info = { 301 HSW_FEATURES, 302 .platform = INTEL_HASWELL, 303 .has_l3_dpf = 1, 304 }; 305 306 #define BDW_FEATURES \ 307 HSW_FEATURES, \ 308 BDW_COLORS, \ 309 .has_logical_ring_contexts = 1, \ 310 .has_full_48bit_ppgtt = 1, \ 311 .has_64bit_reloc = 1 312 313 static const struct intel_device_info intel_broadwell_info = { 314 BDW_FEATURES, 315 .gen = 8, 316 .platform = INTEL_BROADWELL, 317 }; 318 319 static const struct intel_device_info intel_broadwell_gt3_info = { 320 BDW_FEATURES, 321 .gen = 8, 322 .platform = INTEL_BROADWELL, 323 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 324 }; 325 326 static const struct intel_device_info intel_cherryview_info = { 327 .gen = 8, .num_pipes = 3, 328 .has_hotplug = 1, 329 .is_lp = 1, 330 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, 331 .platform = INTEL_CHERRYVIEW, 332 .has_64bit_reloc = 1, 333 .has_psr = 1, 334 .has_runtime_pm = 1, 335 .has_resource_streamer = 1, 336 .has_rc6 = 1, 337 .has_gmbus_irq = 1, 338 .has_hw_contexts = 1, 339 .has_logical_ring_contexts = 1, 340 .has_gmch_display = 1, 341 .has_aliasing_ppgtt = 1, 342 .has_full_ppgtt = 1, 343 .display_mmio_offset = VLV_DISPLAY_BASE, 344 GEN_CHV_PIPEOFFSETS, 345 CURSOR_OFFSETS, 346 CHV_COLORS, 347 }; 348 349 static const struct intel_device_info intel_skylake_info = { 350 BDW_FEATURES, 351 .platform = INTEL_SKYLAKE, 352 .gen = 9, 353 .has_csr = 1, 354 .has_guc = 1, 355 .ddb_size = 896, 356 }; 357 358 static const struct intel_device_info intel_skylake_gt3_info = { 359 BDW_FEATURES, 360 .platform = INTEL_SKYLAKE, 361 .gen = 9, 362 .has_csr = 1, 363 .has_guc = 1, 364 .ddb_size = 896, 365 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 366 }; 367 368 #define GEN9_LP_FEATURES \ 369 .gen = 9, \ 370 .is_lp = 1, \ 371 .has_hotplug = 1, \ 372 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \ 373 .num_pipes = 3, \ 374 .has_64bit_reloc = 1, \ 375 .has_ddi = 1, \ 376 .has_fpga_dbg = 1, \ 377 .has_fbc = 1, \ 378 .has_runtime_pm = 1, \ 379 .has_pooled_eu = 0, \ 380 .has_csr = 1, \ 381 .has_resource_streamer = 1, \ 382 .has_rc6 = 1, \ 383 .has_dp_mst = 1, \ 384 .has_gmbus_irq = 1, \ 385 .has_hw_contexts = 1, \ 386 .has_logical_ring_contexts = 1, \ 387 .has_guc = 1, \ 388 .has_decoupled_mmio = 1, \ 389 .has_aliasing_ppgtt = 1, \ 390 .has_full_ppgtt = 1, \ 391 .has_full_48bit_ppgtt = 1, \ 392 GEN_DEFAULT_PIPEOFFSETS, \ 393 IVB_CURSOR_OFFSETS, \ 394 BDW_COLORS 395 396 static const struct intel_device_info intel_broxton_info = { 397 GEN9_LP_FEATURES, 398 .platform = INTEL_BROXTON, 399 .ddb_size = 512, 400 }; 401 402 static const struct intel_device_info intel_geminilake_info = { 403 GEN9_LP_FEATURES, 404 .platform = INTEL_GEMINILAKE, 405 .is_alpha_support = 1, 406 .ddb_size = 1024, 407 .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 } 408 }; 409 410 static const struct intel_device_info intel_kabylake_info = { 411 BDW_FEATURES, 412 .platform = INTEL_KABYLAKE, 413 .gen = 9, 414 .has_csr = 1, 415 .has_guc = 1, 416 .ddb_size = 896, 417 }; 418 419 static const struct intel_device_info intel_kabylake_gt3_info = { 420 BDW_FEATURES, 421 .platform = INTEL_KABYLAKE, 422 .gen = 9, 423 .has_csr = 1, 424 .has_guc = 1, 425 .ddb_size = 896, 426 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 427 }; 428 429 /* 430 * Make sure any device matches here are from most specific to most 431 * general. For example, since the Quanta match is based on the subsystem 432 * and subvendor IDs, we need it to come before the more general IVB 433 * PCI ID matches, otherwise we'll use the wrong info struct above. 434 */ 435 static const struct pci_device_id pciidlist[] = { 436 INTEL_I830_IDS(&intel_i830_info), 437 INTEL_I845G_IDS(&intel_i845g_info), 438 INTEL_I85X_IDS(&intel_i85x_info), 439 INTEL_I865G_IDS(&intel_i865g_info), 440 INTEL_I915G_IDS(&intel_i915g_info), 441 INTEL_I915GM_IDS(&intel_i915gm_info), 442 INTEL_I945G_IDS(&intel_i945g_info), 443 INTEL_I945GM_IDS(&intel_i945gm_info), 444 INTEL_I965G_IDS(&intel_i965g_info), 445 INTEL_G33_IDS(&intel_g33_info), 446 INTEL_I965GM_IDS(&intel_i965gm_info), 447 INTEL_GM45_IDS(&intel_gm45_info), 448 INTEL_G45_IDS(&intel_g45_info), 449 INTEL_PINEVIEW_IDS(&intel_pineview_info), 450 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), 451 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), 452 INTEL_SNB_D_IDS(&intel_sandybridge_d_info), 453 INTEL_SNB_M_IDS(&intel_sandybridge_m_info), 454 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ 455 INTEL_IVB_M_IDS(&intel_ivybridge_m_info), 456 INTEL_IVB_D_IDS(&intel_ivybridge_d_info), 457 INTEL_HSW_IDS(&intel_haswell_info), 458 INTEL_VLV_IDS(&intel_valleyview_info), 459 INTEL_BDW_GT12_IDS(&intel_broadwell_info), 460 INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info), 461 INTEL_BDW_RSVD_IDS(&intel_broadwell_info), 462 INTEL_CHV_IDS(&intel_cherryview_info), 463 INTEL_SKL_GT1_IDS(&intel_skylake_info), 464 INTEL_SKL_GT2_IDS(&intel_skylake_info), 465 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), 466 INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info), 467 INTEL_BXT_IDS(&intel_broxton_info), 468 INTEL_GLK_IDS(&intel_geminilake_info), 469 INTEL_KBL_GT1_IDS(&intel_kabylake_info), 470 INTEL_KBL_GT2_IDS(&intel_kabylake_info), 471 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info), 472 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info), 473 {0, 0, 0} 474 }; 475 MODULE_DEVICE_TABLE(pci, pciidlist); 476 477 static void i915_pci_remove(struct pci_dev *pdev) 478 { 479 struct drm_device *dev = pci_get_drvdata(pdev); 480 481 i915_driver_unload(dev); 482 drm_dev_unref(dev); 483 } 484 485 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 486 { 487 struct intel_device_info *intel_info = 488 (struct intel_device_info *) ent->driver_data; 489 int err; 490 491 if (IS_ALPHA_SUPPORT(intel_info) && !i915.alpha_support) { 492 DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n" 493 "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n" 494 "to enable support in this kernel version, or check for kernel updates.\n"); 495 return -ENODEV; 496 } 497 498 /* Only bind to function 0 of the device. Early generations 499 * used function 1 as a placeholder for multi-head. This causes 500 * us confusion instead, especially on the systems where both 501 * functions have the same PCI-ID! 502 */ 503 if (PCI_FUNC(pdev->devfn)) 504 return -ENODEV; 505 506 /* 507 * apple-gmux is needed on dual GPU MacBook Pro 508 * to probe the panel if we're the inactive GPU. 509 */ 510 if (vga_switcheroo_client_probe_defer(pdev)) 511 return -EPROBE_DEFER; 512 513 err = i915_driver_load(pdev, ent); 514 if (err) 515 return err; 516 517 err = i915_live_selftests(pdev); 518 if (err) { 519 i915_pci_remove(pdev); 520 return err > 0 ? -ENOTTY : err; 521 } 522 523 return 0; 524 } 525 526 static struct pci_driver i915_pci_driver = { 527 .name = DRIVER_NAME, 528 .id_table = pciidlist, 529 .probe = i915_pci_probe, 530 .remove = i915_pci_remove, 531 .driver.pm = &i915_pm_ops, 532 }; 533 534 static int __init i915_init(void) 535 { 536 bool use_kms = true; 537 int err; 538 539 err = i915_mock_selftests(); 540 if (err) 541 return err > 0 ? 0 : err; 542 543 /* 544 * Enable KMS by default, unless explicitly overriden by 545 * either the i915.modeset prarameter or by the 546 * vga_text_mode_force boot option. 547 */ 548 549 if (i915.modeset == 0) 550 use_kms = false; 551 552 if (vgacon_text_force() && i915.modeset == -1) 553 use_kms = false; 554 555 if (!use_kms) { 556 /* Silently fail loading to not upset userspace. */ 557 DRM_DEBUG_DRIVER("KMS disabled.\n"); 558 return 0; 559 } 560 561 return pci_register_driver(&i915_pci_driver); 562 } 563 564 static void __exit i915_exit(void) 565 { 566 if (!i915_pci_driver.driver.owner) 567 return; 568 569 pci_unregister_driver(&i915_pci_driver); 570 } 571 572 module_init(i915_init); 573 module_exit(i915_exit); 574 575 MODULE_AUTHOR("Tungsten Graphics, Inc."); 576 MODULE_AUTHOR("Intel Corporation"); 577 578 MODULE_DESCRIPTION(DRIVER_DESC); 579 MODULE_LICENSE("GPL and additional rights"); 580