xref: /openbmc/linux/drivers/gpu/drm/i915/i915_pci.c (revision ddc141e5)
1 /*
2  * Copyright © 2016 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  */
24 
25 #include <linux/console.h>
26 #include <linux/vgaarb.h>
27 #include <linux/vga_switcheroo.h>
28 
29 #include "i915_drv.h"
30 #include "i915_selftest.h"
31 
32 #define GEN_DEFAULT_PIPEOFFSETS \
33 	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
34 			  PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
35 	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
36 			   TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
37 	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
38 
39 #define GEN_CHV_PIPEOFFSETS \
40 	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
41 			  CHV_PIPE_C_OFFSET }, \
42 	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
43 			   CHV_TRANSCODER_C_OFFSET, }, \
44 	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
45 			     CHV_PALETTE_C_OFFSET }
46 
47 #define CURSOR_OFFSETS \
48 	.cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
49 
50 #define IVB_CURSOR_OFFSETS \
51 	.cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
52 
53 #define BDW_COLORS \
54 	.color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
55 #define CHV_COLORS \
56 	.color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
57 #define GLK_COLORS \
58 	.color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
59 
60 /* Keep in gen based order, and chronological order within a gen */
61 
62 #define GEN_DEFAULT_PAGE_SIZES \
63 	.page_sizes = I915_GTT_PAGE_SIZE_4K
64 
65 #define GEN2_FEATURES \
66 	.gen = 2, .num_pipes = 1, \
67 	.has_overlay = 1, .overlay_needs_physical = 1, \
68 	.has_gmch_display = 1, \
69 	.hws_needs_physical = 1, \
70 	.unfenced_needs_alignment = 1, \
71 	.ring_mask = RENDER_RING, \
72 	.has_snoop = true, \
73 	GEN_DEFAULT_PIPEOFFSETS, \
74 	GEN_DEFAULT_PAGE_SIZES, \
75 	CURSOR_OFFSETS
76 
77 static const struct intel_device_info intel_i830_info = {
78 	GEN2_FEATURES,
79 	.platform = INTEL_I830,
80 	.is_mobile = 1, .cursor_needs_physical = 1,
81 	.num_pipes = 2, /* legal, last one wins */
82 };
83 
84 static const struct intel_device_info intel_i845g_info = {
85 	GEN2_FEATURES,
86 	.platform = INTEL_I845G,
87 };
88 
89 static const struct intel_device_info intel_i85x_info = {
90 	GEN2_FEATURES,
91 	.platform = INTEL_I85X, .is_mobile = 1,
92 	.num_pipes = 2, /* legal, last one wins */
93 	.cursor_needs_physical = 1,
94 	.has_fbc = 1,
95 };
96 
97 static const struct intel_device_info intel_i865g_info = {
98 	GEN2_FEATURES,
99 	.platform = INTEL_I865G,
100 };
101 
102 #define GEN3_FEATURES \
103 	.gen = 3, .num_pipes = 2, \
104 	.has_gmch_display = 1, \
105 	.ring_mask = RENDER_RING, \
106 	.has_snoop = true, \
107 	GEN_DEFAULT_PIPEOFFSETS, \
108 	GEN_DEFAULT_PAGE_SIZES, \
109 	CURSOR_OFFSETS
110 
111 static const struct intel_device_info intel_i915g_info = {
112 	GEN3_FEATURES,
113 	.platform = INTEL_I915G, .cursor_needs_physical = 1,
114 	.has_overlay = 1, .overlay_needs_physical = 1,
115 	.hws_needs_physical = 1,
116 	.unfenced_needs_alignment = 1,
117 };
118 
119 static const struct intel_device_info intel_i915gm_info = {
120 	GEN3_FEATURES,
121 	.platform = INTEL_I915GM,
122 	.is_mobile = 1,
123 	.cursor_needs_physical = 1,
124 	.has_overlay = 1, .overlay_needs_physical = 1,
125 	.supports_tv = 1,
126 	.has_fbc = 1,
127 	.hws_needs_physical = 1,
128 	.unfenced_needs_alignment = 1,
129 };
130 
131 static const struct intel_device_info intel_i945g_info = {
132 	GEN3_FEATURES,
133 	.platform = INTEL_I945G,
134 	.has_hotplug = 1, .cursor_needs_physical = 1,
135 	.has_overlay = 1, .overlay_needs_physical = 1,
136 	.hws_needs_physical = 1,
137 	.unfenced_needs_alignment = 1,
138 };
139 
140 static const struct intel_device_info intel_i945gm_info = {
141 	GEN3_FEATURES,
142 	.platform = INTEL_I945GM, .is_mobile = 1,
143 	.has_hotplug = 1, .cursor_needs_physical = 1,
144 	.has_overlay = 1, .overlay_needs_physical = 1,
145 	.supports_tv = 1,
146 	.has_fbc = 1,
147 	.hws_needs_physical = 1,
148 	.unfenced_needs_alignment = 1,
149 };
150 
151 static const struct intel_device_info intel_g33_info = {
152 	GEN3_FEATURES,
153 	.platform = INTEL_G33,
154 	.has_hotplug = 1,
155 	.has_overlay = 1,
156 };
157 
158 static const struct intel_device_info intel_pineview_info = {
159 	GEN3_FEATURES,
160 	.platform = INTEL_PINEVIEW, .is_mobile = 1,
161 	.has_hotplug = 1,
162 	.has_overlay = 1,
163 };
164 
165 #define GEN4_FEATURES \
166 	.gen = 4, .num_pipes = 2, \
167 	.has_hotplug = 1, \
168 	.has_gmch_display = 1, \
169 	.ring_mask = RENDER_RING, \
170 	.has_snoop = true, \
171 	GEN_DEFAULT_PIPEOFFSETS, \
172 	GEN_DEFAULT_PAGE_SIZES, \
173 	CURSOR_OFFSETS
174 
175 static const struct intel_device_info intel_i965g_info = {
176 	GEN4_FEATURES,
177 	.platform = INTEL_I965G,
178 	.has_overlay = 1,
179 	.hws_needs_physical = 1,
180 	.has_snoop = false,
181 };
182 
183 static const struct intel_device_info intel_i965gm_info = {
184 	GEN4_FEATURES,
185 	.platform = INTEL_I965GM,
186 	.is_mobile = 1, .has_fbc = 1,
187 	.has_overlay = 1,
188 	.supports_tv = 1,
189 	.hws_needs_physical = 1,
190 	.has_snoop = false,
191 };
192 
193 static const struct intel_device_info intel_g45_info = {
194 	GEN4_FEATURES,
195 	.platform = INTEL_G45,
196 	.ring_mask = RENDER_RING | BSD_RING,
197 };
198 
199 static const struct intel_device_info intel_gm45_info = {
200 	GEN4_FEATURES,
201 	.platform = INTEL_GM45,
202 	.is_mobile = 1, .has_fbc = 1,
203 	.supports_tv = 1,
204 	.ring_mask = RENDER_RING | BSD_RING,
205 };
206 
207 #define GEN5_FEATURES \
208 	.gen = 5, .num_pipes = 2, \
209 	.has_hotplug = 1, \
210 	.ring_mask = RENDER_RING | BSD_RING, \
211 	.has_snoop = true, \
212 	/* ilk does support rc6, but we do not implement [power] contexts */ \
213 	.has_rc6 = 0, \
214 	GEN_DEFAULT_PIPEOFFSETS, \
215 	GEN_DEFAULT_PAGE_SIZES, \
216 	CURSOR_OFFSETS
217 
218 static const struct intel_device_info intel_ironlake_d_info = {
219 	GEN5_FEATURES,
220 	.platform = INTEL_IRONLAKE,
221 };
222 
223 static const struct intel_device_info intel_ironlake_m_info = {
224 	GEN5_FEATURES,
225 	.platform = INTEL_IRONLAKE,
226 	.is_mobile = 1, .has_fbc = 1,
227 };
228 
229 #define GEN6_FEATURES \
230 	.gen = 6, .num_pipes = 2, \
231 	.has_hotplug = 1, \
232 	.has_fbc = 1, \
233 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
234 	.has_llc = 1, \
235 	.has_rc6 = 1, \
236 	.has_rc6p = 1, \
237 	.has_aliasing_ppgtt = 1, \
238 	GEN_DEFAULT_PIPEOFFSETS, \
239 	GEN_DEFAULT_PAGE_SIZES, \
240 	CURSOR_OFFSETS
241 
242 #define SNB_D_PLATFORM \
243 	GEN6_FEATURES, \
244 	.platform = INTEL_SANDYBRIDGE
245 
246 static const struct intel_device_info intel_sandybridge_d_gt1_info = {
247 	SNB_D_PLATFORM,
248 	.gt = 1,
249 };
250 
251 static const struct intel_device_info intel_sandybridge_d_gt2_info = {
252 	SNB_D_PLATFORM,
253 	.gt = 2,
254 };
255 
256 #define SNB_M_PLATFORM \
257 	GEN6_FEATURES, \
258 	.platform = INTEL_SANDYBRIDGE, \
259 	.is_mobile = 1
260 
261 
262 static const struct intel_device_info intel_sandybridge_m_gt1_info = {
263 	SNB_M_PLATFORM,
264 	.gt = 1,
265 };
266 
267 static const struct intel_device_info intel_sandybridge_m_gt2_info = {
268 	SNB_M_PLATFORM,
269 	.gt = 2,
270 };
271 
272 #define GEN7_FEATURES  \
273 	.gen = 7, .num_pipes = 3, \
274 	.has_hotplug = 1, \
275 	.has_fbc = 1, \
276 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
277 	.has_llc = 1, \
278 	.has_rc6 = 1, \
279 	.has_rc6p = 1, \
280 	.has_aliasing_ppgtt = 1, \
281 	.has_full_ppgtt = 1, \
282 	GEN_DEFAULT_PIPEOFFSETS, \
283 	GEN_DEFAULT_PAGE_SIZES, \
284 	IVB_CURSOR_OFFSETS
285 
286 #define IVB_D_PLATFORM \
287 	GEN7_FEATURES, \
288 	.platform = INTEL_IVYBRIDGE, \
289 	.has_l3_dpf = 1
290 
291 static const struct intel_device_info intel_ivybridge_d_gt1_info = {
292 	IVB_D_PLATFORM,
293 	.gt = 1,
294 };
295 
296 static const struct intel_device_info intel_ivybridge_d_gt2_info = {
297 	IVB_D_PLATFORM,
298 	.gt = 2,
299 };
300 
301 #define IVB_M_PLATFORM \
302 	GEN7_FEATURES, \
303 	.platform = INTEL_IVYBRIDGE, \
304 	.is_mobile = 1, \
305 	.has_l3_dpf = 1
306 
307 static const struct intel_device_info intel_ivybridge_m_gt1_info = {
308 	IVB_M_PLATFORM,
309 	.gt = 1,
310 };
311 
312 static const struct intel_device_info intel_ivybridge_m_gt2_info = {
313 	IVB_M_PLATFORM,
314 	.gt = 2,
315 };
316 
317 static const struct intel_device_info intel_ivybridge_q_info = {
318 	GEN7_FEATURES,
319 	.platform = INTEL_IVYBRIDGE,
320 	.gt = 2,
321 	.num_pipes = 0, /* legal, last one wins */
322 	.has_l3_dpf = 1,
323 };
324 
325 static const struct intel_device_info intel_valleyview_info = {
326 	.platform = INTEL_VALLEYVIEW,
327 	.gen = 7,
328 	.is_lp = 1,
329 	.num_pipes = 2,
330 	.has_psr = 1,
331 	.has_runtime_pm = 1,
332 	.has_rc6 = 1,
333 	.has_gmch_display = 1,
334 	.has_hotplug = 1,
335 	.has_aliasing_ppgtt = 1,
336 	.has_full_ppgtt = 1,
337 	.has_snoop = true,
338 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
339 	.display_mmio_offset = VLV_DISPLAY_BASE,
340 	GEN_DEFAULT_PAGE_SIZES,
341 	GEN_DEFAULT_PIPEOFFSETS,
342 	CURSOR_OFFSETS
343 };
344 
345 #define G75_FEATURES  \
346 	GEN7_FEATURES, \
347 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
348 	.has_ddi = 1, \
349 	.has_fpga_dbg = 1, \
350 	.has_psr = 1, \
351 	.has_resource_streamer = 1, \
352 	.has_dp_mst = 1, \
353 	.has_rc6p = 0 /* RC6p removed-by HSW */, \
354 	.has_runtime_pm = 1
355 
356 #define HSW_PLATFORM \
357 	G75_FEATURES, \
358 	.platform = INTEL_HASWELL, \
359 	.has_l3_dpf = 1
360 
361 static const struct intel_device_info intel_haswell_gt1_info = {
362 	HSW_PLATFORM,
363 	.gt = 1,
364 };
365 
366 static const struct intel_device_info intel_haswell_gt2_info = {
367 	HSW_PLATFORM,
368 	.gt = 2,
369 };
370 
371 static const struct intel_device_info intel_haswell_gt3_info = {
372 	HSW_PLATFORM,
373 	.gt = 3,
374 };
375 
376 #define GEN8_FEATURES \
377 	G75_FEATURES, \
378 	BDW_COLORS, \
379 	.page_sizes = I915_GTT_PAGE_SIZE_4K | \
380 		      I915_GTT_PAGE_SIZE_2M, \
381 	.has_logical_ring_contexts = 1, \
382 	.has_full_48bit_ppgtt = 1, \
383 	.has_64bit_reloc = 1, \
384 	.has_reset_engine = 1
385 
386 #define BDW_PLATFORM \
387 	GEN8_FEATURES, \
388 	.gen = 8, \
389 	.platform = INTEL_BROADWELL
390 
391 static const struct intel_device_info intel_broadwell_gt1_info = {
392 	BDW_PLATFORM,
393 	.gt = 1,
394 };
395 
396 static const struct intel_device_info intel_broadwell_gt2_info = {
397 	BDW_PLATFORM,
398 	.gt = 2,
399 };
400 
401 static const struct intel_device_info intel_broadwell_rsvd_info = {
402 	BDW_PLATFORM,
403 	.gt = 3,
404 	/* According to the device ID those devices are GT3, they were
405 	 * previously treated as not GT3, keep it like that.
406 	 */
407 };
408 
409 static const struct intel_device_info intel_broadwell_gt3_info = {
410 	BDW_PLATFORM,
411 	.gt = 3,
412 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
413 };
414 
415 static const struct intel_device_info intel_cherryview_info = {
416 	.gen = 8, .num_pipes = 3,
417 	.has_hotplug = 1,
418 	.is_lp = 1,
419 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
420 	.platform = INTEL_CHERRYVIEW,
421 	.has_64bit_reloc = 1,
422 	.has_psr = 1,
423 	.has_runtime_pm = 1,
424 	.has_resource_streamer = 1,
425 	.has_rc6 = 1,
426 	.has_logical_ring_contexts = 1,
427 	.has_gmch_display = 1,
428 	.has_aliasing_ppgtt = 1,
429 	.has_full_ppgtt = 1,
430 	.has_reset_engine = 1,
431 	.has_snoop = true,
432 	.display_mmio_offset = VLV_DISPLAY_BASE,
433 	GEN_DEFAULT_PAGE_SIZES,
434 	GEN_CHV_PIPEOFFSETS,
435 	CURSOR_OFFSETS,
436 	CHV_COLORS,
437 };
438 
439 #define GEN9_DEFAULT_PAGE_SIZES \
440 	.page_sizes = I915_GTT_PAGE_SIZE_4K | \
441 		      I915_GTT_PAGE_SIZE_64K | \
442 		      I915_GTT_PAGE_SIZE_2M
443 
444 #define GEN9_FEATURES \
445 	GEN8_FEATURES, \
446 	GEN9_DEFAULT_PAGE_SIZES, \
447 	.has_logical_ring_preemption = 1, \
448 	.has_csr = 1, \
449 	.has_guc = 1, \
450 	.has_ipc = 1, \
451 	.ddb_size = 896
452 
453 #define SKL_PLATFORM \
454 	GEN9_FEATURES, \
455 	.gen = 9, \
456 	.platform = INTEL_SKYLAKE
457 
458 static const struct intel_device_info intel_skylake_gt1_info = {
459 	SKL_PLATFORM,
460 	.gt = 1,
461 };
462 
463 static const struct intel_device_info intel_skylake_gt2_info = {
464 	SKL_PLATFORM,
465 	.gt = 2,
466 };
467 
468 #define SKL_GT3_PLUS_PLATFORM \
469 	SKL_PLATFORM, \
470 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING
471 
472 
473 static const struct intel_device_info intel_skylake_gt3_info = {
474 	SKL_GT3_PLUS_PLATFORM,
475 	.gt = 3,
476 };
477 
478 static const struct intel_device_info intel_skylake_gt4_info = {
479 	SKL_GT3_PLUS_PLATFORM,
480 	.gt = 4,
481 };
482 
483 #define GEN9_LP_FEATURES \
484 	.gen = 9, \
485 	.is_lp = 1, \
486 	.has_hotplug = 1, \
487 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
488 	.num_pipes = 3, \
489 	.has_64bit_reloc = 1, \
490 	.has_ddi = 1, \
491 	.has_fpga_dbg = 1, \
492 	.has_fbc = 1, \
493 	.has_psr = 1, \
494 	.has_runtime_pm = 1, \
495 	.has_pooled_eu = 0, \
496 	.has_csr = 1, \
497 	.has_resource_streamer = 1, \
498 	.has_rc6 = 1, \
499 	.has_dp_mst = 1, \
500 	.has_logical_ring_contexts = 1, \
501 	.has_logical_ring_preemption = 1, \
502 	.has_guc = 1, \
503 	.has_aliasing_ppgtt = 1, \
504 	.has_full_ppgtt = 1, \
505 	.has_full_48bit_ppgtt = 1, \
506 	.has_reset_engine = 1, \
507 	.has_snoop = true, \
508 	.has_ipc = 1, \
509 	GEN9_DEFAULT_PAGE_SIZES, \
510 	GEN_DEFAULT_PIPEOFFSETS, \
511 	IVB_CURSOR_OFFSETS, \
512 	BDW_COLORS
513 
514 static const struct intel_device_info intel_broxton_info = {
515 	GEN9_LP_FEATURES,
516 	.platform = INTEL_BROXTON,
517 	.ddb_size = 512,
518 };
519 
520 static const struct intel_device_info intel_geminilake_info = {
521 	GEN9_LP_FEATURES,
522 	.platform = INTEL_GEMINILAKE,
523 	.ddb_size = 1024,
524 	GLK_COLORS,
525 };
526 
527 #define KBL_PLATFORM \
528 	GEN9_FEATURES, \
529 	.gen = 9, \
530 	.platform = INTEL_KABYLAKE
531 
532 static const struct intel_device_info intel_kabylake_gt1_info = {
533 	KBL_PLATFORM,
534 	.gt = 1,
535 };
536 
537 static const struct intel_device_info intel_kabylake_gt2_info = {
538 	KBL_PLATFORM,
539 	.gt = 2,
540 };
541 
542 static const struct intel_device_info intel_kabylake_gt3_info = {
543 	KBL_PLATFORM,
544 	.gt = 3,
545 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
546 };
547 
548 #define CFL_PLATFORM \
549 	GEN9_FEATURES, \
550 	.gen = 9, \
551 	.platform = INTEL_COFFEELAKE
552 
553 static const struct intel_device_info intel_coffeelake_gt1_info = {
554 	CFL_PLATFORM,
555 	.gt = 1,
556 };
557 
558 static const struct intel_device_info intel_coffeelake_gt2_info = {
559 	CFL_PLATFORM,
560 	.gt = 2,
561 };
562 
563 static const struct intel_device_info intel_coffeelake_gt3_info = {
564 	CFL_PLATFORM,
565 	.gt = 3,
566 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
567 };
568 
569 #define GEN10_FEATURES \
570 	GEN9_FEATURES, \
571 	.ddb_size = 1024, \
572 	GLK_COLORS
573 
574 static const struct intel_device_info intel_cannonlake_gt2_info = {
575 	GEN10_FEATURES,
576 	.is_alpha_support = 1,
577 	.platform = INTEL_CANNONLAKE,
578 	.gen = 10,
579 	.gt = 2,
580 };
581 
582 /*
583  * Make sure any device matches here are from most specific to most
584  * general.  For example, since the Quanta match is based on the subsystem
585  * and subvendor IDs, we need it to come before the more general IVB
586  * PCI ID matches, otherwise we'll use the wrong info struct above.
587  */
588 static const struct pci_device_id pciidlist[] = {
589 	INTEL_I830_IDS(&intel_i830_info),
590 	INTEL_I845G_IDS(&intel_i845g_info),
591 	INTEL_I85X_IDS(&intel_i85x_info),
592 	INTEL_I865G_IDS(&intel_i865g_info),
593 	INTEL_I915G_IDS(&intel_i915g_info),
594 	INTEL_I915GM_IDS(&intel_i915gm_info),
595 	INTEL_I945G_IDS(&intel_i945g_info),
596 	INTEL_I945GM_IDS(&intel_i945gm_info),
597 	INTEL_I965G_IDS(&intel_i965g_info),
598 	INTEL_G33_IDS(&intel_g33_info),
599 	INTEL_I965GM_IDS(&intel_i965gm_info),
600 	INTEL_GM45_IDS(&intel_gm45_info),
601 	INTEL_G45_IDS(&intel_g45_info),
602 	INTEL_PINEVIEW_IDS(&intel_pineview_info),
603 	INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
604 	INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
605 	INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info),
606 	INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info),
607 	INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info),
608 	INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info),
609 	INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
610 	INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info),
611 	INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info),
612 	INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info),
613 	INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info),
614 	INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info),
615 	INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info),
616 	INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info),
617 	INTEL_VLV_IDS(&intel_valleyview_info),
618 	INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
619 	INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info),
620 	INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
621 	INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info),
622 	INTEL_CHV_IDS(&intel_cherryview_info),
623 	INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info),
624 	INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info),
625 	INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
626 	INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info),
627 	INTEL_BXT_IDS(&intel_broxton_info),
628 	INTEL_GLK_IDS(&intel_geminilake_info),
629 	INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info),
630 	INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info),
631 	INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
632 	INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
633 	INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
634 	INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
635 	INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
636 	INTEL_CFL_U_GT1_IDS(&intel_coffeelake_gt1_info),
637 	INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),
638 	INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
639 	INTEL_CNL_U_GT2_IDS(&intel_cannonlake_gt2_info),
640 	INTEL_CNL_Y_GT2_IDS(&intel_cannonlake_gt2_info),
641 	{0, 0, 0}
642 };
643 MODULE_DEVICE_TABLE(pci, pciidlist);
644 
645 static void i915_pci_remove(struct pci_dev *pdev)
646 {
647 	struct drm_device *dev = pci_get_drvdata(pdev);
648 
649 	i915_driver_unload(dev);
650 	drm_dev_put(dev);
651 }
652 
653 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
654 {
655 	struct intel_device_info *intel_info =
656 		(struct intel_device_info *) ent->driver_data;
657 	int err;
658 
659 	if (IS_ALPHA_SUPPORT(intel_info) && !i915_modparams.alpha_support) {
660 		DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n"
661 			 "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n"
662 			 "to enable support in this kernel version, or check for kernel updates.\n");
663 		return -ENODEV;
664 	}
665 
666 	/* Only bind to function 0 of the device. Early generations
667 	 * used function 1 as a placeholder for multi-head. This causes
668 	 * us confusion instead, especially on the systems where both
669 	 * functions have the same PCI-ID!
670 	 */
671 	if (PCI_FUNC(pdev->devfn))
672 		return -ENODEV;
673 
674 	/*
675 	 * apple-gmux is needed on dual GPU MacBook Pro
676 	 * to probe the panel if we're the inactive GPU.
677 	 */
678 	if (vga_switcheroo_client_probe_defer(pdev))
679 		return -EPROBE_DEFER;
680 
681 	err = i915_driver_load(pdev, ent);
682 	if (err)
683 		return err;
684 
685 	err = i915_live_selftests(pdev);
686 	if (err) {
687 		i915_pci_remove(pdev);
688 		return err > 0 ? -ENOTTY : err;
689 	}
690 
691 	return 0;
692 }
693 
694 static struct pci_driver i915_pci_driver = {
695 	.name = DRIVER_NAME,
696 	.id_table = pciidlist,
697 	.probe = i915_pci_probe,
698 	.remove = i915_pci_remove,
699 	.driver.pm = &i915_pm_ops,
700 };
701 
702 static int __init i915_init(void)
703 {
704 	bool use_kms = true;
705 	int err;
706 
707 	err = i915_mock_selftests();
708 	if (err)
709 		return err > 0 ? 0 : err;
710 
711 	/*
712 	 * Enable KMS by default, unless explicitly overriden by
713 	 * either the i915.modeset prarameter or by the
714 	 * vga_text_mode_force boot option.
715 	 */
716 
717 	if (i915_modparams.modeset == 0)
718 		use_kms = false;
719 
720 	if (vgacon_text_force() && i915_modparams.modeset == -1)
721 		use_kms = false;
722 
723 	if (!use_kms) {
724 		/* Silently fail loading to not upset userspace. */
725 		DRM_DEBUG_DRIVER("KMS disabled.\n");
726 		return 0;
727 	}
728 
729 	return pci_register_driver(&i915_pci_driver);
730 }
731 
732 static void __exit i915_exit(void)
733 {
734 	if (!i915_pci_driver.driver.owner)
735 		return;
736 
737 	pci_unregister_driver(&i915_pci_driver);
738 }
739 
740 module_init(i915_init);
741 module_exit(i915_exit);
742 
743 MODULE_AUTHOR("Tungsten Graphics, Inc.");
744 MODULE_AUTHOR("Intel Corporation");
745 
746 MODULE_DESCRIPTION(DRIVER_DESC);
747 MODULE_LICENSE("GPL and additional rights");
748