1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/console.h> 26 #include <linux/vga_switcheroo.h> 27 28 #include <drm/drm_drv.h> 29 #include <drm/i915_pciids.h> 30 31 #include "display/intel_fbdev.h" 32 33 #include "i915_drv.h" 34 #include "i915_perf.h" 35 #include "i915_globals.h" 36 #include "i915_selftest.h" 37 38 #define PLATFORM(x) .platform = (x) 39 #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1) 40 41 #define I845_PIPE_OFFSETS \ 42 .pipe_offsets = { \ 43 [TRANSCODER_A] = PIPE_A_OFFSET, \ 44 }, \ 45 .trans_offsets = { \ 46 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 47 } 48 49 #define I9XX_PIPE_OFFSETS \ 50 .pipe_offsets = { \ 51 [TRANSCODER_A] = PIPE_A_OFFSET, \ 52 [TRANSCODER_B] = PIPE_B_OFFSET, \ 53 }, \ 54 .trans_offsets = { \ 55 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 56 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 57 } 58 59 #define IVB_PIPE_OFFSETS \ 60 .pipe_offsets = { \ 61 [TRANSCODER_A] = PIPE_A_OFFSET, \ 62 [TRANSCODER_B] = PIPE_B_OFFSET, \ 63 [TRANSCODER_C] = PIPE_C_OFFSET, \ 64 }, \ 65 .trans_offsets = { \ 66 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 67 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 68 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 69 } 70 71 #define HSW_PIPE_OFFSETS \ 72 .pipe_offsets = { \ 73 [TRANSCODER_A] = PIPE_A_OFFSET, \ 74 [TRANSCODER_B] = PIPE_B_OFFSET, \ 75 [TRANSCODER_C] = PIPE_C_OFFSET, \ 76 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 77 }, \ 78 .trans_offsets = { \ 79 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 80 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 81 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 82 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 83 } 84 85 #define CHV_PIPE_OFFSETS \ 86 .pipe_offsets = { \ 87 [TRANSCODER_A] = PIPE_A_OFFSET, \ 88 [TRANSCODER_B] = PIPE_B_OFFSET, \ 89 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \ 90 }, \ 91 .trans_offsets = { \ 92 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 93 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 94 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \ 95 } 96 97 #define I845_CURSOR_OFFSETS \ 98 .cursor_offsets = { \ 99 [PIPE_A] = CURSOR_A_OFFSET, \ 100 } 101 102 #define I9XX_CURSOR_OFFSETS \ 103 .cursor_offsets = { \ 104 [PIPE_A] = CURSOR_A_OFFSET, \ 105 [PIPE_B] = CURSOR_B_OFFSET, \ 106 } 107 108 #define CHV_CURSOR_OFFSETS \ 109 .cursor_offsets = { \ 110 [PIPE_A] = CURSOR_A_OFFSET, \ 111 [PIPE_B] = CURSOR_B_OFFSET, \ 112 [PIPE_C] = CHV_CURSOR_C_OFFSET, \ 113 } 114 115 #define IVB_CURSOR_OFFSETS \ 116 .cursor_offsets = { \ 117 [PIPE_A] = CURSOR_A_OFFSET, \ 118 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 119 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 120 } 121 122 #define TGL_CURSOR_OFFSETS \ 123 .cursor_offsets = { \ 124 [PIPE_A] = CURSOR_A_OFFSET, \ 125 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 126 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 127 [PIPE_D] = TGL_CURSOR_D_OFFSET, \ 128 } 129 130 #define I9XX_COLORS \ 131 .color = { .gamma_lut_size = 256 } 132 #define I965_COLORS \ 133 .color = { .gamma_lut_size = 129, \ 134 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 135 } 136 #define ILK_COLORS \ 137 .color = { .gamma_lut_size = 1024 } 138 #define IVB_COLORS \ 139 .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 } 140 #define CHV_COLORS \ 141 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \ 142 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 143 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 144 } 145 #define GLK_COLORS \ 146 .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \ 147 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 148 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 149 } 150 151 /* Keep in gen based order, and chronological order within a gen */ 152 153 #define GEN_DEFAULT_PAGE_SIZES \ 154 .page_sizes = I915_GTT_PAGE_SIZE_4K 155 156 #define GEN_DEFAULT_REGIONS \ 157 .memory_regions = REGION_SMEM | REGION_STOLEN 158 159 #define I830_FEATURES \ 160 GEN(2), \ 161 .is_mobile = 1, \ 162 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 163 .display.has_overlay = 1, \ 164 .display.cursor_needs_physical = 1, \ 165 .display.overlay_needs_physical = 1, \ 166 .display.has_gmch = 1, \ 167 .gpu_reset_clobbers_display = true, \ 168 .hws_needs_physical = 1, \ 169 .unfenced_needs_alignment = 1, \ 170 .engine_mask = BIT(RCS0), \ 171 .has_snoop = true, \ 172 .has_coherent_ggtt = false, \ 173 I9XX_PIPE_OFFSETS, \ 174 I9XX_CURSOR_OFFSETS, \ 175 I9XX_COLORS, \ 176 GEN_DEFAULT_PAGE_SIZES, \ 177 GEN_DEFAULT_REGIONS 178 179 #define I845_FEATURES \ 180 GEN(2), \ 181 .pipe_mask = BIT(PIPE_A), \ 182 .display.has_overlay = 1, \ 183 .display.overlay_needs_physical = 1, \ 184 .display.has_gmch = 1, \ 185 .gpu_reset_clobbers_display = true, \ 186 .hws_needs_physical = 1, \ 187 .unfenced_needs_alignment = 1, \ 188 .engine_mask = BIT(RCS0), \ 189 .has_snoop = true, \ 190 .has_coherent_ggtt = false, \ 191 I845_PIPE_OFFSETS, \ 192 I845_CURSOR_OFFSETS, \ 193 I9XX_COLORS, \ 194 GEN_DEFAULT_PAGE_SIZES, \ 195 GEN_DEFAULT_REGIONS 196 197 static const struct intel_device_info i830_info = { 198 I830_FEATURES, 199 PLATFORM(INTEL_I830), 200 }; 201 202 static const struct intel_device_info i845g_info = { 203 I845_FEATURES, 204 PLATFORM(INTEL_I845G), 205 }; 206 207 static const struct intel_device_info i85x_info = { 208 I830_FEATURES, 209 PLATFORM(INTEL_I85X), 210 .display.has_fbc = 1, 211 }; 212 213 static const struct intel_device_info i865g_info = { 214 I845_FEATURES, 215 PLATFORM(INTEL_I865G), 216 }; 217 218 #define GEN3_FEATURES \ 219 GEN(3), \ 220 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 221 .display.has_gmch = 1, \ 222 .gpu_reset_clobbers_display = true, \ 223 .engine_mask = BIT(RCS0), \ 224 .has_snoop = true, \ 225 .has_coherent_ggtt = true, \ 226 I9XX_PIPE_OFFSETS, \ 227 I9XX_CURSOR_OFFSETS, \ 228 I9XX_COLORS, \ 229 GEN_DEFAULT_PAGE_SIZES, \ 230 GEN_DEFAULT_REGIONS 231 232 static const struct intel_device_info i915g_info = { 233 GEN3_FEATURES, 234 PLATFORM(INTEL_I915G), 235 .has_coherent_ggtt = false, 236 .display.cursor_needs_physical = 1, 237 .display.has_overlay = 1, 238 .display.overlay_needs_physical = 1, 239 .hws_needs_physical = 1, 240 .unfenced_needs_alignment = 1, 241 }; 242 243 static const struct intel_device_info i915gm_info = { 244 GEN3_FEATURES, 245 PLATFORM(INTEL_I915GM), 246 .is_mobile = 1, 247 .display.cursor_needs_physical = 1, 248 .display.has_overlay = 1, 249 .display.overlay_needs_physical = 1, 250 .display.supports_tv = 1, 251 .display.has_fbc = 1, 252 .hws_needs_physical = 1, 253 .unfenced_needs_alignment = 1, 254 }; 255 256 static const struct intel_device_info i945g_info = { 257 GEN3_FEATURES, 258 PLATFORM(INTEL_I945G), 259 .display.has_hotplug = 1, 260 .display.cursor_needs_physical = 1, 261 .display.has_overlay = 1, 262 .display.overlay_needs_physical = 1, 263 .hws_needs_physical = 1, 264 .unfenced_needs_alignment = 1, 265 }; 266 267 static const struct intel_device_info i945gm_info = { 268 GEN3_FEATURES, 269 PLATFORM(INTEL_I945GM), 270 .is_mobile = 1, 271 .display.has_hotplug = 1, 272 .display.cursor_needs_physical = 1, 273 .display.has_overlay = 1, 274 .display.overlay_needs_physical = 1, 275 .display.supports_tv = 1, 276 .display.has_fbc = 1, 277 .hws_needs_physical = 1, 278 .unfenced_needs_alignment = 1, 279 }; 280 281 static const struct intel_device_info g33_info = { 282 GEN3_FEATURES, 283 PLATFORM(INTEL_G33), 284 .display.has_hotplug = 1, 285 .display.has_overlay = 1, 286 }; 287 288 static const struct intel_device_info pnv_g_info = { 289 GEN3_FEATURES, 290 PLATFORM(INTEL_PINEVIEW), 291 .display.has_hotplug = 1, 292 .display.has_overlay = 1, 293 }; 294 295 static const struct intel_device_info pnv_m_info = { 296 GEN3_FEATURES, 297 PLATFORM(INTEL_PINEVIEW), 298 .is_mobile = 1, 299 .display.has_hotplug = 1, 300 .display.has_overlay = 1, 301 }; 302 303 #define GEN4_FEATURES \ 304 GEN(4), \ 305 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 306 .display.has_hotplug = 1, \ 307 .display.has_gmch = 1, \ 308 .gpu_reset_clobbers_display = true, \ 309 .engine_mask = BIT(RCS0), \ 310 .has_snoop = true, \ 311 .has_coherent_ggtt = true, \ 312 I9XX_PIPE_OFFSETS, \ 313 I9XX_CURSOR_OFFSETS, \ 314 I965_COLORS, \ 315 GEN_DEFAULT_PAGE_SIZES, \ 316 GEN_DEFAULT_REGIONS 317 318 static const struct intel_device_info i965g_info = { 319 GEN4_FEATURES, 320 PLATFORM(INTEL_I965G), 321 .display.has_overlay = 1, 322 .hws_needs_physical = 1, 323 .has_snoop = false, 324 }; 325 326 static const struct intel_device_info i965gm_info = { 327 GEN4_FEATURES, 328 PLATFORM(INTEL_I965GM), 329 .is_mobile = 1, 330 .display.has_fbc = 1, 331 .display.has_overlay = 1, 332 .display.supports_tv = 1, 333 .hws_needs_physical = 1, 334 .has_snoop = false, 335 }; 336 337 static const struct intel_device_info g45_info = { 338 GEN4_FEATURES, 339 PLATFORM(INTEL_G45), 340 .engine_mask = BIT(RCS0) | BIT(VCS0), 341 .gpu_reset_clobbers_display = false, 342 }; 343 344 static const struct intel_device_info gm45_info = { 345 GEN4_FEATURES, 346 PLATFORM(INTEL_GM45), 347 .is_mobile = 1, 348 .display.has_fbc = 1, 349 .display.supports_tv = 1, 350 .engine_mask = BIT(RCS0) | BIT(VCS0), 351 .gpu_reset_clobbers_display = false, 352 }; 353 354 #define GEN5_FEATURES \ 355 GEN(5), \ 356 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 357 .display.has_hotplug = 1, \ 358 .engine_mask = BIT(RCS0) | BIT(VCS0), \ 359 .has_snoop = true, \ 360 .has_coherent_ggtt = true, \ 361 /* ilk does support rc6, but we do not implement [power] contexts */ \ 362 .has_rc6 = 0, \ 363 I9XX_PIPE_OFFSETS, \ 364 I9XX_CURSOR_OFFSETS, \ 365 ILK_COLORS, \ 366 GEN_DEFAULT_PAGE_SIZES, \ 367 GEN_DEFAULT_REGIONS 368 369 static const struct intel_device_info ilk_d_info = { 370 GEN5_FEATURES, 371 PLATFORM(INTEL_IRONLAKE), 372 }; 373 374 static const struct intel_device_info ilk_m_info = { 375 GEN5_FEATURES, 376 PLATFORM(INTEL_IRONLAKE), 377 .is_mobile = 1, 378 .display.has_fbc = 1, 379 }; 380 381 #define GEN6_FEATURES \ 382 GEN(6), \ 383 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 384 .display.has_hotplug = 1, \ 385 .display.has_fbc = 1, \ 386 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ 387 .has_coherent_ggtt = true, \ 388 .has_llc = 1, \ 389 .has_rc6 = 1, \ 390 .has_rc6p = 1, \ 391 .has_rps = true, \ 392 .ppgtt_type = INTEL_PPGTT_ALIASING, \ 393 .ppgtt_size = 31, \ 394 I9XX_PIPE_OFFSETS, \ 395 I9XX_CURSOR_OFFSETS, \ 396 ILK_COLORS, \ 397 GEN_DEFAULT_PAGE_SIZES, \ 398 GEN_DEFAULT_REGIONS 399 400 #define SNB_D_PLATFORM \ 401 GEN6_FEATURES, \ 402 PLATFORM(INTEL_SANDYBRIDGE) 403 404 static const struct intel_device_info snb_d_gt1_info = { 405 SNB_D_PLATFORM, 406 .gt = 1, 407 }; 408 409 static const struct intel_device_info snb_d_gt2_info = { 410 SNB_D_PLATFORM, 411 .gt = 2, 412 }; 413 414 #define SNB_M_PLATFORM \ 415 GEN6_FEATURES, \ 416 PLATFORM(INTEL_SANDYBRIDGE), \ 417 .is_mobile = 1 418 419 420 static const struct intel_device_info snb_m_gt1_info = { 421 SNB_M_PLATFORM, 422 .gt = 1, 423 }; 424 425 static const struct intel_device_info snb_m_gt2_info = { 426 SNB_M_PLATFORM, 427 .gt = 2, 428 }; 429 430 #define GEN7_FEATURES \ 431 GEN(7), \ 432 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ 433 .display.has_hotplug = 1, \ 434 .display.has_fbc = 1, \ 435 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ 436 .has_coherent_ggtt = true, \ 437 .has_llc = 1, \ 438 .has_rc6 = 1, \ 439 .has_rc6p = 1, \ 440 .has_rps = true, \ 441 .ppgtt_type = INTEL_PPGTT_ALIASING, \ 442 .ppgtt_size = 31, \ 443 IVB_PIPE_OFFSETS, \ 444 IVB_CURSOR_OFFSETS, \ 445 IVB_COLORS, \ 446 GEN_DEFAULT_PAGE_SIZES, \ 447 GEN_DEFAULT_REGIONS 448 449 #define IVB_D_PLATFORM \ 450 GEN7_FEATURES, \ 451 PLATFORM(INTEL_IVYBRIDGE), \ 452 .has_l3_dpf = 1 453 454 static const struct intel_device_info ivb_d_gt1_info = { 455 IVB_D_PLATFORM, 456 .gt = 1, 457 }; 458 459 static const struct intel_device_info ivb_d_gt2_info = { 460 IVB_D_PLATFORM, 461 .gt = 2, 462 }; 463 464 #define IVB_M_PLATFORM \ 465 GEN7_FEATURES, \ 466 PLATFORM(INTEL_IVYBRIDGE), \ 467 .is_mobile = 1, \ 468 .has_l3_dpf = 1 469 470 static const struct intel_device_info ivb_m_gt1_info = { 471 IVB_M_PLATFORM, 472 .gt = 1, 473 }; 474 475 static const struct intel_device_info ivb_m_gt2_info = { 476 IVB_M_PLATFORM, 477 .gt = 2, 478 }; 479 480 static const struct intel_device_info ivb_q_info = { 481 GEN7_FEATURES, 482 PLATFORM(INTEL_IVYBRIDGE), 483 .gt = 2, 484 .pipe_mask = 0, /* legal, last one wins */ 485 .has_l3_dpf = 1, 486 }; 487 488 static const struct intel_device_info vlv_info = { 489 PLATFORM(INTEL_VALLEYVIEW), 490 GEN(7), 491 .is_lp = 1, 492 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), 493 .has_runtime_pm = 1, 494 .has_rc6 = 1, 495 .has_rps = true, 496 .display.has_gmch = 1, 497 .display.has_hotplug = 1, 498 .ppgtt_type = INTEL_PPGTT_ALIASING, 499 .ppgtt_size = 31, 500 .has_snoop = true, 501 .has_coherent_ggtt = false, 502 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), 503 .display_mmio_offset = VLV_DISPLAY_BASE, 504 I9XX_PIPE_OFFSETS, 505 I9XX_CURSOR_OFFSETS, 506 I965_COLORS, 507 GEN_DEFAULT_PAGE_SIZES, 508 GEN_DEFAULT_REGIONS, 509 }; 510 511 #define G75_FEATURES \ 512 GEN7_FEATURES, \ 513 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ 514 .display.has_ddi = 1, \ 515 .has_fpga_dbg = 1, \ 516 .display.has_psr = 1, \ 517 .display.has_dp_mst = 1, \ 518 .has_rc6p = 0 /* RC6p removed-by HSW */, \ 519 HSW_PIPE_OFFSETS, \ 520 .has_runtime_pm = 1 521 522 #define HSW_PLATFORM \ 523 G75_FEATURES, \ 524 PLATFORM(INTEL_HASWELL), \ 525 .has_l3_dpf = 1 526 527 static const struct intel_device_info hsw_gt1_info = { 528 HSW_PLATFORM, 529 .gt = 1, 530 }; 531 532 static const struct intel_device_info hsw_gt2_info = { 533 HSW_PLATFORM, 534 .gt = 2, 535 }; 536 537 static const struct intel_device_info hsw_gt3_info = { 538 HSW_PLATFORM, 539 .gt = 3, 540 }; 541 542 #define GEN8_FEATURES \ 543 G75_FEATURES, \ 544 GEN(8), \ 545 .has_logical_ring_contexts = 1, \ 546 .ppgtt_type = INTEL_PPGTT_FULL, \ 547 .ppgtt_size = 48, \ 548 .has_64bit_reloc = 1, \ 549 .has_reset_engine = 1 550 551 #define BDW_PLATFORM \ 552 GEN8_FEATURES, \ 553 PLATFORM(INTEL_BROADWELL) 554 555 static const struct intel_device_info bdw_gt1_info = { 556 BDW_PLATFORM, 557 .gt = 1, 558 }; 559 560 static const struct intel_device_info bdw_gt2_info = { 561 BDW_PLATFORM, 562 .gt = 2, 563 }; 564 565 static const struct intel_device_info bdw_rsvd_info = { 566 BDW_PLATFORM, 567 .gt = 3, 568 /* According to the device ID those devices are GT3, they were 569 * previously treated as not GT3, keep it like that. 570 */ 571 }; 572 573 static const struct intel_device_info bdw_gt3_info = { 574 BDW_PLATFORM, 575 .gt = 3, 576 .engine_mask = 577 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 578 }; 579 580 static const struct intel_device_info chv_info = { 581 PLATFORM(INTEL_CHERRYVIEW), 582 GEN(8), 583 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 584 .display.has_hotplug = 1, 585 .is_lp = 1, 586 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), 587 .has_64bit_reloc = 1, 588 .has_runtime_pm = 1, 589 .has_rc6 = 1, 590 .has_rps = true, 591 .has_logical_ring_contexts = 1, 592 .display.has_gmch = 1, 593 .ppgtt_type = INTEL_PPGTT_ALIASING, 594 .ppgtt_size = 32, 595 .has_reset_engine = 1, 596 .has_snoop = true, 597 .has_coherent_ggtt = false, 598 .display_mmio_offset = VLV_DISPLAY_BASE, 599 CHV_PIPE_OFFSETS, 600 CHV_CURSOR_OFFSETS, 601 CHV_COLORS, 602 GEN_DEFAULT_PAGE_SIZES, 603 GEN_DEFAULT_REGIONS, 604 }; 605 606 #define GEN9_DEFAULT_PAGE_SIZES \ 607 .page_sizes = I915_GTT_PAGE_SIZE_4K | \ 608 I915_GTT_PAGE_SIZE_64K 609 610 #define GEN9_FEATURES \ 611 GEN8_FEATURES, \ 612 GEN(9), \ 613 GEN9_DEFAULT_PAGE_SIZES, \ 614 .has_logical_ring_preemption = 1, \ 615 .display.has_csr = 1, \ 616 .has_gt_uc = 1, \ 617 .display.has_hdcp = 1, \ 618 .display.has_ipc = 1, \ 619 .ddb_size = 896, \ 620 .num_supported_dbuf_slices = 1 621 622 #define SKL_PLATFORM \ 623 GEN9_FEATURES, \ 624 PLATFORM(INTEL_SKYLAKE) 625 626 static const struct intel_device_info skl_gt1_info = { 627 SKL_PLATFORM, 628 .gt = 1, 629 }; 630 631 static const struct intel_device_info skl_gt2_info = { 632 SKL_PLATFORM, 633 .gt = 2, 634 }; 635 636 #define SKL_GT3_PLUS_PLATFORM \ 637 SKL_PLATFORM, \ 638 .engine_mask = \ 639 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1) 640 641 642 static const struct intel_device_info skl_gt3_info = { 643 SKL_GT3_PLUS_PLATFORM, 644 .gt = 3, 645 }; 646 647 static const struct intel_device_info skl_gt4_info = { 648 SKL_GT3_PLUS_PLATFORM, 649 .gt = 4, 650 }; 651 652 #define GEN9_LP_FEATURES \ 653 GEN(9), \ 654 .is_lp = 1, \ 655 .num_supported_dbuf_slices = 1, \ 656 .display.has_hotplug = 1, \ 657 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ 658 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ 659 .has_64bit_reloc = 1, \ 660 .display.has_ddi = 1, \ 661 .has_fpga_dbg = 1, \ 662 .display.has_fbc = 1, \ 663 .display.has_hdcp = 1, \ 664 .display.has_psr = 1, \ 665 .has_runtime_pm = 1, \ 666 .display.has_csr = 1, \ 667 .has_rc6 = 1, \ 668 .has_rps = true, \ 669 .display.has_dp_mst = 1, \ 670 .has_logical_ring_contexts = 1, \ 671 .has_logical_ring_preemption = 1, \ 672 .has_gt_uc = 1, \ 673 .ppgtt_type = INTEL_PPGTT_FULL, \ 674 .ppgtt_size = 48, \ 675 .has_reset_engine = 1, \ 676 .has_snoop = true, \ 677 .has_coherent_ggtt = false, \ 678 .display.has_ipc = 1, \ 679 HSW_PIPE_OFFSETS, \ 680 IVB_CURSOR_OFFSETS, \ 681 IVB_COLORS, \ 682 GEN9_DEFAULT_PAGE_SIZES, \ 683 GEN_DEFAULT_REGIONS 684 685 static const struct intel_device_info bxt_info = { 686 GEN9_LP_FEATURES, 687 PLATFORM(INTEL_BROXTON), 688 .ddb_size = 512, 689 }; 690 691 static const struct intel_device_info glk_info = { 692 GEN9_LP_FEATURES, 693 PLATFORM(INTEL_GEMINILAKE), 694 .ddb_size = 1024, 695 GLK_COLORS, 696 }; 697 698 #define KBL_PLATFORM \ 699 GEN9_FEATURES, \ 700 PLATFORM(INTEL_KABYLAKE) 701 702 static const struct intel_device_info kbl_gt1_info = { 703 KBL_PLATFORM, 704 .gt = 1, 705 }; 706 707 static const struct intel_device_info kbl_gt2_info = { 708 KBL_PLATFORM, 709 .gt = 2, 710 }; 711 712 static const struct intel_device_info kbl_gt3_info = { 713 KBL_PLATFORM, 714 .gt = 3, 715 .engine_mask = 716 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 717 }; 718 719 #define CFL_PLATFORM \ 720 GEN9_FEATURES, \ 721 PLATFORM(INTEL_COFFEELAKE) 722 723 static const struct intel_device_info cfl_gt1_info = { 724 CFL_PLATFORM, 725 .gt = 1, 726 }; 727 728 static const struct intel_device_info cfl_gt2_info = { 729 CFL_PLATFORM, 730 .gt = 2, 731 }; 732 733 static const struct intel_device_info cfl_gt3_info = { 734 CFL_PLATFORM, 735 .gt = 3, 736 .engine_mask = 737 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 738 }; 739 740 #define GEN10_FEATURES \ 741 GEN9_FEATURES, \ 742 GEN(10), \ 743 .ddb_size = 1024, \ 744 .display.has_dsc = 1, \ 745 .has_coherent_ggtt = false, \ 746 GLK_COLORS 747 748 static const struct intel_device_info cnl_info = { 749 GEN10_FEATURES, 750 PLATFORM(INTEL_CANNONLAKE), 751 .gt = 2, 752 }; 753 754 #define GEN11_DEFAULT_PAGE_SIZES \ 755 .page_sizes = I915_GTT_PAGE_SIZE_4K | \ 756 I915_GTT_PAGE_SIZE_64K | \ 757 I915_GTT_PAGE_SIZE_2M 758 759 #define GEN11_FEATURES \ 760 GEN10_FEATURES, \ 761 GEN11_DEFAULT_PAGE_SIZES, \ 762 .pipe_offsets = { \ 763 [TRANSCODER_A] = PIPE_A_OFFSET, \ 764 [TRANSCODER_B] = PIPE_B_OFFSET, \ 765 [TRANSCODER_C] = PIPE_C_OFFSET, \ 766 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 767 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 768 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 769 }, \ 770 .trans_offsets = { \ 771 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 772 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 773 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 774 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 775 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 776 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 777 }, \ 778 GEN(11), \ 779 .ddb_size = 2048, \ 780 .num_supported_dbuf_slices = 2, \ 781 .has_logical_ring_elsq = 1, \ 782 .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 } 783 784 static const struct intel_device_info icl_info = { 785 GEN11_FEATURES, 786 PLATFORM(INTEL_ICELAKE), 787 .engine_mask = 788 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 789 }; 790 791 static const struct intel_device_info ehl_info = { 792 GEN11_FEATURES, 793 PLATFORM(INTEL_ELKHARTLAKE), 794 .require_force_probe = 1, 795 .engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0), 796 .ppgtt_size = 36, 797 }; 798 799 #define GEN12_FEATURES \ 800 GEN11_FEATURES, \ 801 GEN(12), \ 802 .pipe_offsets = { \ 803 [TRANSCODER_A] = PIPE_A_OFFSET, \ 804 [TRANSCODER_B] = PIPE_B_OFFSET, \ 805 [TRANSCODER_C] = PIPE_C_OFFSET, \ 806 [TRANSCODER_D] = PIPE_D_OFFSET, \ 807 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 808 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 809 }, \ 810 .trans_offsets = { \ 811 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 812 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 813 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 814 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ 815 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 816 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 817 }, \ 818 TGL_CURSOR_OFFSETS, \ 819 .has_global_mocs = 1, \ 820 .display.has_dsb = 1 821 822 static const struct intel_device_info tgl_info = { 823 GEN12_FEATURES, 824 PLATFORM(INTEL_TIGERLAKE), 825 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 826 .display.has_modular_fia = 1, 827 .engine_mask = 828 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 829 }; 830 831 #define GEN12_DGFX_FEATURES \ 832 GEN12_FEATURES, \ 833 .is_dgfx = 1 834 835 #undef GEN 836 #undef PLATFORM 837 838 /* 839 * Make sure any device matches here are from most specific to most 840 * general. For example, since the Quanta match is based on the subsystem 841 * and subvendor IDs, we need it to come before the more general IVB 842 * PCI ID matches, otherwise we'll use the wrong info struct above. 843 */ 844 static const struct pci_device_id pciidlist[] = { 845 INTEL_I830_IDS(&i830_info), 846 INTEL_I845G_IDS(&i845g_info), 847 INTEL_I85X_IDS(&i85x_info), 848 INTEL_I865G_IDS(&i865g_info), 849 INTEL_I915G_IDS(&i915g_info), 850 INTEL_I915GM_IDS(&i915gm_info), 851 INTEL_I945G_IDS(&i945g_info), 852 INTEL_I945GM_IDS(&i945gm_info), 853 INTEL_I965G_IDS(&i965g_info), 854 INTEL_G33_IDS(&g33_info), 855 INTEL_I965GM_IDS(&i965gm_info), 856 INTEL_GM45_IDS(&gm45_info), 857 INTEL_G45_IDS(&g45_info), 858 INTEL_PINEVIEW_G_IDS(&pnv_g_info), 859 INTEL_PINEVIEW_M_IDS(&pnv_m_info), 860 INTEL_IRONLAKE_D_IDS(&ilk_d_info), 861 INTEL_IRONLAKE_M_IDS(&ilk_m_info), 862 INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info), 863 INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info), 864 INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info), 865 INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info), 866 INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */ 867 INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info), 868 INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info), 869 INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info), 870 INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info), 871 INTEL_HSW_GT1_IDS(&hsw_gt1_info), 872 INTEL_HSW_GT2_IDS(&hsw_gt2_info), 873 INTEL_HSW_GT3_IDS(&hsw_gt3_info), 874 INTEL_VLV_IDS(&vlv_info), 875 INTEL_BDW_GT1_IDS(&bdw_gt1_info), 876 INTEL_BDW_GT2_IDS(&bdw_gt2_info), 877 INTEL_BDW_GT3_IDS(&bdw_gt3_info), 878 INTEL_BDW_RSVD_IDS(&bdw_rsvd_info), 879 INTEL_CHV_IDS(&chv_info), 880 INTEL_SKL_GT1_IDS(&skl_gt1_info), 881 INTEL_SKL_GT2_IDS(&skl_gt2_info), 882 INTEL_SKL_GT3_IDS(&skl_gt3_info), 883 INTEL_SKL_GT4_IDS(&skl_gt4_info), 884 INTEL_BXT_IDS(&bxt_info), 885 INTEL_GLK_IDS(&glk_info), 886 INTEL_KBL_GT1_IDS(&kbl_gt1_info), 887 INTEL_KBL_GT2_IDS(&kbl_gt2_info), 888 INTEL_KBL_GT3_IDS(&kbl_gt3_info), 889 INTEL_KBL_GT4_IDS(&kbl_gt3_info), 890 INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info), 891 INTEL_CFL_S_GT1_IDS(&cfl_gt1_info), 892 INTEL_CFL_S_GT2_IDS(&cfl_gt2_info), 893 INTEL_CFL_H_GT1_IDS(&cfl_gt1_info), 894 INTEL_CFL_H_GT2_IDS(&cfl_gt2_info), 895 INTEL_CFL_U_GT2_IDS(&cfl_gt2_info), 896 INTEL_CFL_U_GT3_IDS(&cfl_gt3_info), 897 INTEL_WHL_U_GT1_IDS(&cfl_gt1_info), 898 INTEL_WHL_U_GT2_IDS(&cfl_gt2_info), 899 INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info), 900 INTEL_WHL_U_GT3_IDS(&cfl_gt3_info), 901 INTEL_CML_GT1_IDS(&cfl_gt1_info), 902 INTEL_CML_GT2_IDS(&cfl_gt2_info), 903 INTEL_CML_U_GT1_IDS(&cfl_gt1_info), 904 INTEL_CML_U_GT2_IDS(&cfl_gt2_info), 905 INTEL_CNL_IDS(&cnl_info), 906 INTEL_ICL_11_IDS(&icl_info), 907 INTEL_EHL_IDS(&ehl_info), 908 INTEL_TGL_12_IDS(&tgl_info), 909 {0, 0, 0} 910 }; 911 MODULE_DEVICE_TABLE(pci, pciidlist); 912 913 static void i915_pci_remove(struct pci_dev *pdev) 914 { 915 struct drm_i915_private *i915; 916 917 i915 = pci_get_drvdata(pdev); 918 if (!i915) /* driver load aborted, nothing to cleanup */ 919 return; 920 921 i915_driver_remove(i915); 922 pci_set_drvdata(pdev, NULL); 923 924 drm_dev_put(&i915->drm); 925 } 926 927 /* is device_id present in comma separated list of ids */ 928 static bool force_probe(u16 device_id, const char *devices) 929 { 930 char *s, *p, *tok; 931 bool ret; 932 933 if (!devices || !*devices) 934 return false; 935 936 /* match everything */ 937 if (strcmp(devices, "*") == 0) 938 return true; 939 940 s = kstrdup(devices, GFP_KERNEL); 941 if (!s) 942 return false; 943 944 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) { 945 u16 val; 946 947 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) { 948 ret = true; 949 break; 950 } 951 } 952 953 kfree(s); 954 955 return ret; 956 } 957 958 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 959 { 960 struct intel_device_info *intel_info = 961 (struct intel_device_info *) ent->driver_data; 962 int err; 963 964 if (intel_info->require_force_probe && 965 !force_probe(pdev->device, i915_modparams.force_probe)) { 966 dev_info(&pdev->dev, 967 "Your graphics device %04x is not properly supported by the driver in this\n" 968 "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n" 969 "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n" 970 "or (recommended) check for kernel updates.\n", 971 pdev->device, pdev->device, pdev->device); 972 return -ENODEV; 973 } 974 975 /* Only bind to function 0 of the device. Early generations 976 * used function 1 as a placeholder for multi-head. This causes 977 * us confusion instead, especially on the systems where both 978 * functions have the same PCI-ID! 979 */ 980 if (PCI_FUNC(pdev->devfn)) 981 return -ENODEV; 982 983 /* 984 * apple-gmux is needed on dual GPU MacBook Pro 985 * to probe the panel if we're the inactive GPU. 986 */ 987 if (vga_switcheroo_client_probe_defer(pdev)) 988 return -EPROBE_DEFER; 989 990 err = i915_driver_probe(pdev, ent); 991 if (err) 992 return err; 993 994 if (i915_inject_probe_failure(pci_get_drvdata(pdev))) { 995 i915_pci_remove(pdev); 996 return -ENODEV; 997 } 998 999 err = i915_live_selftests(pdev); 1000 if (err) { 1001 i915_pci_remove(pdev); 1002 return err > 0 ? -ENOTTY : err; 1003 } 1004 1005 err = i915_perf_selftests(pdev); 1006 if (err) { 1007 i915_pci_remove(pdev); 1008 return err > 0 ? -ENOTTY : err; 1009 } 1010 1011 return 0; 1012 } 1013 1014 static struct pci_driver i915_pci_driver = { 1015 .name = DRIVER_NAME, 1016 .id_table = pciidlist, 1017 .probe = i915_pci_probe, 1018 .remove = i915_pci_remove, 1019 .driver.pm = &i915_pm_ops, 1020 }; 1021 1022 static int __init i915_init(void) 1023 { 1024 bool use_kms = true; 1025 int err; 1026 1027 err = i915_globals_init(); 1028 if (err) 1029 return err; 1030 1031 err = i915_mock_selftests(); 1032 if (err) 1033 return err > 0 ? 0 : err; 1034 1035 /* 1036 * Enable KMS by default, unless explicitly overriden by 1037 * either the i915.modeset prarameter or by the 1038 * vga_text_mode_force boot option. 1039 */ 1040 1041 if (i915_modparams.modeset == 0) 1042 use_kms = false; 1043 1044 if (vgacon_text_force() && i915_modparams.modeset == -1) 1045 use_kms = false; 1046 1047 if (!use_kms) { 1048 /* Silently fail loading to not upset userspace. */ 1049 DRM_DEBUG_DRIVER("KMS disabled.\n"); 1050 return 0; 1051 } 1052 1053 err = pci_register_driver(&i915_pci_driver); 1054 if (err) 1055 return err; 1056 1057 i915_perf_sysctl_register(); 1058 return 0; 1059 } 1060 1061 static void __exit i915_exit(void) 1062 { 1063 if (!i915_pci_driver.driver.owner) 1064 return; 1065 1066 i915_perf_sysctl_unregister(); 1067 pci_unregister_driver(&i915_pci_driver); 1068 i915_globals_exit(); 1069 } 1070 1071 module_init(i915_init); 1072 module_exit(i915_exit); 1073 1074 MODULE_AUTHOR("Tungsten Graphics, Inc."); 1075 MODULE_AUTHOR("Intel Corporation"); 1076 1077 MODULE_DESCRIPTION(DRIVER_DESC); 1078 MODULE_LICENSE("GPL and additional rights"); 1079