1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/console.h> 26 #include <linux/vgaarb.h> 27 #include <linux/vga_switcheroo.h> 28 29 #include <drm/drm_drv.h> 30 31 #include "i915_drv.h" 32 #include "i915_globals.h" 33 #include "i915_selftest.h" 34 #include "intel_fbdev.h" 35 36 #define PLATFORM(x) .platform = (x) 37 #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1) 38 39 #define I845_PIPE_OFFSETS \ 40 .pipe_offsets = { \ 41 [TRANSCODER_A] = PIPE_A_OFFSET, \ 42 }, \ 43 .trans_offsets = { \ 44 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 45 } 46 47 #define I9XX_PIPE_OFFSETS \ 48 .pipe_offsets = { \ 49 [TRANSCODER_A] = PIPE_A_OFFSET, \ 50 [TRANSCODER_B] = PIPE_B_OFFSET, \ 51 }, \ 52 .trans_offsets = { \ 53 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 54 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 55 } 56 57 #define IVB_PIPE_OFFSETS \ 58 .pipe_offsets = { \ 59 [TRANSCODER_A] = PIPE_A_OFFSET, \ 60 [TRANSCODER_B] = PIPE_B_OFFSET, \ 61 [TRANSCODER_C] = PIPE_C_OFFSET, \ 62 }, \ 63 .trans_offsets = { \ 64 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 65 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 66 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 67 } 68 69 #define HSW_PIPE_OFFSETS \ 70 .pipe_offsets = { \ 71 [TRANSCODER_A] = PIPE_A_OFFSET, \ 72 [TRANSCODER_B] = PIPE_B_OFFSET, \ 73 [TRANSCODER_C] = PIPE_C_OFFSET, \ 74 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 75 }, \ 76 .trans_offsets = { \ 77 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 78 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 79 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 80 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 81 } 82 83 #define CHV_PIPE_OFFSETS \ 84 .pipe_offsets = { \ 85 [TRANSCODER_A] = PIPE_A_OFFSET, \ 86 [TRANSCODER_B] = PIPE_B_OFFSET, \ 87 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \ 88 }, \ 89 .trans_offsets = { \ 90 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 91 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 92 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \ 93 } 94 95 #define I845_CURSOR_OFFSETS \ 96 .cursor_offsets = { \ 97 [PIPE_A] = CURSOR_A_OFFSET, \ 98 } 99 100 #define I9XX_CURSOR_OFFSETS \ 101 .cursor_offsets = { \ 102 [PIPE_A] = CURSOR_A_OFFSET, \ 103 [PIPE_B] = CURSOR_B_OFFSET, \ 104 } 105 106 #define CHV_CURSOR_OFFSETS \ 107 .cursor_offsets = { \ 108 [PIPE_A] = CURSOR_A_OFFSET, \ 109 [PIPE_B] = CURSOR_B_OFFSET, \ 110 [PIPE_C] = CHV_CURSOR_C_OFFSET, \ 111 } 112 113 #define IVB_CURSOR_OFFSETS \ 114 .cursor_offsets = { \ 115 [PIPE_A] = CURSOR_A_OFFSET, \ 116 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 117 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 118 } 119 120 #define I9XX_COLORS \ 121 .color = { .gamma_lut_size = 256 } 122 #define I965_COLORS \ 123 .color = { .gamma_lut_size = 129, \ 124 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 125 } 126 #define ILK_COLORS \ 127 .color = { .gamma_lut_size = 1024 } 128 #define IVB_COLORS \ 129 .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 } 130 #define CHV_COLORS \ 131 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \ 132 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 133 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 134 } 135 #define GLK_COLORS \ 136 .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \ 137 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 138 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 139 } 140 141 /* Keep in gen based order, and chronological order within a gen */ 142 143 #define GEN_DEFAULT_PAGE_SIZES \ 144 .page_sizes = I915_GTT_PAGE_SIZE_4K 145 146 #define I830_FEATURES \ 147 GEN(2), \ 148 .is_mobile = 1, \ 149 .num_pipes = 2, \ 150 .display.has_overlay = 1, \ 151 .display.cursor_needs_physical = 1, \ 152 .display.overlay_needs_physical = 1, \ 153 .display.has_gmch = 1, \ 154 .gpu_reset_clobbers_display = true, \ 155 .hws_needs_physical = 1, \ 156 .unfenced_needs_alignment = 1, \ 157 .engine_mask = BIT(RCS0), \ 158 .has_snoop = true, \ 159 .has_coherent_ggtt = false, \ 160 I9XX_PIPE_OFFSETS, \ 161 I9XX_CURSOR_OFFSETS, \ 162 I9XX_COLORS, \ 163 GEN_DEFAULT_PAGE_SIZES 164 165 #define I845_FEATURES \ 166 GEN(2), \ 167 .num_pipes = 1, \ 168 .display.has_overlay = 1, \ 169 .display.overlay_needs_physical = 1, \ 170 .display.has_gmch = 1, \ 171 .gpu_reset_clobbers_display = true, \ 172 .hws_needs_physical = 1, \ 173 .unfenced_needs_alignment = 1, \ 174 .engine_mask = BIT(RCS0), \ 175 .has_snoop = true, \ 176 .has_coherent_ggtt = false, \ 177 I845_PIPE_OFFSETS, \ 178 I845_CURSOR_OFFSETS, \ 179 I9XX_COLORS, \ 180 GEN_DEFAULT_PAGE_SIZES 181 182 static const struct intel_device_info intel_i830_info = { 183 I830_FEATURES, 184 PLATFORM(INTEL_I830), 185 }; 186 187 static const struct intel_device_info intel_i845g_info = { 188 I845_FEATURES, 189 PLATFORM(INTEL_I845G), 190 }; 191 192 static const struct intel_device_info intel_i85x_info = { 193 I830_FEATURES, 194 PLATFORM(INTEL_I85X), 195 .display.has_fbc = 1, 196 }; 197 198 static const struct intel_device_info intel_i865g_info = { 199 I845_FEATURES, 200 PLATFORM(INTEL_I865G), 201 }; 202 203 #define GEN3_FEATURES \ 204 GEN(3), \ 205 .num_pipes = 2, \ 206 .display.has_gmch = 1, \ 207 .gpu_reset_clobbers_display = true, \ 208 .engine_mask = BIT(RCS0), \ 209 .has_snoop = true, \ 210 .has_coherent_ggtt = true, \ 211 I9XX_PIPE_OFFSETS, \ 212 I9XX_CURSOR_OFFSETS, \ 213 I9XX_COLORS, \ 214 GEN_DEFAULT_PAGE_SIZES 215 216 static const struct intel_device_info intel_i915g_info = { 217 GEN3_FEATURES, 218 PLATFORM(INTEL_I915G), 219 .has_coherent_ggtt = false, 220 .display.cursor_needs_physical = 1, 221 .display.has_overlay = 1, 222 .display.overlay_needs_physical = 1, 223 .hws_needs_physical = 1, 224 .unfenced_needs_alignment = 1, 225 }; 226 227 static const struct intel_device_info intel_i915gm_info = { 228 GEN3_FEATURES, 229 PLATFORM(INTEL_I915GM), 230 .is_mobile = 1, 231 .display.cursor_needs_physical = 1, 232 .display.has_overlay = 1, 233 .display.overlay_needs_physical = 1, 234 .display.supports_tv = 1, 235 .display.has_fbc = 1, 236 .hws_needs_physical = 1, 237 .unfenced_needs_alignment = 1, 238 }; 239 240 static const struct intel_device_info intel_i945g_info = { 241 GEN3_FEATURES, 242 PLATFORM(INTEL_I945G), 243 .display.has_hotplug = 1, 244 .display.cursor_needs_physical = 1, 245 .display.has_overlay = 1, 246 .display.overlay_needs_physical = 1, 247 .hws_needs_physical = 1, 248 .unfenced_needs_alignment = 1, 249 }; 250 251 static const struct intel_device_info intel_i945gm_info = { 252 GEN3_FEATURES, 253 PLATFORM(INTEL_I945GM), 254 .is_mobile = 1, 255 .display.has_hotplug = 1, 256 .display.cursor_needs_physical = 1, 257 .display.has_overlay = 1, 258 .display.overlay_needs_physical = 1, 259 .display.supports_tv = 1, 260 .display.has_fbc = 1, 261 .hws_needs_physical = 1, 262 .unfenced_needs_alignment = 1, 263 }; 264 265 static const struct intel_device_info intel_g33_info = { 266 GEN3_FEATURES, 267 PLATFORM(INTEL_G33), 268 .display.has_hotplug = 1, 269 .display.has_overlay = 1, 270 }; 271 272 static const struct intel_device_info intel_pineview_g_info = { 273 GEN3_FEATURES, 274 PLATFORM(INTEL_PINEVIEW), 275 .display.has_hotplug = 1, 276 .display.has_overlay = 1, 277 }; 278 279 static const struct intel_device_info intel_pineview_m_info = { 280 GEN3_FEATURES, 281 PLATFORM(INTEL_PINEVIEW), 282 .is_mobile = 1, 283 .display.has_hotplug = 1, 284 .display.has_overlay = 1, 285 }; 286 287 #define GEN4_FEATURES \ 288 GEN(4), \ 289 .num_pipes = 2, \ 290 .display.has_hotplug = 1, \ 291 .display.has_gmch = 1, \ 292 .gpu_reset_clobbers_display = true, \ 293 .engine_mask = BIT(RCS0), \ 294 .has_snoop = true, \ 295 .has_coherent_ggtt = true, \ 296 I9XX_PIPE_OFFSETS, \ 297 I9XX_CURSOR_OFFSETS, \ 298 I965_COLORS, \ 299 GEN_DEFAULT_PAGE_SIZES 300 301 static const struct intel_device_info intel_i965g_info = { 302 GEN4_FEATURES, 303 PLATFORM(INTEL_I965G), 304 .display.has_overlay = 1, 305 .hws_needs_physical = 1, 306 .has_snoop = false, 307 }; 308 309 static const struct intel_device_info intel_i965gm_info = { 310 GEN4_FEATURES, 311 PLATFORM(INTEL_I965GM), 312 .is_mobile = 1, 313 .display.has_fbc = 1, 314 .display.has_overlay = 1, 315 .display.supports_tv = 1, 316 .hws_needs_physical = 1, 317 .has_snoop = false, 318 }; 319 320 static const struct intel_device_info intel_g45_info = { 321 GEN4_FEATURES, 322 PLATFORM(INTEL_G45), 323 .engine_mask = BIT(RCS0) | BIT(VCS0), 324 .gpu_reset_clobbers_display = false, 325 }; 326 327 static const struct intel_device_info intel_gm45_info = { 328 GEN4_FEATURES, 329 PLATFORM(INTEL_GM45), 330 .is_mobile = 1, 331 .display.has_fbc = 1, 332 .display.supports_tv = 1, 333 .engine_mask = BIT(RCS0) | BIT(VCS0), 334 .gpu_reset_clobbers_display = false, 335 }; 336 337 #define GEN5_FEATURES \ 338 GEN(5), \ 339 .num_pipes = 2, \ 340 .display.has_hotplug = 1, \ 341 .engine_mask = BIT(RCS0) | BIT(VCS0), \ 342 .has_snoop = true, \ 343 .has_coherent_ggtt = true, \ 344 /* ilk does support rc6, but we do not implement [power] contexts */ \ 345 .has_rc6 = 0, \ 346 I9XX_PIPE_OFFSETS, \ 347 I9XX_CURSOR_OFFSETS, \ 348 ILK_COLORS, \ 349 GEN_DEFAULT_PAGE_SIZES 350 351 static const struct intel_device_info intel_ironlake_d_info = { 352 GEN5_FEATURES, 353 PLATFORM(INTEL_IRONLAKE), 354 }; 355 356 static const struct intel_device_info intel_ironlake_m_info = { 357 GEN5_FEATURES, 358 PLATFORM(INTEL_IRONLAKE), 359 .is_mobile = 1, 360 .display.has_fbc = 1, 361 }; 362 363 #define GEN6_FEATURES \ 364 GEN(6), \ 365 .num_pipes = 2, \ 366 .display.has_hotplug = 1, \ 367 .display.has_fbc = 1, \ 368 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ 369 .has_coherent_ggtt = true, \ 370 .has_llc = 1, \ 371 .has_rc6 = 1, \ 372 .has_rc6p = 1, \ 373 .has_rps = true, \ 374 .ppgtt_type = INTEL_PPGTT_ALIASING, \ 375 .ppgtt_size = 31, \ 376 I9XX_PIPE_OFFSETS, \ 377 I9XX_CURSOR_OFFSETS, \ 378 ILK_COLORS, \ 379 GEN_DEFAULT_PAGE_SIZES 380 381 #define SNB_D_PLATFORM \ 382 GEN6_FEATURES, \ 383 PLATFORM(INTEL_SANDYBRIDGE) 384 385 static const struct intel_device_info intel_sandybridge_d_gt1_info = { 386 SNB_D_PLATFORM, 387 .gt = 1, 388 }; 389 390 static const struct intel_device_info intel_sandybridge_d_gt2_info = { 391 SNB_D_PLATFORM, 392 .gt = 2, 393 }; 394 395 #define SNB_M_PLATFORM \ 396 GEN6_FEATURES, \ 397 PLATFORM(INTEL_SANDYBRIDGE), \ 398 .is_mobile = 1 399 400 401 static const struct intel_device_info intel_sandybridge_m_gt1_info = { 402 SNB_M_PLATFORM, 403 .gt = 1, 404 }; 405 406 static const struct intel_device_info intel_sandybridge_m_gt2_info = { 407 SNB_M_PLATFORM, 408 .gt = 2, 409 }; 410 411 #define GEN7_FEATURES \ 412 GEN(7), \ 413 .num_pipes = 3, \ 414 .display.has_hotplug = 1, \ 415 .display.has_fbc = 1, \ 416 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ 417 .has_coherent_ggtt = true, \ 418 .has_llc = 1, \ 419 .has_rc6 = 1, \ 420 .has_rc6p = 1, \ 421 .has_rps = true, \ 422 .ppgtt_type = INTEL_PPGTT_FULL, \ 423 .ppgtt_size = 31, \ 424 IVB_PIPE_OFFSETS, \ 425 IVB_CURSOR_OFFSETS, \ 426 IVB_COLORS, \ 427 GEN_DEFAULT_PAGE_SIZES 428 429 #define IVB_D_PLATFORM \ 430 GEN7_FEATURES, \ 431 PLATFORM(INTEL_IVYBRIDGE), \ 432 .has_l3_dpf = 1 433 434 static const struct intel_device_info intel_ivybridge_d_gt1_info = { 435 IVB_D_PLATFORM, 436 .gt = 1, 437 }; 438 439 static const struct intel_device_info intel_ivybridge_d_gt2_info = { 440 IVB_D_PLATFORM, 441 .gt = 2, 442 }; 443 444 #define IVB_M_PLATFORM \ 445 GEN7_FEATURES, \ 446 PLATFORM(INTEL_IVYBRIDGE), \ 447 .is_mobile = 1, \ 448 .has_l3_dpf = 1 449 450 static const struct intel_device_info intel_ivybridge_m_gt1_info = { 451 IVB_M_PLATFORM, 452 .gt = 1, 453 }; 454 455 static const struct intel_device_info intel_ivybridge_m_gt2_info = { 456 IVB_M_PLATFORM, 457 .gt = 2, 458 }; 459 460 static const struct intel_device_info intel_ivybridge_q_info = { 461 GEN7_FEATURES, 462 PLATFORM(INTEL_IVYBRIDGE), 463 .gt = 2, 464 .num_pipes = 0, /* legal, last one wins */ 465 .has_l3_dpf = 1, 466 }; 467 468 static const struct intel_device_info intel_valleyview_info = { 469 PLATFORM(INTEL_VALLEYVIEW), 470 GEN(7), 471 .is_lp = 1, 472 .num_pipes = 2, 473 .has_runtime_pm = 1, 474 .has_rc6 = 1, 475 .has_rps = true, 476 .display.has_gmch = 1, 477 .display.has_hotplug = 1, 478 .ppgtt_type = INTEL_PPGTT_FULL, 479 .ppgtt_size = 31, 480 .has_snoop = true, 481 .has_coherent_ggtt = false, 482 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), 483 .display_mmio_offset = VLV_DISPLAY_BASE, 484 I9XX_PIPE_OFFSETS, 485 I9XX_CURSOR_OFFSETS, 486 I965_COLORS, 487 GEN_DEFAULT_PAGE_SIZES, 488 }; 489 490 #define G75_FEATURES \ 491 GEN7_FEATURES, \ 492 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ 493 .display.has_ddi = 1, \ 494 .has_fpga_dbg = 1, \ 495 .display.has_psr = 1, \ 496 .display.has_dp_mst = 1, \ 497 .has_rc6p = 0 /* RC6p removed-by HSW */, \ 498 HSW_PIPE_OFFSETS, \ 499 .has_runtime_pm = 1 500 501 #define HSW_PLATFORM \ 502 G75_FEATURES, \ 503 PLATFORM(INTEL_HASWELL), \ 504 .has_l3_dpf = 1 505 506 static const struct intel_device_info intel_haswell_gt1_info = { 507 HSW_PLATFORM, 508 .gt = 1, 509 }; 510 511 static const struct intel_device_info intel_haswell_gt2_info = { 512 HSW_PLATFORM, 513 .gt = 2, 514 }; 515 516 static const struct intel_device_info intel_haswell_gt3_info = { 517 HSW_PLATFORM, 518 .gt = 3, 519 }; 520 521 #define GEN8_FEATURES \ 522 G75_FEATURES, \ 523 GEN(8), \ 524 .page_sizes = I915_GTT_PAGE_SIZE_4K | \ 525 I915_GTT_PAGE_SIZE_2M, \ 526 .has_logical_ring_contexts = 1, \ 527 .ppgtt_type = INTEL_PPGTT_FULL, \ 528 .ppgtt_size = 48, \ 529 .has_64bit_reloc = 1, \ 530 .has_reset_engine = 1 531 532 #define BDW_PLATFORM \ 533 GEN8_FEATURES, \ 534 PLATFORM(INTEL_BROADWELL) 535 536 static const struct intel_device_info intel_broadwell_gt1_info = { 537 BDW_PLATFORM, 538 .gt = 1, 539 }; 540 541 static const struct intel_device_info intel_broadwell_gt2_info = { 542 BDW_PLATFORM, 543 .gt = 2, 544 }; 545 546 static const struct intel_device_info intel_broadwell_rsvd_info = { 547 BDW_PLATFORM, 548 .gt = 3, 549 /* According to the device ID those devices are GT3, they were 550 * previously treated as not GT3, keep it like that. 551 */ 552 }; 553 554 static const struct intel_device_info intel_broadwell_gt3_info = { 555 BDW_PLATFORM, 556 .gt = 3, 557 .engine_mask = 558 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 559 }; 560 561 static const struct intel_device_info intel_cherryview_info = { 562 PLATFORM(INTEL_CHERRYVIEW), 563 GEN(8), 564 .num_pipes = 3, 565 .display.has_hotplug = 1, 566 .is_lp = 1, 567 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), 568 .has_64bit_reloc = 1, 569 .has_runtime_pm = 1, 570 .has_rc6 = 1, 571 .has_rps = true, 572 .has_logical_ring_contexts = 1, 573 .display.has_gmch = 1, 574 .ppgtt_type = INTEL_PPGTT_FULL, 575 .ppgtt_size = 32, 576 .has_reset_engine = 1, 577 .has_snoop = true, 578 .has_coherent_ggtt = false, 579 .display_mmio_offset = VLV_DISPLAY_BASE, 580 CHV_PIPE_OFFSETS, 581 CHV_CURSOR_OFFSETS, 582 CHV_COLORS, 583 GEN_DEFAULT_PAGE_SIZES, 584 }; 585 586 #define GEN9_DEFAULT_PAGE_SIZES \ 587 .page_sizes = I915_GTT_PAGE_SIZE_4K | \ 588 I915_GTT_PAGE_SIZE_64K | \ 589 I915_GTT_PAGE_SIZE_2M 590 591 #define GEN9_FEATURES \ 592 GEN8_FEATURES, \ 593 GEN(9), \ 594 GEN9_DEFAULT_PAGE_SIZES, \ 595 .has_logical_ring_preemption = 1, \ 596 .display.has_csr = 1, \ 597 .has_guc = 1, \ 598 .display.has_ipc = 1, \ 599 .ddb_size = 896 600 601 #define SKL_PLATFORM \ 602 GEN9_FEATURES, \ 603 PLATFORM(INTEL_SKYLAKE) 604 605 static const struct intel_device_info intel_skylake_gt1_info = { 606 SKL_PLATFORM, 607 .gt = 1, 608 }; 609 610 static const struct intel_device_info intel_skylake_gt2_info = { 611 SKL_PLATFORM, 612 .gt = 2, 613 }; 614 615 #define SKL_GT3_PLUS_PLATFORM \ 616 SKL_PLATFORM, \ 617 .engine_mask = \ 618 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1) 619 620 621 static const struct intel_device_info intel_skylake_gt3_info = { 622 SKL_GT3_PLUS_PLATFORM, 623 .gt = 3, 624 }; 625 626 static const struct intel_device_info intel_skylake_gt4_info = { 627 SKL_GT3_PLUS_PLATFORM, 628 .gt = 4, 629 }; 630 631 #define GEN9_LP_FEATURES \ 632 GEN(9), \ 633 .is_lp = 1, \ 634 .display.has_hotplug = 1, \ 635 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ 636 .num_pipes = 3, \ 637 .has_64bit_reloc = 1, \ 638 .display.has_ddi = 1, \ 639 .has_fpga_dbg = 1, \ 640 .display.has_fbc = 1, \ 641 .display.has_psr = 1, \ 642 .has_runtime_pm = 1, \ 643 .display.has_csr = 1, \ 644 .has_rc6 = 1, \ 645 .has_rps = true, \ 646 .display.has_dp_mst = 1, \ 647 .has_logical_ring_contexts = 1, \ 648 .has_logical_ring_preemption = 1, \ 649 .has_guc = 1, \ 650 .ppgtt_type = INTEL_PPGTT_FULL, \ 651 .ppgtt_size = 48, \ 652 .has_reset_engine = 1, \ 653 .has_snoop = true, \ 654 .has_coherent_ggtt = false, \ 655 .display.has_ipc = 1, \ 656 HSW_PIPE_OFFSETS, \ 657 IVB_CURSOR_OFFSETS, \ 658 IVB_COLORS, \ 659 GEN9_DEFAULT_PAGE_SIZES 660 661 static const struct intel_device_info intel_broxton_info = { 662 GEN9_LP_FEATURES, 663 PLATFORM(INTEL_BROXTON), 664 .ddb_size = 512, 665 }; 666 667 static const struct intel_device_info intel_geminilake_info = { 668 GEN9_LP_FEATURES, 669 PLATFORM(INTEL_GEMINILAKE), 670 .ddb_size = 1024, 671 GLK_COLORS, 672 }; 673 674 #define KBL_PLATFORM \ 675 GEN9_FEATURES, \ 676 PLATFORM(INTEL_KABYLAKE) 677 678 static const struct intel_device_info intel_kabylake_gt1_info = { 679 KBL_PLATFORM, 680 .gt = 1, 681 }; 682 683 static const struct intel_device_info intel_kabylake_gt2_info = { 684 KBL_PLATFORM, 685 .gt = 2, 686 }; 687 688 static const struct intel_device_info intel_kabylake_gt3_info = { 689 KBL_PLATFORM, 690 .gt = 3, 691 .engine_mask = 692 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 693 }; 694 695 #define CFL_PLATFORM \ 696 GEN9_FEATURES, \ 697 PLATFORM(INTEL_COFFEELAKE) 698 699 static const struct intel_device_info intel_coffeelake_gt1_info = { 700 CFL_PLATFORM, 701 .gt = 1, 702 }; 703 704 static const struct intel_device_info intel_coffeelake_gt2_info = { 705 CFL_PLATFORM, 706 .gt = 2, 707 }; 708 709 static const struct intel_device_info intel_coffeelake_gt3_info = { 710 CFL_PLATFORM, 711 .gt = 3, 712 .engine_mask = 713 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 714 }; 715 716 #define GEN10_FEATURES \ 717 GEN9_FEATURES, \ 718 GEN(10), \ 719 .ddb_size = 1024, \ 720 .has_coherent_ggtt = false, \ 721 GLK_COLORS 722 723 static const struct intel_device_info intel_cannonlake_info = { 724 GEN10_FEATURES, 725 PLATFORM(INTEL_CANNONLAKE), 726 .gt = 2, 727 }; 728 729 #define GEN11_FEATURES \ 730 GEN10_FEATURES, \ 731 .pipe_offsets = { \ 732 [TRANSCODER_A] = PIPE_A_OFFSET, \ 733 [TRANSCODER_B] = PIPE_B_OFFSET, \ 734 [TRANSCODER_C] = PIPE_C_OFFSET, \ 735 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 736 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 737 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 738 }, \ 739 .trans_offsets = { \ 740 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 741 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 742 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 743 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 744 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 745 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 746 }, \ 747 GEN(11), \ 748 .ddb_size = 2048, \ 749 .has_logical_ring_elsq = 1, \ 750 .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024 } 751 752 static const struct intel_device_info intel_icelake_11_info = { 753 GEN11_FEATURES, 754 PLATFORM(INTEL_ICELAKE), 755 .engine_mask = 756 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 757 }; 758 759 static const struct intel_device_info intel_elkhartlake_info = { 760 GEN11_FEATURES, 761 PLATFORM(INTEL_ELKHARTLAKE), 762 .is_alpha_support = 1, 763 .engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0), 764 .ppgtt_size = 36, 765 }; 766 767 #undef GEN 768 #undef PLATFORM 769 770 /* 771 * Make sure any device matches here are from most specific to most 772 * general. For example, since the Quanta match is based on the subsystem 773 * and subvendor IDs, we need it to come before the more general IVB 774 * PCI ID matches, otherwise we'll use the wrong info struct above. 775 */ 776 static const struct pci_device_id pciidlist[] = { 777 INTEL_I830_IDS(&intel_i830_info), 778 INTEL_I845G_IDS(&intel_i845g_info), 779 INTEL_I85X_IDS(&intel_i85x_info), 780 INTEL_I865G_IDS(&intel_i865g_info), 781 INTEL_I915G_IDS(&intel_i915g_info), 782 INTEL_I915GM_IDS(&intel_i915gm_info), 783 INTEL_I945G_IDS(&intel_i945g_info), 784 INTEL_I945GM_IDS(&intel_i945gm_info), 785 INTEL_I965G_IDS(&intel_i965g_info), 786 INTEL_G33_IDS(&intel_g33_info), 787 INTEL_I965GM_IDS(&intel_i965gm_info), 788 INTEL_GM45_IDS(&intel_gm45_info), 789 INTEL_G45_IDS(&intel_g45_info), 790 INTEL_PINEVIEW_G_IDS(&intel_pineview_g_info), 791 INTEL_PINEVIEW_M_IDS(&intel_pineview_m_info), 792 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), 793 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), 794 INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info), 795 INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info), 796 INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info), 797 INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info), 798 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ 799 INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info), 800 INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info), 801 INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info), 802 INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info), 803 INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info), 804 INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info), 805 INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info), 806 INTEL_VLV_IDS(&intel_valleyview_info), 807 INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info), 808 INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info), 809 INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info), 810 INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info), 811 INTEL_CHV_IDS(&intel_cherryview_info), 812 INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info), 813 INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info), 814 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), 815 INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info), 816 INTEL_BXT_IDS(&intel_broxton_info), 817 INTEL_GLK_IDS(&intel_geminilake_info), 818 INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info), 819 INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info), 820 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info), 821 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info), 822 INTEL_AML_KBL_GT2_IDS(&intel_kabylake_gt2_info), 823 INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info), 824 INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info), 825 INTEL_CFL_H_GT1_IDS(&intel_coffeelake_gt1_info), 826 INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info), 827 INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info), 828 INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info), 829 INTEL_WHL_U_GT1_IDS(&intel_coffeelake_gt1_info), 830 INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info), 831 INTEL_AML_CFL_GT2_IDS(&intel_coffeelake_gt2_info), 832 INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info), 833 INTEL_CML_GT1_IDS(&intel_coffeelake_gt1_info), 834 INTEL_CML_GT2_IDS(&intel_coffeelake_gt2_info), 835 INTEL_CNL_IDS(&intel_cannonlake_info), 836 INTEL_ICL_11_IDS(&intel_icelake_11_info), 837 INTEL_EHL_IDS(&intel_elkhartlake_info), 838 {0, 0, 0} 839 }; 840 MODULE_DEVICE_TABLE(pci, pciidlist); 841 842 static void i915_pci_remove(struct pci_dev *pdev) 843 { 844 struct drm_device *dev; 845 846 dev = pci_get_drvdata(pdev); 847 if (!dev) /* driver load aborted, nothing to cleanup */ 848 return; 849 850 i915_driver_unload(dev); 851 drm_dev_put(dev); 852 853 pci_set_drvdata(pdev, NULL); 854 } 855 856 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 857 { 858 struct intel_device_info *intel_info = 859 (struct intel_device_info *) ent->driver_data; 860 int err; 861 862 if (IS_ALPHA_SUPPORT(intel_info) && !i915_modparams.alpha_support) { 863 DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n" 864 "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n" 865 "to enable support in this kernel version, or check for kernel updates.\n"); 866 return -ENODEV; 867 } 868 869 /* Only bind to function 0 of the device. Early generations 870 * used function 1 as a placeholder for multi-head. This causes 871 * us confusion instead, especially on the systems where both 872 * functions have the same PCI-ID! 873 */ 874 if (PCI_FUNC(pdev->devfn)) 875 return -ENODEV; 876 877 /* 878 * apple-gmux is needed on dual GPU MacBook Pro 879 * to probe the panel if we're the inactive GPU. 880 */ 881 if (vga_switcheroo_client_probe_defer(pdev)) 882 return -EPROBE_DEFER; 883 884 err = i915_driver_load(pdev, ent); 885 if (err) 886 return err; 887 888 if (i915_inject_load_failure()) { 889 i915_pci_remove(pdev); 890 return -ENODEV; 891 } 892 893 err = i915_live_selftests(pdev); 894 if (err) { 895 i915_pci_remove(pdev); 896 return err > 0 ? -ENOTTY : err; 897 } 898 899 return 0; 900 } 901 902 static struct pci_driver i915_pci_driver = { 903 .name = DRIVER_NAME, 904 .id_table = pciidlist, 905 .probe = i915_pci_probe, 906 .remove = i915_pci_remove, 907 .driver.pm = &i915_pm_ops, 908 }; 909 910 static int __init i915_init(void) 911 { 912 bool use_kms = true; 913 int err; 914 915 err = i915_globals_init(); 916 if (err) 917 return err; 918 919 err = i915_mock_selftests(); 920 if (err) 921 return err > 0 ? 0 : err; 922 923 /* 924 * Enable KMS by default, unless explicitly overriden by 925 * either the i915.modeset prarameter or by the 926 * vga_text_mode_force boot option. 927 */ 928 929 if (i915_modparams.modeset == 0) 930 use_kms = false; 931 932 if (vgacon_text_force() && i915_modparams.modeset == -1) 933 use_kms = false; 934 935 if (!use_kms) { 936 /* Silently fail loading to not upset userspace. */ 937 DRM_DEBUG_DRIVER("KMS disabled.\n"); 938 return 0; 939 } 940 941 return pci_register_driver(&i915_pci_driver); 942 } 943 944 static void __exit i915_exit(void) 945 { 946 if (!i915_pci_driver.driver.owner) 947 return; 948 949 pci_unregister_driver(&i915_pci_driver); 950 i915_globals_exit(); 951 } 952 953 module_init(i915_init); 954 module_exit(i915_exit); 955 956 MODULE_AUTHOR("Tungsten Graphics, Inc."); 957 MODULE_AUTHOR("Intel Corporation"); 958 959 MODULE_DESCRIPTION(DRIVER_DESC); 960 MODULE_LICENSE("GPL and additional rights"); 961