1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <drm/drm_drv.h> 26 #include <drm/i915_pciids.h> 27 28 #include "i915_driver.h" 29 #include "i915_drv.h" 30 #include "i915_pci.h" 31 32 #define PLATFORM(x) .platform = (x) 33 #define GEN(x) \ 34 .graphics.ver = (x), \ 35 .media.ver = (x), \ 36 .display.ver = (x) 37 38 #define I845_PIPE_OFFSETS \ 39 .pipe_offsets = { \ 40 [TRANSCODER_A] = PIPE_A_OFFSET, \ 41 }, \ 42 .trans_offsets = { \ 43 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 44 } 45 46 #define I9XX_PIPE_OFFSETS \ 47 .pipe_offsets = { \ 48 [TRANSCODER_A] = PIPE_A_OFFSET, \ 49 [TRANSCODER_B] = PIPE_B_OFFSET, \ 50 }, \ 51 .trans_offsets = { \ 52 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 53 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 54 } 55 56 #define IVB_PIPE_OFFSETS \ 57 .pipe_offsets = { \ 58 [TRANSCODER_A] = PIPE_A_OFFSET, \ 59 [TRANSCODER_B] = PIPE_B_OFFSET, \ 60 [TRANSCODER_C] = PIPE_C_OFFSET, \ 61 }, \ 62 .trans_offsets = { \ 63 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 64 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 65 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 66 } 67 68 #define HSW_PIPE_OFFSETS \ 69 .pipe_offsets = { \ 70 [TRANSCODER_A] = PIPE_A_OFFSET, \ 71 [TRANSCODER_B] = PIPE_B_OFFSET, \ 72 [TRANSCODER_C] = PIPE_C_OFFSET, \ 73 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 74 }, \ 75 .trans_offsets = { \ 76 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 77 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 78 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 79 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 80 } 81 82 #define CHV_PIPE_OFFSETS \ 83 .pipe_offsets = { \ 84 [TRANSCODER_A] = PIPE_A_OFFSET, \ 85 [TRANSCODER_B] = PIPE_B_OFFSET, \ 86 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \ 87 }, \ 88 .trans_offsets = { \ 89 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 90 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 91 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \ 92 } 93 94 #define I845_CURSOR_OFFSETS \ 95 .cursor_offsets = { \ 96 [PIPE_A] = CURSOR_A_OFFSET, \ 97 } 98 99 #define I9XX_CURSOR_OFFSETS \ 100 .cursor_offsets = { \ 101 [PIPE_A] = CURSOR_A_OFFSET, \ 102 [PIPE_B] = CURSOR_B_OFFSET, \ 103 } 104 105 #define CHV_CURSOR_OFFSETS \ 106 .cursor_offsets = { \ 107 [PIPE_A] = CURSOR_A_OFFSET, \ 108 [PIPE_B] = CURSOR_B_OFFSET, \ 109 [PIPE_C] = CHV_CURSOR_C_OFFSET, \ 110 } 111 112 #define IVB_CURSOR_OFFSETS \ 113 .cursor_offsets = { \ 114 [PIPE_A] = CURSOR_A_OFFSET, \ 115 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 116 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 117 } 118 119 #define TGL_CURSOR_OFFSETS \ 120 .cursor_offsets = { \ 121 [PIPE_A] = CURSOR_A_OFFSET, \ 122 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 123 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 124 [PIPE_D] = TGL_CURSOR_D_OFFSET, \ 125 } 126 127 #define I9XX_COLORS \ 128 .color = { .gamma_lut_size = 256 } 129 #define I965_COLORS \ 130 .color = { .gamma_lut_size = 129, \ 131 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 132 } 133 #define ILK_COLORS \ 134 .color = { .gamma_lut_size = 1024 } 135 #define IVB_COLORS \ 136 .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 } 137 #define CHV_COLORS \ 138 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \ 139 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 140 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 141 } 142 #define GLK_COLORS \ 143 .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \ 144 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 145 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 146 } 147 #define ICL_COLORS \ 148 .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145, \ 149 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 150 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 151 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 152 } 153 154 /* Keep in gen based order, and chronological order within a gen */ 155 156 #define GEN_DEFAULT_PAGE_SIZES \ 157 .page_sizes = I915_GTT_PAGE_SIZE_4K 158 159 #define GEN_DEFAULT_REGIONS \ 160 .memory_regions = REGION_SMEM | REGION_STOLEN_SMEM 161 162 #define I830_FEATURES \ 163 GEN(2), \ 164 .is_mobile = 1, \ 165 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 166 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 167 .display.has_overlay = 1, \ 168 .display.cursor_needs_physical = 1, \ 169 .display.overlay_needs_physical = 1, \ 170 .display.has_gmch = 1, \ 171 .gpu_reset_clobbers_display = true, \ 172 .hws_needs_physical = 1, \ 173 .unfenced_needs_alignment = 1, \ 174 .platform_engine_mask = BIT(RCS0), \ 175 .has_snoop = true, \ 176 .has_coherent_ggtt = false, \ 177 .dma_mask_size = 32, \ 178 I9XX_PIPE_OFFSETS, \ 179 I9XX_CURSOR_OFFSETS, \ 180 I9XX_COLORS, \ 181 GEN_DEFAULT_PAGE_SIZES, \ 182 GEN_DEFAULT_REGIONS 183 184 #define I845_FEATURES \ 185 GEN(2), \ 186 .display.pipe_mask = BIT(PIPE_A), \ 187 .display.cpu_transcoder_mask = BIT(TRANSCODER_A), \ 188 .display.has_overlay = 1, \ 189 .display.overlay_needs_physical = 1, \ 190 .display.has_gmch = 1, \ 191 .gpu_reset_clobbers_display = true, \ 192 .hws_needs_physical = 1, \ 193 .unfenced_needs_alignment = 1, \ 194 .platform_engine_mask = BIT(RCS0), \ 195 .has_snoop = true, \ 196 .has_coherent_ggtt = false, \ 197 .dma_mask_size = 32, \ 198 I845_PIPE_OFFSETS, \ 199 I845_CURSOR_OFFSETS, \ 200 I9XX_COLORS, \ 201 GEN_DEFAULT_PAGE_SIZES, \ 202 GEN_DEFAULT_REGIONS 203 204 static const struct intel_device_info i830_info = { 205 I830_FEATURES, 206 PLATFORM(INTEL_I830), 207 }; 208 209 static const struct intel_device_info i845g_info = { 210 I845_FEATURES, 211 PLATFORM(INTEL_I845G), 212 }; 213 214 static const struct intel_device_info i85x_info = { 215 I830_FEATURES, 216 PLATFORM(INTEL_I85X), 217 .display.has_fbc = 1, 218 }; 219 220 static const struct intel_device_info i865g_info = { 221 I845_FEATURES, 222 PLATFORM(INTEL_I865G), 223 .display.has_fbc = 1, 224 }; 225 226 #define GEN3_FEATURES \ 227 GEN(3), \ 228 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 229 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 230 .display.has_gmch = 1, \ 231 .gpu_reset_clobbers_display = true, \ 232 .platform_engine_mask = BIT(RCS0), \ 233 .has_snoop = true, \ 234 .has_coherent_ggtt = true, \ 235 .dma_mask_size = 32, \ 236 I9XX_PIPE_OFFSETS, \ 237 I9XX_CURSOR_OFFSETS, \ 238 I9XX_COLORS, \ 239 GEN_DEFAULT_PAGE_SIZES, \ 240 GEN_DEFAULT_REGIONS 241 242 static const struct intel_device_info i915g_info = { 243 GEN3_FEATURES, 244 PLATFORM(INTEL_I915G), 245 .has_coherent_ggtt = false, 246 .display.cursor_needs_physical = 1, 247 .display.has_overlay = 1, 248 .display.overlay_needs_physical = 1, 249 .hws_needs_physical = 1, 250 .unfenced_needs_alignment = 1, 251 }; 252 253 static const struct intel_device_info i915gm_info = { 254 GEN3_FEATURES, 255 PLATFORM(INTEL_I915GM), 256 .is_mobile = 1, 257 .display.cursor_needs_physical = 1, 258 .display.has_overlay = 1, 259 .display.overlay_needs_physical = 1, 260 .display.supports_tv = 1, 261 .display.has_fbc = 1, 262 .hws_needs_physical = 1, 263 .unfenced_needs_alignment = 1, 264 }; 265 266 static const struct intel_device_info i945g_info = { 267 GEN3_FEATURES, 268 PLATFORM(INTEL_I945G), 269 .display.has_hotplug = 1, 270 .display.cursor_needs_physical = 1, 271 .display.has_overlay = 1, 272 .display.overlay_needs_physical = 1, 273 .hws_needs_physical = 1, 274 .unfenced_needs_alignment = 1, 275 }; 276 277 static const struct intel_device_info i945gm_info = { 278 GEN3_FEATURES, 279 PLATFORM(INTEL_I945GM), 280 .is_mobile = 1, 281 .display.has_hotplug = 1, 282 .display.cursor_needs_physical = 1, 283 .display.has_overlay = 1, 284 .display.overlay_needs_physical = 1, 285 .display.supports_tv = 1, 286 .display.has_fbc = 1, 287 .hws_needs_physical = 1, 288 .unfenced_needs_alignment = 1, 289 }; 290 291 static const struct intel_device_info g33_info = { 292 GEN3_FEATURES, 293 PLATFORM(INTEL_G33), 294 .display.has_hotplug = 1, 295 .display.has_overlay = 1, 296 .dma_mask_size = 36, 297 }; 298 299 static const struct intel_device_info pnv_g_info = { 300 GEN3_FEATURES, 301 PLATFORM(INTEL_PINEVIEW), 302 .display.has_hotplug = 1, 303 .display.has_overlay = 1, 304 .dma_mask_size = 36, 305 }; 306 307 static const struct intel_device_info pnv_m_info = { 308 GEN3_FEATURES, 309 PLATFORM(INTEL_PINEVIEW), 310 .is_mobile = 1, 311 .display.has_hotplug = 1, 312 .display.has_overlay = 1, 313 .dma_mask_size = 36, 314 }; 315 316 #define GEN4_FEATURES \ 317 GEN(4), \ 318 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 319 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 320 .display.has_hotplug = 1, \ 321 .display.has_gmch = 1, \ 322 .gpu_reset_clobbers_display = true, \ 323 .platform_engine_mask = BIT(RCS0), \ 324 .has_snoop = true, \ 325 .has_coherent_ggtt = true, \ 326 .dma_mask_size = 36, \ 327 I9XX_PIPE_OFFSETS, \ 328 I9XX_CURSOR_OFFSETS, \ 329 I965_COLORS, \ 330 GEN_DEFAULT_PAGE_SIZES, \ 331 GEN_DEFAULT_REGIONS 332 333 static const struct intel_device_info i965g_info = { 334 GEN4_FEATURES, 335 PLATFORM(INTEL_I965G), 336 .display.has_overlay = 1, 337 .hws_needs_physical = 1, 338 .has_snoop = false, 339 }; 340 341 static const struct intel_device_info i965gm_info = { 342 GEN4_FEATURES, 343 PLATFORM(INTEL_I965GM), 344 .is_mobile = 1, 345 .display.has_fbc = 1, 346 .display.has_overlay = 1, 347 .display.supports_tv = 1, 348 .hws_needs_physical = 1, 349 .has_snoop = false, 350 }; 351 352 static const struct intel_device_info g45_info = { 353 GEN4_FEATURES, 354 PLATFORM(INTEL_G45), 355 .platform_engine_mask = BIT(RCS0) | BIT(VCS0), 356 .gpu_reset_clobbers_display = false, 357 }; 358 359 static const struct intel_device_info gm45_info = { 360 GEN4_FEATURES, 361 PLATFORM(INTEL_GM45), 362 .is_mobile = 1, 363 .display.has_fbc = 1, 364 .display.supports_tv = 1, 365 .platform_engine_mask = BIT(RCS0) | BIT(VCS0), 366 .gpu_reset_clobbers_display = false, 367 }; 368 369 #define GEN5_FEATURES \ 370 GEN(5), \ 371 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 372 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 373 .display.has_hotplug = 1, \ 374 .platform_engine_mask = BIT(RCS0) | BIT(VCS0), \ 375 .has_snoop = true, \ 376 .has_coherent_ggtt = true, \ 377 /* ilk does support rc6, but we do not implement [power] contexts */ \ 378 .has_rc6 = 0, \ 379 .dma_mask_size = 36, \ 380 I9XX_PIPE_OFFSETS, \ 381 I9XX_CURSOR_OFFSETS, \ 382 ILK_COLORS, \ 383 GEN_DEFAULT_PAGE_SIZES, \ 384 GEN_DEFAULT_REGIONS 385 386 static const struct intel_device_info ilk_d_info = { 387 GEN5_FEATURES, 388 PLATFORM(INTEL_IRONLAKE), 389 }; 390 391 static const struct intel_device_info ilk_m_info = { 392 GEN5_FEATURES, 393 PLATFORM(INTEL_IRONLAKE), 394 .is_mobile = 1, 395 .has_rps = true, 396 .display.has_fbc = 1, 397 }; 398 399 #define GEN6_FEATURES \ 400 GEN(6), \ 401 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 402 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 403 .display.has_hotplug = 1, \ 404 .display.has_fbc = 1, \ 405 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ 406 .has_coherent_ggtt = true, \ 407 .has_llc = 1, \ 408 .has_rc6 = 1, \ 409 .has_rc6p = 1, \ 410 .has_rps = true, \ 411 .dma_mask_size = 40, \ 412 .ppgtt_type = INTEL_PPGTT_ALIASING, \ 413 .ppgtt_size = 31, \ 414 I9XX_PIPE_OFFSETS, \ 415 I9XX_CURSOR_OFFSETS, \ 416 ILK_COLORS, \ 417 GEN_DEFAULT_PAGE_SIZES, \ 418 GEN_DEFAULT_REGIONS 419 420 #define SNB_D_PLATFORM \ 421 GEN6_FEATURES, \ 422 PLATFORM(INTEL_SANDYBRIDGE) 423 424 static const struct intel_device_info snb_d_gt1_info = { 425 SNB_D_PLATFORM, 426 .gt = 1, 427 }; 428 429 static const struct intel_device_info snb_d_gt2_info = { 430 SNB_D_PLATFORM, 431 .gt = 2, 432 }; 433 434 #define SNB_M_PLATFORM \ 435 GEN6_FEATURES, \ 436 PLATFORM(INTEL_SANDYBRIDGE), \ 437 .is_mobile = 1 438 439 440 static const struct intel_device_info snb_m_gt1_info = { 441 SNB_M_PLATFORM, 442 .gt = 1, 443 }; 444 445 static const struct intel_device_info snb_m_gt2_info = { 446 SNB_M_PLATFORM, 447 .gt = 2, 448 }; 449 450 #define GEN7_FEATURES \ 451 GEN(7), \ 452 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ 453 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \ 454 .display.has_hotplug = 1, \ 455 .display.has_fbc = 1, \ 456 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ 457 .has_coherent_ggtt = true, \ 458 .has_llc = 1, \ 459 .has_rc6 = 1, \ 460 .has_rc6p = 1, \ 461 .has_reset_engine = true, \ 462 .has_rps = true, \ 463 .dma_mask_size = 40, \ 464 .ppgtt_type = INTEL_PPGTT_ALIASING, \ 465 .ppgtt_size = 31, \ 466 IVB_PIPE_OFFSETS, \ 467 IVB_CURSOR_OFFSETS, \ 468 IVB_COLORS, \ 469 GEN_DEFAULT_PAGE_SIZES, \ 470 GEN_DEFAULT_REGIONS 471 472 #define IVB_D_PLATFORM \ 473 GEN7_FEATURES, \ 474 PLATFORM(INTEL_IVYBRIDGE), \ 475 .has_l3_dpf = 1 476 477 static const struct intel_device_info ivb_d_gt1_info = { 478 IVB_D_PLATFORM, 479 .gt = 1, 480 }; 481 482 static const struct intel_device_info ivb_d_gt2_info = { 483 IVB_D_PLATFORM, 484 .gt = 2, 485 }; 486 487 #define IVB_M_PLATFORM \ 488 GEN7_FEATURES, \ 489 PLATFORM(INTEL_IVYBRIDGE), \ 490 .is_mobile = 1, \ 491 .has_l3_dpf = 1 492 493 static const struct intel_device_info ivb_m_gt1_info = { 494 IVB_M_PLATFORM, 495 .gt = 1, 496 }; 497 498 static const struct intel_device_info ivb_m_gt2_info = { 499 IVB_M_PLATFORM, 500 .gt = 2, 501 }; 502 503 static const struct intel_device_info ivb_q_info = { 504 GEN7_FEATURES, 505 PLATFORM(INTEL_IVYBRIDGE), 506 .gt = 2, 507 .display.pipe_mask = 0, /* legal, last one wins */ 508 .display.cpu_transcoder_mask = 0, 509 .has_l3_dpf = 1, 510 }; 511 512 static const struct intel_device_info vlv_info = { 513 PLATFORM(INTEL_VALLEYVIEW), 514 GEN(7), 515 .is_lp = 1, 516 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), 517 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), 518 .has_runtime_pm = 1, 519 .has_rc6 = 1, 520 .has_reset_engine = true, 521 .has_rps = true, 522 .display.has_gmch = 1, 523 .display.has_hotplug = 1, 524 .dma_mask_size = 40, 525 .ppgtt_type = INTEL_PPGTT_ALIASING, 526 .ppgtt_size = 31, 527 .has_snoop = true, 528 .has_coherent_ggtt = false, 529 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), 530 .display_mmio_offset = VLV_DISPLAY_BASE, 531 I9XX_PIPE_OFFSETS, 532 I9XX_CURSOR_OFFSETS, 533 I965_COLORS, 534 GEN_DEFAULT_PAGE_SIZES, 535 GEN_DEFAULT_REGIONS, 536 }; 537 538 #define G75_FEATURES \ 539 GEN7_FEATURES, \ 540 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ 541 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 542 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \ 543 .display.has_ddi = 1, \ 544 .display.has_fpga_dbg = 1, \ 545 .display.has_dp_mst = 1, \ 546 .has_rc6p = 0 /* RC6p removed-by HSW */, \ 547 HSW_PIPE_OFFSETS, \ 548 .has_runtime_pm = 1 549 550 #define HSW_PLATFORM \ 551 G75_FEATURES, \ 552 PLATFORM(INTEL_HASWELL), \ 553 .has_l3_dpf = 1 554 555 static const struct intel_device_info hsw_gt1_info = { 556 HSW_PLATFORM, 557 .gt = 1, 558 }; 559 560 static const struct intel_device_info hsw_gt2_info = { 561 HSW_PLATFORM, 562 .gt = 2, 563 }; 564 565 static const struct intel_device_info hsw_gt3_info = { 566 HSW_PLATFORM, 567 .gt = 3, 568 }; 569 570 #define GEN8_FEATURES \ 571 G75_FEATURES, \ 572 GEN(8), \ 573 .has_logical_ring_contexts = 1, \ 574 .dma_mask_size = 39, \ 575 .ppgtt_type = INTEL_PPGTT_FULL, \ 576 .ppgtt_size = 48, \ 577 .has_64bit_reloc = 1 578 579 #define BDW_PLATFORM \ 580 GEN8_FEATURES, \ 581 PLATFORM(INTEL_BROADWELL) 582 583 static const struct intel_device_info bdw_gt1_info = { 584 BDW_PLATFORM, 585 .gt = 1, 586 }; 587 588 static const struct intel_device_info bdw_gt2_info = { 589 BDW_PLATFORM, 590 .gt = 2, 591 }; 592 593 static const struct intel_device_info bdw_rsvd_info = { 594 BDW_PLATFORM, 595 .gt = 3, 596 /* According to the device ID those devices are GT3, they were 597 * previously treated as not GT3, keep it like that. 598 */ 599 }; 600 601 static const struct intel_device_info bdw_gt3_info = { 602 BDW_PLATFORM, 603 .gt = 3, 604 .platform_engine_mask = 605 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 606 }; 607 608 static const struct intel_device_info chv_info = { 609 PLATFORM(INTEL_CHERRYVIEW), 610 GEN(8), 611 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 612 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), 613 .display.has_hotplug = 1, 614 .is_lp = 1, 615 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), 616 .has_64bit_reloc = 1, 617 .has_runtime_pm = 1, 618 .has_rc6 = 1, 619 .has_rps = true, 620 .has_logical_ring_contexts = 1, 621 .display.has_gmch = 1, 622 .dma_mask_size = 39, 623 .ppgtt_type = INTEL_PPGTT_FULL, 624 .ppgtt_size = 32, 625 .has_reset_engine = 1, 626 .has_snoop = true, 627 .has_coherent_ggtt = false, 628 .display_mmio_offset = VLV_DISPLAY_BASE, 629 CHV_PIPE_OFFSETS, 630 CHV_CURSOR_OFFSETS, 631 CHV_COLORS, 632 GEN_DEFAULT_PAGE_SIZES, 633 GEN_DEFAULT_REGIONS, 634 }; 635 636 #define GEN9_DEFAULT_PAGE_SIZES \ 637 .page_sizes = I915_GTT_PAGE_SIZE_4K | \ 638 I915_GTT_PAGE_SIZE_64K 639 640 #define GEN9_FEATURES \ 641 GEN8_FEATURES, \ 642 GEN(9), \ 643 GEN9_DEFAULT_PAGE_SIZES, \ 644 .display.has_dmc = 1, \ 645 .has_gt_uc = 1, \ 646 .display.has_hdcp = 1, \ 647 .display.has_ipc = 1, \ 648 .display.has_psr = 1, \ 649 .display.has_psr_hw_tracking = 1, \ 650 .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \ 651 .dbuf.slice_mask = BIT(DBUF_S1) 652 653 #define SKL_PLATFORM \ 654 GEN9_FEATURES, \ 655 PLATFORM(INTEL_SKYLAKE) 656 657 static const struct intel_device_info skl_gt1_info = { 658 SKL_PLATFORM, 659 .gt = 1, 660 }; 661 662 static const struct intel_device_info skl_gt2_info = { 663 SKL_PLATFORM, 664 .gt = 2, 665 }; 666 667 #define SKL_GT3_PLUS_PLATFORM \ 668 SKL_PLATFORM, \ 669 .platform_engine_mask = \ 670 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1) 671 672 673 static const struct intel_device_info skl_gt3_info = { 674 SKL_GT3_PLUS_PLATFORM, 675 .gt = 3, 676 }; 677 678 static const struct intel_device_info skl_gt4_info = { 679 SKL_GT3_PLUS_PLATFORM, 680 .gt = 4, 681 }; 682 683 #define GEN9_LP_FEATURES \ 684 GEN(9), \ 685 .is_lp = 1, \ 686 .dbuf.slice_mask = BIT(DBUF_S1), \ 687 .display.has_hotplug = 1, \ 688 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ 689 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ 690 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 691 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ 692 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \ 693 .has_64bit_reloc = 1, \ 694 .display.has_ddi = 1, \ 695 .display.has_fpga_dbg = 1, \ 696 .display.has_fbc = 1, \ 697 .display.has_hdcp = 1, \ 698 .display.has_psr = 1, \ 699 .display.has_psr_hw_tracking = 1, \ 700 .has_runtime_pm = 1, \ 701 .display.has_dmc = 1, \ 702 .has_rc6 = 1, \ 703 .has_rps = true, \ 704 .display.has_dp_mst = 1, \ 705 .has_logical_ring_contexts = 1, \ 706 .has_gt_uc = 1, \ 707 .dma_mask_size = 39, \ 708 .ppgtt_type = INTEL_PPGTT_FULL, \ 709 .ppgtt_size = 48, \ 710 .has_reset_engine = 1, \ 711 .has_snoop = true, \ 712 .has_coherent_ggtt = false, \ 713 .display.has_ipc = 1, \ 714 HSW_PIPE_OFFSETS, \ 715 IVB_CURSOR_OFFSETS, \ 716 IVB_COLORS, \ 717 GEN9_DEFAULT_PAGE_SIZES, \ 718 GEN_DEFAULT_REGIONS 719 720 static const struct intel_device_info bxt_info = { 721 GEN9_LP_FEATURES, 722 PLATFORM(INTEL_BROXTON), 723 .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */ 724 }; 725 726 static const struct intel_device_info glk_info = { 727 GEN9_LP_FEATURES, 728 PLATFORM(INTEL_GEMINILAKE), 729 .display.ver = 10, 730 .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ 731 GLK_COLORS, 732 }; 733 734 #define KBL_PLATFORM \ 735 GEN9_FEATURES, \ 736 PLATFORM(INTEL_KABYLAKE) 737 738 static const struct intel_device_info kbl_gt1_info = { 739 KBL_PLATFORM, 740 .gt = 1, 741 }; 742 743 static const struct intel_device_info kbl_gt2_info = { 744 KBL_PLATFORM, 745 .gt = 2, 746 }; 747 748 static const struct intel_device_info kbl_gt3_info = { 749 KBL_PLATFORM, 750 .gt = 3, 751 .platform_engine_mask = 752 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 753 }; 754 755 #define CFL_PLATFORM \ 756 GEN9_FEATURES, \ 757 PLATFORM(INTEL_COFFEELAKE) 758 759 static const struct intel_device_info cfl_gt1_info = { 760 CFL_PLATFORM, 761 .gt = 1, 762 }; 763 764 static const struct intel_device_info cfl_gt2_info = { 765 CFL_PLATFORM, 766 .gt = 2, 767 }; 768 769 static const struct intel_device_info cfl_gt3_info = { 770 CFL_PLATFORM, 771 .gt = 3, 772 .platform_engine_mask = 773 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 774 }; 775 776 #define CML_PLATFORM \ 777 GEN9_FEATURES, \ 778 PLATFORM(INTEL_COMETLAKE) 779 780 static const struct intel_device_info cml_gt1_info = { 781 CML_PLATFORM, 782 .gt = 1, 783 }; 784 785 static const struct intel_device_info cml_gt2_info = { 786 CML_PLATFORM, 787 .gt = 2, 788 }; 789 790 #define GEN11_DEFAULT_PAGE_SIZES \ 791 .page_sizes = I915_GTT_PAGE_SIZE_4K | \ 792 I915_GTT_PAGE_SIZE_64K | \ 793 I915_GTT_PAGE_SIZE_2M 794 795 #define GEN11_FEATURES \ 796 GEN9_FEATURES, \ 797 GEN11_DEFAULT_PAGE_SIZES, \ 798 .display.abox_mask = BIT(0), \ 799 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 800 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ 801 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ 802 .pipe_offsets = { \ 803 [TRANSCODER_A] = PIPE_A_OFFSET, \ 804 [TRANSCODER_B] = PIPE_B_OFFSET, \ 805 [TRANSCODER_C] = PIPE_C_OFFSET, \ 806 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 807 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 808 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 809 }, \ 810 .trans_offsets = { \ 811 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 812 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 813 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 814 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 815 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 816 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 817 }, \ 818 GEN(11), \ 819 ICL_COLORS, \ 820 .dbuf.size = 2048, \ 821 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \ 822 .display.has_dsc = 1, \ 823 .has_coherent_ggtt = false, \ 824 .has_logical_ring_elsq = 1 825 826 static const struct intel_device_info icl_info = { 827 GEN11_FEATURES, 828 PLATFORM(INTEL_ICELAKE), 829 .platform_engine_mask = 830 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 831 }; 832 833 static const struct intel_device_info ehl_info = { 834 GEN11_FEATURES, 835 PLATFORM(INTEL_ELKHARTLAKE), 836 .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0), 837 .ppgtt_size = 36, 838 }; 839 840 static const struct intel_device_info jsl_info = { 841 GEN11_FEATURES, 842 PLATFORM(INTEL_JASPERLAKE), 843 .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0), 844 .ppgtt_size = 36, 845 }; 846 847 #define GEN12_FEATURES \ 848 GEN11_FEATURES, \ 849 GEN(12), \ 850 .display.abox_mask = GENMASK(2, 1), \ 851 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ 852 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 853 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \ 854 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ 855 .pipe_offsets = { \ 856 [TRANSCODER_A] = PIPE_A_OFFSET, \ 857 [TRANSCODER_B] = PIPE_B_OFFSET, \ 858 [TRANSCODER_C] = PIPE_C_OFFSET, \ 859 [TRANSCODER_D] = PIPE_D_OFFSET, \ 860 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 861 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 862 }, \ 863 .trans_offsets = { \ 864 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 865 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 866 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 867 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ 868 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 869 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 870 }, \ 871 TGL_CURSOR_OFFSETS, \ 872 .has_global_mocs = 1, \ 873 .has_pxp = 1, \ 874 .display.has_dsb = 0 /* FIXME: LUT load is broken with DSB */ 875 876 static const struct intel_device_info tgl_info = { 877 GEN12_FEATURES, 878 PLATFORM(INTEL_TIGERLAKE), 879 .display.has_modular_fia = 1, 880 .platform_engine_mask = 881 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 882 }; 883 884 static const struct intel_device_info rkl_info = { 885 GEN12_FEATURES, 886 PLATFORM(INTEL_ROCKETLAKE), 887 .display.abox_mask = BIT(0), 888 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 889 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 890 BIT(TRANSCODER_C), 891 .display.has_hti = 1, 892 .display.has_psr_hw_tracking = 0, 893 .platform_engine_mask = 894 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0), 895 }; 896 897 #define DGFX_FEATURES \ 898 .memory_regions = REGION_SMEM | REGION_LMEM | REGION_STOLEN_LMEM, \ 899 .has_llc = 0, \ 900 .has_pxp = 0, \ 901 .has_snoop = 1, \ 902 .is_dgfx = 1 903 904 static const struct intel_device_info dg1_info = { 905 GEN12_FEATURES, 906 DGFX_FEATURES, 907 .graphics.rel = 10, 908 PLATFORM(INTEL_DG1), 909 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 910 .require_force_probe = 1, 911 .platform_engine_mask = 912 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | 913 BIT(VCS0) | BIT(VCS2), 914 /* Wa_16011227922 */ 915 .ppgtt_size = 47, 916 }; 917 918 static const struct intel_device_info adl_s_info = { 919 GEN12_FEATURES, 920 PLATFORM(INTEL_ALDERLAKE_S), 921 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 922 .display.has_hti = 1, 923 .display.has_psr_hw_tracking = 0, 924 .platform_engine_mask = 925 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 926 .dma_mask_size = 39, 927 }; 928 929 #define XE_LPD_CURSOR_OFFSETS \ 930 .cursor_offsets = { \ 931 [PIPE_A] = CURSOR_A_OFFSET, \ 932 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 933 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 934 [PIPE_D] = TGL_CURSOR_D_OFFSET, \ 935 } 936 937 #define XE_LPD_FEATURES \ 938 .display.abox_mask = GENMASK(1, 0), \ 939 .color = { .degamma_lut_size = 128, .gamma_lut_size = 1024, \ 940 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 941 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 942 }, \ 943 .dbuf.size = 4096, \ 944 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \ 945 BIT(DBUF_S4), \ 946 .display.has_ddi = 1, \ 947 .display.has_dmc = 1, \ 948 .display.has_dp_mst = 1, \ 949 .display.has_dsb = 1, \ 950 .display.has_dsc = 1, \ 951 .display.has_fbc = 1, \ 952 .display.has_fpga_dbg = 1, \ 953 .display.has_hdcp = 1, \ 954 .display.has_hotplug = 1, \ 955 .display.has_ipc = 1, \ 956 .display.has_psr = 1, \ 957 .display.ver = 13, \ 958 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ 959 .pipe_offsets = { \ 960 [TRANSCODER_A] = PIPE_A_OFFSET, \ 961 [TRANSCODER_B] = PIPE_B_OFFSET, \ 962 [TRANSCODER_C] = PIPE_C_OFFSET, \ 963 [TRANSCODER_D] = PIPE_D_OFFSET, \ 964 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 965 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 966 }, \ 967 .trans_offsets = { \ 968 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 969 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 970 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 971 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ 972 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 973 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 974 }, \ 975 XE_LPD_CURSOR_OFFSETS 976 977 static const struct intel_device_info adl_p_info = { 978 GEN12_FEATURES, 979 XE_LPD_FEATURES, 980 PLATFORM(INTEL_ALDERLAKE_P), 981 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 982 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | 983 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), 984 .display.has_cdclk_crawl = 1, 985 .display.has_modular_fia = 1, 986 .display.has_psr_hw_tracking = 0, 987 .platform_engine_mask = 988 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 989 .ppgtt_size = 48, 990 .dma_mask_size = 39, 991 }; 992 993 #undef GEN 994 995 #define XE_HP_PAGE_SIZES \ 996 .page_sizes = I915_GTT_PAGE_SIZE_4K | \ 997 I915_GTT_PAGE_SIZE_64K | \ 998 I915_GTT_PAGE_SIZE_2M 999 1000 #define XE_HP_FEATURES \ 1001 .graphics.ver = 12, \ 1002 .graphics.rel = 50, \ 1003 XE_HP_PAGE_SIZES, \ 1004 .dma_mask_size = 46, \ 1005 .has_64bit_reloc = 1, \ 1006 .has_global_mocs = 1, \ 1007 .has_gt_uc = 1, \ 1008 .has_llc = 1, \ 1009 .has_logical_ring_contexts = 1, \ 1010 .has_logical_ring_elsq = 1, \ 1011 .has_mslices = 1, \ 1012 .has_rc6 = 1, \ 1013 .has_reset_engine = 1, \ 1014 .has_rps = 1, \ 1015 .has_runtime_pm = 1, \ 1016 .ppgtt_size = 48, \ 1017 .ppgtt_type = INTEL_PPGTT_FULL 1018 1019 #define XE_HPM_FEATURES \ 1020 .media.ver = 12, \ 1021 .media.rel = 50 1022 1023 __maybe_unused 1024 static const struct intel_device_info xehpsdv_info = { 1025 XE_HP_FEATURES, 1026 XE_HPM_FEATURES, 1027 DGFX_FEATURES, 1028 PLATFORM(INTEL_XEHPSDV), 1029 .display = { }, 1030 .has_64k_pages = 1, 1031 .platform_engine_mask = 1032 BIT(RCS0) | BIT(BCS0) | 1033 BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) | 1034 BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) | 1035 BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7), 1036 .require_force_probe = 1, 1037 }; 1038 1039 __maybe_unused 1040 static const struct intel_device_info dg2_info = { 1041 XE_HP_FEATURES, 1042 XE_HPM_FEATURES, 1043 XE_LPD_FEATURES, 1044 DGFX_FEATURES, 1045 .graphics.rel = 55, 1046 .media.rel = 55, 1047 PLATFORM(INTEL_DG2), 1048 .has_64k_pages = 1, 1049 .platform_engine_mask = 1050 BIT(RCS0) | BIT(BCS0) | 1051 BIT(VECS0) | BIT(VECS1) | 1052 BIT(VCS0) | BIT(VCS2), 1053 .require_force_probe = 1, 1054 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 1055 BIT(TRANSCODER_C) | BIT(TRANSCODER_D), 1056 }; 1057 1058 #undef PLATFORM 1059 1060 /* 1061 * Make sure any device matches here are from most specific to most 1062 * general. For example, since the Quanta match is based on the subsystem 1063 * and subvendor IDs, we need it to come before the more general IVB 1064 * PCI ID matches, otherwise we'll use the wrong info struct above. 1065 */ 1066 static const struct pci_device_id pciidlist[] = { 1067 INTEL_I830_IDS(&i830_info), 1068 INTEL_I845G_IDS(&i845g_info), 1069 INTEL_I85X_IDS(&i85x_info), 1070 INTEL_I865G_IDS(&i865g_info), 1071 INTEL_I915G_IDS(&i915g_info), 1072 INTEL_I915GM_IDS(&i915gm_info), 1073 INTEL_I945G_IDS(&i945g_info), 1074 INTEL_I945GM_IDS(&i945gm_info), 1075 INTEL_I965G_IDS(&i965g_info), 1076 INTEL_G33_IDS(&g33_info), 1077 INTEL_I965GM_IDS(&i965gm_info), 1078 INTEL_GM45_IDS(&gm45_info), 1079 INTEL_G45_IDS(&g45_info), 1080 INTEL_PINEVIEW_G_IDS(&pnv_g_info), 1081 INTEL_PINEVIEW_M_IDS(&pnv_m_info), 1082 INTEL_IRONLAKE_D_IDS(&ilk_d_info), 1083 INTEL_IRONLAKE_M_IDS(&ilk_m_info), 1084 INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info), 1085 INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info), 1086 INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info), 1087 INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info), 1088 INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */ 1089 INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info), 1090 INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info), 1091 INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info), 1092 INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info), 1093 INTEL_HSW_GT1_IDS(&hsw_gt1_info), 1094 INTEL_HSW_GT2_IDS(&hsw_gt2_info), 1095 INTEL_HSW_GT3_IDS(&hsw_gt3_info), 1096 INTEL_VLV_IDS(&vlv_info), 1097 INTEL_BDW_GT1_IDS(&bdw_gt1_info), 1098 INTEL_BDW_GT2_IDS(&bdw_gt2_info), 1099 INTEL_BDW_GT3_IDS(&bdw_gt3_info), 1100 INTEL_BDW_RSVD_IDS(&bdw_rsvd_info), 1101 INTEL_CHV_IDS(&chv_info), 1102 INTEL_SKL_GT1_IDS(&skl_gt1_info), 1103 INTEL_SKL_GT2_IDS(&skl_gt2_info), 1104 INTEL_SKL_GT3_IDS(&skl_gt3_info), 1105 INTEL_SKL_GT4_IDS(&skl_gt4_info), 1106 INTEL_BXT_IDS(&bxt_info), 1107 INTEL_GLK_IDS(&glk_info), 1108 INTEL_KBL_GT1_IDS(&kbl_gt1_info), 1109 INTEL_KBL_GT2_IDS(&kbl_gt2_info), 1110 INTEL_KBL_GT3_IDS(&kbl_gt3_info), 1111 INTEL_KBL_GT4_IDS(&kbl_gt3_info), 1112 INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info), 1113 INTEL_CFL_S_GT1_IDS(&cfl_gt1_info), 1114 INTEL_CFL_S_GT2_IDS(&cfl_gt2_info), 1115 INTEL_CFL_H_GT1_IDS(&cfl_gt1_info), 1116 INTEL_CFL_H_GT2_IDS(&cfl_gt2_info), 1117 INTEL_CFL_U_GT2_IDS(&cfl_gt2_info), 1118 INTEL_CFL_U_GT3_IDS(&cfl_gt3_info), 1119 INTEL_WHL_U_GT1_IDS(&cfl_gt1_info), 1120 INTEL_WHL_U_GT2_IDS(&cfl_gt2_info), 1121 INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info), 1122 INTEL_WHL_U_GT3_IDS(&cfl_gt3_info), 1123 INTEL_CML_GT1_IDS(&cml_gt1_info), 1124 INTEL_CML_GT2_IDS(&cml_gt2_info), 1125 INTEL_CML_U_GT1_IDS(&cml_gt1_info), 1126 INTEL_CML_U_GT2_IDS(&cml_gt2_info), 1127 INTEL_ICL_11_IDS(&icl_info), 1128 INTEL_EHL_IDS(&ehl_info), 1129 INTEL_JSL_IDS(&jsl_info), 1130 INTEL_TGL_12_IDS(&tgl_info), 1131 INTEL_RKL_IDS(&rkl_info), 1132 INTEL_ADLS_IDS(&adl_s_info), 1133 INTEL_ADLP_IDS(&adl_p_info), 1134 INTEL_DG1_IDS(&dg1_info), 1135 INTEL_RPLS_IDS(&adl_s_info), 1136 {0, 0, 0} 1137 }; 1138 MODULE_DEVICE_TABLE(pci, pciidlist); 1139 1140 static void i915_pci_remove(struct pci_dev *pdev) 1141 { 1142 struct drm_i915_private *i915; 1143 1144 i915 = pci_get_drvdata(pdev); 1145 if (!i915) /* driver load aborted, nothing to cleanup */ 1146 return; 1147 1148 i915_driver_remove(i915); 1149 pci_set_drvdata(pdev, NULL); 1150 } 1151 1152 /* is device_id present in comma separated list of ids */ 1153 static bool force_probe(u16 device_id, const char *devices) 1154 { 1155 char *s, *p, *tok; 1156 bool ret; 1157 1158 if (!devices || !*devices) 1159 return false; 1160 1161 /* match everything */ 1162 if (strcmp(devices, "*") == 0) 1163 return true; 1164 1165 s = kstrdup(devices, GFP_KERNEL); 1166 if (!s) 1167 return false; 1168 1169 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) { 1170 u16 val; 1171 1172 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) { 1173 ret = true; 1174 break; 1175 } 1176 } 1177 1178 kfree(s); 1179 1180 return ret; 1181 } 1182 1183 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1184 { 1185 struct intel_device_info *intel_info = 1186 (struct intel_device_info *) ent->driver_data; 1187 int err; 1188 1189 if (intel_info->require_force_probe && 1190 !force_probe(pdev->device, i915_modparams.force_probe)) { 1191 dev_info(&pdev->dev, 1192 "Your graphics device %04x is not properly supported by the driver in this\n" 1193 "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n" 1194 "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n" 1195 "or (recommended) check for kernel updates.\n", 1196 pdev->device, pdev->device, pdev->device); 1197 return -ENODEV; 1198 } 1199 1200 /* Only bind to function 0 of the device. Early generations 1201 * used function 1 as a placeholder for multi-head. This causes 1202 * us confusion instead, especially on the systems where both 1203 * functions have the same PCI-ID! 1204 */ 1205 if (PCI_FUNC(pdev->devfn)) 1206 return -ENODEV; 1207 1208 /* Detect if we need to wait for other drivers early on */ 1209 if (intel_modeset_probe_defer(pdev)) 1210 return -EPROBE_DEFER; 1211 1212 err = i915_driver_probe(pdev, ent); 1213 if (err) 1214 return err; 1215 1216 if (i915_inject_probe_failure(pci_get_drvdata(pdev))) { 1217 i915_pci_remove(pdev); 1218 return -ENODEV; 1219 } 1220 1221 err = i915_live_selftests(pdev); 1222 if (err) { 1223 i915_pci_remove(pdev); 1224 return err > 0 ? -ENOTTY : err; 1225 } 1226 1227 err = i915_perf_selftests(pdev); 1228 if (err) { 1229 i915_pci_remove(pdev); 1230 return err > 0 ? -ENOTTY : err; 1231 } 1232 1233 return 0; 1234 } 1235 1236 static void i915_pci_shutdown(struct pci_dev *pdev) 1237 { 1238 struct drm_i915_private *i915 = pci_get_drvdata(pdev); 1239 1240 i915_driver_shutdown(i915); 1241 } 1242 1243 static struct pci_driver i915_pci_driver = { 1244 .name = DRIVER_NAME, 1245 .id_table = pciidlist, 1246 .probe = i915_pci_probe, 1247 .remove = i915_pci_remove, 1248 .shutdown = i915_pci_shutdown, 1249 .driver.pm = &i915_pm_ops, 1250 }; 1251 1252 int i915_pci_register_driver(void) 1253 { 1254 return pci_register_driver(&i915_pci_driver); 1255 } 1256 1257 void i915_pci_unregister_driver(void) 1258 { 1259 pci_unregister_driver(&i915_pci_driver); 1260 } 1261