xref: /openbmc/linux/drivers/gpu/drm/i915/i915_pci.c (revision 9659281c)
1 /*
2  * Copyright © 2016 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  */
24 
25 #include <linux/console.h>
26 #include <linux/vga_switcheroo.h>
27 
28 #include <drm/drm_drv.h>
29 #include <drm/i915_pciids.h>
30 
31 #include "display/intel_fbdev.h"
32 
33 #include "i915_drv.h"
34 #include "i915_perf.h"
35 #include "i915_globals.h"
36 #include "i915_selftest.h"
37 
38 #define PLATFORM(x) .platform = (x)
39 #define GEN(x) \
40 	.graphics_ver = (x), \
41 	.media_ver = (x), \
42 	.display.ver = (x)
43 
44 #define I845_PIPE_OFFSETS \
45 	.pipe_offsets = { \
46 		[TRANSCODER_A] = PIPE_A_OFFSET,	\
47 	}, \
48 	.trans_offsets = { \
49 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
50 	}
51 
52 #define I9XX_PIPE_OFFSETS \
53 	.pipe_offsets = { \
54 		[TRANSCODER_A] = PIPE_A_OFFSET,	\
55 		[TRANSCODER_B] = PIPE_B_OFFSET, \
56 	}, \
57 	.trans_offsets = { \
58 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
59 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
60 	}
61 
62 #define IVB_PIPE_OFFSETS \
63 	.pipe_offsets = { \
64 		[TRANSCODER_A] = PIPE_A_OFFSET,	\
65 		[TRANSCODER_B] = PIPE_B_OFFSET, \
66 		[TRANSCODER_C] = PIPE_C_OFFSET, \
67 	}, \
68 	.trans_offsets = { \
69 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
70 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
71 		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
72 	}
73 
74 #define HSW_PIPE_OFFSETS \
75 	.pipe_offsets = { \
76 		[TRANSCODER_A] = PIPE_A_OFFSET,	\
77 		[TRANSCODER_B] = PIPE_B_OFFSET, \
78 		[TRANSCODER_C] = PIPE_C_OFFSET, \
79 		[TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
80 	}, \
81 	.trans_offsets = { \
82 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
83 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
84 		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
85 		[TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
86 	}
87 
88 #define CHV_PIPE_OFFSETS \
89 	.pipe_offsets = { \
90 		[TRANSCODER_A] = PIPE_A_OFFSET, \
91 		[TRANSCODER_B] = PIPE_B_OFFSET, \
92 		[TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
93 	}, \
94 	.trans_offsets = { \
95 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
96 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
97 		[TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
98 	}
99 
100 #define I845_CURSOR_OFFSETS \
101 	.cursor_offsets = { \
102 		[PIPE_A] = CURSOR_A_OFFSET, \
103 	}
104 
105 #define I9XX_CURSOR_OFFSETS \
106 	.cursor_offsets = { \
107 		[PIPE_A] = CURSOR_A_OFFSET, \
108 		[PIPE_B] = CURSOR_B_OFFSET, \
109 	}
110 
111 #define CHV_CURSOR_OFFSETS \
112 	.cursor_offsets = { \
113 		[PIPE_A] = CURSOR_A_OFFSET, \
114 		[PIPE_B] = CURSOR_B_OFFSET, \
115 		[PIPE_C] = CHV_CURSOR_C_OFFSET, \
116 	}
117 
118 #define IVB_CURSOR_OFFSETS \
119 	.cursor_offsets = { \
120 		[PIPE_A] = CURSOR_A_OFFSET, \
121 		[PIPE_B] = IVB_CURSOR_B_OFFSET, \
122 		[PIPE_C] = IVB_CURSOR_C_OFFSET, \
123 	}
124 
125 #define TGL_CURSOR_OFFSETS \
126 	.cursor_offsets = { \
127 		[PIPE_A] = CURSOR_A_OFFSET, \
128 		[PIPE_B] = IVB_CURSOR_B_OFFSET, \
129 		[PIPE_C] = IVB_CURSOR_C_OFFSET, \
130 		[PIPE_D] = TGL_CURSOR_D_OFFSET, \
131 	}
132 
133 #define I9XX_COLORS \
134 	.color = { .gamma_lut_size = 256 }
135 #define I965_COLORS \
136 	.color = { .gamma_lut_size = 129, \
137 		   .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
138 	}
139 #define ILK_COLORS \
140 	.color = { .gamma_lut_size = 1024 }
141 #define IVB_COLORS \
142 	.color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
143 #define CHV_COLORS \
144 	.color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \
145 		   .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
146 		   .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
147 	}
148 #define GLK_COLORS \
149 	.color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \
150 		   .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
151 					DRM_COLOR_LUT_EQUAL_CHANNELS, \
152 	}
153 
154 /* Keep in gen based order, and chronological order within a gen */
155 
156 #define GEN_DEFAULT_PAGE_SIZES \
157 	.page_sizes = I915_GTT_PAGE_SIZE_4K
158 
159 #define GEN_DEFAULT_REGIONS \
160 	.memory_regions = REGION_SMEM | REGION_STOLEN_SMEM
161 
162 #define I830_FEATURES \
163 	GEN(2), \
164 	.is_mobile = 1, \
165 	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
166 	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
167 	.display.has_overlay = 1, \
168 	.display.cursor_needs_physical = 1, \
169 	.display.overlay_needs_physical = 1, \
170 	.display.has_gmch = 1, \
171 	.gpu_reset_clobbers_display = true, \
172 	.hws_needs_physical = 1, \
173 	.unfenced_needs_alignment = 1, \
174 	.platform_engine_mask = BIT(RCS0), \
175 	.has_snoop = true, \
176 	.has_coherent_ggtt = false, \
177 	.dma_mask_size = 32, \
178 	I9XX_PIPE_OFFSETS, \
179 	I9XX_CURSOR_OFFSETS, \
180 	I9XX_COLORS, \
181 	GEN_DEFAULT_PAGE_SIZES, \
182 	GEN_DEFAULT_REGIONS
183 
184 #define I845_FEATURES \
185 	GEN(2), \
186 	.pipe_mask = BIT(PIPE_A), \
187 	.cpu_transcoder_mask = BIT(TRANSCODER_A), \
188 	.display.has_overlay = 1, \
189 	.display.overlay_needs_physical = 1, \
190 	.display.has_gmch = 1, \
191 	.gpu_reset_clobbers_display = true, \
192 	.hws_needs_physical = 1, \
193 	.unfenced_needs_alignment = 1, \
194 	.platform_engine_mask = BIT(RCS0), \
195 	.has_snoop = true, \
196 	.has_coherent_ggtt = false, \
197 	.dma_mask_size = 32, \
198 	I845_PIPE_OFFSETS, \
199 	I845_CURSOR_OFFSETS, \
200 	I9XX_COLORS, \
201 	GEN_DEFAULT_PAGE_SIZES, \
202 	GEN_DEFAULT_REGIONS
203 
204 static const struct intel_device_info i830_info = {
205 	I830_FEATURES,
206 	PLATFORM(INTEL_I830),
207 };
208 
209 static const struct intel_device_info i845g_info = {
210 	I845_FEATURES,
211 	PLATFORM(INTEL_I845G),
212 };
213 
214 static const struct intel_device_info i85x_info = {
215 	I830_FEATURES,
216 	PLATFORM(INTEL_I85X),
217 	.display.has_fbc = 1,
218 };
219 
220 static const struct intel_device_info i865g_info = {
221 	I845_FEATURES,
222 	PLATFORM(INTEL_I865G),
223 	.display.has_fbc = 1,
224 };
225 
226 #define GEN3_FEATURES \
227 	GEN(3), \
228 	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
229 	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
230 	.display.has_gmch = 1, \
231 	.gpu_reset_clobbers_display = true, \
232 	.platform_engine_mask = BIT(RCS0), \
233 	.has_snoop = true, \
234 	.has_coherent_ggtt = true, \
235 	.dma_mask_size = 32, \
236 	I9XX_PIPE_OFFSETS, \
237 	I9XX_CURSOR_OFFSETS, \
238 	I9XX_COLORS, \
239 	GEN_DEFAULT_PAGE_SIZES, \
240 	GEN_DEFAULT_REGIONS
241 
242 static const struct intel_device_info i915g_info = {
243 	GEN3_FEATURES,
244 	PLATFORM(INTEL_I915G),
245 	.has_coherent_ggtt = false,
246 	.display.cursor_needs_physical = 1,
247 	.display.has_overlay = 1,
248 	.display.overlay_needs_physical = 1,
249 	.hws_needs_physical = 1,
250 	.unfenced_needs_alignment = 1,
251 };
252 
253 static const struct intel_device_info i915gm_info = {
254 	GEN3_FEATURES,
255 	PLATFORM(INTEL_I915GM),
256 	.is_mobile = 1,
257 	.display.cursor_needs_physical = 1,
258 	.display.has_overlay = 1,
259 	.display.overlay_needs_physical = 1,
260 	.display.supports_tv = 1,
261 	.display.has_fbc = 1,
262 	.hws_needs_physical = 1,
263 	.unfenced_needs_alignment = 1,
264 };
265 
266 static const struct intel_device_info i945g_info = {
267 	GEN3_FEATURES,
268 	PLATFORM(INTEL_I945G),
269 	.display.has_hotplug = 1,
270 	.display.cursor_needs_physical = 1,
271 	.display.has_overlay = 1,
272 	.display.overlay_needs_physical = 1,
273 	.hws_needs_physical = 1,
274 	.unfenced_needs_alignment = 1,
275 };
276 
277 static const struct intel_device_info i945gm_info = {
278 	GEN3_FEATURES,
279 	PLATFORM(INTEL_I945GM),
280 	.is_mobile = 1,
281 	.display.has_hotplug = 1,
282 	.display.cursor_needs_physical = 1,
283 	.display.has_overlay = 1,
284 	.display.overlay_needs_physical = 1,
285 	.display.supports_tv = 1,
286 	.display.has_fbc = 1,
287 	.hws_needs_physical = 1,
288 	.unfenced_needs_alignment = 1,
289 };
290 
291 static const struct intel_device_info g33_info = {
292 	GEN3_FEATURES,
293 	PLATFORM(INTEL_G33),
294 	.display.has_hotplug = 1,
295 	.display.has_overlay = 1,
296 	.dma_mask_size = 36,
297 };
298 
299 static const struct intel_device_info pnv_g_info = {
300 	GEN3_FEATURES,
301 	PLATFORM(INTEL_PINEVIEW),
302 	.display.has_hotplug = 1,
303 	.display.has_overlay = 1,
304 	.dma_mask_size = 36,
305 };
306 
307 static const struct intel_device_info pnv_m_info = {
308 	GEN3_FEATURES,
309 	PLATFORM(INTEL_PINEVIEW),
310 	.is_mobile = 1,
311 	.display.has_hotplug = 1,
312 	.display.has_overlay = 1,
313 	.dma_mask_size = 36,
314 };
315 
316 #define GEN4_FEATURES \
317 	GEN(4), \
318 	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
319 	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
320 	.display.has_hotplug = 1, \
321 	.display.has_gmch = 1, \
322 	.gpu_reset_clobbers_display = true, \
323 	.platform_engine_mask = BIT(RCS0), \
324 	.has_snoop = true, \
325 	.has_coherent_ggtt = true, \
326 	.dma_mask_size = 36, \
327 	I9XX_PIPE_OFFSETS, \
328 	I9XX_CURSOR_OFFSETS, \
329 	I965_COLORS, \
330 	GEN_DEFAULT_PAGE_SIZES, \
331 	GEN_DEFAULT_REGIONS
332 
333 static const struct intel_device_info i965g_info = {
334 	GEN4_FEATURES,
335 	PLATFORM(INTEL_I965G),
336 	.display.has_overlay = 1,
337 	.hws_needs_physical = 1,
338 	.has_snoop = false,
339 };
340 
341 static const struct intel_device_info i965gm_info = {
342 	GEN4_FEATURES,
343 	PLATFORM(INTEL_I965GM),
344 	.is_mobile = 1,
345 	.display.has_fbc = 1,
346 	.display.has_overlay = 1,
347 	.display.supports_tv = 1,
348 	.hws_needs_physical = 1,
349 	.has_snoop = false,
350 };
351 
352 static const struct intel_device_info g45_info = {
353 	GEN4_FEATURES,
354 	PLATFORM(INTEL_G45),
355 	.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
356 	.gpu_reset_clobbers_display = false,
357 };
358 
359 static const struct intel_device_info gm45_info = {
360 	GEN4_FEATURES,
361 	PLATFORM(INTEL_GM45),
362 	.is_mobile = 1,
363 	.display.has_fbc = 1,
364 	.display.supports_tv = 1,
365 	.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
366 	.gpu_reset_clobbers_display = false,
367 };
368 
369 #define GEN5_FEATURES \
370 	GEN(5), \
371 	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
372 	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
373 	.display.has_hotplug = 1, \
374 	.platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
375 	.has_snoop = true, \
376 	.has_coherent_ggtt = true, \
377 	/* ilk does support rc6, but we do not implement [power] contexts */ \
378 	.has_rc6 = 0, \
379 	.dma_mask_size = 36, \
380 	I9XX_PIPE_OFFSETS, \
381 	I9XX_CURSOR_OFFSETS, \
382 	ILK_COLORS, \
383 	GEN_DEFAULT_PAGE_SIZES, \
384 	GEN_DEFAULT_REGIONS
385 
386 static const struct intel_device_info ilk_d_info = {
387 	GEN5_FEATURES,
388 	PLATFORM(INTEL_IRONLAKE),
389 };
390 
391 static const struct intel_device_info ilk_m_info = {
392 	GEN5_FEATURES,
393 	PLATFORM(INTEL_IRONLAKE),
394 	.is_mobile = 1,
395 	.has_rps = true,
396 	.display.has_fbc = 1,
397 };
398 
399 #define GEN6_FEATURES \
400 	GEN(6), \
401 	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
402 	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
403 	.display.has_hotplug = 1, \
404 	.display.has_fbc = 1, \
405 	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
406 	.has_coherent_ggtt = true, \
407 	.has_llc = 1, \
408 	.has_rc6 = 1, \
409 	.has_rc6p = 1, \
410 	.has_rps = true, \
411 	.dma_mask_size = 40, \
412 	.ppgtt_type = INTEL_PPGTT_ALIASING, \
413 	.ppgtt_size = 31, \
414 	I9XX_PIPE_OFFSETS, \
415 	I9XX_CURSOR_OFFSETS, \
416 	ILK_COLORS, \
417 	GEN_DEFAULT_PAGE_SIZES, \
418 	GEN_DEFAULT_REGIONS
419 
420 #define SNB_D_PLATFORM \
421 	GEN6_FEATURES, \
422 	PLATFORM(INTEL_SANDYBRIDGE)
423 
424 static const struct intel_device_info snb_d_gt1_info = {
425 	SNB_D_PLATFORM,
426 	.gt = 1,
427 };
428 
429 static const struct intel_device_info snb_d_gt2_info = {
430 	SNB_D_PLATFORM,
431 	.gt = 2,
432 };
433 
434 #define SNB_M_PLATFORM \
435 	GEN6_FEATURES, \
436 	PLATFORM(INTEL_SANDYBRIDGE), \
437 	.is_mobile = 1
438 
439 
440 static const struct intel_device_info snb_m_gt1_info = {
441 	SNB_M_PLATFORM,
442 	.gt = 1,
443 };
444 
445 static const struct intel_device_info snb_m_gt2_info = {
446 	SNB_M_PLATFORM,
447 	.gt = 2,
448 };
449 
450 #define GEN7_FEATURES  \
451 	GEN(7), \
452 	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
453 	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
454 	.display.has_hotplug = 1, \
455 	.display.has_fbc = 1, \
456 	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
457 	.has_coherent_ggtt = true, \
458 	.has_llc = 1, \
459 	.has_rc6 = 1, \
460 	.has_rc6p = 1, \
461 	.has_reset_engine = true, \
462 	.has_rps = true, \
463 	.dma_mask_size = 40, \
464 	.ppgtt_type = INTEL_PPGTT_ALIASING, \
465 	.ppgtt_size = 31, \
466 	IVB_PIPE_OFFSETS, \
467 	IVB_CURSOR_OFFSETS, \
468 	IVB_COLORS, \
469 	GEN_DEFAULT_PAGE_SIZES, \
470 	GEN_DEFAULT_REGIONS
471 
472 #define IVB_D_PLATFORM \
473 	GEN7_FEATURES, \
474 	PLATFORM(INTEL_IVYBRIDGE), \
475 	.has_l3_dpf = 1
476 
477 static const struct intel_device_info ivb_d_gt1_info = {
478 	IVB_D_PLATFORM,
479 	.gt = 1,
480 };
481 
482 static const struct intel_device_info ivb_d_gt2_info = {
483 	IVB_D_PLATFORM,
484 	.gt = 2,
485 };
486 
487 #define IVB_M_PLATFORM \
488 	GEN7_FEATURES, \
489 	PLATFORM(INTEL_IVYBRIDGE), \
490 	.is_mobile = 1, \
491 	.has_l3_dpf = 1
492 
493 static const struct intel_device_info ivb_m_gt1_info = {
494 	IVB_M_PLATFORM,
495 	.gt = 1,
496 };
497 
498 static const struct intel_device_info ivb_m_gt2_info = {
499 	IVB_M_PLATFORM,
500 	.gt = 2,
501 };
502 
503 static const struct intel_device_info ivb_q_info = {
504 	GEN7_FEATURES,
505 	PLATFORM(INTEL_IVYBRIDGE),
506 	.gt = 2,
507 	.pipe_mask = 0, /* legal, last one wins */
508 	.cpu_transcoder_mask = 0,
509 	.has_l3_dpf = 1,
510 };
511 
512 static const struct intel_device_info vlv_info = {
513 	PLATFORM(INTEL_VALLEYVIEW),
514 	GEN(7),
515 	.is_lp = 1,
516 	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
517 	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
518 	.has_runtime_pm = 1,
519 	.has_rc6 = 1,
520 	.has_reset_engine = true,
521 	.has_rps = true,
522 	.display.has_gmch = 1,
523 	.display.has_hotplug = 1,
524 	.dma_mask_size = 40,
525 	.ppgtt_type = INTEL_PPGTT_ALIASING,
526 	.ppgtt_size = 31,
527 	.has_snoop = true,
528 	.has_coherent_ggtt = false,
529 	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
530 	.display_mmio_offset = VLV_DISPLAY_BASE,
531 	I9XX_PIPE_OFFSETS,
532 	I9XX_CURSOR_OFFSETS,
533 	I965_COLORS,
534 	GEN_DEFAULT_PAGE_SIZES,
535 	GEN_DEFAULT_REGIONS,
536 };
537 
538 #define G75_FEATURES  \
539 	GEN7_FEATURES, \
540 	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
541 	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
542 		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
543 	.display.has_ddi = 1, \
544 	.display.has_fpga_dbg = 1, \
545 	.display.has_psr = 1, \
546 	.display.has_psr_hw_tracking = 1, \
547 	.display.has_dp_mst = 1, \
548 	.has_rc6p = 0 /* RC6p removed-by HSW */, \
549 	HSW_PIPE_OFFSETS, \
550 	.has_runtime_pm = 1
551 
552 #define HSW_PLATFORM \
553 	G75_FEATURES, \
554 	PLATFORM(INTEL_HASWELL), \
555 	.has_l3_dpf = 1
556 
557 static const struct intel_device_info hsw_gt1_info = {
558 	HSW_PLATFORM,
559 	.gt = 1,
560 };
561 
562 static const struct intel_device_info hsw_gt2_info = {
563 	HSW_PLATFORM,
564 	.gt = 2,
565 };
566 
567 static const struct intel_device_info hsw_gt3_info = {
568 	HSW_PLATFORM,
569 	.gt = 3,
570 };
571 
572 #define GEN8_FEATURES \
573 	G75_FEATURES, \
574 	GEN(8), \
575 	.has_logical_ring_contexts = 1, \
576 	.dma_mask_size = 39, \
577 	.ppgtt_type = INTEL_PPGTT_FULL, \
578 	.ppgtt_size = 48, \
579 	.has_64bit_reloc = 1
580 
581 #define BDW_PLATFORM \
582 	GEN8_FEATURES, \
583 	PLATFORM(INTEL_BROADWELL)
584 
585 static const struct intel_device_info bdw_gt1_info = {
586 	BDW_PLATFORM,
587 	.gt = 1,
588 };
589 
590 static const struct intel_device_info bdw_gt2_info = {
591 	BDW_PLATFORM,
592 	.gt = 2,
593 };
594 
595 static const struct intel_device_info bdw_rsvd_info = {
596 	BDW_PLATFORM,
597 	.gt = 3,
598 	/* According to the device ID those devices are GT3, they were
599 	 * previously treated as not GT3, keep it like that.
600 	 */
601 };
602 
603 static const struct intel_device_info bdw_gt3_info = {
604 	BDW_PLATFORM,
605 	.gt = 3,
606 	.platform_engine_mask =
607 		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
608 };
609 
610 static const struct intel_device_info chv_info = {
611 	PLATFORM(INTEL_CHERRYVIEW),
612 	GEN(8),
613 	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
614 	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
615 	.display.has_hotplug = 1,
616 	.is_lp = 1,
617 	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
618 	.has_64bit_reloc = 1,
619 	.has_runtime_pm = 1,
620 	.has_rc6 = 1,
621 	.has_rps = true,
622 	.has_logical_ring_contexts = 1,
623 	.display.has_gmch = 1,
624 	.dma_mask_size = 39,
625 	.ppgtt_type = INTEL_PPGTT_FULL,
626 	.ppgtt_size = 32,
627 	.has_reset_engine = 1,
628 	.has_snoop = true,
629 	.has_coherent_ggtt = false,
630 	.display_mmio_offset = VLV_DISPLAY_BASE,
631 	CHV_PIPE_OFFSETS,
632 	CHV_CURSOR_OFFSETS,
633 	CHV_COLORS,
634 	GEN_DEFAULT_PAGE_SIZES,
635 	GEN_DEFAULT_REGIONS,
636 };
637 
638 #define GEN9_DEFAULT_PAGE_SIZES \
639 	.page_sizes = I915_GTT_PAGE_SIZE_4K | \
640 		      I915_GTT_PAGE_SIZE_64K
641 
642 #define GEN9_FEATURES \
643 	GEN8_FEATURES, \
644 	GEN(9), \
645 	GEN9_DEFAULT_PAGE_SIZES, \
646 	.display.has_dmc = 1, \
647 	.has_gt_uc = 1, \
648 	.display.has_hdcp = 1, \
649 	.display.has_ipc = 1, \
650 	.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
651 	.dbuf.slice_mask = BIT(DBUF_S1)
652 
653 #define SKL_PLATFORM \
654 	GEN9_FEATURES, \
655 	PLATFORM(INTEL_SKYLAKE)
656 
657 static const struct intel_device_info skl_gt1_info = {
658 	SKL_PLATFORM,
659 	.gt = 1,
660 };
661 
662 static const struct intel_device_info skl_gt2_info = {
663 	SKL_PLATFORM,
664 	.gt = 2,
665 };
666 
667 #define SKL_GT3_PLUS_PLATFORM \
668 	SKL_PLATFORM, \
669 	.platform_engine_mask = \
670 		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
671 
672 
673 static const struct intel_device_info skl_gt3_info = {
674 	SKL_GT3_PLUS_PLATFORM,
675 	.gt = 3,
676 };
677 
678 static const struct intel_device_info skl_gt4_info = {
679 	SKL_GT3_PLUS_PLATFORM,
680 	.gt = 4,
681 };
682 
683 #define GEN9_LP_FEATURES \
684 	GEN(9), \
685 	.is_lp = 1, \
686 	.dbuf.slice_mask = BIT(DBUF_S1), \
687 	.display.has_hotplug = 1, \
688 	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
689 	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
690 	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
691 		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
692 		BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
693 	.has_64bit_reloc = 1, \
694 	.display.has_ddi = 1, \
695 	.display.has_fpga_dbg = 1, \
696 	.display.has_fbc = 1, \
697 	.display.has_hdcp = 1, \
698 	.display.has_psr = 1, \
699 	.display.has_psr_hw_tracking = 1, \
700 	.has_runtime_pm = 1, \
701 	.display.has_dmc = 1, \
702 	.has_rc6 = 1, \
703 	.has_rps = true, \
704 	.display.has_dp_mst = 1, \
705 	.has_logical_ring_contexts = 1, \
706 	.has_gt_uc = 1, \
707 	.dma_mask_size = 39, \
708 	.ppgtt_type = INTEL_PPGTT_FULL, \
709 	.ppgtt_size = 48, \
710 	.has_reset_engine = 1, \
711 	.has_snoop = true, \
712 	.has_coherent_ggtt = false, \
713 	.display.has_ipc = 1, \
714 	HSW_PIPE_OFFSETS, \
715 	IVB_CURSOR_OFFSETS, \
716 	IVB_COLORS, \
717 	GEN9_DEFAULT_PAGE_SIZES, \
718 	GEN_DEFAULT_REGIONS
719 
720 static const struct intel_device_info bxt_info = {
721 	GEN9_LP_FEATURES,
722 	PLATFORM(INTEL_BROXTON),
723 	.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
724 };
725 
726 static const struct intel_device_info glk_info = {
727 	GEN9_LP_FEATURES,
728 	PLATFORM(INTEL_GEMINILAKE),
729 	.display.ver = 10,
730 	.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
731 	GLK_COLORS,
732 };
733 
734 #define KBL_PLATFORM \
735 	GEN9_FEATURES, \
736 	PLATFORM(INTEL_KABYLAKE)
737 
738 static const struct intel_device_info kbl_gt1_info = {
739 	KBL_PLATFORM,
740 	.gt = 1,
741 };
742 
743 static const struct intel_device_info kbl_gt2_info = {
744 	KBL_PLATFORM,
745 	.gt = 2,
746 };
747 
748 static const struct intel_device_info kbl_gt3_info = {
749 	KBL_PLATFORM,
750 	.gt = 3,
751 	.platform_engine_mask =
752 		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
753 };
754 
755 #define CFL_PLATFORM \
756 	GEN9_FEATURES, \
757 	PLATFORM(INTEL_COFFEELAKE)
758 
759 static const struct intel_device_info cfl_gt1_info = {
760 	CFL_PLATFORM,
761 	.gt = 1,
762 };
763 
764 static const struct intel_device_info cfl_gt2_info = {
765 	CFL_PLATFORM,
766 	.gt = 2,
767 };
768 
769 static const struct intel_device_info cfl_gt3_info = {
770 	CFL_PLATFORM,
771 	.gt = 3,
772 	.platform_engine_mask =
773 		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
774 };
775 
776 #define CML_PLATFORM \
777 	GEN9_FEATURES, \
778 	PLATFORM(INTEL_COMETLAKE)
779 
780 static const struct intel_device_info cml_gt1_info = {
781 	CML_PLATFORM,
782 	.gt = 1,
783 };
784 
785 static const struct intel_device_info cml_gt2_info = {
786 	CML_PLATFORM,
787 	.gt = 2,
788 };
789 
790 #define GEN10_FEATURES \
791 	GEN9_FEATURES, \
792 	GEN(10), \
793 	.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ \
794 	.display.has_dsc = 1, \
795 	.has_coherent_ggtt = false, \
796 	GLK_COLORS
797 
798 static const struct intel_device_info cnl_info = {
799 	GEN10_FEATURES,
800 	PLATFORM(INTEL_CANNONLAKE),
801 	.gt = 2,
802 };
803 
804 #define GEN11_DEFAULT_PAGE_SIZES \
805 	.page_sizes = I915_GTT_PAGE_SIZE_4K | \
806 		      I915_GTT_PAGE_SIZE_64K | \
807 		      I915_GTT_PAGE_SIZE_2M
808 
809 #define GEN11_FEATURES \
810 	GEN10_FEATURES, \
811 	GEN11_DEFAULT_PAGE_SIZES, \
812 	.abox_mask = BIT(0), \
813 	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
814 		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
815 		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
816 	.pipe_offsets = { \
817 		[TRANSCODER_A] = PIPE_A_OFFSET, \
818 		[TRANSCODER_B] = PIPE_B_OFFSET, \
819 		[TRANSCODER_C] = PIPE_C_OFFSET, \
820 		[TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
821 		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
822 		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
823 	}, \
824 	.trans_offsets = { \
825 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
826 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
827 		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
828 		[TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
829 		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
830 		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
831 	}, \
832 	GEN(11), \
833 	.dbuf.size = 2048, \
834 	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
835 	.has_logical_ring_elsq = 1, \
836 	.color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }
837 
838 static const struct intel_device_info icl_info = {
839 	GEN11_FEATURES,
840 	PLATFORM(INTEL_ICELAKE),
841 	.platform_engine_mask =
842 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
843 };
844 
845 static const struct intel_device_info ehl_info = {
846 	GEN11_FEATURES,
847 	PLATFORM(INTEL_ELKHARTLAKE),
848 	.require_force_probe = 1,
849 	.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
850 	.ppgtt_size = 36,
851 };
852 
853 static const struct intel_device_info jsl_info = {
854 	GEN11_FEATURES,
855 	PLATFORM(INTEL_JASPERLAKE),
856 	.require_force_probe = 1,
857 	.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
858 	.ppgtt_size = 36,
859 };
860 
861 #define GEN12_FEATURES \
862 	GEN11_FEATURES, \
863 	GEN(12), \
864 	.abox_mask = GENMASK(2, 1), \
865 	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
866 	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
867 		BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
868 		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
869 	.pipe_offsets = { \
870 		[TRANSCODER_A] = PIPE_A_OFFSET, \
871 		[TRANSCODER_B] = PIPE_B_OFFSET, \
872 		[TRANSCODER_C] = PIPE_C_OFFSET, \
873 		[TRANSCODER_D] = PIPE_D_OFFSET, \
874 		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
875 		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
876 	}, \
877 	.trans_offsets = { \
878 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
879 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
880 		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
881 		[TRANSCODER_D] = TRANSCODER_D_OFFSET, \
882 		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
883 		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
884 	}, \
885 	TGL_CURSOR_OFFSETS, \
886 	.has_global_mocs = 1, \
887 	.display.has_dsb = 1
888 
889 static const struct intel_device_info tgl_info = {
890 	GEN12_FEATURES,
891 	PLATFORM(INTEL_TIGERLAKE),
892 	.display.has_modular_fia = 1,
893 	.platform_engine_mask =
894 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
895 };
896 
897 static const struct intel_device_info rkl_info = {
898 	GEN12_FEATURES,
899 	PLATFORM(INTEL_ROCKETLAKE),
900 	.abox_mask = BIT(0),
901 	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
902 	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
903 		BIT(TRANSCODER_C),
904 	.display.has_hti = 1,
905 	.display.has_psr_hw_tracking = 0,
906 	.platform_engine_mask =
907 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
908 };
909 
910 #define DGFX_FEATURES \
911 	.memory_regions = REGION_SMEM | REGION_LMEM | REGION_STOLEN_LMEM, \
912 	.has_master_unit_irq = 1, \
913 	.has_llc = 0, \
914 	.has_snoop = 1, \
915 	.is_dgfx = 1
916 
917 static const struct intel_device_info dg1_info __maybe_unused = {
918 	GEN12_FEATURES,
919 	DGFX_FEATURES,
920 	PLATFORM(INTEL_DG1),
921 	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
922 	.require_force_probe = 1,
923 	.platform_engine_mask =
924 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
925 		BIT(VCS0) | BIT(VCS2),
926 	/* Wa_16011227922 */
927 	.ppgtt_size = 47,
928 };
929 
930 static const struct intel_device_info adl_s_info = {
931 	GEN12_FEATURES,
932 	PLATFORM(INTEL_ALDERLAKE_S),
933 	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
934 	.require_force_probe = 1,
935 	.display.has_hti = 1,
936 	.display.has_psr_hw_tracking = 0,
937 	.platform_engine_mask =
938 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
939 	.dma_mask_size = 46,
940 };
941 
942 #define XE_LPD_FEATURES \
943 	.display.ver = 13,						\
944 	.display.has_psr_hw_tracking = 0,				\
945 	.abox_mask = GENMASK(1, 0),					\
946 	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
947 	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |	\
948 		BIT(TRANSCODER_C) | BIT(TRANSCODER_D),			\
949 	.dbuf.size = 4096,						\
950 	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | BIT(DBUF_S4)
951 
952 static const struct intel_device_info adl_p_info = {
953 	GEN12_FEATURES,
954 	XE_LPD_FEATURES,
955 	PLATFORM(INTEL_ALDERLAKE_P),
956 	.has_cdclk_crawl = 1,
957 	.require_force_probe = 1,
958 	.display.has_modular_fia = 1,
959 	.platform_engine_mask =
960 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
961 	.ppgtt_size = 48,
962 	.dma_mask_size = 39,
963 };
964 
965 #undef GEN
966 #undef PLATFORM
967 
968 /*
969  * Make sure any device matches here are from most specific to most
970  * general.  For example, since the Quanta match is based on the subsystem
971  * and subvendor IDs, we need it to come before the more general IVB
972  * PCI ID matches, otherwise we'll use the wrong info struct above.
973  */
974 static const struct pci_device_id pciidlist[] = {
975 	INTEL_I830_IDS(&i830_info),
976 	INTEL_I845G_IDS(&i845g_info),
977 	INTEL_I85X_IDS(&i85x_info),
978 	INTEL_I865G_IDS(&i865g_info),
979 	INTEL_I915G_IDS(&i915g_info),
980 	INTEL_I915GM_IDS(&i915gm_info),
981 	INTEL_I945G_IDS(&i945g_info),
982 	INTEL_I945GM_IDS(&i945gm_info),
983 	INTEL_I965G_IDS(&i965g_info),
984 	INTEL_G33_IDS(&g33_info),
985 	INTEL_I965GM_IDS(&i965gm_info),
986 	INTEL_GM45_IDS(&gm45_info),
987 	INTEL_G45_IDS(&g45_info),
988 	INTEL_PINEVIEW_G_IDS(&pnv_g_info),
989 	INTEL_PINEVIEW_M_IDS(&pnv_m_info),
990 	INTEL_IRONLAKE_D_IDS(&ilk_d_info),
991 	INTEL_IRONLAKE_M_IDS(&ilk_m_info),
992 	INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info),
993 	INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info),
994 	INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info),
995 	INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info),
996 	INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */
997 	INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info),
998 	INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info),
999 	INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info),
1000 	INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info),
1001 	INTEL_HSW_GT1_IDS(&hsw_gt1_info),
1002 	INTEL_HSW_GT2_IDS(&hsw_gt2_info),
1003 	INTEL_HSW_GT3_IDS(&hsw_gt3_info),
1004 	INTEL_VLV_IDS(&vlv_info),
1005 	INTEL_BDW_GT1_IDS(&bdw_gt1_info),
1006 	INTEL_BDW_GT2_IDS(&bdw_gt2_info),
1007 	INTEL_BDW_GT3_IDS(&bdw_gt3_info),
1008 	INTEL_BDW_RSVD_IDS(&bdw_rsvd_info),
1009 	INTEL_CHV_IDS(&chv_info),
1010 	INTEL_SKL_GT1_IDS(&skl_gt1_info),
1011 	INTEL_SKL_GT2_IDS(&skl_gt2_info),
1012 	INTEL_SKL_GT3_IDS(&skl_gt3_info),
1013 	INTEL_SKL_GT4_IDS(&skl_gt4_info),
1014 	INTEL_BXT_IDS(&bxt_info),
1015 	INTEL_GLK_IDS(&glk_info),
1016 	INTEL_KBL_GT1_IDS(&kbl_gt1_info),
1017 	INTEL_KBL_GT2_IDS(&kbl_gt2_info),
1018 	INTEL_KBL_GT3_IDS(&kbl_gt3_info),
1019 	INTEL_KBL_GT4_IDS(&kbl_gt3_info),
1020 	INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info),
1021 	INTEL_CFL_S_GT1_IDS(&cfl_gt1_info),
1022 	INTEL_CFL_S_GT2_IDS(&cfl_gt2_info),
1023 	INTEL_CFL_H_GT1_IDS(&cfl_gt1_info),
1024 	INTEL_CFL_H_GT2_IDS(&cfl_gt2_info),
1025 	INTEL_CFL_U_GT2_IDS(&cfl_gt2_info),
1026 	INTEL_CFL_U_GT3_IDS(&cfl_gt3_info),
1027 	INTEL_WHL_U_GT1_IDS(&cfl_gt1_info),
1028 	INTEL_WHL_U_GT2_IDS(&cfl_gt2_info),
1029 	INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info),
1030 	INTEL_WHL_U_GT3_IDS(&cfl_gt3_info),
1031 	INTEL_CML_GT1_IDS(&cml_gt1_info),
1032 	INTEL_CML_GT2_IDS(&cml_gt2_info),
1033 	INTEL_CML_U_GT1_IDS(&cml_gt1_info),
1034 	INTEL_CML_U_GT2_IDS(&cml_gt2_info),
1035 	INTEL_CNL_IDS(&cnl_info),
1036 	INTEL_ICL_11_IDS(&icl_info),
1037 	INTEL_EHL_IDS(&ehl_info),
1038 	INTEL_JSL_IDS(&jsl_info),
1039 	INTEL_TGL_12_IDS(&tgl_info),
1040 	INTEL_RKL_IDS(&rkl_info),
1041 	INTEL_ADLS_IDS(&adl_s_info),
1042 	INTEL_ADLP_IDS(&adl_p_info),
1043 	{0, 0, 0}
1044 };
1045 MODULE_DEVICE_TABLE(pci, pciidlist);
1046 
1047 static void i915_pci_remove(struct pci_dev *pdev)
1048 {
1049 	struct drm_i915_private *i915;
1050 
1051 	i915 = pci_get_drvdata(pdev);
1052 	if (!i915) /* driver load aborted, nothing to cleanup */
1053 		return;
1054 
1055 	i915_driver_remove(i915);
1056 	pci_set_drvdata(pdev, NULL);
1057 }
1058 
1059 /* is device_id present in comma separated list of ids */
1060 static bool force_probe(u16 device_id, const char *devices)
1061 {
1062 	char *s, *p, *tok;
1063 	bool ret;
1064 
1065 	if (!devices || !*devices)
1066 		return false;
1067 
1068 	/* match everything */
1069 	if (strcmp(devices, "*") == 0)
1070 		return true;
1071 
1072 	s = kstrdup(devices, GFP_KERNEL);
1073 	if (!s)
1074 		return false;
1075 
1076 	for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) {
1077 		u16 val;
1078 
1079 		if (kstrtou16(tok, 16, &val) == 0 && val == device_id) {
1080 			ret = true;
1081 			break;
1082 		}
1083 	}
1084 
1085 	kfree(s);
1086 
1087 	return ret;
1088 }
1089 
1090 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1091 {
1092 	struct intel_device_info *intel_info =
1093 		(struct intel_device_info *) ent->driver_data;
1094 	int err;
1095 
1096 	if (intel_info->require_force_probe &&
1097 	    !force_probe(pdev->device, i915_modparams.force_probe)) {
1098 		dev_info(&pdev->dev,
1099 			 "Your graphics device %04x is not properly supported by the driver in this\n"
1100 			 "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n"
1101 			 "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n"
1102 			 "or (recommended) check for kernel updates.\n",
1103 			 pdev->device, pdev->device, pdev->device);
1104 		return -ENODEV;
1105 	}
1106 
1107 	/* Only bind to function 0 of the device. Early generations
1108 	 * used function 1 as a placeholder for multi-head. This causes
1109 	 * us confusion instead, especially on the systems where both
1110 	 * functions have the same PCI-ID!
1111 	 */
1112 	if (PCI_FUNC(pdev->devfn))
1113 		return -ENODEV;
1114 
1115 	/*
1116 	 * apple-gmux is needed on dual GPU MacBook Pro
1117 	 * to probe the panel if we're the inactive GPU.
1118 	 */
1119 	if (vga_switcheroo_client_probe_defer(pdev))
1120 		return -EPROBE_DEFER;
1121 
1122 	err = i915_driver_probe(pdev, ent);
1123 	if (err)
1124 		return err;
1125 
1126 	if (i915_inject_probe_failure(pci_get_drvdata(pdev))) {
1127 		i915_pci_remove(pdev);
1128 		return -ENODEV;
1129 	}
1130 
1131 	err = i915_live_selftests(pdev);
1132 	if (err) {
1133 		i915_pci_remove(pdev);
1134 		return err > 0 ? -ENOTTY : err;
1135 	}
1136 
1137 	err = i915_perf_selftests(pdev);
1138 	if (err) {
1139 		i915_pci_remove(pdev);
1140 		return err > 0 ? -ENOTTY : err;
1141 	}
1142 
1143 	return 0;
1144 }
1145 
1146 static void i915_pci_shutdown(struct pci_dev *pdev)
1147 {
1148 	struct drm_i915_private *i915 = pci_get_drvdata(pdev);
1149 
1150 	i915_driver_shutdown(i915);
1151 }
1152 
1153 static struct pci_driver i915_pci_driver = {
1154 	.name = DRIVER_NAME,
1155 	.id_table = pciidlist,
1156 	.probe = i915_pci_probe,
1157 	.remove = i915_pci_remove,
1158 	.shutdown = i915_pci_shutdown,
1159 	.driver.pm = &i915_pm_ops,
1160 };
1161 
1162 static int __init i915_init(void)
1163 {
1164 	bool use_kms = true;
1165 	int err;
1166 
1167 	err = i915_globals_init();
1168 	if (err)
1169 		return err;
1170 
1171 	err = i915_mock_selftests();
1172 	if (err)
1173 		return err > 0 ? 0 : err;
1174 
1175 	/*
1176 	 * Enable KMS by default, unless explicitly overriden by
1177 	 * either the i915.modeset prarameter or by the
1178 	 * vga_text_mode_force boot option.
1179 	 */
1180 
1181 	if (i915_modparams.modeset == 0)
1182 		use_kms = false;
1183 
1184 	if (vgacon_text_force() && i915_modparams.modeset == -1)
1185 		use_kms = false;
1186 
1187 	if (!use_kms) {
1188 		/* Silently fail loading to not upset userspace. */
1189 		DRM_DEBUG_DRIVER("KMS disabled.\n");
1190 		return 0;
1191 	}
1192 
1193 	i915_pmu_init();
1194 
1195 	err = pci_register_driver(&i915_pci_driver);
1196 	if (err) {
1197 		i915_pmu_exit();
1198 		i915_globals_exit();
1199 		return err;
1200 	}
1201 
1202 	i915_perf_sysctl_register();
1203 	return 0;
1204 }
1205 
1206 static void __exit i915_exit(void)
1207 {
1208 	if (!i915_pci_driver.driver.owner)
1209 		return;
1210 
1211 	i915_perf_sysctl_unregister();
1212 	pci_unregister_driver(&i915_pci_driver);
1213 	i915_globals_exit();
1214 	i915_pmu_exit();
1215 }
1216 
1217 module_init(i915_init);
1218 module_exit(i915_exit);
1219 
1220 MODULE_AUTHOR("Tungsten Graphics, Inc.");
1221 MODULE_AUTHOR("Intel Corporation");
1222 
1223 MODULE_DESCRIPTION(DRIVER_DESC);
1224 MODULE_LICENSE("GPL and additional rights");
1225