1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <drm/drm_color_mgmt.h> 26 #include <drm/drm_drv.h> 27 #include <drm/i915_pciids.h> 28 29 #include "display/intel_display.h" 30 #include "gt/intel_gt_regs.h" 31 #include "gt/intel_sa_media.h" 32 #include "gem/i915_gem_object_types.h" 33 34 #include "i915_driver.h" 35 #include "i915_drv.h" 36 #include "i915_pci.h" 37 #include "i915_reg.h" 38 #include "intel_pci_config.h" 39 40 #define PLATFORM(x) .platform = (x) 41 #define GEN(x) \ 42 .__runtime.graphics.ip.ver = (x), \ 43 .__runtime.media.ip.ver = (x), \ 44 .__runtime.display.ip.ver = (x) 45 46 #define NO_DISPLAY .__runtime.pipe_mask = 0 47 48 #define I845_PIPE_OFFSETS \ 49 .display.pipe_offsets = { \ 50 [TRANSCODER_A] = PIPE_A_OFFSET, \ 51 }, \ 52 .display.trans_offsets = { \ 53 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 54 } 55 56 #define I9XX_PIPE_OFFSETS \ 57 .display.pipe_offsets = { \ 58 [TRANSCODER_A] = PIPE_A_OFFSET, \ 59 [TRANSCODER_B] = PIPE_B_OFFSET, \ 60 }, \ 61 .display.trans_offsets = { \ 62 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 63 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 64 } 65 66 #define IVB_PIPE_OFFSETS \ 67 .display.pipe_offsets = { \ 68 [TRANSCODER_A] = PIPE_A_OFFSET, \ 69 [TRANSCODER_B] = PIPE_B_OFFSET, \ 70 [TRANSCODER_C] = PIPE_C_OFFSET, \ 71 }, \ 72 .display.trans_offsets = { \ 73 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 74 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 75 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 76 } 77 78 #define HSW_PIPE_OFFSETS \ 79 .display.pipe_offsets = { \ 80 [TRANSCODER_A] = PIPE_A_OFFSET, \ 81 [TRANSCODER_B] = PIPE_B_OFFSET, \ 82 [TRANSCODER_C] = PIPE_C_OFFSET, \ 83 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 84 }, \ 85 .display.trans_offsets = { \ 86 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 87 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 88 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 89 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 90 } 91 92 #define CHV_PIPE_OFFSETS \ 93 .display.pipe_offsets = { \ 94 [TRANSCODER_A] = PIPE_A_OFFSET, \ 95 [TRANSCODER_B] = PIPE_B_OFFSET, \ 96 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \ 97 }, \ 98 .display.trans_offsets = { \ 99 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 100 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 101 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \ 102 } 103 104 #define I845_CURSOR_OFFSETS \ 105 .display.cursor_offsets = { \ 106 [PIPE_A] = CURSOR_A_OFFSET, \ 107 } 108 109 #define I9XX_CURSOR_OFFSETS \ 110 .display.cursor_offsets = { \ 111 [PIPE_A] = CURSOR_A_OFFSET, \ 112 [PIPE_B] = CURSOR_B_OFFSET, \ 113 } 114 115 #define CHV_CURSOR_OFFSETS \ 116 .display.cursor_offsets = { \ 117 [PIPE_A] = CURSOR_A_OFFSET, \ 118 [PIPE_B] = CURSOR_B_OFFSET, \ 119 [PIPE_C] = CHV_CURSOR_C_OFFSET, \ 120 } 121 122 #define IVB_CURSOR_OFFSETS \ 123 .display.cursor_offsets = { \ 124 [PIPE_A] = CURSOR_A_OFFSET, \ 125 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 126 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 127 } 128 129 #define TGL_CURSOR_OFFSETS \ 130 .display.cursor_offsets = { \ 131 [PIPE_A] = CURSOR_A_OFFSET, \ 132 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 133 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 134 [PIPE_D] = TGL_CURSOR_D_OFFSET, \ 135 } 136 137 #define I845_COLORS \ 138 .display.color = { .gamma_lut_size = 256 } 139 #define I9XX_COLORS \ 140 .display.color = { .gamma_lut_size = 129, \ 141 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 142 } 143 #define ILK_COLORS \ 144 .display.color = { .gamma_lut_size = 1024 } 145 #define IVB_COLORS \ 146 .display.color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 } 147 #define CHV_COLORS \ 148 .display.color = { \ 149 .degamma_lut_size = 65, .gamma_lut_size = 257, \ 150 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 151 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 152 } 153 #define GLK_COLORS \ 154 .display.color = { \ 155 .degamma_lut_size = 33, .gamma_lut_size = 1024, \ 156 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 157 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 158 } 159 #define ICL_COLORS \ 160 .display.color = { \ 161 .degamma_lut_size = 33, .gamma_lut_size = 262145, \ 162 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 163 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 164 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 165 } 166 167 #define LEGACY_CACHELEVEL \ 168 .cachelevel_to_pat = { \ 169 [I915_CACHE_NONE] = 0, \ 170 [I915_CACHE_LLC] = 1, \ 171 [I915_CACHE_L3_LLC] = 2, \ 172 [I915_CACHE_WT] = 3, \ 173 } 174 175 #define TGL_CACHELEVEL \ 176 .cachelevel_to_pat = { \ 177 [I915_CACHE_NONE] = 3, \ 178 [I915_CACHE_LLC] = 0, \ 179 [I915_CACHE_L3_LLC] = 0, \ 180 [I915_CACHE_WT] = 2, \ 181 } 182 183 #define PVC_CACHELEVEL \ 184 .cachelevel_to_pat = { \ 185 [I915_CACHE_NONE] = 0, \ 186 [I915_CACHE_LLC] = 3, \ 187 [I915_CACHE_L3_LLC] = 3, \ 188 [I915_CACHE_WT] = 2, \ 189 } 190 191 #define MTL_CACHELEVEL \ 192 .cachelevel_to_pat = { \ 193 [I915_CACHE_NONE] = 2, \ 194 [I915_CACHE_LLC] = 3, \ 195 [I915_CACHE_L3_LLC] = 3, \ 196 [I915_CACHE_WT] = 1, \ 197 } 198 199 /* Keep in gen based order, and chronological order within a gen */ 200 201 #define GEN_DEFAULT_PAGE_SIZES \ 202 .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K 203 204 #define GEN_DEFAULT_REGIONS \ 205 .__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_SMEM 206 207 #define I830_FEATURES \ 208 GEN(2), \ 209 .is_mobile = 1, \ 210 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 211 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 212 .display.has_overlay = 1, \ 213 .display.cursor_needs_physical = 1, \ 214 .display.overlay_needs_physical = 1, \ 215 .display.has_gmch = 1, \ 216 .gpu_reset_clobbers_display = true, \ 217 .has_3d_pipeline = 1, \ 218 .hws_needs_physical = 1, \ 219 .unfenced_needs_alignment = 1, \ 220 .__runtime.platform_engine_mask = BIT(RCS0), \ 221 .has_snoop = true, \ 222 .has_coherent_ggtt = false, \ 223 .dma_mask_size = 32, \ 224 .max_pat_index = 3, \ 225 I9XX_PIPE_OFFSETS, \ 226 I9XX_CURSOR_OFFSETS, \ 227 I9XX_COLORS, \ 228 GEN_DEFAULT_PAGE_SIZES, \ 229 GEN_DEFAULT_REGIONS, \ 230 LEGACY_CACHELEVEL 231 232 #define I845_FEATURES \ 233 GEN(2), \ 234 .__runtime.pipe_mask = BIT(PIPE_A), \ 235 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A), \ 236 .display.has_overlay = 1, \ 237 .display.overlay_needs_physical = 1, \ 238 .display.has_gmch = 1, \ 239 .has_3d_pipeline = 1, \ 240 .gpu_reset_clobbers_display = true, \ 241 .hws_needs_physical = 1, \ 242 .unfenced_needs_alignment = 1, \ 243 .__runtime.platform_engine_mask = BIT(RCS0), \ 244 .has_snoop = true, \ 245 .has_coherent_ggtt = false, \ 246 .dma_mask_size = 32, \ 247 .max_pat_index = 3, \ 248 I845_PIPE_OFFSETS, \ 249 I845_CURSOR_OFFSETS, \ 250 I845_COLORS, \ 251 GEN_DEFAULT_PAGE_SIZES, \ 252 GEN_DEFAULT_REGIONS, \ 253 LEGACY_CACHELEVEL 254 255 static const struct intel_device_info i830_info = { 256 I830_FEATURES, 257 PLATFORM(INTEL_I830), 258 }; 259 260 static const struct intel_device_info i845g_info = { 261 I845_FEATURES, 262 PLATFORM(INTEL_I845G), 263 }; 264 265 static const struct intel_device_info i85x_info = { 266 I830_FEATURES, 267 PLATFORM(INTEL_I85X), 268 .__runtime.fbc_mask = BIT(INTEL_FBC_A), 269 }; 270 271 static const struct intel_device_info i865g_info = { 272 I845_FEATURES, 273 PLATFORM(INTEL_I865G), 274 .__runtime.fbc_mask = BIT(INTEL_FBC_A), 275 }; 276 277 #define GEN3_FEATURES \ 278 GEN(3), \ 279 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 280 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 281 .display.has_gmch = 1, \ 282 .gpu_reset_clobbers_display = true, \ 283 .__runtime.platform_engine_mask = BIT(RCS0), \ 284 .has_3d_pipeline = 1, \ 285 .has_snoop = true, \ 286 .has_coherent_ggtt = true, \ 287 .dma_mask_size = 32, \ 288 .max_pat_index = 3, \ 289 I9XX_PIPE_OFFSETS, \ 290 I9XX_CURSOR_OFFSETS, \ 291 I9XX_COLORS, \ 292 GEN_DEFAULT_PAGE_SIZES, \ 293 GEN_DEFAULT_REGIONS, \ 294 LEGACY_CACHELEVEL 295 296 static const struct intel_device_info i915g_info = { 297 GEN3_FEATURES, 298 PLATFORM(INTEL_I915G), 299 .has_coherent_ggtt = false, 300 .display.cursor_needs_physical = 1, 301 .display.has_overlay = 1, 302 .display.overlay_needs_physical = 1, 303 .hws_needs_physical = 1, 304 .unfenced_needs_alignment = 1, 305 }; 306 307 static const struct intel_device_info i915gm_info = { 308 GEN3_FEATURES, 309 PLATFORM(INTEL_I915GM), 310 .is_mobile = 1, 311 .display.cursor_needs_physical = 1, 312 .display.has_overlay = 1, 313 .display.overlay_needs_physical = 1, 314 .display.supports_tv = 1, 315 .__runtime.fbc_mask = BIT(INTEL_FBC_A), 316 .hws_needs_physical = 1, 317 .unfenced_needs_alignment = 1, 318 }; 319 320 static const struct intel_device_info i945g_info = { 321 GEN3_FEATURES, 322 PLATFORM(INTEL_I945G), 323 .display.has_hotplug = 1, 324 .display.cursor_needs_physical = 1, 325 .display.has_overlay = 1, 326 .display.overlay_needs_physical = 1, 327 .hws_needs_physical = 1, 328 .unfenced_needs_alignment = 1, 329 }; 330 331 static const struct intel_device_info i945gm_info = { 332 GEN3_FEATURES, 333 PLATFORM(INTEL_I945GM), 334 .is_mobile = 1, 335 .display.has_hotplug = 1, 336 .display.cursor_needs_physical = 1, 337 .display.has_overlay = 1, 338 .display.overlay_needs_physical = 1, 339 .display.supports_tv = 1, 340 .__runtime.fbc_mask = BIT(INTEL_FBC_A), 341 .hws_needs_physical = 1, 342 .unfenced_needs_alignment = 1, 343 }; 344 345 static const struct intel_device_info g33_info = { 346 GEN3_FEATURES, 347 PLATFORM(INTEL_G33), 348 .display.has_hotplug = 1, 349 .display.has_overlay = 1, 350 .dma_mask_size = 36, 351 }; 352 353 static const struct intel_device_info pnv_g_info = { 354 GEN3_FEATURES, 355 PLATFORM(INTEL_PINEVIEW), 356 .display.has_hotplug = 1, 357 .display.has_overlay = 1, 358 .dma_mask_size = 36, 359 }; 360 361 static const struct intel_device_info pnv_m_info = { 362 GEN3_FEATURES, 363 PLATFORM(INTEL_PINEVIEW), 364 .is_mobile = 1, 365 .display.has_hotplug = 1, 366 .display.has_overlay = 1, 367 .dma_mask_size = 36, 368 }; 369 370 #define GEN4_FEATURES \ 371 GEN(4), \ 372 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 373 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 374 .display.has_hotplug = 1, \ 375 .display.has_gmch = 1, \ 376 .gpu_reset_clobbers_display = true, \ 377 .__runtime.platform_engine_mask = BIT(RCS0), \ 378 .has_3d_pipeline = 1, \ 379 .has_snoop = true, \ 380 .has_coherent_ggtt = true, \ 381 .dma_mask_size = 36, \ 382 .max_pat_index = 3, \ 383 I9XX_PIPE_OFFSETS, \ 384 I9XX_CURSOR_OFFSETS, \ 385 I9XX_COLORS, \ 386 GEN_DEFAULT_PAGE_SIZES, \ 387 GEN_DEFAULT_REGIONS, \ 388 LEGACY_CACHELEVEL 389 390 static const struct intel_device_info i965g_info = { 391 GEN4_FEATURES, 392 PLATFORM(INTEL_I965G), 393 .display.has_overlay = 1, 394 .hws_needs_physical = 1, 395 .has_snoop = false, 396 }; 397 398 static const struct intel_device_info i965gm_info = { 399 GEN4_FEATURES, 400 PLATFORM(INTEL_I965GM), 401 .is_mobile = 1, 402 .__runtime.fbc_mask = BIT(INTEL_FBC_A), 403 .display.has_overlay = 1, 404 .display.supports_tv = 1, 405 .hws_needs_physical = 1, 406 .has_snoop = false, 407 }; 408 409 static const struct intel_device_info g45_info = { 410 GEN4_FEATURES, 411 PLATFORM(INTEL_G45), 412 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0), 413 .gpu_reset_clobbers_display = false, 414 }; 415 416 static const struct intel_device_info gm45_info = { 417 GEN4_FEATURES, 418 PLATFORM(INTEL_GM45), 419 .is_mobile = 1, 420 .__runtime.fbc_mask = BIT(INTEL_FBC_A), 421 .display.supports_tv = 1, 422 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0), 423 .gpu_reset_clobbers_display = false, 424 }; 425 426 #define GEN5_FEATURES \ 427 GEN(5), \ 428 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 429 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 430 .display.has_hotplug = 1, \ 431 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0), \ 432 .has_3d_pipeline = 1, \ 433 .has_snoop = true, \ 434 .has_coherent_ggtt = true, \ 435 /* ilk does support rc6, but we do not implement [power] contexts */ \ 436 .has_rc6 = 0, \ 437 .dma_mask_size = 36, \ 438 .max_pat_index = 3, \ 439 I9XX_PIPE_OFFSETS, \ 440 I9XX_CURSOR_OFFSETS, \ 441 ILK_COLORS, \ 442 GEN_DEFAULT_PAGE_SIZES, \ 443 GEN_DEFAULT_REGIONS, \ 444 LEGACY_CACHELEVEL 445 446 static const struct intel_device_info ilk_d_info = { 447 GEN5_FEATURES, 448 PLATFORM(INTEL_IRONLAKE), 449 }; 450 451 static const struct intel_device_info ilk_m_info = { 452 GEN5_FEATURES, 453 PLATFORM(INTEL_IRONLAKE), 454 .is_mobile = 1, 455 .has_rps = true, 456 .__runtime.fbc_mask = BIT(INTEL_FBC_A), 457 }; 458 459 #define GEN6_FEATURES \ 460 GEN(6), \ 461 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 462 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 463 .display.has_hotplug = 1, \ 464 .__runtime.fbc_mask = BIT(INTEL_FBC_A), \ 465 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ 466 .has_3d_pipeline = 1, \ 467 .has_coherent_ggtt = true, \ 468 .has_llc = 1, \ 469 .has_rc6 = 1, \ 470 /* snb does support rc6p, but enabling it causes various issues */ \ 471 .has_rc6p = 0, \ 472 .has_rps = true, \ 473 .dma_mask_size = 40, \ 474 .max_pat_index = 3, \ 475 .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \ 476 .__runtime.ppgtt_size = 31, \ 477 I9XX_PIPE_OFFSETS, \ 478 I9XX_CURSOR_OFFSETS, \ 479 ILK_COLORS, \ 480 GEN_DEFAULT_PAGE_SIZES, \ 481 GEN_DEFAULT_REGIONS, \ 482 LEGACY_CACHELEVEL 483 484 #define SNB_D_PLATFORM \ 485 GEN6_FEATURES, \ 486 PLATFORM(INTEL_SANDYBRIDGE) 487 488 static const struct intel_device_info snb_d_gt1_info = { 489 SNB_D_PLATFORM, 490 .gt = 1, 491 }; 492 493 static const struct intel_device_info snb_d_gt2_info = { 494 SNB_D_PLATFORM, 495 .gt = 2, 496 }; 497 498 #define SNB_M_PLATFORM \ 499 GEN6_FEATURES, \ 500 PLATFORM(INTEL_SANDYBRIDGE), \ 501 .is_mobile = 1 502 503 504 static const struct intel_device_info snb_m_gt1_info = { 505 SNB_M_PLATFORM, 506 .gt = 1, 507 }; 508 509 static const struct intel_device_info snb_m_gt2_info = { 510 SNB_M_PLATFORM, 511 .gt = 2, 512 }; 513 514 #define GEN7_FEATURES \ 515 GEN(7), \ 516 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ 517 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \ 518 .display.has_hotplug = 1, \ 519 .__runtime.fbc_mask = BIT(INTEL_FBC_A), \ 520 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ 521 .has_3d_pipeline = 1, \ 522 .has_coherent_ggtt = true, \ 523 .has_llc = 1, \ 524 .has_rc6 = 1, \ 525 .has_rc6p = 1, \ 526 .has_reset_engine = true, \ 527 .has_rps = true, \ 528 .dma_mask_size = 40, \ 529 .max_pat_index = 3, \ 530 .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \ 531 .__runtime.ppgtt_size = 31, \ 532 IVB_PIPE_OFFSETS, \ 533 IVB_CURSOR_OFFSETS, \ 534 IVB_COLORS, \ 535 GEN_DEFAULT_PAGE_SIZES, \ 536 GEN_DEFAULT_REGIONS, \ 537 LEGACY_CACHELEVEL 538 539 #define IVB_D_PLATFORM \ 540 GEN7_FEATURES, \ 541 PLATFORM(INTEL_IVYBRIDGE), \ 542 .has_l3_dpf = 1 543 544 static const struct intel_device_info ivb_d_gt1_info = { 545 IVB_D_PLATFORM, 546 .gt = 1, 547 }; 548 549 static const struct intel_device_info ivb_d_gt2_info = { 550 IVB_D_PLATFORM, 551 .gt = 2, 552 }; 553 554 #define IVB_M_PLATFORM \ 555 GEN7_FEATURES, \ 556 PLATFORM(INTEL_IVYBRIDGE), \ 557 .is_mobile = 1, \ 558 .has_l3_dpf = 1 559 560 static const struct intel_device_info ivb_m_gt1_info = { 561 IVB_M_PLATFORM, 562 .gt = 1, 563 }; 564 565 static const struct intel_device_info ivb_m_gt2_info = { 566 IVB_M_PLATFORM, 567 .gt = 2, 568 }; 569 570 static const struct intel_device_info ivb_q_info = { 571 GEN7_FEATURES, 572 PLATFORM(INTEL_IVYBRIDGE), 573 NO_DISPLAY, 574 .gt = 2, 575 .has_l3_dpf = 1, 576 }; 577 578 static const struct intel_device_info vlv_info = { 579 PLATFORM(INTEL_VALLEYVIEW), 580 GEN(7), 581 .is_lp = 1, 582 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), 583 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), 584 .has_runtime_pm = 1, 585 .has_rc6 = 1, 586 .has_reset_engine = true, 587 .has_rps = true, 588 .display.has_gmch = 1, 589 .display.has_hotplug = 1, 590 .dma_mask_size = 40, 591 .max_pat_index = 3, 592 .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, 593 .__runtime.ppgtt_size = 31, 594 .has_snoop = true, 595 .has_coherent_ggtt = false, 596 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), 597 .display.mmio_offset = VLV_DISPLAY_BASE, 598 I9XX_PIPE_OFFSETS, 599 I9XX_CURSOR_OFFSETS, 600 I9XX_COLORS, 601 GEN_DEFAULT_PAGE_SIZES, 602 GEN_DEFAULT_REGIONS, 603 LEGACY_CACHELEVEL, 604 }; 605 606 #define G75_FEATURES \ 607 GEN7_FEATURES, \ 608 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ 609 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 610 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \ 611 .display.has_ddi = 1, \ 612 .display.has_fpga_dbg = 1, \ 613 .display.has_dp_mst = 1, \ 614 .has_rc6p = 0 /* RC6p removed-by HSW */, \ 615 HSW_PIPE_OFFSETS, \ 616 .has_runtime_pm = 1 617 618 #define HSW_PLATFORM \ 619 G75_FEATURES, \ 620 PLATFORM(INTEL_HASWELL), \ 621 .has_l3_dpf = 1 622 623 static const struct intel_device_info hsw_gt1_info = { 624 HSW_PLATFORM, 625 .gt = 1, 626 }; 627 628 static const struct intel_device_info hsw_gt2_info = { 629 HSW_PLATFORM, 630 .gt = 2, 631 }; 632 633 static const struct intel_device_info hsw_gt3_info = { 634 HSW_PLATFORM, 635 .gt = 3, 636 }; 637 638 #define GEN8_FEATURES \ 639 G75_FEATURES, \ 640 GEN(8), \ 641 .has_logical_ring_contexts = 1, \ 642 .dma_mask_size = 39, \ 643 .__runtime.ppgtt_type = INTEL_PPGTT_FULL, \ 644 .__runtime.ppgtt_size = 48, \ 645 .has_64bit_reloc = 1 646 647 #define BDW_PLATFORM \ 648 GEN8_FEATURES, \ 649 PLATFORM(INTEL_BROADWELL) 650 651 static const struct intel_device_info bdw_gt1_info = { 652 BDW_PLATFORM, 653 .gt = 1, 654 }; 655 656 static const struct intel_device_info bdw_gt2_info = { 657 BDW_PLATFORM, 658 .gt = 2, 659 }; 660 661 static const struct intel_device_info bdw_rsvd_info = { 662 BDW_PLATFORM, 663 .gt = 3, 664 /* According to the device ID those devices are GT3, they were 665 * previously treated as not GT3, keep it like that. 666 */ 667 }; 668 669 static const struct intel_device_info bdw_gt3_info = { 670 BDW_PLATFORM, 671 .gt = 3, 672 .__runtime.platform_engine_mask = 673 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 674 }; 675 676 static const struct intel_device_info chv_info = { 677 PLATFORM(INTEL_CHERRYVIEW), 678 GEN(8), 679 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 680 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), 681 .display.has_hotplug = 1, 682 .is_lp = 1, 683 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), 684 .has_64bit_reloc = 1, 685 .has_runtime_pm = 1, 686 .has_rc6 = 1, 687 .has_rps = true, 688 .has_logical_ring_contexts = 1, 689 .display.has_gmch = 1, 690 .dma_mask_size = 39, 691 .max_pat_index = 3, 692 .__runtime.ppgtt_type = INTEL_PPGTT_FULL, 693 .__runtime.ppgtt_size = 32, 694 .has_reset_engine = 1, 695 .has_snoop = true, 696 .has_coherent_ggtt = false, 697 .display.mmio_offset = VLV_DISPLAY_BASE, 698 CHV_PIPE_OFFSETS, 699 CHV_CURSOR_OFFSETS, 700 CHV_COLORS, 701 GEN_DEFAULT_PAGE_SIZES, 702 GEN_DEFAULT_REGIONS, 703 LEGACY_CACHELEVEL, 704 }; 705 706 #define GEN9_DEFAULT_PAGE_SIZES \ 707 .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \ 708 I915_GTT_PAGE_SIZE_64K 709 710 #define GEN9_FEATURES \ 711 GEN8_FEATURES, \ 712 GEN(9), \ 713 GEN9_DEFAULT_PAGE_SIZES, \ 714 .__runtime.has_dmc = 1, \ 715 .has_gt_uc = 1, \ 716 .__runtime.has_hdcp = 1, \ 717 .display.has_ipc = 1, \ 718 .display.has_psr = 1, \ 719 .display.has_psr_hw_tracking = 1, \ 720 .display.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \ 721 .display.dbuf.slice_mask = BIT(DBUF_S1) 722 723 #define SKL_PLATFORM \ 724 GEN9_FEATURES, \ 725 PLATFORM(INTEL_SKYLAKE) 726 727 static const struct intel_device_info skl_gt1_info = { 728 SKL_PLATFORM, 729 .gt = 1, 730 }; 731 732 static const struct intel_device_info skl_gt2_info = { 733 SKL_PLATFORM, 734 .gt = 2, 735 }; 736 737 #define SKL_GT3_PLUS_PLATFORM \ 738 SKL_PLATFORM, \ 739 .__runtime.platform_engine_mask = \ 740 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1) 741 742 743 static const struct intel_device_info skl_gt3_info = { 744 SKL_GT3_PLUS_PLATFORM, 745 .gt = 3, 746 }; 747 748 static const struct intel_device_info skl_gt4_info = { 749 SKL_GT3_PLUS_PLATFORM, 750 .gt = 4, 751 }; 752 753 #define GEN9_LP_FEATURES \ 754 GEN(9), \ 755 .is_lp = 1, \ 756 .display.dbuf.slice_mask = BIT(DBUF_S1), \ 757 .display.has_hotplug = 1, \ 758 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ 759 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ 760 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 761 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ 762 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \ 763 .has_3d_pipeline = 1, \ 764 .has_64bit_reloc = 1, \ 765 .display.has_ddi = 1, \ 766 .display.has_fpga_dbg = 1, \ 767 .__runtime.fbc_mask = BIT(INTEL_FBC_A), \ 768 .__runtime.has_hdcp = 1, \ 769 .display.has_psr = 1, \ 770 .display.has_psr_hw_tracking = 1, \ 771 .has_runtime_pm = 1, \ 772 .__runtime.has_dmc = 1, \ 773 .has_rc6 = 1, \ 774 .has_rps = true, \ 775 .display.has_dp_mst = 1, \ 776 .has_logical_ring_contexts = 1, \ 777 .has_gt_uc = 1, \ 778 .dma_mask_size = 39, \ 779 .__runtime.ppgtt_type = INTEL_PPGTT_FULL, \ 780 .__runtime.ppgtt_size = 48, \ 781 .has_reset_engine = 1, \ 782 .has_snoop = true, \ 783 .has_coherent_ggtt = false, \ 784 .display.has_ipc = 1, \ 785 .max_pat_index = 3, \ 786 HSW_PIPE_OFFSETS, \ 787 IVB_CURSOR_OFFSETS, \ 788 IVB_COLORS, \ 789 GEN9_DEFAULT_PAGE_SIZES, \ 790 GEN_DEFAULT_REGIONS, \ 791 LEGACY_CACHELEVEL 792 793 static const struct intel_device_info bxt_info = { 794 GEN9_LP_FEATURES, 795 PLATFORM(INTEL_BROXTON), 796 .display.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */ 797 }; 798 799 static const struct intel_device_info glk_info = { 800 GEN9_LP_FEATURES, 801 PLATFORM(INTEL_GEMINILAKE), 802 .__runtime.display.ip.ver = 10, 803 .display.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ 804 GLK_COLORS, 805 }; 806 807 #define KBL_PLATFORM \ 808 GEN9_FEATURES, \ 809 PLATFORM(INTEL_KABYLAKE) 810 811 static const struct intel_device_info kbl_gt1_info = { 812 KBL_PLATFORM, 813 .gt = 1, 814 }; 815 816 static const struct intel_device_info kbl_gt2_info = { 817 KBL_PLATFORM, 818 .gt = 2, 819 }; 820 821 static const struct intel_device_info kbl_gt3_info = { 822 KBL_PLATFORM, 823 .gt = 3, 824 .__runtime.platform_engine_mask = 825 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 826 }; 827 828 #define CFL_PLATFORM \ 829 GEN9_FEATURES, \ 830 PLATFORM(INTEL_COFFEELAKE) 831 832 static const struct intel_device_info cfl_gt1_info = { 833 CFL_PLATFORM, 834 .gt = 1, 835 }; 836 837 static const struct intel_device_info cfl_gt2_info = { 838 CFL_PLATFORM, 839 .gt = 2, 840 }; 841 842 static const struct intel_device_info cfl_gt3_info = { 843 CFL_PLATFORM, 844 .gt = 3, 845 .__runtime.platform_engine_mask = 846 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 847 }; 848 849 #define CML_PLATFORM \ 850 GEN9_FEATURES, \ 851 PLATFORM(INTEL_COMETLAKE) 852 853 static const struct intel_device_info cml_gt1_info = { 854 CML_PLATFORM, 855 .gt = 1, 856 }; 857 858 static const struct intel_device_info cml_gt2_info = { 859 CML_PLATFORM, 860 .gt = 2, 861 }; 862 863 #define GEN11_DEFAULT_PAGE_SIZES \ 864 .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \ 865 I915_GTT_PAGE_SIZE_64K | \ 866 I915_GTT_PAGE_SIZE_2M 867 868 #define GEN11_FEATURES \ 869 GEN9_FEATURES, \ 870 GEN11_DEFAULT_PAGE_SIZES, \ 871 .display.abox_mask = BIT(0), \ 872 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 873 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ 874 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ 875 .display.pipe_offsets = { \ 876 [TRANSCODER_A] = PIPE_A_OFFSET, \ 877 [TRANSCODER_B] = PIPE_B_OFFSET, \ 878 [TRANSCODER_C] = PIPE_C_OFFSET, \ 879 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 880 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 881 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 882 }, \ 883 .display.trans_offsets = { \ 884 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 885 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 886 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 887 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 888 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 889 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 890 }, \ 891 GEN(11), \ 892 ICL_COLORS, \ 893 .display.dbuf.size = 2048, \ 894 .display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \ 895 .__runtime.has_dsc = 1, \ 896 .has_coherent_ggtt = false, \ 897 .has_logical_ring_elsq = 1 898 899 static const struct intel_device_info icl_info = { 900 GEN11_FEATURES, 901 PLATFORM(INTEL_ICELAKE), 902 .__runtime.platform_engine_mask = 903 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 904 }; 905 906 static const struct intel_device_info ehl_info = { 907 GEN11_FEATURES, 908 PLATFORM(INTEL_ELKHARTLAKE), 909 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0), 910 .__runtime.ppgtt_size = 36, 911 }; 912 913 static const struct intel_device_info jsl_info = { 914 GEN11_FEATURES, 915 PLATFORM(INTEL_JASPERLAKE), 916 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0), 917 .__runtime.ppgtt_size = 36, 918 }; 919 920 #define GEN12_FEATURES \ 921 GEN11_FEATURES, \ 922 GEN(12), \ 923 .display.abox_mask = GENMASK(2, 1), \ 924 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ 925 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 926 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \ 927 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ 928 .display.pipe_offsets = { \ 929 [TRANSCODER_A] = PIPE_A_OFFSET, \ 930 [TRANSCODER_B] = PIPE_B_OFFSET, \ 931 [TRANSCODER_C] = PIPE_C_OFFSET, \ 932 [TRANSCODER_D] = PIPE_D_OFFSET, \ 933 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 934 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 935 }, \ 936 .display.trans_offsets = { \ 937 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 938 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 939 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 940 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ 941 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 942 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 943 }, \ 944 TGL_CURSOR_OFFSETS, \ 945 TGL_CACHELEVEL, \ 946 .has_global_mocs = 1, \ 947 .has_pxp = 1, \ 948 .display.has_dsb = 1, \ 949 .max_pat_index = 3 950 951 static const struct intel_device_info tgl_info = { 952 GEN12_FEATURES, 953 PLATFORM(INTEL_TIGERLAKE), 954 .__runtime.platform_engine_mask = 955 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 956 }; 957 958 static const struct intel_device_info rkl_info = { 959 GEN12_FEATURES, 960 PLATFORM(INTEL_ROCKETLAKE), 961 .display.abox_mask = BIT(0), 962 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 963 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 964 BIT(TRANSCODER_C), 965 .display.has_hti = 1, 966 .display.has_psr_hw_tracking = 0, 967 .__runtime.platform_engine_mask = 968 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0), 969 }; 970 971 #define DGFX_FEATURES \ 972 .__runtime.memory_regions = REGION_SMEM | REGION_LMEM | REGION_STOLEN_LMEM, \ 973 .has_llc = 0, \ 974 .has_pxp = 0, \ 975 .has_snoop = 1, \ 976 .is_dgfx = 1, \ 977 .has_heci_gscfi = 1 978 979 static const struct intel_device_info dg1_info = { 980 GEN12_FEATURES, 981 DGFX_FEATURES, 982 .__runtime.graphics.ip.rel = 10, 983 PLATFORM(INTEL_DG1), 984 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 985 .require_force_probe = 1, 986 .__runtime.platform_engine_mask = 987 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | 988 BIT(VCS0) | BIT(VCS2), 989 /* Wa_16011227922 */ 990 .__runtime.ppgtt_size = 47, 991 }; 992 993 static const struct intel_device_info adl_s_info = { 994 GEN12_FEATURES, 995 PLATFORM(INTEL_ALDERLAKE_S), 996 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 997 .display.has_hti = 1, 998 .display.has_psr_hw_tracking = 0, 999 .__runtime.platform_engine_mask = 1000 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 1001 .dma_mask_size = 39, 1002 }; 1003 1004 #define XE_LPD_FEATURES \ 1005 .display.abox_mask = GENMASK(1, 0), \ 1006 .display.color = { \ 1007 .degamma_lut_size = 129, .gamma_lut_size = 1024, \ 1008 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 1009 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 1010 }, \ 1011 .display.dbuf.size = 4096, \ 1012 .display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \ 1013 BIT(DBUF_S4), \ 1014 .display.has_ddi = 1, \ 1015 .__runtime.has_dmc = 1, \ 1016 .display.has_dp_mst = 1, \ 1017 .display.has_dsb = 1, \ 1018 .__runtime.has_dsc = 1, \ 1019 .__runtime.fbc_mask = BIT(INTEL_FBC_A), \ 1020 .display.has_fpga_dbg = 1, \ 1021 .__runtime.has_hdcp = 1, \ 1022 .display.has_hotplug = 1, \ 1023 .display.has_ipc = 1, \ 1024 .display.has_psr = 1, \ 1025 .__runtime.display.ip.ver = 13, \ 1026 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ 1027 .display.pipe_offsets = { \ 1028 [TRANSCODER_A] = PIPE_A_OFFSET, \ 1029 [TRANSCODER_B] = PIPE_B_OFFSET, \ 1030 [TRANSCODER_C] = PIPE_C_OFFSET, \ 1031 [TRANSCODER_D] = PIPE_D_OFFSET, \ 1032 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 1033 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 1034 }, \ 1035 .display.trans_offsets = { \ 1036 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 1037 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 1038 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 1039 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ 1040 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 1041 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 1042 }, \ 1043 TGL_CURSOR_OFFSETS 1044 1045 static const struct intel_device_info adl_p_info = { 1046 GEN12_FEATURES, 1047 XE_LPD_FEATURES, 1048 PLATFORM(INTEL_ALDERLAKE_P), 1049 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 1050 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | 1051 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), 1052 .display.has_cdclk_crawl = 1, 1053 .display.has_psr_hw_tracking = 0, 1054 .__runtime.platform_engine_mask = 1055 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 1056 .__runtime.ppgtt_size = 48, 1057 .dma_mask_size = 39, 1058 }; 1059 1060 #undef GEN 1061 1062 #define XE_HP_PAGE_SIZES \ 1063 .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \ 1064 I915_GTT_PAGE_SIZE_64K | \ 1065 I915_GTT_PAGE_SIZE_2M 1066 1067 #define XE_HP_FEATURES \ 1068 .__runtime.graphics.ip.ver = 12, \ 1069 .__runtime.graphics.ip.rel = 50, \ 1070 XE_HP_PAGE_SIZES, \ 1071 TGL_CACHELEVEL, \ 1072 .dma_mask_size = 46, \ 1073 .has_3d_pipeline = 1, \ 1074 .has_64bit_reloc = 1, \ 1075 .has_flat_ccs = 1, \ 1076 .has_4tile = 1, \ 1077 .has_global_mocs = 1, \ 1078 .has_gt_uc = 1, \ 1079 .has_llc = 1, \ 1080 .has_logical_ring_contexts = 1, \ 1081 .has_logical_ring_elsq = 1, \ 1082 .has_mslice_steering = 1, \ 1083 .has_oa_bpc_reporting = 1, \ 1084 .has_oa_slice_contrib_limits = 1, \ 1085 .has_oam = 1, \ 1086 .has_rc6 = 1, \ 1087 .has_reset_engine = 1, \ 1088 .has_rps = 1, \ 1089 .has_runtime_pm = 1, \ 1090 .max_pat_index = 3, \ 1091 .__runtime.ppgtt_size = 48, \ 1092 .__runtime.ppgtt_type = INTEL_PPGTT_FULL 1093 1094 #define XE_HPM_FEATURES \ 1095 .__runtime.media.ip.ver = 12, \ 1096 .__runtime.media.ip.rel = 50 1097 1098 __maybe_unused 1099 static const struct intel_device_info xehpsdv_info = { 1100 XE_HP_FEATURES, 1101 XE_HPM_FEATURES, 1102 DGFX_FEATURES, 1103 PLATFORM(INTEL_XEHPSDV), 1104 NO_DISPLAY, 1105 .has_64k_pages = 1, 1106 .has_media_ratio_mode = 1, 1107 .__runtime.platform_engine_mask = 1108 BIT(RCS0) | BIT(BCS0) | 1109 BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) | 1110 BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) | 1111 BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7) | 1112 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3), 1113 .require_force_probe = 1, 1114 }; 1115 1116 #define DG2_FEATURES \ 1117 XE_HP_FEATURES, \ 1118 XE_HPM_FEATURES, \ 1119 DGFX_FEATURES, \ 1120 .__runtime.graphics.ip.rel = 55, \ 1121 .__runtime.media.ip.rel = 55, \ 1122 PLATFORM(INTEL_DG2), \ 1123 .has_64k_pages = 1, \ 1124 .has_guc_deprivilege = 1, \ 1125 .has_heci_pxp = 1, \ 1126 .has_media_ratio_mode = 1, \ 1127 .display.has_cdclk_squash = 1, \ 1128 .__runtime.platform_engine_mask = \ 1129 BIT(RCS0) | BIT(BCS0) | \ 1130 BIT(VECS0) | BIT(VECS1) | \ 1131 BIT(VCS0) | BIT(VCS2) | \ 1132 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3) 1133 1134 static const struct intel_device_info dg2_info = { 1135 DG2_FEATURES, 1136 XE_LPD_FEATURES, 1137 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 1138 BIT(TRANSCODER_C) | BIT(TRANSCODER_D), 1139 }; 1140 1141 static const struct intel_device_info ats_m_info = { 1142 DG2_FEATURES, 1143 NO_DISPLAY, 1144 .require_force_probe = 1, 1145 .tuning_thread_rr_after_dep = 1, 1146 }; 1147 1148 #define XE_HPC_FEATURES \ 1149 XE_HP_FEATURES, \ 1150 .dma_mask_size = 52, \ 1151 .has_3d_pipeline = 0, \ 1152 .has_guc_deprivilege = 1, \ 1153 .has_l3_ccs_read = 1, \ 1154 .has_mslice_steering = 0, \ 1155 .has_one_eu_per_fuse_bit = 1 1156 1157 __maybe_unused 1158 static const struct intel_device_info pvc_info = { 1159 XE_HPC_FEATURES, 1160 XE_HPM_FEATURES, 1161 DGFX_FEATURES, 1162 .__runtime.graphics.ip.rel = 60, 1163 .__runtime.media.ip.rel = 60, 1164 PLATFORM(INTEL_PONTEVECCHIO), 1165 NO_DISPLAY, 1166 .has_flat_ccs = 0, 1167 .max_pat_index = 7, 1168 .__runtime.platform_engine_mask = 1169 BIT(BCS0) | 1170 BIT(VCS0) | 1171 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3), 1172 .require_force_probe = 1, 1173 PVC_CACHELEVEL, 1174 }; 1175 1176 #define XE_LPDP_FEATURES \ 1177 XE_LPD_FEATURES, \ 1178 .__runtime.display.ip.ver = 14, \ 1179 .display.has_cdclk_crawl = 1, \ 1180 .display.has_cdclk_squash = 1, \ 1181 .__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B) 1182 1183 static const struct intel_gt_definition xelpmp_extra_gt[] = { 1184 { 1185 .type = GT_MEDIA, 1186 .name = "Standalone Media GT", 1187 .gsi_offset = MTL_MEDIA_GSI_BASE, 1188 .engine_mask = BIT(VECS0) | BIT(VCS0) | BIT(VCS2) | BIT(GSC0), 1189 }, 1190 {} 1191 }; 1192 1193 static const struct intel_device_info mtl_info = { 1194 XE_HP_FEATURES, 1195 XE_LPDP_FEATURES, 1196 /* 1197 * Real graphics IP version will be obtained from hardware GMD_ID 1198 * register. Value provided here is just for sanity checking. 1199 */ 1200 .__runtime.graphics.ip.ver = 12, 1201 .__runtime.graphics.ip.rel = 70, 1202 .__runtime.media.ip.ver = 13, 1203 PLATFORM(INTEL_METEORLAKE), 1204 .extra_gt_list = xelpmp_extra_gt, 1205 .has_flat_ccs = 0, 1206 .has_gmd_id = 1, 1207 .has_guc_deprivilege = 1, 1208 .has_llc = 0, 1209 .has_mslice_steering = 0, 1210 .has_snoop = 1, 1211 .max_pat_index = 4, 1212 .__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM, 1213 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0), 1214 .require_force_probe = 1, 1215 MTL_CACHELEVEL, 1216 }; 1217 1218 #undef PLATFORM 1219 1220 /* 1221 * Make sure any device matches here are from most specific to most 1222 * general. For example, since the Quanta match is based on the subsystem 1223 * and subvendor IDs, we need it to come before the more general IVB 1224 * PCI ID matches, otherwise we'll use the wrong info struct above. 1225 */ 1226 static const struct pci_device_id pciidlist[] = { 1227 INTEL_I830_IDS(&i830_info), 1228 INTEL_I845G_IDS(&i845g_info), 1229 INTEL_I85X_IDS(&i85x_info), 1230 INTEL_I865G_IDS(&i865g_info), 1231 INTEL_I915G_IDS(&i915g_info), 1232 INTEL_I915GM_IDS(&i915gm_info), 1233 INTEL_I945G_IDS(&i945g_info), 1234 INTEL_I945GM_IDS(&i945gm_info), 1235 INTEL_I965G_IDS(&i965g_info), 1236 INTEL_G33_IDS(&g33_info), 1237 INTEL_I965GM_IDS(&i965gm_info), 1238 INTEL_GM45_IDS(&gm45_info), 1239 INTEL_G45_IDS(&g45_info), 1240 INTEL_PINEVIEW_G_IDS(&pnv_g_info), 1241 INTEL_PINEVIEW_M_IDS(&pnv_m_info), 1242 INTEL_IRONLAKE_D_IDS(&ilk_d_info), 1243 INTEL_IRONLAKE_M_IDS(&ilk_m_info), 1244 INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info), 1245 INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info), 1246 INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info), 1247 INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info), 1248 INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */ 1249 INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info), 1250 INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info), 1251 INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info), 1252 INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info), 1253 INTEL_HSW_GT1_IDS(&hsw_gt1_info), 1254 INTEL_HSW_GT2_IDS(&hsw_gt2_info), 1255 INTEL_HSW_GT3_IDS(&hsw_gt3_info), 1256 INTEL_VLV_IDS(&vlv_info), 1257 INTEL_BDW_GT1_IDS(&bdw_gt1_info), 1258 INTEL_BDW_GT2_IDS(&bdw_gt2_info), 1259 INTEL_BDW_GT3_IDS(&bdw_gt3_info), 1260 INTEL_BDW_RSVD_IDS(&bdw_rsvd_info), 1261 INTEL_CHV_IDS(&chv_info), 1262 INTEL_SKL_GT1_IDS(&skl_gt1_info), 1263 INTEL_SKL_GT2_IDS(&skl_gt2_info), 1264 INTEL_SKL_GT3_IDS(&skl_gt3_info), 1265 INTEL_SKL_GT4_IDS(&skl_gt4_info), 1266 INTEL_BXT_IDS(&bxt_info), 1267 INTEL_GLK_IDS(&glk_info), 1268 INTEL_KBL_GT1_IDS(&kbl_gt1_info), 1269 INTEL_KBL_GT2_IDS(&kbl_gt2_info), 1270 INTEL_KBL_GT3_IDS(&kbl_gt3_info), 1271 INTEL_KBL_GT4_IDS(&kbl_gt3_info), 1272 INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info), 1273 INTEL_CFL_S_GT1_IDS(&cfl_gt1_info), 1274 INTEL_CFL_S_GT2_IDS(&cfl_gt2_info), 1275 INTEL_CFL_H_GT1_IDS(&cfl_gt1_info), 1276 INTEL_CFL_H_GT2_IDS(&cfl_gt2_info), 1277 INTEL_CFL_U_GT2_IDS(&cfl_gt2_info), 1278 INTEL_CFL_U_GT3_IDS(&cfl_gt3_info), 1279 INTEL_WHL_U_GT1_IDS(&cfl_gt1_info), 1280 INTEL_WHL_U_GT2_IDS(&cfl_gt2_info), 1281 INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info), 1282 INTEL_WHL_U_GT3_IDS(&cfl_gt3_info), 1283 INTEL_CML_GT1_IDS(&cml_gt1_info), 1284 INTEL_CML_GT2_IDS(&cml_gt2_info), 1285 INTEL_CML_U_GT1_IDS(&cml_gt1_info), 1286 INTEL_CML_U_GT2_IDS(&cml_gt2_info), 1287 INTEL_ICL_11_IDS(&icl_info), 1288 INTEL_EHL_IDS(&ehl_info), 1289 INTEL_JSL_IDS(&jsl_info), 1290 INTEL_TGL_12_IDS(&tgl_info), 1291 INTEL_RKL_IDS(&rkl_info), 1292 INTEL_ADLS_IDS(&adl_s_info), 1293 INTEL_ADLP_IDS(&adl_p_info), 1294 INTEL_ADLN_IDS(&adl_p_info), 1295 INTEL_DG1_IDS(&dg1_info), 1296 INTEL_RPLS_IDS(&adl_s_info), 1297 INTEL_RPLP_IDS(&adl_p_info), 1298 INTEL_DG2_IDS(&dg2_info), 1299 INTEL_ATS_M_IDS(&ats_m_info), 1300 INTEL_MTL_IDS(&mtl_info), 1301 {0, 0, 0} 1302 }; 1303 MODULE_DEVICE_TABLE(pci, pciidlist); 1304 1305 static void i915_pci_remove(struct pci_dev *pdev) 1306 { 1307 struct drm_i915_private *i915; 1308 1309 i915 = pci_get_drvdata(pdev); 1310 if (!i915) /* driver load aborted, nothing to cleanup */ 1311 return; 1312 1313 i915_driver_remove(i915); 1314 pci_set_drvdata(pdev, NULL); 1315 } 1316 1317 /* is device_id present in comma separated list of ids */ 1318 static bool device_id_in_list(u16 device_id, const char *devices, bool negative) 1319 { 1320 char *s, *p, *tok; 1321 bool ret; 1322 1323 if (!devices || !*devices) 1324 return false; 1325 1326 /* match everything */ 1327 if (negative && strcmp(devices, "!*") == 0) 1328 return true; 1329 if (!negative && strcmp(devices, "*") == 0) 1330 return true; 1331 1332 s = kstrdup(devices, GFP_KERNEL); 1333 if (!s) 1334 return false; 1335 1336 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) { 1337 u16 val; 1338 1339 if (negative && tok[0] == '!') 1340 tok++; 1341 else if ((negative && tok[0] != '!') || 1342 (!negative && tok[0] == '!')) 1343 continue; 1344 1345 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) { 1346 ret = true; 1347 break; 1348 } 1349 } 1350 1351 kfree(s); 1352 1353 return ret; 1354 } 1355 1356 static bool id_forced(u16 device_id) 1357 { 1358 return device_id_in_list(device_id, i915_modparams.force_probe, false); 1359 } 1360 1361 static bool id_blocked(u16 device_id) 1362 { 1363 return device_id_in_list(device_id, i915_modparams.force_probe, true); 1364 } 1365 1366 bool i915_pci_resource_valid(struct pci_dev *pdev, int bar) 1367 { 1368 if (!pci_resource_flags(pdev, bar)) 1369 return false; 1370 1371 if (pci_resource_flags(pdev, bar) & IORESOURCE_UNSET) 1372 return false; 1373 1374 if (!pci_resource_len(pdev, bar)) 1375 return false; 1376 1377 return true; 1378 } 1379 1380 static bool intel_mmio_bar_valid(struct pci_dev *pdev, struct intel_device_info *intel_info) 1381 { 1382 return i915_pci_resource_valid(pdev, intel_mmio_bar(intel_info->__runtime.graphics.ip.ver)); 1383 } 1384 1385 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1386 { 1387 struct intel_device_info *intel_info = 1388 (struct intel_device_info *) ent->driver_data; 1389 int err; 1390 1391 if (intel_info->require_force_probe && !id_forced(pdev->device)) { 1392 dev_info(&pdev->dev, 1393 "Your graphics device %04x is not properly supported by i915 in this\n" 1394 "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n" 1395 "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n" 1396 "or (recommended) check for kernel updates.\n", 1397 pdev->device, pdev->device, pdev->device); 1398 return -ENODEV; 1399 } 1400 1401 if (id_blocked(pdev->device)) { 1402 dev_info(&pdev->dev, "I915 probe blocked for Device ID %04x.\n", 1403 pdev->device); 1404 return -ENODEV; 1405 } 1406 1407 /* Only bind to function 0 of the device. Early generations 1408 * used function 1 as a placeholder for multi-head. This causes 1409 * us confusion instead, especially on the systems where both 1410 * functions have the same PCI-ID! 1411 */ 1412 if (PCI_FUNC(pdev->devfn)) 1413 return -ENODEV; 1414 1415 if (!intel_mmio_bar_valid(pdev, intel_info)) 1416 return -ENXIO; 1417 1418 /* Detect if we need to wait for other drivers early on */ 1419 if (intel_modeset_probe_defer(pdev)) 1420 return -EPROBE_DEFER; 1421 1422 err = i915_driver_probe(pdev, ent); 1423 if (err) 1424 return err; 1425 1426 if (i915_inject_probe_failure(pci_get_drvdata(pdev))) { 1427 i915_pci_remove(pdev); 1428 return -ENODEV; 1429 } 1430 1431 err = i915_live_selftests(pdev); 1432 if (err) { 1433 i915_pci_remove(pdev); 1434 return err > 0 ? -ENOTTY : err; 1435 } 1436 1437 err = i915_perf_selftests(pdev); 1438 if (err) { 1439 i915_pci_remove(pdev); 1440 return err > 0 ? -ENOTTY : err; 1441 } 1442 1443 return 0; 1444 } 1445 1446 static void i915_pci_shutdown(struct pci_dev *pdev) 1447 { 1448 struct drm_i915_private *i915 = pci_get_drvdata(pdev); 1449 1450 i915_driver_shutdown(i915); 1451 } 1452 1453 static struct pci_driver i915_pci_driver = { 1454 .name = DRIVER_NAME, 1455 .id_table = pciidlist, 1456 .probe = i915_pci_probe, 1457 .remove = i915_pci_remove, 1458 .shutdown = i915_pci_shutdown, 1459 .driver.pm = &i915_pm_ops, 1460 }; 1461 1462 int i915_pci_register_driver(void) 1463 { 1464 return pci_register_driver(&i915_pci_driver); 1465 } 1466 1467 void i915_pci_unregister_driver(void) 1468 { 1469 pci_unregister_driver(&i915_pci_driver); 1470 } 1471