1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/console.h> 26 #include <linux/vgaarb.h> 27 #include <linux/vga_switcheroo.h> 28 29 #include <drm/drm_drv.h> 30 31 #include "i915_drv.h" 32 #include "i915_selftest.h" 33 34 #define PLATFORM(x) .platform = (x), .platform_mask = BIT(x) 35 #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1) 36 37 #define GEN_DEFAULT_PIPEOFFSETS \ 38 .pipe_offsets = { \ 39 [TRANSCODER_A] = PIPE_A_OFFSET, \ 40 [TRANSCODER_B] = PIPE_B_OFFSET, \ 41 [TRANSCODER_C] = PIPE_C_OFFSET, \ 42 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 43 }, \ 44 .trans_offsets = { \ 45 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 46 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 47 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 48 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 49 } 50 51 #define GEN_CHV_PIPEOFFSETS \ 52 .pipe_offsets = { \ 53 [TRANSCODER_A] = PIPE_A_OFFSET, \ 54 [TRANSCODER_B] = PIPE_B_OFFSET, \ 55 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \ 56 }, \ 57 .trans_offsets = { \ 58 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 59 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 60 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \ 61 } 62 63 #define CURSOR_OFFSETS \ 64 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET } 65 66 #define IVB_CURSOR_OFFSETS \ 67 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET } 68 69 #define BDW_COLORS \ 70 .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 } 71 #define CHV_COLORS \ 72 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \ 73 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 74 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 75 } 76 #define GLK_COLORS \ 77 .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024, \ 78 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 79 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 80 } 81 82 /* Keep in gen based order, and chronological order within a gen */ 83 84 #define GEN_DEFAULT_PAGE_SIZES \ 85 .page_sizes = I915_GTT_PAGE_SIZE_4K 86 87 #define GEN2_FEATURES \ 88 GEN(2), \ 89 .num_pipes = 1, \ 90 .display.has_overlay = 1, \ 91 .display.overlay_needs_physical = 1, \ 92 .display.has_gmch_display = 1, \ 93 .gpu_reset_clobbers_display = true, \ 94 .hws_needs_physical = 1, \ 95 .unfenced_needs_alignment = 1, \ 96 .ring_mask = RENDER_RING, \ 97 .has_snoop = true, \ 98 .has_coherent_ggtt = false, \ 99 GEN_DEFAULT_PIPEOFFSETS, \ 100 GEN_DEFAULT_PAGE_SIZES, \ 101 CURSOR_OFFSETS 102 103 static const struct intel_device_info intel_i830_info = { 104 GEN2_FEATURES, 105 PLATFORM(INTEL_I830), 106 .is_mobile = 1, 107 .display.cursor_needs_physical = 1, 108 .num_pipes = 2, /* legal, last one wins */ 109 }; 110 111 static const struct intel_device_info intel_i845g_info = { 112 GEN2_FEATURES, 113 PLATFORM(INTEL_I845G), 114 }; 115 116 static const struct intel_device_info intel_i85x_info = { 117 GEN2_FEATURES, 118 PLATFORM(INTEL_I85X), 119 .is_mobile = 1, 120 .num_pipes = 2, /* legal, last one wins */ 121 .display.cursor_needs_physical = 1, 122 .display.has_fbc = 1, 123 }; 124 125 static const struct intel_device_info intel_i865g_info = { 126 GEN2_FEATURES, 127 PLATFORM(INTEL_I865G), 128 }; 129 130 #define GEN3_FEATURES \ 131 GEN(3), \ 132 .num_pipes = 2, \ 133 .display.has_gmch_display = 1, \ 134 .gpu_reset_clobbers_display = true, \ 135 .ring_mask = RENDER_RING, \ 136 .has_snoop = true, \ 137 .has_coherent_ggtt = true, \ 138 GEN_DEFAULT_PIPEOFFSETS, \ 139 GEN_DEFAULT_PAGE_SIZES, \ 140 CURSOR_OFFSETS 141 142 static const struct intel_device_info intel_i915g_info = { 143 GEN3_FEATURES, 144 PLATFORM(INTEL_I915G), 145 .has_coherent_ggtt = false, 146 .display.cursor_needs_physical = 1, 147 .display.has_overlay = 1, 148 .display.overlay_needs_physical = 1, 149 .hws_needs_physical = 1, 150 .unfenced_needs_alignment = 1, 151 }; 152 153 static const struct intel_device_info intel_i915gm_info = { 154 GEN3_FEATURES, 155 PLATFORM(INTEL_I915GM), 156 .is_mobile = 1, 157 .display.cursor_needs_physical = 1, 158 .display.has_overlay = 1, 159 .display.overlay_needs_physical = 1, 160 .display.supports_tv = 1, 161 .display.has_fbc = 1, 162 .hws_needs_physical = 1, 163 .unfenced_needs_alignment = 1, 164 }; 165 166 static const struct intel_device_info intel_i945g_info = { 167 GEN3_FEATURES, 168 PLATFORM(INTEL_I945G), 169 .display.has_hotplug = 1, 170 .display.cursor_needs_physical = 1, 171 .display.has_overlay = 1, 172 .display.overlay_needs_physical = 1, 173 .hws_needs_physical = 1, 174 .unfenced_needs_alignment = 1, 175 }; 176 177 static const struct intel_device_info intel_i945gm_info = { 178 GEN3_FEATURES, 179 PLATFORM(INTEL_I945GM), 180 .is_mobile = 1, 181 .display.has_hotplug = 1, 182 .display.cursor_needs_physical = 1, 183 .display.has_overlay = 1, 184 .display.overlay_needs_physical = 1, 185 .display.supports_tv = 1, 186 .display.has_fbc = 1, 187 .hws_needs_physical = 1, 188 .unfenced_needs_alignment = 1, 189 }; 190 191 static const struct intel_device_info intel_g33_info = { 192 GEN3_FEATURES, 193 PLATFORM(INTEL_G33), 194 .display.has_hotplug = 1, 195 .display.has_overlay = 1, 196 }; 197 198 static const struct intel_device_info intel_pineview_info = { 199 GEN3_FEATURES, 200 PLATFORM(INTEL_PINEVIEW), 201 .is_mobile = 1, 202 .display.has_hotplug = 1, 203 .display.has_overlay = 1, 204 }; 205 206 #define GEN4_FEATURES \ 207 GEN(4), \ 208 .num_pipes = 2, \ 209 .display.has_hotplug = 1, \ 210 .display.has_gmch_display = 1, \ 211 .gpu_reset_clobbers_display = true, \ 212 .ring_mask = RENDER_RING, \ 213 .has_snoop = true, \ 214 .has_coherent_ggtt = true, \ 215 GEN_DEFAULT_PIPEOFFSETS, \ 216 GEN_DEFAULT_PAGE_SIZES, \ 217 CURSOR_OFFSETS 218 219 static const struct intel_device_info intel_i965g_info = { 220 GEN4_FEATURES, 221 PLATFORM(INTEL_I965G), 222 .display.has_overlay = 1, 223 .hws_needs_physical = 1, 224 .has_snoop = false, 225 }; 226 227 static const struct intel_device_info intel_i965gm_info = { 228 GEN4_FEATURES, 229 PLATFORM(INTEL_I965GM), 230 .is_mobile = 1, 231 .display.has_fbc = 1, 232 .display.has_overlay = 1, 233 .display.supports_tv = 1, 234 .hws_needs_physical = 1, 235 .has_snoop = false, 236 }; 237 238 static const struct intel_device_info intel_g45_info = { 239 GEN4_FEATURES, 240 PLATFORM(INTEL_G45), 241 .ring_mask = RENDER_RING | BSD_RING, 242 .gpu_reset_clobbers_display = false, 243 }; 244 245 static const struct intel_device_info intel_gm45_info = { 246 GEN4_FEATURES, 247 PLATFORM(INTEL_GM45), 248 .is_mobile = 1, 249 .display.has_fbc = 1, 250 .display.supports_tv = 1, 251 .ring_mask = RENDER_RING | BSD_RING, 252 .gpu_reset_clobbers_display = false, 253 }; 254 255 #define GEN5_FEATURES \ 256 GEN(5), \ 257 .num_pipes = 2, \ 258 .display.has_hotplug = 1, \ 259 .ring_mask = RENDER_RING | BSD_RING, \ 260 .has_snoop = true, \ 261 .has_coherent_ggtt = true, \ 262 /* ilk does support rc6, but we do not implement [power] contexts */ \ 263 .has_rc6 = 0, \ 264 GEN_DEFAULT_PIPEOFFSETS, \ 265 GEN_DEFAULT_PAGE_SIZES, \ 266 CURSOR_OFFSETS 267 268 static const struct intel_device_info intel_ironlake_d_info = { 269 GEN5_FEATURES, 270 PLATFORM(INTEL_IRONLAKE), 271 }; 272 273 static const struct intel_device_info intel_ironlake_m_info = { 274 GEN5_FEATURES, 275 PLATFORM(INTEL_IRONLAKE), 276 .is_mobile = 1, 277 .display.has_fbc = 1, 278 }; 279 280 #define GEN6_FEATURES \ 281 GEN(6), \ 282 .num_pipes = 2, \ 283 .display.has_hotplug = 1, \ 284 .display.has_fbc = 1, \ 285 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ 286 .has_coherent_ggtt = true, \ 287 .has_llc = 1, \ 288 .has_rc6 = 1, \ 289 .has_rc6p = 1, \ 290 .ppgtt = INTEL_PPGTT_ALIASING, \ 291 GEN_DEFAULT_PIPEOFFSETS, \ 292 GEN_DEFAULT_PAGE_SIZES, \ 293 CURSOR_OFFSETS 294 295 #define SNB_D_PLATFORM \ 296 GEN6_FEATURES, \ 297 PLATFORM(INTEL_SANDYBRIDGE) 298 299 static const struct intel_device_info intel_sandybridge_d_gt1_info = { 300 SNB_D_PLATFORM, 301 .gt = 1, 302 }; 303 304 static const struct intel_device_info intel_sandybridge_d_gt2_info = { 305 SNB_D_PLATFORM, 306 .gt = 2, 307 }; 308 309 #define SNB_M_PLATFORM \ 310 GEN6_FEATURES, \ 311 PLATFORM(INTEL_SANDYBRIDGE), \ 312 .is_mobile = 1 313 314 315 static const struct intel_device_info intel_sandybridge_m_gt1_info = { 316 SNB_M_PLATFORM, 317 .gt = 1, 318 }; 319 320 static const struct intel_device_info intel_sandybridge_m_gt2_info = { 321 SNB_M_PLATFORM, 322 .gt = 2, 323 }; 324 325 #define GEN7_FEATURES \ 326 GEN(7), \ 327 .num_pipes = 3, \ 328 .display.has_hotplug = 1, \ 329 .display.has_fbc = 1, \ 330 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ 331 .has_coherent_ggtt = true, \ 332 .has_llc = 1, \ 333 .has_rc6 = 1, \ 334 .has_rc6p = 1, \ 335 .ppgtt = INTEL_PPGTT_FULL, \ 336 GEN_DEFAULT_PIPEOFFSETS, \ 337 GEN_DEFAULT_PAGE_SIZES, \ 338 IVB_CURSOR_OFFSETS 339 340 #define IVB_D_PLATFORM \ 341 GEN7_FEATURES, \ 342 PLATFORM(INTEL_IVYBRIDGE), \ 343 .has_l3_dpf = 1 344 345 static const struct intel_device_info intel_ivybridge_d_gt1_info = { 346 IVB_D_PLATFORM, 347 .gt = 1, 348 }; 349 350 static const struct intel_device_info intel_ivybridge_d_gt2_info = { 351 IVB_D_PLATFORM, 352 .gt = 2, 353 }; 354 355 #define IVB_M_PLATFORM \ 356 GEN7_FEATURES, \ 357 PLATFORM(INTEL_IVYBRIDGE), \ 358 .is_mobile = 1, \ 359 .has_l3_dpf = 1 360 361 static const struct intel_device_info intel_ivybridge_m_gt1_info = { 362 IVB_M_PLATFORM, 363 .gt = 1, 364 }; 365 366 static const struct intel_device_info intel_ivybridge_m_gt2_info = { 367 IVB_M_PLATFORM, 368 .gt = 2, 369 }; 370 371 static const struct intel_device_info intel_ivybridge_q_info = { 372 GEN7_FEATURES, 373 PLATFORM(INTEL_IVYBRIDGE), 374 .gt = 2, 375 .num_pipes = 0, /* legal, last one wins */ 376 .has_l3_dpf = 1, 377 }; 378 379 static const struct intel_device_info intel_valleyview_info = { 380 PLATFORM(INTEL_VALLEYVIEW), 381 GEN(7), 382 .is_lp = 1, 383 .num_pipes = 2, 384 .has_runtime_pm = 1, 385 .has_rc6 = 1, 386 .display.has_gmch_display = 1, 387 .display.has_hotplug = 1, 388 .ppgtt = INTEL_PPGTT_FULL, 389 .has_snoop = true, 390 .has_coherent_ggtt = false, 391 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, 392 .display_mmio_offset = VLV_DISPLAY_BASE, 393 GEN_DEFAULT_PAGE_SIZES, 394 GEN_DEFAULT_PIPEOFFSETS, 395 CURSOR_OFFSETS 396 }; 397 398 #define G75_FEATURES \ 399 GEN7_FEATURES, \ 400 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \ 401 .display.has_ddi = 1, \ 402 .has_fpga_dbg = 1, \ 403 .display.has_psr = 1, \ 404 .display.has_dp_mst = 1, \ 405 .has_rc6p = 0 /* RC6p removed-by HSW */, \ 406 .has_runtime_pm = 1 407 408 #define HSW_PLATFORM \ 409 G75_FEATURES, \ 410 PLATFORM(INTEL_HASWELL), \ 411 .has_l3_dpf = 1 412 413 static const struct intel_device_info intel_haswell_gt1_info = { 414 HSW_PLATFORM, 415 .gt = 1, 416 }; 417 418 static const struct intel_device_info intel_haswell_gt2_info = { 419 HSW_PLATFORM, 420 .gt = 2, 421 }; 422 423 static const struct intel_device_info intel_haswell_gt3_info = { 424 HSW_PLATFORM, 425 .gt = 3, 426 }; 427 428 #define GEN8_FEATURES \ 429 G75_FEATURES, \ 430 GEN(8), \ 431 BDW_COLORS, \ 432 .page_sizes = I915_GTT_PAGE_SIZE_4K | \ 433 I915_GTT_PAGE_SIZE_2M, \ 434 .has_logical_ring_contexts = 1, \ 435 .ppgtt = INTEL_PPGTT_FULL_4LVL, \ 436 .has_64bit_reloc = 1, \ 437 .has_reset_engine = 1 438 439 #define BDW_PLATFORM \ 440 GEN8_FEATURES, \ 441 PLATFORM(INTEL_BROADWELL) 442 443 static const struct intel_device_info intel_broadwell_gt1_info = { 444 BDW_PLATFORM, 445 .gt = 1, 446 }; 447 448 static const struct intel_device_info intel_broadwell_gt2_info = { 449 BDW_PLATFORM, 450 .gt = 2, 451 }; 452 453 static const struct intel_device_info intel_broadwell_rsvd_info = { 454 BDW_PLATFORM, 455 .gt = 3, 456 /* According to the device ID those devices are GT3, they were 457 * previously treated as not GT3, keep it like that. 458 */ 459 }; 460 461 static const struct intel_device_info intel_broadwell_gt3_info = { 462 BDW_PLATFORM, 463 .gt = 3, 464 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 465 }; 466 467 static const struct intel_device_info intel_cherryview_info = { 468 PLATFORM(INTEL_CHERRYVIEW), 469 GEN(8), 470 .num_pipes = 3, 471 .display.has_hotplug = 1, 472 .is_lp = 1, 473 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, 474 .has_64bit_reloc = 1, 475 .has_runtime_pm = 1, 476 .has_rc6 = 1, 477 .has_logical_ring_contexts = 1, 478 .display.has_gmch_display = 1, 479 .ppgtt = INTEL_PPGTT_FULL, 480 .has_reset_engine = 1, 481 .has_snoop = true, 482 .has_coherent_ggtt = false, 483 .display_mmio_offset = VLV_DISPLAY_BASE, 484 GEN_DEFAULT_PAGE_SIZES, 485 GEN_CHV_PIPEOFFSETS, 486 CURSOR_OFFSETS, 487 CHV_COLORS, 488 }; 489 490 #define GEN9_DEFAULT_PAGE_SIZES \ 491 .page_sizes = I915_GTT_PAGE_SIZE_4K | \ 492 I915_GTT_PAGE_SIZE_64K | \ 493 I915_GTT_PAGE_SIZE_2M 494 495 #define GEN9_FEATURES \ 496 GEN8_FEATURES, \ 497 GEN(9), \ 498 GEN9_DEFAULT_PAGE_SIZES, \ 499 .has_logical_ring_preemption = 1, \ 500 .display.has_csr = 1, \ 501 .has_guc = 1, \ 502 .display.has_ipc = 1, \ 503 .ddb_size = 896 504 505 #define SKL_PLATFORM \ 506 GEN9_FEATURES, \ 507 /* Display WA #0477 WaDisableIPC: skl */ \ 508 .display.has_ipc = 0, \ 509 PLATFORM(INTEL_SKYLAKE) 510 511 static const struct intel_device_info intel_skylake_gt1_info = { 512 SKL_PLATFORM, 513 .gt = 1, 514 }; 515 516 static const struct intel_device_info intel_skylake_gt2_info = { 517 SKL_PLATFORM, 518 .gt = 2, 519 }; 520 521 #define SKL_GT3_PLUS_PLATFORM \ 522 SKL_PLATFORM, \ 523 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING 524 525 526 static const struct intel_device_info intel_skylake_gt3_info = { 527 SKL_GT3_PLUS_PLATFORM, 528 .gt = 3, 529 }; 530 531 static const struct intel_device_info intel_skylake_gt4_info = { 532 SKL_GT3_PLUS_PLATFORM, 533 .gt = 4, 534 }; 535 536 #define GEN9_LP_FEATURES \ 537 GEN(9), \ 538 .is_lp = 1, \ 539 .display.has_hotplug = 1, \ 540 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \ 541 .num_pipes = 3, \ 542 .has_64bit_reloc = 1, \ 543 .display.has_ddi = 1, \ 544 .has_fpga_dbg = 1, \ 545 .display.has_fbc = 1, \ 546 .display.has_psr = 1, \ 547 .has_runtime_pm = 1, \ 548 .display.has_csr = 1, \ 549 .has_rc6 = 1, \ 550 .display.has_dp_mst = 1, \ 551 .has_logical_ring_contexts = 1, \ 552 .has_logical_ring_preemption = 1, \ 553 .has_guc = 1, \ 554 .ppgtt = INTEL_PPGTT_FULL_4LVL, \ 555 .has_reset_engine = 1, \ 556 .has_snoop = true, \ 557 .has_coherent_ggtt = false, \ 558 .display.has_ipc = 1, \ 559 GEN9_DEFAULT_PAGE_SIZES, \ 560 GEN_DEFAULT_PIPEOFFSETS, \ 561 IVB_CURSOR_OFFSETS, \ 562 BDW_COLORS 563 564 static const struct intel_device_info intel_broxton_info = { 565 GEN9_LP_FEATURES, 566 PLATFORM(INTEL_BROXTON), 567 .ddb_size = 512, 568 }; 569 570 static const struct intel_device_info intel_geminilake_info = { 571 GEN9_LP_FEATURES, 572 PLATFORM(INTEL_GEMINILAKE), 573 .ddb_size = 1024, 574 GLK_COLORS, 575 }; 576 577 #define KBL_PLATFORM \ 578 GEN9_FEATURES, \ 579 PLATFORM(INTEL_KABYLAKE) 580 581 static const struct intel_device_info intel_kabylake_gt1_info = { 582 KBL_PLATFORM, 583 .gt = 1, 584 }; 585 586 static const struct intel_device_info intel_kabylake_gt2_info = { 587 KBL_PLATFORM, 588 .gt = 2, 589 }; 590 591 static const struct intel_device_info intel_kabylake_gt3_info = { 592 KBL_PLATFORM, 593 .gt = 3, 594 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 595 }; 596 597 #define CFL_PLATFORM \ 598 GEN9_FEATURES, \ 599 PLATFORM(INTEL_COFFEELAKE) 600 601 static const struct intel_device_info intel_coffeelake_gt1_info = { 602 CFL_PLATFORM, 603 .gt = 1, 604 }; 605 606 static const struct intel_device_info intel_coffeelake_gt2_info = { 607 CFL_PLATFORM, 608 .gt = 2, 609 }; 610 611 static const struct intel_device_info intel_coffeelake_gt3_info = { 612 CFL_PLATFORM, 613 .gt = 3, 614 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 615 }; 616 617 #define GEN10_FEATURES \ 618 GEN9_FEATURES, \ 619 GEN(10), \ 620 .ddb_size = 1024, \ 621 .has_coherent_ggtt = false, \ 622 GLK_COLORS 623 624 static const struct intel_device_info intel_cannonlake_info = { 625 GEN10_FEATURES, 626 PLATFORM(INTEL_CANNONLAKE), 627 .gt = 2, 628 }; 629 630 #define GEN11_FEATURES \ 631 GEN10_FEATURES, \ 632 .pipe_offsets = { \ 633 [TRANSCODER_A] = PIPE_A_OFFSET, \ 634 [TRANSCODER_B] = PIPE_B_OFFSET, \ 635 [TRANSCODER_C] = PIPE_C_OFFSET, \ 636 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 637 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 638 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 639 }, \ 640 .trans_offsets = { \ 641 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 642 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 643 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 644 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 645 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 646 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 647 }, \ 648 GEN(11), \ 649 .ddb_size = 2048, \ 650 .has_logical_ring_elsq = 1 651 652 static const struct intel_device_info intel_icelake_11_info = { 653 GEN11_FEATURES, 654 PLATFORM(INTEL_ICELAKE), 655 .is_alpha_support = 1, 656 .ring_mask = RENDER_RING | BLT_RING | VEBOX_RING | BSD_RING | BSD3_RING, 657 }; 658 659 #undef GEN 660 #undef PLATFORM 661 662 /* 663 * Make sure any device matches here are from most specific to most 664 * general. For example, since the Quanta match is based on the subsystem 665 * and subvendor IDs, we need it to come before the more general IVB 666 * PCI ID matches, otherwise we'll use the wrong info struct above. 667 */ 668 static const struct pci_device_id pciidlist[] = { 669 INTEL_I830_IDS(&intel_i830_info), 670 INTEL_I845G_IDS(&intel_i845g_info), 671 INTEL_I85X_IDS(&intel_i85x_info), 672 INTEL_I865G_IDS(&intel_i865g_info), 673 INTEL_I915G_IDS(&intel_i915g_info), 674 INTEL_I915GM_IDS(&intel_i915gm_info), 675 INTEL_I945G_IDS(&intel_i945g_info), 676 INTEL_I945GM_IDS(&intel_i945gm_info), 677 INTEL_I965G_IDS(&intel_i965g_info), 678 INTEL_G33_IDS(&intel_g33_info), 679 INTEL_I965GM_IDS(&intel_i965gm_info), 680 INTEL_GM45_IDS(&intel_gm45_info), 681 INTEL_G45_IDS(&intel_g45_info), 682 INTEL_PINEVIEW_IDS(&intel_pineview_info), 683 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), 684 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), 685 INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info), 686 INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info), 687 INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info), 688 INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info), 689 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ 690 INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info), 691 INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info), 692 INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info), 693 INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info), 694 INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info), 695 INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info), 696 INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info), 697 INTEL_VLV_IDS(&intel_valleyview_info), 698 INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info), 699 INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info), 700 INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info), 701 INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info), 702 INTEL_CHV_IDS(&intel_cherryview_info), 703 INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info), 704 INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info), 705 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), 706 INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info), 707 INTEL_BXT_IDS(&intel_broxton_info), 708 INTEL_GLK_IDS(&intel_geminilake_info), 709 INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info), 710 INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info), 711 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info), 712 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info), 713 INTEL_AML_KBL_GT2_IDS(&intel_kabylake_gt2_info), 714 INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info), 715 INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info), 716 INTEL_CFL_H_GT1_IDS(&intel_coffeelake_gt1_info), 717 INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info), 718 INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info), 719 INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info), 720 INTEL_WHL_U_GT1_IDS(&intel_coffeelake_gt1_info), 721 INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info), 722 INTEL_AML_CFL_GT2_IDS(&intel_coffeelake_gt2_info), 723 INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info), 724 INTEL_CNL_IDS(&intel_cannonlake_info), 725 INTEL_ICL_11_IDS(&intel_icelake_11_info), 726 {0, 0, 0} 727 }; 728 MODULE_DEVICE_TABLE(pci, pciidlist); 729 730 static void i915_pci_remove(struct pci_dev *pdev) 731 { 732 struct drm_device *dev; 733 734 dev = pci_get_drvdata(pdev); 735 if (!dev) /* driver load aborted, nothing to cleanup */ 736 return; 737 738 i915_driver_unload(dev); 739 drm_dev_put(dev); 740 741 pci_set_drvdata(pdev, NULL); 742 } 743 744 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 745 { 746 struct intel_device_info *intel_info = 747 (struct intel_device_info *) ent->driver_data; 748 int err; 749 750 if (IS_ALPHA_SUPPORT(intel_info) && !i915_modparams.alpha_support) { 751 DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n" 752 "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n" 753 "to enable support in this kernel version, or check for kernel updates.\n"); 754 return -ENODEV; 755 } 756 757 /* Only bind to function 0 of the device. Early generations 758 * used function 1 as a placeholder for multi-head. This causes 759 * us confusion instead, especially on the systems where both 760 * functions have the same PCI-ID! 761 */ 762 if (PCI_FUNC(pdev->devfn)) 763 return -ENODEV; 764 765 /* 766 * apple-gmux is needed on dual GPU MacBook Pro 767 * to probe the panel if we're the inactive GPU. 768 */ 769 if (vga_switcheroo_client_probe_defer(pdev)) 770 return -EPROBE_DEFER; 771 772 err = i915_driver_load(pdev, ent); 773 if (err) 774 return err; 775 776 if (i915_inject_load_failure()) { 777 i915_pci_remove(pdev); 778 return -ENODEV; 779 } 780 781 err = i915_live_selftests(pdev); 782 if (err) { 783 i915_pci_remove(pdev); 784 return err > 0 ? -ENOTTY : err; 785 } 786 787 return 0; 788 } 789 790 static struct pci_driver i915_pci_driver = { 791 .name = DRIVER_NAME, 792 .id_table = pciidlist, 793 .probe = i915_pci_probe, 794 .remove = i915_pci_remove, 795 .driver.pm = &i915_pm_ops, 796 }; 797 798 static int __init i915_init(void) 799 { 800 bool use_kms = true; 801 int err; 802 803 err = i915_mock_selftests(); 804 if (err) 805 return err > 0 ? 0 : err; 806 807 /* 808 * Enable KMS by default, unless explicitly overriden by 809 * either the i915.modeset prarameter or by the 810 * vga_text_mode_force boot option. 811 */ 812 813 if (i915_modparams.modeset == 0) 814 use_kms = false; 815 816 if (vgacon_text_force() && i915_modparams.modeset == -1) 817 use_kms = false; 818 819 if (!use_kms) { 820 /* Silently fail loading to not upset userspace. */ 821 DRM_DEBUG_DRIVER("KMS disabled.\n"); 822 return 0; 823 } 824 825 return pci_register_driver(&i915_pci_driver); 826 } 827 828 static void __exit i915_exit(void) 829 { 830 if (!i915_pci_driver.driver.owner) 831 return; 832 833 pci_unregister_driver(&i915_pci_driver); 834 } 835 836 module_init(i915_init); 837 module_exit(i915_exit); 838 839 MODULE_AUTHOR("Tungsten Graphics, Inc."); 840 MODULE_AUTHOR("Intel Corporation"); 841 842 MODULE_DESCRIPTION(DRIVER_DESC); 843 MODULE_LICENSE("GPL and additional rights"); 844