1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/console.h> 26 #include <linux/vgaarb.h> 27 #include <linux/vga_switcheroo.h> 28 29 #include "i915_drv.h" 30 31 #define GEN_DEFAULT_PIPEOFFSETS \ 32 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ 33 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \ 34 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ 35 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \ 36 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET } 37 38 #define GEN_CHV_PIPEOFFSETS \ 39 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ 40 CHV_PIPE_C_OFFSET }, \ 41 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ 42 CHV_TRANSCODER_C_OFFSET, }, \ 43 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \ 44 CHV_PALETTE_C_OFFSET } 45 46 #define CURSOR_OFFSETS \ 47 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET } 48 49 #define IVB_CURSOR_OFFSETS \ 50 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET } 51 52 #define BDW_COLORS \ 53 .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 } 54 #define CHV_COLORS \ 55 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 } 56 57 #define GEN2_FEATURES \ 58 .gen = 2, .num_pipes = 1, \ 59 .has_overlay = 1, .overlay_needs_physical = 1, \ 60 .has_gmch_display = 1, \ 61 .hws_needs_physical = 1, \ 62 .ring_mask = RENDER_RING, \ 63 GEN_DEFAULT_PIPEOFFSETS, \ 64 CURSOR_OFFSETS 65 66 static const struct intel_device_info intel_i830_info = { 67 GEN2_FEATURES, 68 .is_mobile = 1, .cursor_needs_physical = 1, 69 .num_pipes = 2, /* legal, last one wins */ 70 }; 71 72 static const struct intel_device_info intel_845g_info = { 73 GEN2_FEATURES, 74 }; 75 76 static const struct intel_device_info intel_i85x_info = { 77 GEN2_FEATURES, 78 .is_i85x = 1, .is_mobile = 1, 79 .num_pipes = 2, /* legal, last one wins */ 80 .cursor_needs_physical = 1, 81 .has_fbc = 1, 82 }; 83 84 static const struct intel_device_info intel_i865g_info = { 85 GEN2_FEATURES, 86 }; 87 88 #define GEN3_FEATURES \ 89 .gen = 3, .num_pipes = 2, \ 90 .has_gmch_display = 1, \ 91 .ring_mask = RENDER_RING, \ 92 GEN_DEFAULT_PIPEOFFSETS, \ 93 CURSOR_OFFSETS 94 95 static const struct intel_device_info intel_i915g_info = { 96 GEN3_FEATURES, 97 .is_i915g = 1, .cursor_needs_physical = 1, 98 .has_overlay = 1, .overlay_needs_physical = 1, 99 .hws_needs_physical = 1, 100 }; 101 static const struct intel_device_info intel_i915gm_info = { 102 GEN3_FEATURES, 103 .is_mobile = 1, 104 .cursor_needs_physical = 1, 105 .has_overlay = 1, .overlay_needs_physical = 1, 106 .supports_tv = 1, 107 .has_fbc = 1, 108 .hws_needs_physical = 1, 109 }; 110 static const struct intel_device_info intel_i945g_info = { 111 GEN3_FEATURES, 112 .has_hotplug = 1, .cursor_needs_physical = 1, 113 .has_overlay = 1, .overlay_needs_physical = 1, 114 .hws_needs_physical = 1, 115 }; 116 static const struct intel_device_info intel_i945gm_info = { 117 GEN3_FEATURES, 118 .is_i945gm = 1, .is_mobile = 1, 119 .has_hotplug = 1, .cursor_needs_physical = 1, 120 .has_overlay = 1, .overlay_needs_physical = 1, 121 .supports_tv = 1, 122 .has_fbc = 1, 123 .hws_needs_physical = 1, 124 }; 125 126 #define GEN4_FEATURES \ 127 .gen = 4, .num_pipes = 2, \ 128 .has_hotplug = 1, \ 129 .has_gmch_display = 1, \ 130 .ring_mask = RENDER_RING, \ 131 GEN_DEFAULT_PIPEOFFSETS, \ 132 CURSOR_OFFSETS 133 134 static const struct intel_device_info intel_i965g_info = { 135 GEN4_FEATURES, 136 .is_broadwater = 1, 137 .has_overlay = 1, 138 .hws_needs_physical = 1, 139 }; 140 141 static const struct intel_device_info intel_i965gm_info = { 142 GEN4_FEATURES, 143 .is_crestline = 1, 144 .is_mobile = 1, .has_fbc = 1, 145 .has_overlay = 1, 146 .supports_tv = 1, 147 .hws_needs_physical = 1, 148 }; 149 150 static const struct intel_device_info intel_g33_info = { 151 GEN3_FEATURES, 152 .is_g33 = 1, 153 .has_hotplug = 1, 154 .has_overlay = 1, 155 }; 156 157 static const struct intel_device_info intel_g45_info = { 158 GEN4_FEATURES, 159 .is_g4x = 1, 160 .has_pipe_cxsr = 1, 161 .ring_mask = RENDER_RING | BSD_RING, 162 }; 163 164 static const struct intel_device_info intel_gm45_info = { 165 GEN4_FEATURES, 166 .is_g4x = 1, 167 .is_mobile = 1, .has_fbc = 1, 168 .has_pipe_cxsr = 1, 169 .supports_tv = 1, 170 .ring_mask = RENDER_RING | BSD_RING, 171 }; 172 173 static const struct intel_device_info intel_pineview_info = { 174 GEN3_FEATURES, 175 .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, 176 .has_hotplug = 1, 177 .has_overlay = 1, 178 }; 179 180 #define GEN5_FEATURES \ 181 .gen = 5, .num_pipes = 2, \ 182 .has_hotplug = 1, \ 183 .has_gmbus_irq = 1, \ 184 .ring_mask = RENDER_RING | BSD_RING, \ 185 GEN_DEFAULT_PIPEOFFSETS, \ 186 CURSOR_OFFSETS 187 188 static const struct intel_device_info intel_ironlake_d_info = { 189 GEN5_FEATURES, 190 }; 191 192 static const struct intel_device_info intel_ironlake_m_info = { 193 GEN5_FEATURES, 194 .is_mobile = 1, 195 }; 196 197 #define GEN6_FEATURES \ 198 .gen = 6, .num_pipes = 2, \ 199 .has_hotplug = 1, \ 200 .has_fbc = 1, \ 201 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ 202 .has_llc = 1, \ 203 .has_rc6 = 1, \ 204 .has_rc6p = 1, \ 205 .has_gmbus_irq = 1, \ 206 .has_hw_contexts = 1, \ 207 GEN_DEFAULT_PIPEOFFSETS, \ 208 CURSOR_OFFSETS 209 210 static const struct intel_device_info intel_sandybridge_d_info = { 211 GEN6_FEATURES, 212 }; 213 214 static const struct intel_device_info intel_sandybridge_m_info = { 215 GEN6_FEATURES, 216 .is_mobile = 1, 217 }; 218 219 #define GEN7_FEATURES \ 220 .gen = 7, .num_pipes = 3, \ 221 .has_hotplug = 1, \ 222 .has_fbc = 1, \ 223 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ 224 .has_llc = 1, \ 225 .has_rc6 = 1, \ 226 .has_rc6p = 1, \ 227 .has_gmbus_irq = 1, \ 228 .has_hw_contexts = 1, \ 229 GEN_DEFAULT_PIPEOFFSETS, \ 230 IVB_CURSOR_OFFSETS 231 232 static const struct intel_device_info intel_ivybridge_d_info = { 233 GEN7_FEATURES, 234 .is_ivybridge = 1, 235 .has_l3_dpf = 1, 236 }; 237 238 static const struct intel_device_info intel_ivybridge_m_info = { 239 GEN7_FEATURES, 240 .is_ivybridge = 1, 241 .is_mobile = 1, 242 .has_l3_dpf = 1, 243 }; 244 245 static const struct intel_device_info intel_ivybridge_q_info = { 246 GEN7_FEATURES, 247 .is_ivybridge = 1, 248 .num_pipes = 0, /* legal, last one wins */ 249 .has_l3_dpf = 1, 250 }; 251 252 #define VLV_FEATURES \ 253 .gen = 7, .num_pipes = 2, \ 254 .has_psr = 1, \ 255 .has_runtime_pm = 1, \ 256 .has_rc6 = 1, \ 257 .has_gmbus_irq = 1, \ 258 .has_hw_contexts = 1, \ 259 .has_gmch_display = 1, \ 260 .has_hotplug = 1, \ 261 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ 262 .display_mmio_offset = VLV_DISPLAY_BASE, \ 263 GEN_DEFAULT_PIPEOFFSETS, \ 264 CURSOR_OFFSETS 265 266 static const struct intel_device_info intel_valleyview_info = { 267 VLV_FEATURES, 268 .is_valleyview = 1, 269 }; 270 271 #define HSW_FEATURES \ 272 GEN7_FEATURES, \ 273 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \ 274 .has_ddi = 1, \ 275 .has_fpga_dbg = 1, \ 276 .has_psr = 1, \ 277 .has_resource_streamer = 1, \ 278 .has_dp_mst = 1, \ 279 .has_rc6p = 0 /* RC6p removed-by HSW */, \ 280 .has_runtime_pm = 1 281 282 static const struct intel_device_info intel_haswell_info = { 283 HSW_FEATURES, 284 .is_haswell = 1, 285 .has_l3_dpf = 1, 286 }; 287 288 #define BDW_FEATURES \ 289 HSW_FEATURES, \ 290 BDW_COLORS, \ 291 .has_logical_ring_contexts = 1, \ 292 .has_64bit_reloc = 1 293 294 static const struct intel_device_info intel_broadwell_info = { 295 BDW_FEATURES, 296 .gen = 8, 297 .is_broadwell = 1, 298 }; 299 300 static const struct intel_device_info intel_broadwell_gt3_info = { 301 BDW_FEATURES, 302 .gen = 8, 303 .is_broadwell = 1, 304 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 305 }; 306 307 static const struct intel_device_info intel_cherryview_info = { 308 .gen = 8, .num_pipes = 3, 309 .has_hotplug = 1, 310 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, 311 .is_cherryview = 1, 312 .has_64bit_reloc = 1, 313 .has_psr = 1, 314 .has_runtime_pm = 1, 315 .has_resource_streamer = 1, 316 .has_rc6 = 1, 317 .has_gmbus_irq = 1, 318 .has_hw_contexts = 1, 319 .has_logical_ring_contexts = 1, 320 .has_gmch_display = 1, 321 .display_mmio_offset = VLV_DISPLAY_BASE, 322 GEN_CHV_PIPEOFFSETS, 323 CURSOR_OFFSETS, 324 CHV_COLORS, 325 }; 326 327 static const struct intel_device_info intel_skylake_info = { 328 BDW_FEATURES, 329 .is_skylake = 1, 330 .gen = 9, 331 .has_csr = 1, 332 .has_guc = 1, 333 .ddb_size = 896, 334 }; 335 336 static const struct intel_device_info intel_skylake_gt3_info = { 337 BDW_FEATURES, 338 .is_skylake = 1, 339 .gen = 9, 340 .has_csr = 1, 341 .has_guc = 1, 342 .ddb_size = 896, 343 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 344 }; 345 346 static const struct intel_device_info intel_broxton_info = { 347 .is_broxton = 1, 348 .gen = 9, 349 .has_hotplug = 1, 350 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, 351 .num_pipes = 3, 352 .has_64bit_reloc = 1, 353 .has_ddi = 1, 354 .has_fpga_dbg = 1, 355 .has_fbc = 1, 356 .has_runtime_pm = 1, 357 .has_pooled_eu = 0, 358 .has_csr = 1, 359 .has_resource_streamer = 1, 360 .has_rc6 = 1, 361 .has_dp_mst = 1, 362 .has_gmbus_irq = 1, 363 .has_hw_contexts = 1, 364 .has_logical_ring_contexts = 1, 365 .has_guc = 1, 366 .has_decoupled_mmio = 1, 367 .ddb_size = 512, 368 GEN_DEFAULT_PIPEOFFSETS, 369 IVB_CURSOR_OFFSETS, 370 BDW_COLORS, 371 }; 372 373 static const struct intel_device_info intel_kabylake_info = { 374 BDW_FEATURES, 375 .is_kabylake = 1, 376 .gen = 9, 377 .has_csr = 1, 378 .has_guc = 1, 379 .ddb_size = 896, 380 }; 381 382 static const struct intel_device_info intel_kabylake_gt3_info = { 383 BDW_FEATURES, 384 .is_kabylake = 1, 385 .gen = 9, 386 .has_csr = 1, 387 .has_guc = 1, 388 .ddb_size = 896, 389 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 390 }; 391 392 /* 393 * Make sure any device matches here are from most specific to most 394 * general. For example, since the Quanta match is based on the subsystem 395 * and subvendor IDs, we need it to come before the more general IVB 396 * PCI ID matches, otherwise we'll use the wrong info struct above. 397 */ 398 static const struct pci_device_id pciidlist[] = { 399 INTEL_I830_IDS(&intel_i830_info), 400 INTEL_I845G_IDS(&intel_845g_info), 401 INTEL_I85X_IDS(&intel_i85x_info), 402 INTEL_I865G_IDS(&intel_i865g_info), 403 INTEL_I915G_IDS(&intel_i915g_info), 404 INTEL_I915GM_IDS(&intel_i915gm_info), 405 INTEL_I945G_IDS(&intel_i945g_info), 406 INTEL_I945GM_IDS(&intel_i945gm_info), 407 INTEL_I965G_IDS(&intel_i965g_info), 408 INTEL_G33_IDS(&intel_g33_info), 409 INTEL_I965GM_IDS(&intel_i965gm_info), 410 INTEL_GM45_IDS(&intel_gm45_info), 411 INTEL_G45_IDS(&intel_g45_info), 412 INTEL_PINEVIEW_IDS(&intel_pineview_info), 413 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), 414 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), 415 INTEL_SNB_D_IDS(&intel_sandybridge_d_info), 416 INTEL_SNB_M_IDS(&intel_sandybridge_m_info), 417 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ 418 INTEL_IVB_M_IDS(&intel_ivybridge_m_info), 419 INTEL_IVB_D_IDS(&intel_ivybridge_d_info), 420 INTEL_HSW_IDS(&intel_haswell_info), 421 INTEL_VLV_IDS(&intel_valleyview_info), 422 INTEL_BDW_GT12_IDS(&intel_broadwell_info), 423 INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info), 424 INTEL_CHV_IDS(&intel_cherryview_info), 425 INTEL_SKL_GT1_IDS(&intel_skylake_info), 426 INTEL_SKL_GT2_IDS(&intel_skylake_info), 427 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), 428 INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info), 429 INTEL_BXT_IDS(&intel_broxton_info), 430 INTEL_KBL_GT1_IDS(&intel_kabylake_info), 431 INTEL_KBL_GT2_IDS(&intel_kabylake_info), 432 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info), 433 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info), 434 {0, 0, 0} 435 }; 436 MODULE_DEVICE_TABLE(pci, pciidlist); 437 438 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 439 { 440 struct intel_device_info *intel_info = 441 (struct intel_device_info *) ent->driver_data; 442 443 if (IS_ALPHA_SUPPORT(intel_info) && !i915.alpha_support) { 444 DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n" 445 "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n" 446 "to enable support in this kernel version, or check for kernel updates.\n"); 447 return -ENODEV; 448 } 449 450 /* Only bind to function 0 of the device. Early generations 451 * used function 1 as a placeholder for multi-head. This causes 452 * us confusion instead, especially on the systems where both 453 * functions have the same PCI-ID! 454 */ 455 if (PCI_FUNC(pdev->devfn)) 456 return -ENODEV; 457 458 /* 459 * apple-gmux is needed on dual GPU MacBook Pro 460 * to probe the panel if we're the inactive GPU. 461 */ 462 if (vga_switcheroo_client_probe_defer(pdev)) 463 return -EPROBE_DEFER; 464 465 return i915_driver_load(pdev, ent); 466 } 467 468 static void i915_pci_remove(struct pci_dev *pdev) 469 { 470 struct drm_device *dev = pci_get_drvdata(pdev); 471 472 i915_driver_unload(dev); 473 drm_dev_unref(dev); 474 } 475 476 static struct pci_driver i915_pci_driver = { 477 .name = DRIVER_NAME, 478 .id_table = pciidlist, 479 .probe = i915_pci_probe, 480 .remove = i915_pci_remove, 481 .driver.pm = &i915_pm_ops, 482 }; 483 484 static int __init i915_init(void) 485 { 486 bool use_kms = true; 487 488 /* 489 * Enable KMS by default, unless explicitly overriden by 490 * either the i915.modeset prarameter or by the 491 * vga_text_mode_force boot option. 492 */ 493 494 if (i915.modeset == 0) 495 use_kms = false; 496 497 if (vgacon_text_force() && i915.modeset == -1) 498 use_kms = false; 499 500 if (!use_kms) { 501 /* Silently fail loading to not upset userspace. */ 502 DRM_DEBUG_DRIVER("KMS disabled.\n"); 503 return 0; 504 } 505 506 return pci_register_driver(&i915_pci_driver); 507 } 508 509 static void __exit i915_exit(void) 510 { 511 if (!i915_pci_driver.driver.owner) 512 return; 513 514 pci_unregister_driver(&i915_pci_driver); 515 } 516 517 module_init(i915_init); 518 module_exit(i915_exit); 519 520 MODULE_AUTHOR("Tungsten Graphics, Inc."); 521 MODULE_AUTHOR("Intel Corporation"); 522 523 MODULE_DESCRIPTION(DRIVER_DESC); 524 MODULE_LICENSE("GPL and additional rights"); 525