xref: /openbmc/linux/drivers/gpu/drm/i915/i915_pci.c (revision 7b73a9c8)
1 /*
2  * Copyright © 2016 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  */
24 
25 #include <linux/console.h>
26 #include <linux/vga_switcheroo.h>
27 
28 #include <drm/drm_drv.h>
29 
30 #include "display/intel_fbdev.h"
31 
32 #include "i915_drv.h"
33 #include "i915_globals.h"
34 #include "i915_selftest.h"
35 
36 #define PLATFORM(x) .platform = (x)
37 #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
38 
39 #define I845_PIPE_OFFSETS \
40 	.pipe_offsets = { \
41 		[TRANSCODER_A] = PIPE_A_OFFSET,	\
42 	}, \
43 	.trans_offsets = { \
44 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
45 	}
46 
47 #define I9XX_PIPE_OFFSETS \
48 	.pipe_offsets = { \
49 		[TRANSCODER_A] = PIPE_A_OFFSET,	\
50 		[TRANSCODER_B] = PIPE_B_OFFSET, \
51 	}, \
52 	.trans_offsets = { \
53 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
54 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
55 	}
56 
57 #define IVB_PIPE_OFFSETS \
58 	.pipe_offsets = { \
59 		[TRANSCODER_A] = PIPE_A_OFFSET,	\
60 		[TRANSCODER_B] = PIPE_B_OFFSET, \
61 		[TRANSCODER_C] = PIPE_C_OFFSET, \
62 	}, \
63 	.trans_offsets = { \
64 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
65 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
66 		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
67 	}
68 
69 #define HSW_PIPE_OFFSETS \
70 	.pipe_offsets = { \
71 		[TRANSCODER_A] = PIPE_A_OFFSET,	\
72 		[TRANSCODER_B] = PIPE_B_OFFSET, \
73 		[TRANSCODER_C] = PIPE_C_OFFSET, \
74 		[TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
75 	}, \
76 	.trans_offsets = { \
77 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
78 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
79 		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
80 		[TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
81 	}
82 
83 #define CHV_PIPE_OFFSETS \
84 	.pipe_offsets = { \
85 		[TRANSCODER_A] = PIPE_A_OFFSET, \
86 		[TRANSCODER_B] = PIPE_B_OFFSET, \
87 		[TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
88 	}, \
89 	.trans_offsets = { \
90 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
91 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
92 		[TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
93 	}
94 
95 #define I845_CURSOR_OFFSETS \
96 	.cursor_offsets = { \
97 		[PIPE_A] = CURSOR_A_OFFSET, \
98 	}
99 
100 #define I9XX_CURSOR_OFFSETS \
101 	.cursor_offsets = { \
102 		[PIPE_A] = CURSOR_A_OFFSET, \
103 		[PIPE_B] = CURSOR_B_OFFSET, \
104 	}
105 
106 #define CHV_CURSOR_OFFSETS \
107 	.cursor_offsets = { \
108 		[PIPE_A] = CURSOR_A_OFFSET, \
109 		[PIPE_B] = CURSOR_B_OFFSET, \
110 		[PIPE_C] = CHV_CURSOR_C_OFFSET, \
111 	}
112 
113 #define IVB_CURSOR_OFFSETS \
114 	.cursor_offsets = { \
115 		[PIPE_A] = CURSOR_A_OFFSET, \
116 		[PIPE_B] = IVB_CURSOR_B_OFFSET, \
117 		[PIPE_C] = IVB_CURSOR_C_OFFSET, \
118 	}
119 
120 #define TGL_CURSOR_OFFSETS \
121 	.cursor_offsets = { \
122 		[PIPE_A] = CURSOR_A_OFFSET, \
123 		[PIPE_B] = IVB_CURSOR_B_OFFSET, \
124 		[PIPE_C] = IVB_CURSOR_C_OFFSET, \
125 		[PIPE_D] = TGL_CURSOR_D_OFFSET, \
126 	}
127 
128 #define I9XX_COLORS \
129 	.color = { .gamma_lut_size = 256 }
130 #define I965_COLORS \
131 	.color = { .gamma_lut_size = 129, \
132 		   .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
133 	}
134 #define ILK_COLORS \
135 	.color = { .gamma_lut_size = 1024 }
136 #define IVB_COLORS \
137 	.color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
138 #define CHV_COLORS \
139 	.color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \
140 		   .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
141 		   .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
142 	}
143 #define GLK_COLORS \
144 	.color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \
145 		   .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
146 					DRM_COLOR_LUT_EQUAL_CHANNELS, \
147 	}
148 
149 /* Keep in gen based order, and chronological order within a gen */
150 
151 #define GEN_DEFAULT_PAGE_SIZES \
152 	.page_sizes = I915_GTT_PAGE_SIZE_4K
153 
154 #define GEN_DEFAULT_REGIONS \
155 	.memory_regions = REGION_SMEM | REGION_STOLEN
156 
157 #define I830_FEATURES \
158 	GEN(2), \
159 	.is_mobile = 1, \
160 	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
161 	.display.has_overlay = 1, \
162 	.display.cursor_needs_physical = 1, \
163 	.display.overlay_needs_physical = 1, \
164 	.display.has_gmch = 1, \
165 	.gpu_reset_clobbers_display = true, \
166 	.hws_needs_physical = 1, \
167 	.unfenced_needs_alignment = 1, \
168 	.engine_mask = BIT(RCS0), \
169 	.has_snoop = true, \
170 	.has_coherent_ggtt = false, \
171 	I9XX_PIPE_OFFSETS, \
172 	I9XX_CURSOR_OFFSETS, \
173 	I9XX_COLORS, \
174 	GEN_DEFAULT_PAGE_SIZES, \
175 	GEN_DEFAULT_REGIONS
176 
177 #define I845_FEATURES \
178 	GEN(2), \
179 	.pipe_mask = BIT(PIPE_A), \
180 	.display.has_overlay = 1, \
181 	.display.overlay_needs_physical = 1, \
182 	.display.has_gmch = 1, \
183 	.gpu_reset_clobbers_display = true, \
184 	.hws_needs_physical = 1, \
185 	.unfenced_needs_alignment = 1, \
186 	.engine_mask = BIT(RCS0), \
187 	.has_snoop = true, \
188 	.has_coherent_ggtt = false, \
189 	I845_PIPE_OFFSETS, \
190 	I845_CURSOR_OFFSETS, \
191 	I9XX_COLORS, \
192 	GEN_DEFAULT_PAGE_SIZES, \
193 	GEN_DEFAULT_REGIONS
194 
195 static const struct intel_device_info intel_i830_info = {
196 	I830_FEATURES,
197 	PLATFORM(INTEL_I830),
198 };
199 
200 static const struct intel_device_info intel_i845g_info = {
201 	I845_FEATURES,
202 	PLATFORM(INTEL_I845G),
203 };
204 
205 static const struct intel_device_info intel_i85x_info = {
206 	I830_FEATURES,
207 	PLATFORM(INTEL_I85X),
208 	.display.has_fbc = 1,
209 };
210 
211 static const struct intel_device_info intel_i865g_info = {
212 	I845_FEATURES,
213 	PLATFORM(INTEL_I865G),
214 };
215 
216 #define GEN3_FEATURES \
217 	GEN(3), \
218 	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
219 	.display.has_gmch = 1, \
220 	.gpu_reset_clobbers_display = true, \
221 	.engine_mask = BIT(RCS0), \
222 	.has_snoop = true, \
223 	.has_coherent_ggtt = true, \
224 	I9XX_PIPE_OFFSETS, \
225 	I9XX_CURSOR_OFFSETS, \
226 	I9XX_COLORS, \
227 	GEN_DEFAULT_PAGE_SIZES, \
228 	GEN_DEFAULT_REGIONS
229 
230 static const struct intel_device_info intel_i915g_info = {
231 	GEN3_FEATURES,
232 	PLATFORM(INTEL_I915G),
233 	.has_coherent_ggtt = false,
234 	.display.cursor_needs_physical = 1,
235 	.display.has_overlay = 1,
236 	.display.overlay_needs_physical = 1,
237 	.hws_needs_physical = 1,
238 	.unfenced_needs_alignment = 1,
239 };
240 
241 static const struct intel_device_info intel_i915gm_info = {
242 	GEN3_FEATURES,
243 	PLATFORM(INTEL_I915GM),
244 	.is_mobile = 1,
245 	.display.cursor_needs_physical = 1,
246 	.display.has_overlay = 1,
247 	.display.overlay_needs_physical = 1,
248 	.display.supports_tv = 1,
249 	.display.has_fbc = 1,
250 	.hws_needs_physical = 1,
251 	.unfenced_needs_alignment = 1,
252 };
253 
254 static const struct intel_device_info intel_i945g_info = {
255 	GEN3_FEATURES,
256 	PLATFORM(INTEL_I945G),
257 	.display.has_hotplug = 1,
258 	.display.cursor_needs_physical = 1,
259 	.display.has_overlay = 1,
260 	.display.overlay_needs_physical = 1,
261 	.hws_needs_physical = 1,
262 	.unfenced_needs_alignment = 1,
263 };
264 
265 static const struct intel_device_info intel_i945gm_info = {
266 	GEN3_FEATURES,
267 	PLATFORM(INTEL_I945GM),
268 	.is_mobile = 1,
269 	.display.has_hotplug = 1,
270 	.display.cursor_needs_physical = 1,
271 	.display.has_overlay = 1,
272 	.display.overlay_needs_physical = 1,
273 	.display.supports_tv = 1,
274 	.display.has_fbc = 1,
275 	.hws_needs_physical = 1,
276 	.unfenced_needs_alignment = 1,
277 };
278 
279 static const struct intel_device_info intel_g33_info = {
280 	GEN3_FEATURES,
281 	PLATFORM(INTEL_G33),
282 	.display.has_hotplug = 1,
283 	.display.has_overlay = 1,
284 };
285 
286 static const struct intel_device_info intel_pineview_g_info = {
287 	GEN3_FEATURES,
288 	PLATFORM(INTEL_PINEVIEW),
289 	.display.has_hotplug = 1,
290 	.display.has_overlay = 1,
291 };
292 
293 static const struct intel_device_info intel_pineview_m_info = {
294 	GEN3_FEATURES,
295 	PLATFORM(INTEL_PINEVIEW),
296 	.is_mobile = 1,
297 	.display.has_hotplug = 1,
298 	.display.has_overlay = 1,
299 };
300 
301 #define GEN4_FEATURES \
302 	GEN(4), \
303 	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
304 	.display.has_hotplug = 1, \
305 	.display.has_gmch = 1, \
306 	.gpu_reset_clobbers_display = true, \
307 	.engine_mask = BIT(RCS0), \
308 	.has_snoop = true, \
309 	.has_coherent_ggtt = true, \
310 	I9XX_PIPE_OFFSETS, \
311 	I9XX_CURSOR_OFFSETS, \
312 	I965_COLORS, \
313 	GEN_DEFAULT_PAGE_SIZES, \
314 	GEN_DEFAULT_REGIONS
315 
316 static const struct intel_device_info intel_i965g_info = {
317 	GEN4_FEATURES,
318 	PLATFORM(INTEL_I965G),
319 	.display.has_overlay = 1,
320 	.hws_needs_physical = 1,
321 	.has_snoop = false,
322 };
323 
324 static const struct intel_device_info intel_i965gm_info = {
325 	GEN4_FEATURES,
326 	PLATFORM(INTEL_I965GM),
327 	.is_mobile = 1,
328 	.display.has_fbc = 1,
329 	.display.has_overlay = 1,
330 	.display.supports_tv = 1,
331 	.hws_needs_physical = 1,
332 	.has_snoop = false,
333 };
334 
335 static const struct intel_device_info intel_g45_info = {
336 	GEN4_FEATURES,
337 	PLATFORM(INTEL_G45),
338 	.engine_mask = BIT(RCS0) | BIT(VCS0),
339 	.gpu_reset_clobbers_display = false,
340 };
341 
342 static const struct intel_device_info intel_gm45_info = {
343 	GEN4_FEATURES,
344 	PLATFORM(INTEL_GM45),
345 	.is_mobile = 1,
346 	.display.has_fbc = 1,
347 	.display.supports_tv = 1,
348 	.engine_mask = BIT(RCS0) | BIT(VCS0),
349 	.gpu_reset_clobbers_display = false,
350 };
351 
352 #define GEN5_FEATURES \
353 	GEN(5), \
354 	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
355 	.display.has_hotplug = 1, \
356 	.engine_mask = BIT(RCS0) | BIT(VCS0), \
357 	.has_snoop = true, \
358 	.has_coherent_ggtt = true, \
359 	/* ilk does support rc6, but we do not implement [power] contexts */ \
360 	.has_rc6 = 0, \
361 	I9XX_PIPE_OFFSETS, \
362 	I9XX_CURSOR_OFFSETS, \
363 	ILK_COLORS, \
364 	GEN_DEFAULT_PAGE_SIZES, \
365 	GEN_DEFAULT_REGIONS
366 
367 static const struct intel_device_info intel_ironlake_d_info = {
368 	GEN5_FEATURES,
369 	PLATFORM(INTEL_IRONLAKE),
370 };
371 
372 static const struct intel_device_info intel_ironlake_m_info = {
373 	GEN5_FEATURES,
374 	PLATFORM(INTEL_IRONLAKE),
375 	.is_mobile = 1,
376 	.display.has_fbc = 1,
377 };
378 
379 #define GEN6_FEATURES \
380 	GEN(6), \
381 	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
382 	.display.has_hotplug = 1, \
383 	.display.has_fbc = 1, \
384 	.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
385 	.has_coherent_ggtt = true, \
386 	.has_llc = 1, \
387 	.has_rc6 = 1, \
388 	.has_rc6p = 1, \
389 	.has_rps = true, \
390 	.ppgtt_type = INTEL_PPGTT_ALIASING, \
391 	.ppgtt_size = 31, \
392 	I9XX_PIPE_OFFSETS, \
393 	I9XX_CURSOR_OFFSETS, \
394 	ILK_COLORS, \
395 	GEN_DEFAULT_PAGE_SIZES, \
396 	GEN_DEFAULT_REGIONS
397 
398 #define SNB_D_PLATFORM \
399 	GEN6_FEATURES, \
400 	PLATFORM(INTEL_SANDYBRIDGE)
401 
402 static const struct intel_device_info intel_sandybridge_d_gt1_info = {
403 	SNB_D_PLATFORM,
404 	.gt = 1,
405 };
406 
407 static const struct intel_device_info intel_sandybridge_d_gt2_info = {
408 	SNB_D_PLATFORM,
409 	.gt = 2,
410 };
411 
412 #define SNB_M_PLATFORM \
413 	GEN6_FEATURES, \
414 	PLATFORM(INTEL_SANDYBRIDGE), \
415 	.is_mobile = 1
416 
417 
418 static const struct intel_device_info intel_sandybridge_m_gt1_info = {
419 	SNB_M_PLATFORM,
420 	.gt = 1,
421 };
422 
423 static const struct intel_device_info intel_sandybridge_m_gt2_info = {
424 	SNB_M_PLATFORM,
425 	.gt = 2,
426 };
427 
428 #define GEN7_FEATURES  \
429 	GEN(7), \
430 	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
431 	.display.has_hotplug = 1, \
432 	.display.has_fbc = 1, \
433 	.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
434 	.has_coherent_ggtt = true, \
435 	.has_llc = 1, \
436 	.has_rc6 = 1, \
437 	.has_rc6p = 1, \
438 	.has_rps = true, \
439 	.ppgtt_type = INTEL_PPGTT_ALIASING, \
440 	.ppgtt_size = 31, \
441 	IVB_PIPE_OFFSETS, \
442 	IVB_CURSOR_OFFSETS, \
443 	IVB_COLORS, \
444 	GEN_DEFAULT_PAGE_SIZES, \
445 	GEN_DEFAULT_REGIONS
446 
447 #define IVB_D_PLATFORM \
448 	GEN7_FEATURES, \
449 	PLATFORM(INTEL_IVYBRIDGE), \
450 	.has_l3_dpf = 1
451 
452 static const struct intel_device_info intel_ivybridge_d_gt1_info = {
453 	IVB_D_PLATFORM,
454 	.gt = 1,
455 };
456 
457 static const struct intel_device_info intel_ivybridge_d_gt2_info = {
458 	IVB_D_PLATFORM,
459 	.gt = 2,
460 };
461 
462 #define IVB_M_PLATFORM \
463 	GEN7_FEATURES, \
464 	PLATFORM(INTEL_IVYBRIDGE), \
465 	.is_mobile = 1, \
466 	.has_l3_dpf = 1
467 
468 static const struct intel_device_info intel_ivybridge_m_gt1_info = {
469 	IVB_M_PLATFORM,
470 	.gt = 1,
471 };
472 
473 static const struct intel_device_info intel_ivybridge_m_gt2_info = {
474 	IVB_M_PLATFORM,
475 	.gt = 2,
476 };
477 
478 static const struct intel_device_info intel_ivybridge_q_info = {
479 	GEN7_FEATURES,
480 	PLATFORM(INTEL_IVYBRIDGE),
481 	.gt = 2,
482 	.pipe_mask = 0, /* legal, last one wins */
483 	.has_l3_dpf = 1,
484 };
485 
486 static const struct intel_device_info intel_valleyview_info = {
487 	PLATFORM(INTEL_VALLEYVIEW),
488 	GEN(7),
489 	.is_lp = 1,
490 	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
491 	.has_runtime_pm = 1,
492 	.has_rc6 = 1,
493 	.has_rps = true,
494 	.display.has_gmch = 1,
495 	.display.has_hotplug = 1,
496 	.ppgtt_type = INTEL_PPGTT_ALIASING,
497 	.ppgtt_size = 31,
498 	.has_snoop = true,
499 	.has_coherent_ggtt = false,
500 	.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
501 	.display_mmio_offset = VLV_DISPLAY_BASE,
502 	I9XX_PIPE_OFFSETS,
503 	I9XX_CURSOR_OFFSETS,
504 	I965_COLORS,
505 	GEN_DEFAULT_PAGE_SIZES,
506 	GEN_DEFAULT_REGIONS,
507 };
508 
509 #define G75_FEATURES  \
510 	GEN7_FEATURES, \
511 	.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
512 	.display.has_ddi = 1, \
513 	.has_fpga_dbg = 1, \
514 	.display.has_psr = 1, \
515 	.display.has_dp_mst = 1, \
516 	.has_rc6p = 0 /* RC6p removed-by HSW */, \
517 	HSW_PIPE_OFFSETS, \
518 	.has_runtime_pm = 1
519 
520 #define HSW_PLATFORM \
521 	G75_FEATURES, \
522 	PLATFORM(INTEL_HASWELL), \
523 	.has_l3_dpf = 1
524 
525 static const struct intel_device_info intel_haswell_gt1_info = {
526 	HSW_PLATFORM,
527 	.gt = 1,
528 };
529 
530 static const struct intel_device_info intel_haswell_gt2_info = {
531 	HSW_PLATFORM,
532 	.gt = 2,
533 };
534 
535 static const struct intel_device_info intel_haswell_gt3_info = {
536 	HSW_PLATFORM,
537 	.gt = 3,
538 };
539 
540 #define GEN8_FEATURES \
541 	G75_FEATURES, \
542 	GEN(8), \
543 	.has_logical_ring_contexts = 1, \
544 	.ppgtt_type = INTEL_PPGTT_FULL, \
545 	.ppgtt_size = 48, \
546 	.has_64bit_reloc = 1, \
547 	.has_reset_engine = 1
548 
549 #define BDW_PLATFORM \
550 	GEN8_FEATURES, \
551 	PLATFORM(INTEL_BROADWELL)
552 
553 static const struct intel_device_info intel_broadwell_gt1_info = {
554 	BDW_PLATFORM,
555 	.gt = 1,
556 };
557 
558 static const struct intel_device_info intel_broadwell_gt2_info = {
559 	BDW_PLATFORM,
560 	.gt = 2,
561 };
562 
563 static const struct intel_device_info intel_broadwell_rsvd_info = {
564 	BDW_PLATFORM,
565 	.gt = 3,
566 	/* According to the device ID those devices are GT3, they were
567 	 * previously treated as not GT3, keep it like that.
568 	 */
569 };
570 
571 static const struct intel_device_info intel_broadwell_gt3_info = {
572 	BDW_PLATFORM,
573 	.gt = 3,
574 	.engine_mask =
575 		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
576 };
577 
578 static const struct intel_device_info intel_cherryview_info = {
579 	PLATFORM(INTEL_CHERRYVIEW),
580 	GEN(8),
581 	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
582 	.display.has_hotplug = 1,
583 	.is_lp = 1,
584 	.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
585 	.has_64bit_reloc = 1,
586 	.has_runtime_pm = 1,
587 	.has_rc6 = 1,
588 	.has_rps = true,
589 	.has_logical_ring_contexts = 1,
590 	.display.has_gmch = 1,
591 	.ppgtt_type = INTEL_PPGTT_ALIASING,
592 	.ppgtt_size = 32,
593 	.has_reset_engine = 1,
594 	.has_snoop = true,
595 	.has_coherent_ggtt = false,
596 	.display_mmio_offset = VLV_DISPLAY_BASE,
597 	CHV_PIPE_OFFSETS,
598 	CHV_CURSOR_OFFSETS,
599 	CHV_COLORS,
600 	GEN_DEFAULT_PAGE_SIZES,
601 	GEN_DEFAULT_REGIONS,
602 };
603 
604 #define GEN9_DEFAULT_PAGE_SIZES \
605 	.page_sizes = I915_GTT_PAGE_SIZE_4K | \
606 		      I915_GTT_PAGE_SIZE_64K
607 
608 #define GEN9_FEATURES \
609 	GEN8_FEATURES, \
610 	GEN(9), \
611 	GEN9_DEFAULT_PAGE_SIZES, \
612 	.has_logical_ring_preemption = 1, \
613 	.display.has_csr = 1, \
614 	.has_gt_uc = 1, \
615 	.display.has_hdcp = 1, \
616 	.display.has_ipc = 1, \
617 	.ddb_size = 896
618 
619 #define SKL_PLATFORM \
620 	GEN9_FEATURES, \
621 	PLATFORM(INTEL_SKYLAKE)
622 
623 static const struct intel_device_info intel_skylake_gt1_info = {
624 	SKL_PLATFORM,
625 	.gt = 1,
626 };
627 
628 static const struct intel_device_info intel_skylake_gt2_info = {
629 	SKL_PLATFORM,
630 	.gt = 2,
631 };
632 
633 #define SKL_GT3_PLUS_PLATFORM \
634 	SKL_PLATFORM, \
635 	.engine_mask = \
636 		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
637 
638 
639 static const struct intel_device_info intel_skylake_gt3_info = {
640 	SKL_GT3_PLUS_PLATFORM,
641 	.gt = 3,
642 };
643 
644 static const struct intel_device_info intel_skylake_gt4_info = {
645 	SKL_GT3_PLUS_PLATFORM,
646 	.gt = 4,
647 };
648 
649 #define GEN9_LP_FEATURES \
650 	GEN(9), \
651 	.is_lp = 1, \
652 	.display.has_hotplug = 1, \
653 	.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
654 	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
655 	.has_64bit_reloc = 1, \
656 	.display.has_ddi = 1, \
657 	.has_fpga_dbg = 1, \
658 	.display.has_fbc = 1, \
659 	.display.has_hdcp = 1, \
660 	.display.has_psr = 1, \
661 	.has_runtime_pm = 1, \
662 	.display.has_csr = 1, \
663 	.has_rc6 = 1, \
664 	.has_rps = true, \
665 	.display.has_dp_mst = 1, \
666 	.has_logical_ring_contexts = 1, \
667 	.has_logical_ring_preemption = 1, \
668 	.has_gt_uc = 1, \
669 	.ppgtt_type = INTEL_PPGTT_FULL, \
670 	.ppgtt_size = 48, \
671 	.has_reset_engine = 1, \
672 	.has_snoop = true, \
673 	.has_coherent_ggtt = false, \
674 	.display.has_ipc = 1, \
675 	HSW_PIPE_OFFSETS, \
676 	IVB_CURSOR_OFFSETS, \
677 	IVB_COLORS, \
678 	GEN9_DEFAULT_PAGE_SIZES, \
679 	GEN_DEFAULT_REGIONS
680 
681 static const struct intel_device_info intel_broxton_info = {
682 	GEN9_LP_FEATURES,
683 	PLATFORM(INTEL_BROXTON),
684 	.ddb_size = 512,
685 };
686 
687 static const struct intel_device_info intel_geminilake_info = {
688 	GEN9_LP_FEATURES,
689 	PLATFORM(INTEL_GEMINILAKE),
690 	.ddb_size = 1024,
691 	GLK_COLORS,
692 };
693 
694 #define KBL_PLATFORM \
695 	GEN9_FEATURES, \
696 	PLATFORM(INTEL_KABYLAKE)
697 
698 static const struct intel_device_info intel_kabylake_gt1_info = {
699 	KBL_PLATFORM,
700 	.gt = 1,
701 };
702 
703 static const struct intel_device_info intel_kabylake_gt2_info = {
704 	KBL_PLATFORM,
705 	.gt = 2,
706 };
707 
708 static const struct intel_device_info intel_kabylake_gt3_info = {
709 	KBL_PLATFORM,
710 	.gt = 3,
711 	.engine_mask =
712 		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
713 };
714 
715 #define CFL_PLATFORM \
716 	GEN9_FEATURES, \
717 	PLATFORM(INTEL_COFFEELAKE)
718 
719 static const struct intel_device_info intel_coffeelake_gt1_info = {
720 	CFL_PLATFORM,
721 	.gt = 1,
722 };
723 
724 static const struct intel_device_info intel_coffeelake_gt2_info = {
725 	CFL_PLATFORM,
726 	.gt = 2,
727 };
728 
729 static const struct intel_device_info intel_coffeelake_gt3_info = {
730 	CFL_PLATFORM,
731 	.gt = 3,
732 	.engine_mask =
733 		BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
734 };
735 
736 #define GEN10_FEATURES \
737 	GEN9_FEATURES, \
738 	GEN(10), \
739 	.ddb_size = 1024, \
740 	.display.has_dsc = 1, \
741 	.has_coherent_ggtt = false, \
742 	GLK_COLORS
743 
744 static const struct intel_device_info intel_cannonlake_info = {
745 	GEN10_FEATURES,
746 	PLATFORM(INTEL_CANNONLAKE),
747 	.gt = 2,
748 };
749 
750 #define GEN11_DEFAULT_PAGE_SIZES \
751 	.page_sizes = I915_GTT_PAGE_SIZE_4K | \
752 		      I915_GTT_PAGE_SIZE_64K | \
753 		      I915_GTT_PAGE_SIZE_2M
754 
755 #define GEN11_FEATURES \
756 	GEN10_FEATURES, \
757 	GEN11_DEFAULT_PAGE_SIZES, \
758 	.pipe_offsets = { \
759 		[TRANSCODER_A] = PIPE_A_OFFSET, \
760 		[TRANSCODER_B] = PIPE_B_OFFSET, \
761 		[TRANSCODER_C] = PIPE_C_OFFSET, \
762 		[TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
763 		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
764 		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
765 	}, \
766 	.trans_offsets = { \
767 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
768 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
769 		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
770 		[TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
771 		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
772 		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
773 	}, \
774 	GEN(11), \
775 	.ddb_size = 2048, \
776 	.has_logical_ring_elsq = 1, \
777 	.color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }
778 
779 static const struct intel_device_info intel_icelake_11_info = {
780 	GEN11_FEATURES,
781 	PLATFORM(INTEL_ICELAKE),
782 	.engine_mask =
783 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
784 };
785 
786 static const struct intel_device_info intel_elkhartlake_info = {
787 	GEN11_FEATURES,
788 	PLATFORM(INTEL_ELKHARTLAKE),
789 	.require_force_probe = 1,
790 	.engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
791 	.ppgtt_size = 36,
792 };
793 
794 #define GEN12_FEATURES \
795 	GEN11_FEATURES, \
796 	GEN(12), \
797 	.pipe_offsets = { \
798 		[TRANSCODER_A] = PIPE_A_OFFSET, \
799 		[TRANSCODER_B] = PIPE_B_OFFSET, \
800 		[TRANSCODER_C] = PIPE_C_OFFSET, \
801 		[TRANSCODER_D] = PIPE_D_OFFSET, \
802 		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
803 		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
804 	}, \
805 	.trans_offsets = { \
806 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
807 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
808 		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
809 		[TRANSCODER_D] = TRANSCODER_D_OFFSET, \
810 		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
811 		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
812 	}, \
813 	TGL_CURSOR_OFFSETS, \
814 	.has_global_mocs = 1, \
815 	.display.has_dsb = 1
816 
817 static const struct intel_device_info intel_tigerlake_12_info = {
818 	GEN12_FEATURES,
819 	PLATFORM(INTEL_TIGERLAKE),
820 	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
821 	.require_force_probe = 1,
822 	.display.has_modular_fia = 1,
823 	.engine_mask =
824 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
825 	.has_rps = false, /* XXX disabled for debugging */
826 };
827 
828 #define GEN12_DGFX_FEATURES \
829 	GEN12_FEATURES, \
830 	.is_dgfx = 1
831 
832 #undef GEN
833 #undef PLATFORM
834 
835 /*
836  * Make sure any device matches here are from most specific to most
837  * general.  For example, since the Quanta match is based on the subsystem
838  * and subvendor IDs, we need it to come before the more general IVB
839  * PCI ID matches, otherwise we'll use the wrong info struct above.
840  */
841 static const struct pci_device_id pciidlist[] = {
842 	INTEL_I830_IDS(&intel_i830_info),
843 	INTEL_I845G_IDS(&intel_i845g_info),
844 	INTEL_I85X_IDS(&intel_i85x_info),
845 	INTEL_I865G_IDS(&intel_i865g_info),
846 	INTEL_I915G_IDS(&intel_i915g_info),
847 	INTEL_I915GM_IDS(&intel_i915gm_info),
848 	INTEL_I945G_IDS(&intel_i945g_info),
849 	INTEL_I945GM_IDS(&intel_i945gm_info),
850 	INTEL_I965G_IDS(&intel_i965g_info),
851 	INTEL_G33_IDS(&intel_g33_info),
852 	INTEL_I965GM_IDS(&intel_i965gm_info),
853 	INTEL_GM45_IDS(&intel_gm45_info),
854 	INTEL_G45_IDS(&intel_g45_info),
855 	INTEL_PINEVIEW_G_IDS(&intel_pineview_g_info),
856 	INTEL_PINEVIEW_M_IDS(&intel_pineview_m_info),
857 	INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
858 	INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
859 	INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info),
860 	INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info),
861 	INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info),
862 	INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info),
863 	INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
864 	INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info),
865 	INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info),
866 	INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info),
867 	INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info),
868 	INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info),
869 	INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info),
870 	INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info),
871 	INTEL_VLV_IDS(&intel_valleyview_info),
872 	INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
873 	INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info),
874 	INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
875 	INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info),
876 	INTEL_CHV_IDS(&intel_cherryview_info),
877 	INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info),
878 	INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info),
879 	INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
880 	INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info),
881 	INTEL_BXT_IDS(&intel_broxton_info),
882 	INTEL_GLK_IDS(&intel_geminilake_info),
883 	INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info),
884 	INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info),
885 	INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
886 	INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
887 	INTEL_AML_KBL_GT2_IDS(&intel_kabylake_gt2_info),
888 	INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
889 	INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
890 	INTEL_CFL_H_GT1_IDS(&intel_coffeelake_gt1_info),
891 	INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
892 	INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),
893 	INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
894 	INTEL_WHL_U_GT1_IDS(&intel_coffeelake_gt1_info),
895 	INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info),
896 	INTEL_AML_CFL_GT2_IDS(&intel_coffeelake_gt2_info),
897 	INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info),
898 	INTEL_CML_GT1_IDS(&intel_coffeelake_gt1_info),
899 	INTEL_CML_GT2_IDS(&intel_coffeelake_gt2_info),
900 	INTEL_CNL_IDS(&intel_cannonlake_info),
901 	INTEL_ICL_11_IDS(&intel_icelake_11_info),
902 	INTEL_EHL_IDS(&intel_elkhartlake_info),
903 	INTEL_TGL_12_IDS(&intel_tigerlake_12_info),
904 	{0, 0, 0}
905 };
906 MODULE_DEVICE_TABLE(pci, pciidlist);
907 
908 static void i915_pci_remove(struct pci_dev *pdev)
909 {
910 	struct drm_i915_private *i915;
911 
912 	i915 = pci_get_drvdata(pdev);
913 	if (!i915) /* driver load aborted, nothing to cleanup */
914 		return;
915 
916 	i915_driver_remove(i915);
917 	pci_set_drvdata(pdev, NULL);
918 
919 	drm_dev_put(&i915->drm);
920 }
921 
922 /* is device_id present in comma separated list of ids */
923 static bool force_probe(u16 device_id, const char *devices)
924 {
925 	char *s, *p, *tok;
926 	bool ret;
927 
928 	/* FIXME: transitional */
929 	if (i915_modparams.alpha_support) {
930 		DRM_INFO("i915.alpha_support is deprecated, use i915.force_probe=%04x instead\n",
931 			 device_id);
932 		return true;
933 	}
934 
935 	if (!devices || !*devices)
936 		return false;
937 
938 	/* match everything */
939 	if (strcmp(devices, "*") == 0)
940 		return true;
941 
942 	s = kstrdup(devices, GFP_KERNEL);
943 	if (!s)
944 		return false;
945 
946 	for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) {
947 		u16 val;
948 
949 		if (kstrtou16(tok, 16, &val) == 0 && val == device_id) {
950 			ret = true;
951 			break;
952 		}
953 	}
954 
955 	kfree(s);
956 
957 	return ret;
958 }
959 
960 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
961 {
962 	struct intel_device_info *intel_info =
963 		(struct intel_device_info *) ent->driver_data;
964 	int err;
965 
966 	if (intel_info->require_force_probe &&
967 	    !force_probe(pdev->device, i915_modparams.force_probe)) {
968 		DRM_INFO("Your graphics device %04x is not properly supported by the driver in this\n"
969 			 "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n"
970 			 "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n"
971 			 "or (recommended) check for kernel updates.\n",
972 			 pdev->device, pdev->device, pdev->device);
973 		return -ENODEV;
974 	}
975 
976 	/* Only bind to function 0 of the device. Early generations
977 	 * used function 1 as a placeholder for multi-head. This causes
978 	 * us confusion instead, especially on the systems where both
979 	 * functions have the same PCI-ID!
980 	 */
981 	if (PCI_FUNC(pdev->devfn))
982 		return -ENODEV;
983 
984 	/*
985 	 * apple-gmux is needed on dual GPU MacBook Pro
986 	 * to probe the panel if we're the inactive GPU.
987 	 */
988 	if (vga_switcheroo_client_probe_defer(pdev))
989 		return -EPROBE_DEFER;
990 
991 	err = i915_driver_probe(pdev, ent);
992 	if (err)
993 		return err;
994 
995 	if (i915_inject_probe_failure(pci_get_drvdata(pdev))) {
996 		i915_pci_remove(pdev);
997 		return -ENODEV;
998 	}
999 
1000 	err = i915_live_selftests(pdev);
1001 	if (err) {
1002 		i915_pci_remove(pdev);
1003 		return err > 0 ? -ENOTTY : err;
1004 	}
1005 
1006 	return 0;
1007 }
1008 
1009 static struct pci_driver i915_pci_driver = {
1010 	.name = DRIVER_NAME,
1011 	.id_table = pciidlist,
1012 	.probe = i915_pci_probe,
1013 	.remove = i915_pci_remove,
1014 	.driver.pm = &i915_pm_ops,
1015 };
1016 
1017 static int __init i915_init(void)
1018 {
1019 	bool use_kms = true;
1020 	int err;
1021 
1022 	err = i915_globals_init();
1023 	if (err)
1024 		return err;
1025 
1026 	err = i915_mock_selftests();
1027 	if (err)
1028 		return err > 0 ? 0 : err;
1029 
1030 	/*
1031 	 * Enable KMS by default, unless explicitly overriden by
1032 	 * either the i915.modeset prarameter or by the
1033 	 * vga_text_mode_force boot option.
1034 	 */
1035 
1036 	if (i915_modparams.modeset == 0)
1037 		use_kms = false;
1038 
1039 	if (vgacon_text_force() && i915_modparams.modeset == -1)
1040 		use_kms = false;
1041 
1042 	if (!use_kms) {
1043 		/* Silently fail loading to not upset userspace. */
1044 		DRM_DEBUG_DRIVER("KMS disabled.\n");
1045 		return 0;
1046 	}
1047 
1048 	return pci_register_driver(&i915_pci_driver);
1049 }
1050 
1051 static void __exit i915_exit(void)
1052 {
1053 	if (!i915_pci_driver.driver.owner)
1054 		return;
1055 
1056 	pci_unregister_driver(&i915_pci_driver);
1057 	i915_globals_exit();
1058 }
1059 
1060 module_init(i915_init);
1061 module_exit(i915_exit);
1062 
1063 MODULE_AUTHOR("Tungsten Graphics, Inc.");
1064 MODULE_AUTHOR("Intel Corporation");
1065 
1066 MODULE_DESCRIPTION(DRIVER_DESC);
1067 MODULE_LICENSE("GPL and additional rights");
1068