1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/console.h> 26 #include <linux/vgaarb.h> 27 #include <linux/vga_switcheroo.h> 28 29 #include "i915_drv.h" 30 #include "i915_selftest.h" 31 32 #define GEN_DEFAULT_PIPEOFFSETS \ 33 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ 34 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \ 35 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ 36 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \ 37 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET } 38 39 #define GEN_CHV_PIPEOFFSETS \ 40 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ 41 CHV_PIPE_C_OFFSET }, \ 42 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ 43 CHV_TRANSCODER_C_OFFSET, }, \ 44 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \ 45 CHV_PALETTE_C_OFFSET } 46 47 #define CURSOR_OFFSETS \ 48 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET } 49 50 #define IVB_CURSOR_OFFSETS \ 51 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET } 52 53 #define BDW_COLORS \ 54 .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 } 55 #define CHV_COLORS \ 56 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 } 57 58 /* Keep in gen based order, and chronological order within a gen */ 59 #define GEN2_FEATURES \ 60 .gen = 2, .num_pipes = 1, \ 61 .has_overlay = 1, .overlay_needs_physical = 1, \ 62 .has_gmch_display = 1, \ 63 .hws_needs_physical = 1, \ 64 .unfenced_needs_alignment = 1, \ 65 .ring_mask = RENDER_RING, \ 66 GEN_DEFAULT_PIPEOFFSETS, \ 67 CURSOR_OFFSETS 68 69 static const struct intel_device_info intel_i830_info = { 70 GEN2_FEATURES, 71 .platform = INTEL_I830, 72 .is_mobile = 1, .cursor_needs_physical = 1, 73 .num_pipes = 2, /* legal, last one wins */ 74 }; 75 76 static const struct intel_device_info intel_i845g_info = { 77 GEN2_FEATURES, 78 .platform = INTEL_I845G, 79 }; 80 81 static const struct intel_device_info intel_i85x_info = { 82 GEN2_FEATURES, 83 .platform = INTEL_I85X, .is_mobile = 1, 84 .num_pipes = 2, /* legal, last one wins */ 85 .cursor_needs_physical = 1, 86 .has_fbc = 1, 87 }; 88 89 static const struct intel_device_info intel_i865g_info = { 90 GEN2_FEATURES, 91 .platform = INTEL_I865G, 92 }; 93 94 #define GEN3_FEATURES \ 95 .gen = 3, .num_pipes = 2, \ 96 .has_gmch_display = 1, \ 97 .ring_mask = RENDER_RING, \ 98 GEN_DEFAULT_PIPEOFFSETS, \ 99 CURSOR_OFFSETS 100 101 static const struct intel_device_info intel_i915g_info = { 102 GEN3_FEATURES, 103 .platform = INTEL_I915G, .cursor_needs_physical = 1, 104 .has_overlay = 1, .overlay_needs_physical = 1, 105 .hws_needs_physical = 1, 106 .unfenced_needs_alignment = 1, 107 }; 108 109 static const struct intel_device_info intel_i915gm_info = { 110 GEN3_FEATURES, 111 .platform = INTEL_I915GM, 112 .is_mobile = 1, 113 .cursor_needs_physical = 1, 114 .has_overlay = 1, .overlay_needs_physical = 1, 115 .supports_tv = 1, 116 .has_fbc = 1, 117 .hws_needs_physical = 1, 118 .unfenced_needs_alignment = 1, 119 }; 120 121 static const struct intel_device_info intel_i945g_info = { 122 GEN3_FEATURES, 123 .platform = INTEL_I945G, 124 .has_hotplug = 1, .cursor_needs_physical = 1, 125 .has_overlay = 1, .overlay_needs_physical = 1, 126 .hws_needs_physical = 1, 127 .unfenced_needs_alignment = 1, 128 }; 129 130 static const struct intel_device_info intel_i945gm_info = { 131 GEN3_FEATURES, 132 .platform = INTEL_I945GM, .is_mobile = 1, 133 .has_hotplug = 1, .cursor_needs_physical = 1, 134 .has_overlay = 1, .overlay_needs_physical = 1, 135 .supports_tv = 1, 136 .has_fbc = 1, 137 .hws_needs_physical = 1, 138 .unfenced_needs_alignment = 1, 139 }; 140 141 static const struct intel_device_info intel_g33_info = { 142 GEN3_FEATURES, 143 .platform = INTEL_G33, 144 .has_hotplug = 1, 145 .has_overlay = 1, 146 }; 147 148 static const struct intel_device_info intel_pineview_info = { 149 GEN3_FEATURES, 150 .platform = INTEL_PINEVIEW, .is_mobile = 1, 151 .has_hotplug = 1, 152 .has_overlay = 1, 153 }; 154 155 #define GEN4_FEATURES \ 156 .gen = 4, .num_pipes = 2, \ 157 .has_hotplug = 1, \ 158 .has_gmch_display = 1, \ 159 .ring_mask = RENDER_RING, \ 160 GEN_DEFAULT_PIPEOFFSETS, \ 161 CURSOR_OFFSETS 162 163 static const struct intel_device_info intel_i965g_info = { 164 GEN4_FEATURES, 165 .platform = INTEL_I965G, 166 .has_overlay = 1, 167 .hws_needs_physical = 1, 168 }; 169 170 static const struct intel_device_info intel_i965gm_info = { 171 GEN4_FEATURES, 172 .platform = INTEL_I965GM, 173 .is_mobile = 1, .has_fbc = 1, 174 .has_overlay = 1, 175 .supports_tv = 1, 176 .hws_needs_physical = 1, 177 }; 178 179 static const struct intel_device_info intel_g45_info = { 180 GEN4_FEATURES, 181 .platform = INTEL_G45, 182 .has_pipe_cxsr = 1, 183 .ring_mask = RENDER_RING | BSD_RING, 184 }; 185 186 static const struct intel_device_info intel_gm45_info = { 187 GEN4_FEATURES, 188 .platform = INTEL_GM45, 189 .is_mobile = 1, .has_fbc = 1, 190 .has_pipe_cxsr = 1, 191 .supports_tv = 1, 192 .ring_mask = RENDER_RING | BSD_RING, 193 }; 194 195 #define GEN5_FEATURES \ 196 .gen = 5, .num_pipes = 2, \ 197 .has_hotplug = 1, \ 198 .has_gmbus_irq = 1, \ 199 .ring_mask = RENDER_RING | BSD_RING, \ 200 GEN_DEFAULT_PIPEOFFSETS, \ 201 CURSOR_OFFSETS 202 203 static const struct intel_device_info intel_ironlake_d_info = { 204 GEN5_FEATURES, 205 .platform = INTEL_IRONLAKE, 206 }; 207 208 static const struct intel_device_info intel_ironlake_m_info = { 209 GEN5_FEATURES, 210 .platform = INTEL_IRONLAKE, 211 .is_mobile = 1, .has_fbc = 1, 212 }; 213 214 #define GEN6_FEATURES \ 215 .gen = 6, .num_pipes = 2, \ 216 .has_hotplug = 1, \ 217 .has_fbc = 1, \ 218 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ 219 .has_llc = 1, \ 220 .has_rc6 = 1, \ 221 .has_rc6p = 1, \ 222 .has_gmbus_irq = 1, \ 223 .has_aliasing_ppgtt = 1, \ 224 GEN_DEFAULT_PIPEOFFSETS, \ 225 CURSOR_OFFSETS 226 227 static const struct intel_device_info intel_sandybridge_d_info = { 228 GEN6_FEATURES, 229 .platform = INTEL_SANDYBRIDGE, 230 }; 231 232 static const struct intel_device_info intel_sandybridge_m_info = { 233 GEN6_FEATURES, 234 .platform = INTEL_SANDYBRIDGE, 235 .is_mobile = 1, 236 }; 237 238 #define GEN7_FEATURES \ 239 .gen = 7, .num_pipes = 3, \ 240 .has_hotplug = 1, \ 241 .has_fbc = 1, \ 242 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ 243 .has_llc = 1, \ 244 .has_rc6 = 1, \ 245 .has_rc6p = 1, \ 246 .has_gmbus_irq = 1, \ 247 .has_aliasing_ppgtt = 1, \ 248 .has_full_ppgtt = 1, \ 249 GEN_DEFAULT_PIPEOFFSETS, \ 250 IVB_CURSOR_OFFSETS 251 252 static const struct intel_device_info intel_ivybridge_d_info = { 253 GEN7_FEATURES, 254 .platform = INTEL_IVYBRIDGE, 255 .has_l3_dpf = 1, 256 }; 257 258 static const struct intel_device_info intel_ivybridge_m_info = { 259 GEN7_FEATURES, 260 .platform = INTEL_IVYBRIDGE, 261 .is_mobile = 1, 262 .has_l3_dpf = 1, 263 }; 264 265 static const struct intel_device_info intel_ivybridge_q_info = { 266 GEN7_FEATURES, 267 .platform = INTEL_IVYBRIDGE, 268 .num_pipes = 0, /* legal, last one wins */ 269 .has_l3_dpf = 1, 270 }; 271 272 static const struct intel_device_info intel_valleyview_info = { 273 .platform = INTEL_VALLEYVIEW, 274 .gen = 7, 275 .is_lp = 1, 276 .num_pipes = 2, 277 .has_psr = 1, 278 .has_runtime_pm = 1, 279 .has_rc6 = 1, 280 .has_gmbus_irq = 1, 281 .has_gmch_display = 1, 282 .has_hotplug = 1, 283 .has_aliasing_ppgtt = 1, 284 .has_full_ppgtt = 1, 285 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, 286 .display_mmio_offset = VLV_DISPLAY_BASE, 287 GEN_DEFAULT_PIPEOFFSETS, 288 CURSOR_OFFSETS 289 }; 290 291 #define HSW_FEATURES \ 292 GEN7_FEATURES, \ 293 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \ 294 .has_ddi = 1, \ 295 .has_fpga_dbg = 1, \ 296 .has_psr = 1, \ 297 .has_resource_streamer = 1, \ 298 .has_dp_mst = 1, \ 299 .has_rc6p = 0 /* RC6p removed-by HSW */, \ 300 .has_runtime_pm = 1 301 302 static const struct intel_device_info intel_haswell_info = { 303 HSW_FEATURES, 304 .platform = INTEL_HASWELL, 305 .has_l3_dpf = 1, 306 }; 307 308 #define BDW_FEATURES \ 309 HSW_FEATURES, \ 310 BDW_COLORS, \ 311 .has_logical_ring_contexts = 1, \ 312 .has_full_48bit_ppgtt = 1, \ 313 .has_64bit_reloc = 1 314 315 #define BDW_PLATFORM \ 316 BDW_FEATURES, \ 317 .gen = 8, \ 318 .platform = INTEL_BROADWELL 319 320 static const struct intel_device_info intel_broadwell_info = { 321 BDW_PLATFORM, 322 }; 323 324 static const struct intel_device_info intel_broadwell_gt3_info = { 325 BDW_PLATFORM, 326 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 327 }; 328 329 static const struct intel_device_info intel_cherryview_info = { 330 .gen = 8, .num_pipes = 3, 331 .has_hotplug = 1, 332 .is_lp = 1, 333 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, 334 .platform = INTEL_CHERRYVIEW, 335 .has_64bit_reloc = 1, 336 .has_psr = 1, 337 .has_runtime_pm = 1, 338 .has_resource_streamer = 1, 339 .has_rc6 = 1, 340 .has_gmbus_irq = 1, 341 .has_logical_ring_contexts = 1, 342 .has_gmch_display = 1, 343 .has_aliasing_ppgtt = 1, 344 .has_full_ppgtt = 1, 345 .display_mmio_offset = VLV_DISPLAY_BASE, 346 GEN_CHV_PIPEOFFSETS, 347 CURSOR_OFFSETS, 348 CHV_COLORS, 349 }; 350 351 #define SKL_PLATFORM \ 352 BDW_FEATURES, \ 353 .gen = 9, \ 354 .platform = INTEL_SKYLAKE, \ 355 .has_csr = 1, \ 356 .has_guc = 1, \ 357 .ddb_size = 896 358 359 static const struct intel_device_info intel_skylake_info = { 360 SKL_PLATFORM, 361 }; 362 363 static const struct intel_device_info intel_skylake_gt3_info = { 364 SKL_PLATFORM, 365 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 366 }; 367 368 #define GEN9_LP_FEATURES \ 369 .gen = 9, \ 370 .is_lp = 1, \ 371 .has_hotplug = 1, \ 372 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \ 373 .num_pipes = 3, \ 374 .has_64bit_reloc = 1, \ 375 .has_ddi = 1, \ 376 .has_fpga_dbg = 1, \ 377 .has_fbc = 1, \ 378 .has_runtime_pm = 1, \ 379 .has_pooled_eu = 0, \ 380 .has_csr = 1, \ 381 .has_resource_streamer = 1, \ 382 .has_rc6 = 1, \ 383 .has_dp_mst = 1, \ 384 .has_gmbus_irq = 1, \ 385 .has_logical_ring_contexts = 1, \ 386 .has_guc = 1, \ 387 .has_aliasing_ppgtt = 1, \ 388 .has_full_ppgtt = 1, \ 389 .has_full_48bit_ppgtt = 1, \ 390 GEN_DEFAULT_PIPEOFFSETS, \ 391 IVB_CURSOR_OFFSETS, \ 392 BDW_COLORS 393 394 static const struct intel_device_info intel_broxton_info = { 395 GEN9_LP_FEATURES, 396 .platform = INTEL_BROXTON, 397 .ddb_size = 512, 398 }; 399 400 static const struct intel_device_info intel_geminilake_info = { 401 GEN9_LP_FEATURES, 402 .platform = INTEL_GEMINILAKE, 403 .ddb_size = 1024, 404 .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 } 405 }; 406 407 #define KBL_PLATFORM \ 408 BDW_FEATURES, \ 409 .gen = 9, \ 410 .platform = INTEL_KABYLAKE, \ 411 .has_csr = 1, \ 412 .has_guc = 1, \ 413 .ddb_size = 896 414 415 static const struct intel_device_info intel_kabylake_info = { 416 KBL_PLATFORM, 417 }; 418 419 static const struct intel_device_info intel_kabylake_gt3_info = { 420 KBL_PLATFORM, 421 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 422 }; 423 424 #define CFL_PLATFORM \ 425 .is_alpha_support = 1, \ 426 BDW_FEATURES, \ 427 .gen = 9, \ 428 .platform = INTEL_COFFEELAKE, \ 429 .has_csr = 1, \ 430 .has_guc = 1, \ 431 .ddb_size = 896 432 433 static const struct intel_device_info intel_coffeelake_info = { 434 CFL_PLATFORM, 435 }; 436 437 static const struct intel_device_info intel_coffeelake_gt3_info = { 438 CFL_PLATFORM, 439 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 440 }; 441 442 static const struct intel_device_info intel_cannonlake_info = { 443 BDW_FEATURES, 444 .is_alpha_support = 1, 445 .platform = INTEL_CANNONLAKE, 446 .gen = 10, 447 .ddb_size = 1024, 448 .has_csr = 1, 449 }; 450 451 /* 452 * Make sure any device matches here are from most specific to most 453 * general. For example, since the Quanta match is based on the subsystem 454 * and subvendor IDs, we need it to come before the more general IVB 455 * PCI ID matches, otherwise we'll use the wrong info struct above. 456 */ 457 static const struct pci_device_id pciidlist[] = { 458 INTEL_I830_IDS(&intel_i830_info), 459 INTEL_I845G_IDS(&intel_i845g_info), 460 INTEL_I85X_IDS(&intel_i85x_info), 461 INTEL_I865G_IDS(&intel_i865g_info), 462 INTEL_I915G_IDS(&intel_i915g_info), 463 INTEL_I915GM_IDS(&intel_i915gm_info), 464 INTEL_I945G_IDS(&intel_i945g_info), 465 INTEL_I945GM_IDS(&intel_i945gm_info), 466 INTEL_I965G_IDS(&intel_i965g_info), 467 INTEL_G33_IDS(&intel_g33_info), 468 INTEL_I965GM_IDS(&intel_i965gm_info), 469 INTEL_GM45_IDS(&intel_gm45_info), 470 INTEL_G45_IDS(&intel_g45_info), 471 INTEL_PINEVIEW_IDS(&intel_pineview_info), 472 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), 473 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), 474 INTEL_SNB_D_IDS(&intel_sandybridge_d_info), 475 INTEL_SNB_M_IDS(&intel_sandybridge_m_info), 476 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ 477 INTEL_IVB_M_IDS(&intel_ivybridge_m_info), 478 INTEL_IVB_D_IDS(&intel_ivybridge_d_info), 479 INTEL_HSW_IDS(&intel_haswell_info), 480 INTEL_VLV_IDS(&intel_valleyview_info), 481 INTEL_BDW_GT12_IDS(&intel_broadwell_info), 482 INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info), 483 INTEL_BDW_RSVD_IDS(&intel_broadwell_info), 484 INTEL_CHV_IDS(&intel_cherryview_info), 485 INTEL_SKL_GT1_IDS(&intel_skylake_info), 486 INTEL_SKL_GT2_IDS(&intel_skylake_info), 487 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), 488 INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info), 489 INTEL_BXT_IDS(&intel_broxton_info), 490 INTEL_GLK_IDS(&intel_geminilake_info), 491 INTEL_KBL_GT1_IDS(&intel_kabylake_info), 492 INTEL_KBL_GT2_IDS(&intel_kabylake_info), 493 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info), 494 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info), 495 INTEL_CFL_S_IDS(&intel_coffeelake_info), 496 INTEL_CFL_H_IDS(&intel_coffeelake_info), 497 INTEL_CFL_U_IDS(&intel_coffeelake_gt3_info), 498 INTEL_CNL_IDS(&intel_cannonlake_info), 499 {0, 0, 0} 500 }; 501 MODULE_DEVICE_TABLE(pci, pciidlist); 502 503 static void i915_pci_remove(struct pci_dev *pdev) 504 { 505 struct drm_device *dev = pci_get_drvdata(pdev); 506 507 i915_driver_unload(dev); 508 drm_dev_unref(dev); 509 } 510 511 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 512 { 513 struct intel_device_info *intel_info = 514 (struct intel_device_info *) ent->driver_data; 515 int err; 516 517 if (IS_ALPHA_SUPPORT(intel_info) && !i915.alpha_support) { 518 DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n" 519 "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n" 520 "to enable support in this kernel version, or check for kernel updates.\n"); 521 return -ENODEV; 522 } 523 524 /* Only bind to function 0 of the device. Early generations 525 * used function 1 as a placeholder for multi-head. This causes 526 * us confusion instead, especially on the systems where both 527 * functions have the same PCI-ID! 528 */ 529 if (PCI_FUNC(pdev->devfn)) 530 return -ENODEV; 531 532 /* 533 * apple-gmux is needed on dual GPU MacBook Pro 534 * to probe the panel if we're the inactive GPU. 535 */ 536 if (vga_switcheroo_client_probe_defer(pdev)) 537 return -EPROBE_DEFER; 538 539 err = i915_driver_load(pdev, ent); 540 if (err) 541 return err; 542 543 err = i915_live_selftests(pdev); 544 if (err) { 545 i915_pci_remove(pdev); 546 return err > 0 ? -ENOTTY : err; 547 } 548 549 return 0; 550 } 551 552 static struct pci_driver i915_pci_driver = { 553 .name = DRIVER_NAME, 554 .id_table = pciidlist, 555 .probe = i915_pci_probe, 556 .remove = i915_pci_remove, 557 .driver.pm = &i915_pm_ops, 558 }; 559 560 static int __init i915_init(void) 561 { 562 bool use_kms = true; 563 int err; 564 565 err = i915_mock_selftests(); 566 if (err) 567 return err > 0 ? 0 : err; 568 569 /* 570 * Enable KMS by default, unless explicitly overriden by 571 * either the i915.modeset prarameter or by the 572 * vga_text_mode_force boot option. 573 */ 574 575 if (i915.modeset == 0) 576 use_kms = false; 577 578 if (vgacon_text_force() && i915.modeset == -1) 579 use_kms = false; 580 581 if (!use_kms) { 582 /* Silently fail loading to not upset userspace. */ 583 DRM_DEBUG_DRIVER("KMS disabled.\n"); 584 return 0; 585 } 586 587 return pci_register_driver(&i915_pci_driver); 588 } 589 590 static void __exit i915_exit(void) 591 { 592 if (!i915_pci_driver.driver.owner) 593 return; 594 595 pci_unregister_driver(&i915_pci_driver); 596 } 597 598 module_init(i915_init); 599 module_exit(i915_exit); 600 601 MODULE_AUTHOR("Tungsten Graphics, Inc."); 602 MODULE_AUTHOR("Intel Corporation"); 603 604 MODULE_DESCRIPTION(DRIVER_DESC); 605 MODULE_LICENSE("GPL and additional rights"); 606