1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <drm/drm_color_mgmt.h> 26 #include <drm/drm_drv.h> 27 #include <drm/i915_pciids.h> 28 29 #include "i915_driver.h" 30 #include "i915_drv.h" 31 #include "i915_pci.h" 32 #include "i915_reg.h" 33 34 #define PLATFORM(x) .platform = (x) 35 #define GEN(x) \ 36 .graphics.ver = (x), \ 37 .media.ver = (x), \ 38 .display.ver = (x) 39 40 #define I845_PIPE_OFFSETS \ 41 .display.pipe_offsets = { \ 42 [TRANSCODER_A] = PIPE_A_OFFSET, \ 43 }, \ 44 .display.trans_offsets = { \ 45 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 46 } 47 48 #define I9XX_PIPE_OFFSETS \ 49 .display.pipe_offsets = { \ 50 [TRANSCODER_A] = PIPE_A_OFFSET, \ 51 [TRANSCODER_B] = PIPE_B_OFFSET, \ 52 }, \ 53 .display.trans_offsets = { \ 54 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 55 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 56 } 57 58 #define IVB_PIPE_OFFSETS \ 59 .display.pipe_offsets = { \ 60 [TRANSCODER_A] = PIPE_A_OFFSET, \ 61 [TRANSCODER_B] = PIPE_B_OFFSET, \ 62 [TRANSCODER_C] = PIPE_C_OFFSET, \ 63 }, \ 64 .display.trans_offsets = { \ 65 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 66 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 67 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 68 } 69 70 #define HSW_PIPE_OFFSETS \ 71 .display.pipe_offsets = { \ 72 [TRANSCODER_A] = PIPE_A_OFFSET, \ 73 [TRANSCODER_B] = PIPE_B_OFFSET, \ 74 [TRANSCODER_C] = PIPE_C_OFFSET, \ 75 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 76 }, \ 77 .display.trans_offsets = { \ 78 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 79 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 80 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 81 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 82 } 83 84 #define CHV_PIPE_OFFSETS \ 85 .display.pipe_offsets = { \ 86 [TRANSCODER_A] = PIPE_A_OFFSET, \ 87 [TRANSCODER_B] = PIPE_B_OFFSET, \ 88 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \ 89 }, \ 90 .display.trans_offsets = { \ 91 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 92 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 93 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \ 94 } 95 96 #define I845_CURSOR_OFFSETS \ 97 .display.cursor_offsets = { \ 98 [PIPE_A] = CURSOR_A_OFFSET, \ 99 } 100 101 #define I9XX_CURSOR_OFFSETS \ 102 .display.cursor_offsets = { \ 103 [PIPE_A] = CURSOR_A_OFFSET, \ 104 [PIPE_B] = CURSOR_B_OFFSET, \ 105 } 106 107 #define CHV_CURSOR_OFFSETS \ 108 .display.cursor_offsets = { \ 109 [PIPE_A] = CURSOR_A_OFFSET, \ 110 [PIPE_B] = CURSOR_B_OFFSET, \ 111 [PIPE_C] = CHV_CURSOR_C_OFFSET, \ 112 } 113 114 #define IVB_CURSOR_OFFSETS \ 115 .display.cursor_offsets = { \ 116 [PIPE_A] = CURSOR_A_OFFSET, \ 117 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 118 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 119 } 120 121 #define TGL_CURSOR_OFFSETS \ 122 .display.cursor_offsets = { \ 123 [PIPE_A] = CURSOR_A_OFFSET, \ 124 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 125 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 126 [PIPE_D] = TGL_CURSOR_D_OFFSET, \ 127 } 128 129 #define I9XX_COLORS \ 130 .display.color = { .gamma_lut_size = 256 } 131 #define I965_COLORS \ 132 .display.color = { .gamma_lut_size = 129, \ 133 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 134 } 135 #define ILK_COLORS \ 136 .display.color = { .gamma_lut_size = 1024 } 137 #define IVB_COLORS \ 138 .display.color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 } 139 #define CHV_COLORS \ 140 .display.color = { \ 141 .degamma_lut_size = 65, .gamma_lut_size = 257, \ 142 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 143 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 144 } 145 #define GLK_COLORS \ 146 .display.color = { \ 147 .degamma_lut_size = 33, .gamma_lut_size = 1024, \ 148 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 149 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 150 } 151 #define ICL_COLORS \ 152 .display.color = { \ 153 .degamma_lut_size = 33, .gamma_lut_size = 262145, \ 154 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 155 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 156 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 157 } 158 159 /* Keep in gen based order, and chronological order within a gen */ 160 161 #define GEN_DEFAULT_PAGE_SIZES \ 162 .page_sizes = I915_GTT_PAGE_SIZE_4K 163 164 #define GEN_DEFAULT_REGIONS \ 165 .memory_regions = REGION_SMEM | REGION_STOLEN_SMEM 166 167 #define I830_FEATURES \ 168 GEN(2), \ 169 .is_mobile = 1, \ 170 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 171 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 172 .display.has_overlay = 1, \ 173 .display.cursor_needs_physical = 1, \ 174 .display.overlay_needs_physical = 1, \ 175 .display.has_gmch = 1, \ 176 .gpu_reset_clobbers_display = true, \ 177 .has_3d_pipeline = 1, \ 178 .hws_needs_physical = 1, \ 179 .unfenced_needs_alignment = 1, \ 180 .platform_engine_mask = BIT(RCS0), \ 181 .has_snoop = true, \ 182 .has_coherent_ggtt = false, \ 183 .dma_mask_size = 32, \ 184 I9XX_PIPE_OFFSETS, \ 185 I9XX_CURSOR_OFFSETS, \ 186 I9XX_COLORS, \ 187 GEN_DEFAULT_PAGE_SIZES, \ 188 GEN_DEFAULT_REGIONS 189 190 #define I845_FEATURES \ 191 GEN(2), \ 192 .display.pipe_mask = BIT(PIPE_A), \ 193 .display.cpu_transcoder_mask = BIT(TRANSCODER_A), \ 194 .display.has_overlay = 1, \ 195 .display.overlay_needs_physical = 1, \ 196 .display.has_gmch = 1, \ 197 .has_3d_pipeline = 1, \ 198 .gpu_reset_clobbers_display = true, \ 199 .hws_needs_physical = 1, \ 200 .unfenced_needs_alignment = 1, \ 201 .platform_engine_mask = BIT(RCS0), \ 202 .has_snoop = true, \ 203 .has_coherent_ggtt = false, \ 204 .dma_mask_size = 32, \ 205 I845_PIPE_OFFSETS, \ 206 I845_CURSOR_OFFSETS, \ 207 I9XX_COLORS, \ 208 GEN_DEFAULT_PAGE_SIZES, \ 209 GEN_DEFAULT_REGIONS 210 211 static const struct intel_device_info i830_info = { 212 I830_FEATURES, 213 PLATFORM(INTEL_I830), 214 }; 215 216 static const struct intel_device_info i845g_info = { 217 I845_FEATURES, 218 PLATFORM(INTEL_I845G), 219 }; 220 221 static const struct intel_device_info i85x_info = { 222 I830_FEATURES, 223 PLATFORM(INTEL_I85X), 224 .display.fbc_mask = BIT(INTEL_FBC_A), 225 }; 226 227 static const struct intel_device_info i865g_info = { 228 I845_FEATURES, 229 PLATFORM(INTEL_I865G), 230 .display.fbc_mask = BIT(INTEL_FBC_A), 231 }; 232 233 #define GEN3_FEATURES \ 234 GEN(3), \ 235 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 236 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 237 .display.has_gmch = 1, \ 238 .gpu_reset_clobbers_display = true, \ 239 .platform_engine_mask = BIT(RCS0), \ 240 .has_3d_pipeline = 1, \ 241 .has_snoop = true, \ 242 .has_coherent_ggtt = true, \ 243 .dma_mask_size = 32, \ 244 I9XX_PIPE_OFFSETS, \ 245 I9XX_CURSOR_OFFSETS, \ 246 I9XX_COLORS, \ 247 GEN_DEFAULT_PAGE_SIZES, \ 248 GEN_DEFAULT_REGIONS 249 250 static const struct intel_device_info i915g_info = { 251 GEN3_FEATURES, 252 PLATFORM(INTEL_I915G), 253 .has_coherent_ggtt = false, 254 .display.cursor_needs_physical = 1, 255 .display.has_overlay = 1, 256 .display.overlay_needs_physical = 1, 257 .hws_needs_physical = 1, 258 .unfenced_needs_alignment = 1, 259 }; 260 261 static const struct intel_device_info i915gm_info = { 262 GEN3_FEATURES, 263 PLATFORM(INTEL_I915GM), 264 .is_mobile = 1, 265 .display.cursor_needs_physical = 1, 266 .display.has_overlay = 1, 267 .display.overlay_needs_physical = 1, 268 .display.supports_tv = 1, 269 .display.fbc_mask = BIT(INTEL_FBC_A), 270 .hws_needs_physical = 1, 271 .unfenced_needs_alignment = 1, 272 }; 273 274 static const struct intel_device_info i945g_info = { 275 GEN3_FEATURES, 276 PLATFORM(INTEL_I945G), 277 .display.has_hotplug = 1, 278 .display.cursor_needs_physical = 1, 279 .display.has_overlay = 1, 280 .display.overlay_needs_physical = 1, 281 .hws_needs_physical = 1, 282 .unfenced_needs_alignment = 1, 283 }; 284 285 static const struct intel_device_info i945gm_info = { 286 GEN3_FEATURES, 287 PLATFORM(INTEL_I945GM), 288 .is_mobile = 1, 289 .display.has_hotplug = 1, 290 .display.cursor_needs_physical = 1, 291 .display.has_overlay = 1, 292 .display.overlay_needs_physical = 1, 293 .display.supports_tv = 1, 294 .display.fbc_mask = BIT(INTEL_FBC_A), 295 .hws_needs_physical = 1, 296 .unfenced_needs_alignment = 1, 297 }; 298 299 static const struct intel_device_info g33_info = { 300 GEN3_FEATURES, 301 PLATFORM(INTEL_G33), 302 .display.has_hotplug = 1, 303 .display.has_overlay = 1, 304 .dma_mask_size = 36, 305 }; 306 307 static const struct intel_device_info pnv_g_info = { 308 GEN3_FEATURES, 309 PLATFORM(INTEL_PINEVIEW), 310 .display.has_hotplug = 1, 311 .display.has_overlay = 1, 312 .dma_mask_size = 36, 313 }; 314 315 static const struct intel_device_info pnv_m_info = { 316 GEN3_FEATURES, 317 PLATFORM(INTEL_PINEVIEW), 318 .is_mobile = 1, 319 .display.has_hotplug = 1, 320 .display.has_overlay = 1, 321 .dma_mask_size = 36, 322 }; 323 324 #define GEN4_FEATURES \ 325 GEN(4), \ 326 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 327 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 328 .display.has_hotplug = 1, \ 329 .display.has_gmch = 1, \ 330 .gpu_reset_clobbers_display = true, \ 331 .platform_engine_mask = BIT(RCS0), \ 332 .has_3d_pipeline = 1, \ 333 .has_snoop = true, \ 334 .has_coherent_ggtt = true, \ 335 .dma_mask_size = 36, \ 336 I9XX_PIPE_OFFSETS, \ 337 I9XX_CURSOR_OFFSETS, \ 338 I965_COLORS, \ 339 GEN_DEFAULT_PAGE_SIZES, \ 340 GEN_DEFAULT_REGIONS 341 342 static const struct intel_device_info i965g_info = { 343 GEN4_FEATURES, 344 PLATFORM(INTEL_I965G), 345 .display.has_overlay = 1, 346 .hws_needs_physical = 1, 347 .has_snoop = false, 348 }; 349 350 static const struct intel_device_info i965gm_info = { 351 GEN4_FEATURES, 352 PLATFORM(INTEL_I965GM), 353 .is_mobile = 1, 354 .display.fbc_mask = BIT(INTEL_FBC_A), 355 .display.has_overlay = 1, 356 .display.supports_tv = 1, 357 .hws_needs_physical = 1, 358 .has_snoop = false, 359 }; 360 361 static const struct intel_device_info g45_info = { 362 GEN4_FEATURES, 363 PLATFORM(INTEL_G45), 364 .platform_engine_mask = BIT(RCS0) | BIT(VCS0), 365 .gpu_reset_clobbers_display = false, 366 }; 367 368 static const struct intel_device_info gm45_info = { 369 GEN4_FEATURES, 370 PLATFORM(INTEL_GM45), 371 .is_mobile = 1, 372 .display.fbc_mask = BIT(INTEL_FBC_A), 373 .display.supports_tv = 1, 374 .platform_engine_mask = BIT(RCS0) | BIT(VCS0), 375 .gpu_reset_clobbers_display = false, 376 }; 377 378 #define GEN5_FEATURES \ 379 GEN(5), \ 380 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 381 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 382 .display.has_hotplug = 1, \ 383 .platform_engine_mask = BIT(RCS0) | BIT(VCS0), \ 384 .has_3d_pipeline = 1, \ 385 .has_snoop = true, \ 386 .has_coherent_ggtt = true, \ 387 /* ilk does support rc6, but we do not implement [power] contexts */ \ 388 .has_rc6 = 0, \ 389 .dma_mask_size = 36, \ 390 I9XX_PIPE_OFFSETS, \ 391 I9XX_CURSOR_OFFSETS, \ 392 ILK_COLORS, \ 393 GEN_DEFAULT_PAGE_SIZES, \ 394 GEN_DEFAULT_REGIONS 395 396 static const struct intel_device_info ilk_d_info = { 397 GEN5_FEATURES, 398 PLATFORM(INTEL_IRONLAKE), 399 }; 400 401 static const struct intel_device_info ilk_m_info = { 402 GEN5_FEATURES, 403 PLATFORM(INTEL_IRONLAKE), 404 .is_mobile = 1, 405 .has_rps = true, 406 .display.fbc_mask = BIT(INTEL_FBC_A), 407 }; 408 409 #define GEN6_FEATURES \ 410 GEN(6), \ 411 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 412 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 413 .display.has_hotplug = 1, \ 414 .display.fbc_mask = BIT(INTEL_FBC_A), \ 415 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ 416 .has_3d_pipeline = 1, \ 417 .has_coherent_ggtt = true, \ 418 .has_llc = 1, \ 419 .has_rc6 = 1, \ 420 .has_rc6p = 1, \ 421 .has_rps = true, \ 422 .dma_mask_size = 40, \ 423 .ppgtt_type = INTEL_PPGTT_ALIASING, \ 424 .ppgtt_size = 31, \ 425 I9XX_PIPE_OFFSETS, \ 426 I9XX_CURSOR_OFFSETS, \ 427 ILK_COLORS, \ 428 GEN_DEFAULT_PAGE_SIZES, \ 429 GEN_DEFAULT_REGIONS 430 431 #define SNB_D_PLATFORM \ 432 GEN6_FEATURES, \ 433 PLATFORM(INTEL_SANDYBRIDGE) 434 435 static const struct intel_device_info snb_d_gt1_info = { 436 SNB_D_PLATFORM, 437 .gt = 1, 438 }; 439 440 static const struct intel_device_info snb_d_gt2_info = { 441 SNB_D_PLATFORM, 442 .gt = 2, 443 }; 444 445 #define SNB_M_PLATFORM \ 446 GEN6_FEATURES, \ 447 PLATFORM(INTEL_SANDYBRIDGE), \ 448 .is_mobile = 1 449 450 451 static const struct intel_device_info snb_m_gt1_info = { 452 SNB_M_PLATFORM, 453 .gt = 1, 454 }; 455 456 static const struct intel_device_info snb_m_gt2_info = { 457 SNB_M_PLATFORM, 458 .gt = 2, 459 }; 460 461 #define GEN7_FEATURES \ 462 GEN(7), \ 463 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ 464 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \ 465 .display.has_hotplug = 1, \ 466 .display.fbc_mask = BIT(INTEL_FBC_A), \ 467 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ 468 .has_3d_pipeline = 1, \ 469 .has_coherent_ggtt = true, \ 470 .has_llc = 1, \ 471 .has_rc6 = 1, \ 472 .has_rc6p = 1, \ 473 .has_reset_engine = true, \ 474 .has_rps = true, \ 475 .dma_mask_size = 40, \ 476 .ppgtt_type = INTEL_PPGTT_ALIASING, \ 477 .ppgtt_size = 31, \ 478 IVB_PIPE_OFFSETS, \ 479 IVB_CURSOR_OFFSETS, \ 480 IVB_COLORS, \ 481 GEN_DEFAULT_PAGE_SIZES, \ 482 GEN_DEFAULT_REGIONS 483 484 #define IVB_D_PLATFORM \ 485 GEN7_FEATURES, \ 486 PLATFORM(INTEL_IVYBRIDGE), \ 487 .has_l3_dpf = 1 488 489 static const struct intel_device_info ivb_d_gt1_info = { 490 IVB_D_PLATFORM, 491 .gt = 1, 492 }; 493 494 static const struct intel_device_info ivb_d_gt2_info = { 495 IVB_D_PLATFORM, 496 .gt = 2, 497 }; 498 499 #define IVB_M_PLATFORM \ 500 GEN7_FEATURES, \ 501 PLATFORM(INTEL_IVYBRIDGE), \ 502 .is_mobile = 1, \ 503 .has_l3_dpf = 1 504 505 static const struct intel_device_info ivb_m_gt1_info = { 506 IVB_M_PLATFORM, 507 .gt = 1, 508 }; 509 510 static const struct intel_device_info ivb_m_gt2_info = { 511 IVB_M_PLATFORM, 512 .gt = 2, 513 }; 514 515 static const struct intel_device_info ivb_q_info = { 516 GEN7_FEATURES, 517 PLATFORM(INTEL_IVYBRIDGE), 518 .gt = 2, 519 .display.pipe_mask = 0, /* legal, last one wins */ 520 .display.cpu_transcoder_mask = 0, 521 .has_l3_dpf = 1, 522 }; 523 524 static const struct intel_device_info vlv_info = { 525 PLATFORM(INTEL_VALLEYVIEW), 526 GEN(7), 527 .is_lp = 1, 528 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), 529 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), 530 .has_runtime_pm = 1, 531 .has_rc6 = 1, 532 .has_reset_engine = true, 533 .has_rps = true, 534 .display.has_gmch = 1, 535 .display.has_hotplug = 1, 536 .dma_mask_size = 40, 537 .ppgtt_type = INTEL_PPGTT_ALIASING, 538 .ppgtt_size = 31, 539 .has_snoop = true, 540 .has_coherent_ggtt = false, 541 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), 542 .display.mmio_offset = VLV_DISPLAY_BASE, 543 I9XX_PIPE_OFFSETS, 544 I9XX_CURSOR_OFFSETS, 545 I965_COLORS, 546 GEN_DEFAULT_PAGE_SIZES, 547 GEN_DEFAULT_REGIONS, 548 }; 549 550 #define G75_FEATURES \ 551 GEN7_FEATURES, \ 552 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ 553 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 554 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \ 555 .display.has_ddi = 1, \ 556 .display.has_fpga_dbg = 1, \ 557 .display.has_dp_mst = 1, \ 558 .has_rc6p = 0 /* RC6p removed-by HSW */, \ 559 HSW_PIPE_OFFSETS, \ 560 .has_runtime_pm = 1 561 562 #define HSW_PLATFORM \ 563 G75_FEATURES, \ 564 PLATFORM(INTEL_HASWELL), \ 565 .has_l3_dpf = 1 566 567 static const struct intel_device_info hsw_gt1_info = { 568 HSW_PLATFORM, 569 .gt = 1, 570 }; 571 572 static const struct intel_device_info hsw_gt2_info = { 573 HSW_PLATFORM, 574 .gt = 2, 575 }; 576 577 static const struct intel_device_info hsw_gt3_info = { 578 HSW_PLATFORM, 579 .gt = 3, 580 }; 581 582 #define GEN8_FEATURES \ 583 G75_FEATURES, \ 584 GEN(8), \ 585 .has_logical_ring_contexts = 1, \ 586 .dma_mask_size = 39, \ 587 .ppgtt_type = INTEL_PPGTT_FULL, \ 588 .ppgtt_size = 48, \ 589 .has_64bit_reloc = 1 590 591 #define BDW_PLATFORM \ 592 GEN8_FEATURES, \ 593 PLATFORM(INTEL_BROADWELL) 594 595 static const struct intel_device_info bdw_gt1_info = { 596 BDW_PLATFORM, 597 .gt = 1, 598 }; 599 600 static const struct intel_device_info bdw_gt2_info = { 601 BDW_PLATFORM, 602 .gt = 2, 603 }; 604 605 static const struct intel_device_info bdw_rsvd_info = { 606 BDW_PLATFORM, 607 .gt = 3, 608 /* According to the device ID those devices are GT3, they were 609 * previously treated as not GT3, keep it like that. 610 */ 611 }; 612 613 static const struct intel_device_info bdw_gt3_info = { 614 BDW_PLATFORM, 615 .gt = 3, 616 .platform_engine_mask = 617 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 618 }; 619 620 static const struct intel_device_info chv_info = { 621 PLATFORM(INTEL_CHERRYVIEW), 622 GEN(8), 623 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 624 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), 625 .display.has_hotplug = 1, 626 .is_lp = 1, 627 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), 628 .has_64bit_reloc = 1, 629 .has_runtime_pm = 1, 630 .has_rc6 = 1, 631 .has_rps = true, 632 .has_logical_ring_contexts = 1, 633 .display.has_gmch = 1, 634 .dma_mask_size = 39, 635 .ppgtt_type = INTEL_PPGTT_FULL, 636 .ppgtt_size = 32, 637 .has_reset_engine = 1, 638 .has_snoop = true, 639 .has_coherent_ggtt = false, 640 .display.mmio_offset = VLV_DISPLAY_BASE, 641 CHV_PIPE_OFFSETS, 642 CHV_CURSOR_OFFSETS, 643 CHV_COLORS, 644 GEN_DEFAULT_PAGE_SIZES, 645 GEN_DEFAULT_REGIONS, 646 }; 647 648 #define GEN9_DEFAULT_PAGE_SIZES \ 649 .page_sizes = I915_GTT_PAGE_SIZE_4K | \ 650 I915_GTT_PAGE_SIZE_64K 651 652 #define GEN9_FEATURES \ 653 GEN8_FEATURES, \ 654 GEN(9), \ 655 GEN9_DEFAULT_PAGE_SIZES, \ 656 .display.has_dmc = 1, \ 657 .has_gt_uc = 1, \ 658 .display.has_hdcp = 1, \ 659 .display.has_ipc = 1, \ 660 .display.has_psr = 1, \ 661 .display.has_psr_hw_tracking = 1, \ 662 .display.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \ 663 .display.dbuf.slice_mask = BIT(DBUF_S1) 664 665 #define SKL_PLATFORM \ 666 GEN9_FEATURES, \ 667 PLATFORM(INTEL_SKYLAKE) 668 669 static const struct intel_device_info skl_gt1_info = { 670 SKL_PLATFORM, 671 .gt = 1, 672 }; 673 674 static const struct intel_device_info skl_gt2_info = { 675 SKL_PLATFORM, 676 .gt = 2, 677 }; 678 679 #define SKL_GT3_PLUS_PLATFORM \ 680 SKL_PLATFORM, \ 681 .platform_engine_mask = \ 682 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1) 683 684 685 static const struct intel_device_info skl_gt3_info = { 686 SKL_GT3_PLUS_PLATFORM, 687 .gt = 3, 688 }; 689 690 static const struct intel_device_info skl_gt4_info = { 691 SKL_GT3_PLUS_PLATFORM, 692 .gt = 4, 693 }; 694 695 #define GEN9_LP_FEATURES \ 696 GEN(9), \ 697 .is_lp = 1, \ 698 .display.dbuf.slice_mask = BIT(DBUF_S1), \ 699 .display.has_hotplug = 1, \ 700 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ 701 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ 702 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 703 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ 704 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \ 705 .has_3d_pipeline = 1, \ 706 .has_64bit_reloc = 1, \ 707 .display.has_ddi = 1, \ 708 .display.has_fpga_dbg = 1, \ 709 .display.fbc_mask = BIT(INTEL_FBC_A), \ 710 .display.has_hdcp = 1, \ 711 .display.has_psr = 1, \ 712 .display.has_psr_hw_tracking = 1, \ 713 .has_runtime_pm = 1, \ 714 .display.has_dmc = 1, \ 715 .has_rc6 = 1, \ 716 .has_rps = true, \ 717 .display.has_dp_mst = 1, \ 718 .has_logical_ring_contexts = 1, \ 719 .has_gt_uc = 1, \ 720 .dma_mask_size = 39, \ 721 .ppgtt_type = INTEL_PPGTT_FULL, \ 722 .ppgtt_size = 48, \ 723 .has_reset_engine = 1, \ 724 .has_snoop = true, \ 725 .has_coherent_ggtt = false, \ 726 .display.has_ipc = 1, \ 727 HSW_PIPE_OFFSETS, \ 728 IVB_CURSOR_OFFSETS, \ 729 IVB_COLORS, \ 730 GEN9_DEFAULT_PAGE_SIZES, \ 731 GEN_DEFAULT_REGIONS 732 733 static const struct intel_device_info bxt_info = { 734 GEN9_LP_FEATURES, 735 PLATFORM(INTEL_BROXTON), 736 .display.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */ 737 }; 738 739 static const struct intel_device_info glk_info = { 740 GEN9_LP_FEATURES, 741 PLATFORM(INTEL_GEMINILAKE), 742 .display.ver = 10, 743 .display.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ 744 GLK_COLORS, 745 }; 746 747 #define KBL_PLATFORM \ 748 GEN9_FEATURES, \ 749 PLATFORM(INTEL_KABYLAKE) 750 751 static const struct intel_device_info kbl_gt1_info = { 752 KBL_PLATFORM, 753 .gt = 1, 754 }; 755 756 static const struct intel_device_info kbl_gt2_info = { 757 KBL_PLATFORM, 758 .gt = 2, 759 }; 760 761 static const struct intel_device_info kbl_gt3_info = { 762 KBL_PLATFORM, 763 .gt = 3, 764 .platform_engine_mask = 765 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 766 }; 767 768 #define CFL_PLATFORM \ 769 GEN9_FEATURES, \ 770 PLATFORM(INTEL_COFFEELAKE) 771 772 static const struct intel_device_info cfl_gt1_info = { 773 CFL_PLATFORM, 774 .gt = 1, 775 }; 776 777 static const struct intel_device_info cfl_gt2_info = { 778 CFL_PLATFORM, 779 .gt = 2, 780 }; 781 782 static const struct intel_device_info cfl_gt3_info = { 783 CFL_PLATFORM, 784 .gt = 3, 785 .platform_engine_mask = 786 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 787 }; 788 789 #define CML_PLATFORM \ 790 GEN9_FEATURES, \ 791 PLATFORM(INTEL_COMETLAKE) 792 793 static const struct intel_device_info cml_gt1_info = { 794 CML_PLATFORM, 795 .gt = 1, 796 }; 797 798 static const struct intel_device_info cml_gt2_info = { 799 CML_PLATFORM, 800 .gt = 2, 801 }; 802 803 #define GEN11_DEFAULT_PAGE_SIZES \ 804 .page_sizes = I915_GTT_PAGE_SIZE_4K | \ 805 I915_GTT_PAGE_SIZE_64K | \ 806 I915_GTT_PAGE_SIZE_2M 807 808 #define GEN11_FEATURES \ 809 GEN9_FEATURES, \ 810 GEN11_DEFAULT_PAGE_SIZES, \ 811 .display.abox_mask = BIT(0), \ 812 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 813 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ 814 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ 815 .display.pipe_offsets = { \ 816 [TRANSCODER_A] = PIPE_A_OFFSET, \ 817 [TRANSCODER_B] = PIPE_B_OFFSET, \ 818 [TRANSCODER_C] = PIPE_C_OFFSET, \ 819 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 820 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 821 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 822 }, \ 823 .display.trans_offsets = { \ 824 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 825 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 826 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 827 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 828 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 829 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 830 }, \ 831 GEN(11), \ 832 ICL_COLORS, \ 833 .display.dbuf.size = 2048, \ 834 .display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \ 835 .display.has_dsc = 1, \ 836 .has_coherent_ggtt = false, \ 837 .has_logical_ring_elsq = 1 838 839 static const struct intel_device_info icl_info = { 840 GEN11_FEATURES, 841 PLATFORM(INTEL_ICELAKE), 842 .platform_engine_mask = 843 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 844 }; 845 846 static const struct intel_device_info ehl_info = { 847 GEN11_FEATURES, 848 PLATFORM(INTEL_ELKHARTLAKE), 849 .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0), 850 .ppgtt_size = 36, 851 }; 852 853 static const struct intel_device_info jsl_info = { 854 GEN11_FEATURES, 855 PLATFORM(INTEL_JASPERLAKE), 856 .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0), 857 .ppgtt_size = 36, 858 }; 859 860 #define GEN12_FEATURES \ 861 GEN11_FEATURES, \ 862 GEN(12), \ 863 .display.abox_mask = GENMASK(2, 1), \ 864 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ 865 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 866 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \ 867 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ 868 .display.pipe_offsets = { \ 869 [TRANSCODER_A] = PIPE_A_OFFSET, \ 870 [TRANSCODER_B] = PIPE_B_OFFSET, \ 871 [TRANSCODER_C] = PIPE_C_OFFSET, \ 872 [TRANSCODER_D] = PIPE_D_OFFSET, \ 873 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 874 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 875 }, \ 876 .display.trans_offsets = { \ 877 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 878 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 879 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 880 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ 881 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 882 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 883 }, \ 884 TGL_CURSOR_OFFSETS, \ 885 .has_global_mocs = 1, \ 886 .has_pxp = 1, \ 887 .display.has_dsb = 0 /* FIXME: LUT load is broken with DSB */ 888 889 static const struct intel_device_info tgl_info = { 890 GEN12_FEATURES, 891 PLATFORM(INTEL_TIGERLAKE), 892 .display.has_modular_fia = 1, 893 .platform_engine_mask = 894 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 895 }; 896 897 static const struct intel_device_info rkl_info = { 898 GEN12_FEATURES, 899 PLATFORM(INTEL_ROCKETLAKE), 900 .display.abox_mask = BIT(0), 901 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 902 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 903 BIT(TRANSCODER_C), 904 .display.has_hti = 1, 905 .display.has_psr_hw_tracking = 0, 906 .platform_engine_mask = 907 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0), 908 }; 909 910 #define DGFX_FEATURES \ 911 .memory_regions = REGION_SMEM | REGION_LMEM | REGION_STOLEN_LMEM, \ 912 .has_llc = 0, \ 913 .has_pxp = 0, \ 914 .has_snoop = 1, \ 915 .is_dgfx = 1, \ 916 .has_heci_gscfi = 1 917 918 static const struct intel_device_info dg1_info = { 919 GEN12_FEATURES, 920 DGFX_FEATURES, 921 .graphics.rel = 10, 922 PLATFORM(INTEL_DG1), 923 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 924 .require_force_probe = 1, 925 .platform_engine_mask = 926 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | 927 BIT(VCS0) | BIT(VCS2), 928 /* Wa_16011227922 */ 929 .ppgtt_size = 47, 930 }; 931 932 static const struct intel_device_info adl_s_info = { 933 GEN12_FEATURES, 934 PLATFORM(INTEL_ALDERLAKE_S), 935 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 936 .display.has_hti = 1, 937 .display.has_psr_hw_tracking = 0, 938 .platform_engine_mask = 939 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 940 .dma_mask_size = 39, 941 }; 942 943 #define XE_LPD_FEATURES \ 944 .display.abox_mask = GENMASK(1, 0), \ 945 .display.color = { \ 946 .degamma_lut_size = 128, .gamma_lut_size = 1024, \ 947 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 948 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 949 }, \ 950 .display.dbuf.size = 4096, \ 951 .display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \ 952 BIT(DBUF_S4), \ 953 .display.has_ddi = 1, \ 954 .display.has_dmc = 1, \ 955 .display.has_dp_mst = 1, \ 956 .display.has_dsb = 1, \ 957 .display.has_dsc = 1, \ 958 .display.fbc_mask = BIT(INTEL_FBC_A), \ 959 .display.has_fpga_dbg = 1, \ 960 .display.has_hdcp = 1, \ 961 .display.has_hotplug = 1, \ 962 .display.has_ipc = 1, \ 963 .display.has_psr = 1, \ 964 .display.ver = 13, \ 965 .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ 966 .display.pipe_offsets = { \ 967 [TRANSCODER_A] = PIPE_A_OFFSET, \ 968 [TRANSCODER_B] = PIPE_B_OFFSET, \ 969 [TRANSCODER_C] = PIPE_C_OFFSET, \ 970 [TRANSCODER_D] = PIPE_D_OFFSET, \ 971 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 972 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 973 }, \ 974 .display.trans_offsets = { \ 975 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 976 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 977 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 978 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ 979 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 980 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 981 }, \ 982 TGL_CURSOR_OFFSETS 983 984 static const struct intel_device_info adl_p_info = { 985 GEN12_FEATURES, 986 XE_LPD_FEATURES, 987 PLATFORM(INTEL_ALDERLAKE_P), 988 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 989 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | 990 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), 991 .display.has_cdclk_crawl = 1, 992 .display.has_modular_fia = 1, 993 .display.has_psr_hw_tracking = 0, 994 .platform_engine_mask = 995 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 996 .ppgtt_size = 48, 997 .dma_mask_size = 39, 998 }; 999 1000 #undef GEN 1001 1002 #define XE_HP_PAGE_SIZES \ 1003 .page_sizes = I915_GTT_PAGE_SIZE_4K | \ 1004 I915_GTT_PAGE_SIZE_64K | \ 1005 I915_GTT_PAGE_SIZE_2M 1006 1007 #define XE_HP_FEATURES \ 1008 .graphics.ver = 12, \ 1009 .graphics.rel = 50, \ 1010 XE_HP_PAGE_SIZES, \ 1011 .dma_mask_size = 46, \ 1012 .has_3d_pipeline = 1, \ 1013 .has_64bit_reloc = 1, \ 1014 .has_flat_ccs = 1, \ 1015 .has_global_mocs = 1, \ 1016 .has_gt_uc = 1, \ 1017 .has_llc = 1, \ 1018 .has_logical_ring_contexts = 1, \ 1019 .has_logical_ring_elsq = 1, \ 1020 .has_mslice_steering = 1, \ 1021 .has_rc6 = 1, \ 1022 .has_reset_engine = 1, \ 1023 .has_rps = 1, \ 1024 .has_runtime_pm = 1, \ 1025 .ppgtt_size = 48, \ 1026 .ppgtt_type = INTEL_PPGTT_FULL 1027 1028 #define XE_HPM_FEATURES \ 1029 .media.ver = 12, \ 1030 .media.rel = 50 1031 1032 __maybe_unused 1033 static const struct intel_device_info xehpsdv_info = { 1034 XE_HP_FEATURES, 1035 XE_HPM_FEATURES, 1036 DGFX_FEATURES, 1037 PLATFORM(INTEL_XEHPSDV), 1038 .display = { }, 1039 .has_64k_pages = 1, 1040 .needs_compact_pt = 1, 1041 .has_media_ratio_mode = 1, 1042 .platform_engine_mask = 1043 BIT(RCS0) | BIT(BCS0) | 1044 BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) | 1045 BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) | 1046 BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7) | 1047 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3), 1048 .require_force_probe = 1, 1049 }; 1050 1051 #define DG2_FEATURES \ 1052 XE_HP_FEATURES, \ 1053 XE_HPM_FEATURES, \ 1054 DGFX_FEATURES, \ 1055 .graphics.rel = 55, \ 1056 .media.rel = 55, \ 1057 PLATFORM(INTEL_DG2), \ 1058 .has_4tile = 1, \ 1059 .has_64k_pages = 1, \ 1060 .has_guc_deprivilege = 1, \ 1061 .has_heci_pxp = 1, \ 1062 .needs_compact_pt = 1, \ 1063 .has_media_ratio_mode = 1, \ 1064 .platform_engine_mask = \ 1065 BIT(RCS0) | BIT(BCS0) | \ 1066 BIT(VECS0) | BIT(VECS1) | \ 1067 BIT(VCS0) | BIT(VCS2) | \ 1068 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3) 1069 1070 static const struct intel_device_info dg2_info = { 1071 DG2_FEATURES, 1072 XE_LPD_FEATURES, 1073 .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 1074 BIT(TRANSCODER_C) | BIT(TRANSCODER_D), 1075 .require_force_probe = 1, 1076 }; 1077 1078 static const struct intel_device_info ats_m_info = { 1079 DG2_FEATURES, 1080 .display = { 0 }, 1081 .require_force_probe = 1, 1082 }; 1083 1084 #define XE_HPC_FEATURES \ 1085 XE_HP_FEATURES, \ 1086 .dma_mask_size = 52, \ 1087 .has_3d_pipeline = 0, \ 1088 .has_guc_deprivilege = 1, \ 1089 .has_l3_ccs_read = 1, \ 1090 .has_mslice_steering = 0, \ 1091 .has_one_eu_per_fuse_bit = 1 1092 1093 __maybe_unused 1094 static const struct intel_device_info pvc_info = { 1095 XE_HPC_FEATURES, 1096 XE_HPM_FEATURES, 1097 DGFX_FEATURES, 1098 .graphics.rel = 60, 1099 .media.rel = 60, 1100 PLATFORM(INTEL_PONTEVECCHIO), 1101 .display = { 0 }, 1102 .has_flat_ccs = 0, 1103 .platform_engine_mask = 1104 BIT(BCS0) | 1105 BIT(VCS0) | 1106 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3), 1107 .require_force_probe = 1, 1108 }; 1109 1110 #define XE_LPDP_FEATURES \ 1111 XE_LPD_FEATURES, \ 1112 .display.ver = 14, \ 1113 .display.has_cdclk_crawl = 1 1114 1115 __maybe_unused 1116 static const struct intel_device_info mtl_info = { 1117 XE_HP_FEATURES, 1118 XE_LPDP_FEATURES, 1119 /* 1120 * Real graphics IP version will be obtained from hardware GMD_ID 1121 * register. Value provided here is just for sanity checking. 1122 */ 1123 .graphics.ver = 12, 1124 .graphics.rel = 70, 1125 .media.ver = 13, 1126 PLATFORM(INTEL_METEORLAKE), 1127 .display.has_modular_fia = 1, 1128 .has_flat_ccs = 0, 1129 .has_snoop = 1, 1130 .memory_regions = REGION_SMEM | REGION_STOLEN_LMEM, 1131 .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0), 1132 .require_force_probe = 1, 1133 }; 1134 1135 #undef PLATFORM 1136 1137 /* 1138 * Make sure any device matches here are from most specific to most 1139 * general. For example, since the Quanta match is based on the subsystem 1140 * and subvendor IDs, we need it to come before the more general IVB 1141 * PCI ID matches, otherwise we'll use the wrong info struct above. 1142 */ 1143 static const struct pci_device_id pciidlist[] = { 1144 INTEL_I830_IDS(&i830_info), 1145 INTEL_I845G_IDS(&i845g_info), 1146 INTEL_I85X_IDS(&i85x_info), 1147 INTEL_I865G_IDS(&i865g_info), 1148 INTEL_I915G_IDS(&i915g_info), 1149 INTEL_I915GM_IDS(&i915gm_info), 1150 INTEL_I945G_IDS(&i945g_info), 1151 INTEL_I945GM_IDS(&i945gm_info), 1152 INTEL_I965G_IDS(&i965g_info), 1153 INTEL_G33_IDS(&g33_info), 1154 INTEL_I965GM_IDS(&i965gm_info), 1155 INTEL_GM45_IDS(&gm45_info), 1156 INTEL_G45_IDS(&g45_info), 1157 INTEL_PINEVIEW_G_IDS(&pnv_g_info), 1158 INTEL_PINEVIEW_M_IDS(&pnv_m_info), 1159 INTEL_IRONLAKE_D_IDS(&ilk_d_info), 1160 INTEL_IRONLAKE_M_IDS(&ilk_m_info), 1161 INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info), 1162 INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info), 1163 INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info), 1164 INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info), 1165 INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */ 1166 INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info), 1167 INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info), 1168 INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info), 1169 INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info), 1170 INTEL_HSW_GT1_IDS(&hsw_gt1_info), 1171 INTEL_HSW_GT2_IDS(&hsw_gt2_info), 1172 INTEL_HSW_GT3_IDS(&hsw_gt3_info), 1173 INTEL_VLV_IDS(&vlv_info), 1174 INTEL_BDW_GT1_IDS(&bdw_gt1_info), 1175 INTEL_BDW_GT2_IDS(&bdw_gt2_info), 1176 INTEL_BDW_GT3_IDS(&bdw_gt3_info), 1177 INTEL_BDW_RSVD_IDS(&bdw_rsvd_info), 1178 INTEL_CHV_IDS(&chv_info), 1179 INTEL_SKL_GT1_IDS(&skl_gt1_info), 1180 INTEL_SKL_GT2_IDS(&skl_gt2_info), 1181 INTEL_SKL_GT3_IDS(&skl_gt3_info), 1182 INTEL_SKL_GT4_IDS(&skl_gt4_info), 1183 INTEL_BXT_IDS(&bxt_info), 1184 INTEL_GLK_IDS(&glk_info), 1185 INTEL_KBL_GT1_IDS(&kbl_gt1_info), 1186 INTEL_KBL_GT2_IDS(&kbl_gt2_info), 1187 INTEL_KBL_GT3_IDS(&kbl_gt3_info), 1188 INTEL_KBL_GT4_IDS(&kbl_gt3_info), 1189 INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info), 1190 INTEL_CFL_S_GT1_IDS(&cfl_gt1_info), 1191 INTEL_CFL_S_GT2_IDS(&cfl_gt2_info), 1192 INTEL_CFL_H_GT1_IDS(&cfl_gt1_info), 1193 INTEL_CFL_H_GT2_IDS(&cfl_gt2_info), 1194 INTEL_CFL_U_GT2_IDS(&cfl_gt2_info), 1195 INTEL_CFL_U_GT3_IDS(&cfl_gt3_info), 1196 INTEL_WHL_U_GT1_IDS(&cfl_gt1_info), 1197 INTEL_WHL_U_GT2_IDS(&cfl_gt2_info), 1198 INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info), 1199 INTEL_WHL_U_GT3_IDS(&cfl_gt3_info), 1200 INTEL_CML_GT1_IDS(&cml_gt1_info), 1201 INTEL_CML_GT2_IDS(&cml_gt2_info), 1202 INTEL_CML_U_GT1_IDS(&cml_gt1_info), 1203 INTEL_CML_U_GT2_IDS(&cml_gt2_info), 1204 INTEL_ICL_11_IDS(&icl_info), 1205 INTEL_EHL_IDS(&ehl_info), 1206 INTEL_JSL_IDS(&jsl_info), 1207 INTEL_TGL_12_IDS(&tgl_info), 1208 INTEL_RKL_IDS(&rkl_info), 1209 INTEL_ADLS_IDS(&adl_s_info), 1210 INTEL_ADLP_IDS(&adl_p_info), 1211 INTEL_ADLN_IDS(&adl_p_info), 1212 INTEL_DG1_IDS(&dg1_info), 1213 INTEL_RPLS_IDS(&adl_s_info), 1214 INTEL_RPLP_IDS(&adl_p_info), 1215 INTEL_DG2_IDS(&dg2_info), 1216 INTEL_ATS_M_IDS(&ats_m_info), 1217 INTEL_MTL_IDS(&mtl_info), 1218 {0, 0, 0} 1219 }; 1220 MODULE_DEVICE_TABLE(pci, pciidlist); 1221 1222 static void i915_pci_remove(struct pci_dev *pdev) 1223 { 1224 struct drm_i915_private *i915; 1225 1226 i915 = pci_get_drvdata(pdev); 1227 if (!i915) /* driver load aborted, nothing to cleanup */ 1228 return; 1229 1230 i915_driver_remove(i915); 1231 pci_set_drvdata(pdev, NULL); 1232 } 1233 1234 /* is device_id present in comma separated list of ids */ 1235 static bool force_probe(u16 device_id, const char *devices) 1236 { 1237 char *s, *p, *tok; 1238 bool ret; 1239 1240 if (!devices || !*devices) 1241 return false; 1242 1243 /* match everything */ 1244 if (strcmp(devices, "*") == 0) 1245 return true; 1246 1247 s = kstrdup(devices, GFP_KERNEL); 1248 if (!s) 1249 return false; 1250 1251 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) { 1252 u16 val; 1253 1254 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) { 1255 ret = true; 1256 break; 1257 } 1258 } 1259 1260 kfree(s); 1261 1262 return ret; 1263 } 1264 1265 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1266 { 1267 struct intel_device_info *intel_info = 1268 (struct intel_device_info *) ent->driver_data; 1269 int err; 1270 1271 if (intel_info->require_force_probe && 1272 !force_probe(pdev->device, i915_modparams.force_probe)) { 1273 dev_info(&pdev->dev, 1274 "Your graphics device %04x is not properly supported by the driver in this\n" 1275 "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n" 1276 "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n" 1277 "or (recommended) check for kernel updates.\n", 1278 pdev->device, pdev->device, pdev->device); 1279 return -ENODEV; 1280 } 1281 1282 /* Only bind to function 0 of the device. Early generations 1283 * used function 1 as a placeholder for multi-head. This causes 1284 * us confusion instead, especially on the systems where both 1285 * functions have the same PCI-ID! 1286 */ 1287 if (PCI_FUNC(pdev->devfn)) 1288 return -ENODEV; 1289 1290 /* Detect if we need to wait for other drivers early on */ 1291 if (intel_modeset_probe_defer(pdev)) 1292 return -EPROBE_DEFER; 1293 1294 err = i915_driver_probe(pdev, ent); 1295 if (err) 1296 return err; 1297 1298 if (i915_inject_probe_failure(pci_get_drvdata(pdev))) { 1299 i915_pci_remove(pdev); 1300 return -ENODEV; 1301 } 1302 1303 err = i915_live_selftests(pdev); 1304 if (err) { 1305 i915_pci_remove(pdev); 1306 return err > 0 ? -ENOTTY : err; 1307 } 1308 1309 err = i915_perf_selftests(pdev); 1310 if (err) { 1311 i915_pci_remove(pdev); 1312 return err > 0 ? -ENOTTY : err; 1313 } 1314 1315 return 0; 1316 } 1317 1318 static void i915_pci_shutdown(struct pci_dev *pdev) 1319 { 1320 struct drm_i915_private *i915 = pci_get_drvdata(pdev); 1321 1322 i915_driver_shutdown(i915); 1323 } 1324 1325 static struct pci_driver i915_pci_driver = { 1326 .name = DRIVER_NAME, 1327 .id_table = pciidlist, 1328 .probe = i915_pci_probe, 1329 .remove = i915_pci_remove, 1330 .shutdown = i915_pci_shutdown, 1331 .driver.pm = &i915_pm_ops, 1332 }; 1333 1334 int i915_pci_register_driver(void) 1335 { 1336 return pci_register_driver(&i915_pci_driver); 1337 } 1338 1339 void i915_pci_unregister_driver(void) 1340 { 1341 pci_unregister_driver(&i915_pci_driver); 1342 } 1343