1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <drm/drm_color_mgmt.h> 26 #include <drm/drm_drv.h> 27 #include <drm/i915_pciids.h> 28 29 #include "display/intel_display.h" 30 #include "gt/intel_gt_regs.h" 31 #include "gt/intel_sa_media.h" 32 33 #include "i915_driver.h" 34 #include "i915_drv.h" 35 #include "i915_pci.h" 36 #include "i915_reg.h" 37 #include "intel_pci_config.h" 38 39 #define PLATFORM(x) .platform = (x) 40 #define GEN(x) \ 41 .__runtime.graphics.ip.ver = (x), \ 42 .__runtime.media.ip.ver = (x), \ 43 .__runtime.display.ip.ver = (x) 44 45 #define NO_DISPLAY .__runtime.pipe_mask = 0 46 47 #define I845_PIPE_OFFSETS \ 48 .display.pipe_offsets = { \ 49 [TRANSCODER_A] = PIPE_A_OFFSET, \ 50 }, \ 51 .display.trans_offsets = { \ 52 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 53 } 54 55 #define I9XX_PIPE_OFFSETS \ 56 .display.pipe_offsets = { \ 57 [TRANSCODER_A] = PIPE_A_OFFSET, \ 58 [TRANSCODER_B] = PIPE_B_OFFSET, \ 59 }, \ 60 .display.trans_offsets = { \ 61 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 62 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 63 } 64 65 #define IVB_PIPE_OFFSETS \ 66 .display.pipe_offsets = { \ 67 [TRANSCODER_A] = PIPE_A_OFFSET, \ 68 [TRANSCODER_B] = PIPE_B_OFFSET, \ 69 [TRANSCODER_C] = PIPE_C_OFFSET, \ 70 }, \ 71 .display.trans_offsets = { \ 72 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 73 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 74 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 75 } 76 77 #define HSW_PIPE_OFFSETS \ 78 .display.pipe_offsets = { \ 79 [TRANSCODER_A] = PIPE_A_OFFSET, \ 80 [TRANSCODER_B] = PIPE_B_OFFSET, \ 81 [TRANSCODER_C] = PIPE_C_OFFSET, \ 82 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 83 }, \ 84 .display.trans_offsets = { \ 85 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 86 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 87 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 88 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 89 } 90 91 #define CHV_PIPE_OFFSETS \ 92 .display.pipe_offsets = { \ 93 [TRANSCODER_A] = PIPE_A_OFFSET, \ 94 [TRANSCODER_B] = PIPE_B_OFFSET, \ 95 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \ 96 }, \ 97 .display.trans_offsets = { \ 98 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 99 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 100 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \ 101 } 102 103 #define I845_CURSOR_OFFSETS \ 104 .display.cursor_offsets = { \ 105 [PIPE_A] = CURSOR_A_OFFSET, \ 106 } 107 108 #define I9XX_CURSOR_OFFSETS \ 109 .display.cursor_offsets = { \ 110 [PIPE_A] = CURSOR_A_OFFSET, \ 111 [PIPE_B] = CURSOR_B_OFFSET, \ 112 } 113 114 #define CHV_CURSOR_OFFSETS \ 115 .display.cursor_offsets = { \ 116 [PIPE_A] = CURSOR_A_OFFSET, \ 117 [PIPE_B] = CURSOR_B_OFFSET, \ 118 [PIPE_C] = CHV_CURSOR_C_OFFSET, \ 119 } 120 121 #define IVB_CURSOR_OFFSETS \ 122 .display.cursor_offsets = { \ 123 [PIPE_A] = CURSOR_A_OFFSET, \ 124 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 125 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 126 } 127 128 #define TGL_CURSOR_OFFSETS \ 129 .display.cursor_offsets = { \ 130 [PIPE_A] = CURSOR_A_OFFSET, \ 131 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 132 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 133 [PIPE_D] = TGL_CURSOR_D_OFFSET, \ 134 } 135 136 #define I845_COLORS \ 137 .display.color = { .gamma_lut_size = 256 } 138 #define I9XX_COLORS \ 139 .display.color = { .gamma_lut_size = 129, \ 140 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 141 } 142 #define ILK_COLORS \ 143 .display.color = { .gamma_lut_size = 1024 } 144 #define IVB_COLORS \ 145 .display.color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 } 146 #define CHV_COLORS \ 147 .display.color = { \ 148 .degamma_lut_size = 65, .gamma_lut_size = 257, \ 149 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 150 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 151 } 152 #define GLK_COLORS \ 153 .display.color = { \ 154 .degamma_lut_size = 33, .gamma_lut_size = 1024, \ 155 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 156 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 157 } 158 #define ICL_COLORS \ 159 .display.color = { \ 160 .degamma_lut_size = 33, .gamma_lut_size = 262145, \ 161 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 162 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 163 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 164 } 165 166 /* Keep in gen based order, and chronological order within a gen */ 167 168 #define GEN_DEFAULT_PAGE_SIZES \ 169 .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K 170 171 #define GEN_DEFAULT_REGIONS \ 172 .__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_SMEM 173 174 #define I830_FEATURES \ 175 GEN(2), \ 176 .is_mobile = 1, \ 177 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 178 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 179 .display.has_overlay = 1, \ 180 .display.cursor_needs_physical = 1, \ 181 .display.overlay_needs_physical = 1, \ 182 .display.has_gmch = 1, \ 183 .gpu_reset_clobbers_display = true, \ 184 .has_3d_pipeline = 1, \ 185 .hws_needs_physical = 1, \ 186 .unfenced_needs_alignment = 1, \ 187 .__runtime.platform_engine_mask = BIT(RCS0), \ 188 .has_snoop = true, \ 189 .has_coherent_ggtt = false, \ 190 .dma_mask_size = 32, \ 191 I9XX_PIPE_OFFSETS, \ 192 I9XX_CURSOR_OFFSETS, \ 193 I9XX_COLORS, \ 194 GEN_DEFAULT_PAGE_SIZES, \ 195 GEN_DEFAULT_REGIONS 196 197 #define I845_FEATURES \ 198 GEN(2), \ 199 .__runtime.pipe_mask = BIT(PIPE_A), \ 200 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A), \ 201 .display.has_overlay = 1, \ 202 .display.overlay_needs_physical = 1, \ 203 .display.has_gmch = 1, \ 204 .has_3d_pipeline = 1, \ 205 .gpu_reset_clobbers_display = true, \ 206 .hws_needs_physical = 1, \ 207 .unfenced_needs_alignment = 1, \ 208 .__runtime.platform_engine_mask = BIT(RCS0), \ 209 .has_snoop = true, \ 210 .has_coherent_ggtt = false, \ 211 .dma_mask_size = 32, \ 212 I845_PIPE_OFFSETS, \ 213 I845_CURSOR_OFFSETS, \ 214 I845_COLORS, \ 215 GEN_DEFAULT_PAGE_SIZES, \ 216 GEN_DEFAULT_REGIONS 217 218 static const struct intel_device_info i830_info = { 219 I830_FEATURES, 220 PLATFORM(INTEL_I830), 221 }; 222 223 static const struct intel_device_info i845g_info = { 224 I845_FEATURES, 225 PLATFORM(INTEL_I845G), 226 }; 227 228 static const struct intel_device_info i85x_info = { 229 I830_FEATURES, 230 PLATFORM(INTEL_I85X), 231 .__runtime.fbc_mask = BIT(INTEL_FBC_A), 232 }; 233 234 static const struct intel_device_info i865g_info = { 235 I845_FEATURES, 236 PLATFORM(INTEL_I865G), 237 .__runtime.fbc_mask = BIT(INTEL_FBC_A), 238 }; 239 240 #define GEN3_FEATURES \ 241 GEN(3), \ 242 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 243 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 244 .display.has_gmch = 1, \ 245 .gpu_reset_clobbers_display = true, \ 246 .__runtime.platform_engine_mask = BIT(RCS0), \ 247 .has_3d_pipeline = 1, \ 248 .has_snoop = true, \ 249 .has_coherent_ggtt = true, \ 250 .dma_mask_size = 32, \ 251 I9XX_PIPE_OFFSETS, \ 252 I9XX_CURSOR_OFFSETS, \ 253 I9XX_COLORS, \ 254 GEN_DEFAULT_PAGE_SIZES, \ 255 GEN_DEFAULT_REGIONS 256 257 static const struct intel_device_info i915g_info = { 258 GEN3_FEATURES, 259 PLATFORM(INTEL_I915G), 260 .has_coherent_ggtt = false, 261 .display.cursor_needs_physical = 1, 262 .display.has_overlay = 1, 263 .display.overlay_needs_physical = 1, 264 .hws_needs_physical = 1, 265 .unfenced_needs_alignment = 1, 266 }; 267 268 static const struct intel_device_info i915gm_info = { 269 GEN3_FEATURES, 270 PLATFORM(INTEL_I915GM), 271 .is_mobile = 1, 272 .display.cursor_needs_physical = 1, 273 .display.has_overlay = 1, 274 .display.overlay_needs_physical = 1, 275 .display.supports_tv = 1, 276 .__runtime.fbc_mask = BIT(INTEL_FBC_A), 277 .hws_needs_physical = 1, 278 .unfenced_needs_alignment = 1, 279 }; 280 281 static const struct intel_device_info i945g_info = { 282 GEN3_FEATURES, 283 PLATFORM(INTEL_I945G), 284 .display.has_hotplug = 1, 285 .display.cursor_needs_physical = 1, 286 .display.has_overlay = 1, 287 .display.overlay_needs_physical = 1, 288 .hws_needs_physical = 1, 289 .unfenced_needs_alignment = 1, 290 }; 291 292 static const struct intel_device_info i945gm_info = { 293 GEN3_FEATURES, 294 PLATFORM(INTEL_I945GM), 295 .is_mobile = 1, 296 .display.has_hotplug = 1, 297 .display.cursor_needs_physical = 1, 298 .display.has_overlay = 1, 299 .display.overlay_needs_physical = 1, 300 .display.supports_tv = 1, 301 .__runtime.fbc_mask = BIT(INTEL_FBC_A), 302 .hws_needs_physical = 1, 303 .unfenced_needs_alignment = 1, 304 }; 305 306 static const struct intel_device_info g33_info = { 307 GEN3_FEATURES, 308 PLATFORM(INTEL_G33), 309 .display.has_hotplug = 1, 310 .display.has_overlay = 1, 311 .dma_mask_size = 36, 312 }; 313 314 static const struct intel_device_info pnv_g_info = { 315 GEN3_FEATURES, 316 PLATFORM(INTEL_PINEVIEW), 317 .display.has_hotplug = 1, 318 .display.has_overlay = 1, 319 .dma_mask_size = 36, 320 }; 321 322 static const struct intel_device_info pnv_m_info = { 323 GEN3_FEATURES, 324 PLATFORM(INTEL_PINEVIEW), 325 .is_mobile = 1, 326 .display.has_hotplug = 1, 327 .display.has_overlay = 1, 328 .dma_mask_size = 36, 329 }; 330 331 #define GEN4_FEATURES \ 332 GEN(4), \ 333 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 334 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 335 .display.has_hotplug = 1, \ 336 .display.has_gmch = 1, \ 337 .gpu_reset_clobbers_display = true, \ 338 .__runtime.platform_engine_mask = BIT(RCS0), \ 339 .has_3d_pipeline = 1, \ 340 .has_snoop = true, \ 341 .has_coherent_ggtt = true, \ 342 .dma_mask_size = 36, \ 343 I9XX_PIPE_OFFSETS, \ 344 I9XX_CURSOR_OFFSETS, \ 345 I9XX_COLORS, \ 346 GEN_DEFAULT_PAGE_SIZES, \ 347 GEN_DEFAULT_REGIONS 348 349 static const struct intel_device_info i965g_info = { 350 GEN4_FEATURES, 351 PLATFORM(INTEL_I965G), 352 .display.has_overlay = 1, 353 .hws_needs_physical = 1, 354 .has_snoop = false, 355 }; 356 357 static const struct intel_device_info i965gm_info = { 358 GEN4_FEATURES, 359 PLATFORM(INTEL_I965GM), 360 .is_mobile = 1, 361 .__runtime.fbc_mask = BIT(INTEL_FBC_A), 362 .display.has_overlay = 1, 363 .display.supports_tv = 1, 364 .hws_needs_physical = 1, 365 .has_snoop = false, 366 }; 367 368 static const struct intel_device_info g45_info = { 369 GEN4_FEATURES, 370 PLATFORM(INTEL_G45), 371 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0), 372 .gpu_reset_clobbers_display = false, 373 }; 374 375 static const struct intel_device_info gm45_info = { 376 GEN4_FEATURES, 377 PLATFORM(INTEL_GM45), 378 .is_mobile = 1, 379 .__runtime.fbc_mask = BIT(INTEL_FBC_A), 380 .display.supports_tv = 1, 381 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0), 382 .gpu_reset_clobbers_display = false, 383 }; 384 385 #define GEN5_FEATURES \ 386 GEN(5), \ 387 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 388 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 389 .display.has_hotplug = 1, \ 390 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0), \ 391 .has_3d_pipeline = 1, \ 392 .has_snoop = true, \ 393 .has_coherent_ggtt = true, \ 394 /* ilk does support rc6, but we do not implement [power] contexts */ \ 395 .has_rc6 = 0, \ 396 .dma_mask_size = 36, \ 397 I9XX_PIPE_OFFSETS, \ 398 I9XX_CURSOR_OFFSETS, \ 399 ILK_COLORS, \ 400 GEN_DEFAULT_PAGE_SIZES, \ 401 GEN_DEFAULT_REGIONS 402 403 static const struct intel_device_info ilk_d_info = { 404 GEN5_FEATURES, 405 PLATFORM(INTEL_IRONLAKE), 406 }; 407 408 static const struct intel_device_info ilk_m_info = { 409 GEN5_FEATURES, 410 PLATFORM(INTEL_IRONLAKE), 411 .is_mobile = 1, 412 .has_rps = true, 413 .__runtime.fbc_mask = BIT(INTEL_FBC_A), 414 }; 415 416 #define GEN6_FEATURES \ 417 GEN(6), \ 418 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 419 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 420 .display.has_hotplug = 1, \ 421 .__runtime.fbc_mask = BIT(INTEL_FBC_A), \ 422 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ 423 .has_3d_pipeline = 1, \ 424 .has_coherent_ggtt = true, \ 425 .has_llc = 1, \ 426 .has_rc6 = 1, \ 427 /* snb does support rc6p, but enabling it causes various issues */ \ 428 .has_rc6p = 0, \ 429 .has_rps = true, \ 430 .dma_mask_size = 40, \ 431 .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \ 432 .__runtime.ppgtt_size = 31, \ 433 I9XX_PIPE_OFFSETS, \ 434 I9XX_CURSOR_OFFSETS, \ 435 ILK_COLORS, \ 436 GEN_DEFAULT_PAGE_SIZES, \ 437 GEN_DEFAULT_REGIONS 438 439 #define SNB_D_PLATFORM \ 440 GEN6_FEATURES, \ 441 PLATFORM(INTEL_SANDYBRIDGE) 442 443 static const struct intel_device_info snb_d_gt1_info = { 444 SNB_D_PLATFORM, 445 .gt = 1, 446 }; 447 448 static const struct intel_device_info snb_d_gt2_info = { 449 SNB_D_PLATFORM, 450 .gt = 2, 451 }; 452 453 #define SNB_M_PLATFORM \ 454 GEN6_FEATURES, \ 455 PLATFORM(INTEL_SANDYBRIDGE), \ 456 .is_mobile = 1 457 458 459 static const struct intel_device_info snb_m_gt1_info = { 460 SNB_M_PLATFORM, 461 .gt = 1, 462 }; 463 464 static const struct intel_device_info snb_m_gt2_info = { 465 SNB_M_PLATFORM, 466 .gt = 2, 467 }; 468 469 #define GEN7_FEATURES \ 470 GEN(7), \ 471 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ 472 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \ 473 .display.has_hotplug = 1, \ 474 .__runtime.fbc_mask = BIT(INTEL_FBC_A), \ 475 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ 476 .has_3d_pipeline = 1, \ 477 .has_coherent_ggtt = true, \ 478 .has_llc = 1, \ 479 .has_rc6 = 1, \ 480 .has_rc6p = 1, \ 481 .has_reset_engine = true, \ 482 .has_rps = true, \ 483 .dma_mask_size = 40, \ 484 .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \ 485 .__runtime.ppgtt_size = 31, \ 486 IVB_PIPE_OFFSETS, \ 487 IVB_CURSOR_OFFSETS, \ 488 IVB_COLORS, \ 489 GEN_DEFAULT_PAGE_SIZES, \ 490 GEN_DEFAULT_REGIONS 491 492 #define IVB_D_PLATFORM \ 493 GEN7_FEATURES, \ 494 PLATFORM(INTEL_IVYBRIDGE), \ 495 .has_l3_dpf = 1 496 497 static const struct intel_device_info ivb_d_gt1_info = { 498 IVB_D_PLATFORM, 499 .gt = 1, 500 }; 501 502 static const struct intel_device_info ivb_d_gt2_info = { 503 IVB_D_PLATFORM, 504 .gt = 2, 505 }; 506 507 #define IVB_M_PLATFORM \ 508 GEN7_FEATURES, \ 509 PLATFORM(INTEL_IVYBRIDGE), \ 510 .is_mobile = 1, \ 511 .has_l3_dpf = 1 512 513 static const struct intel_device_info ivb_m_gt1_info = { 514 IVB_M_PLATFORM, 515 .gt = 1, 516 }; 517 518 static const struct intel_device_info ivb_m_gt2_info = { 519 IVB_M_PLATFORM, 520 .gt = 2, 521 }; 522 523 static const struct intel_device_info ivb_q_info = { 524 GEN7_FEATURES, 525 PLATFORM(INTEL_IVYBRIDGE), 526 NO_DISPLAY, 527 .gt = 2, 528 .has_l3_dpf = 1, 529 }; 530 531 static const struct intel_device_info vlv_info = { 532 PLATFORM(INTEL_VALLEYVIEW), 533 GEN(7), 534 .is_lp = 1, 535 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), 536 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), 537 .has_runtime_pm = 1, 538 .has_rc6 = 1, 539 .has_reset_engine = true, 540 .has_rps = true, 541 .display.has_gmch = 1, 542 .display.has_hotplug = 1, 543 .dma_mask_size = 40, 544 .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, 545 .__runtime.ppgtt_size = 31, 546 .has_snoop = true, 547 .has_coherent_ggtt = false, 548 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), 549 .display.mmio_offset = VLV_DISPLAY_BASE, 550 I9XX_PIPE_OFFSETS, 551 I9XX_CURSOR_OFFSETS, 552 I9XX_COLORS, 553 GEN_DEFAULT_PAGE_SIZES, 554 GEN_DEFAULT_REGIONS, 555 }; 556 557 #define G75_FEATURES \ 558 GEN7_FEATURES, \ 559 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ 560 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 561 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \ 562 .display.has_ddi = 1, \ 563 .display.has_fpga_dbg = 1, \ 564 .display.has_dp_mst = 1, \ 565 .has_rc6p = 0 /* RC6p removed-by HSW */, \ 566 HSW_PIPE_OFFSETS, \ 567 .has_runtime_pm = 1 568 569 #define HSW_PLATFORM \ 570 G75_FEATURES, \ 571 PLATFORM(INTEL_HASWELL), \ 572 .has_l3_dpf = 1 573 574 static const struct intel_device_info hsw_gt1_info = { 575 HSW_PLATFORM, 576 .gt = 1, 577 }; 578 579 static const struct intel_device_info hsw_gt2_info = { 580 HSW_PLATFORM, 581 .gt = 2, 582 }; 583 584 static const struct intel_device_info hsw_gt3_info = { 585 HSW_PLATFORM, 586 .gt = 3, 587 }; 588 589 #define GEN8_FEATURES \ 590 G75_FEATURES, \ 591 GEN(8), \ 592 .has_logical_ring_contexts = 1, \ 593 .dma_mask_size = 39, \ 594 .__runtime.ppgtt_type = INTEL_PPGTT_FULL, \ 595 .__runtime.ppgtt_size = 48, \ 596 .has_64bit_reloc = 1 597 598 #define BDW_PLATFORM \ 599 GEN8_FEATURES, \ 600 PLATFORM(INTEL_BROADWELL) 601 602 static const struct intel_device_info bdw_gt1_info = { 603 BDW_PLATFORM, 604 .gt = 1, 605 }; 606 607 static const struct intel_device_info bdw_gt2_info = { 608 BDW_PLATFORM, 609 .gt = 2, 610 }; 611 612 static const struct intel_device_info bdw_rsvd_info = { 613 BDW_PLATFORM, 614 .gt = 3, 615 /* According to the device ID those devices are GT3, they were 616 * previously treated as not GT3, keep it like that. 617 */ 618 }; 619 620 static const struct intel_device_info bdw_gt3_info = { 621 BDW_PLATFORM, 622 .gt = 3, 623 .__runtime.platform_engine_mask = 624 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 625 }; 626 627 static const struct intel_device_info chv_info = { 628 PLATFORM(INTEL_CHERRYVIEW), 629 GEN(8), 630 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 631 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), 632 .display.has_hotplug = 1, 633 .is_lp = 1, 634 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), 635 .has_64bit_reloc = 1, 636 .has_runtime_pm = 1, 637 .has_rc6 = 1, 638 .has_rps = true, 639 .has_logical_ring_contexts = 1, 640 .display.has_gmch = 1, 641 .dma_mask_size = 39, 642 .__runtime.ppgtt_type = INTEL_PPGTT_FULL, 643 .__runtime.ppgtt_size = 32, 644 .has_reset_engine = 1, 645 .has_snoop = true, 646 .has_coherent_ggtt = false, 647 .display.mmio_offset = VLV_DISPLAY_BASE, 648 CHV_PIPE_OFFSETS, 649 CHV_CURSOR_OFFSETS, 650 CHV_COLORS, 651 GEN_DEFAULT_PAGE_SIZES, 652 GEN_DEFAULT_REGIONS, 653 }; 654 655 #define GEN9_DEFAULT_PAGE_SIZES \ 656 .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \ 657 I915_GTT_PAGE_SIZE_64K 658 659 #define GEN9_FEATURES \ 660 GEN8_FEATURES, \ 661 GEN(9), \ 662 GEN9_DEFAULT_PAGE_SIZES, \ 663 .__runtime.has_dmc = 1, \ 664 .has_gt_uc = 1, \ 665 .__runtime.has_hdcp = 1, \ 666 .display.has_ipc = 1, \ 667 .display.has_psr = 1, \ 668 .display.has_psr_hw_tracking = 1, \ 669 .display.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \ 670 .display.dbuf.slice_mask = BIT(DBUF_S1) 671 672 #define SKL_PLATFORM \ 673 GEN9_FEATURES, \ 674 PLATFORM(INTEL_SKYLAKE) 675 676 static const struct intel_device_info skl_gt1_info = { 677 SKL_PLATFORM, 678 .gt = 1, 679 }; 680 681 static const struct intel_device_info skl_gt2_info = { 682 SKL_PLATFORM, 683 .gt = 2, 684 }; 685 686 #define SKL_GT3_PLUS_PLATFORM \ 687 SKL_PLATFORM, \ 688 .__runtime.platform_engine_mask = \ 689 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1) 690 691 692 static const struct intel_device_info skl_gt3_info = { 693 SKL_GT3_PLUS_PLATFORM, 694 .gt = 3, 695 }; 696 697 static const struct intel_device_info skl_gt4_info = { 698 SKL_GT3_PLUS_PLATFORM, 699 .gt = 4, 700 }; 701 702 #define GEN9_LP_FEATURES \ 703 GEN(9), \ 704 .is_lp = 1, \ 705 .display.dbuf.slice_mask = BIT(DBUF_S1), \ 706 .display.has_hotplug = 1, \ 707 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ 708 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ 709 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 710 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ 711 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \ 712 .has_3d_pipeline = 1, \ 713 .has_64bit_reloc = 1, \ 714 .display.has_ddi = 1, \ 715 .display.has_fpga_dbg = 1, \ 716 .__runtime.fbc_mask = BIT(INTEL_FBC_A), \ 717 .__runtime.has_hdcp = 1, \ 718 .display.has_psr = 1, \ 719 .display.has_psr_hw_tracking = 1, \ 720 .has_runtime_pm = 1, \ 721 .__runtime.has_dmc = 1, \ 722 .has_rc6 = 1, \ 723 .has_rps = true, \ 724 .display.has_dp_mst = 1, \ 725 .has_logical_ring_contexts = 1, \ 726 .has_gt_uc = 1, \ 727 .dma_mask_size = 39, \ 728 .__runtime.ppgtt_type = INTEL_PPGTT_FULL, \ 729 .__runtime.ppgtt_size = 48, \ 730 .has_reset_engine = 1, \ 731 .has_snoop = true, \ 732 .has_coherent_ggtt = false, \ 733 .display.has_ipc = 1, \ 734 HSW_PIPE_OFFSETS, \ 735 IVB_CURSOR_OFFSETS, \ 736 IVB_COLORS, \ 737 GEN9_DEFAULT_PAGE_SIZES, \ 738 GEN_DEFAULT_REGIONS 739 740 static const struct intel_device_info bxt_info = { 741 GEN9_LP_FEATURES, 742 PLATFORM(INTEL_BROXTON), 743 .display.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */ 744 }; 745 746 static const struct intel_device_info glk_info = { 747 GEN9_LP_FEATURES, 748 PLATFORM(INTEL_GEMINILAKE), 749 .__runtime.display.ip.ver = 10, 750 .display.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ 751 GLK_COLORS, 752 }; 753 754 #define KBL_PLATFORM \ 755 GEN9_FEATURES, \ 756 PLATFORM(INTEL_KABYLAKE) 757 758 static const struct intel_device_info kbl_gt1_info = { 759 KBL_PLATFORM, 760 .gt = 1, 761 }; 762 763 static const struct intel_device_info kbl_gt2_info = { 764 KBL_PLATFORM, 765 .gt = 2, 766 }; 767 768 static const struct intel_device_info kbl_gt3_info = { 769 KBL_PLATFORM, 770 .gt = 3, 771 .__runtime.platform_engine_mask = 772 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 773 }; 774 775 #define CFL_PLATFORM \ 776 GEN9_FEATURES, \ 777 PLATFORM(INTEL_COFFEELAKE) 778 779 static const struct intel_device_info cfl_gt1_info = { 780 CFL_PLATFORM, 781 .gt = 1, 782 }; 783 784 static const struct intel_device_info cfl_gt2_info = { 785 CFL_PLATFORM, 786 .gt = 2, 787 }; 788 789 static const struct intel_device_info cfl_gt3_info = { 790 CFL_PLATFORM, 791 .gt = 3, 792 .__runtime.platform_engine_mask = 793 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 794 }; 795 796 #define CML_PLATFORM \ 797 GEN9_FEATURES, \ 798 PLATFORM(INTEL_COMETLAKE) 799 800 static const struct intel_device_info cml_gt1_info = { 801 CML_PLATFORM, 802 .gt = 1, 803 }; 804 805 static const struct intel_device_info cml_gt2_info = { 806 CML_PLATFORM, 807 .gt = 2, 808 }; 809 810 #define GEN11_DEFAULT_PAGE_SIZES \ 811 .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \ 812 I915_GTT_PAGE_SIZE_64K | \ 813 I915_GTT_PAGE_SIZE_2M 814 815 #define GEN11_FEATURES \ 816 GEN9_FEATURES, \ 817 GEN11_DEFAULT_PAGE_SIZES, \ 818 .display.abox_mask = BIT(0), \ 819 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 820 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ 821 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ 822 .display.pipe_offsets = { \ 823 [TRANSCODER_A] = PIPE_A_OFFSET, \ 824 [TRANSCODER_B] = PIPE_B_OFFSET, \ 825 [TRANSCODER_C] = PIPE_C_OFFSET, \ 826 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 827 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 828 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 829 }, \ 830 .display.trans_offsets = { \ 831 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 832 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 833 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 834 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 835 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 836 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 837 }, \ 838 GEN(11), \ 839 ICL_COLORS, \ 840 .display.dbuf.size = 2048, \ 841 .display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \ 842 .__runtime.has_dsc = 1, \ 843 .has_coherent_ggtt = false, \ 844 .has_logical_ring_elsq = 1 845 846 static const struct intel_device_info icl_info = { 847 GEN11_FEATURES, 848 PLATFORM(INTEL_ICELAKE), 849 .__runtime.platform_engine_mask = 850 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 851 }; 852 853 static const struct intel_device_info ehl_info = { 854 GEN11_FEATURES, 855 PLATFORM(INTEL_ELKHARTLAKE), 856 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0), 857 .__runtime.ppgtt_size = 36, 858 }; 859 860 static const struct intel_device_info jsl_info = { 861 GEN11_FEATURES, 862 PLATFORM(INTEL_JASPERLAKE), 863 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0), 864 .__runtime.ppgtt_size = 36, 865 }; 866 867 #define GEN12_FEATURES \ 868 GEN11_FEATURES, \ 869 GEN(12), \ 870 .display.abox_mask = GENMASK(2, 1), \ 871 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ 872 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 873 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \ 874 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ 875 .display.pipe_offsets = { \ 876 [TRANSCODER_A] = PIPE_A_OFFSET, \ 877 [TRANSCODER_B] = PIPE_B_OFFSET, \ 878 [TRANSCODER_C] = PIPE_C_OFFSET, \ 879 [TRANSCODER_D] = PIPE_D_OFFSET, \ 880 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 881 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 882 }, \ 883 .display.trans_offsets = { \ 884 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 885 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 886 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 887 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ 888 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 889 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 890 }, \ 891 TGL_CURSOR_OFFSETS, \ 892 .has_global_mocs = 1, \ 893 .has_pxp = 1, \ 894 .display.has_dsb = 1 895 896 static const struct intel_device_info tgl_info = { 897 GEN12_FEATURES, 898 PLATFORM(INTEL_TIGERLAKE), 899 .__runtime.platform_engine_mask = 900 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 901 }; 902 903 static const struct intel_device_info rkl_info = { 904 GEN12_FEATURES, 905 PLATFORM(INTEL_ROCKETLAKE), 906 .display.abox_mask = BIT(0), 907 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 908 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 909 BIT(TRANSCODER_C), 910 .display.has_hti = 1, 911 .display.has_psr_hw_tracking = 0, 912 .__runtime.platform_engine_mask = 913 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0), 914 }; 915 916 #define DGFX_FEATURES \ 917 .__runtime.memory_regions = REGION_SMEM | REGION_LMEM | REGION_STOLEN_LMEM, \ 918 .has_llc = 0, \ 919 .has_pxp = 0, \ 920 .has_snoop = 1, \ 921 .is_dgfx = 1, \ 922 .has_heci_gscfi = 1 923 924 static const struct intel_device_info dg1_info = { 925 GEN12_FEATURES, 926 DGFX_FEATURES, 927 .__runtime.graphics.ip.rel = 10, 928 PLATFORM(INTEL_DG1), 929 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 930 .require_force_probe = 1, 931 .__runtime.platform_engine_mask = 932 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | 933 BIT(VCS0) | BIT(VCS2), 934 /* Wa_16011227922 */ 935 .__runtime.ppgtt_size = 47, 936 }; 937 938 static const struct intel_device_info adl_s_info = { 939 GEN12_FEATURES, 940 PLATFORM(INTEL_ALDERLAKE_S), 941 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 942 .display.has_hti = 1, 943 .display.has_psr_hw_tracking = 0, 944 .__runtime.platform_engine_mask = 945 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 946 .dma_mask_size = 39, 947 }; 948 949 #define XE_LPD_FEATURES \ 950 .display.abox_mask = GENMASK(1, 0), \ 951 .display.color = { \ 952 .degamma_lut_size = 129, .gamma_lut_size = 1024, \ 953 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 954 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 955 }, \ 956 .display.dbuf.size = 4096, \ 957 .display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \ 958 BIT(DBUF_S4), \ 959 .display.has_ddi = 1, \ 960 .__runtime.has_dmc = 1, \ 961 .display.has_dp_mst = 1, \ 962 .display.has_dsb = 1, \ 963 .__runtime.has_dsc = 1, \ 964 .__runtime.fbc_mask = BIT(INTEL_FBC_A), \ 965 .display.has_fpga_dbg = 1, \ 966 .__runtime.has_hdcp = 1, \ 967 .display.has_hotplug = 1, \ 968 .display.has_ipc = 1, \ 969 .display.has_psr = 1, \ 970 .__runtime.display.ip.ver = 13, \ 971 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ 972 .display.pipe_offsets = { \ 973 [TRANSCODER_A] = PIPE_A_OFFSET, \ 974 [TRANSCODER_B] = PIPE_B_OFFSET, \ 975 [TRANSCODER_C] = PIPE_C_OFFSET, \ 976 [TRANSCODER_D] = PIPE_D_OFFSET, \ 977 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 978 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 979 }, \ 980 .display.trans_offsets = { \ 981 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 982 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 983 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 984 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ 985 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 986 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 987 }, \ 988 TGL_CURSOR_OFFSETS 989 990 static const struct intel_device_info adl_p_info = { 991 GEN12_FEATURES, 992 XE_LPD_FEATURES, 993 PLATFORM(INTEL_ALDERLAKE_P), 994 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 995 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | 996 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), 997 .display.has_cdclk_crawl = 1, 998 .display.has_psr_hw_tracking = 0, 999 .__runtime.platform_engine_mask = 1000 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 1001 .__runtime.ppgtt_size = 48, 1002 .dma_mask_size = 39, 1003 }; 1004 1005 #undef GEN 1006 1007 #define XE_HP_PAGE_SIZES \ 1008 .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \ 1009 I915_GTT_PAGE_SIZE_64K | \ 1010 I915_GTT_PAGE_SIZE_2M 1011 1012 #define XE_HP_FEATURES \ 1013 .__runtime.graphics.ip.ver = 12, \ 1014 .__runtime.graphics.ip.rel = 50, \ 1015 XE_HP_PAGE_SIZES, \ 1016 .dma_mask_size = 46, \ 1017 .has_3d_pipeline = 1, \ 1018 .has_64bit_reloc = 1, \ 1019 .has_flat_ccs = 1, \ 1020 .has_4tile = 1, \ 1021 .has_global_mocs = 1, \ 1022 .has_gt_uc = 1, \ 1023 .has_llc = 1, \ 1024 .has_logical_ring_contexts = 1, \ 1025 .has_logical_ring_elsq = 1, \ 1026 .has_mslice_steering = 1, \ 1027 .has_oa_bpc_reporting = 1, \ 1028 .has_oa_slice_contrib_limits = 1, \ 1029 .has_oam = 1, \ 1030 .has_rc6 = 1, \ 1031 .has_reset_engine = 1, \ 1032 .has_rps = 1, \ 1033 .has_runtime_pm = 1, \ 1034 .__runtime.ppgtt_size = 48, \ 1035 .__runtime.ppgtt_type = INTEL_PPGTT_FULL 1036 1037 #define XE_HPM_FEATURES \ 1038 .__runtime.media.ip.ver = 12, \ 1039 .__runtime.media.ip.rel = 50 1040 1041 __maybe_unused 1042 static const struct intel_device_info xehpsdv_info = { 1043 XE_HP_FEATURES, 1044 XE_HPM_FEATURES, 1045 DGFX_FEATURES, 1046 PLATFORM(INTEL_XEHPSDV), 1047 NO_DISPLAY, 1048 .has_64k_pages = 1, 1049 .has_media_ratio_mode = 1, 1050 .__runtime.platform_engine_mask = 1051 BIT(RCS0) | BIT(BCS0) | 1052 BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) | 1053 BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) | 1054 BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7) | 1055 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3), 1056 .require_force_probe = 1, 1057 }; 1058 1059 #define DG2_FEATURES \ 1060 XE_HP_FEATURES, \ 1061 XE_HPM_FEATURES, \ 1062 DGFX_FEATURES, \ 1063 .__runtime.graphics.ip.rel = 55, \ 1064 .__runtime.media.ip.rel = 55, \ 1065 PLATFORM(INTEL_DG2), \ 1066 .has_64k_pages = 1, \ 1067 .has_guc_deprivilege = 1, \ 1068 .has_heci_pxp = 1, \ 1069 .has_media_ratio_mode = 1, \ 1070 .display.has_cdclk_squash = 1, \ 1071 .__runtime.platform_engine_mask = \ 1072 BIT(RCS0) | BIT(BCS0) | \ 1073 BIT(VECS0) | BIT(VECS1) | \ 1074 BIT(VCS0) | BIT(VCS2) | \ 1075 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3) 1076 1077 static const struct intel_device_info dg2_info = { 1078 DG2_FEATURES, 1079 XE_LPD_FEATURES, 1080 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 1081 BIT(TRANSCODER_C) | BIT(TRANSCODER_D), 1082 }; 1083 1084 static const struct intel_device_info ats_m_info = { 1085 DG2_FEATURES, 1086 NO_DISPLAY, 1087 .require_force_probe = 1, 1088 .tuning_thread_rr_after_dep = 1, 1089 }; 1090 1091 #define XE_HPC_FEATURES \ 1092 XE_HP_FEATURES, \ 1093 .dma_mask_size = 52, \ 1094 .has_3d_pipeline = 0, \ 1095 .has_guc_deprivilege = 1, \ 1096 .has_l3_ccs_read = 1, \ 1097 .has_mslice_steering = 0, \ 1098 .has_one_eu_per_fuse_bit = 1 1099 1100 __maybe_unused 1101 static const struct intel_device_info pvc_info = { 1102 XE_HPC_FEATURES, 1103 XE_HPM_FEATURES, 1104 DGFX_FEATURES, 1105 .__runtime.graphics.ip.rel = 60, 1106 .__runtime.media.ip.rel = 60, 1107 PLATFORM(INTEL_PONTEVECCHIO), 1108 NO_DISPLAY, 1109 .has_flat_ccs = 0, 1110 .__runtime.platform_engine_mask = 1111 BIT(BCS0) | 1112 BIT(VCS0) | 1113 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3), 1114 .require_force_probe = 1, 1115 }; 1116 1117 #define XE_LPDP_FEATURES \ 1118 XE_LPD_FEATURES, \ 1119 .__runtime.display.ip.ver = 14, \ 1120 .display.has_cdclk_crawl = 1, \ 1121 .display.has_cdclk_squash = 1, \ 1122 .__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B) 1123 1124 static const struct intel_gt_definition xelpmp_extra_gt[] = { 1125 { 1126 .type = GT_MEDIA, 1127 .name = "Standalone Media GT", 1128 .gsi_offset = MTL_MEDIA_GSI_BASE, 1129 .engine_mask = BIT(VECS0) | BIT(VCS0) | BIT(VCS2) | BIT(GSC0), 1130 }, 1131 {} 1132 }; 1133 1134 static const struct intel_device_info mtl_info = { 1135 XE_HP_FEATURES, 1136 XE_LPDP_FEATURES, 1137 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 1138 BIT(TRANSCODER_C) | BIT(TRANSCODER_D), 1139 /* 1140 * Real graphics IP version will be obtained from hardware GMD_ID 1141 * register. Value provided here is just for sanity checking. 1142 */ 1143 .__runtime.graphics.ip.ver = 12, 1144 .__runtime.graphics.ip.rel = 70, 1145 .__runtime.media.ip.ver = 13, 1146 PLATFORM(INTEL_METEORLAKE), 1147 .extra_gt_list = xelpmp_extra_gt, 1148 .has_flat_ccs = 0, 1149 .has_gmd_id = 1, 1150 .has_guc_deprivilege = 1, 1151 .has_mslice_steering = 0, 1152 .has_snoop = 1, 1153 .__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM, 1154 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0), 1155 .require_force_probe = 1, 1156 }; 1157 1158 #undef PLATFORM 1159 1160 /* 1161 * Make sure any device matches here are from most specific to most 1162 * general. For example, since the Quanta match is based on the subsystem 1163 * and subvendor IDs, we need it to come before the more general IVB 1164 * PCI ID matches, otherwise we'll use the wrong info struct above. 1165 */ 1166 static const struct pci_device_id pciidlist[] = { 1167 INTEL_I830_IDS(&i830_info), 1168 INTEL_I845G_IDS(&i845g_info), 1169 INTEL_I85X_IDS(&i85x_info), 1170 INTEL_I865G_IDS(&i865g_info), 1171 INTEL_I915G_IDS(&i915g_info), 1172 INTEL_I915GM_IDS(&i915gm_info), 1173 INTEL_I945G_IDS(&i945g_info), 1174 INTEL_I945GM_IDS(&i945gm_info), 1175 INTEL_I965G_IDS(&i965g_info), 1176 INTEL_G33_IDS(&g33_info), 1177 INTEL_I965GM_IDS(&i965gm_info), 1178 INTEL_GM45_IDS(&gm45_info), 1179 INTEL_G45_IDS(&g45_info), 1180 INTEL_PINEVIEW_G_IDS(&pnv_g_info), 1181 INTEL_PINEVIEW_M_IDS(&pnv_m_info), 1182 INTEL_IRONLAKE_D_IDS(&ilk_d_info), 1183 INTEL_IRONLAKE_M_IDS(&ilk_m_info), 1184 INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info), 1185 INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info), 1186 INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info), 1187 INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info), 1188 INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */ 1189 INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info), 1190 INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info), 1191 INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info), 1192 INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info), 1193 INTEL_HSW_GT1_IDS(&hsw_gt1_info), 1194 INTEL_HSW_GT2_IDS(&hsw_gt2_info), 1195 INTEL_HSW_GT3_IDS(&hsw_gt3_info), 1196 INTEL_VLV_IDS(&vlv_info), 1197 INTEL_BDW_GT1_IDS(&bdw_gt1_info), 1198 INTEL_BDW_GT2_IDS(&bdw_gt2_info), 1199 INTEL_BDW_GT3_IDS(&bdw_gt3_info), 1200 INTEL_BDW_RSVD_IDS(&bdw_rsvd_info), 1201 INTEL_CHV_IDS(&chv_info), 1202 INTEL_SKL_GT1_IDS(&skl_gt1_info), 1203 INTEL_SKL_GT2_IDS(&skl_gt2_info), 1204 INTEL_SKL_GT3_IDS(&skl_gt3_info), 1205 INTEL_SKL_GT4_IDS(&skl_gt4_info), 1206 INTEL_BXT_IDS(&bxt_info), 1207 INTEL_GLK_IDS(&glk_info), 1208 INTEL_KBL_GT1_IDS(&kbl_gt1_info), 1209 INTEL_KBL_GT2_IDS(&kbl_gt2_info), 1210 INTEL_KBL_GT3_IDS(&kbl_gt3_info), 1211 INTEL_KBL_GT4_IDS(&kbl_gt3_info), 1212 INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info), 1213 INTEL_CFL_S_GT1_IDS(&cfl_gt1_info), 1214 INTEL_CFL_S_GT2_IDS(&cfl_gt2_info), 1215 INTEL_CFL_H_GT1_IDS(&cfl_gt1_info), 1216 INTEL_CFL_H_GT2_IDS(&cfl_gt2_info), 1217 INTEL_CFL_U_GT2_IDS(&cfl_gt2_info), 1218 INTEL_CFL_U_GT3_IDS(&cfl_gt3_info), 1219 INTEL_WHL_U_GT1_IDS(&cfl_gt1_info), 1220 INTEL_WHL_U_GT2_IDS(&cfl_gt2_info), 1221 INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info), 1222 INTEL_WHL_U_GT3_IDS(&cfl_gt3_info), 1223 INTEL_CML_GT1_IDS(&cml_gt1_info), 1224 INTEL_CML_GT2_IDS(&cml_gt2_info), 1225 INTEL_CML_U_GT1_IDS(&cml_gt1_info), 1226 INTEL_CML_U_GT2_IDS(&cml_gt2_info), 1227 INTEL_ICL_11_IDS(&icl_info), 1228 INTEL_EHL_IDS(&ehl_info), 1229 INTEL_JSL_IDS(&jsl_info), 1230 INTEL_TGL_12_IDS(&tgl_info), 1231 INTEL_RKL_IDS(&rkl_info), 1232 INTEL_ADLS_IDS(&adl_s_info), 1233 INTEL_ADLP_IDS(&adl_p_info), 1234 INTEL_ADLN_IDS(&adl_p_info), 1235 INTEL_DG1_IDS(&dg1_info), 1236 INTEL_RPLS_IDS(&adl_s_info), 1237 INTEL_RPLP_IDS(&adl_p_info), 1238 INTEL_DG2_IDS(&dg2_info), 1239 INTEL_ATS_M_IDS(&ats_m_info), 1240 INTEL_MTL_IDS(&mtl_info), 1241 {0, 0, 0} 1242 }; 1243 MODULE_DEVICE_TABLE(pci, pciidlist); 1244 1245 static void i915_pci_remove(struct pci_dev *pdev) 1246 { 1247 struct drm_i915_private *i915; 1248 1249 i915 = pci_get_drvdata(pdev); 1250 if (!i915) /* driver load aborted, nothing to cleanup */ 1251 return; 1252 1253 i915_driver_remove(i915); 1254 pci_set_drvdata(pdev, NULL); 1255 } 1256 1257 /* is device_id present in comma separated list of ids */ 1258 static bool device_id_in_list(u16 device_id, const char *devices, bool negative) 1259 { 1260 char *s, *p, *tok; 1261 bool ret; 1262 1263 if (!devices || !*devices) 1264 return false; 1265 1266 /* match everything */ 1267 if (negative && strcmp(devices, "!*") == 0) 1268 return true; 1269 if (!negative && strcmp(devices, "*") == 0) 1270 return true; 1271 1272 s = kstrdup(devices, GFP_KERNEL); 1273 if (!s) 1274 return false; 1275 1276 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) { 1277 u16 val; 1278 1279 if (negative && tok[0] == '!') 1280 tok++; 1281 else if ((negative && tok[0] != '!') || 1282 (!negative && tok[0] == '!')) 1283 continue; 1284 1285 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) { 1286 ret = true; 1287 break; 1288 } 1289 } 1290 1291 kfree(s); 1292 1293 return ret; 1294 } 1295 1296 static bool id_forced(u16 device_id) 1297 { 1298 return device_id_in_list(device_id, i915_modparams.force_probe, false); 1299 } 1300 1301 static bool id_blocked(u16 device_id) 1302 { 1303 return device_id_in_list(device_id, i915_modparams.force_probe, true); 1304 } 1305 1306 bool i915_pci_resource_valid(struct pci_dev *pdev, int bar) 1307 { 1308 if (!pci_resource_flags(pdev, bar)) 1309 return false; 1310 1311 if (pci_resource_flags(pdev, bar) & IORESOURCE_UNSET) 1312 return false; 1313 1314 if (!pci_resource_len(pdev, bar)) 1315 return false; 1316 1317 return true; 1318 } 1319 1320 static bool intel_mmio_bar_valid(struct pci_dev *pdev, struct intel_device_info *intel_info) 1321 { 1322 return i915_pci_resource_valid(pdev, intel_mmio_bar(intel_info->__runtime.graphics.ip.ver)); 1323 } 1324 1325 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1326 { 1327 struct intel_device_info *intel_info = 1328 (struct intel_device_info *) ent->driver_data; 1329 int err; 1330 1331 if (intel_info->require_force_probe && !id_forced(pdev->device)) { 1332 dev_info(&pdev->dev, 1333 "Your graphics device %04x is not properly supported by i915 in this\n" 1334 "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n" 1335 "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n" 1336 "or (recommended) check for kernel updates.\n", 1337 pdev->device, pdev->device, pdev->device); 1338 return -ENODEV; 1339 } 1340 1341 if (id_blocked(pdev->device)) { 1342 dev_info(&pdev->dev, "I915 probe blocked for Device ID %04x.\n", 1343 pdev->device); 1344 return -ENODEV; 1345 } 1346 1347 if (intel_info->require_force_probe) { 1348 dev_info(&pdev->dev, "Force probing unsupported Device ID %04x, tainting kernel\n", 1349 pdev->device); 1350 add_taint(TAINT_USER, LOCKDEP_STILL_OK); 1351 } 1352 1353 /* Only bind to function 0 of the device. Early generations 1354 * used function 1 as a placeholder for multi-head. This causes 1355 * us confusion instead, especially on the systems where both 1356 * functions have the same PCI-ID! 1357 */ 1358 if (PCI_FUNC(pdev->devfn)) 1359 return -ENODEV; 1360 1361 if (!intel_mmio_bar_valid(pdev, intel_info)) 1362 return -ENXIO; 1363 1364 /* Detect if we need to wait for other drivers early on */ 1365 if (intel_modeset_probe_defer(pdev)) 1366 return -EPROBE_DEFER; 1367 1368 err = i915_driver_probe(pdev, ent); 1369 if (err) 1370 return err; 1371 1372 if (i915_inject_probe_failure(pci_get_drvdata(pdev))) { 1373 i915_pci_remove(pdev); 1374 return -ENODEV; 1375 } 1376 1377 err = i915_live_selftests(pdev); 1378 if (err) { 1379 i915_pci_remove(pdev); 1380 return err > 0 ? -ENOTTY : err; 1381 } 1382 1383 err = i915_perf_selftests(pdev); 1384 if (err) { 1385 i915_pci_remove(pdev); 1386 return err > 0 ? -ENOTTY : err; 1387 } 1388 1389 return 0; 1390 } 1391 1392 static void i915_pci_shutdown(struct pci_dev *pdev) 1393 { 1394 struct drm_i915_private *i915 = pci_get_drvdata(pdev); 1395 1396 i915_driver_shutdown(i915); 1397 } 1398 1399 static struct pci_driver i915_pci_driver = { 1400 .name = DRIVER_NAME, 1401 .id_table = pciidlist, 1402 .probe = i915_pci_probe, 1403 .remove = i915_pci_remove, 1404 .shutdown = i915_pci_shutdown, 1405 .driver.pm = &i915_pm_ops, 1406 }; 1407 1408 int i915_pci_register_driver(void) 1409 { 1410 return pci_register_driver(&i915_pci_driver); 1411 } 1412 1413 void i915_pci_unregister_driver(void) 1414 { 1415 pci_unregister_driver(&i915_pci_driver); 1416 } 1417