1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/console.h> 26 #include <linux/vgaarb.h> 27 #include <linux/vga_switcheroo.h> 28 29 #include "i915_drv.h" 30 #include "i915_selftest.h" 31 32 #define PLATFORM(x) .platform = (x), .platform_mask = BIT(x) 33 #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1) 34 35 #define GEN_DEFAULT_PIPEOFFSETS \ 36 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ 37 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \ 38 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ 39 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \ 40 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET } 41 42 #define GEN_CHV_PIPEOFFSETS \ 43 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ 44 CHV_PIPE_C_OFFSET }, \ 45 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ 46 CHV_TRANSCODER_C_OFFSET, }, \ 47 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \ 48 CHV_PALETTE_C_OFFSET } 49 50 #define CURSOR_OFFSETS \ 51 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET } 52 53 #define IVB_CURSOR_OFFSETS \ 54 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET } 55 56 #define BDW_COLORS \ 57 .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 } 58 #define CHV_COLORS \ 59 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 } 60 #define GLK_COLORS \ 61 .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 } 62 63 /* Keep in gen based order, and chronological order within a gen */ 64 65 #define GEN_DEFAULT_PAGE_SIZES \ 66 .page_sizes = I915_GTT_PAGE_SIZE_4K 67 68 #define GEN2_FEATURES \ 69 GEN(2), \ 70 .num_pipes = 1, \ 71 .has_overlay = 1, .overlay_needs_physical = 1, \ 72 .has_gmch_display = 1, \ 73 .hws_needs_physical = 1, \ 74 .unfenced_needs_alignment = 1, \ 75 .ring_mask = RENDER_RING, \ 76 .has_snoop = true, \ 77 .has_coherent_ggtt = false, \ 78 GEN_DEFAULT_PIPEOFFSETS, \ 79 GEN_DEFAULT_PAGE_SIZES, \ 80 CURSOR_OFFSETS 81 82 static const struct intel_device_info intel_i830_info = { 83 GEN2_FEATURES, 84 PLATFORM(INTEL_I830), 85 .is_mobile = 1, .cursor_needs_physical = 1, 86 .num_pipes = 2, /* legal, last one wins */ 87 }; 88 89 static const struct intel_device_info intel_i845g_info = { 90 GEN2_FEATURES, 91 PLATFORM(INTEL_I845G), 92 }; 93 94 static const struct intel_device_info intel_i85x_info = { 95 GEN2_FEATURES, 96 PLATFORM(INTEL_I85X), 97 .is_mobile = 1, 98 .num_pipes = 2, /* legal, last one wins */ 99 .cursor_needs_physical = 1, 100 .has_fbc = 1, 101 }; 102 103 static const struct intel_device_info intel_i865g_info = { 104 GEN2_FEATURES, 105 PLATFORM(INTEL_I865G), 106 }; 107 108 #define GEN3_FEATURES \ 109 GEN(3), \ 110 .num_pipes = 2, \ 111 .has_gmch_display = 1, \ 112 .ring_mask = RENDER_RING, \ 113 .has_snoop = true, \ 114 .has_coherent_ggtt = true, \ 115 GEN_DEFAULT_PIPEOFFSETS, \ 116 GEN_DEFAULT_PAGE_SIZES, \ 117 CURSOR_OFFSETS 118 119 static const struct intel_device_info intel_i915g_info = { 120 GEN3_FEATURES, 121 PLATFORM(INTEL_I915G), 122 .has_coherent_ggtt = false, 123 .cursor_needs_physical = 1, 124 .has_overlay = 1, .overlay_needs_physical = 1, 125 .hws_needs_physical = 1, 126 .unfenced_needs_alignment = 1, 127 }; 128 129 static const struct intel_device_info intel_i915gm_info = { 130 GEN3_FEATURES, 131 PLATFORM(INTEL_I915GM), 132 .is_mobile = 1, 133 .cursor_needs_physical = 1, 134 .has_overlay = 1, .overlay_needs_physical = 1, 135 .supports_tv = 1, 136 .has_fbc = 1, 137 .hws_needs_physical = 1, 138 .unfenced_needs_alignment = 1, 139 }; 140 141 static const struct intel_device_info intel_i945g_info = { 142 GEN3_FEATURES, 143 PLATFORM(INTEL_I945G), 144 .has_hotplug = 1, .cursor_needs_physical = 1, 145 .has_overlay = 1, .overlay_needs_physical = 1, 146 .hws_needs_physical = 1, 147 .unfenced_needs_alignment = 1, 148 }; 149 150 static const struct intel_device_info intel_i945gm_info = { 151 GEN3_FEATURES, 152 PLATFORM(INTEL_I945GM), 153 .is_mobile = 1, 154 .has_hotplug = 1, .cursor_needs_physical = 1, 155 .has_overlay = 1, .overlay_needs_physical = 1, 156 .supports_tv = 1, 157 .has_fbc = 1, 158 .hws_needs_physical = 1, 159 .unfenced_needs_alignment = 1, 160 }; 161 162 static const struct intel_device_info intel_g33_info = { 163 GEN3_FEATURES, 164 PLATFORM(INTEL_G33), 165 .has_hotplug = 1, 166 .has_overlay = 1, 167 }; 168 169 static const struct intel_device_info intel_pineview_info = { 170 GEN3_FEATURES, 171 PLATFORM(INTEL_PINEVIEW), 172 .is_mobile = 1, 173 .has_hotplug = 1, 174 .has_overlay = 1, 175 }; 176 177 #define GEN4_FEATURES \ 178 GEN(4), \ 179 .num_pipes = 2, \ 180 .has_hotplug = 1, \ 181 .has_gmch_display = 1, \ 182 .ring_mask = RENDER_RING, \ 183 .has_snoop = true, \ 184 .has_coherent_ggtt = true, \ 185 GEN_DEFAULT_PIPEOFFSETS, \ 186 GEN_DEFAULT_PAGE_SIZES, \ 187 CURSOR_OFFSETS 188 189 static const struct intel_device_info intel_i965g_info = { 190 GEN4_FEATURES, 191 PLATFORM(INTEL_I965G), 192 .has_overlay = 1, 193 .hws_needs_physical = 1, 194 .has_snoop = false, 195 }; 196 197 static const struct intel_device_info intel_i965gm_info = { 198 GEN4_FEATURES, 199 PLATFORM(INTEL_I965GM), 200 .is_mobile = 1, .has_fbc = 1, 201 .has_overlay = 1, 202 .supports_tv = 1, 203 .hws_needs_physical = 1, 204 .has_snoop = false, 205 }; 206 207 static const struct intel_device_info intel_g45_info = { 208 GEN4_FEATURES, 209 PLATFORM(INTEL_G45), 210 .ring_mask = RENDER_RING | BSD_RING, 211 }; 212 213 static const struct intel_device_info intel_gm45_info = { 214 GEN4_FEATURES, 215 PLATFORM(INTEL_GM45), 216 .is_mobile = 1, .has_fbc = 1, 217 .supports_tv = 1, 218 .ring_mask = RENDER_RING | BSD_RING, 219 }; 220 221 #define GEN5_FEATURES \ 222 GEN(5), \ 223 .num_pipes = 2, \ 224 .has_hotplug = 1, \ 225 .ring_mask = RENDER_RING | BSD_RING, \ 226 .has_snoop = true, \ 227 .has_coherent_ggtt = true, \ 228 /* ilk does support rc6, but we do not implement [power] contexts */ \ 229 .has_rc6 = 0, \ 230 GEN_DEFAULT_PIPEOFFSETS, \ 231 GEN_DEFAULT_PAGE_SIZES, \ 232 CURSOR_OFFSETS 233 234 static const struct intel_device_info intel_ironlake_d_info = { 235 GEN5_FEATURES, 236 PLATFORM(INTEL_IRONLAKE), 237 }; 238 239 static const struct intel_device_info intel_ironlake_m_info = { 240 GEN5_FEATURES, 241 PLATFORM(INTEL_IRONLAKE), 242 .is_mobile = 1, .has_fbc = 1, 243 }; 244 245 #define GEN6_FEATURES \ 246 GEN(6), \ 247 .num_pipes = 2, \ 248 .has_hotplug = 1, \ 249 .has_fbc = 1, \ 250 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ 251 .has_coherent_ggtt = true, \ 252 .has_llc = 1, \ 253 .has_rc6 = 1, \ 254 .has_rc6p = 1, \ 255 .has_aliasing_ppgtt = 1, \ 256 GEN_DEFAULT_PIPEOFFSETS, \ 257 GEN_DEFAULT_PAGE_SIZES, \ 258 CURSOR_OFFSETS 259 260 #define SNB_D_PLATFORM \ 261 GEN6_FEATURES, \ 262 PLATFORM(INTEL_SANDYBRIDGE) 263 264 static const struct intel_device_info intel_sandybridge_d_gt1_info = { 265 SNB_D_PLATFORM, 266 .gt = 1, 267 }; 268 269 static const struct intel_device_info intel_sandybridge_d_gt2_info = { 270 SNB_D_PLATFORM, 271 .gt = 2, 272 }; 273 274 #define SNB_M_PLATFORM \ 275 GEN6_FEATURES, \ 276 PLATFORM(INTEL_SANDYBRIDGE), \ 277 .is_mobile = 1 278 279 280 static const struct intel_device_info intel_sandybridge_m_gt1_info = { 281 SNB_M_PLATFORM, 282 .gt = 1, 283 }; 284 285 static const struct intel_device_info intel_sandybridge_m_gt2_info = { 286 SNB_M_PLATFORM, 287 .gt = 2, 288 }; 289 290 #define GEN7_FEATURES \ 291 GEN(7), \ 292 .num_pipes = 3, \ 293 .has_hotplug = 1, \ 294 .has_fbc = 1, \ 295 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ 296 .has_coherent_ggtt = true, \ 297 .has_llc = 1, \ 298 .has_rc6 = 1, \ 299 .has_rc6p = 1, \ 300 .has_aliasing_ppgtt = 1, \ 301 .has_full_ppgtt = 1, \ 302 GEN_DEFAULT_PIPEOFFSETS, \ 303 GEN_DEFAULT_PAGE_SIZES, \ 304 IVB_CURSOR_OFFSETS 305 306 #define IVB_D_PLATFORM \ 307 GEN7_FEATURES, \ 308 PLATFORM(INTEL_IVYBRIDGE), \ 309 .has_l3_dpf = 1 310 311 static const struct intel_device_info intel_ivybridge_d_gt1_info = { 312 IVB_D_PLATFORM, 313 .gt = 1, 314 }; 315 316 static const struct intel_device_info intel_ivybridge_d_gt2_info = { 317 IVB_D_PLATFORM, 318 .gt = 2, 319 }; 320 321 #define IVB_M_PLATFORM \ 322 GEN7_FEATURES, \ 323 PLATFORM(INTEL_IVYBRIDGE), \ 324 .is_mobile = 1, \ 325 .has_l3_dpf = 1 326 327 static const struct intel_device_info intel_ivybridge_m_gt1_info = { 328 IVB_M_PLATFORM, 329 .gt = 1, 330 }; 331 332 static const struct intel_device_info intel_ivybridge_m_gt2_info = { 333 IVB_M_PLATFORM, 334 .gt = 2, 335 }; 336 337 static const struct intel_device_info intel_ivybridge_q_info = { 338 GEN7_FEATURES, 339 PLATFORM(INTEL_IVYBRIDGE), 340 .gt = 2, 341 .num_pipes = 0, /* legal, last one wins */ 342 .has_l3_dpf = 1, 343 }; 344 345 static const struct intel_device_info intel_valleyview_info = { 346 PLATFORM(INTEL_VALLEYVIEW), 347 GEN(7), 348 .is_lp = 1, 349 .num_pipes = 2, 350 .has_runtime_pm = 1, 351 .has_rc6 = 1, 352 .has_gmch_display = 1, 353 .has_hotplug = 1, 354 .has_aliasing_ppgtt = 1, 355 .has_full_ppgtt = 1, 356 .has_snoop = true, 357 .has_coherent_ggtt = false, 358 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, 359 .display_mmio_offset = VLV_DISPLAY_BASE, 360 GEN_DEFAULT_PAGE_SIZES, 361 GEN_DEFAULT_PIPEOFFSETS, 362 CURSOR_OFFSETS 363 }; 364 365 #define G75_FEATURES \ 366 GEN7_FEATURES, \ 367 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \ 368 .has_ddi = 1, \ 369 .has_fpga_dbg = 1, \ 370 .has_psr = 1, \ 371 .has_dp_mst = 1, \ 372 .has_rc6p = 0 /* RC6p removed-by HSW */, \ 373 .has_runtime_pm = 1 374 375 #define HSW_PLATFORM \ 376 G75_FEATURES, \ 377 PLATFORM(INTEL_HASWELL), \ 378 .has_l3_dpf = 1 379 380 static const struct intel_device_info intel_haswell_gt1_info = { 381 HSW_PLATFORM, 382 .gt = 1, 383 }; 384 385 static const struct intel_device_info intel_haswell_gt2_info = { 386 HSW_PLATFORM, 387 .gt = 2, 388 }; 389 390 static const struct intel_device_info intel_haswell_gt3_info = { 391 HSW_PLATFORM, 392 .gt = 3, 393 }; 394 395 #define GEN8_FEATURES \ 396 G75_FEATURES, \ 397 GEN(8), \ 398 BDW_COLORS, \ 399 .page_sizes = I915_GTT_PAGE_SIZE_4K | \ 400 I915_GTT_PAGE_SIZE_2M, \ 401 .has_logical_ring_contexts = 1, \ 402 .has_full_48bit_ppgtt = 1, \ 403 .has_64bit_reloc = 1, \ 404 .has_reset_engine = 1 405 406 #define BDW_PLATFORM \ 407 GEN8_FEATURES, \ 408 PLATFORM(INTEL_BROADWELL) 409 410 static const struct intel_device_info intel_broadwell_gt1_info = { 411 BDW_PLATFORM, 412 .gt = 1, 413 }; 414 415 static const struct intel_device_info intel_broadwell_gt2_info = { 416 BDW_PLATFORM, 417 .gt = 2, 418 }; 419 420 static const struct intel_device_info intel_broadwell_rsvd_info = { 421 BDW_PLATFORM, 422 .gt = 3, 423 /* According to the device ID those devices are GT3, they were 424 * previously treated as not GT3, keep it like that. 425 */ 426 }; 427 428 static const struct intel_device_info intel_broadwell_gt3_info = { 429 BDW_PLATFORM, 430 .gt = 3, 431 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 432 }; 433 434 static const struct intel_device_info intel_cherryview_info = { 435 PLATFORM(INTEL_CHERRYVIEW), 436 GEN(8), 437 .num_pipes = 3, 438 .has_hotplug = 1, 439 .is_lp = 1, 440 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, 441 .has_64bit_reloc = 1, 442 .has_runtime_pm = 1, 443 .has_rc6 = 1, 444 .has_logical_ring_contexts = 1, 445 .has_gmch_display = 1, 446 .has_aliasing_ppgtt = 1, 447 .has_full_ppgtt = 1, 448 .has_reset_engine = 1, 449 .has_snoop = true, 450 .has_coherent_ggtt = false, 451 .display_mmio_offset = VLV_DISPLAY_BASE, 452 GEN_DEFAULT_PAGE_SIZES, 453 GEN_CHV_PIPEOFFSETS, 454 CURSOR_OFFSETS, 455 CHV_COLORS, 456 }; 457 458 #define GEN9_DEFAULT_PAGE_SIZES \ 459 .page_sizes = I915_GTT_PAGE_SIZE_4K | \ 460 I915_GTT_PAGE_SIZE_64K | \ 461 I915_GTT_PAGE_SIZE_2M 462 463 #define GEN9_FEATURES \ 464 GEN8_FEATURES, \ 465 GEN(9), \ 466 GEN9_DEFAULT_PAGE_SIZES, \ 467 .has_logical_ring_preemption = 1, \ 468 .has_csr = 1, \ 469 .has_guc = 1, \ 470 .has_ipc = 1, \ 471 .ddb_size = 896 472 473 #define SKL_PLATFORM \ 474 GEN9_FEATURES, \ 475 PLATFORM(INTEL_SKYLAKE) 476 477 static const struct intel_device_info intel_skylake_gt1_info = { 478 SKL_PLATFORM, 479 .gt = 1, 480 }; 481 482 static const struct intel_device_info intel_skylake_gt2_info = { 483 SKL_PLATFORM, 484 .gt = 2, 485 }; 486 487 #define SKL_GT3_PLUS_PLATFORM \ 488 SKL_PLATFORM, \ 489 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING 490 491 492 static const struct intel_device_info intel_skylake_gt3_info = { 493 SKL_GT3_PLUS_PLATFORM, 494 .gt = 3, 495 }; 496 497 static const struct intel_device_info intel_skylake_gt4_info = { 498 SKL_GT3_PLUS_PLATFORM, 499 .gt = 4, 500 }; 501 502 #define GEN9_LP_FEATURES \ 503 GEN(9), \ 504 .is_lp = 1, \ 505 .has_hotplug = 1, \ 506 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \ 507 .num_pipes = 3, \ 508 .has_64bit_reloc = 1, \ 509 .has_ddi = 1, \ 510 .has_fpga_dbg = 1, \ 511 .has_fbc = 1, \ 512 .has_psr = 1, \ 513 .has_runtime_pm = 1, \ 514 .has_pooled_eu = 0, \ 515 .has_csr = 1, \ 516 .has_rc6 = 1, \ 517 .has_dp_mst = 1, \ 518 .has_logical_ring_contexts = 1, \ 519 .has_logical_ring_preemption = 1, \ 520 .has_guc = 1, \ 521 .has_aliasing_ppgtt = 1, \ 522 .has_full_ppgtt = 1, \ 523 .has_full_48bit_ppgtt = 1, \ 524 .has_reset_engine = 1, \ 525 .has_snoop = true, \ 526 .has_coherent_ggtt = false, \ 527 .has_ipc = 1, \ 528 GEN9_DEFAULT_PAGE_SIZES, \ 529 GEN_DEFAULT_PIPEOFFSETS, \ 530 IVB_CURSOR_OFFSETS, \ 531 BDW_COLORS 532 533 static const struct intel_device_info intel_broxton_info = { 534 GEN9_LP_FEATURES, 535 PLATFORM(INTEL_BROXTON), 536 .ddb_size = 512, 537 }; 538 539 static const struct intel_device_info intel_geminilake_info = { 540 GEN9_LP_FEATURES, 541 PLATFORM(INTEL_GEMINILAKE), 542 .ddb_size = 1024, 543 GLK_COLORS, 544 }; 545 546 #define KBL_PLATFORM \ 547 GEN9_FEATURES, \ 548 PLATFORM(INTEL_KABYLAKE) 549 550 static const struct intel_device_info intel_kabylake_gt1_info = { 551 KBL_PLATFORM, 552 .gt = 1, 553 }; 554 555 static const struct intel_device_info intel_kabylake_gt2_info = { 556 KBL_PLATFORM, 557 .gt = 2, 558 }; 559 560 static const struct intel_device_info intel_kabylake_gt3_info = { 561 KBL_PLATFORM, 562 .gt = 3, 563 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 564 }; 565 566 #define CFL_PLATFORM \ 567 GEN9_FEATURES, \ 568 PLATFORM(INTEL_COFFEELAKE) 569 570 static const struct intel_device_info intel_coffeelake_gt1_info = { 571 CFL_PLATFORM, 572 .gt = 1, 573 }; 574 575 static const struct intel_device_info intel_coffeelake_gt2_info = { 576 CFL_PLATFORM, 577 .gt = 2, 578 }; 579 580 static const struct intel_device_info intel_coffeelake_gt3_info = { 581 CFL_PLATFORM, 582 .gt = 3, 583 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 584 }; 585 586 #define GEN10_FEATURES \ 587 GEN9_FEATURES, \ 588 GEN(10), \ 589 .ddb_size = 1024, \ 590 .has_coherent_ggtt = false, \ 591 GLK_COLORS 592 593 static const struct intel_device_info intel_cannonlake_info = { 594 GEN10_FEATURES, 595 PLATFORM(INTEL_CANNONLAKE), 596 .gt = 2, 597 }; 598 599 #define GEN11_FEATURES \ 600 GEN10_FEATURES, \ 601 GEN(11), \ 602 .ddb_size = 2048, \ 603 .has_logical_ring_elsq = 1 604 605 static const struct intel_device_info intel_icelake_11_info = { 606 GEN11_FEATURES, 607 PLATFORM(INTEL_ICELAKE), 608 .is_alpha_support = 1, 609 .ring_mask = RENDER_RING | BLT_RING | VEBOX_RING | BSD_RING | BSD3_RING, 610 }; 611 612 #undef GEN 613 #undef PLATFORM 614 615 /* 616 * Make sure any device matches here are from most specific to most 617 * general. For example, since the Quanta match is based on the subsystem 618 * and subvendor IDs, we need it to come before the more general IVB 619 * PCI ID matches, otherwise we'll use the wrong info struct above. 620 */ 621 static const struct pci_device_id pciidlist[] = { 622 INTEL_I830_IDS(&intel_i830_info), 623 INTEL_I845G_IDS(&intel_i845g_info), 624 INTEL_I85X_IDS(&intel_i85x_info), 625 INTEL_I865G_IDS(&intel_i865g_info), 626 INTEL_I915G_IDS(&intel_i915g_info), 627 INTEL_I915GM_IDS(&intel_i915gm_info), 628 INTEL_I945G_IDS(&intel_i945g_info), 629 INTEL_I945GM_IDS(&intel_i945gm_info), 630 INTEL_I965G_IDS(&intel_i965g_info), 631 INTEL_G33_IDS(&intel_g33_info), 632 INTEL_I965GM_IDS(&intel_i965gm_info), 633 INTEL_GM45_IDS(&intel_gm45_info), 634 INTEL_G45_IDS(&intel_g45_info), 635 INTEL_PINEVIEW_IDS(&intel_pineview_info), 636 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), 637 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), 638 INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info), 639 INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info), 640 INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info), 641 INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info), 642 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ 643 INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info), 644 INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info), 645 INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info), 646 INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info), 647 INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info), 648 INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info), 649 INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info), 650 INTEL_VLV_IDS(&intel_valleyview_info), 651 INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info), 652 INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info), 653 INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info), 654 INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info), 655 INTEL_CHV_IDS(&intel_cherryview_info), 656 INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info), 657 INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info), 658 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), 659 INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info), 660 INTEL_BXT_IDS(&intel_broxton_info), 661 INTEL_GLK_IDS(&intel_geminilake_info), 662 INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info), 663 INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info), 664 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info), 665 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info), 666 INTEL_AML_GT2_IDS(&intel_kabylake_gt2_info), 667 INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info), 668 INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info), 669 INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info), 670 INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info), 671 INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info), 672 INTEL_WHL_U_GT1_IDS(&intel_coffeelake_gt1_info), 673 INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info), 674 INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info), 675 INTEL_CNL_IDS(&intel_cannonlake_info), 676 INTEL_ICL_11_IDS(&intel_icelake_11_info), 677 {0, 0, 0} 678 }; 679 MODULE_DEVICE_TABLE(pci, pciidlist); 680 681 static void i915_pci_remove(struct pci_dev *pdev) 682 { 683 struct drm_device *dev; 684 685 dev = pci_get_drvdata(pdev); 686 if (!dev) /* driver load aborted, nothing to cleanup */ 687 return; 688 689 i915_driver_unload(dev); 690 drm_dev_put(dev); 691 692 pci_set_drvdata(pdev, NULL); 693 } 694 695 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 696 { 697 struct intel_device_info *intel_info = 698 (struct intel_device_info *) ent->driver_data; 699 int err; 700 701 if (IS_ALPHA_SUPPORT(intel_info) && !i915_modparams.alpha_support) { 702 DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n" 703 "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n" 704 "to enable support in this kernel version, or check for kernel updates.\n"); 705 return -ENODEV; 706 } 707 708 /* Only bind to function 0 of the device. Early generations 709 * used function 1 as a placeholder for multi-head. This causes 710 * us confusion instead, especially on the systems where both 711 * functions have the same PCI-ID! 712 */ 713 if (PCI_FUNC(pdev->devfn)) 714 return -ENODEV; 715 716 /* 717 * apple-gmux is needed on dual GPU MacBook Pro 718 * to probe the panel if we're the inactive GPU. 719 */ 720 if (vga_switcheroo_client_probe_defer(pdev)) 721 return -EPROBE_DEFER; 722 723 err = i915_driver_load(pdev, ent); 724 if (err) 725 return err; 726 727 if (i915_inject_load_failure()) { 728 i915_pci_remove(pdev); 729 return -ENODEV; 730 } 731 732 err = i915_live_selftests(pdev); 733 if (err) { 734 i915_pci_remove(pdev); 735 return err > 0 ? -ENOTTY : err; 736 } 737 738 return 0; 739 } 740 741 static struct pci_driver i915_pci_driver = { 742 .name = DRIVER_NAME, 743 .id_table = pciidlist, 744 .probe = i915_pci_probe, 745 .remove = i915_pci_remove, 746 .driver.pm = &i915_pm_ops, 747 }; 748 749 static int __init i915_init(void) 750 { 751 bool use_kms = true; 752 int err; 753 754 err = i915_mock_selftests(); 755 if (err) 756 return err > 0 ? 0 : err; 757 758 /* 759 * Enable KMS by default, unless explicitly overriden by 760 * either the i915.modeset prarameter or by the 761 * vga_text_mode_force boot option. 762 */ 763 764 if (i915_modparams.modeset == 0) 765 use_kms = false; 766 767 if (vgacon_text_force() && i915_modparams.modeset == -1) 768 use_kms = false; 769 770 if (!use_kms) { 771 /* Silently fail loading to not upset userspace. */ 772 DRM_DEBUG_DRIVER("KMS disabled.\n"); 773 return 0; 774 } 775 776 return pci_register_driver(&i915_pci_driver); 777 } 778 779 static void __exit i915_exit(void) 780 { 781 if (!i915_pci_driver.driver.owner) 782 return; 783 784 pci_unregister_driver(&i915_pci_driver); 785 } 786 787 module_init(i915_init); 788 module_exit(i915_exit); 789 790 MODULE_AUTHOR("Tungsten Graphics, Inc."); 791 MODULE_AUTHOR("Intel Corporation"); 792 793 MODULE_DESCRIPTION(DRIVER_DESC); 794 MODULE_LICENSE("GPL and additional rights"); 795