1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/console.h> 26 #include <linux/vga_switcheroo.h> 27 28 #include <drm/drm_drv.h> 29 #include <drm/i915_pciids.h> 30 31 #include "display/intel_fbdev.h" 32 33 #include "i915_drv.h" 34 #include "i915_perf.h" 35 #include "i915_globals.h" 36 #include "i915_selftest.h" 37 38 #define PLATFORM(x) .platform = (x) 39 #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1) 40 41 #define I845_PIPE_OFFSETS \ 42 .pipe_offsets = { \ 43 [TRANSCODER_A] = PIPE_A_OFFSET, \ 44 }, \ 45 .trans_offsets = { \ 46 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 47 } 48 49 #define I9XX_PIPE_OFFSETS \ 50 .pipe_offsets = { \ 51 [TRANSCODER_A] = PIPE_A_OFFSET, \ 52 [TRANSCODER_B] = PIPE_B_OFFSET, \ 53 }, \ 54 .trans_offsets = { \ 55 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 56 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 57 } 58 59 #define IVB_PIPE_OFFSETS \ 60 .pipe_offsets = { \ 61 [TRANSCODER_A] = PIPE_A_OFFSET, \ 62 [TRANSCODER_B] = PIPE_B_OFFSET, \ 63 [TRANSCODER_C] = PIPE_C_OFFSET, \ 64 }, \ 65 .trans_offsets = { \ 66 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 67 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 68 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 69 } 70 71 #define HSW_PIPE_OFFSETS \ 72 .pipe_offsets = { \ 73 [TRANSCODER_A] = PIPE_A_OFFSET, \ 74 [TRANSCODER_B] = PIPE_B_OFFSET, \ 75 [TRANSCODER_C] = PIPE_C_OFFSET, \ 76 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 77 }, \ 78 .trans_offsets = { \ 79 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 80 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 81 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 82 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 83 } 84 85 #define CHV_PIPE_OFFSETS \ 86 .pipe_offsets = { \ 87 [TRANSCODER_A] = PIPE_A_OFFSET, \ 88 [TRANSCODER_B] = PIPE_B_OFFSET, \ 89 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \ 90 }, \ 91 .trans_offsets = { \ 92 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 93 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 94 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \ 95 } 96 97 #define I845_CURSOR_OFFSETS \ 98 .cursor_offsets = { \ 99 [PIPE_A] = CURSOR_A_OFFSET, \ 100 } 101 102 #define I9XX_CURSOR_OFFSETS \ 103 .cursor_offsets = { \ 104 [PIPE_A] = CURSOR_A_OFFSET, \ 105 [PIPE_B] = CURSOR_B_OFFSET, \ 106 } 107 108 #define CHV_CURSOR_OFFSETS \ 109 .cursor_offsets = { \ 110 [PIPE_A] = CURSOR_A_OFFSET, \ 111 [PIPE_B] = CURSOR_B_OFFSET, \ 112 [PIPE_C] = CHV_CURSOR_C_OFFSET, \ 113 } 114 115 #define IVB_CURSOR_OFFSETS \ 116 .cursor_offsets = { \ 117 [PIPE_A] = CURSOR_A_OFFSET, \ 118 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 119 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 120 } 121 122 #define TGL_CURSOR_OFFSETS \ 123 .cursor_offsets = { \ 124 [PIPE_A] = CURSOR_A_OFFSET, \ 125 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 126 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 127 [PIPE_D] = TGL_CURSOR_D_OFFSET, \ 128 } 129 130 #define I9XX_COLORS \ 131 .color = { .gamma_lut_size = 256 } 132 #define I965_COLORS \ 133 .color = { .gamma_lut_size = 129, \ 134 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 135 } 136 #define ILK_COLORS \ 137 .color = { .gamma_lut_size = 1024 } 138 #define IVB_COLORS \ 139 .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 } 140 #define CHV_COLORS \ 141 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \ 142 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 143 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 144 } 145 #define GLK_COLORS \ 146 .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \ 147 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 148 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 149 } 150 151 /* Keep in gen based order, and chronological order within a gen */ 152 153 #define GEN_DEFAULT_PAGE_SIZES \ 154 .page_sizes = I915_GTT_PAGE_SIZE_4K 155 156 #define GEN_DEFAULT_REGIONS \ 157 .memory_regions = REGION_SMEM | REGION_STOLEN 158 159 #define I830_FEATURES \ 160 GEN(2), \ 161 .is_mobile = 1, \ 162 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 163 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 164 .display.has_overlay = 1, \ 165 .display.cursor_needs_physical = 1, \ 166 .display.overlay_needs_physical = 1, \ 167 .display.has_gmch = 1, \ 168 .gpu_reset_clobbers_display = true, \ 169 .hws_needs_physical = 1, \ 170 .unfenced_needs_alignment = 1, \ 171 .platform_engine_mask = BIT(RCS0), \ 172 .has_snoop = true, \ 173 .has_coherent_ggtt = false, \ 174 .dma_mask_size = 32, \ 175 I9XX_PIPE_OFFSETS, \ 176 I9XX_CURSOR_OFFSETS, \ 177 I9XX_COLORS, \ 178 GEN_DEFAULT_PAGE_SIZES, \ 179 GEN_DEFAULT_REGIONS 180 181 #define I845_FEATURES \ 182 GEN(2), \ 183 .pipe_mask = BIT(PIPE_A), \ 184 .cpu_transcoder_mask = BIT(TRANSCODER_A), \ 185 .display.has_overlay = 1, \ 186 .display.overlay_needs_physical = 1, \ 187 .display.has_gmch = 1, \ 188 .gpu_reset_clobbers_display = true, \ 189 .hws_needs_physical = 1, \ 190 .unfenced_needs_alignment = 1, \ 191 .platform_engine_mask = BIT(RCS0), \ 192 .has_snoop = true, \ 193 .has_coherent_ggtt = false, \ 194 .dma_mask_size = 32, \ 195 I845_PIPE_OFFSETS, \ 196 I845_CURSOR_OFFSETS, \ 197 I9XX_COLORS, \ 198 GEN_DEFAULT_PAGE_SIZES, \ 199 GEN_DEFAULT_REGIONS 200 201 static const struct intel_device_info i830_info = { 202 I830_FEATURES, 203 PLATFORM(INTEL_I830), 204 }; 205 206 static const struct intel_device_info i845g_info = { 207 I845_FEATURES, 208 PLATFORM(INTEL_I845G), 209 }; 210 211 static const struct intel_device_info i85x_info = { 212 I830_FEATURES, 213 PLATFORM(INTEL_I85X), 214 .display.has_fbc = 1, 215 }; 216 217 static const struct intel_device_info i865g_info = { 218 I845_FEATURES, 219 PLATFORM(INTEL_I865G), 220 .display.has_fbc = 1, 221 }; 222 223 #define GEN3_FEATURES \ 224 GEN(3), \ 225 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 226 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 227 .display.has_gmch = 1, \ 228 .gpu_reset_clobbers_display = true, \ 229 .platform_engine_mask = BIT(RCS0), \ 230 .has_snoop = true, \ 231 .has_coherent_ggtt = true, \ 232 .dma_mask_size = 32, \ 233 I9XX_PIPE_OFFSETS, \ 234 I9XX_CURSOR_OFFSETS, \ 235 I9XX_COLORS, \ 236 GEN_DEFAULT_PAGE_SIZES, \ 237 GEN_DEFAULT_REGIONS 238 239 static const struct intel_device_info i915g_info = { 240 GEN3_FEATURES, 241 PLATFORM(INTEL_I915G), 242 .has_coherent_ggtt = false, 243 .display.cursor_needs_physical = 1, 244 .display.has_overlay = 1, 245 .display.overlay_needs_physical = 1, 246 .hws_needs_physical = 1, 247 .unfenced_needs_alignment = 1, 248 }; 249 250 static const struct intel_device_info i915gm_info = { 251 GEN3_FEATURES, 252 PLATFORM(INTEL_I915GM), 253 .is_mobile = 1, 254 .display.cursor_needs_physical = 1, 255 .display.has_overlay = 1, 256 .display.overlay_needs_physical = 1, 257 .display.supports_tv = 1, 258 .display.has_fbc = 1, 259 .hws_needs_physical = 1, 260 .unfenced_needs_alignment = 1, 261 }; 262 263 static const struct intel_device_info i945g_info = { 264 GEN3_FEATURES, 265 PLATFORM(INTEL_I945G), 266 .display.has_hotplug = 1, 267 .display.cursor_needs_physical = 1, 268 .display.has_overlay = 1, 269 .display.overlay_needs_physical = 1, 270 .hws_needs_physical = 1, 271 .unfenced_needs_alignment = 1, 272 }; 273 274 static const struct intel_device_info i945gm_info = { 275 GEN3_FEATURES, 276 PLATFORM(INTEL_I945GM), 277 .is_mobile = 1, 278 .display.has_hotplug = 1, 279 .display.cursor_needs_physical = 1, 280 .display.has_overlay = 1, 281 .display.overlay_needs_physical = 1, 282 .display.supports_tv = 1, 283 .display.has_fbc = 1, 284 .hws_needs_physical = 1, 285 .unfenced_needs_alignment = 1, 286 }; 287 288 static const struct intel_device_info g33_info = { 289 GEN3_FEATURES, 290 PLATFORM(INTEL_G33), 291 .display.has_hotplug = 1, 292 .display.has_overlay = 1, 293 .dma_mask_size = 36, 294 }; 295 296 static const struct intel_device_info pnv_g_info = { 297 GEN3_FEATURES, 298 PLATFORM(INTEL_PINEVIEW), 299 .display.has_hotplug = 1, 300 .display.has_overlay = 1, 301 .dma_mask_size = 36, 302 }; 303 304 static const struct intel_device_info pnv_m_info = { 305 GEN3_FEATURES, 306 PLATFORM(INTEL_PINEVIEW), 307 .is_mobile = 1, 308 .display.has_hotplug = 1, 309 .display.has_overlay = 1, 310 .dma_mask_size = 36, 311 }; 312 313 #define GEN4_FEATURES \ 314 GEN(4), \ 315 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 316 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 317 .display.has_hotplug = 1, \ 318 .display.has_gmch = 1, \ 319 .gpu_reset_clobbers_display = true, \ 320 .platform_engine_mask = BIT(RCS0), \ 321 .has_snoop = true, \ 322 .has_coherent_ggtt = true, \ 323 .dma_mask_size = 36, \ 324 I9XX_PIPE_OFFSETS, \ 325 I9XX_CURSOR_OFFSETS, \ 326 I965_COLORS, \ 327 GEN_DEFAULT_PAGE_SIZES, \ 328 GEN_DEFAULT_REGIONS 329 330 static const struct intel_device_info i965g_info = { 331 GEN4_FEATURES, 332 PLATFORM(INTEL_I965G), 333 .display.has_overlay = 1, 334 .hws_needs_physical = 1, 335 .has_snoop = false, 336 }; 337 338 static const struct intel_device_info i965gm_info = { 339 GEN4_FEATURES, 340 PLATFORM(INTEL_I965GM), 341 .is_mobile = 1, 342 .display.has_fbc = 1, 343 .display.has_overlay = 1, 344 .display.supports_tv = 1, 345 .hws_needs_physical = 1, 346 .has_snoop = false, 347 }; 348 349 static const struct intel_device_info g45_info = { 350 GEN4_FEATURES, 351 PLATFORM(INTEL_G45), 352 .platform_engine_mask = BIT(RCS0) | BIT(VCS0), 353 .gpu_reset_clobbers_display = false, 354 }; 355 356 static const struct intel_device_info gm45_info = { 357 GEN4_FEATURES, 358 PLATFORM(INTEL_GM45), 359 .is_mobile = 1, 360 .display.has_fbc = 1, 361 .display.supports_tv = 1, 362 .platform_engine_mask = BIT(RCS0) | BIT(VCS0), 363 .gpu_reset_clobbers_display = false, 364 }; 365 366 #define GEN5_FEATURES \ 367 GEN(5), \ 368 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 369 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 370 .display.has_hotplug = 1, \ 371 .platform_engine_mask = BIT(RCS0) | BIT(VCS0), \ 372 .has_snoop = true, \ 373 .has_coherent_ggtt = true, \ 374 /* ilk does support rc6, but we do not implement [power] contexts */ \ 375 .has_rc6 = 0, \ 376 .dma_mask_size = 36, \ 377 I9XX_PIPE_OFFSETS, \ 378 I9XX_CURSOR_OFFSETS, \ 379 ILK_COLORS, \ 380 GEN_DEFAULT_PAGE_SIZES, \ 381 GEN_DEFAULT_REGIONS 382 383 static const struct intel_device_info ilk_d_info = { 384 GEN5_FEATURES, 385 PLATFORM(INTEL_IRONLAKE), 386 }; 387 388 static const struct intel_device_info ilk_m_info = { 389 GEN5_FEATURES, 390 PLATFORM(INTEL_IRONLAKE), 391 .is_mobile = 1, 392 .display.has_fbc = 1, 393 }; 394 395 #define GEN6_FEATURES \ 396 GEN(6), \ 397 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 398 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 399 .display.has_hotplug = 1, \ 400 .display.has_fbc = 1, \ 401 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ 402 .has_coherent_ggtt = true, \ 403 .has_llc = 1, \ 404 .has_rc6 = 1, \ 405 .has_rc6p = 1, \ 406 .has_rps = true, \ 407 .dma_mask_size = 40, \ 408 .ppgtt_type = INTEL_PPGTT_ALIASING, \ 409 .ppgtt_size = 31, \ 410 I9XX_PIPE_OFFSETS, \ 411 I9XX_CURSOR_OFFSETS, \ 412 ILK_COLORS, \ 413 GEN_DEFAULT_PAGE_SIZES, \ 414 GEN_DEFAULT_REGIONS 415 416 #define SNB_D_PLATFORM \ 417 GEN6_FEATURES, \ 418 PLATFORM(INTEL_SANDYBRIDGE) 419 420 static const struct intel_device_info snb_d_gt1_info = { 421 SNB_D_PLATFORM, 422 .gt = 1, 423 }; 424 425 static const struct intel_device_info snb_d_gt2_info = { 426 SNB_D_PLATFORM, 427 .gt = 2, 428 }; 429 430 #define SNB_M_PLATFORM \ 431 GEN6_FEATURES, \ 432 PLATFORM(INTEL_SANDYBRIDGE), \ 433 .is_mobile = 1 434 435 436 static const struct intel_device_info snb_m_gt1_info = { 437 SNB_M_PLATFORM, 438 .gt = 1, 439 }; 440 441 static const struct intel_device_info snb_m_gt2_info = { 442 SNB_M_PLATFORM, 443 .gt = 2, 444 }; 445 446 #define GEN7_FEATURES \ 447 GEN(7), \ 448 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ 449 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \ 450 .display.has_hotplug = 1, \ 451 .display.has_fbc = 1, \ 452 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ 453 .has_coherent_ggtt = true, \ 454 .has_llc = 1, \ 455 .has_rc6 = 1, \ 456 .has_rc6p = 1, \ 457 .has_rps = true, \ 458 .dma_mask_size = 40, \ 459 .ppgtt_type = INTEL_PPGTT_ALIASING, \ 460 .ppgtt_size = 31, \ 461 IVB_PIPE_OFFSETS, \ 462 IVB_CURSOR_OFFSETS, \ 463 IVB_COLORS, \ 464 GEN_DEFAULT_PAGE_SIZES, \ 465 GEN_DEFAULT_REGIONS 466 467 #define IVB_D_PLATFORM \ 468 GEN7_FEATURES, \ 469 PLATFORM(INTEL_IVYBRIDGE), \ 470 .has_l3_dpf = 1 471 472 static const struct intel_device_info ivb_d_gt1_info = { 473 IVB_D_PLATFORM, 474 .gt = 1, 475 }; 476 477 static const struct intel_device_info ivb_d_gt2_info = { 478 IVB_D_PLATFORM, 479 .gt = 2, 480 }; 481 482 #define IVB_M_PLATFORM \ 483 GEN7_FEATURES, \ 484 PLATFORM(INTEL_IVYBRIDGE), \ 485 .is_mobile = 1, \ 486 .has_l3_dpf = 1 487 488 static const struct intel_device_info ivb_m_gt1_info = { 489 IVB_M_PLATFORM, 490 .gt = 1, 491 }; 492 493 static const struct intel_device_info ivb_m_gt2_info = { 494 IVB_M_PLATFORM, 495 .gt = 2, 496 }; 497 498 static const struct intel_device_info ivb_q_info = { 499 GEN7_FEATURES, 500 PLATFORM(INTEL_IVYBRIDGE), 501 .gt = 2, 502 .pipe_mask = 0, /* legal, last one wins */ 503 .cpu_transcoder_mask = 0, 504 .has_l3_dpf = 1, 505 }; 506 507 static const struct intel_device_info vlv_info = { 508 PLATFORM(INTEL_VALLEYVIEW), 509 GEN(7), 510 .is_lp = 1, 511 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), 512 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), 513 .has_runtime_pm = 1, 514 .has_rc6 = 1, 515 .has_rps = true, 516 .display.has_gmch = 1, 517 .display.has_hotplug = 1, 518 .dma_mask_size = 40, 519 .ppgtt_type = INTEL_PPGTT_ALIASING, 520 .ppgtt_size = 31, 521 .has_snoop = true, 522 .has_coherent_ggtt = false, 523 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), 524 .display_mmio_offset = VLV_DISPLAY_BASE, 525 I9XX_PIPE_OFFSETS, 526 I9XX_CURSOR_OFFSETS, 527 I965_COLORS, 528 GEN_DEFAULT_PAGE_SIZES, 529 GEN_DEFAULT_REGIONS, 530 }; 531 532 #define G75_FEATURES \ 533 GEN7_FEATURES, \ 534 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ 535 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 536 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \ 537 .display.has_ddi = 1, \ 538 .has_fpga_dbg = 1, \ 539 .display.has_psr = 1, \ 540 .display.has_psr_hw_tracking = 1, \ 541 .display.has_dp_mst = 1, \ 542 .has_rc6p = 0 /* RC6p removed-by HSW */, \ 543 HSW_PIPE_OFFSETS, \ 544 .has_runtime_pm = 1 545 546 #define HSW_PLATFORM \ 547 G75_FEATURES, \ 548 PLATFORM(INTEL_HASWELL), \ 549 .has_l3_dpf = 1 550 551 static const struct intel_device_info hsw_gt1_info = { 552 HSW_PLATFORM, 553 .gt = 1, 554 }; 555 556 static const struct intel_device_info hsw_gt2_info = { 557 HSW_PLATFORM, 558 .gt = 2, 559 }; 560 561 static const struct intel_device_info hsw_gt3_info = { 562 HSW_PLATFORM, 563 .gt = 3, 564 }; 565 566 #define GEN8_FEATURES \ 567 G75_FEATURES, \ 568 GEN(8), \ 569 .has_logical_ring_contexts = 1, \ 570 .dma_mask_size = 39, \ 571 .ppgtt_type = INTEL_PPGTT_FULL, \ 572 .ppgtt_size = 48, \ 573 .has_64bit_reloc = 1, \ 574 .has_reset_engine = 1 575 576 #define BDW_PLATFORM \ 577 GEN8_FEATURES, \ 578 PLATFORM(INTEL_BROADWELL) 579 580 static const struct intel_device_info bdw_gt1_info = { 581 BDW_PLATFORM, 582 .gt = 1, 583 }; 584 585 static const struct intel_device_info bdw_gt2_info = { 586 BDW_PLATFORM, 587 .gt = 2, 588 }; 589 590 static const struct intel_device_info bdw_rsvd_info = { 591 BDW_PLATFORM, 592 .gt = 3, 593 /* According to the device ID those devices are GT3, they were 594 * previously treated as not GT3, keep it like that. 595 */ 596 }; 597 598 static const struct intel_device_info bdw_gt3_info = { 599 BDW_PLATFORM, 600 .gt = 3, 601 .platform_engine_mask = 602 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 603 }; 604 605 static const struct intel_device_info chv_info = { 606 PLATFORM(INTEL_CHERRYVIEW), 607 GEN(8), 608 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 609 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), 610 .display.has_hotplug = 1, 611 .is_lp = 1, 612 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), 613 .has_64bit_reloc = 1, 614 .has_runtime_pm = 1, 615 .has_rc6 = 1, 616 .has_rps = true, 617 .has_logical_ring_contexts = 1, 618 .display.has_gmch = 1, 619 .dma_mask_size = 39, 620 .ppgtt_type = INTEL_PPGTT_FULL, 621 .ppgtt_size = 32, 622 .has_reset_engine = 1, 623 .has_snoop = true, 624 .has_coherent_ggtt = false, 625 .display_mmio_offset = VLV_DISPLAY_BASE, 626 CHV_PIPE_OFFSETS, 627 CHV_CURSOR_OFFSETS, 628 CHV_COLORS, 629 GEN_DEFAULT_PAGE_SIZES, 630 GEN_DEFAULT_REGIONS, 631 }; 632 633 #define GEN9_DEFAULT_PAGE_SIZES \ 634 .page_sizes = I915_GTT_PAGE_SIZE_4K | \ 635 I915_GTT_PAGE_SIZE_64K 636 637 #define GEN9_FEATURES \ 638 GEN8_FEATURES, \ 639 GEN(9), \ 640 GEN9_DEFAULT_PAGE_SIZES, \ 641 .has_logical_ring_preemption = 1, \ 642 .display.has_csr = 1, \ 643 .has_gt_uc = 1, \ 644 .display.has_hdcp = 1, \ 645 .display.has_ipc = 1, \ 646 .ddb_size = 896, \ 647 .num_supported_dbuf_slices = 1 648 649 #define SKL_PLATFORM \ 650 GEN9_FEATURES, \ 651 PLATFORM(INTEL_SKYLAKE) 652 653 static const struct intel_device_info skl_gt1_info = { 654 SKL_PLATFORM, 655 .gt = 1, 656 }; 657 658 static const struct intel_device_info skl_gt2_info = { 659 SKL_PLATFORM, 660 .gt = 2, 661 }; 662 663 #define SKL_GT3_PLUS_PLATFORM \ 664 SKL_PLATFORM, \ 665 .platform_engine_mask = \ 666 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1) 667 668 669 static const struct intel_device_info skl_gt3_info = { 670 SKL_GT3_PLUS_PLATFORM, 671 .gt = 3, 672 }; 673 674 static const struct intel_device_info skl_gt4_info = { 675 SKL_GT3_PLUS_PLATFORM, 676 .gt = 4, 677 }; 678 679 #define GEN9_LP_FEATURES \ 680 GEN(9), \ 681 .is_lp = 1, \ 682 .num_supported_dbuf_slices = 1, \ 683 .display.has_hotplug = 1, \ 684 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ 685 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ 686 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 687 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ 688 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \ 689 .has_64bit_reloc = 1, \ 690 .display.has_ddi = 1, \ 691 .has_fpga_dbg = 1, \ 692 .display.has_fbc = 1, \ 693 .display.has_hdcp = 1, \ 694 .display.has_psr = 1, \ 695 .display.has_psr_hw_tracking = 1, \ 696 .has_runtime_pm = 1, \ 697 .display.has_csr = 1, \ 698 .has_rc6 = 1, \ 699 .has_rps = true, \ 700 .display.has_dp_mst = 1, \ 701 .has_logical_ring_contexts = 1, \ 702 .has_logical_ring_preemption = 1, \ 703 .has_gt_uc = 1, \ 704 .dma_mask_size = 39, \ 705 .ppgtt_type = INTEL_PPGTT_FULL, \ 706 .ppgtt_size = 48, \ 707 .has_reset_engine = 1, \ 708 .has_snoop = true, \ 709 .has_coherent_ggtt = false, \ 710 .display.has_ipc = 1, \ 711 HSW_PIPE_OFFSETS, \ 712 IVB_CURSOR_OFFSETS, \ 713 IVB_COLORS, \ 714 GEN9_DEFAULT_PAGE_SIZES, \ 715 GEN_DEFAULT_REGIONS 716 717 static const struct intel_device_info bxt_info = { 718 GEN9_LP_FEATURES, 719 PLATFORM(INTEL_BROXTON), 720 .ddb_size = 512, 721 }; 722 723 static const struct intel_device_info glk_info = { 724 GEN9_LP_FEATURES, 725 PLATFORM(INTEL_GEMINILAKE), 726 .ddb_size = 1024, 727 GLK_COLORS, 728 }; 729 730 #define KBL_PLATFORM \ 731 GEN9_FEATURES, \ 732 PLATFORM(INTEL_KABYLAKE) 733 734 static const struct intel_device_info kbl_gt1_info = { 735 KBL_PLATFORM, 736 .gt = 1, 737 }; 738 739 static const struct intel_device_info kbl_gt2_info = { 740 KBL_PLATFORM, 741 .gt = 2, 742 }; 743 744 static const struct intel_device_info kbl_gt3_info = { 745 KBL_PLATFORM, 746 .gt = 3, 747 .platform_engine_mask = 748 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 749 }; 750 751 #define CFL_PLATFORM \ 752 GEN9_FEATURES, \ 753 PLATFORM(INTEL_COFFEELAKE) 754 755 static const struct intel_device_info cfl_gt1_info = { 756 CFL_PLATFORM, 757 .gt = 1, 758 }; 759 760 static const struct intel_device_info cfl_gt2_info = { 761 CFL_PLATFORM, 762 .gt = 2, 763 }; 764 765 static const struct intel_device_info cfl_gt3_info = { 766 CFL_PLATFORM, 767 .gt = 3, 768 .platform_engine_mask = 769 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 770 }; 771 772 #define CML_PLATFORM \ 773 GEN9_FEATURES, \ 774 PLATFORM(INTEL_COMETLAKE) 775 776 static const struct intel_device_info cml_gt1_info = { 777 CML_PLATFORM, 778 .gt = 1, 779 }; 780 781 static const struct intel_device_info cml_gt2_info = { 782 CML_PLATFORM, 783 .gt = 2, 784 }; 785 786 #define GEN10_FEATURES \ 787 GEN9_FEATURES, \ 788 GEN(10), \ 789 .ddb_size = 1024, \ 790 .display.has_dsc = 1, \ 791 .has_coherent_ggtt = false, \ 792 GLK_COLORS 793 794 static const struct intel_device_info cnl_info = { 795 GEN10_FEATURES, 796 PLATFORM(INTEL_CANNONLAKE), 797 .gt = 2, 798 }; 799 800 #define GEN11_DEFAULT_PAGE_SIZES \ 801 .page_sizes = I915_GTT_PAGE_SIZE_4K | \ 802 I915_GTT_PAGE_SIZE_64K | \ 803 I915_GTT_PAGE_SIZE_2M 804 805 #define GEN11_FEATURES \ 806 GEN10_FEATURES, \ 807 GEN11_DEFAULT_PAGE_SIZES, \ 808 .abox_mask = BIT(0), \ 809 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 810 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ 811 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ 812 .pipe_offsets = { \ 813 [TRANSCODER_A] = PIPE_A_OFFSET, \ 814 [TRANSCODER_B] = PIPE_B_OFFSET, \ 815 [TRANSCODER_C] = PIPE_C_OFFSET, \ 816 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 817 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 818 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 819 }, \ 820 .trans_offsets = { \ 821 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 822 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 823 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 824 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 825 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 826 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 827 }, \ 828 GEN(11), \ 829 .ddb_size = 2048, \ 830 .num_supported_dbuf_slices = 2, \ 831 .has_logical_ring_elsq = 1, \ 832 .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 } 833 834 static const struct intel_device_info icl_info = { 835 GEN11_FEATURES, 836 PLATFORM(INTEL_ICELAKE), 837 .platform_engine_mask = 838 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 839 }; 840 841 static const struct intel_device_info ehl_info = { 842 GEN11_FEATURES, 843 PLATFORM(INTEL_ELKHARTLAKE), 844 .require_force_probe = 1, 845 .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0), 846 .ppgtt_size = 36, 847 }; 848 849 #define GEN12_FEATURES \ 850 GEN11_FEATURES, \ 851 GEN(12), \ 852 .abox_mask = GENMASK(2, 1), \ 853 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ 854 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 855 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \ 856 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ 857 .pipe_offsets = { \ 858 [TRANSCODER_A] = PIPE_A_OFFSET, \ 859 [TRANSCODER_B] = PIPE_B_OFFSET, \ 860 [TRANSCODER_C] = PIPE_C_OFFSET, \ 861 [TRANSCODER_D] = PIPE_D_OFFSET, \ 862 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 863 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 864 }, \ 865 .trans_offsets = { \ 866 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 867 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 868 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 869 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ 870 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 871 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 872 }, \ 873 TGL_CURSOR_OFFSETS, \ 874 .has_global_mocs = 1, \ 875 .display.has_dsb = 1 876 877 static const struct intel_device_info tgl_info = { 878 GEN12_FEATURES, 879 PLATFORM(INTEL_TIGERLAKE), 880 .display.has_modular_fia = 1, 881 .platform_engine_mask = 882 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 883 }; 884 885 static const struct intel_device_info rkl_info = { 886 GEN12_FEATURES, 887 PLATFORM(INTEL_ROCKETLAKE), 888 .abox_mask = BIT(0), 889 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 890 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 891 BIT(TRANSCODER_C), 892 .require_force_probe = 1, 893 .display.has_psr_hw_tracking = 0, 894 .platform_engine_mask = 895 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0), 896 }; 897 898 #define GEN12_DGFX_FEATURES \ 899 GEN12_FEATURES, \ 900 .memory_regions = REGION_SMEM | REGION_LMEM, \ 901 .has_master_unit_irq = 1, \ 902 .is_dgfx = 1 903 904 static const struct intel_device_info dg1_info __maybe_unused = { 905 GEN12_DGFX_FEATURES, 906 PLATFORM(INTEL_DG1), 907 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 908 .require_force_probe = 1, 909 .platform_engine_mask = 910 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | 911 BIT(VCS0) | BIT(VCS2), 912 }; 913 914 #undef GEN 915 #undef PLATFORM 916 917 /* 918 * Make sure any device matches here are from most specific to most 919 * general. For example, since the Quanta match is based on the subsystem 920 * and subvendor IDs, we need it to come before the more general IVB 921 * PCI ID matches, otherwise we'll use the wrong info struct above. 922 */ 923 static const struct pci_device_id pciidlist[] = { 924 INTEL_I830_IDS(&i830_info), 925 INTEL_I845G_IDS(&i845g_info), 926 INTEL_I85X_IDS(&i85x_info), 927 INTEL_I865G_IDS(&i865g_info), 928 INTEL_I915G_IDS(&i915g_info), 929 INTEL_I915GM_IDS(&i915gm_info), 930 INTEL_I945G_IDS(&i945g_info), 931 INTEL_I945GM_IDS(&i945gm_info), 932 INTEL_I965G_IDS(&i965g_info), 933 INTEL_G33_IDS(&g33_info), 934 INTEL_I965GM_IDS(&i965gm_info), 935 INTEL_GM45_IDS(&gm45_info), 936 INTEL_G45_IDS(&g45_info), 937 INTEL_PINEVIEW_G_IDS(&pnv_g_info), 938 INTEL_PINEVIEW_M_IDS(&pnv_m_info), 939 INTEL_IRONLAKE_D_IDS(&ilk_d_info), 940 INTEL_IRONLAKE_M_IDS(&ilk_m_info), 941 INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info), 942 INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info), 943 INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info), 944 INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info), 945 INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */ 946 INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info), 947 INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info), 948 INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info), 949 INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info), 950 INTEL_HSW_GT1_IDS(&hsw_gt1_info), 951 INTEL_HSW_GT2_IDS(&hsw_gt2_info), 952 INTEL_HSW_GT3_IDS(&hsw_gt3_info), 953 INTEL_VLV_IDS(&vlv_info), 954 INTEL_BDW_GT1_IDS(&bdw_gt1_info), 955 INTEL_BDW_GT2_IDS(&bdw_gt2_info), 956 INTEL_BDW_GT3_IDS(&bdw_gt3_info), 957 INTEL_BDW_RSVD_IDS(&bdw_rsvd_info), 958 INTEL_CHV_IDS(&chv_info), 959 INTEL_SKL_GT1_IDS(&skl_gt1_info), 960 INTEL_SKL_GT2_IDS(&skl_gt2_info), 961 INTEL_SKL_GT3_IDS(&skl_gt3_info), 962 INTEL_SKL_GT4_IDS(&skl_gt4_info), 963 INTEL_BXT_IDS(&bxt_info), 964 INTEL_GLK_IDS(&glk_info), 965 INTEL_KBL_GT1_IDS(&kbl_gt1_info), 966 INTEL_KBL_GT2_IDS(&kbl_gt2_info), 967 INTEL_KBL_GT3_IDS(&kbl_gt3_info), 968 INTEL_KBL_GT4_IDS(&kbl_gt3_info), 969 INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info), 970 INTEL_CFL_S_GT1_IDS(&cfl_gt1_info), 971 INTEL_CFL_S_GT2_IDS(&cfl_gt2_info), 972 INTEL_CFL_H_GT1_IDS(&cfl_gt1_info), 973 INTEL_CFL_H_GT2_IDS(&cfl_gt2_info), 974 INTEL_CFL_U_GT2_IDS(&cfl_gt2_info), 975 INTEL_CFL_U_GT3_IDS(&cfl_gt3_info), 976 INTEL_WHL_U_GT1_IDS(&cfl_gt1_info), 977 INTEL_WHL_U_GT2_IDS(&cfl_gt2_info), 978 INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info), 979 INTEL_WHL_U_GT3_IDS(&cfl_gt3_info), 980 INTEL_CML_GT1_IDS(&cml_gt1_info), 981 INTEL_CML_GT2_IDS(&cml_gt2_info), 982 INTEL_CML_U_GT1_IDS(&cml_gt1_info), 983 INTEL_CML_U_GT2_IDS(&cml_gt2_info), 984 INTEL_CNL_IDS(&cnl_info), 985 INTEL_ICL_11_IDS(&icl_info), 986 INTEL_EHL_IDS(&ehl_info), 987 INTEL_TGL_12_IDS(&tgl_info), 988 INTEL_RKL_IDS(&rkl_info), 989 {0, 0, 0} 990 }; 991 MODULE_DEVICE_TABLE(pci, pciidlist); 992 993 static void i915_pci_remove(struct pci_dev *pdev) 994 { 995 struct drm_i915_private *i915; 996 997 i915 = pci_get_drvdata(pdev); 998 if (!i915) /* driver load aborted, nothing to cleanup */ 999 return; 1000 1001 i915_driver_remove(i915); 1002 pci_set_drvdata(pdev, NULL); 1003 } 1004 1005 /* is device_id present in comma separated list of ids */ 1006 static bool force_probe(u16 device_id, const char *devices) 1007 { 1008 char *s, *p, *tok; 1009 bool ret; 1010 1011 if (!devices || !*devices) 1012 return false; 1013 1014 /* match everything */ 1015 if (strcmp(devices, "*") == 0) 1016 return true; 1017 1018 s = kstrdup(devices, GFP_KERNEL); 1019 if (!s) 1020 return false; 1021 1022 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) { 1023 u16 val; 1024 1025 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) { 1026 ret = true; 1027 break; 1028 } 1029 } 1030 1031 kfree(s); 1032 1033 return ret; 1034 } 1035 1036 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1037 { 1038 struct intel_device_info *intel_info = 1039 (struct intel_device_info *) ent->driver_data; 1040 int err; 1041 1042 if (intel_info->require_force_probe && 1043 !force_probe(pdev->device, i915_modparams.force_probe)) { 1044 dev_info(&pdev->dev, 1045 "Your graphics device %04x is not properly supported by the driver in this\n" 1046 "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n" 1047 "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n" 1048 "or (recommended) check for kernel updates.\n", 1049 pdev->device, pdev->device, pdev->device); 1050 return -ENODEV; 1051 } 1052 1053 /* Only bind to function 0 of the device. Early generations 1054 * used function 1 as a placeholder for multi-head. This causes 1055 * us confusion instead, especially on the systems where both 1056 * functions have the same PCI-ID! 1057 */ 1058 if (PCI_FUNC(pdev->devfn)) 1059 return -ENODEV; 1060 1061 /* 1062 * apple-gmux is needed on dual GPU MacBook Pro 1063 * to probe the panel if we're the inactive GPU. 1064 */ 1065 if (vga_switcheroo_client_probe_defer(pdev)) 1066 return -EPROBE_DEFER; 1067 1068 err = i915_driver_probe(pdev, ent); 1069 if (err) 1070 return err; 1071 1072 if (i915_inject_probe_failure(pci_get_drvdata(pdev))) { 1073 i915_pci_remove(pdev); 1074 return -ENODEV; 1075 } 1076 1077 err = i915_live_selftests(pdev); 1078 if (err) { 1079 i915_pci_remove(pdev); 1080 return err > 0 ? -ENOTTY : err; 1081 } 1082 1083 err = i915_perf_selftests(pdev); 1084 if (err) { 1085 i915_pci_remove(pdev); 1086 return err > 0 ? -ENOTTY : err; 1087 } 1088 1089 return 0; 1090 } 1091 1092 static struct pci_driver i915_pci_driver = { 1093 .name = DRIVER_NAME, 1094 .id_table = pciidlist, 1095 .probe = i915_pci_probe, 1096 .remove = i915_pci_remove, 1097 .driver.pm = &i915_pm_ops, 1098 }; 1099 1100 static int __init i915_init(void) 1101 { 1102 bool use_kms = true; 1103 int err; 1104 1105 err = i915_globals_init(); 1106 if (err) 1107 return err; 1108 1109 err = i915_mock_selftests(); 1110 if (err) 1111 return err > 0 ? 0 : err; 1112 1113 /* 1114 * Enable KMS by default, unless explicitly overriden by 1115 * either the i915.modeset prarameter or by the 1116 * vga_text_mode_force boot option. 1117 */ 1118 1119 if (i915_modparams.modeset == 0) 1120 use_kms = false; 1121 1122 if (vgacon_text_force() && i915_modparams.modeset == -1) 1123 use_kms = false; 1124 1125 if (!use_kms) { 1126 /* Silently fail loading to not upset userspace. */ 1127 DRM_DEBUG_DRIVER("KMS disabled.\n"); 1128 return 0; 1129 } 1130 1131 err = pci_register_driver(&i915_pci_driver); 1132 if (err) 1133 return err; 1134 1135 i915_perf_sysctl_register(); 1136 return 0; 1137 } 1138 1139 static void __exit i915_exit(void) 1140 { 1141 if (!i915_pci_driver.driver.owner) 1142 return; 1143 1144 i915_perf_sysctl_unregister(); 1145 pci_unregister_driver(&i915_pci_driver); 1146 i915_globals_exit(); 1147 } 1148 1149 module_init(i915_init); 1150 module_exit(i915_exit); 1151 1152 MODULE_AUTHOR("Tungsten Graphics, Inc."); 1153 MODULE_AUTHOR("Intel Corporation"); 1154 1155 MODULE_DESCRIPTION(DRIVER_DESC); 1156 MODULE_LICENSE("GPL and additional rights"); 1157