1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <drm/drm_color_mgmt.h> 26 #include <drm/drm_drv.h> 27 #include <drm/i915_pciids.h> 28 29 #include "gt/intel_gt_regs.h" 30 #include "gt/intel_sa_media.h" 31 32 #include "i915_driver.h" 33 #include "i915_drv.h" 34 #include "i915_pci.h" 35 #include "i915_reg.h" 36 #include "intel_pci_config.h" 37 38 #define PLATFORM(x) .platform = (x) 39 #define GEN(x) \ 40 .__runtime.graphics.ip.ver = (x), \ 41 .__runtime.media.ip.ver = (x), \ 42 .__runtime.display.ip.ver = (x) 43 44 #define NO_DISPLAY .__runtime.pipe_mask = 0 45 46 #define I845_PIPE_OFFSETS \ 47 .display.pipe_offsets = { \ 48 [TRANSCODER_A] = PIPE_A_OFFSET, \ 49 }, \ 50 .display.trans_offsets = { \ 51 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 52 } 53 54 #define I9XX_PIPE_OFFSETS \ 55 .display.pipe_offsets = { \ 56 [TRANSCODER_A] = PIPE_A_OFFSET, \ 57 [TRANSCODER_B] = PIPE_B_OFFSET, \ 58 }, \ 59 .display.trans_offsets = { \ 60 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 61 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 62 } 63 64 #define IVB_PIPE_OFFSETS \ 65 .display.pipe_offsets = { \ 66 [TRANSCODER_A] = PIPE_A_OFFSET, \ 67 [TRANSCODER_B] = PIPE_B_OFFSET, \ 68 [TRANSCODER_C] = PIPE_C_OFFSET, \ 69 }, \ 70 .display.trans_offsets = { \ 71 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 72 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 73 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 74 } 75 76 #define HSW_PIPE_OFFSETS \ 77 .display.pipe_offsets = { \ 78 [TRANSCODER_A] = PIPE_A_OFFSET, \ 79 [TRANSCODER_B] = PIPE_B_OFFSET, \ 80 [TRANSCODER_C] = PIPE_C_OFFSET, \ 81 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 82 }, \ 83 .display.trans_offsets = { \ 84 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 85 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 86 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 87 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 88 } 89 90 #define CHV_PIPE_OFFSETS \ 91 .display.pipe_offsets = { \ 92 [TRANSCODER_A] = PIPE_A_OFFSET, \ 93 [TRANSCODER_B] = PIPE_B_OFFSET, \ 94 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \ 95 }, \ 96 .display.trans_offsets = { \ 97 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 98 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 99 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \ 100 } 101 102 #define I845_CURSOR_OFFSETS \ 103 .display.cursor_offsets = { \ 104 [PIPE_A] = CURSOR_A_OFFSET, \ 105 } 106 107 #define I9XX_CURSOR_OFFSETS \ 108 .display.cursor_offsets = { \ 109 [PIPE_A] = CURSOR_A_OFFSET, \ 110 [PIPE_B] = CURSOR_B_OFFSET, \ 111 } 112 113 #define CHV_CURSOR_OFFSETS \ 114 .display.cursor_offsets = { \ 115 [PIPE_A] = CURSOR_A_OFFSET, \ 116 [PIPE_B] = CURSOR_B_OFFSET, \ 117 [PIPE_C] = CHV_CURSOR_C_OFFSET, \ 118 } 119 120 #define IVB_CURSOR_OFFSETS \ 121 .display.cursor_offsets = { \ 122 [PIPE_A] = CURSOR_A_OFFSET, \ 123 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 124 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 125 } 126 127 #define TGL_CURSOR_OFFSETS \ 128 .display.cursor_offsets = { \ 129 [PIPE_A] = CURSOR_A_OFFSET, \ 130 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 131 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 132 [PIPE_D] = TGL_CURSOR_D_OFFSET, \ 133 } 134 135 #define I9XX_COLORS \ 136 .display.color = { .gamma_lut_size = 256 } 137 #define I965_COLORS \ 138 .display.color = { .gamma_lut_size = 129, \ 139 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 140 } 141 #define ILK_COLORS \ 142 .display.color = { .gamma_lut_size = 1024 } 143 #define IVB_COLORS \ 144 .display.color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 } 145 #define CHV_COLORS \ 146 .display.color = { \ 147 .degamma_lut_size = 65, .gamma_lut_size = 257, \ 148 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 149 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 150 } 151 #define GLK_COLORS \ 152 .display.color = { \ 153 .degamma_lut_size = 33, .gamma_lut_size = 1024, \ 154 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 155 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 156 } 157 #define ICL_COLORS \ 158 .display.color = { \ 159 .degamma_lut_size = 33, .gamma_lut_size = 262145, \ 160 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 161 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 162 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 163 } 164 165 /* Keep in gen based order, and chronological order within a gen */ 166 167 #define GEN_DEFAULT_PAGE_SIZES \ 168 .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K 169 170 #define GEN_DEFAULT_REGIONS \ 171 .__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_SMEM 172 173 #define I830_FEATURES \ 174 GEN(2), \ 175 .is_mobile = 1, \ 176 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 177 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 178 .display.has_overlay = 1, \ 179 .display.cursor_needs_physical = 1, \ 180 .display.overlay_needs_physical = 1, \ 181 .display.has_gmch = 1, \ 182 .gpu_reset_clobbers_display = true, \ 183 .has_3d_pipeline = 1, \ 184 .hws_needs_physical = 1, \ 185 .unfenced_needs_alignment = 1, \ 186 .__runtime.platform_engine_mask = BIT(RCS0), \ 187 .has_snoop = true, \ 188 .has_coherent_ggtt = false, \ 189 .dma_mask_size = 32, \ 190 I9XX_PIPE_OFFSETS, \ 191 I9XX_CURSOR_OFFSETS, \ 192 I9XX_COLORS, \ 193 GEN_DEFAULT_PAGE_SIZES, \ 194 GEN_DEFAULT_REGIONS 195 196 #define I845_FEATURES \ 197 GEN(2), \ 198 .__runtime.pipe_mask = BIT(PIPE_A), \ 199 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A), \ 200 .display.has_overlay = 1, \ 201 .display.overlay_needs_physical = 1, \ 202 .display.has_gmch = 1, \ 203 .has_3d_pipeline = 1, \ 204 .gpu_reset_clobbers_display = true, \ 205 .hws_needs_physical = 1, \ 206 .unfenced_needs_alignment = 1, \ 207 .__runtime.platform_engine_mask = BIT(RCS0), \ 208 .has_snoop = true, \ 209 .has_coherent_ggtt = false, \ 210 .dma_mask_size = 32, \ 211 I845_PIPE_OFFSETS, \ 212 I845_CURSOR_OFFSETS, \ 213 I9XX_COLORS, \ 214 GEN_DEFAULT_PAGE_SIZES, \ 215 GEN_DEFAULT_REGIONS 216 217 static const struct intel_device_info i830_info = { 218 I830_FEATURES, 219 PLATFORM(INTEL_I830), 220 }; 221 222 static const struct intel_device_info i845g_info = { 223 I845_FEATURES, 224 PLATFORM(INTEL_I845G), 225 }; 226 227 static const struct intel_device_info i85x_info = { 228 I830_FEATURES, 229 PLATFORM(INTEL_I85X), 230 .__runtime.fbc_mask = BIT(INTEL_FBC_A), 231 }; 232 233 static const struct intel_device_info i865g_info = { 234 I845_FEATURES, 235 PLATFORM(INTEL_I865G), 236 .__runtime.fbc_mask = BIT(INTEL_FBC_A), 237 }; 238 239 #define GEN3_FEATURES \ 240 GEN(3), \ 241 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 242 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 243 .display.has_gmch = 1, \ 244 .gpu_reset_clobbers_display = true, \ 245 .__runtime.platform_engine_mask = BIT(RCS0), \ 246 .has_3d_pipeline = 1, \ 247 .has_snoop = true, \ 248 .has_coherent_ggtt = true, \ 249 .dma_mask_size = 32, \ 250 I9XX_PIPE_OFFSETS, \ 251 I9XX_CURSOR_OFFSETS, \ 252 I9XX_COLORS, \ 253 GEN_DEFAULT_PAGE_SIZES, \ 254 GEN_DEFAULT_REGIONS 255 256 static const struct intel_device_info i915g_info = { 257 GEN3_FEATURES, 258 PLATFORM(INTEL_I915G), 259 .has_coherent_ggtt = false, 260 .display.cursor_needs_physical = 1, 261 .display.has_overlay = 1, 262 .display.overlay_needs_physical = 1, 263 .hws_needs_physical = 1, 264 .unfenced_needs_alignment = 1, 265 }; 266 267 static const struct intel_device_info i915gm_info = { 268 GEN3_FEATURES, 269 PLATFORM(INTEL_I915GM), 270 .is_mobile = 1, 271 .display.cursor_needs_physical = 1, 272 .display.has_overlay = 1, 273 .display.overlay_needs_physical = 1, 274 .display.supports_tv = 1, 275 .__runtime.fbc_mask = BIT(INTEL_FBC_A), 276 .hws_needs_physical = 1, 277 .unfenced_needs_alignment = 1, 278 }; 279 280 static const struct intel_device_info i945g_info = { 281 GEN3_FEATURES, 282 PLATFORM(INTEL_I945G), 283 .display.has_hotplug = 1, 284 .display.cursor_needs_physical = 1, 285 .display.has_overlay = 1, 286 .display.overlay_needs_physical = 1, 287 .hws_needs_physical = 1, 288 .unfenced_needs_alignment = 1, 289 }; 290 291 static const struct intel_device_info i945gm_info = { 292 GEN3_FEATURES, 293 PLATFORM(INTEL_I945GM), 294 .is_mobile = 1, 295 .display.has_hotplug = 1, 296 .display.cursor_needs_physical = 1, 297 .display.has_overlay = 1, 298 .display.overlay_needs_physical = 1, 299 .display.supports_tv = 1, 300 .__runtime.fbc_mask = BIT(INTEL_FBC_A), 301 .hws_needs_physical = 1, 302 .unfenced_needs_alignment = 1, 303 }; 304 305 static const struct intel_device_info g33_info = { 306 GEN3_FEATURES, 307 PLATFORM(INTEL_G33), 308 .display.has_hotplug = 1, 309 .display.has_overlay = 1, 310 .dma_mask_size = 36, 311 }; 312 313 static const struct intel_device_info pnv_g_info = { 314 GEN3_FEATURES, 315 PLATFORM(INTEL_PINEVIEW), 316 .display.has_hotplug = 1, 317 .display.has_overlay = 1, 318 .dma_mask_size = 36, 319 }; 320 321 static const struct intel_device_info pnv_m_info = { 322 GEN3_FEATURES, 323 PLATFORM(INTEL_PINEVIEW), 324 .is_mobile = 1, 325 .display.has_hotplug = 1, 326 .display.has_overlay = 1, 327 .dma_mask_size = 36, 328 }; 329 330 #define GEN4_FEATURES \ 331 GEN(4), \ 332 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 333 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 334 .display.has_hotplug = 1, \ 335 .display.has_gmch = 1, \ 336 .gpu_reset_clobbers_display = true, \ 337 .__runtime.platform_engine_mask = BIT(RCS0), \ 338 .has_3d_pipeline = 1, \ 339 .has_snoop = true, \ 340 .has_coherent_ggtt = true, \ 341 .dma_mask_size = 36, \ 342 I9XX_PIPE_OFFSETS, \ 343 I9XX_CURSOR_OFFSETS, \ 344 I965_COLORS, \ 345 GEN_DEFAULT_PAGE_SIZES, \ 346 GEN_DEFAULT_REGIONS 347 348 static const struct intel_device_info i965g_info = { 349 GEN4_FEATURES, 350 PLATFORM(INTEL_I965G), 351 .display.has_overlay = 1, 352 .hws_needs_physical = 1, 353 .has_snoop = false, 354 }; 355 356 static const struct intel_device_info i965gm_info = { 357 GEN4_FEATURES, 358 PLATFORM(INTEL_I965GM), 359 .is_mobile = 1, 360 .__runtime.fbc_mask = BIT(INTEL_FBC_A), 361 .display.has_overlay = 1, 362 .display.supports_tv = 1, 363 .hws_needs_physical = 1, 364 .has_snoop = false, 365 }; 366 367 static const struct intel_device_info g45_info = { 368 GEN4_FEATURES, 369 PLATFORM(INTEL_G45), 370 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0), 371 .gpu_reset_clobbers_display = false, 372 }; 373 374 static const struct intel_device_info gm45_info = { 375 GEN4_FEATURES, 376 PLATFORM(INTEL_GM45), 377 .is_mobile = 1, 378 .__runtime.fbc_mask = BIT(INTEL_FBC_A), 379 .display.supports_tv = 1, 380 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0), 381 .gpu_reset_clobbers_display = false, 382 }; 383 384 #define GEN5_FEATURES \ 385 GEN(5), \ 386 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 387 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 388 .display.has_hotplug = 1, \ 389 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0), \ 390 .has_3d_pipeline = 1, \ 391 .has_snoop = true, \ 392 .has_coherent_ggtt = true, \ 393 /* ilk does support rc6, but we do not implement [power] contexts */ \ 394 .has_rc6 = 0, \ 395 .dma_mask_size = 36, \ 396 I9XX_PIPE_OFFSETS, \ 397 I9XX_CURSOR_OFFSETS, \ 398 ILK_COLORS, \ 399 GEN_DEFAULT_PAGE_SIZES, \ 400 GEN_DEFAULT_REGIONS 401 402 static const struct intel_device_info ilk_d_info = { 403 GEN5_FEATURES, 404 PLATFORM(INTEL_IRONLAKE), 405 }; 406 407 static const struct intel_device_info ilk_m_info = { 408 GEN5_FEATURES, 409 PLATFORM(INTEL_IRONLAKE), 410 .is_mobile = 1, 411 .has_rps = true, 412 .__runtime.fbc_mask = BIT(INTEL_FBC_A), 413 }; 414 415 #define GEN6_FEATURES \ 416 GEN(6), \ 417 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 418 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 419 .display.has_hotplug = 1, \ 420 .__runtime.fbc_mask = BIT(INTEL_FBC_A), \ 421 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ 422 .has_3d_pipeline = 1, \ 423 .has_coherent_ggtt = true, \ 424 .has_llc = 1, \ 425 .has_rc6 = 1, \ 426 .has_rc6p = 1, \ 427 .has_rps = true, \ 428 .dma_mask_size = 40, \ 429 .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \ 430 .__runtime.ppgtt_size = 31, \ 431 I9XX_PIPE_OFFSETS, \ 432 I9XX_CURSOR_OFFSETS, \ 433 ILK_COLORS, \ 434 GEN_DEFAULT_PAGE_SIZES, \ 435 GEN_DEFAULT_REGIONS 436 437 #define SNB_D_PLATFORM \ 438 GEN6_FEATURES, \ 439 PLATFORM(INTEL_SANDYBRIDGE) 440 441 static const struct intel_device_info snb_d_gt1_info = { 442 SNB_D_PLATFORM, 443 .gt = 1, 444 }; 445 446 static const struct intel_device_info snb_d_gt2_info = { 447 SNB_D_PLATFORM, 448 .gt = 2, 449 }; 450 451 #define SNB_M_PLATFORM \ 452 GEN6_FEATURES, \ 453 PLATFORM(INTEL_SANDYBRIDGE), \ 454 .is_mobile = 1 455 456 457 static const struct intel_device_info snb_m_gt1_info = { 458 SNB_M_PLATFORM, 459 .gt = 1, 460 }; 461 462 static const struct intel_device_info snb_m_gt2_info = { 463 SNB_M_PLATFORM, 464 .gt = 2, 465 }; 466 467 #define GEN7_FEATURES \ 468 GEN(7), \ 469 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ 470 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \ 471 .display.has_hotplug = 1, \ 472 .__runtime.fbc_mask = BIT(INTEL_FBC_A), \ 473 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ 474 .has_3d_pipeline = 1, \ 475 .has_coherent_ggtt = true, \ 476 .has_llc = 1, \ 477 .has_rc6 = 1, \ 478 .has_rc6p = 1, \ 479 .has_reset_engine = true, \ 480 .has_rps = true, \ 481 .dma_mask_size = 40, \ 482 .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \ 483 .__runtime.ppgtt_size = 31, \ 484 IVB_PIPE_OFFSETS, \ 485 IVB_CURSOR_OFFSETS, \ 486 IVB_COLORS, \ 487 GEN_DEFAULT_PAGE_SIZES, \ 488 GEN_DEFAULT_REGIONS 489 490 #define IVB_D_PLATFORM \ 491 GEN7_FEATURES, \ 492 PLATFORM(INTEL_IVYBRIDGE), \ 493 .has_l3_dpf = 1 494 495 static const struct intel_device_info ivb_d_gt1_info = { 496 IVB_D_PLATFORM, 497 .gt = 1, 498 }; 499 500 static const struct intel_device_info ivb_d_gt2_info = { 501 IVB_D_PLATFORM, 502 .gt = 2, 503 }; 504 505 #define IVB_M_PLATFORM \ 506 GEN7_FEATURES, \ 507 PLATFORM(INTEL_IVYBRIDGE), \ 508 .is_mobile = 1, \ 509 .has_l3_dpf = 1 510 511 static const struct intel_device_info ivb_m_gt1_info = { 512 IVB_M_PLATFORM, 513 .gt = 1, 514 }; 515 516 static const struct intel_device_info ivb_m_gt2_info = { 517 IVB_M_PLATFORM, 518 .gt = 2, 519 }; 520 521 static const struct intel_device_info ivb_q_info = { 522 GEN7_FEATURES, 523 PLATFORM(INTEL_IVYBRIDGE), 524 NO_DISPLAY, 525 .gt = 2, 526 .has_l3_dpf = 1, 527 }; 528 529 static const struct intel_device_info vlv_info = { 530 PLATFORM(INTEL_VALLEYVIEW), 531 GEN(7), 532 .is_lp = 1, 533 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), 534 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), 535 .has_runtime_pm = 1, 536 .has_rc6 = 1, 537 .has_reset_engine = true, 538 .has_rps = true, 539 .display.has_gmch = 1, 540 .display.has_hotplug = 1, 541 .dma_mask_size = 40, 542 .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, 543 .__runtime.ppgtt_size = 31, 544 .has_snoop = true, 545 .has_coherent_ggtt = false, 546 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), 547 .display.mmio_offset = VLV_DISPLAY_BASE, 548 I9XX_PIPE_OFFSETS, 549 I9XX_CURSOR_OFFSETS, 550 I965_COLORS, 551 GEN_DEFAULT_PAGE_SIZES, 552 GEN_DEFAULT_REGIONS, 553 }; 554 555 #define G75_FEATURES \ 556 GEN7_FEATURES, \ 557 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ 558 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 559 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \ 560 .display.has_ddi = 1, \ 561 .display.has_fpga_dbg = 1, \ 562 .display.has_dp_mst = 1, \ 563 .has_rc6p = 0 /* RC6p removed-by HSW */, \ 564 HSW_PIPE_OFFSETS, \ 565 .has_runtime_pm = 1 566 567 #define HSW_PLATFORM \ 568 G75_FEATURES, \ 569 PLATFORM(INTEL_HASWELL), \ 570 .has_l3_dpf = 1 571 572 static const struct intel_device_info hsw_gt1_info = { 573 HSW_PLATFORM, 574 .gt = 1, 575 }; 576 577 static const struct intel_device_info hsw_gt2_info = { 578 HSW_PLATFORM, 579 .gt = 2, 580 }; 581 582 static const struct intel_device_info hsw_gt3_info = { 583 HSW_PLATFORM, 584 .gt = 3, 585 }; 586 587 #define GEN8_FEATURES \ 588 G75_FEATURES, \ 589 GEN(8), \ 590 .has_logical_ring_contexts = 1, \ 591 .dma_mask_size = 39, \ 592 .__runtime.ppgtt_type = INTEL_PPGTT_FULL, \ 593 .__runtime.ppgtt_size = 48, \ 594 .has_64bit_reloc = 1 595 596 #define BDW_PLATFORM \ 597 GEN8_FEATURES, \ 598 PLATFORM(INTEL_BROADWELL) 599 600 static const struct intel_device_info bdw_gt1_info = { 601 BDW_PLATFORM, 602 .gt = 1, 603 }; 604 605 static const struct intel_device_info bdw_gt2_info = { 606 BDW_PLATFORM, 607 .gt = 2, 608 }; 609 610 static const struct intel_device_info bdw_rsvd_info = { 611 BDW_PLATFORM, 612 .gt = 3, 613 /* According to the device ID those devices are GT3, they were 614 * previously treated as not GT3, keep it like that. 615 */ 616 }; 617 618 static const struct intel_device_info bdw_gt3_info = { 619 BDW_PLATFORM, 620 .gt = 3, 621 .__runtime.platform_engine_mask = 622 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 623 }; 624 625 static const struct intel_device_info chv_info = { 626 PLATFORM(INTEL_CHERRYVIEW), 627 GEN(8), 628 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 629 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), 630 .display.has_hotplug = 1, 631 .is_lp = 1, 632 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), 633 .has_64bit_reloc = 1, 634 .has_runtime_pm = 1, 635 .has_rc6 = 1, 636 .has_rps = true, 637 .has_logical_ring_contexts = 1, 638 .display.has_gmch = 1, 639 .dma_mask_size = 39, 640 .__runtime.ppgtt_type = INTEL_PPGTT_FULL, 641 .__runtime.ppgtt_size = 32, 642 .has_reset_engine = 1, 643 .has_snoop = true, 644 .has_coherent_ggtt = false, 645 .display.mmio_offset = VLV_DISPLAY_BASE, 646 CHV_PIPE_OFFSETS, 647 CHV_CURSOR_OFFSETS, 648 CHV_COLORS, 649 GEN_DEFAULT_PAGE_SIZES, 650 GEN_DEFAULT_REGIONS, 651 }; 652 653 #define GEN9_DEFAULT_PAGE_SIZES \ 654 .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \ 655 I915_GTT_PAGE_SIZE_64K 656 657 #define GEN9_FEATURES \ 658 GEN8_FEATURES, \ 659 GEN(9), \ 660 GEN9_DEFAULT_PAGE_SIZES, \ 661 .__runtime.has_dmc = 1, \ 662 .has_gt_uc = 1, \ 663 .__runtime.has_hdcp = 1, \ 664 .display.has_ipc = 1, \ 665 .display.has_psr = 1, \ 666 .display.has_psr_hw_tracking = 1, \ 667 .display.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \ 668 .display.dbuf.slice_mask = BIT(DBUF_S1) 669 670 #define SKL_PLATFORM \ 671 GEN9_FEATURES, \ 672 PLATFORM(INTEL_SKYLAKE) 673 674 static const struct intel_device_info skl_gt1_info = { 675 SKL_PLATFORM, 676 .gt = 1, 677 }; 678 679 static const struct intel_device_info skl_gt2_info = { 680 SKL_PLATFORM, 681 .gt = 2, 682 }; 683 684 #define SKL_GT3_PLUS_PLATFORM \ 685 SKL_PLATFORM, \ 686 .__runtime.platform_engine_mask = \ 687 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1) 688 689 690 static const struct intel_device_info skl_gt3_info = { 691 SKL_GT3_PLUS_PLATFORM, 692 .gt = 3, 693 }; 694 695 static const struct intel_device_info skl_gt4_info = { 696 SKL_GT3_PLUS_PLATFORM, 697 .gt = 4, 698 }; 699 700 #define GEN9_LP_FEATURES \ 701 GEN(9), \ 702 .is_lp = 1, \ 703 .display.dbuf.slice_mask = BIT(DBUF_S1), \ 704 .display.has_hotplug = 1, \ 705 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ 706 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ 707 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 708 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ 709 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \ 710 .has_3d_pipeline = 1, \ 711 .has_64bit_reloc = 1, \ 712 .display.has_ddi = 1, \ 713 .display.has_fpga_dbg = 1, \ 714 .__runtime.fbc_mask = BIT(INTEL_FBC_A), \ 715 .__runtime.has_hdcp = 1, \ 716 .display.has_psr = 1, \ 717 .display.has_psr_hw_tracking = 1, \ 718 .has_runtime_pm = 1, \ 719 .__runtime.has_dmc = 1, \ 720 .has_rc6 = 1, \ 721 .has_rps = true, \ 722 .display.has_dp_mst = 1, \ 723 .has_logical_ring_contexts = 1, \ 724 .has_gt_uc = 1, \ 725 .dma_mask_size = 39, \ 726 .__runtime.ppgtt_type = INTEL_PPGTT_FULL, \ 727 .__runtime.ppgtt_size = 48, \ 728 .has_reset_engine = 1, \ 729 .has_snoop = true, \ 730 .has_coherent_ggtt = false, \ 731 .display.has_ipc = 1, \ 732 HSW_PIPE_OFFSETS, \ 733 IVB_CURSOR_OFFSETS, \ 734 IVB_COLORS, \ 735 GEN9_DEFAULT_PAGE_SIZES, \ 736 GEN_DEFAULT_REGIONS 737 738 static const struct intel_device_info bxt_info = { 739 GEN9_LP_FEATURES, 740 PLATFORM(INTEL_BROXTON), 741 .display.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */ 742 }; 743 744 static const struct intel_device_info glk_info = { 745 GEN9_LP_FEATURES, 746 PLATFORM(INTEL_GEMINILAKE), 747 .__runtime.display.ip.ver = 10, 748 .display.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ 749 GLK_COLORS, 750 }; 751 752 #define KBL_PLATFORM \ 753 GEN9_FEATURES, \ 754 PLATFORM(INTEL_KABYLAKE) 755 756 static const struct intel_device_info kbl_gt1_info = { 757 KBL_PLATFORM, 758 .gt = 1, 759 }; 760 761 static const struct intel_device_info kbl_gt2_info = { 762 KBL_PLATFORM, 763 .gt = 2, 764 }; 765 766 static const struct intel_device_info kbl_gt3_info = { 767 KBL_PLATFORM, 768 .gt = 3, 769 .__runtime.platform_engine_mask = 770 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 771 }; 772 773 #define CFL_PLATFORM \ 774 GEN9_FEATURES, \ 775 PLATFORM(INTEL_COFFEELAKE) 776 777 static const struct intel_device_info cfl_gt1_info = { 778 CFL_PLATFORM, 779 .gt = 1, 780 }; 781 782 static const struct intel_device_info cfl_gt2_info = { 783 CFL_PLATFORM, 784 .gt = 2, 785 }; 786 787 static const struct intel_device_info cfl_gt3_info = { 788 CFL_PLATFORM, 789 .gt = 3, 790 .__runtime.platform_engine_mask = 791 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 792 }; 793 794 #define CML_PLATFORM \ 795 GEN9_FEATURES, \ 796 PLATFORM(INTEL_COMETLAKE) 797 798 static const struct intel_device_info cml_gt1_info = { 799 CML_PLATFORM, 800 .gt = 1, 801 }; 802 803 static const struct intel_device_info cml_gt2_info = { 804 CML_PLATFORM, 805 .gt = 2, 806 }; 807 808 #define GEN11_DEFAULT_PAGE_SIZES \ 809 .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \ 810 I915_GTT_PAGE_SIZE_64K | \ 811 I915_GTT_PAGE_SIZE_2M 812 813 #define GEN11_FEATURES \ 814 GEN9_FEATURES, \ 815 GEN11_DEFAULT_PAGE_SIZES, \ 816 .display.abox_mask = BIT(0), \ 817 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 818 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ 819 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ 820 .display.pipe_offsets = { \ 821 [TRANSCODER_A] = PIPE_A_OFFSET, \ 822 [TRANSCODER_B] = PIPE_B_OFFSET, \ 823 [TRANSCODER_C] = PIPE_C_OFFSET, \ 824 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 825 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 826 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 827 }, \ 828 .display.trans_offsets = { \ 829 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 830 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 831 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 832 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 833 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 834 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 835 }, \ 836 GEN(11), \ 837 ICL_COLORS, \ 838 .display.dbuf.size = 2048, \ 839 .display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \ 840 .__runtime.has_dsc = 1, \ 841 .has_coherent_ggtt = false, \ 842 .has_logical_ring_elsq = 1 843 844 static const struct intel_device_info icl_info = { 845 GEN11_FEATURES, 846 PLATFORM(INTEL_ICELAKE), 847 .__runtime.platform_engine_mask = 848 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 849 }; 850 851 static const struct intel_device_info ehl_info = { 852 GEN11_FEATURES, 853 PLATFORM(INTEL_ELKHARTLAKE), 854 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0), 855 .__runtime.ppgtt_size = 36, 856 }; 857 858 static const struct intel_device_info jsl_info = { 859 GEN11_FEATURES, 860 PLATFORM(INTEL_JASPERLAKE), 861 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0), 862 .__runtime.ppgtt_size = 36, 863 }; 864 865 #define GEN12_FEATURES \ 866 GEN11_FEATURES, \ 867 GEN(12), \ 868 .display.abox_mask = GENMASK(2, 1), \ 869 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ 870 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 871 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \ 872 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ 873 .display.pipe_offsets = { \ 874 [TRANSCODER_A] = PIPE_A_OFFSET, \ 875 [TRANSCODER_B] = PIPE_B_OFFSET, \ 876 [TRANSCODER_C] = PIPE_C_OFFSET, \ 877 [TRANSCODER_D] = PIPE_D_OFFSET, \ 878 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 879 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 880 }, \ 881 .display.trans_offsets = { \ 882 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 883 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 884 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 885 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ 886 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 887 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 888 }, \ 889 TGL_CURSOR_OFFSETS, \ 890 .has_global_mocs = 1, \ 891 .has_pxp = 1, \ 892 .display.has_dsb = 0 /* FIXME: LUT load is broken with DSB */ 893 894 static const struct intel_device_info tgl_info = { 895 GEN12_FEATURES, 896 PLATFORM(INTEL_TIGERLAKE), 897 .display.has_modular_fia = 1, 898 .__runtime.platform_engine_mask = 899 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 900 }; 901 902 static const struct intel_device_info rkl_info = { 903 GEN12_FEATURES, 904 PLATFORM(INTEL_ROCKETLAKE), 905 .display.abox_mask = BIT(0), 906 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 907 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 908 BIT(TRANSCODER_C), 909 .display.has_hti = 1, 910 .display.has_psr_hw_tracking = 0, 911 .__runtime.platform_engine_mask = 912 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0), 913 }; 914 915 #define DGFX_FEATURES \ 916 .__runtime.memory_regions = REGION_SMEM | REGION_LMEM | REGION_STOLEN_LMEM, \ 917 .has_llc = 0, \ 918 .has_pxp = 0, \ 919 .has_snoop = 1, \ 920 .is_dgfx = 1, \ 921 .has_heci_gscfi = 1 922 923 static const struct intel_device_info dg1_info = { 924 GEN12_FEATURES, 925 DGFX_FEATURES, 926 .__runtime.graphics.ip.rel = 10, 927 PLATFORM(INTEL_DG1), 928 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 929 .require_force_probe = 1, 930 .__runtime.platform_engine_mask = 931 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | 932 BIT(VCS0) | BIT(VCS2), 933 /* Wa_16011227922 */ 934 .__runtime.ppgtt_size = 47, 935 }; 936 937 static const struct intel_device_info adl_s_info = { 938 GEN12_FEATURES, 939 PLATFORM(INTEL_ALDERLAKE_S), 940 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 941 .display.has_hti = 1, 942 .display.has_psr_hw_tracking = 0, 943 .__runtime.platform_engine_mask = 944 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 945 .dma_mask_size = 39, 946 }; 947 948 #define XE_LPD_FEATURES \ 949 .display.abox_mask = GENMASK(1, 0), \ 950 .display.color = { \ 951 .degamma_lut_size = 128, .gamma_lut_size = 1024, \ 952 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 953 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 954 }, \ 955 .display.dbuf.size = 4096, \ 956 .display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \ 957 BIT(DBUF_S4), \ 958 .display.has_ddi = 1, \ 959 .__runtime.has_dmc = 1, \ 960 .display.has_dp_mst = 1, \ 961 .display.has_dsb = 1, \ 962 .__runtime.has_dsc = 1, \ 963 .__runtime.fbc_mask = BIT(INTEL_FBC_A), \ 964 .display.has_fpga_dbg = 1, \ 965 .__runtime.has_hdcp = 1, \ 966 .display.has_hotplug = 1, \ 967 .display.has_ipc = 1, \ 968 .display.has_psr = 1, \ 969 .__runtime.display.ip.ver = 13, \ 970 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ 971 .display.pipe_offsets = { \ 972 [TRANSCODER_A] = PIPE_A_OFFSET, \ 973 [TRANSCODER_B] = PIPE_B_OFFSET, \ 974 [TRANSCODER_C] = PIPE_C_OFFSET, \ 975 [TRANSCODER_D] = PIPE_D_OFFSET, \ 976 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 977 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 978 }, \ 979 .display.trans_offsets = { \ 980 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 981 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 982 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 983 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ 984 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 985 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 986 }, \ 987 TGL_CURSOR_OFFSETS 988 989 static const struct intel_device_info adl_p_info = { 990 GEN12_FEATURES, 991 XE_LPD_FEATURES, 992 PLATFORM(INTEL_ALDERLAKE_P), 993 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 994 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | 995 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), 996 .display.has_cdclk_crawl = 1, 997 .display.has_modular_fia = 1, 998 .display.has_psr_hw_tracking = 0, 999 .__runtime.platform_engine_mask = 1000 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 1001 .__runtime.ppgtt_size = 48, 1002 .dma_mask_size = 39, 1003 }; 1004 1005 #undef GEN 1006 1007 #define XE_HP_PAGE_SIZES \ 1008 .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \ 1009 I915_GTT_PAGE_SIZE_64K | \ 1010 I915_GTT_PAGE_SIZE_2M 1011 1012 #define XE_HP_FEATURES \ 1013 .__runtime.graphics.ip.ver = 12, \ 1014 .__runtime.graphics.ip.rel = 50, \ 1015 XE_HP_PAGE_SIZES, \ 1016 .dma_mask_size = 46, \ 1017 .has_3d_pipeline = 1, \ 1018 .has_64bit_reloc = 1, \ 1019 .has_flat_ccs = 1, \ 1020 .has_global_mocs = 1, \ 1021 .has_gt_uc = 1, \ 1022 .has_llc = 1, \ 1023 .has_logical_ring_contexts = 1, \ 1024 .has_logical_ring_elsq = 1, \ 1025 .has_mslice_steering = 1, \ 1026 .has_rc6 = 1, \ 1027 .has_reset_engine = 1, \ 1028 .has_rps = 1, \ 1029 .has_runtime_pm = 1, \ 1030 .__runtime.ppgtt_size = 48, \ 1031 .__runtime.ppgtt_type = INTEL_PPGTT_FULL 1032 1033 #define XE_HPM_FEATURES \ 1034 .__runtime.media.ip.ver = 12, \ 1035 .__runtime.media.ip.rel = 50 1036 1037 __maybe_unused 1038 static const struct intel_device_info xehpsdv_info = { 1039 XE_HP_FEATURES, 1040 XE_HPM_FEATURES, 1041 DGFX_FEATURES, 1042 PLATFORM(INTEL_XEHPSDV), 1043 NO_DISPLAY, 1044 .has_64k_pages = 1, 1045 .needs_compact_pt = 1, 1046 .has_media_ratio_mode = 1, 1047 .__runtime.platform_engine_mask = 1048 BIT(RCS0) | BIT(BCS0) | 1049 BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) | 1050 BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) | 1051 BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7) | 1052 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3), 1053 .require_force_probe = 1, 1054 }; 1055 1056 #define DG2_FEATURES \ 1057 XE_HP_FEATURES, \ 1058 XE_HPM_FEATURES, \ 1059 DGFX_FEATURES, \ 1060 .__runtime.graphics.ip.rel = 55, \ 1061 .__runtime.media.ip.rel = 55, \ 1062 PLATFORM(INTEL_DG2), \ 1063 .has_4tile = 1, \ 1064 .has_64k_pages = 1, \ 1065 .has_guc_deprivilege = 1, \ 1066 .has_heci_pxp = 1, \ 1067 .needs_compact_pt = 1, \ 1068 .has_media_ratio_mode = 1, \ 1069 .__runtime.platform_engine_mask = \ 1070 BIT(RCS0) | BIT(BCS0) | \ 1071 BIT(VECS0) | BIT(VECS1) | \ 1072 BIT(VCS0) | BIT(VCS2) | \ 1073 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3) 1074 1075 static const struct intel_device_info dg2_info = { 1076 DG2_FEATURES, 1077 XE_LPD_FEATURES, 1078 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 1079 BIT(TRANSCODER_C) | BIT(TRANSCODER_D), 1080 .require_force_probe = 1, 1081 }; 1082 1083 static const struct intel_device_info ats_m_info = { 1084 DG2_FEATURES, 1085 NO_DISPLAY, 1086 .require_force_probe = 1, 1087 .tuning_thread_rr_after_dep = 1, 1088 }; 1089 1090 #define XE_HPC_FEATURES \ 1091 XE_HP_FEATURES, \ 1092 .dma_mask_size = 52, \ 1093 .has_3d_pipeline = 0, \ 1094 .has_guc_deprivilege = 1, \ 1095 .has_l3_ccs_read = 1, \ 1096 .has_mslice_steering = 0, \ 1097 .has_one_eu_per_fuse_bit = 1 1098 1099 __maybe_unused 1100 static const struct intel_device_info pvc_info = { 1101 XE_HPC_FEATURES, 1102 XE_HPM_FEATURES, 1103 DGFX_FEATURES, 1104 .__runtime.graphics.ip.rel = 60, 1105 .__runtime.media.ip.rel = 60, 1106 PLATFORM(INTEL_PONTEVECCHIO), 1107 NO_DISPLAY, 1108 .has_flat_ccs = 0, 1109 .__runtime.platform_engine_mask = 1110 BIT(BCS0) | 1111 BIT(VCS0) | 1112 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3), 1113 .require_force_probe = 1, 1114 }; 1115 1116 #define XE_LPDP_FEATURES \ 1117 XE_LPD_FEATURES, \ 1118 .__runtime.display.ip.ver = 14, \ 1119 .display.has_cdclk_crawl = 1, \ 1120 .__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B) 1121 1122 static const struct intel_gt_definition xelpmp_extra_gt[] = { 1123 { 1124 .type = GT_MEDIA, 1125 .name = "Standalone Media GT", 1126 .gsi_offset = MTL_MEDIA_GSI_BASE, 1127 .engine_mask = BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 1128 }, 1129 {} 1130 }; 1131 1132 __maybe_unused 1133 static const struct intel_device_info mtl_info = { 1134 XE_HP_FEATURES, 1135 XE_LPDP_FEATURES, 1136 /* 1137 * Real graphics IP version will be obtained from hardware GMD_ID 1138 * register. Value provided here is just for sanity checking. 1139 */ 1140 .__runtime.graphics.ip.ver = 12, 1141 .__runtime.graphics.ip.rel = 70, 1142 .__runtime.media.ip.ver = 13, 1143 PLATFORM(INTEL_METEORLAKE), 1144 .display.has_modular_fia = 1, 1145 .extra_gt_list = xelpmp_extra_gt, 1146 .has_flat_ccs = 0, 1147 .has_snoop = 1, 1148 .__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM, 1149 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0), 1150 .require_force_probe = 1, 1151 }; 1152 1153 #undef PLATFORM 1154 1155 /* 1156 * Make sure any device matches here are from most specific to most 1157 * general. For example, since the Quanta match is based on the subsystem 1158 * and subvendor IDs, we need it to come before the more general IVB 1159 * PCI ID matches, otherwise we'll use the wrong info struct above. 1160 */ 1161 static const struct pci_device_id pciidlist[] = { 1162 INTEL_I830_IDS(&i830_info), 1163 INTEL_I845G_IDS(&i845g_info), 1164 INTEL_I85X_IDS(&i85x_info), 1165 INTEL_I865G_IDS(&i865g_info), 1166 INTEL_I915G_IDS(&i915g_info), 1167 INTEL_I915GM_IDS(&i915gm_info), 1168 INTEL_I945G_IDS(&i945g_info), 1169 INTEL_I945GM_IDS(&i945gm_info), 1170 INTEL_I965G_IDS(&i965g_info), 1171 INTEL_G33_IDS(&g33_info), 1172 INTEL_I965GM_IDS(&i965gm_info), 1173 INTEL_GM45_IDS(&gm45_info), 1174 INTEL_G45_IDS(&g45_info), 1175 INTEL_PINEVIEW_G_IDS(&pnv_g_info), 1176 INTEL_PINEVIEW_M_IDS(&pnv_m_info), 1177 INTEL_IRONLAKE_D_IDS(&ilk_d_info), 1178 INTEL_IRONLAKE_M_IDS(&ilk_m_info), 1179 INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info), 1180 INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info), 1181 INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info), 1182 INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info), 1183 INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */ 1184 INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info), 1185 INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info), 1186 INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info), 1187 INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info), 1188 INTEL_HSW_GT1_IDS(&hsw_gt1_info), 1189 INTEL_HSW_GT2_IDS(&hsw_gt2_info), 1190 INTEL_HSW_GT3_IDS(&hsw_gt3_info), 1191 INTEL_VLV_IDS(&vlv_info), 1192 INTEL_BDW_GT1_IDS(&bdw_gt1_info), 1193 INTEL_BDW_GT2_IDS(&bdw_gt2_info), 1194 INTEL_BDW_GT3_IDS(&bdw_gt3_info), 1195 INTEL_BDW_RSVD_IDS(&bdw_rsvd_info), 1196 INTEL_CHV_IDS(&chv_info), 1197 INTEL_SKL_GT1_IDS(&skl_gt1_info), 1198 INTEL_SKL_GT2_IDS(&skl_gt2_info), 1199 INTEL_SKL_GT3_IDS(&skl_gt3_info), 1200 INTEL_SKL_GT4_IDS(&skl_gt4_info), 1201 INTEL_BXT_IDS(&bxt_info), 1202 INTEL_GLK_IDS(&glk_info), 1203 INTEL_KBL_GT1_IDS(&kbl_gt1_info), 1204 INTEL_KBL_GT2_IDS(&kbl_gt2_info), 1205 INTEL_KBL_GT3_IDS(&kbl_gt3_info), 1206 INTEL_KBL_GT4_IDS(&kbl_gt3_info), 1207 INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info), 1208 INTEL_CFL_S_GT1_IDS(&cfl_gt1_info), 1209 INTEL_CFL_S_GT2_IDS(&cfl_gt2_info), 1210 INTEL_CFL_H_GT1_IDS(&cfl_gt1_info), 1211 INTEL_CFL_H_GT2_IDS(&cfl_gt2_info), 1212 INTEL_CFL_U_GT2_IDS(&cfl_gt2_info), 1213 INTEL_CFL_U_GT3_IDS(&cfl_gt3_info), 1214 INTEL_WHL_U_GT1_IDS(&cfl_gt1_info), 1215 INTEL_WHL_U_GT2_IDS(&cfl_gt2_info), 1216 INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info), 1217 INTEL_WHL_U_GT3_IDS(&cfl_gt3_info), 1218 INTEL_CML_GT1_IDS(&cml_gt1_info), 1219 INTEL_CML_GT2_IDS(&cml_gt2_info), 1220 INTEL_CML_U_GT1_IDS(&cml_gt1_info), 1221 INTEL_CML_U_GT2_IDS(&cml_gt2_info), 1222 INTEL_ICL_11_IDS(&icl_info), 1223 INTEL_EHL_IDS(&ehl_info), 1224 INTEL_JSL_IDS(&jsl_info), 1225 INTEL_TGL_12_IDS(&tgl_info), 1226 INTEL_RKL_IDS(&rkl_info), 1227 INTEL_ADLS_IDS(&adl_s_info), 1228 INTEL_ADLP_IDS(&adl_p_info), 1229 INTEL_ADLN_IDS(&adl_p_info), 1230 INTEL_DG1_IDS(&dg1_info), 1231 INTEL_RPLS_IDS(&adl_s_info), 1232 INTEL_RPLP_IDS(&adl_p_info), 1233 INTEL_DG2_IDS(&dg2_info), 1234 INTEL_ATS_M_IDS(&ats_m_info), 1235 INTEL_MTL_IDS(&mtl_info), 1236 {0, 0, 0} 1237 }; 1238 MODULE_DEVICE_TABLE(pci, pciidlist); 1239 1240 static void i915_pci_remove(struct pci_dev *pdev) 1241 { 1242 struct drm_i915_private *i915; 1243 1244 i915 = pci_get_drvdata(pdev); 1245 if (!i915) /* driver load aborted, nothing to cleanup */ 1246 return; 1247 1248 i915_driver_remove(i915); 1249 pci_set_drvdata(pdev, NULL); 1250 } 1251 1252 /* is device_id present in comma separated list of ids */ 1253 static bool force_probe(u16 device_id, const char *devices) 1254 { 1255 char *s, *p, *tok; 1256 bool ret; 1257 1258 if (!devices || !*devices) 1259 return false; 1260 1261 /* match everything */ 1262 if (strcmp(devices, "*") == 0) 1263 return true; 1264 1265 s = kstrdup(devices, GFP_KERNEL); 1266 if (!s) 1267 return false; 1268 1269 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) { 1270 u16 val; 1271 1272 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) { 1273 ret = true; 1274 break; 1275 } 1276 } 1277 1278 kfree(s); 1279 1280 return ret; 1281 } 1282 1283 bool i915_pci_resource_valid(struct pci_dev *pdev, int bar) 1284 { 1285 if (!pci_resource_flags(pdev, bar)) 1286 return false; 1287 1288 if (pci_resource_flags(pdev, bar) & IORESOURCE_UNSET) 1289 return false; 1290 1291 if (!pci_resource_len(pdev, bar)) 1292 return false; 1293 1294 return true; 1295 } 1296 1297 static bool intel_mmio_bar_valid(struct pci_dev *pdev, struct intel_device_info *intel_info) 1298 { 1299 int gttmmaddr_bar = intel_info->__runtime.graphics.ip.ver == 2 ? GEN2_GTTMMADR_BAR : GTTMMADR_BAR; 1300 1301 return i915_pci_resource_valid(pdev, gttmmaddr_bar); 1302 } 1303 1304 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1305 { 1306 struct intel_device_info *intel_info = 1307 (struct intel_device_info *) ent->driver_data; 1308 int err; 1309 1310 if (intel_info->require_force_probe && 1311 !force_probe(pdev->device, i915_modparams.force_probe)) { 1312 dev_info(&pdev->dev, 1313 "Your graphics device %04x is not properly supported by the driver in this\n" 1314 "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n" 1315 "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n" 1316 "or (recommended) check for kernel updates.\n", 1317 pdev->device, pdev->device, pdev->device); 1318 return -ENODEV; 1319 } 1320 1321 /* Only bind to function 0 of the device. Early generations 1322 * used function 1 as a placeholder for multi-head. This causes 1323 * us confusion instead, especially on the systems where both 1324 * functions have the same PCI-ID! 1325 */ 1326 if (PCI_FUNC(pdev->devfn)) 1327 return -ENODEV; 1328 1329 if (!intel_mmio_bar_valid(pdev, intel_info)) 1330 return -ENXIO; 1331 1332 /* Detect if we need to wait for other drivers early on */ 1333 if (intel_modeset_probe_defer(pdev)) 1334 return -EPROBE_DEFER; 1335 1336 err = i915_driver_probe(pdev, ent); 1337 if (err) 1338 return err; 1339 1340 if (i915_inject_probe_failure(pci_get_drvdata(pdev))) { 1341 i915_pci_remove(pdev); 1342 return -ENODEV; 1343 } 1344 1345 err = i915_live_selftests(pdev); 1346 if (err) { 1347 i915_pci_remove(pdev); 1348 return err > 0 ? -ENOTTY : err; 1349 } 1350 1351 err = i915_perf_selftests(pdev); 1352 if (err) { 1353 i915_pci_remove(pdev); 1354 return err > 0 ? -ENOTTY : err; 1355 } 1356 1357 return 0; 1358 } 1359 1360 static void i915_pci_shutdown(struct pci_dev *pdev) 1361 { 1362 struct drm_i915_private *i915 = pci_get_drvdata(pdev); 1363 1364 i915_driver_shutdown(i915); 1365 } 1366 1367 static struct pci_driver i915_pci_driver = { 1368 .name = DRIVER_NAME, 1369 .id_table = pciidlist, 1370 .probe = i915_pci_probe, 1371 .remove = i915_pci_remove, 1372 .shutdown = i915_pci_shutdown, 1373 .driver.pm = &i915_pm_ops, 1374 }; 1375 1376 int i915_pci_register_driver(void) 1377 { 1378 return pci_register_driver(&i915_pci_driver); 1379 } 1380 1381 void i915_pci_unregister_driver(void) 1382 { 1383 pci_unregister_driver(&i915_pci_driver); 1384 } 1385