1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <drm/drm_color_mgmt.h> 26 #include <drm/drm_drv.h> 27 #include <drm/i915_pciids.h> 28 29 #include "display/intel_display.h" 30 #include "display/intel_display_driver.h" 31 #include "gt/intel_gt_regs.h" 32 #include "gt/intel_sa_media.h" 33 34 #include "i915_driver.h" 35 #include "i915_drv.h" 36 #include "i915_pci.h" 37 #include "i915_reg.h" 38 #include "intel_pci_config.h" 39 40 #define PLATFORM(x) .platform = (x) 41 #define GEN(x) \ 42 .__runtime.graphics.ip.ver = (x), \ 43 .__runtime.media.ip.ver = (x), \ 44 .__runtime.display.ip.ver = (x) 45 46 #define NO_DISPLAY .__runtime.pipe_mask = 0 47 48 #define I845_PIPE_OFFSETS \ 49 .display.pipe_offsets = { \ 50 [TRANSCODER_A] = PIPE_A_OFFSET, \ 51 }, \ 52 .display.trans_offsets = { \ 53 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 54 } 55 56 #define I9XX_PIPE_OFFSETS \ 57 .display.pipe_offsets = { \ 58 [TRANSCODER_A] = PIPE_A_OFFSET, \ 59 [TRANSCODER_B] = PIPE_B_OFFSET, \ 60 }, \ 61 .display.trans_offsets = { \ 62 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 63 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 64 } 65 66 #define IVB_PIPE_OFFSETS \ 67 .display.pipe_offsets = { \ 68 [TRANSCODER_A] = PIPE_A_OFFSET, \ 69 [TRANSCODER_B] = PIPE_B_OFFSET, \ 70 [TRANSCODER_C] = PIPE_C_OFFSET, \ 71 }, \ 72 .display.trans_offsets = { \ 73 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 74 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 75 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 76 } 77 78 #define HSW_PIPE_OFFSETS \ 79 .display.pipe_offsets = { \ 80 [TRANSCODER_A] = PIPE_A_OFFSET, \ 81 [TRANSCODER_B] = PIPE_B_OFFSET, \ 82 [TRANSCODER_C] = PIPE_C_OFFSET, \ 83 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 84 }, \ 85 .display.trans_offsets = { \ 86 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 87 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 88 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 89 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 90 } 91 92 #define CHV_PIPE_OFFSETS \ 93 .display.pipe_offsets = { \ 94 [TRANSCODER_A] = PIPE_A_OFFSET, \ 95 [TRANSCODER_B] = PIPE_B_OFFSET, \ 96 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \ 97 }, \ 98 .display.trans_offsets = { \ 99 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 100 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 101 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \ 102 } 103 104 #define I845_CURSOR_OFFSETS \ 105 .display.cursor_offsets = { \ 106 [PIPE_A] = CURSOR_A_OFFSET, \ 107 } 108 109 #define I9XX_CURSOR_OFFSETS \ 110 .display.cursor_offsets = { \ 111 [PIPE_A] = CURSOR_A_OFFSET, \ 112 [PIPE_B] = CURSOR_B_OFFSET, \ 113 } 114 115 #define CHV_CURSOR_OFFSETS \ 116 .display.cursor_offsets = { \ 117 [PIPE_A] = CURSOR_A_OFFSET, \ 118 [PIPE_B] = CURSOR_B_OFFSET, \ 119 [PIPE_C] = CHV_CURSOR_C_OFFSET, \ 120 } 121 122 #define IVB_CURSOR_OFFSETS \ 123 .display.cursor_offsets = { \ 124 [PIPE_A] = CURSOR_A_OFFSET, \ 125 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 126 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 127 } 128 129 #define TGL_CURSOR_OFFSETS \ 130 .display.cursor_offsets = { \ 131 [PIPE_A] = CURSOR_A_OFFSET, \ 132 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 133 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 134 [PIPE_D] = TGL_CURSOR_D_OFFSET, \ 135 } 136 137 #define I845_COLORS \ 138 .display.color = { .gamma_lut_size = 256 } 139 #define I9XX_COLORS \ 140 .display.color = { .gamma_lut_size = 129, \ 141 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 142 } 143 #define ILK_COLORS \ 144 .display.color = { .gamma_lut_size = 1024 } 145 #define IVB_COLORS \ 146 .display.color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 } 147 #define CHV_COLORS \ 148 .display.color = { \ 149 .degamma_lut_size = 65, .gamma_lut_size = 257, \ 150 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 151 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 152 } 153 #define GLK_COLORS \ 154 .display.color = { \ 155 .degamma_lut_size = 33, .gamma_lut_size = 1024, \ 156 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 157 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 158 } 159 #define ICL_COLORS \ 160 .display.color = { \ 161 .degamma_lut_size = 33, .gamma_lut_size = 262145, \ 162 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 163 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 164 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 165 } 166 167 /* Keep in gen based order, and chronological order within a gen */ 168 169 #define GEN_DEFAULT_PAGE_SIZES \ 170 .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K 171 172 #define GEN_DEFAULT_REGIONS \ 173 .__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_SMEM 174 175 #define I830_FEATURES \ 176 GEN(2), \ 177 .is_mobile = 1, \ 178 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 179 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 180 .display.has_overlay = 1, \ 181 .display.cursor_needs_physical = 1, \ 182 .display.overlay_needs_physical = 1, \ 183 .display.has_gmch = 1, \ 184 .gpu_reset_clobbers_display = true, \ 185 .has_3d_pipeline = 1, \ 186 .hws_needs_physical = 1, \ 187 .unfenced_needs_alignment = 1, \ 188 .__runtime.platform_engine_mask = BIT(RCS0), \ 189 .has_snoop = true, \ 190 .has_coherent_ggtt = false, \ 191 .dma_mask_size = 32, \ 192 I9XX_PIPE_OFFSETS, \ 193 I9XX_CURSOR_OFFSETS, \ 194 I9XX_COLORS, \ 195 GEN_DEFAULT_PAGE_SIZES, \ 196 GEN_DEFAULT_REGIONS 197 198 #define I845_FEATURES \ 199 GEN(2), \ 200 .__runtime.pipe_mask = BIT(PIPE_A), \ 201 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A), \ 202 .display.has_overlay = 1, \ 203 .display.overlay_needs_physical = 1, \ 204 .display.has_gmch = 1, \ 205 .has_3d_pipeline = 1, \ 206 .gpu_reset_clobbers_display = true, \ 207 .hws_needs_physical = 1, \ 208 .unfenced_needs_alignment = 1, \ 209 .__runtime.platform_engine_mask = BIT(RCS0), \ 210 .has_snoop = true, \ 211 .has_coherent_ggtt = false, \ 212 .dma_mask_size = 32, \ 213 I845_PIPE_OFFSETS, \ 214 I845_CURSOR_OFFSETS, \ 215 I845_COLORS, \ 216 GEN_DEFAULT_PAGE_SIZES, \ 217 GEN_DEFAULT_REGIONS 218 219 static const struct intel_device_info i830_info = { 220 I830_FEATURES, 221 PLATFORM(INTEL_I830), 222 }; 223 224 static const struct intel_device_info i845g_info = { 225 I845_FEATURES, 226 PLATFORM(INTEL_I845G), 227 }; 228 229 static const struct intel_device_info i85x_info = { 230 I830_FEATURES, 231 PLATFORM(INTEL_I85X), 232 .__runtime.fbc_mask = BIT(INTEL_FBC_A), 233 }; 234 235 static const struct intel_device_info i865g_info = { 236 I845_FEATURES, 237 PLATFORM(INTEL_I865G), 238 .__runtime.fbc_mask = BIT(INTEL_FBC_A), 239 }; 240 241 #define GEN3_FEATURES \ 242 GEN(3), \ 243 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 244 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 245 .display.has_gmch = 1, \ 246 .gpu_reset_clobbers_display = true, \ 247 .__runtime.platform_engine_mask = BIT(RCS0), \ 248 .has_3d_pipeline = 1, \ 249 .has_snoop = true, \ 250 .has_coherent_ggtt = true, \ 251 .dma_mask_size = 32, \ 252 I9XX_PIPE_OFFSETS, \ 253 I9XX_CURSOR_OFFSETS, \ 254 I9XX_COLORS, \ 255 GEN_DEFAULT_PAGE_SIZES, \ 256 GEN_DEFAULT_REGIONS 257 258 static const struct intel_device_info i915g_info = { 259 GEN3_FEATURES, 260 PLATFORM(INTEL_I915G), 261 .has_coherent_ggtt = false, 262 .display.cursor_needs_physical = 1, 263 .display.has_overlay = 1, 264 .display.overlay_needs_physical = 1, 265 .hws_needs_physical = 1, 266 .unfenced_needs_alignment = 1, 267 }; 268 269 static const struct intel_device_info i915gm_info = { 270 GEN3_FEATURES, 271 PLATFORM(INTEL_I915GM), 272 .is_mobile = 1, 273 .display.cursor_needs_physical = 1, 274 .display.has_overlay = 1, 275 .display.overlay_needs_physical = 1, 276 .display.supports_tv = 1, 277 .__runtime.fbc_mask = BIT(INTEL_FBC_A), 278 .hws_needs_physical = 1, 279 .unfenced_needs_alignment = 1, 280 }; 281 282 static const struct intel_device_info i945g_info = { 283 GEN3_FEATURES, 284 PLATFORM(INTEL_I945G), 285 .display.has_hotplug = 1, 286 .display.cursor_needs_physical = 1, 287 .display.has_overlay = 1, 288 .display.overlay_needs_physical = 1, 289 .hws_needs_physical = 1, 290 .unfenced_needs_alignment = 1, 291 }; 292 293 static const struct intel_device_info i945gm_info = { 294 GEN3_FEATURES, 295 PLATFORM(INTEL_I945GM), 296 .is_mobile = 1, 297 .display.has_hotplug = 1, 298 .display.cursor_needs_physical = 1, 299 .display.has_overlay = 1, 300 .display.overlay_needs_physical = 1, 301 .display.supports_tv = 1, 302 .__runtime.fbc_mask = BIT(INTEL_FBC_A), 303 .hws_needs_physical = 1, 304 .unfenced_needs_alignment = 1, 305 }; 306 307 static const struct intel_device_info g33_info = { 308 GEN3_FEATURES, 309 PLATFORM(INTEL_G33), 310 .display.has_hotplug = 1, 311 .display.has_overlay = 1, 312 .dma_mask_size = 36, 313 }; 314 315 static const struct intel_device_info pnv_g_info = { 316 GEN3_FEATURES, 317 PLATFORM(INTEL_PINEVIEW), 318 .display.has_hotplug = 1, 319 .display.has_overlay = 1, 320 .dma_mask_size = 36, 321 }; 322 323 static const struct intel_device_info pnv_m_info = { 324 GEN3_FEATURES, 325 PLATFORM(INTEL_PINEVIEW), 326 .is_mobile = 1, 327 .display.has_hotplug = 1, 328 .display.has_overlay = 1, 329 .dma_mask_size = 36, 330 }; 331 332 #define GEN4_FEATURES \ 333 GEN(4), \ 334 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 335 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 336 .display.has_hotplug = 1, \ 337 .display.has_gmch = 1, \ 338 .gpu_reset_clobbers_display = true, \ 339 .__runtime.platform_engine_mask = BIT(RCS0), \ 340 .has_3d_pipeline = 1, \ 341 .has_snoop = true, \ 342 .has_coherent_ggtt = true, \ 343 .dma_mask_size = 36, \ 344 I9XX_PIPE_OFFSETS, \ 345 I9XX_CURSOR_OFFSETS, \ 346 I9XX_COLORS, \ 347 GEN_DEFAULT_PAGE_SIZES, \ 348 GEN_DEFAULT_REGIONS 349 350 static const struct intel_device_info i965g_info = { 351 GEN4_FEATURES, 352 PLATFORM(INTEL_I965G), 353 .display.has_overlay = 1, 354 .hws_needs_physical = 1, 355 .has_snoop = false, 356 }; 357 358 static const struct intel_device_info i965gm_info = { 359 GEN4_FEATURES, 360 PLATFORM(INTEL_I965GM), 361 .is_mobile = 1, 362 .__runtime.fbc_mask = BIT(INTEL_FBC_A), 363 .display.has_overlay = 1, 364 .display.supports_tv = 1, 365 .hws_needs_physical = 1, 366 .has_snoop = false, 367 }; 368 369 static const struct intel_device_info g45_info = { 370 GEN4_FEATURES, 371 PLATFORM(INTEL_G45), 372 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0), 373 .gpu_reset_clobbers_display = false, 374 }; 375 376 static const struct intel_device_info gm45_info = { 377 GEN4_FEATURES, 378 PLATFORM(INTEL_GM45), 379 .is_mobile = 1, 380 .__runtime.fbc_mask = BIT(INTEL_FBC_A), 381 .display.supports_tv = 1, 382 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0), 383 .gpu_reset_clobbers_display = false, 384 }; 385 386 #define GEN5_FEATURES \ 387 GEN(5), \ 388 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 389 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 390 .display.has_hotplug = 1, \ 391 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0), \ 392 .has_3d_pipeline = 1, \ 393 .has_snoop = true, \ 394 .has_coherent_ggtt = true, \ 395 /* ilk does support rc6, but we do not implement [power] contexts */ \ 396 .has_rc6 = 0, \ 397 .dma_mask_size = 36, \ 398 I9XX_PIPE_OFFSETS, \ 399 I9XX_CURSOR_OFFSETS, \ 400 ILK_COLORS, \ 401 GEN_DEFAULT_PAGE_SIZES, \ 402 GEN_DEFAULT_REGIONS 403 404 static const struct intel_device_info ilk_d_info = { 405 GEN5_FEATURES, 406 PLATFORM(INTEL_IRONLAKE), 407 }; 408 409 static const struct intel_device_info ilk_m_info = { 410 GEN5_FEATURES, 411 PLATFORM(INTEL_IRONLAKE), 412 .is_mobile = 1, 413 .has_rps = true, 414 .__runtime.fbc_mask = BIT(INTEL_FBC_A), 415 }; 416 417 #define GEN6_FEATURES \ 418 GEN(6), \ 419 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ 420 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ 421 .display.has_hotplug = 1, \ 422 .__runtime.fbc_mask = BIT(INTEL_FBC_A), \ 423 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ 424 .has_3d_pipeline = 1, \ 425 .has_coherent_ggtt = true, \ 426 .has_llc = 1, \ 427 .has_rc6 = 1, \ 428 /* snb does support rc6p, but enabling it causes various issues */ \ 429 .has_rc6p = 0, \ 430 .has_rps = true, \ 431 .dma_mask_size = 40, \ 432 .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \ 433 .__runtime.ppgtt_size = 31, \ 434 I9XX_PIPE_OFFSETS, \ 435 I9XX_CURSOR_OFFSETS, \ 436 ILK_COLORS, \ 437 GEN_DEFAULT_PAGE_SIZES, \ 438 GEN_DEFAULT_REGIONS 439 440 #define SNB_D_PLATFORM \ 441 GEN6_FEATURES, \ 442 PLATFORM(INTEL_SANDYBRIDGE) 443 444 static const struct intel_device_info snb_d_gt1_info = { 445 SNB_D_PLATFORM, 446 .gt = 1, 447 }; 448 449 static const struct intel_device_info snb_d_gt2_info = { 450 SNB_D_PLATFORM, 451 .gt = 2, 452 }; 453 454 #define SNB_M_PLATFORM \ 455 GEN6_FEATURES, \ 456 PLATFORM(INTEL_SANDYBRIDGE), \ 457 .is_mobile = 1 458 459 460 static const struct intel_device_info snb_m_gt1_info = { 461 SNB_M_PLATFORM, 462 .gt = 1, 463 }; 464 465 static const struct intel_device_info snb_m_gt2_info = { 466 SNB_M_PLATFORM, 467 .gt = 2, 468 }; 469 470 #define GEN7_FEATURES \ 471 GEN(7), \ 472 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ 473 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \ 474 .display.has_hotplug = 1, \ 475 .__runtime.fbc_mask = BIT(INTEL_FBC_A), \ 476 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ 477 .has_3d_pipeline = 1, \ 478 .has_coherent_ggtt = true, \ 479 .has_llc = 1, \ 480 .has_rc6 = 1, \ 481 .has_rc6p = 1, \ 482 .has_reset_engine = true, \ 483 .has_rps = true, \ 484 .dma_mask_size = 40, \ 485 .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \ 486 .__runtime.ppgtt_size = 31, \ 487 IVB_PIPE_OFFSETS, \ 488 IVB_CURSOR_OFFSETS, \ 489 IVB_COLORS, \ 490 GEN_DEFAULT_PAGE_SIZES, \ 491 GEN_DEFAULT_REGIONS 492 493 #define IVB_D_PLATFORM \ 494 GEN7_FEATURES, \ 495 PLATFORM(INTEL_IVYBRIDGE), \ 496 .has_l3_dpf = 1 497 498 static const struct intel_device_info ivb_d_gt1_info = { 499 IVB_D_PLATFORM, 500 .gt = 1, 501 }; 502 503 static const struct intel_device_info ivb_d_gt2_info = { 504 IVB_D_PLATFORM, 505 .gt = 2, 506 }; 507 508 #define IVB_M_PLATFORM \ 509 GEN7_FEATURES, \ 510 PLATFORM(INTEL_IVYBRIDGE), \ 511 .is_mobile = 1, \ 512 .has_l3_dpf = 1 513 514 static const struct intel_device_info ivb_m_gt1_info = { 515 IVB_M_PLATFORM, 516 .gt = 1, 517 }; 518 519 static const struct intel_device_info ivb_m_gt2_info = { 520 IVB_M_PLATFORM, 521 .gt = 2, 522 }; 523 524 static const struct intel_device_info ivb_q_info = { 525 GEN7_FEATURES, 526 PLATFORM(INTEL_IVYBRIDGE), 527 NO_DISPLAY, 528 .gt = 2, 529 .has_l3_dpf = 1, 530 }; 531 532 static const struct intel_device_info vlv_info = { 533 PLATFORM(INTEL_VALLEYVIEW), 534 GEN(7), 535 .is_lp = 1, 536 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), 537 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), 538 .has_runtime_pm = 1, 539 .has_rc6 = 1, 540 .has_reset_engine = true, 541 .has_rps = true, 542 .display.has_gmch = 1, 543 .display.has_hotplug = 1, 544 .dma_mask_size = 40, 545 .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, 546 .__runtime.ppgtt_size = 31, 547 .has_snoop = true, 548 .has_coherent_ggtt = false, 549 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), 550 .display.mmio_offset = VLV_DISPLAY_BASE, 551 I9XX_PIPE_OFFSETS, 552 I9XX_CURSOR_OFFSETS, 553 I9XX_COLORS, 554 GEN_DEFAULT_PAGE_SIZES, 555 GEN_DEFAULT_REGIONS, 556 }; 557 558 #define G75_FEATURES \ 559 GEN7_FEATURES, \ 560 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ 561 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 562 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \ 563 .display.has_ddi = 1, \ 564 .display.has_fpga_dbg = 1, \ 565 .display.has_dp_mst = 1, \ 566 .has_rc6p = 0 /* RC6p removed-by HSW */, \ 567 HSW_PIPE_OFFSETS, \ 568 .has_runtime_pm = 1 569 570 #define HSW_PLATFORM \ 571 G75_FEATURES, \ 572 PLATFORM(INTEL_HASWELL), \ 573 .has_l3_dpf = 1 574 575 static const struct intel_device_info hsw_gt1_info = { 576 HSW_PLATFORM, 577 .gt = 1, 578 }; 579 580 static const struct intel_device_info hsw_gt2_info = { 581 HSW_PLATFORM, 582 .gt = 2, 583 }; 584 585 static const struct intel_device_info hsw_gt3_info = { 586 HSW_PLATFORM, 587 .gt = 3, 588 }; 589 590 #define GEN8_FEATURES \ 591 G75_FEATURES, \ 592 GEN(8), \ 593 .has_logical_ring_contexts = 1, \ 594 .dma_mask_size = 39, \ 595 .__runtime.ppgtt_type = INTEL_PPGTT_FULL, \ 596 .__runtime.ppgtt_size = 48, \ 597 .has_64bit_reloc = 1 598 599 #define BDW_PLATFORM \ 600 GEN8_FEATURES, \ 601 PLATFORM(INTEL_BROADWELL) 602 603 static const struct intel_device_info bdw_gt1_info = { 604 BDW_PLATFORM, 605 .gt = 1, 606 }; 607 608 static const struct intel_device_info bdw_gt2_info = { 609 BDW_PLATFORM, 610 .gt = 2, 611 }; 612 613 static const struct intel_device_info bdw_rsvd_info = { 614 BDW_PLATFORM, 615 .gt = 3, 616 /* According to the device ID those devices are GT3, they were 617 * previously treated as not GT3, keep it like that. 618 */ 619 }; 620 621 static const struct intel_device_info bdw_gt3_info = { 622 BDW_PLATFORM, 623 .gt = 3, 624 .__runtime.platform_engine_mask = 625 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 626 }; 627 628 static const struct intel_device_info chv_info = { 629 PLATFORM(INTEL_CHERRYVIEW), 630 GEN(8), 631 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 632 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), 633 .display.has_hotplug = 1, 634 .is_lp = 1, 635 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), 636 .has_64bit_reloc = 1, 637 .has_runtime_pm = 1, 638 .has_rc6 = 1, 639 .has_rps = true, 640 .has_logical_ring_contexts = 1, 641 .display.has_gmch = 1, 642 .dma_mask_size = 39, 643 .__runtime.ppgtt_type = INTEL_PPGTT_FULL, 644 .__runtime.ppgtt_size = 32, 645 .has_reset_engine = 1, 646 .has_snoop = true, 647 .has_coherent_ggtt = false, 648 .display.mmio_offset = VLV_DISPLAY_BASE, 649 CHV_PIPE_OFFSETS, 650 CHV_CURSOR_OFFSETS, 651 CHV_COLORS, 652 GEN_DEFAULT_PAGE_SIZES, 653 GEN_DEFAULT_REGIONS, 654 }; 655 656 #define GEN9_DEFAULT_PAGE_SIZES \ 657 .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \ 658 I915_GTT_PAGE_SIZE_64K 659 660 #define GEN9_FEATURES \ 661 GEN8_FEATURES, \ 662 GEN(9), \ 663 GEN9_DEFAULT_PAGE_SIZES, \ 664 .__runtime.has_dmc = 1, \ 665 .has_gt_uc = 1, \ 666 .__runtime.has_hdcp = 1, \ 667 .display.has_ipc = 1, \ 668 .display.has_psr = 1, \ 669 .display.has_psr_hw_tracking = 1, \ 670 .display.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \ 671 .display.dbuf.slice_mask = BIT(DBUF_S1) 672 673 #define SKL_PLATFORM \ 674 GEN9_FEATURES, \ 675 PLATFORM(INTEL_SKYLAKE) 676 677 static const struct intel_device_info skl_gt1_info = { 678 SKL_PLATFORM, 679 .gt = 1, 680 }; 681 682 static const struct intel_device_info skl_gt2_info = { 683 SKL_PLATFORM, 684 .gt = 2, 685 }; 686 687 #define SKL_GT3_PLUS_PLATFORM \ 688 SKL_PLATFORM, \ 689 .__runtime.platform_engine_mask = \ 690 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1) 691 692 693 static const struct intel_device_info skl_gt3_info = { 694 SKL_GT3_PLUS_PLATFORM, 695 .gt = 3, 696 }; 697 698 static const struct intel_device_info skl_gt4_info = { 699 SKL_GT3_PLUS_PLATFORM, 700 .gt = 4, 701 }; 702 703 #define GEN9_LP_FEATURES \ 704 GEN(9), \ 705 .is_lp = 1, \ 706 .display.dbuf.slice_mask = BIT(DBUF_S1), \ 707 .display.has_hotplug = 1, \ 708 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ 709 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ 710 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 711 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ 712 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \ 713 .has_3d_pipeline = 1, \ 714 .has_64bit_reloc = 1, \ 715 .display.has_ddi = 1, \ 716 .display.has_fpga_dbg = 1, \ 717 .__runtime.fbc_mask = BIT(INTEL_FBC_A), \ 718 .__runtime.has_hdcp = 1, \ 719 .display.has_psr = 1, \ 720 .display.has_psr_hw_tracking = 1, \ 721 .has_runtime_pm = 1, \ 722 .__runtime.has_dmc = 1, \ 723 .has_rc6 = 1, \ 724 .has_rps = true, \ 725 .display.has_dp_mst = 1, \ 726 .has_logical_ring_contexts = 1, \ 727 .has_gt_uc = 1, \ 728 .dma_mask_size = 39, \ 729 .__runtime.ppgtt_type = INTEL_PPGTT_FULL, \ 730 .__runtime.ppgtt_size = 48, \ 731 .has_reset_engine = 1, \ 732 .has_snoop = true, \ 733 .has_coherent_ggtt = false, \ 734 .display.has_ipc = 1, \ 735 HSW_PIPE_OFFSETS, \ 736 IVB_CURSOR_OFFSETS, \ 737 IVB_COLORS, \ 738 GEN9_DEFAULT_PAGE_SIZES, \ 739 GEN_DEFAULT_REGIONS 740 741 static const struct intel_device_info bxt_info = { 742 GEN9_LP_FEATURES, 743 PLATFORM(INTEL_BROXTON), 744 .display.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */ 745 }; 746 747 static const struct intel_device_info glk_info = { 748 GEN9_LP_FEATURES, 749 PLATFORM(INTEL_GEMINILAKE), 750 .__runtime.display.ip.ver = 10, 751 .display.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ 752 GLK_COLORS, 753 }; 754 755 #define KBL_PLATFORM \ 756 GEN9_FEATURES, \ 757 PLATFORM(INTEL_KABYLAKE) 758 759 static const struct intel_device_info kbl_gt1_info = { 760 KBL_PLATFORM, 761 .gt = 1, 762 }; 763 764 static const struct intel_device_info kbl_gt2_info = { 765 KBL_PLATFORM, 766 .gt = 2, 767 }; 768 769 static const struct intel_device_info kbl_gt3_info = { 770 KBL_PLATFORM, 771 .gt = 3, 772 .__runtime.platform_engine_mask = 773 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 774 }; 775 776 #define CFL_PLATFORM \ 777 GEN9_FEATURES, \ 778 PLATFORM(INTEL_COFFEELAKE) 779 780 static const struct intel_device_info cfl_gt1_info = { 781 CFL_PLATFORM, 782 .gt = 1, 783 }; 784 785 static const struct intel_device_info cfl_gt2_info = { 786 CFL_PLATFORM, 787 .gt = 2, 788 }; 789 790 static const struct intel_device_info cfl_gt3_info = { 791 CFL_PLATFORM, 792 .gt = 3, 793 .__runtime.platform_engine_mask = 794 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 795 }; 796 797 #define CML_PLATFORM \ 798 GEN9_FEATURES, \ 799 PLATFORM(INTEL_COMETLAKE) 800 801 static const struct intel_device_info cml_gt1_info = { 802 CML_PLATFORM, 803 .gt = 1, 804 }; 805 806 static const struct intel_device_info cml_gt2_info = { 807 CML_PLATFORM, 808 .gt = 2, 809 }; 810 811 #define GEN11_DEFAULT_PAGE_SIZES \ 812 .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \ 813 I915_GTT_PAGE_SIZE_64K | \ 814 I915_GTT_PAGE_SIZE_2M 815 816 #define GEN11_FEATURES \ 817 GEN9_FEATURES, \ 818 GEN11_DEFAULT_PAGE_SIZES, \ 819 .display.abox_mask = BIT(0), \ 820 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 821 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ 822 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ 823 .display.pipe_offsets = { \ 824 [TRANSCODER_A] = PIPE_A_OFFSET, \ 825 [TRANSCODER_B] = PIPE_B_OFFSET, \ 826 [TRANSCODER_C] = PIPE_C_OFFSET, \ 827 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 828 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 829 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 830 }, \ 831 .display.trans_offsets = { \ 832 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 833 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 834 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 835 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 836 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 837 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 838 }, \ 839 GEN(11), \ 840 ICL_COLORS, \ 841 .display.dbuf.size = 2048, \ 842 .display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \ 843 .__runtime.has_dsc = 1, \ 844 .has_coherent_ggtt = false, \ 845 .has_logical_ring_elsq = 1 846 847 static const struct intel_device_info icl_info = { 848 GEN11_FEATURES, 849 PLATFORM(INTEL_ICELAKE), 850 .__runtime.platform_engine_mask = 851 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 852 }; 853 854 static const struct intel_device_info ehl_info = { 855 GEN11_FEATURES, 856 PLATFORM(INTEL_ELKHARTLAKE), 857 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0), 858 .__runtime.ppgtt_size = 36, 859 }; 860 861 static const struct intel_device_info jsl_info = { 862 GEN11_FEATURES, 863 PLATFORM(INTEL_JASPERLAKE), 864 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0), 865 .__runtime.ppgtt_size = 36, 866 }; 867 868 #define GEN12_FEATURES \ 869 GEN11_FEATURES, \ 870 GEN(12), \ 871 .display.abox_mask = GENMASK(2, 1), \ 872 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ 873 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ 874 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \ 875 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ 876 .display.pipe_offsets = { \ 877 [TRANSCODER_A] = PIPE_A_OFFSET, \ 878 [TRANSCODER_B] = PIPE_B_OFFSET, \ 879 [TRANSCODER_C] = PIPE_C_OFFSET, \ 880 [TRANSCODER_D] = PIPE_D_OFFSET, \ 881 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 882 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 883 }, \ 884 .display.trans_offsets = { \ 885 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 886 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 887 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 888 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ 889 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 890 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 891 }, \ 892 TGL_CURSOR_OFFSETS, \ 893 .has_global_mocs = 1, \ 894 .has_pxp = 1, \ 895 .display.has_dsb = 1 896 897 static const struct intel_device_info tgl_info = { 898 GEN12_FEATURES, 899 PLATFORM(INTEL_TIGERLAKE), 900 .__runtime.platform_engine_mask = 901 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 902 }; 903 904 static const struct intel_device_info rkl_info = { 905 GEN12_FEATURES, 906 PLATFORM(INTEL_ROCKETLAKE), 907 .display.abox_mask = BIT(0), 908 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 909 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 910 BIT(TRANSCODER_C), 911 .display.has_hti = 1, 912 .display.has_psr_hw_tracking = 0, 913 .__runtime.platform_engine_mask = 914 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0), 915 }; 916 917 #define DGFX_FEATURES \ 918 .__runtime.memory_regions = REGION_SMEM | REGION_LMEM | REGION_STOLEN_LMEM, \ 919 .has_llc = 0, \ 920 .has_pxp = 0, \ 921 .has_snoop = 1, \ 922 .is_dgfx = 1, \ 923 .has_heci_gscfi = 1 924 925 static const struct intel_device_info dg1_info = { 926 GEN12_FEATURES, 927 DGFX_FEATURES, 928 .__runtime.graphics.ip.rel = 10, 929 PLATFORM(INTEL_DG1), 930 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 931 .require_force_probe = 1, 932 .__runtime.platform_engine_mask = 933 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | 934 BIT(VCS0) | BIT(VCS2), 935 /* Wa_16011227922 */ 936 .__runtime.ppgtt_size = 47, 937 }; 938 939 static const struct intel_device_info adl_s_info = { 940 GEN12_FEATURES, 941 PLATFORM(INTEL_ALDERLAKE_S), 942 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 943 .display.has_hti = 1, 944 .display.has_psr_hw_tracking = 0, 945 .__runtime.platform_engine_mask = 946 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 947 .dma_mask_size = 39, 948 }; 949 950 #define XE_LPD_FEATURES \ 951 .display.abox_mask = GENMASK(1, 0), \ 952 .display.color = { \ 953 .degamma_lut_size = 129, .gamma_lut_size = 1024, \ 954 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 955 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 956 }, \ 957 .display.dbuf.size = 4096, \ 958 .display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \ 959 BIT(DBUF_S4), \ 960 .display.has_ddi = 1, \ 961 .__runtime.has_dmc = 1, \ 962 .display.has_dp_mst = 1, \ 963 .display.has_dsb = 1, \ 964 .__runtime.has_dsc = 1, \ 965 .__runtime.fbc_mask = BIT(INTEL_FBC_A), \ 966 .display.has_fpga_dbg = 1, \ 967 .__runtime.has_hdcp = 1, \ 968 .display.has_hotplug = 1, \ 969 .display.has_ipc = 1, \ 970 .display.has_psr = 1, \ 971 .__runtime.display.ip.ver = 13, \ 972 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ 973 .display.pipe_offsets = { \ 974 [TRANSCODER_A] = PIPE_A_OFFSET, \ 975 [TRANSCODER_B] = PIPE_B_OFFSET, \ 976 [TRANSCODER_C] = PIPE_C_OFFSET, \ 977 [TRANSCODER_D] = PIPE_D_OFFSET, \ 978 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 979 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 980 }, \ 981 .display.trans_offsets = { \ 982 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 983 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 984 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 985 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ 986 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 987 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 988 }, \ 989 TGL_CURSOR_OFFSETS 990 991 static const struct intel_device_info adl_p_info = { 992 GEN12_FEATURES, 993 XE_LPD_FEATURES, 994 PLATFORM(INTEL_ALDERLAKE_P), 995 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 996 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | 997 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), 998 .display.has_cdclk_crawl = 1, 999 .display.has_psr_hw_tracking = 0, 1000 .__runtime.platform_engine_mask = 1001 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 1002 .__runtime.ppgtt_size = 48, 1003 .dma_mask_size = 39, 1004 }; 1005 1006 #undef GEN 1007 1008 #define XE_HP_PAGE_SIZES \ 1009 .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \ 1010 I915_GTT_PAGE_SIZE_64K | \ 1011 I915_GTT_PAGE_SIZE_2M 1012 1013 #define XE_HP_FEATURES \ 1014 .__runtime.graphics.ip.ver = 12, \ 1015 .__runtime.graphics.ip.rel = 50, \ 1016 XE_HP_PAGE_SIZES, \ 1017 .dma_mask_size = 46, \ 1018 .has_3d_pipeline = 1, \ 1019 .has_64bit_reloc = 1, \ 1020 .has_flat_ccs = 1, \ 1021 .has_4tile = 1, \ 1022 .has_global_mocs = 1, \ 1023 .has_gt_uc = 1, \ 1024 .has_llc = 1, \ 1025 .has_logical_ring_contexts = 1, \ 1026 .has_logical_ring_elsq = 1, \ 1027 .has_mslice_steering = 1, \ 1028 .has_oa_bpc_reporting = 1, \ 1029 .has_oa_slice_contrib_limits = 1, \ 1030 .has_oam = 1, \ 1031 .has_rc6 = 1, \ 1032 .has_reset_engine = 1, \ 1033 .has_rps = 1, \ 1034 .has_runtime_pm = 1, \ 1035 .__runtime.ppgtt_size = 48, \ 1036 .__runtime.ppgtt_type = INTEL_PPGTT_FULL 1037 1038 #define XE_HPM_FEATURES \ 1039 .__runtime.media.ip.ver = 12, \ 1040 .__runtime.media.ip.rel = 50 1041 1042 __maybe_unused 1043 static const struct intel_device_info xehpsdv_info = { 1044 XE_HP_FEATURES, 1045 XE_HPM_FEATURES, 1046 DGFX_FEATURES, 1047 PLATFORM(INTEL_XEHPSDV), 1048 NO_DISPLAY, 1049 .has_64k_pages = 1, 1050 .has_media_ratio_mode = 1, 1051 .__runtime.platform_engine_mask = 1052 BIT(RCS0) | BIT(BCS0) | 1053 BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) | 1054 BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) | 1055 BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7) | 1056 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3), 1057 .require_force_probe = 1, 1058 }; 1059 1060 #define DG2_FEATURES \ 1061 XE_HP_FEATURES, \ 1062 XE_HPM_FEATURES, \ 1063 DGFX_FEATURES, \ 1064 .__runtime.graphics.ip.rel = 55, \ 1065 .__runtime.media.ip.rel = 55, \ 1066 PLATFORM(INTEL_DG2), \ 1067 .has_64k_pages = 1, \ 1068 .has_guc_deprivilege = 1, \ 1069 .has_heci_pxp = 1, \ 1070 .has_media_ratio_mode = 1, \ 1071 .display.has_cdclk_squash = 1, \ 1072 .__runtime.platform_engine_mask = \ 1073 BIT(RCS0) | BIT(BCS0) | \ 1074 BIT(VECS0) | BIT(VECS1) | \ 1075 BIT(VCS0) | BIT(VCS2) | \ 1076 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3) 1077 1078 static const struct intel_device_info dg2_info = { 1079 DG2_FEATURES, 1080 XE_LPD_FEATURES, 1081 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 1082 BIT(TRANSCODER_C) | BIT(TRANSCODER_D), 1083 }; 1084 1085 static const struct intel_device_info ats_m_info = { 1086 DG2_FEATURES, 1087 NO_DISPLAY, 1088 .require_force_probe = 1, 1089 .tuning_thread_rr_after_dep = 1, 1090 }; 1091 1092 #define XE_HPC_FEATURES \ 1093 XE_HP_FEATURES, \ 1094 .dma_mask_size = 52, \ 1095 .has_3d_pipeline = 0, \ 1096 .has_guc_deprivilege = 1, \ 1097 .has_l3_ccs_read = 1, \ 1098 .has_mslice_steering = 0, \ 1099 .has_one_eu_per_fuse_bit = 1 1100 1101 __maybe_unused 1102 static const struct intel_device_info pvc_info = { 1103 XE_HPC_FEATURES, 1104 XE_HPM_FEATURES, 1105 DGFX_FEATURES, 1106 .__runtime.graphics.ip.rel = 60, 1107 .__runtime.media.ip.rel = 60, 1108 PLATFORM(INTEL_PONTEVECCHIO), 1109 NO_DISPLAY, 1110 .has_flat_ccs = 0, 1111 .__runtime.platform_engine_mask = 1112 BIT(BCS0) | 1113 BIT(VCS0) | 1114 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3), 1115 .require_force_probe = 1, 1116 }; 1117 1118 #define XE_LPDP_FEATURES \ 1119 XE_LPD_FEATURES, \ 1120 .__runtime.display.ip.ver = 14, \ 1121 .display.has_cdclk_crawl = 1, \ 1122 .display.has_cdclk_squash = 1, \ 1123 .__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B) 1124 1125 static const struct intel_gt_definition xelpmp_extra_gt[] = { 1126 { 1127 .type = GT_MEDIA, 1128 .name = "Standalone Media GT", 1129 .gsi_offset = MTL_MEDIA_GSI_BASE, 1130 .engine_mask = BIT(VECS0) | BIT(VCS0) | BIT(VCS2) | BIT(GSC0), 1131 }, 1132 {} 1133 }; 1134 1135 static const struct intel_device_info mtl_info = { 1136 XE_HP_FEATURES, 1137 XE_LPDP_FEATURES, 1138 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 1139 BIT(TRANSCODER_C) | BIT(TRANSCODER_D), 1140 /* 1141 * Real graphics IP version will be obtained from hardware GMD_ID 1142 * register. Value provided here is just for sanity checking. 1143 */ 1144 .__runtime.graphics.ip.ver = 12, 1145 .__runtime.graphics.ip.rel = 70, 1146 .__runtime.media.ip.ver = 13, 1147 PLATFORM(INTEL_METEORLAKE), 1148 .extra_gt_list = xelpmp_extra_gt, 1149 .has_flat_ccs = 0, 1150 .has_gmd_id = 1, 1151 .has_guc_deprivilege = 1, 1152 .has_llc = 0, 1153 .has_mslice_steering = 0, 1154 .has_snoop = 1, 1155 .__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM, 1156 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0), 1157 .require_force_probe = 1, 1158 }; 1159 1160 #undef PLATFORM 1161 1162 /* 1163 * Make sure any device matches here are from most specific to most 1164 * general. For example, since the Quanta match is based on the subsystem 1165 * and subvendor IDs, we need it to come before the more general IVB 1166 * PCI ID matches, otherwise we'll use the wrong info struct above. 1167 */ 1168 static const struct pci_device_id pciidlist[] = { 1169 INTEL_I830_IDS(&i830_info), 1170 INTEL_I845G_IDS(&i845g_info), 1171 INTEL_I85X_IDS(&i85x_info), 1172 INTEL_I865G_IDS(&i865g_info), 1173 INTEL_I915G_IDS(&i915g_info), 1174 INTEL_I915GM_IDS(&i915gm_info), 1175 INTEL_I945G_IDS(&i945g_info), 1176 INTEL_I945GM_IDS(&i945gm_info), 1177 INTEL_I965G_IDS(&i965g_info), 1178 INTEL_G33_IDS(&g33_info), 1179 INTEL_I965GM_IDS(&i965gm_info), 1180 INTEL_GM45_IDS(&gm45_info), 1181 INTEL_G45_IDS(&g45_info), 1182 INTEL_PINEVIEW_G_IDS(&pnv_g_info), 1183 INTEL_PINEVIEW_M_IDS(&pnv_m_info), 1184 INTEL_IRONLAKE_D_IDS(&ilk_d_info), 1185 INTEL_IRONLAKE_M_IDS(&ilk_m_info), 1186 INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info), 1187 INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info), 1188 INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info), 1189 INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info), 1190 INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */ 1191 INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info), 1192 INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info), 1193 INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info), 1194 INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info), 1195 INTEL_HSW_GT1_IDS(&hsw_gt1_info), 1196 INTEL_HSW_GT2_IDS(&hsw_gt2_info), 1197 INTEL_HSW_GT3_IDS(&hsw_gt3_info), 1198 INTEL_VLV_IDS(&vlv_info), 1199 INTEL_BDW_GT1_IDS(&bdw_gt1_info), 1200 INTEL_BDW_GT2_IDS(&bdw_gt2_info), 1201 INTEL_BDW_GT3_IDS(&bdw_gt3_info), 1202 INTEL_BDW_RSVD_IDS(&bdw_rsvd_info), 1203 INTEL_CHV_IDS(&chv_info), 1204 INTEL_SKL_GT1_IDS(&skl_gt1_info), 1205 INTEL_SKL_GT2_IDS(&skl_gt2_info), 1206 INTEL_SKL_GT3_IDS(&skl_gt3_info), 1207 INTEL_SKL_GT4_IDS(&skl_gt4_info), 1208 INTEL_BXT_IDS(&bxt_info), 1209 INTEL_GLK_IDS(&glk_info), 1210 INTEL_KBL_GT1_IDS(&kbl_gt1_info), 1211 INTEL_KBL_GT2_IDS(&kbl_gt2_info), 1212 INTEL_KBL_GT3_IDS(&kbl_gt3_info), 1213 INTEL_KBL_GT4_IDS(&kbl_gt3_info), 1214 INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info), 1215 INTEL_CFL_S_GT1_IDS(&cfl_gt1_info), 1216 INTEL_CFL_S_GT2_IDS(&cfl_gt2_info), 1217 INTEL_CFL_H_GT1_IDS(&cfl_gt1_info), 1218 INTEL_CFL_H_GT2_IDS(&cfl_gt2_info), 1219 INTEL_CFL_U_GT2_IDS(&cfl_gt2_info), 1220 INTEL_CFL_U_GT3_IDS(&cfl_gt3_info), 1221 INTEL_WHL_U_GT1_IDS(&cfl_gt1_info), 1222 INTEL_WHL_U_GT2_IDS(&cfl_gt2_info), 1223 INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info), 1224 INTEL_WHL_U_GT3_IDS(&cfl_gt3_info), 1225 INTEL_CML_GT1_IDS(&cml_gt1_info), 1226 INTEL_CML_GT2_IDS(&cml_gt2_info), 1227 INTEL_CML_U_GT1_IDS(&cml_gt1_info), 1228 INTEL_CML_U_GT2_IDS(&cml_gt2_info), 1229 INTEL_ICL_11_IDS(&icl_info), 1230 INTEL_EHL_IDS(&ehl_info), 1231 INTEL_JSL_IDS(&jsl_info), 1232 INTEL_TGL_12_IDS(&tgl_info), 1233 INTEL_RKL_IDS(&rkl_info), 1234 INTEL_ADLS_IDS(&adl_s_info), 1235 INTEL_ADLP_IDS(&adl_p_info), 1236 INTEL_ADLN_IDS(&adl_p_info), 1237 INTEL_DG1_IDS(&dg1_info), 1238 INTEL_RPLS_IDS(&adl_s_info), 1239 INTEL_RPLP_IDS(&adl_p_info), 1240 INTEL_DG2_IDS(&dg2_info), 1241 INTEL_ATS_M_IDS(&ats_m_info), 1242 INTEL_MTL_IDS(&mtl_info), 1243 {0, 0, 0} 1244 }; 1245 MODULE_DEVICE_TABLE(pci, pciidlist); 1246 1247 static void i915_pci_remove(struct pci_dev *pdev) 1248 { 1249 struct drm_i915_private *i915; 1250 1251 i915 = pci_get_drvdata(pdev); 1252 if (!i915) /* driver load aborted, nothing to cleanup */ 1253 return; 1254 1255 i915_driver_remove(i915); 1256 pci_set_drvdata(pdev, NULL); 1257 } 1258 1259 /* is device_id present in comma separated list of ids */ 1260 static bool device_id_in_list(u16 device_id, const char *devices, bool negative) 1261 { 1262 char *s, *p, *tok; 1263 bool ret; 1264 1265 if (!devices || !*devices) 1266 return false; 1267 1268 /* match everything */ 1269 if (negative && strcmp(devices, "!*") == 0) 1270 return true; 1271 if (!negative && strcmp(devices, "*") == 0) 1272 return true; 1273 1274 s = kstrdup(devices, GFP_KERNEL); 1275 if (!s) 1276 return false; 1277 1278 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) { 1279 u16 val; 1280 1281 if (negative && tok[0] == '!') 1282 tok++; 1283 else if ((negative && tok[0] != '!') || 1284 (!negative && tok[0] == '!')) 1285 continue; 1286 1287 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) { 1288 ret = true; 1289 break; 1290 } 1291 } 1292 1293 kfree(s); 1294 1295 return ret; 1296 } 1297 1298 static bool id_forced(u16 device_id) 1299 { 1300 return device_id_in_list(device_id, i915_modparams.force_probe, false); 1301 } 1302 1303 static bool id_blocked(u16 device_id) 1304 { 1305 return device_id_in_list(device_id, i915_modparams.force_probe, true); 1306 } 1307 1308 bool i915_pci_resource_valid(struct pci_dev *pdev, int bar) 1309 { 1310 if (!pci_resource_flags(pdev, bar)) 1311 return false; 1312 1313 if (pci_resource_flags(pdev, bar) & IORESOURCE_UNSET) 1314 return false; 1315 1316 if (!pci_resource_len(pdev, bar)) 1317 return false; 1318 1319 return true; 1320 } 1321 1322 static bool intel_mmio_bar_valid(struct pci_dev *pdev, struct intel_device_info *intel_info) 1323 { 1324 return i915_pci_resource_valid(pdev, intel_mmio_bar(intel_info->__runtime.graphics.ip.ver)); 1325 } 1326 1327 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1328 { 1329 struct intel_device_info *intel_info = 1330 (struct intel_device_info *) ent->driver_data; 1331 int err; 1332 1333 if (intel_info->require_force_probe && !id_forced(pdev->device)) { 1334 dev_info(&pdev->dev, 1335 "Your graphics device %04x is not properly supported by i915 in this\n" 1336 "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n" 1337 "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n" 1338 "or (recommended) check for kernel updates.\n", 1339 pdev->device, pdev->device, pdev->device); 1340 return -ENODEV; 1341 } 1342 1343 if (id_blocked(pdev->device)) { 1344 dev_info(&pdev->dev, "I915 probe blocked for Device ID %04x.\n", 1345 pdev->device); 1346 return -ENODEV; 1347 } 1348 1349 if (intel_info->require_force_probe) { 1350 dev_info(&pdev->dev, "Force probing unsupported Device ID %04x, tainting kernel\n", 1351 pdev->device); 1352 add_taint(TAINT_USER, LOCKDEP_STILL_OK); 1353 } 1354 1355 /* Only bind to function 0 of the device. Early generations 1356 * used function 1 as a placeholder for multi-head. This causes 1357 * us confusion instead, especially on the systems where both 1358 * functions have the same PCI-ID! 1359 */ 1360 if (PCI_FUNC(pdev->devfn)) 1361 return -ENODEV; 1362 1363 if (!intel_mmio_bar_valid(pdev, intel_info)) 1364 return -ENXIO; 1365 1366 /* Detect if we need to wait for other drivers early on */ 1367 if (intel_display_driver_probe_defer(pdev)) 1368 return -EPROBE_DEFER; 1369 1370 err = i915_driver_probe(pdev, ent); 1371 if (err) 1372 return err; 1373 1374 if (i915_inject_probe_failure(pci_get_drvdata(pdev))) { 1375 i915_pci_remove(pdev); 1376 return -ENODEV; 1377 } 1378 1379 err = i915_live_selftests(pdev); 1380 if (err) { 1381 i915_pci_remove(pdev); 1382 return err > 0 ? -ENOTTY : err; 1383 } 1384 1385 err = i915_perf_selftests(pdev); 1386 if (err) { 1387 i915_pci_remove(pdev); 1388 return err > 0 ? -ENOTTY : err; 1389 } 1390 1391 return 0; 1392 } 1393 1394 static void i915_pci_shutdown(struct pci_dev *pdev) 1395 { 1396 struct drm_i915_private *i915 = pci_get_drvdata(pdev); 1397 1398 i915_driver_shutdown(i915); 1399 } 1400 1401 static struct pci_driver i915_pci_driver = { 1402 .name = DRIVER_NAME, 1403 .id_table = pciidlist, 1404 .probe = i915_pci_probe, 1405 .remove = i915_pci_remove, 1406 .shutdown = i915_pci_shutdown, 1407 .driver.pm = &i915_pm_ops, 1408 }; 1409 1410 int i915_pci_register_driver(void) 1411 { 1412 return pci_register_driver(&i915_pci_driver); 1413 } 1414 1415 void i915_pci_unregister_driver(void) 1416 { 1417 pci_unregister_driver(&i915_pci_driver); 1418 } 1419