1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/console.h> 26 #include <linux/vgaarb.h> 27 #include <linux/vga_switcheroo.h> 28 29 #include <drm/drm_drv.h> 30 31 #include "i915_drv.h" 32 #include "i915_globals.h" 33 #include "i915_selftest.h" 34 #include "intel_fbdev.h" 35 36 #define PLATFORM(x) .platform = (x) 37 #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1) 38 39 #define I845_PIPE_OFFSETS \ 40 .pipe_offsets = { \ 41 [TRANSCODER_A] = PIPE_A_OFFSET, \ 42 }, \ 43 .trans_offsets = { \ 44 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 45 } 46 47 #define I9XX_PIPE_OFFSETS \ 48 .pipe_offsets = { \ 49 [TRANSCODER_A] = PIPE_A_OFFSET, \ 50 [TRANSCODER_B] = PIPE_B_OFFSET, \ 51 }, \ 52 .trans_offsets = { \ 53 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 54 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 55 } 56 57 #define IVB_PIPE_OFFSETS \ 58 .pipe_offsets = { \ 59 [TRANSCODER_A] = PIPE_A_OFFSET, \ 60 [TRANSCODER_B] = PIPE_B_OFFSET, \ 61 [TRANSCODER_C] = PIPE_C_OFFSET, \ 62 }, \ 63 .trans_offsets = { \ 64 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 65 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 66 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 67 } 68 69 #define HSW_PIPE_OFFSETS \ 70 .pipe_offsets = { \ 71 [TRANSCODER_A] = PIPE_A_OFFSET, \ 72 [TRANSCODER_B] = PIPE_B_OFFSET, \ 73 [TRANSCODER_C] = PIPE_C_OFFSET, \ 74 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 75 }, \ 76 .trans_offsets = { \ 77 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 78 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 79 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 80 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 81 } 82 83 #define CHV_PIPE_OFFSETS \ 84 .pipe_offsets = { \ 85 [TRANSCODER_A] = PIPE_A_OFFSET, \ 86 [TRANSCODER_B] = PIPE_B_OFFSET, \ 87 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \ 88 }, \ 89 .trans_offsets = { \ 90 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 91 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 92 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \ 93 } 94 95 #define I845_CURSOR_OFFSETS \ 96 .cursor_offsets = { \ 97 [PIPE_A] = CURSOR_A_OFFSET, \ 98 } 99 100 #define I9XX_CURSOR_OFFSETS \ 101 .cursor_offsets = { \ 102 [PIPE_A] = CURSOR_A_OFFSET, \ 103 [PIPE_B] = CURSOR_B_OFFSET, \ 104 } 105 106 #define CHV_CURSOR_OFFSETS \ 107 .cursor_offsets = { \ 108 [PIPE_A] = CURSOR_A_OFFSET, \ 109 [PIPE_B] = CURSOR_B_OFFSET, \ 110 [PIPE_C] = CHV_CURSOR_C_OFFSET, \ 111 } 112 113 #define IVB_CURSOR_OFFSETS \ 114 .cursor_offsets = { \ 115 [PIPE_A] = CURSOR_A_OFFSET, \ 116 [PIPE_B] = IVB_CURSOR_B_OFFSET, \ 117 [PIPE_C] = IVB_CURSOR_C_OFFSET, \ 118 } 119 120 #define I9XX_COLORS \ 121 .color = { .gamma_lut_size = 256 } 122 #define I965_COLORS \ 123 .color = { .gamma_lut_size = 129, \ 124 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 125 } 126 #define ILK_COLORS \ 127 .color = { .gamma_lut_size = 1024 } 128 #define IVB_COLORS \ 129 .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 } 130 #define CHV_COLORS \ 131 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \ 132 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 133 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \ 134 } 135 #define GLK_COLORS \ 136 .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \ 137 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ 138 DRM_COLOR_LUT_EQUAL_CHANNELS, \ 139 } 140 141 /* Keep in gen based order, and chronological order within a gen */ 142 143 #define GEN_DEFAULT_PAGE_SIZES \ 144 .page_sizes = I915_GTT_PAGE_SIZE_4K 145 146 #define I830_FEATURES \ 147 GEN(2), \ 148 .is_mobile = 1, \ 149 .num_pipes = 2, \ 150 .display.has_overlay = 1, \ 151 .display.cursor_needs_physical = 1, \ 152 .display.overlay_needs_physical = 1, \ 153 .display.has_gmch = 1, \ 154 .gpu_reset_clobbers_display = true, \ 155 .hws_needs_physical = 1, \ 156 .unfenced_needs_alignment = 1, \ 157 .engine_mask = BIT(RCS0), \ 158 .has_snoop = true, \ 159 .has_coherent_ggtt = false, \ 160 I9XX_PIPE_OFFSETS, \ 161 I9XX_CURSOR_OFFSETS, \ 162 I9XX_COLORS, \ 163 GEN_DEFAULT_PAGE_SIZES 164 165 #define I845_FEATURES \ 166 GEN(2), \ 167 .num_pipes = 1, \ 168 .display.has_overlay = 1, \ 169 .display.overlay_needs_physical = 1, \ 170 .display.has_gmch = 1, \ 171 .gpu_reset_clobbers_display = true, \ 172 .hws_needs_physical = 1, \ 173 .unfenced_needs_alignment = 1, \ 174 .engine_mask = BIT(RCS0), \ 175 .has_snoop = true, \ 176 .has_coherent_ggtt = false, \ 177 I845_PIPE_OFFSETS, \ 178 I845_CURSOR_OFFSETS, \ 179 I9XX_COLORS, \ 180 GEN_DEFAULT_PAGE_SIZES 181 182 static const struct intel_device_info intel_i830_info = { 183 I830_FEATURES, 184 PLATFORM(INTEL_I830), 185 }; 186 187 static const struct intel_device_info intel_i845g_info = { 188 I845_FEATURES, 189 PLATFORM(INTEL_I845G), 190 }; 191 192 static const struct intel_device_info intel_i85x_info = { 193 I830_FEATURES, 194 PLATFORM(INTEL_I85X), 195 .display.has_fbc = 1, 196 }; 197 198 static const struct intel_device_info intel_i865g_info = { 199 I845_FEATURES, 200 PLATFORM(INTEL_I865G), 201 }; 202 203 #define GEN3_FEATURES \ 204 GEN(3), \ 205 .num_pipes = 2, \ 206 .display.has_gmch = 1, \ 207 .gpu_reset_clobbers_display = true, \ 208 .engine_mask = BIT(RCS0), \ 209 .has_snoop = true, \ 210 .has_coherent_ggtt = true, \ 211 I9XX_PIPE_OFFSETS, \ 212 I9XX_CURSOR_OFFSETS, \ 213 I9XX_COLORS, \ 214 GEN_DEFAULT_PAGE_SIZES 215 216 static const struct intel_device_info intel_i915g_info = { 217 GEN3_FEATURES, 218 PLATFORM(INTEL_I915G), 219 .has_coherent_ggtt = false, 220 .display.cursor_needs_physical = 1, 221 .display.has_overlay = 1, 222 .display.overlay_needs_physical = 1, 223 .hws_needs_physical = 1, 224 .unfenced_needs_alignment = 1, 225 }; 226 227 static const struct intel_device_info intel_i915gm_info = { 228 GEN3_FEATURES, 229 PLATFORM(INTEL_I915GM), 230 .is_mobile = 1, 231 .display.cursor_needs_physical = 1, 232 .display.has_overlay = 1, 233 .display.overlay_needs_physical = 1, 234 .display.supports_tv = 1, 235 .display.has_fbc = 1, 236 .hws_needs_physical = 1, 237 .unfenced_needs_alignment = 1, 238 }; 239 240 static const struct intel_device_info intel_i945g_info = { 241 GEN3_FEATURES, 242 PLATFORM(INTEL_I945G), 243 .display.has_hotplug = 1, 244 .display.cursor_needs_physical = 1, 245 .display.has_overlay = 1, 246 .display.overlay_needs_physical = 1, 247 .hws_needs_physical = 1, 248 .unfenced_needs_alignment = 1, 249 }; 250 251 static const struct intel_device_info intel_i945gm_info = { 252 GEN3_FEATURES, 253 PLATFORM(INTEL_I945GM), 254 .is_mobile = 1, 255 .display.has_hotplug = 1, 256 .display.cursor_needs_physical = 1, 257 .display.has_overlay = 1, 258 .display.overlay_needs_physical = 1, 259 .display.supports_tv = 1, 260 .display.has_fbc = 1, 261 .hws_needs_physical = 1, 262 .unfenced_needs_alignment = 1, 263 }; 264 265 static const struct intel_device_info intel_g33_info = { 266 GEN3_FEATURES, 267 PLATFORM(INTEL_G33), 268 .display.has_hotplug = 1, 269 .display.has_overlay = 1, 270 }; 271 272 static const struct intel_device_info intel_pineview_g_info = { 273 GEN3_FEATURES, 274 PLATFORM(INTEL_PINEVIEW), 275 .display.has_hotplug = 1, 276 .display.has_overlay = 1, 277 }; 278 279 static const struct intel_device_info intel_pineview_m_info = { 280 GEN3_FEATURES, 281 PLATFORM(INTEL_PINEVIEW), 282 .is_mobile = 1, 283 .display.has_hotplug = 1, 284 .display.has_overlay = 1, 285 }; 286 287 #define GEN4_FEATURES \ 288 GEN(4), \ 289 .num_pipes = 2, \ 290 .display.has_hotplug = 1, \ 291 .display.has_gmch = 1, \ 292 .gpu_reset_clobbers_display = true, \ 293 .engine_mask = BIT(RCS0), \ 294 .has_snoop = true, \ 295 .has_coherent_ggtt = true, \ 296 I9XX_PIPE_OFFSETS, \ 297 I9XX_CURSOR_OFFSETS, \ 298 I965_COLORS, \ 299 GEN_DEFAULT_PAGE_SIZES 300 301 static const struct intel_device_info intel_i965g_info = { 302 GEN4_FEATURES, 303 PLATFORM(INTEL_I965G), 304 .display.has_overlay = 1, 305 .hws_needs_physical = 1, 306 .has_snoop = false, 307 }; 308 309 static const struct intel_device_info intel_i965gm_info = { 310 GEN4_FEATURES, 311 PLATFORM(INTEL_I965GM), 312 .is_mobile = 1, 313 .display.has_fbc = 1, 314 .display.has_overlay = 1, 315 .display.supports_tv = 1, 316 .hws_needs_physical = 1, 317 .has_snoop = false, 318 }; 319 320 static const struct intel_device_info intel_g45_info = { 321 GEN4_FEATURES, 322 PLATFORM(INTEL_G45), 323 .engine_mask = BIT(RCS0) | BIT(VCS0), 324 .gpu_reset_clobbers_display = false, 325 }; 326 327 static const struct intel_device_info intel_gm45_info = { 328 GEN4_FEATURES, 329 PLATFORM(INTEL_GM45), 330 .is_mobile = 1, 331 .display.has_fbc = 1, 332 .display.supports_tv = 1, 333 .engine_mask = BIT(RCS0) | BIT(VCS0), 334 .gpu_reset_clobbers_display = false, 335 }; 336 337 #define GEN5_FEATURES \ 338 GEN(5), \ 339 .num_pipes = 2, \ 340 .display.has_hotplug = 1, \ 341 .engine_mask = BIT(RCS0) | BIT(VCS0), \ 342 .has_snoop = true, \ 343 .has_coherent_ggtt = true, \ 344 /* ilk does support rc6, but we do not implement [power] contexts */ \ 345 .has_rc6 = 0, \ 346 I9XX_PIPE_OFFSETS, \ 347 I9XX_CURSOR_OFFSETS, \ 348 ILK_COLORS, \ 349 GEN_DEFAULT_PAGE_SIZES 350 351 static const struct intel_device_info intel_ironlake_d_info = { 352 GEN5_FEATURES, 353 PLATFORM(INTEL_IRONLAKE), 354 }; 355 356 static const struct intel_device_info intel_ironlake_m_info = { 357 GEN5_FEATURES, 358 PLATFORM(INTEL_IRONLAKE), 359 .is_mobile = 1, 360 .display.has_fbc = 1, 361 }; 362 363 #define GEN6_FEATURES \ 364 GEN(6), \ 365 .num_pipes = 2, \ 366 .display.has_hotplug = 1, \ 367 .display.has_fbc = 1, \ 368 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ 369 .has_coherent_ggtt = true, \ 370 .has_llc = 1, \ 371 .has_rc6 = 1, \ 372 .has_rc6p = 1, \ 373 .ppgtt_type = INTEL_PPGTT_ALIASING, \ 374 .ppgtt_size = 31, \ 375 I9XX_PIPE_OFFSETS, \ 376 I9XX_CURSOR_OFFSETS, \ 377 ILK_COLORS, \ 378 GEN_DEFAULT_PAGE_SIZES 379 380 #define SNB_D_PLATFORM \ 381 GEN6_FEATURES, \ 382 PLATFORM(INTEL_SANDYBRIDGE) 383 384 static const struct intel_device_info intel_sandybridge_d_gt1_info = { 385 SNB_D_PLATFORM, 386 .gt = 1, 387 }; 388 389 static const struct intel_device_info intel_sandybridge_d_gt2_info = { 390 SNB_D_PLATFORM, 391 .gt = 2, 392 }; 393 394 #define SNB_M_PLATFORM \ 395 GEN6_FEATURES, \ 396 PLATFORM(INTEL_SANDYBRIDGE), \ 397 .is_mobile = 1 398 399 400 static const struct intel_device_info intel_sandybridge_m_gt1_info = { 401 SNB_M_PLATFORM, 402 .gt = 1, 403 }; 404 405 static const struct intel_device_info intel_sandybridge_m_gt2_info = { 406 SNB_M_PLATFORM, 407 .gt = 2, 408 }; 409 410 #define GEN7_FEATURES \ 411 GEN(7), \ 412 .num_pipes = 3, \ 413 .display.has_hotplug = 1, \ 414 .display.has_fbc = 1, \ 415 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ 416 .has_coherent_ggtt = true, \ 417 .has_llc = 1, \ 418 .has_rc6 = 1, \ 419 .has_rc6p = 1, \ 420 .ppgtt_type = INTEL_PPGTT_FULL, \ 421 .ppgtt_size = 31, \ 422 IVB_PIPE_OFFSETS, \ 423 IVB_CURSOR_OFFSETS, \ 424 IVB_COLORS, \ 425 GEN_DEFAULT_PAGE_SIZES 426 427 #define IVB_D_PLATFORM \ 428 GEN7_FEATURES, \ 429 PLATFORM(INTEL_IVYBRIDGE), \ 430 .has_l3_dpf = 1 431 432 static const struct intel_device_info intel_ivybridge_d_gt1_info = { 433 IVB_D_PLATFORM, 434 .gt = 1, 435 }; 436 437 static const struct intel_device_info intel_ivybridge_d_gt2_info = { 438 IVB_D_PLATFORM, 439 .gt = 2, 440 }; 441 442 #define IVB_M_PLATFORM \ 443 GEN7_FEATURES, \ 444 PLATFORM(INTEL_IVYBRIDGE), \ 445 .is_mobile = 1, \ 446 .has_l3_dpf = 1 447 448 static const struct intel_device_info intel_ivybridge_m_gt1_info = { 449 IVB_M_PLATFORM, 450 .gt = 1, 451 }; 452 453 static const struct intel_device_info intel_ivybridge_m_gt2_info = { 454 IVB_M_PLATFORM, 455 .gt = 2, 456 }; 457 458 static const struct intel_device_info intel_ivybridge_q_info = { 459 GEN7_FEATURES, 460 PLATFORM(INTEL_IVYBRIDGE), 461 .gt = 2, 462 .num_pipes = 0, /* legal, last one wins */ 463 .has_l3_dpf = 1, 464 }; 465 466 static const struct intel_device_info intel_valleyview_info = { 467 PLATFORM(INTEL_VALLEYVIEW), 468 GEN(7), 469 .is_lp = 1, 470 .num_pipes = 2, 471 .has_runtime_pm = 1, 472 .has_rc6 = 1, 473 .display.has_gmch = 1, 474 .display.has_hotplug = 1, 475 .ppgtt_type = INTEL_PPGTT_FULL, 476 .ppgtt_size = 31, 477 .has_snoop = true, 478 .has_coherent_ggtt = false, 479 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), 480 .display_mmio_offset = VLV_DISPLAY_BASE, 481 I9XX_PIPE_OFFSETS, 482 I9XX_CURSOR_OFFSETS, 483 I965_COLORS, 484 GEN_DEFAULT_PAGE_SIZES, 485 }; 486 487 #define G75_FEATURES \ 488 GEN7_FEATURES, \ 489 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ 490 .display.has_ddi = 1, \ 491 .has_fpga_dbg = 1, \ 492 .display.has_psr = 1, \ 493 .display.has_dp_mst = 1, \ 494 .has_rc6p = 0 /* RC6p removed-by HSW */, \ 495 HSW_PIPE_OFFSETS, \ 496 .has_runtime_pm = 1 497 498 #define HSW_PLATFORM \ 499 G75_FEATURES, \ 500 PLATFORM(INTEL_HASWELL), \ 501 .has_l3_dpf = 1 502 503 static const struct intel_device_info intel_haswell_gt1_info = { 504 HSW_PLATFORM, 505 .gt = 1, 506 }; 507 508 static const struct intel_device_info intel_haswell_gt2_info = { 509 HSW_PLATFORM, 510 .gt = 2, 511 }; 512 513 static const struct intel_device_info intel_haswell_gt3_info = { 514 HSW_PLATFORM, 515 .gt = 3, 516 }; 517 518 #define GEN8_FEATURES \ 519 G75_FEATURES, \ 520 GEN(8), \ 521 .page_sizes = I915_GTT_PAGE_SIZE_4K | \ 522 I915_GTT_PAGE_SIZE_2M, \ 523 .has_logical_ring_contexts = 1, \ 524 .ppgtt_type = INTEL_PPGTT_FULL, \ 525 .ppgtt_size = 48, \ 526 .has_64bit_reloc = 1, \ 527 .has_reset_engine = 1 528 529 #define BDW_PLATFORM \ 530 GEN8_FEATURES, \ 531 PLATFORM(INTEL_BROADWELL) 532 533 static const struct intel_device_info intel_broadwell_gt1_info = { 534 BDW_PLATFORM, 535 .gt = 1, 536 }; 537 538 static const struct intel_device_info intel_broadwell_gt2_info = { 539 BDW_PLATFORM, 540 .gt = 2, 541 }; 542 543 static const struct intel_device_info intel_broadwell_rsvd_info = { 544 BDW_PLATFORM, 545 .gt = 3, 546 /* According to the device ID those devices are GT3, they were 547 * previously treated as not GT3, keep it like that. 548 */ 549 }; 550 551 static const struct intel_device_info intel_broadwell_gt3_info = { 552 BDW_PLATFORM, 553 .gt = 3, 554 .engine_mask = 555 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 556 }; 557 558 static const struct intel_device_info intel_cherryview_info = { 559 PLATFORM(INTEL_CHERRYVIEW), 560 GEN(8), 561 .num_pipes = 3, 562 .display.has_hotplug = 1, 563 .is_lp = 1, 564 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), 565 .has_64bit_reloc = 1, 566 .has_runtime_pm = 1, 567 .has_rc6 = 1, 568 .has_logical_ring_contexts = 1, 569 .display.has_gmch = 1, 570 .ppgtt_type = INTEL_PPGTT_FULL, 571 .ppgtt_size = 32, 572 .has_reset_engine = 1, 573 .has_snoop = true, 574 .has_coherent_ggtt = false, 575 .display_mmio_offset = VLV_DISPLAY_BASE, 576 CHV_PIPE_OFFSETS, 577 CHV_CURSOR_OFFSETS, 578 CHV_COLORS, 579 GEN_DEFAULT_PAGE_SIZES, 580 }; 581 582 #define GEN9_DEFAULT_PAGE_SIZES \ 583 .page_sizes = I915_GTT_PAGE_SIZE_4K | \ 584 I915_GTT_PAGE_SIZE_64K | \ 585 I915_GTT_PAGE_SIZE_2M 586 587 #define GEN9_FEATURES \ 588 GEN8_FEATURES, \ 589 GEN(9), \ 590 GEN9_DEFAULT_PAGE_SIZES, \ 591 .has_logical_ring_preemption = 1, \ 592 .display.has_csr = 1, \ 593 .has_guc = 1, \ 594 .display.has_ipc = 1, \ 595 .ddb_size = 896 596 597 #define SKL_PLATFORM \ 598 GEN9_FEATURES, \ 599 /* Display WA #0477 WaDisableIPC: skl */ \ 600 .display.has_ipc = 0, \ 601 PLATFORM(INTEL_SKYLAKE) 602 603 static const struct intel_device_info intel_skylake_gt1_info = { 604 SKL_PLATFORM, 605 .gt = 1, 606 }; 607 608 static const struct intel_device_info intel_skylake_gt2_info = { 609 SKL_PLATFORM, 610 .gt = 2, 611 }; 612 613 #define SKL_GT3_PLUS_PLATFORM \ 614 SKL_PLATFORM, \ 615 .engine_mask = \ 616 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1) 617 618 619 static const struct intel_device_info intel_skylake_gt3_info = { 620 SKL_GT3_PLUS_PLATFORM, 621 .gt = 3, 622 }; 623 624 static const struct intel_device_info intel_skylake_gt4_info = { 625 SKL_GT3_PLUS_PLATFORM, 626 .gt = 4, 627 }; 628 629 #define GEN9_LP_FEATURES \ 630 GEN(9), \ 631 .is_lp = 1, \ 632 .display.has_hotplug = 1, \ 633 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ 634 .num_pipes = 3, \ 635 .has_64bit_reloc = 1, \ 636 .display.has_ddi = 1, \ 637 .has_fpga_dbg = 1, \ 638 .display.has_fbc = 1, \ 639 .display.has_psr = 1, \ 640 .has_runtime_pm = 1, \ 641 .display.has_csr = 1, \ 642 .has_rc6 = 1, \ 643 .display.has_dp_mst = 1, \ 644 .has_logical_ring_contexts = 1, \ 645 .has_logical_ring_preemption = 1, \ 646 .has_guc = 1, \ 647 .ppgtt_type = INTEL_PPGTT_FULL, \ 648 .ppgtt_size = 48, \ 649 .has_reset_engine = 1, \ 650 .has_snoop = true, \ 651 .has_coherent_ggtt = false, \ 652 .display.has_ipc = 1, \ 653 HSW_PIPE_OFFSETS, \ 654 IVB_CURSOR_OFFSETS, \ 655 IVB_COLORS, \ 656 GEN9_DEFAULT_PAGE_SIZES 657 658 static const struct intel_device_info intel_broxton_info = { 659 GEN9_LP_FEATURES, 660 PLATFORM(INTEL_BROXTON), 661 .ddb_size = 512, 662 }; 663 664 static const struct intel_device_info intel_geminilake_info = { 665 GEN9_LP_FEATURES, 666 PLATFORM(INTEL_GEMINILAKE), 667 .ddb_size = 1024, 668 GLK_COLORS, 669 }; 670 671 #define KBL_PLATFORM \ 672 GEN9_FEATURES, \ 673 PLATFORM(INTEL_KABYLAKE) 674 675 static const struct intel_device_info intel_kabylake_gt1_info = { 676 KBL_PLATFORM, 677 .gt = 1, 678 }; 679 680 static const struct intel_device_info intel_kabylake_gt2_info = { 681 KBL_PLATFORM, 682 .gt = 2, 683 }; 684 685 static const struct intel_device_info intel_kabylake_gt3_info = { 686 KBL_PLATFORM, 687 .gt = 3, 688 .engine_mask = 689 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 690 }; 691 692 #define CFL_PLATFORM \ 693 GEN9_FEATURES, \ 694 PLATFORM(INTEL_COFFEELAKE) 695 696 static const struct intel_device_info intel_coffeelake_gt1_info = { 697 CFL_PLATFORM, 698 .gt = 1, 699 }; 700 701 static const struct intel_device_info intel_coffeelake_gt2_info = { 702 CFL_PLATFORM, 703 .gt = 2, 704 }; 705 706 static const struct intel_device_info intel_coffeelake_gt3_info = { 707 CFL_PLATFORM, 708 .gt = 3, 709 .engine_mask = 710 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), 711 }; 712 713 #define GEN10_FEATURES \ 714 GEN9_FEATURES, \ 715 GEN(10), \ 716 .ddb_size = 1024, \ 717 .has_coherent_ggtt = false, \ 718 GLK_COLORS 719 720 static const struct intel_device_info intel_cannonlake_info = { 721 GEN10_FEATURES, 722 PLATFORM(INTEL_CANNONLAKE), 723 .gt = 2, 724 }; 725 726 #define GEN11_FEATURES \ 727 GEN10_FEATURES, \ 728 .pipe_offsets = { \ 729 [TRANSCODER_A] = PIPE_A_OFFSET, \ 730 [TRANSCODER_B] = PIPE_B_OFFSET, \ 731 [TRANSCODER_C] = PIPE_C_OFFSET, \ 732 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \ 733 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ 734 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ 735 }, \ 736 .trans_offsets = { \ 737 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 738 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ 739 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ 740 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \ 741 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ 742 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ 743 }, \ 744 GEN(11), \ 745 .ddb_size = 2048, \ 746 .has_logical_ring_elsq = 1, \ 747 .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024 } 748 749 static const struct intel_device_info intel_icelake_11_info = { 750 GEN11_FEATURES, 751 PLATFORM(INTEL_ICELAKE), 752 .engine_mask = 753 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), 754 }; 755 756 static const struct intel_device_info intel_elkhartlake_info = { 757 GEN11_FEATURES, 758 PLATFORM(INTEL_ELKHARTLAKE), 759 .is_alpha_support = 1, 760 .engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0), 761 .ppgtt_size = 36, 762 }; 763 764 #undef GEN 765 #undef PLATFORM 766 767 /* 768 * Make sure any device matches here are from most specific to most 769 * general. For example, since the Quanta match is based on the subsystem 770 * and subvendor IDs, we need it to come before the more general IVB 771 * PCI ID matches, otherwise we'll use the wrong info struct above. 772 */ 773 static const struct pci_device_id pciidlist[] = { 774 INTEL_I830_IDS(&intel_i830_info), 775 INTEL_I845G_IDS(&intel_i845g_info), 776 INTEL_I85X_IDS(&intel_i85x_info), 777 INTEL_I865G_IDS(&intel_i865g_info), 778 INTEL_I915G_IDS(&intel_i915g_info), 779 INTEL_I915GM_IDS(&intel_i915gm_info), 780 INTEL_I945G_IDS(&intel_i945g_info), 781 INTEL_I945GM_IDS(&intel_i945gm_info), 782 INTEL_I965G_IDS(&intel_i965g_info), 783 INTEL_G33_IDS(&intel_g33_info), 784 INTEL_I965GM_IDS(&intel_i965gm_info), 785 INTEL_GM45_IDS(&intel_gm45_info), 786 INTEL_G45_IDS(&intel_g45_info), 787 INTEL_PINEVIEW_G_IDS(&intel_pineview_g_info), 788 INTEL_PINEVIEW_M_IDS(&intel_pineview_m_info), 789 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), 790 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), 791 INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info), 792 INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info), 793 INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info), 794 INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info), 795 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ 796 INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info), 797 INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info), 798 INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info), 799 INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info), 800 INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info), 801 INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info), 802 INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info), 803 INTEL_VLV_IDS(&intel_valleyview_info), 804 INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info), 805 INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info), 806 INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info), 807 INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info), 808 INTEL_CHV_IDS(&intel_cherryview_info), 809 INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info), 810 INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info), 811 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), 812 INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info), 813 INTEL_BXT_IDS(&intel_broxton_info), 814 INTEL_GLK_IDS(&intel_geminilake_info), 815 INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info), 816 INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info), 817 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info), 818 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info), 819 INTEL_AML_KBL_GT2_IDS(&intel_kabylake_gt2_info), 820 INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info), 821 INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info), 822 INTEL_CFL_H_GT1_IDS(&intel_coffeelake_gt1_info), 823 INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info), 824 INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info), 825 INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info), 826 INTEL_WHL_U_GT1_IDS(&intel_coffeelake_gt1_info), 827 INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info), 828 INTEL_AML_CFL_GT2_IDS(&intel_coffeelake_gt2_info), 829 INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info), 830 INTEL_CML_GT1_IDS(&intel_coffeelake_gt1_info), 831 INTEL_CML_GT2_IDS(&intel_coffeelake_gt2_info), 832 INTEL_CNL_IDS(&intel_cannonlake_info), 833 INTEL_ICL_11_IDS(&intel_icelake_11_info), 834 INTEL_EHL_IDS(&intel_elkhartlake_info), 835 {0, 0, 0} 836 }; 837 MODULE_DEVICE_TABLE(pci, pciidlist); 838 839 static void i915_pci_remove(struct pci_dev *pdev) 840 { 841 struct drm_device *dev; 842 843 dev = pci_get_drvdata(pdev); 844 if (!dev) /* driver load aborted, nothing to cleanup */ 845 return; 846 847 i915_driver_unload(dev); 848 drm_dev_put(dev); 849 850 pci_set_drvdata(pdev, NULL); 851 } 852 853 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 854 { 855 struct intel_device_info *intel_info = 856 (struct intel_device_info *) ent->driver_data; 857 int err; 858 859 if (IS_ALPHA_SUPPORT(intel_info) && !i915_modparams.alpha_support) { 860 DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n" 861 "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n" 862 "to enable support in this kernel version, or check for kernel updates.\n"); 863 return -ENODEV; 864 } 865 866 /* Only bind to function 0 of the device. Early generations 867 * used function 1 as a placeholder for multi-head. This causes 868 * us confusion instead, especially on the systems where both 869 * functions have the same PCI-ID! 870 */ 871 if (PCI_FUNC(pdev->devfn)) 872 return -ENODEV; 873 874 /* 875 * apple-gmux is needed on dual GPU MacBook Pro 876 * to probe the panel if we're the inactive GPU. 877 */ 878 if (vga_switcheroo_client_probe_defer(pdev)) 879 return -EPROBE_DEFER; 880 881 err = i915_driver_load(pdev, ent); 882 if (err) 883 return err; 884 885 if (i915_inject_load_failure()) { 886 i915_pci_remove(pdev); 887 return -ENODEV; 888 } 889 890 err = i915_live_selftests(pdev); 891 if (err) { 892 i915_pci_remove(pdev); 893 return err > 0 ? -ENOTTY : err; 894 } 895 896 return 0; 897 } 898 899 static struct pci_driver i915_pci_driver = { 900 .name = DRIVER_NAME, 901 .id_table = pciidlist, 902 .probe = i915_pci_probe, 903 .remove = i915_pci_remove, 904 .driver.pm = &i915_pm_ops, 905 }; 906 907 static int __init i915_init(void) 908 { 909 bool use_kms = true; 910 int err; 911 912 err = i915_globals_init(); 913 if (err) 914 return err; 915 916 err = i915_mock_selftests(); 917 if (err) 918 return err > 0 ? 0 : err; 919 920 /* 921 * Enable KMS by default, unless explicitly overriden by 922 * either the i915.modeset prarameter or by the 923 * vga_text_mode_force boot option. 924 */ 925 926 if (i915_modparams.modeset == 0) 927 use_kms = false; 928 929 if (vgacon_text_force() && i915_modparams.modeset == -1) 930 use_kms = false; 931 932 if (!use_kms) { 933 /* Silently fail loading to not upset userspace. */ 934 DRM_DEBUG_DRIVER("KMS disabled.\n"); 935 return 0; 936 } 937 938 return pci_register_driver(&i915_pci_driver); 939 } 940 941 static void __exit i915_exit(void) 942 { 943 if (!i915_pci_driver.driver.owner) 944 return; 945 946 pci_unregister_driver(&i915_pci_driver); 947 i915_globals_exit(); 948 } 949 950 module_init(i915_init); 951 module_exit(i915_exit); 952 953 MODULE_AUTHOR("Tungsten Graphics, Inc."); 954 MODULE_AUTHOR("Intel Corporation"); 955 956 MODULE_DESCRIPTION(DRIVER_DESC); 957 MODULE_LICENSE("GPL and additional rights"); 958