1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #ifndef __I915_IRQ_H__ 7 #define __I915_IRQ_H__ 8 9 #include <linux/ktime.h> 10 #include <linux/types.h> 11 12 #include "display/intel_display.h" 13 #include "i915_reg.h" 14 15 struct drm_crtc; 16 struct drm_device; 17 struct drm_display_mode; 18 struct drm_i915_private; 19 struct intel_crtc; 20 struct intel_uncore; 21 22 void intel_irq_init(struct drm_i915_private *dev_priv); 23 void intel_irq_fini(struct drm_i915_private *dev_priv); 24 int intel_irq_install(struct drm_i915_private *dev_priv); 25 void intel_irq_uninstall(struct drm_i915_private *dev_priv); 26 27 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv, 28 enum pipe pipe); 29 void 30 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, 31 u32 status_mask); 32 33 void 34 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, 35 u32 status_mask); 36 37 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); 38 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); 39 40 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, 41 u32 mask, 42 u32 bits); 43 void ilk_update_display_irq(struct drm_i915_private *dev_priv, 44 u32 interrupt_mask, 45 u32 enabled_irq_mask); 46 static inline void 47 ilk_enable_display_irq(struct drm_i915_private *dev_priv, u32 bits) 48 { 49 ilk_update_display_irq(dev_priv, bits, bits); 50 } 51 static inline void 52 ilk_disable_display_irq(struct drm_i915_private *dev_priv, u32 bits) 53 { 54 ilk_update_display_irq(dev_priv, bits, 0); 55 } 56 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, 57 enum pipe pipe, 58 u32 interrupt_mask, 59 u32 enabled_irq_mask); 60 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv, 61 enum pipe pipe, u32 bits) 62 { 63 bdw_update_pipe_irq(dev_priv, pipe, bits, bits); 64 } 65 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv, 66 enum pipe pipe, u32 bits) 67 { 68 bdw_update_pipe_irq(dev_priv, pipe, bits, 0); 69 } 70 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, 71 u32 interrupt_mask, 72 u32 enabled_irq_mask); 73 static inline void 74 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, u32 bits) 75 { 76 ibx_display_interrupt_update(dev_priv, bits, bits); 77 } 78 static inline void 79 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, u32 bits) 80 { 81 ibx_display_interrupt_update(dev_priv, bits, 0); 82 } 83 84 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32 mask); 85 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, u32 mask); 86 void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv); 87 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv); 88 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv); 89 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv); 90 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv); 91 u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915, u32 mask); 92 93 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv); 94 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv); 95 bool intel_irqs_enabled(struct drm_i915_private *dev_priv); 96 void intel_synchronize_irq(struct drm_i915_private *i915); 97 98 int intel_get_crtc_scanline(struct intel_crtc *crtc); 99 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, 100 u8 pipe_mask); 101 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, 102 u8 pipe_mask); 103 104 bool intel_crtc_get_vblank_timestamp(struct drm_crtc *crtc, int *max_error, 105 ktime_t *vblank_time, bool in_vblank_irq); 106 107 u32 i915_get_vblank_counter(struct drm_crtc *crtc); 108 u32 g4x_get_vblank_counter(struct drm_crtc *crtc); 109 110 int i8xx_enable_vblank(struct drm_crtc *crtc); 111 int i915gm_enable_vblank(struct drm_crtc *crtc); 112 int i965_enable_vblank(struct drm_crtc *crtc); 113 int ilk_enable_vblank(struct drm_crtc *crtc); 114 int bdw_enable_vblank(struct drm_crtc *crtc); 115 void i8xx_disable_vblank(struct drm_crtc *crtc); 116 void i915gm_disable_vblank(struct drm_crtc *crtc); 117 void i965_disable_vblank(struct drm_crtc *crtc); 118 void ilk_disable_vblank(struct drm_crtc *crtc); 119 void bdw_disable_vblank(struct drm_crtc *crtc); 120 121 void skl_enable_flip_done(struct intel_crtc *crtc); 122 void skl_disable_flip_done(struct intel_crtc *crtc); 123 124 void gen2_irq_reset(struct intel_uncore *uncore); 125 void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr, 126 i915_reg_t iir, i915_reg_t ier); 127 128 void gen2_irq_init(struct intel_uncore *uncore, 129 u32 imr_val, u32 ier_val); 130 void gen3_irq_init(struct intel_uncore *uncore, 131 i915_reg_t imr, u32 imr_val, 132 i915_reg_t ier, u32 ier_val, 133 i915_reg_t iir); 134 135 #define GEN8_IRQ_RESET_NDX(uncore, type, which) \ 136 ({ \ 137 unsigned int which_ = which; \ 138 gen3_irq_reset((uncore), GEN8_##type##_IMR(which_), \ 139 GEN8_##type##_IIR(which_), GEN8_##type##_IER(which_)); \ 140 }) 141 142 #define GEN3_IRQ_RESET(uncore, type) \ 143 gen3_irq_reset((uncore), type##IMR, type##IIR, type##IER) 144 145 #define GEN2_IRQ_RESET(uncore) \ 146 gen2_irq_reset(uncore) 147 148 #define GEN8_IRQ_INIT_NDX(uncore, type, which, imr_val, ier_val) \ 149 ({ \ 150 unsigned int which_ = which; \ 151 gen3_irq_init((uncore), \ 152 GEN8_##type##_IMR(which_), imr_val, \ 153 GEN8_##type##_IER(which_), ier_val, \ 154 GEN8_##type##_IIR(which_)); \ 155 }) 156 157 #define GEN3_IRQ_INIT(uncore, type, imr_val, ier_val) \ 158 gen3_irq_init((uncore), \ 159 type##IMR, imr_val, \ 160 type##IER, ier_val, \ 161 type##IIR) 162 163 #define GEN2_IRQ_INIT(uncore, imr_val, ier_val) \ 164 gen2_irq_init((uncore), imr_val, ier_val) 165 166 #endif /* __I915_IRQ_H__ */ 167