xref: /openbmc/linux/drivers/gpu/drm/i915/i915_irq.h (revision d6e0cbb1) 
1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2019 Intel Corporation
4  */
5 
6 #ifndef __I915_IRQ_H__
7 #define __I915_IRQ_H__
8 
9 #include <linux/types.h>
10 
11 #include "i915_drv.h"
12 
13 struct drm_i915_private;
14 struct intel_crtc;
15 struct intel_guc;
16 
17 void intel_irq_init(struct drm_i915_private *dev_priv);
18 void intel_irq_fini(struct drm_i915_private *dev_priv);
19 int intel_irq_install(struct drm_i915_private *dev_priv);
20 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
21 
22 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
23 			      enum pipe pipe);
24 void
25 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
26 		     u32 status_mask);
27 
28 void
29 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
30 		      u32 status_mask);
31 
32 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
33 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
34 
35 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
36 				   u32 mask,
37 				   u32 bits);
38 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
39 			    u32 interrupt_mask,
40 			    u32 enabled_irq_mask);
41 static inline void
42 ilk_enable_display_irq(struct drm_i915_private *dev_priv, u32 bits)
43 {
44 	ilk_update_display_irq(dev_priv, bits, bits);
45 }
46 static inline void
47 ilk_disable_display_irq(struct drm_i915_private *dev_priv, u32 bits)
48 {
49 	ilk_update_display_irq(dev_priv, bits, 0);
50 }
51 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
52 			 enum pipe pipe,
53 			 u32 interrupt_mask,
54 			 u32 enabled_irq_mask);
55 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
56 				       enum pipe pipe, u32 bits)
57 {
58 	bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
59 }
60 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
61 					enum pipe pipe, u32 bits)
62 {
63 	bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
64 }
65 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
66 				  u32 interrupt_mask,
67 				  u32 enabled_irq_mask);
68 static inline void
69 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, u32 bits)
70 {
71 	ibx_display_interrupt_update(dev_priv, bits, bits);
72 }
73 static inline void
74 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, u32 bits)
75 {
76 	ibx_display_interrupt_update(dev_priv, bits, 0);
77 }
78 
79 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
80 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
81 void gen6_mask_pm_irq(struct intel_gt *gt, u32 mask);
82 void gen6_unmask_pm_irq(struct intel_gt *gt, u32 mask);
83 void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
84 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
85 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
86 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
87 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
88 
89 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
90 					    u32 mask)
91 {
92 	return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz;
93 }
94 
95 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
96 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
97 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
98 {
99 	/*
100 	 * We only use drm_irq_uninstall() at unload and VT switch, so
101 	 * this is the only thing we need to check.
102 	 */
103 	return dev_priv->runtime_pm.irqs_enabled;
104 }
105 
106 static inline void intel_synchronize_irq(struct drm_i915_private *i915)
107 {
108 	synchronize_irq(i915->drm.pdev->irq);
109 }
110 
111 int intel_get_crtc_scanline(struct intel_crtc *crtc);
112 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
113 				     u8 pipe_mask);
114 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
115 				     u8 pipe_mask);
116 void gen9_reset_guc_interrupts(struct intel_guc *guc);
117 void gen9_enable_guc_interrupts(struct intel_guc *guc);
118 void gen9_disable_guc_interrupts(struct intel_guc *guc);
119 void gen11_reset_guc_interrupts(struct intel_guc *guc);
120 void gen11_enable_guc_interrupts(struct intel_guc *guc);
121 void gen11_disable_guc_interrupts(struct intel_guc *guc);
122 
123 bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
124 			      bool in_vblank_irq, int *vpos, int *hpos,
125 			      ktime_t *stime, ktime_t *etime,
126 			      const struct drm_display_mode *mode);
127 
128 u32 i915_get_vblank_counter(struct drm_crtc *crtc);
129 u32 g4x_get_vblank_counter(struct drm_crtc *crtc);
130 
131 int i8xx_enable_vblank(struct drm_crtc *crtc);
132 int i945gm_enable_vblank(struct drm_crtc *crtc);
133 int i965_enable_vblank(struct drm_crtc *crtc);
134 int ilk_enable_vblank(struct drm_crtc *crtc);
135 int bdw_enable_vblank(struct drm_crtc *crtc);
136 void i8xx_disable_vblank(struct drm_crtc *crtc);
137 void i945gm_disable_vblank(struct drm_crtc *crtc);
138 void i965_disable_vblank(struct drm_crtc *crtc);
139 void ilk_disable_vblank(struct drm_crtc *crtc);
140 void bdw_disable_vblank(struct drm_crtc *crtc);
141 
142 #endif /* __I915_IRQ_H__ */
143