1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #ifndef __I915_IRQ_H__ 7 #define __I915_IRQ_H__ 8 9 #include <linux/ktime.h> 10 #include <linux/types.h> 11 12 #include "display/intel_display.h" 13 #include "i915_reg.h" 14 15 struct drm_crtc; 16 struct drm_device; 17 struct drm_display_mode; 18 struct drm_i915_private; 19 struct intel_crtc; 20 struct intel_crtc; 21 struct intel_gt; 22 struct intel_guc; 23 struct intel_uncore; 24 25 void gen11_rps_irq_handler(struct intel_gt *gt, u32 pm_iir); 26 void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir); 27 28 void intel_irq_init(struct drm_i915_private *dev_priv); 29 void intel_irq_fini(struct drm_i915_private *dev_priv); 30 int intel_irq_install(struct drm_i915_private *dev_priv); 31 void intel_irq_uninstall(struct drm_i915_private *dev_priv); 32 33 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv, 34 enum pipe pipe); 35 void 36 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, 37 u32 status_mask); 38 39 void 40 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, 41 u32 status_mask); 42 43 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); 44 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); 45 46 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, 47 u32 mask, 48 u32 bits); 49 void ilk_update_display_irq(struct drm_i915_private *dev_priv, 50 u32 interrupt_mask, 51 u32 enabled_irq_mask); 52 static inline void 53 ilk_enable_display_irq(struct drm_i915_private *dev_priv, u32 bits) 54 { 55 ilk_update_display_irq(dev_priv, bits, bits); 56 } 57 static inline void 58 ilk_disable_display_irq(struct drm_i915_private *dev_priv, u32 bits) 59 { 60 ilk_update_display_irq(dev_priv, bits, 0); 61 } 62 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, 63 enum pipe pipe, 64 u32 interrupt_mask, 65 u32 enabled_irq_mask); 66 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv, 67 enum pipe pipe, u32 bits) 68 { 69 bdw_update_pipe_irq(dev_priv, pipe, bits, bits); 70 } 71 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv, 72 enum pipe pipe, u32 bits) 73 { 74 bdw_update_pipe_irq(dev_priv, pipe, bits, 0); 75 } 76 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, 77 u32 interrupt_mask, 78 u32 enabled_irq_mask); 79 static inline void 80 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, u32 bits) 81 { 82 ibx_display_interrupt_update(dev_priv, bits, bits); 83 } 84 static inline void 85 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, u32 bits) 86 { 87 ibx_display_interrupt_update(dev_priv, bits, 0); 88 } 89 90 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32 mask); 91 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, u32 mask); 92 void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv); 93 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv); 94 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv); 95 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv); 96 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv); 97 u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915, u32 mask); 98 99 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv); 100 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv); 101 bool intel_irqs_enabled(struct drm_i915_private *dev_priv); 102 void intel_synchronize_irq(struct drm_i915_private *i915); 103 104 int intel_get_crtc_scanline(struct intel_crtc *crtc); 105 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, 106 u8 pipe_mask); 107 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, 108 u8 pipe_mask); 109 void gen9_reset_guc_interrupts(struct intel_guc *guc); 110 void gen9_enable_guc_interrupts(struct intel_guc *guc); 111 void gen9_disable_guc_interrupts(struct intel_guc *guc); 112 void gen11_reset_guc_interrupts(struct intel_guc *guc); 113 void gen11_enable_guc_interrupts(struct intel_guc *guc); 114 void gen11_disable_guc_interrupts(struct intel_guc *guc); 115 116 bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, 117 bool in_vblank_irq, int *vpos, int *hpos, 118 ktime_t *stime, ktime_t *etime, 119 const struct drm_display_mode *mode); 120 121 u32 i915_get_vblank_counter(struct drm_crtc *crtc); 122 u32 g4x_get_vblank_counter(struct drm_crtc *crtc); 123 124 int i8xx_enable_vblank(struct drm_crtc *crtc); 125 int i945gm_enable_vblank(struct drm_crtc *crtc); 126 int i965_enable_vblank(struct drm_crtc *crtc); 127 int ilk_enable_vblank(struct drm_crtc *crtc); 128 int bdw_enable_vblank(struct drm_crtc *crtc); 129 void i8xx_disable_vblank(struct drm_crtc *crtc); 130 void i945gm_disable_vblank(struct drm_crtc *crtc); 131 void i965_disable_vblank(struct drm_crtc *crtc); 132 void ilk_disable_vblank(struct drm_crtc *crtc); 133 void bdw_disable_vblank(struct drm_crtc *crtc); 134 135 void gen2_irq_reset(struct intel_uncore *uncore); 136 void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr, 137 i915_reg_t iir, i915_reg_t ier); 138 139 void gen2_irq_init(struct intel_uncore *uncore, 140 u32 imr_val, u32 ier_val); 141 void gen3_irq_init(struct intel_uncore *uncore, 142 i915_reg_t imr, u32 imr_val, 143 i915_reg_t ier, u32 ier_val, 144 i915_reg_t iir); 145 146 #define GEN8_IRQ_RESET_NDX(uncore, type, which) \ 147 ({ \ 148 unsigned int which_ = which; \ 149 gen3_irq_reset((uncore), GEN8_##type##_IMR(which_), \ 150 GEN8_##type##_IIR(which_), GEN8_##type##_IER(which_)); \ 151 }) 152 153 #define GEN3_IRQ_RESET(uncore, type) \ 154 gen3_irq_reset((uncore), type##IMR, type##IIR, type##IER) 155 156 #define GEN2_IRQ_RESET(uncore) \ 157 gen2_irq_reset(uncore) 158 159 #define GEN8_IRQ_INIT_NDX(uncore, type, which, imr_val, ier_val) \ 160 ({ \ 161 unsigned int which_ = which; \ 162 gen3_irq_init((uncore), \ 163 GEN8_##type##_IMR(which_), imr_val, \ 164 GEN8_##type##_IER(which_), ier_val, \ 165 GEN8_##type##_IIR(which_)); \ 166 }) 167 168 #define GEN3_IRQ_INIT(uncore, type, imr_val, ier_val) \ 169 gen3_irq_init((uncore), \ 170 type##IMR, imr_val, \ 171 type##IER, ier_val, \ 172 type##IIR) 173 174 #define GEN2_IRQ_INIT(uncore, imr_val, ier_val) \ 175 gen2_irq_init((uncore), imr_val, ier_val) 176 177 #endif /* __I915_IRQ_H__ */ 178