xref: /openbmc/linux/drivers/gpu/drm/i915/i915_irq.h (revision 234489ac)
1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2019 Intel Corporation
4  */
5 
6 #ifndef __I915_IRQ_H__
7 #define __I915_IRQ_H__
8 
9 #include <linux/ktime.h>
10 #include <linux/types.h>
11 
12 #include "i915_reg.h"
13 
14 enum pipe;
15 struct drm_crtc;
16 struct drm_device;
17 struct drm_display_mode;
18 struct drm_i915_private;
19 struct intel_crtc;
20 struct intel_uncore;
21 
22 void intel_irq_init(struct drm_i915_private *dev_priv);
23 void intel_irq_fini(struct drm_i915_private *dev_priv);
24 int intel_irq_install(struct drm_i915_private *dev_priv);
25 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
26 
27 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
28 			      enum pipe pipe);
29 void
30 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
31 		     u32 status_mask);
32 
33 void
34 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
35 		      u32 status_mask);
36 
37 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
38 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
39 
40 void intel_hpd_irq_setup(struct drm_i915_private *i915);
41 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
42 				   u32 mask,
43 				   u32 bits);
44 
45 void ilk_enable_display_irq(struct drm_i915_private *i915, u32 bits);
46 void ilk_disable_display_irq(struct drm_i915_private *i915, u32 bits);
47 
48 void bdw_enable_pipe_irq(struct drm_i915_private *i915, enum pipe pipe, u32 bits);
49 void bdw_disable_pipe_irq(struct drm_i915_private *i915, enum pipe pipe, u32 bits);
50 
51 void ibx_enable_display_interrupt(struct drm_i915_private *i915, u32 bits);
52 void ibx_disable_display_interrupt(struct drm_i915_private *i915, u32 bits);
53 
54 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
55 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
56 void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
57 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
58 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
59 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
60 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
61 u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915, u32 mask);
62 
63 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
64 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
65 bool intel_irqs_enabled(struct drm_i915_private *dev_priv);
66 void intel_synchronize_irq(struct drm_i915_private *i915);
67 void intel_synchronize_hardirq(struct drm_i915_private *i915);
68 
69 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
70 				     u8 pipe_mask);
71 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
72 				     u8 pipe_mask);
73 u32 gen8_de_pipe_underrun_mask(struct drm_i915_private *dev_priv);
74 
75 
76 int i8xx_enable_vblank(struct drm_crtc *crtc);
77 int i915gm_enable_vblank(struct drm_crtc *crtc);
78 int i965_enable_vblank(struct drm_crtc *crtc);
79 int ilk_enable_vblank(struct drm_crtc *crtc);
80 int bdw_enable_vblank(struct drm_crtc *crtc);
81 void i8xx_disable_vblank(struct drm_crtc *crtc);
82 void i915gm_disable_vblank(struct drm_crtc *crtc);
83 void i965_disable_vblank(struct drm_crtc *crtc);
84 void ilk_disable_vblank(struct drm_crtc *crtc);
85 void bdw_disable_vblank(struct drm_crtc *crtc);
86 
87 void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
88 		    i915_reg_t iir, i915_reg_t ier);
89 
90 void gen3_irq_init(struct intel_uncore *uncore,
91 		   i915_reg_t imr, u32 imr_val,
92 		   i915_reg_t ier, u32 ier_val,
93 		   i915_reg_t iir);
94 
95 #define GEN8_IRQ_RESET_NDX(uncore, type, which) \
96 ({ \
97 	unsigned int which_ = which; \
98 	gen3_irq_reset((uncore), GEN8_##type##_IMR(which_), \
99 		       GEN8_##type##_IIR(which_), GEN8_##type##_IER(which_)); \
100 })
101 
102 #define GEN3_IRQ_RESET(uncore, type) \
103 	gen3_irq_reset((uncore), type##IMR, type##IIR, type##IER)
104 
105 #define GEN8_IRQ_INIT_NDX(uncore, type, which, imr_val, ier_val) \
106 ({ \
107 	unsigned int which_ = which; \
108 	gen3_irq_init((uncore), \
109 		      GEN8_##type##_IMR(which_), imr_val, \
110 		      GEN8_##type##_IER(which_), ier_val, \
111 		      GEN8_##type##_IIR(which_)); \
112 })
113 
114 #define GEN3_IRQ_INIT(uncore, type, imr_val, ier_val) \
115 	gen3_irq_init((uncore), \
116 		      type##IMR, imr_val, \
117 		      type##IER, ier_val, \
118 		      type##IIR)
119 
120 #endif /* __I915_IRQ_H__ */
121