1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- 2 */ 3 /* 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation the rights to use, copy, modify, merge, publish, 11 * distribute, sub license, and/or sell copies of the Software, and to 12 * permit persons to whom the Software is furnished to do so, subject to 13 * the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial portions 17 * of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 26 * 27 */ 28 29 #include <linux/sysrq.h> 30 #include "drmP.h" 31 #include "drm.h" 32 #include "i915_drm.h" 33 #include "i915_drv.h" 34 #include "intel_drv.h" 35 36 #define MAX_NOPID ((u32)~0) 37 38 /** 39 * Interrupts that are always left unmasked. 40 * 41 * Since pipe events are edge-triggered from the PIPESTAT register to IIR, 42 * we leave them always unmasked in IMR and then control enabling them through 43 * PIPESTAT alone. 44 */ 45 #define I915_INTERRUPT_ENABLE_FIX (I915_ASLE_INTERRUPT | \ 46 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ 47 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \ 48 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) 49 50 /** Interrupts that we mask and unmask at runtime. */ 51 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT) 52 53 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\ 54 PIPE_VBLANK_INTERRUPT_STATUS) 55 56 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\ 57 PIPE_VBLANK_INTERRUPT_ENABLE) 58 59 #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \ 60 DRM_I915_VBLANK_PIPE_B) 61 62 void 63 igdng_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) 64 { 65 if ((dev_priv->gt_irq_mask_reg & mask) != 0) { 66 dev_priv->gt_irq_mask_reg &= ~mask; 67 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); 68 (void) I915_READ(GTIMR); 69 } 70 } 71 72 static inline void 73 igdng_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) 74 { 75 if ((dev_priv->gt_irq_mask_reg & mask) != mask) { 76 dev_priv->gt_irq_mask_reg |= mask; 77 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); 78 (void) I915_READ(GTIMR); 79 } 80 } 81 82 /* For display hotplug interrupt */ 83 void 84 igdng_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) 85 { 86 if ((dev_priv->irq_mask_reg & mask) != 0) { 87 dev_priv->irq_mask_reg &= ~mask; 88 I915_WRITE(DEIMR, dev_priv->irq_mask_reg); 89 (void) I915_READ(DEIMR); 90 } 91 } 92 93 static inline void 94 igdng_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) 95 { 96 if ((dev_priv->irq_mask_reg & mask) != mask) { 97 dev_priv->irq_mask_reg |= mask; 98 I915_WRITE(DEIMR, dev_priv->irq_mask_reg); 99 (void) I915_READ(DEIMR); 100 } 101 } 102 103 void 104 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) 105 { 106 if ((dev_priv->irq_mask_reg & mask) != 0) { 107 dev_priv->irq_mask_reg &= ~mask; 108 I915_WRITE(IMR, dev_priv->irq_mask_reg); 109 (void) I915_READ(IMR); 110 } 111 } 112 113 static inline void 114 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask) 115 { 116 if ((dev_priv->irq_mask_reg & mask) != mask) { 117 dev_priv->irq_mask_reg |= mask; 118 I915_WRITE(IMR, dev_priv->irq_mask_reg); 119 (void) I915_READ(IMR); 120 } 121 } 122 123 static inline u32 124 i915_pipestat(int pipe) 125 { 126 if (pipe == 0) 127 return PIPEASTAT; 128 if (pipe == 1) 129 return PIPEBSTAT; 130 BUG(); 131 } 132 133 void 134 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) 135 { 136 if ((dev_priv->pipestat[pipe] & mask) != mask) { 137 u32 reg = i915_pipestat(pipe); 138 139 dev_priv->pipestat[pipe] |= mask; 140 /* Enable the interrupt, clear any pending status */ 141 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); 142 (void) I915_READ(reg); 143 } 144 } 145 146 void 147 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) 148 { 149 if ((dev_priv->pipestat[pipe] & mask) != 0) { 150 u32 reg = i915_pipestat(pipe); 151 152 dev_priv->pipestat[pipe] &= ~mask; 153 I915_WRITE(reg, dev_priv->pipestat[pipe]); 154 (void) I915_READ(reg); 155 } 156 } 157 158 /** 159 * i915_pipe_enabled - check if a pipe is enabled 160 * @dev: DRM device 161 * @pipe: pipe to check 162 * 163 * Reading certain registers when the pipe is disabled can hang the chip. 164 * Use this routine to make sure the PLL is running and the pipe is active 165 * before reading such registers if unsure. 166 */ 167 static int 168 i915_pipe_enabled(struct drm_device *dev, int pipe) 169 { 170 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 171 unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF; 172 173 if (I915_READ(pipeconf) & PIPEACONF_ENABLE) 174 return 1; 175 176 return 0; 177 } 178 179 /* Called from drm generic code, passed a 'crtc', which 180 * we use as a pipe index 181 */ 182 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) 183 { 184 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 185 unsigned long high_frame; 186 unsigned long low_frame; 187 u32 high1, high2, low, count; 188 189 high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH; 190 low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL; 191 192 if (!i915_pipe_enabled(dev, pipe)) { 193 DRM_DEBUG("trying to get vblank count for disabled pipe %d\n", pipe); 194 return 0; 195 } 196 197 /* 198 * High & low register fields aren't synchronized, so make sure 199 * we get a low value that's stable across two reads of the high 200 * register. 201 */ 202 do { 203 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> 204 PIPE_FRAME_HIGH_SHIFT); 205 low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >> 206 PIPE_FRAME_LOW_SHIFT); 207 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> 208 PIPE_FRAME_HIGH_SHIFT); 209 } while (high1 != high2); 210 211 count = (high1 << 8) | low; 212 213 return count; 214 } 215 216 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) 217 { 218 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 219 int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45; 220 221 if (!i915_pipe_enabled(dev, pipe)) { 222 DRM_DEBUG("trying to get vblank count for disabled pipe %d\n", pipe); 223 return 0; 224 } 225 226 return I915_READ(reg); 227 } 228 229 /* 230 * Handle hotplug events outside the interrupt handler proper. 231 */ 232 static void i915_hotplug_work_func(struct work_struct *work) 233 { 234 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, 235 hotplug_work); 236 struct drm_device *dev = dev_priv->dev; 237 struct drm_mode_config *mode_config = &dev->mode_config; 238 struct drm_connector *connector; 239 240 if (mode_config->num_connector) { 241 list_for_each_entry(connector, &mode_config->connector_list, head) { 242 struct intel_output *intel_output = to_intel_output(connector); 243 244 if (intel_output->hot_plug) 245 (*intel_output->hot_plug) (intel_output); 246 } 247 } 248 /* Just fire off a uevent and let userspace tell us what to do */ 249 drm_sysfs_hotplug_event(dev); 250 } 251 252 irqreturn_t igdng_irq_handler(struct drm_device *dev) 253 { 254 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 255 int ret = IRQ_NONE; 256 u32 de_iir, gt_iir; 257 u32 new_de_iir, new_gt_iir; 258 struct drm_i915_master_private *master_priv; 259 260 de_iir = I915_READ(DEIIR); 261 gt_iir = I915_READ(GTIIR); 262 263 for (;;) { 264 if (de_iir == 0 && gt_iir == 0) 265 break; 266 267 ret = IRQ_HANDLED; 268 269 I915_WRITE(DEIIR, de_iir); 270 new_de_iir = I915_READ(DEIIR); 271 I915_WRITE(GTIIR, gt_iir); 272 new_gt_iir = I915_READ(GTIIR); 273 274 if (dev->primary->master) { 275 master_priv = dev->primary->master->driver_priv; 276 if (master_priv->sarea_priv) 277 master_priv->sarea_priv->last_dispatch = 278 READ_BREADCRUMB(dev_priv); 279 } 280 281 if (gt_iir & GT_USER_INTERRUPT) { 282 dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev); 283 DRM_WAKEUP(&dev_priv->irq_queue); 284 } 285 286 de_iir = new_de_iir; 287 gt_iir = new_gt_iir; 288 } 289 290 return ret; 291 } 292 293 /** 294 * i915_error_work_func - do process context error handling work 295 * @work: work struct 296 * 297 * Fire an error uevent so userspace can see that a hang or error 298 * was detected. 299 */ 300 static void i915_error_work_func(struct work_struct *work) 301 { 302 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, 303 error_work); 304 struct drm_device *dev = dev_priv->dev; 305 char *event_string = "ERROR=1"; 306 char *envp[] = { event_string, NULL }; 307 308 DRM_DEBUG("generating error event\n"); 309 310 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, envp); 311 } 312 313 /** 314 * i915_capture_error_state - capture an error record for later analysis 315 * @dev: drm device 316 * 317 * Should be called when an error is detected (either a hang or an error 318 * interrupt) to capture error state from the time of the error. Fills 319 * out a structure which becomes available in debugfs for user level tools 320 * to pick up. 321 */ 322 static void i915_capture_error_state(struct drm_device *dev) 323 { 324 struct drm_i915_private *dev_priv = dev->dev_private; 325 struct drm_i915_error_state *error; 326 unsigned long flags; 327 328 spin_lock_irqsave(&dev_priv->error_lock, flags); 329 if (dev_priv->first_error) 330 goto out; 331 332 error = kmalloc(sizeof(*error), GFP_ATOMIC); 333 if (!error) { 334 DRM_DEBUG("out ot memory, not capturing error state\n"); 335 goto out; 336 } 337 338 error->eir = I915_READ(EIR); 339 error->pgtbl_er = I915_READ(PGTBL_ER); 340 error->pipeastat = I915_READ(PIPEASTAT); 341 error->pipebstat = I915_READ(PIPEBSTAT); 342 error->instpm = I915_READ(INSTPM); 343 if (!IS_I965G(dev)) { 344 error->ipeir = I915_READ(IPEIR); 345 error->ipehr = I915_READ(IPEHR); 346 error->instdone = I915_READ(INSTDONE); 347 error->acthd = I915_READ(ACTHD); 348 } else { 349 error->ipeir = I915_READ(IPEIR_I965); 350 error->ipehr = I915_READ(IPEHR_I965); 351 error->instdone = I915_READ(INSTDONE_I965); 352 error->instps = I915_READ(INSTPS); 353 error->instdone1 = I915_READ(INSTDONE1); 354 error->acthd = I915_READ(ACTHD_I965); 355 } 356 357 do_gettimeofday(&error->time); 358 359 dev_priv->first_error = error; 360 361 out: 362 spin_unlock_irqrestore(&dev_priv->error_lock, flags); 363 } 364 365 /** 366 * i915_handle_error - handle an error interrupt 367 * @dev: drm device 368 * 369 * Do some basic checking of regsiter state at error interrupt time and 370 * dump it to the syslog. Also call i915_capture_error_state() to make 371 * sure we get a record and make it available in debugfs. Fire a uevent 372 * so userspace knows something bad happened (should trigger collection 373 * of a ring dump etc.). 374 */ 375 static void i915_handle_error(struct drm_device *dev) 376 { 377 struct drm_i915_private *dev_priv = dev->dev_private; 378 u32 eir = I915_READ(EIR); 379 u32 pipea_stats = I915_READ(PIPEASTAT); 380 u32 pipeb_stats = I915_READ(PIPEBSTAT); 381 382 i915_capture_error_state(dev); 383 384 printk(KERN_ERR "render error detected, EIR: 0x%08x\n", 385 eir); 386 387 if (IS_G4X(dev)) { 388 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { 389 u32 ipeir = I915_READ(IPEIR_I965); 390 391 printk(KERN_ERR " IPEIR: 0x%08x\n", 392 I915_READ(IPEIR_I965)); 393 printk(KERN_ERR " IPEHR: 0x%08x\n", 394 I915_READ(IPEHR_I965)); 395 printk(KERN_ERR " INSTDONE: 0x%08x\n", 396 I915_READ(INSTDONE_I965)); 397 printk(KERN_ERR " INSTPS: 0x%08x\n", 398 I915_READ(INSTPS)); 399 printk(KERN_ERR " INSTDONE1: 0x%08x\n", 400 I915_READ(INSTDONE1)); 401 printk(KERN_ERR " ACTHD: 0x%08x\n", 402 I915_READ(ACTHD_I965)); 403 I915_WRITE(IPEIR_I965, ipeir); 404 (void)I915_READ(IPEIR_I965); 405 } 406 if (eir & GM45_ERROR_PAGE_TABLE) { 407 u32 pgtbl_err = I915_READ(PGTBL_ER); 408 printk(KERN_ERR "page table error\n"); 409 printk(KERN_ERR " PGTBL_ER: 0x%08x\n", 410 pgtbl_err); 411 I915_WRITE(PGTBL_ER, pgtbl_err); 412 (void)I915_READ(PGTBL_ER); 413 } 414 } 415 416 if (IS_I9XX(dev)) { 417 if (eir & I915_ERROR_PAGE_TABLE) { 418 u32 pgtbl_err = I915_READ(PGTBL_ER); 419 printk(KERN_ERR "page table error\n"); 420 printk(KERN_ERR " PGTBL_ER: 0x%08x\n", 421 pgtbl_err); 422 I915_WRITE(PGTBL_ER, pgtbl_err); 423 (void)I915_READ(PGTBL_ER); 424 } 425 } 426 427 if (eir & I915_ERROR_MEMORY_REFRESH) { 428 printk(KERN_ERR "memory refresh error\n"); 429 printk(KERN_ERR "PIPEASTAT: 0x%08x\n", 430 pipea_stats); 431 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n", 432 pipeb_stats); 433 /* pipestat has already been acked */ 434 } 435 if (eir & I915_ERROR_INSTRUCTION) { 436 printk(KERN_ERR "instruction error\n"); 437 printk(KERN_ERR " INSTPM: 0x%08x\n", 438 I915_READ(INSTPM)); 439 if (!IS_I965G(dev)) { 440 u32 ipeir = I915_READ(IPEIR); 441 442 printk(KERN_ERR " IPEIR: 0x%08x\n", 443 I915_READ(IPEIR)); 444 printk(KERN_ERR " IPEHR: 0x%08x\n", 445 I915_READ(IPEHR)); 446 printk(KERN_ERR " INSTDONE: 0x%08x\n", 447 I915_READ(INSTDONE)); 448 printk(KERN_ERR " ACTHD: 0x%08x\n", 449 I915_READ(ACTHD)); 450 I915_WRITE(IPEIR, ipeir); 451 (void)I915_READ(IPEIR); 452 } else { 453 u32 ipeir = I915_READ(IPEIR_I965); 454 455 printk(KERN_ERR " IPEIR: 0x%08x\n", 456 I915_READ(IPEIR_I965)); 457 printk(KERN_ERR " IPEHR: 0x%08x\n", 458 I915_READ(IPEHR_I965)); 459 printk(KERN_ERR " INSTDONE: 0x%08x\n", 460 I915_READ(INSTDONE_I965)); 461 printk(KERN_ERR " INSTPS: 0x%08x\n", 462 I915_READ(INSTPS)); 463 printk(KERN_ERR " INSTDONE1: 0x%08x\n", 464 I915_READ(INSTDONE1)); 465 printk(KERN_ERR " ACTHD: 0x%08x\n", 466 I915_READ(ACTHD_I965)); 467 I915_WRITE(IPEIR_I965, ipeir); 468 (void)I915_READ(IPEIR_I965); 469 } 470 } 471 472 I915_WRITE(EIR, eir); 473 (void)I915_READ(EIR); 474 eir = I915_READ(EIR); 475 if (eir) { 476 /* 477 * some errors might have become stuck, 478 * mask them. 479 */ 480 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); 481 I915_WRITE(EMR, I915_READ(EMR) | eir); 482 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); 483 } 484 485 queue_work(dev_priv->wq, &dev_priv->error_work); 486 } 487 488 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) 489 { 490 struct drm_device *dev = (struct drm_device *) arg; 491 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 492 struct drm_i915_master_private *master_priv; 493 u32 iir, new_iir; 494 u32 pipea_stats, pipeb_stats; 495 u32 vblank_status; 496 u32 vblank_enable; 497 int vblank = 0; 498 unsigned long irqflags; 499 int irq_received; 500 int ret = IRQ_NONE; 501 502 atomic_inc(&dev_priv->irq_received); 503 504 if (IS_IGDNG(dev)) 505 return igdng_irq_handler(dev); 506 507 iir = I915_READ(IIR); 508 509 if (IS_I965G(dev)) { 510 vblank_status = I915_START_VBLANK_INTERRUPT_STATUS; 511 vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE; 512 } else { 513 vblank_status = I915_VBLANK_INTERRUPT_STATUS; 514 vblank_enable = I915_VBLANK_INTERRUPT_ENABLE; 515 } 516 517 for (;;) { 518 irq_received = iir != 0; 519 520 /* Can't rely on pipestat interrupt bit in iir as it might 521 * have been cleared after the pipestat interrupt was received. 522 * It doesn't set the bit in iir again, but it still produces 523 * interrupts (for non-MSI). 524 */ 525 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); 526 pipea_stats = I915_READ(PIPEASTAT); 527 pipeb_stats = I915_READ(PIPEBSTAT); 528 529 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) 530 i915_handle_error(dev); 531 532 /* 533 * Clear the PIPE(A|B)STAT regs before the IIR 534 */ 535 if (pipea_stats & 0x8000ffff) { 536 if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS) 537 DRM_DEBUG("pipe a underrun\n"); 538 I915_WRITE(PIPEASTAT, pipea_stats); 539 irq_received = 1; 540 } 541 542 if (pipeb_stats & 0x8000ffff) { 543 if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS) 544 DRM_DEBUG("pipe b underrun\n"); 545 I915_WRITE(PIPEBSTAT, pipeb_stats); 546 irq_received = 1; 547 } 548 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); 549 550 if (!irq_received) 551 break; 552 553 ret = IRQ_HANDLED; 554 555 /* Consume port. Then clear IIR or we'll miss events */ 556 if ((I915_HAS_HOTPLUG(dev)) && 557 (iir & I915_DISPLAY_PORT_INTERRUPT)) { 558 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); 559 560 DRM_DEBUG("hotplug event received, stat 0x%08x\n", 561 hotplug_status); 562 if (hotplug_status & dev_priv->hotplug_supported_mask) 563 queue_work(dev_priv->wq, 564 &dev_priv->hotplug_work); 565 566 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); 567 I915_READ(PORT_HOTPLUG_STAT); 568 } 569 570 I915_WRITE(IIR, iir); 571 new_iir = I915_READ(IIR); /* Flush posted writes */ 572 573 if (dev->primary->master) { 574 master_priv = dev->primary->master->driver_priv; 575 if (master_priv->sarea_priv) 576 master_priv->sarea_priv->last_dispatch = 577 READ_BREADCRUMB(dev_priv); 578 } 579 580 if (iir & I915_USER_INTERRUPT) { 581 dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev); 582 DRM_WAKEUP(&dev_priv->irq_queue); 583 } 584 585 if (pipea_stats & vblank_status) { 586 vblank++; 587 drm_handle_vblank(dev, 0); 588 } 589 590 if (pipeb_stats & vblank_status) { 591 vblank++; 592 drm_handle_vblank(dev, 1); 593 } 594 595 if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) || 596 (iir & I915_ASLE_INTERRUPT)) 597 opregion_asle_intr(dev); 598 599 /* With MSI, interrupts are only generated when iir 600 * transitions from zero to nonzero. If another bit got 601 * set while we were handling the existing iir bits, then 602 * we would never get another interrupt. 603 * 604 * This is fine on non-MSI as well, as if we hit this path 605 * we avoid exiting the interrupt handler only to generate 606 * another one. 607 * 608 * Note that for MSI this could cause a stray interrupt report 609 * if an interrupt landed in the time between writing IIR and 610 * the posting read. This should be rare enough to never 611 * trigger the 99% of 100,000 interrupts test for disabling 612 * stray interrupts. 613 */ 614 iir = new_iir; 615 } 616 617 return ret; 618 } 619 620 static int i915_emit_irq(struct drm_device * dev) 621 { 622 drm_i915_private_t *dev_priv = dev->dev_private; 623 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; 624 RING_LOCALS; 625 626 i915_kernel_lost_context(dev); 627 628 DRM_DEBUG("\n"); 629 630 dev_priv->counter++; 631 if (dev_priv->counter > 0x7FFFFFFFUL) 632 dev_priv->counter = 1; 633 if (master_priv->sarea_priv) 634 master_priv->sarea_priv->last_enqueue = dev_priv->counter; 635 636 BEGIN_LP_RING(4); 637 OUT_RING(MI_STORE_DWORD_INDEX); 638 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); 639 OUT_RING(dev_priv->counter); 640 OUT_RING(MI_USER_INTERRUPT); 641 ADVANCE_LP_RING(); 642 643 return dev_priv->counter; 644 } 645 646 void i915_user_irq_get(struct drm_device *dev) 647 { 648 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 649 unsigned long irqflags; 650 651 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); 652 if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) { 653 if (IS_IGDNG(dev)) 654 igdng_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT); 655 else 656 i915_enable_irq(dev_priv, I915_USER_INTERRUPT); 657 } 658 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); 659 } 660 661 void i915_user_irq_put(struct drm_device *dev) 662 { 663 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 664 unsigned long irqflags; 665 666 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); 667 BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0); 668 if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) { 669 if (IS_IGDNG(dev)) 670 igdng_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT); 671 else 672 i915_disable_irq(dev_priv, I915_USER_INTERRUPT); 673 } 674 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); 675 } 676 677 static int i915_wait_irq(struct drm_device * dev, int irq_nr) 678 { 679 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 680 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; 681 int ret = 0; 682 683 DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr, 684 READ_BREADCRUMB(dev_priv)); 685 686 if (READ_BREADCRUMB(dev_priv) >= irq_nr) { 687 if (master_priv->sarea_priv) 688 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); 689 return 0; 690 } 691 692 if (master_priv->sarea_priv) 693 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; 694 695 i915_user_irq_get(dev); 696 DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ, 697 READ_BREADCRUMB(dev_priv) >= irq_nr); 698 i915_user_irq_put(dev); 699 700 if (ret == -EBUSY) { 701 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", 702 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); 703 } 704 705 return ret; 706 } 707 708 /* Needs the lock as it touches the ring. 709 */ 710 int i915_irq_emit(struct drm_device *dev, void *data, 711 struct drm_file *file_priv) 712 { 713 drm_i915_private_t *dev_priv = dev->dev_private; 714 drm_i915_irq_emit_t *emit = data; 715 int result; 716 717 if (!dev_priv || !dev_priv->ring.virtual_start) { 718 DRM_ERROR("called with no initialization\n"); 719 return -EINVAL; 720 } 721 722 RING_LOCK_TEST_WITH_RETURN(dev, file_priv); 723 724 mutex_lock(&dev->struct_mutex); 725 result = i915_emit_irq(dev); 726 mutex_unlock(&dev->struct_mutex); 727 728 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { 729 DRM_ERROR("copy_to_user\n"); 730 return -EFAULT; 731 } 732 733 return 0; 734 } 735 736 /* Doesn't need the hardware lock. 737 */ 738 int i915_irq_wait(struct drm_device *dev, void *data, 739 struct drm_file *file_priv) 740 { 741 drm_i915_private_t *dev_priv = dev->dev_private; 742 drm_i915_irq_wait_t *irqwait = data; 743 744 if (!dev_priv) { 745 DRM_ERROR("called with no initialization\n"); 746 return -EINVAL; 747 } 748 749 return i915_wait_irq(dev, irqwait->irq_seq); 750 } 751 752 /* Called from drm generic code, passed 'crtc' which 753 * we use as a pipe index 754 */ 755 int i915_enable_vblank(struct drm_device *dev, int pipe) 756 { 757 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 758 unsigned long irqflags; 759 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; 760 u32 pipeconf; 761 762 pipeconf = I915_READ(pipeconf_reg); 763 if (!(pipeconf & PIPEACONF_ENABLE)) 764 return -EINVAL; 765 766 if (IS_IGDNG(dev)) 767 return 0; 768 769 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); 770 if (IS_I965G(dev)) 771 i915_enable_pipestat(dev_priv, pipe, 772 PIPE_START_VBLANK_INTERRUPT_ENABLE); 773 else 774 i915_enable_pipestat(dev_priv, pipe, 775 PIPE_VBLANK_INTERRUPT_ENABLE); 776 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); 777 return 0; 778 } 779 780 /* Called from drm generic code, passed 'crtc' which 781 * we use as a pipe index 782 */ 783 void i915_disable_vblank(struct drm_device *dev, int pipe) 784 { 785 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 786 unsigned long irqflags; 787 788 if (IS_IGDNG(dev)) 789 return; 790 791 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); 792 i915_disable_pipestat(dev_priv, pipe, 793 PIPE_VBLANK_INTERRUPT_ENABLE | 794 PIPE_START_VBLANK_INTERRUPT_ENABLE); 795 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); 796 } 797 798 void i915_enable_interrupt (struct drm_device *dev) 799 { 800 struct drm_i915_private *dev_priv = dev->dev_private; 801 802 if (!IS_IGDNG(dev)) 803 opregion_enable_asle(dev); 804 dev_priv->irq_enabled = 1; 805 } 806 807 808 /* Set the vblank monitor pipe 809 */ 810 int i915_vblank_pipe_set(struct drm_device *dev, void *data, 811 struct drm_file *file_priv) 812 { 813 drm_i915_private_t *dev_priv = dev->dev_private; 814 815 if (!dev_priv) { 816 DRM_ERROR("called with no initialization\n"); 817 return -EINVAL; 818 } 819 820 return 0; 821 } 822 823 int i915_vblank_pipe_get(struct drm_device *dev, void *data, 824 struct drm_file *file_priv) 825 { 826 drm_i915_private_t *dev_priv = dev->dev_private; 827 drm_i915_vblank_pipe_t *pipe = data; 828 829 if (!dev_priv) { 830 DRM_ERROR("called with no initialization\n"); 831 return -EINVAL; 832 } 833 834 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; 835 836 return 0; 837 } 838 839 /** 840 * Schedule buffer swap at given vertical blank. 841 */ 842 int i915_vblank_swap(struct drm_device *dev, void *data, 843 struct drm_file *file_priv) 844 { 845 /* The delayed swap mechanism was fundamentally racy, and has been 846 * removed. The model was that the client requested a delayed flip/swap 847 * from the kernel, then waited for vblank before continuing to perform 848 * rendering. The problem was that the kernel might wake the client 849 * up before it dispatched the vblank swap (since the lock has to be 850 * held while touching the ringbuffer), in which case the client would 851 * clear and start the next frame before the swap occurred, and 852 * flicker would occur in addition to likely missing the vblank. 853 * 854 * In the absence of this ioctl, userland falls back to a correct path 855 * of waiting for a vblank, then dispatching the swap on its own. 856 * Context switching to userland and back is plenty fast enough for 857 * meeting the requirements of vblank swapping. 858 */ 859 return -EINVAL; 860 } 861 862 /* drm_dma.h hooks 863 */ 864 static void igdng_irq_preinstall(struct drm_device *dev) 865 { 866 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 867 868 I915_WRITE(HWSTAM, 0xeffe); 869 870 /* XXX hotplug from PCH */ 871 872 I915_WRITE(DEIMR, 0xffffffff); 873 I915_WRITE(DEIER, 0x0); 874 (void) I915_READ(DEIER); 875 876 /* and GT */ 877 I915_WRITE(GTIMR, 0xffffffff); 878 I915_WRITE(GTIER, 0x0); 879 (void) I915_READ(GTIER); 880 } 881 882 static int igdng_irq_postinstall(struct drm_device *dev) 883 { 884 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 885 /* enable kind of interrupts always enabled */ 886 u32 display_mask = DE_MASTER_IRQ_CONTROL /*| DE_PCH_EVENT */; 887 u32 render_mask = GT_USER_INTERRUPT; 888 889 dev_priv->irq_mask_reg = ~display_mask; 890 dev_priv->de_irq_enable_reg = display_mask; 891 892 /* should always can generate irq */ 893 I915_WRITE(DEIIR, I915_READ(DEIIR)); 894 I915_WRITE(DEIMR, dev_priv->irq_mask_reg); 895 I915_WRITE(DEIER, dev_priv->de_irq_enable_reg); 896 (void) I915_READ(DEIER); 897 898 /* user interrupt should be enabled, but masked initial */ 899 dev_priv->gt_irq_mask_reg = 0xffffffff; 900 dev_priv->gt_irq_enable_reg = render_mask; 901 902 I915_WRITE(GTIIR, I915_READ(GTIIR)); 903 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); 904 I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg); 905 (void) I915_READ(GTIER); 906 907 return 0; 908 } 909 910 void i915_driver_irq_preinstall(struct drm_device * dev) 911 { 912 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 913 914 atomic_set(&dev_priv->irq_received, 0); 915 916 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); 917 INIT_WORK(&dev_priv->error_work, i915_error_work_func); 918 919 if (IS_IGDNG(dev)) { 920 igdng_irq_preinstall(dev); 921 return; 922 } 923 924 if (I915_HAS_HOTPLUG(dev)) { 925 I915_WRITE(PORT_HOTPLUG_EN, 0); 926 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 927 } 928 929 I915_WRITE(HWSTAM, 0xeffe); 930 I915_WRITE(PIPEASTAT, 0); 931 I915_WRITE(PIPEBSTAT, 0); 932 I915_WRITE(IMR, 0xffffffff); 933 I915_WRITE(IER, 0x0); 934 (void) I915_READ(IER); 935 } 936 937 int i915_driver_irq_postinstall(struct drm_device *dev) 938 { 939 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 940 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR; 941 u32 error_mask; 942 943 DRM_INIT_WAITQUEUE(&dev_priv->irq_queue); 944 945 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; 946 947 if (IS_IGDNG(dev)) 948 return igdng_irq_postinstall(dev); 949 950 /* Unmask the interrupts that we always want on. */ 951 dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX; 952 953 dev_priv->pipestat[0] = 0; 954 dev_priv->pipestat[1] = 0; 955 956 if (I915_HAS_HOTPLUG(dev)) { 957 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); 958 959 /* Leave other bits alone */ 960 hotplug_en |= HOTPLUG_EN_MASK; 961 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); 962 963 dev_priv->hotplug_supported_mask = CRT_HOTPLUG_INT_STATUS | 964 TV_HOTPLUG_INT_STATUS | SDVOC_HOTPLUG_INT_STATUS | 965 SDVOB_HOTPLUG_INT_STATUS; 966 if (IS_G4X(dev)) { 967 dev_priv->hotplug_supported_mask |= 968 HDMIB_HOTPLUG_INT_STATUS | 969 HDMIC_HOTPLUG_INT_STATUS | 970 HDMID_HOTPLUG_INT_STATUS; 971 } 972 /* Enable in IER... */ 973 enable_mask |= I915_DISPLAY_PORT_INTERRUPT; 974 /* and unmask in IMR */ 975 i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT); 976 } 977 978 /* 979 * Enable some error detection, note the instruction error mask 980 * bit is reserved, so we leave it masked. 981 */ 982 if (IS_G4X(dev)) { 983 error_mask = ~(GM45_ERROR_PAGE_TABLE | 984 GM45_ERROR_MEM_PRIV | 985 GM45_ERROR_CP_PRIV | 986 I915_ERROR_MEMORY_REFRESH); 987 } else { 988 error_mask = ~(I915_ERROR_PAGE_TABLE | 989 I915_ERROR_MEMORY_REFRESH); 990 } 991 I915_WRITE(EMR, error_mask); 992 993 /* Disable pipe interrupt enables, clear pending pipe status */ 994 I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); 995 I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); 996 /* Clear pending interrupt status */ 997 I915_WRITE(IIR, I915_READ(IIR)); 998 999 I915_WRITE(IER, enable_mask); 1000 I915_WRITE(IMR, dev_priv->irq_mask_reg); 1001 (void) I915_READ(IER); 1002 1003 opregion_enable_asle(dev); 1004 1005 return 0; 1006 } 1007 1008 static void igdng_irq_uninstall(struct drm_device *dev) 1009 { 1010 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1011 I915_WRITE(HWSTAM, 0xffffffff); 1012 1013 I915_WRITE(DEIMR, 0xffffffff); 1014 I915_WRITE(DEIER, 0x0); 1015 I915_WRITE(DEIIR, I915_READ(DEIIR)); 1016 1017 I915_WRITE(GTIMR, 0xffffffff); 1018 I915_WRITE(GTIER, 0x0); 1019 I915_WRITE(GTIIR, I915_READ(GTIIR)); 1020 } 1021 1022 void i915_driver_irq_uninstall(struct drm_device * dev) 1023 { 1024 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1025 1026 if (!dev_priv) 1027 return; 1028 1029 dev_priv->vblank_pipe = 0; 1030 1031 if (IS_IGDNG(dev)) { 1032 igdng_irq_uninstall(dev); 1033 return; 1034 } 1035 1036 if (I915_HAS_HOTPLUG(dev)) { 1037 I915_WRITE(PORT_HOTPLUG_EN, 0); 1038 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 1039 } 1040 1041 I915_WRITE(HWSTAM, 0xffffffff); 1042 I915_WRITE(PIPEASTAT, 0); 1043 I915_WRITE(PIPEBSTAT, 0); 1044 I915_WRITE(IMR, 0xffffffff); 1045 I915_WRITE(IER, 0x0); 1046 1047 I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); 1048 I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); 1049 I915_WRITE(IIR, I915_READ(IIR)); 1050 } 1051