1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- 2 */ 3 /* 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation the rights to use, copy, modify, merge, publish, 11 * distribute, sub license, and/or sell copies of the Software, and to 12 * permit persons to whom the Software is furnished to do so, subject to 13 * the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial portions 17 * of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 26 * 27 */ 28 29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 30 31 #include <linux/sysrq.h> 32 #include <linux/slab.h> 33 #include <linux/circ_buf.h> 34 #include <drm/drmP.h> 35 #include <drm/i915_drm.h> 36 #include "i915_drv.h" 37 #include "i915_trace.h" 38 #include "intel_drv.h" 39 40 static const u32 hpd_ibx[] = { 41 [HPD_CRT] = SDE_CRT_HOTPLUG, 42 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, 43 [HPD_PORT_B] = SDE_PORTB_HOTPLUG, 44 [HPD_PORT_C] = SDE_PORTC_HOTPLUG, 45 [HPD_PORT_D] = SDE_PORTD_HOTPLUG 46 }; 47 48 static const u32 hpd_cpt[] = { 49 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, 50 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, 51 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, 52 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, 53 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT 54 }; 55 56 static const u32 hpd_mask_i915[] = { 57 [HPD_CRT] = CRT_HOTPLUG_INT_EN, 58 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, 59 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, 60 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, 61 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, 62 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN 63 }; 64 65 static const u32 hpd_status_g4x[] = { 66 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, 67 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, 68 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, 69 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, 70 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, 71 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS 72 }; 73 74 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ 75 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, 76 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, 77 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, 78 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, 79 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, 80 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS 81 }; 82 83 /* For display hotplug interrupt */ 84 static void 85 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask) 86 { 87 assert_spin_locked(&dev_priv->irq_lock); 88 89 if (dev_priv->pm.irqs_disabled) { 90 WARN(1, "IRQs disabled\n"); 91 dev_priv->pm.regsave.deimr &= ~mask; 92 return; 93 } 94 95 if ((dev_priv->irq_mask & mask) != 0) { 96 dev_priv->irq_mask &= ~mask; 97 I915_WRITE(DEIMR, dev_priv->irq_mask); 98 POSTING_READ(DEIMR); 99 } 100 } 101 102 static void 103 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask) 104 { 105 assert_spin_locked(&dev_priv->irq_lock); 106 107 if (dev_priv->pm.irqs_disabled) { 108 WARN(1, "IRQs disabled\n"); 109 dev_priv->pm.regsave.deimr |= mask; 110 return; 111 } 112 113 if ((dev_priv->irq_mask & mask) != mask) { 114 dev_priv->irq_mask |= mask; 115 I915_WRITE(DEIMR, dev_priv->irq_mask); 116 POSTING_READ(DEIMR); 117 } 118 } 119 120 /** 121 * ilk_update_gt_irq - update GTIMR 122 * @dev_priv: driver private 123 * @interrupt_mask: mask of interrupt bits to update 124 * @enabled_irq_mask: mask of interrupt bits to enable 125 */ 126 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv, 127 uint32_t interrupt_mask, 128 uint32_t enabled_irq_mask) 129 { 130 assert_spin_locked(&dev_priv->irq_lock); 131 132 if (dev_priv->pm.irqs_disabled) { 133 WARN(1, "IRQs disabled\n"); 134 dev_priv->pm.regsave.gtimr &= ~interrupt_mask; 135 dev_priv->pm.regsave.gtimr |= (~enabled_irq_mask & 136 interrupt_mask); 137 return; 138 } 139 140 dev_priv->gt_irq_mask &= ~interrupt_mask; 141 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); 142 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); 143 POSTING_READ(GTIMR); 144 } 145 146 void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) 147 { 148 ilk_update_gt_irq(dev_priv, mask, mask); 149 } 150 151 void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) 152 { 153 ilk_update_gt_irq(dev_priv, mask, 0); 154 } 155 156 /** 157 * snb_update_pm_irq - update GEN6_PMIMR 158 * @dev_priv: driver private 159 * @interrupt_mask: mask of interrupt bits to update 160 * @enabled_irq_mask: mask of interrupt bits to enable 161 */ 162 static void snb_update_pm_irq(struct drm_i915_private *dev_priv, 163 uint32_t interrupt_mask, 164 uint32_t enabled_irq_mask) 165 { 166 uint32_t new_val; 167 168 assert_spin_locked(&dev_priv->irq_lock); 169 170 if (dev_priv->pm.irqs_disabled) { 171 WARN(1, "IRQs disabled\n"); 172 dev_priv->pm.regsave.gen6_pmimr &= ~interrupt_mask; 173 dev_priv->pm.regsave.gen6_pmimr |= (~enabled_irq_mask & 174 interrupt_mask); 175 return; 176 } 177 178 new_val = dev_priv->pm_irq_mask; 179 new_val &= ~interrupt_mask; 180 new_val |= (~enabled_irq_mask & interrupt_mask); 181 182 if (new_val != dev_priv->pm_irq_mask) { 183 dev_priv->pm_irq_mask = new_val; 184 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask); 185 POSTING_READ(GEN6_PMIMR); 186 } 187 } 188 189 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) 190 { 191 snb_update_pm_irq(dev_priv, mask, mask); 192 } 193 194 void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) 195 { 196 snb_update_pm_irq(dev_priv, mask, 0); 197 } 198 199 static bool ivb_can_enable_err_int(struct drm_device *dev) 200 { 201 struct drm_i915_private *dev_priv = dev->dev_private; 202 struct intel_crtc *crtc; 203 enum pipe pipe; 204 205 assert_spin_locked(&dev_priv->irq_lock); 206 207 for_each_pipe(pipe) { 208 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); 209 210 if (crtc->cpu_fifo_underrun_disabled) 211 return false; 212 } 213 214 return true; 215 } 216 217 static bool cpt_can_enable_serr_int(struct drm_device *dev) 218 { 219 struct drm_i915_private *dev_priv = dev->dev_private; 220 enum pipe pipe; 221 struct intel_crtc *crtc; 222 223 assert_spin_locked(&dev_priv->irq_lock); 224 225 for_each_pipe(pipe) { 226 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); 227 228 if (crtc->pch_fifo_underrun_disabled) 229 return false; 230 } 231 232 return true; 233 } 234 235 static void i9xx_clear_fifo_underrun(struct drm_device *dev, enum pipe pipe) 236 { 237 struct drm_i915_private *dev_priv = dev->dev_private; 238 u32 reg = PIPESTAT(pipe); 239 u32 pipestat = I915_READ(reg) & 0x7fff0000; 240 241 assert_spin_locked(&dev_priv->irq_lock); 242 243 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS); 244 POSTING_READ(reg); 245 } 246 247 static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev, 248 enum pipe pipe, bool enable) 249 { 250 struct drm_i915_private *dev_priv = dev->dev_private; 251 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN : 252 DE_PIPEB_FIFO_UNDERRUN; 253 254 if (enable) 255 ironlake_enable_display_irq(dev_priv, bit); 256 else 257 ironlake_disable_display_irq(dev_priv, bit); 258 } 259 260 static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev, 261 enum pipe pipe, bool enable) 262 { 263 struct drm_i915_private *dev_priv = dev->dev_private; 264 if (enable) { 265 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); 266 267 if (!ivb_can_enable_err_int(dev)) 268 return; 269 270 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB); 271 } else { 272 bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB); 273 274 /* Change the state _after_ we've read out the current one. */ 275 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB); 276 277 if (!was_enabled && 278 (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) { 279 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n", 280 pipe_name(pipe)); 281 } 282 } 283 } 284 285 static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev, 286 enum pipe pipe, bool enable) 287 { 288 struct drm_i915_private *dev_priv = dev->dev_private; 289 290 assert_spin_locked(&dev_priv->irq_lock); 291 292 if (enable) 293 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN; 294 else 295 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN; 296 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); 297 POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); 298 } 299 300 /** 301 * ibx_display_interrupt_update - update SDEIMR 302 * @dev_priv: driver private 303 * @interrupt_mask: mask of interrupt bits to update 304 * @enabled_irq_mask: mask of interrupt bits to enable 305 */ 306 static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, 307 uint32_t interrupt_mask, 308 uint32_t enabled_irq_mask) 309 { 310 uint32_t sdeimr = I915_READ(SDEIMR); 311 sdeimr &= ~interrupt_mask; 312 sdeimr |= (~enabled_irq_mask & interrupt_mask); 313 314 assert_spin_locked(&dev_priv->irq_lock); 315 316 if (dev_priv->pm.irqs_disabled && 317 (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) { 318 WARN(1, "IRQs disabled\n"); 319 dev_priv->pm.regsave.sdeimr &= ~interrupt_mask; 320 dev_priv->pm.regsave.sdeimr |= (~enabled_irq_mask & 321 interrupt_mask); 322 return; 323 } 324 325 I915_WRITE(SDEIMR, sdeimr); 326 POSTING_READ(SDEIMR); 327 } 328 #define ibx_enable_display_interrupt(dev_priv, bits) \ 329 ibx_display_interrupt_update((dev_priv), (bits), (bits)) 330 #define ibx_disable_display_interrupt(dev_priv, bits) \ 331 ibx_display_interrupt_update((dev_priv), (bits), 0) 332 333 static void ibx_set_fifo_underrun_reporting(struct drm_device *dev, 334 enum transcoder pch_transcoder, 335 bool enable) 336 { 337 struct drm_i915_private *dev_priv = dev->dev_private; 338 uint32_t bit = (pch_transcoder == TRANSCODER_A) ? 339 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER; 340 341 if (enable) 342 ibx_enable_display_interrupt(dev_priv, bit); 343 else 344 ibx_disable_display_interrupt(dev_priv, bit); 345 } 346 347 static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, 348 enum transcoder pch_transcoder, 349 bool enable) 350 { 351 struct drm_i915_private *dev_priv = dev->dev_private; 352 353 if (enable) { 354 I915_WRITE(SERR_INT, 355 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); 356 357 if (!cpt_can_enable_serr_int(dev)) 358 return; 359 360 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT); 361 } else { 362 uint32_t tmp = I915_READ(SERR_INT); 363 bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT); 364 365 /* Change the state _after_ we've read out the current one. */ 366 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT); 367 368 if (!was_enabled && 369 (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) { 370 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n", 371 transcoder_name(pch_transcoder)); 372 } 373 } 374 } 375 376 /** 377 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages 378 * @dev: drm device 379 * @pipe: pipe 380 * @enable: true if we want to report FIFO underrun errors, false otherwise 381 * 382 * This function makes us disable or enable CPU fifo underruns for a specific 383 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun 384 * reporting for one pipe may also disable all the other CPU error interruts for 385 * the other pipes, due to the fact that there's just one interrupt mask/enable 386 * bit for all the pipes. 387 * 388 * Returns the previous state of underrun reporting. 389 */ 390 bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, 391 enum pipe pipe, bool enable) 392 { 393 struct drm_i915_private *dev_priv = dev->dev_private; 394 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 396 bool ret; 397 398 assert_spin_locked(&dev_priv->irq_lock); 399 400 ret = !intel_crtc->cpu_fifo_underrun_disabled; 401 402 if (enable == ret) 403 goto done; 404 405 intel_crtc->cpu_fifo_underrun_disabled = !enable; 406 407 if (enable && (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))) 408 i9xx_clear_fifo_underrun(dev, pipe); 409 else if (IS_GEN5(dev) || IS_GEN6(dev)) 410 ironlake_set_fifo_underrun_reporting(dev, pipe, enable); 411 else if (IS_GEN7(dev)) 412 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable); 413 else if (IS_GEN8(dev)) 414 broadwell_set_fifo_underrun_reporting(dev, pipe, enable); 415 416 done: 417 return ret; 418 } 419 420 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, 421 enum pipe pipe, bool enable) 422 { 423 struct drm_i915_private *dev_priv = dev->dev_private; 424 unsigned long flags; 425 bool ret; 426 427 spin_lock_irqsave(&dev_priv->irq_lock, flags); 428 ret = __intel_set_cpu_fifo_underrun_reporting(dev, pipe, enable); 429 spin_unlock_irqrestore(&dev_priv->irq_lock, flags); 430 431 return ret; 432 } 433 434 static bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev, 435 enum pipe pipe) 436 { 437 struct drm_i915_private *dev_priv = dev->dev_private; 438 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 439 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 440 441 return !intel_crtc->cpu_fifo_underrun_disabled; 442 } 443 444 /** 445 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages 446 * @dev: drm device 447 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) 448 * @enable: true if we want to report FIFO underrun errors, false otherwise 449 * 450 * This function makes us disable or enable PCH fifo underruns for a specific 451 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO 452 * underrun reporting for one transcoder may also disable all the other PCH 453 * error interruts for the other transcoders, due to the fact that there's just 454 * one interrupt mask/enable bit for all the transcoders. 455 * 456 * Returns the previous state of underrun reporting. 457 */ 458 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, 459 enum transcoder pch_transcoder, 460 bool enable) 461 { 462 struct drm_i915_private *dev_priv = dev->dev_private; 463 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder]; 464 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 465 unsigned long flags; 466 bool ret; 467 468 /* 469 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT 470 * has only one pch transcoder A that all pipes can use. To avoid racy 471 * pch transcoder -> pipe lookups from interrupt code simply store the 472 * underrun statistics in crtc A. Since we never expose this anywhere 473 * nor use it outside of the fifo underrun code here using the "wrong" 474 * crtc on LPT won't cause issues. 475 */ 476 477 spin_lock_irqsave(&dev_priv->irq_lock, flags); 478 479 ret = !intel_crtc->pch_fifo_underrun_disabled; 480 481 if (enable == ret) 482 goto done; 483 484 intel_crtc->pch_fifo_underrun_disabled = !enable; 485 486 if (HAS_PCH_IBX(dev)) 487 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable); 488 else 489 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable); 490 491 done: 492 spin_unlock_irqrestore(&dev_priv->irq_lock, flags); 493 return ret; 494 } 495 496 497 static void 498 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, 499 u32 enable_mask, u32 status_mask) 500 { 501 u32 reg = PIPESTAT(pipe); 502 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; 503 504 assert_spin_locked(&dev_priv->irq_lock); 505 506 if (WARN_ON_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || 507 status_mask & ~PIPESTAT_INT_STATUS_MASK)) 508 return; 509 510 if ((pipestat & enable_mask) == enable_mask) 511 return; 512 513 dev_priv->pipestat_irq_mask[pipe] |= status_mask; 514 515 /* Enable the interrupt, clear any pending status */ 516 pipestat |= enable_mask | status_mask; 517 I915_WRITE(reg, pipestat); 518 POSTING_READ(reg); 519 } 520 521 static void 522 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, 523 u32 enable_mask, u32 status_mask) 524 { 525 u32 reg = PIPESTAT(pipe); 526 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; 527 528 assert_spin_locked(&dev_priv->irq_lock); 529 530 if (WARN_ON_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || 531 status_mask & ~PIPESTAT_INT_STATUS_MASK)) 532 return; 533 534 if ((pipestat & enable_mask) == 0) 535 return; 536 537 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; 538 539 pipestat &= ~enable_mask; 540 I915_WRITE(reg, pipestat); 541 POSTING_READ(reg); 542 } 543 544 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask) 545 { 546 u32 enable_mask = status_mask << 16; 547 548 /* 549 * On pipe A we don't support the PSR interrupt yet, on pipe B the 550 * same bit MBZ. 551 */ 552 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV)) 553 return 0; 554 555 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS | 556 SPRITE0_FLIP_DONE_INT_EN_VLV | 557 SPRITE1_FLIP_DONE_INT_EN_VLV); 558 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV) 559 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV; 560 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV) 561 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV; 562 563 return enable_mask; 564 } 565 566 void 567 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, 568 u32 status_mask) 569 { 570 u32 enable_mask; 571 572 if (IS_VALLEYVIEW(dev_priv->dev)) 573 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, 574 status_mask); 575 else 576 enable_mask = status_mask << 16; 577 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask); 578 } 579 580 void 581 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, 582 u32 status_mask) 583 { 584 u32 enable_mask; 585 586 if (IS_VALLEYVIEW(dev_priv->dev)) 587 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, 588 status_mask); 589 else 590 enable_mask = status_mask << 16; 591 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask); 592 } 593 594 /** 595 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion 596 */ 597 static void i915_enable_asle_pipestat(struct drm_device *dev) 598 { 599 struct drm_i915_private *dev_priv = dev->dev_private; 600 unsigned long irqflags; 601 602 if (!dev_priv->opregion.asle || !IS_MOBILE(dev)) 603 return; 604 605 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 606 607 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); 608 if (INTEL_INFO(dev)->gen >= 4) 609 i915_enable_pipestat(dev_priv, PIPE_A, 610 PIPE_LEGACY_BLC_EVENT_STATUS); 611 612 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 613 } 614 615 /** 616 * i915_pipe_enabled - check if a pipe is enabled 617 * @dev: DRM device 618 * @pipe: pipe to check 619 * 620 * Reading certain registers when the pipe is disabled can hang the chip. 621 * Use this routine to make sure the PLL is running and the pipe is active 622 * before reading such registers if unsure. 623 */ 624 static int 625 i915_pipe_enabled(struct drm_device *dev, int pipe) 626 { 627 struct drm_i915_private *dev_priv = dev->dev_private; 628 629 if (drm_core_check_feature(dev, DRIVER_MODESET)) { 630 /* Locking is horribly broken here, but whatever. */ 631 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 632 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 633 634 return intel_crtc->active; 635 } else { 636 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; 637 } 638 } 639 640 static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe) 641 { 642 /* Gen2 doesn't have a hardware frame counter */ 643 return 0; 644 } 645 646 /* Called from drm generic code, passed a 'crtc', which 647 * we use as a pipe index 648 */ 649 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) 650 { 651 struct drm_i915_private *dev_priv = dev->dev_private; 652 unsigned long high_frame; 653 unsigned long low_frame; 654 u32 high1, high2, low, pixel, vbl_start; 655 656 if (!i915_pipe_enabled(dev, pipe)) { 657 DRM_DEBUG_DRIVER("trying to get vblank count for disabled " 658 "pipe %c\n", pipe_name(pipe)); 659 return 0; 660 } 661 662 if (drm_core_check_feature(dev, DRIVER_MODESET)) { 663 struct intel_crtc *intel_crtc = 664 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); 665 const struct drm_display_mode *mode = 666 &intel_crtc->config.adjusted_mode; 667 668 vbl_start = mode->crtc_vblank_start * mode->crtc_htotal; 669 } else { 670 enum transcoder cpu_transcoder = (enum transcoder) pipe; 671 u32 htotal; 672 673 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1; 674 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1; 675 676 vbl_start *= htotal; 677 } 678 679 high_frame = PIPEFRAME(pipe); 680 low_frame = PIPEFRAMEPIXEL(pipe); 681 682 /* 683 * High & low register fields aren't synchronized, so make sure 684 * we get a low value that's stable across two reads of the high 685 * register. 686 */ 687 do { 688 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; 689 low = I915_READ(low_frame); 690 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; 691 } while (high1 != high2); 692 693 high1 >>= PIPE_FRAME_HIGH_SHIFT; 694 pixel = low & PIPE_PIXEL_MASK; 695 low >>= PIPE_FRAME_LOW_SHIFT; 696 697 /* 698 * The frame counter increments at beginning of active. 699 * Cook up a vblank counter by also checking the pixel 700 * counter against vblank start. 701 */ 702 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff; 703 } 704 705 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) 706 { 707 struct drm_i915_private *dev_priv = dev->dev_private; 708 int reg = PIPE_FRMCOUNT_GM45(pipe); 709 710 if (!i915_pipe_enabled(dev, pipe)) { 711 DRM_DEBUG_DRIVER("trying to get vblank count for disabled " 712 "pipe %c\n", pipe_name(pipe)); 713 return 0; 714 } 715 716 return I915_READ(reg); 717 } 718 719 /* raw reads, only for fast reads of display block, no need for forcewake etc. */ 720 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__)) 721 722 static bool ilk_pipe_in_vblank_locked(struct drm_device *dev, enum pipe pipe) 723 { 724 struct drm_i915_private *dev_priv = dev->dev_private; 725 uint32_t status; 726 int reg; 727 728 if (INTEL_INFO(dev)->gen >= 8) { 729 status = GEN8_PIPE_VBLANK; 730 reg = GEN8_DE_PIPE_ISR(pipe); 731 } else if (INTEL_INFO(dev)->gen >= 7) { 732 status = DE_PIPE_VBLANK_IVB(pipe); 733 reg = DEISR; 734 } else { 735 status = DE_PIPE_VBLANK(pipe); 736 reg = DEISR; 737 } 738 739 return __raw_i915_read32(dev_priv, reg) & status; 740 } 741 742 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, 743 unsigned int flags, int *vpos, int *hpos, 744 ktime_t *stime, ktime_t *etime) 745 { 746 struct drm_i915_private *dev_priv = dev->dev_private; 747 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 748 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 749 const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode; 750 int position; 751 int vbl_start, vbl_end, htotal, vtotal; 752 bool in_vbl = true; 753 int ret = 0; 754 unsigned long irqflags; 755 756 if (!intel_crtc->active) { 757 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " 758 "pipe %c\n", pipe_name(pipe)); 759 return 0; 760 } 761 762 htotal = mode->crtc_htotal; 763 vtotal = mode->crtc_vtotal; 764 vbl_start = mode->crtc_vblank_start; 765 vbl_end = mode->crtc_vblank_end; 766 767 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 768 vbl_start = DIV_ROUND_UP(vbl_start, 2); 769 vbl_end /= 2; 770 vtotal /= 2; 771 } 772 773 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; 774 775 /* 776 * Lock uncore.lock, as we will do multiple timing critical raw 777 * register reads, potentially with preemption disabled, so the 778 * following code must not block on uncore.lock. 779 */ 780 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 781 782 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 783 784 /* Get optional system timestamp before query. */ 785 if (stime) 786 *stime = ktime_get(); 787 788 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { 789 /* No obvious pixelcount register. Only query vertical 790 * scanout position from Display scan line register. 791 */ 792 if (IS_GEN2(dev)) 793 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; 794 else 795 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; 796 797 if (HAS_DDI(dev)) { 798 /* 799 * On HSW HDMI outputs there seems to be a 2 line 800 * difference, whereas eDP has the normal 1 line 801 * difference that earlier platforms have. External 802 * DP is unknown. For now just check for the 2 line 803 * difference case on all output types on HSW+. 804 * 805 * This might misinterpret the scanline counter being 806 * one line too far along on eDP, but that's less 807 * dangerous than the alternative since that would lead 808 * the vblank timestamp code astray when it sees a 809 * scanline count before vblank_start during a vblank 810 * interrupt. 811 */ 812 in_vbl = ilk_pipe_in_vblank_locked(dev, pipe); 813 if ((in_vbl && (position == vbl_start - 2 || 814 position == vbl_start - 1)) || 815 (!in_vbl && (position == vbl_end - 2 || 816 position == vbl_end - 1))) 817 position = (position + 2) % vtotal; 818 } else if (HAS_PCH_SPLIT(dev)) { 819 /* 820 * The scanline counter increments at the leading edge 821 * of hsync, ie. it completely misses the active portion 822 * of the line. Fix up the counter at both edges of vblank 823 * to get a more accurate picture whether we're in vblank 824 * or not. 825 */ 826 in_vbl = ilk_pipe_in_vblank_locked(dev, pipe); 827 if ((in_vbl && position == vbl_start - 1) || 828 (!in_vbl && position == vbl_end - 1)) 829 position = (position + 1) % vtotal; 830 } else { 831 /* 832 * ISR vblank status bits don't work the way we'd want 833 * them to work on non-PCH platforms (for 834 * ilk_pipe_in_vblank_locked()), and there doesn't 835 * appear any other way to determine if we're currently 836 * in vblank. 837 * 838 * Instead let's assume that we're already in vblank if 839 * we got called from the vblank interrupt and the 840 * scanline counter value indicates that we're on the 841 * line just prior to vblank start. This should result 842 * in the correct answer, unless the vblank interrupt 843 * delivery really got delayed for almost exactly one 844 * full frame/field. 845 */ 846 if (flags & DRM_CALLED_FROM_VBLIRQ && 847 position == vbl_start - 1) { 848 position = (position + 1) % vtotal; 849 850 /* Signal this correction as "applied". */ 851 ret |= 0x8; 852 } 853 } 854 } else { 855 /* Have access to pixelcount since start of frame. 856 * We can split this into vertical and horizontal 857 * scanout position. 858 */ 859 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; 860 861 /* convert to pixel counts */ 862 vbl_start *= htotal; 863 vbl_end *= htotal; 864 vtotal *= htotal; 865 } 866 867 /* Get optional system timestamp after query. */ 868 if (etime) 869 *etime = ktime_get(); 870 871 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 872 873 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 874 875 in_vbl = position >= vbl_start && position < vbl_end; 876 877 /* 878 * While in vblank, position will be negative 879 * counting up towards 0 at vbl_end. And outside 880 * vblank, position will be positive counting 881 * up since vbl_end. 882 */ 883 if (position >= vbl_start) 884 position -= vbl_end; 885 else 886 position += vtotal - vbl_end; 887 888 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { 889 *vpos = position; 890 *hpos = 0; 891 } else { 892 *vpos = position / htotal; 893 *hpos = position - (*vpos * htotal); 894 } 895 896 /* In vblank? */ 897 if (in_vbl) 898 ret |= DRM_SCANOUTPOS_INVBL; 899 900 return ret; 901 } 902 903 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, 904 int *max_error, 905 struct timeval *vblank_time, 906 unsigned flags) 907 { 908 struct drm_crtc *crtc; 909 910 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) { 911 DRM_ERROR("Invalid crtc %d\n", pipe); 912 return -EINVAL; 913 } 914 915 /* Get drm_crtc to timestamp: */ 916 crtc = intel_get_crtc_for_pipe(dev, pipe); 917 if (crtc == NULL) { 918 DRM_ERROR("Invalid crtc %d\n", pipe); 919 return -EINVAL; 920 } 921 922 if (!crtc->enabled) { 923 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); 924 return -EBUSY; 925 } 926 927 /* Helper routine in DRM core does all the work: */ 928 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, 929 vblank_time, flags, 930 crtc, 931 &to_intel_crtc(crtc)->config.adjusted_mode); 932 } 933 934 static bool intel_hpd_irq_event(struct drm_device *dev, 935 struct drm_connector *connector) 936 { 937 enum drm_connector_status old_status; 938 939 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); 940 old_status = connector->status; 941 942 connector->status = connector->funcs->detect(connector, false); 943 if (old_status == connector->status) 944 return false; 945 946 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n", 947 connector->base.id, 948 drm_get_connector_name(connector), 949 drm_get_connector_status_name(old_status), 950 drm_get_connector_status_name(connector->status)); 951 952 return true; 953 } 954 955 /* 956 * Handle hotplug events outside the interrupt handler proper. 957 */ 958 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000) 959 960 static void i915_hotplug_work_func(struct work_struct *work) 961 { 962 struct drm_i915_private *dev_priv = 963 container_of(work, struct drm_i915_private, hotplug_work); 964 struct drm_device *dev = dev_priv->dev; 965 struct drm_mode_config *mode_config = &dev->mode_config; 966 struct intel_connector *intel_connector; 967 struct intel_encoder *intel_encoder; 968 struct drm_connector *connector; 969 unsigned long irqflags; 970 bool hpd_disabled = false; 971 bool changed = false; 972 u32 hpd_event_bits; 973 974 /* HPD irq before everything is fully set up. */ 975 if (!dev_priv->enable_hotplug_processing) 976 return; 977 978 mutex_lock(&mode_config->mutex); 979 DRM_DEBUG_KMS("running encoder hotplug functions\n"); 980 981 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 982 983 hpd_event_bits = dev_priv->hpd_event_bits; 984 dev_priv->hpd_event_bits = 0; 985 list_for_each_entry(connector, &mode_config->connector_list, head) { 986 intel_connector = to_intel_connector(connector); 987 intel_encoder = intel_connector->encoder; 988 if (intel_encoder->hpd_pin > HPD_NONE && 989 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED && 990 connector->polled == DRM_CONNECTOR_POLL_HPD) { 991 DRM_INFO("HPD interrupt storm detected on connector %s: " 992 "switching from hotplug detection to polling\n", 993 drm_get_connector_name(connector)); 994 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED; 995 connector->polled = DRM_CONNECTOR_POLL_CONNECT 996 | DRM_CONNECTOR_POLL_DISCONNECT; 997 hpd_disabled = true; 998 } 999 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { 1000 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n", 1001 drm_get_connector_name(connector), intel_encoder->hpd_pin); 1002 } 1003 } 1004 /* if there were no outputs to poll, poll was disabled, 1005 * therefore make sure it's enabled when disabling HPD on 1006 * some connectors */ 1007 if (hpd_disabled) { 1008 drm_kms_helper_poll_enable(dev); 1009 mod_timer(&dev_priv->hotplug_reenable_timer, 1010 jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY)); 1011 } 1012 1013 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1014 1015 list_for_each_entry(connector, &mode_config->connector_list, head) { 1016 intel_connector = to_intel_connector(connector); 1017 intel_encoder = intel_connector->encoder; 1018 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { 1019 if (intel_encoder->hot_plug) 1020 intel_encoder->hot_plug(intel_encoder); 1021 if (intel_hpd_irq_event(dev, connector)) 1022 changed = true; 1023 } 1024 } 1025 mutex_unlock(&mode_config->mutex); 1026 1027 if (changed) 1028 drm_kms_helper_hotplug_event(dev); 1029 } 1030 1031 static void intel_hpd_irq_uninstall(struct drm_i915_private *dev_priv) 1032 { 1033 del_timer_sync(&dev_priv->hotplug_reenable_timer); 1034 } 1035 1036 static void ironlake_rps_change_irq_handler(struct drm_device *dev) 1037 { 1038 struct drm_i915_private *dev_priv = dev->dev_private; 1039 u32 busy_up, busy_down, max_avg, min_avg; 1040 u8 new_delay; 1041 1042 spin_lock(&mchdev_lock); 1043 1044 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); 1045 1046 new_delay = dev_priv->ips.cur_delay; 1047 1048 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); 1049 busy_up = I915_READ(RCPREVBSYTUPAVG); 1050 busy_down = I915_READ(RCPREVBSYTDNAVG); 1051 max_avg = I915_READ(RCBMAXAVG); 1052 min_avg = I915_READ(RCBMINAVG); 1053 1054 /* Handle RCS change request from hw */ 1055 if (busy_up > max_avg) { 1056 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) 1057 new_delay = dev_priv->ips.cur_delay - 1; 1058 if (new_delay < dev_priv->ips.max_delay) 1059 new_delay = dev_priv->ips.max_delay; 1060 } else if (busy_down < min_avg) { 1061 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) 1062 new_delay = dev_priv->ips.cur_delay + 1; 1063 if (new_delay > dev_priv->ips.min_delay) 1064 new_delay = dev_priv->ips.min_delay; 1065 } 1066 1067 if (ironlake_set_drps(dev, new_delay)) 1068 dev_priv->ips.cur_delay = new_delay; 1069 1070 spin_unlock(&mchdev_lock); 1071 1072 return; 1073 } 1074 1075 static void notify_ring(struct drm_device *dev, 1076 struct intel_ring_buffer *ring) 1077 { 1078 if (ring->obj == NULL) 1079 return; 1080 1081 trace_i915_gem_request_complete(ring); 1082 1083 wake_up_all(&ring->irq_queue); 1084 i915_queue_hangcheck(dev); 1085 } 1086 1087 static void gen6_pm_rps_work(struct work_struct *work) 1088 { 1089 struct drm_i915_private *dev_priv = 1090 container_of(work, struct drm_i915_private, rps.work); 1091 u32 pm_iir; 1092 int new_delay, adj; 1093 1094 spin_lock_irq(&dev_priv->irq_lock); 1095 pm_iir = dev_priv->rps.pm_iir; 1096 dev_priv->rps.pm_iir = 0; 1097 /* Make sure not to corrupt PMIMR state used by ringbuffer code */ 1098 snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); 1099 spin_unlock_irq(&dev_priv->irq_lock); 1100 1101 /* Make sure we didn't queue anything we're not going to process. */ 1102 WARN_ON(pm_iir & ~dev_priv->pm_rps_events); 1103 1104 if ((pm_iir & dev_priv->pm_rps_events) == 0) 1105 return; 1106 1107 mutex_lock(&dev_priv->rps.hw_lock); 1108 1109 adj = dev_priv->rps.last_adj; 1110 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { 1111 if (adj > 0) 1112 adj *= 2; 1113 else 1114 adj = 1; 1115 new_delay = dev_priv->rps.cur_freq + adj; 1116 1117 /* 1118 * For better performance, jump directly 1119 * to RPe if we're below it. 1120 */ 1121 if (new_delay < dev_priv->rps.efficient_freq) 1122 new_delay = dev_priv->rps.efficient_freq; 1123 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { 1124 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq) 1125 new_delay = dev_priv->rps.efficient_freq; 1126 else 1127 new_delay = dev_priv->rps.min_freq_softlimit; 1128 adj = 0; 1129 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { 1130 if (adj < 0) 1131 adj *= 2; 1132 else 1133 adj = -1; 1134 new_delay = dev_priv->rps.cur_freq + adj; 1135 } else { /* unknown event */ 1136 new_delay = dev_priv->rps.cur_freq; 1137 } 1138 1139 /* sysfs frequency interfaces may have snuck in while servicing the 1140 * interrupt 1141 */ 1142 new_delay = clamp_t(int, new_delay, 1143 dev_priv->rps.min_freq_softlimit, 1144 dev_priv->rps.max_freq_softlimit); 1145 1146 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq; 1147 1148 if (IS_VALLEYVIEW(dev_priv->dev)) 1149 valleyview_set_rps(dev_priv->dev, new_delay); 1150 else 1151 gen6_set_rps(dev_priv->dev, new_delay); 1152 1153 mutex_unlock(&dev_priv->rps.hw_lock); 1154 } 1155 1156 1157 /** 1158 * ivybridge_parity_work - Workqueue called when a parity error interrupt 1159 * occurred. 1160 * @work: workqueue struct 1161 * 1162 * Doesn't actually do anything except notify userspace. As a consequence of 1163 * this event, userspace should try to remap the bad rows since statistically 1164 * it is likely the same row is more likely to go bad again. 1165 */ 1166 static void ivybridge_parity_work(struct work_struct *work) 1167 { 1168 struct drm_i915_private *dev_priv = 1169 container_of(work, struct drm_i915_private, l3_parity.error_work); 1170 u32 error_status, row, bank, subbank; 1171 char *parity_event[6]; 1172 uint32_t misccpctl; 1173 unsigned long flags; 1174 uint8_t slice = 0; 1175 1176 /* We must turn off DOP level clock gating to access the L3 registers. 1177 * In order to prevent a get/put style interface, acquire struct mutex 1178 * any time we access those registers. 1179 */ 1180 mutex_lock(&dev_priv->dev->struct_mutex); 1181 1182 /* If we've screwed up tracking, just let the interrupt fire again */ 1183 if (WARN_ON(!dev_priv->l3_parity.which_slice)) 1184 goto out; 1185 1186 misccpctl = I915_READ(GEN7_MISCCPCTL); 1187 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); 1188 POSTING_READ(GEN7_MISCCPCTL); 1189 1190 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { 1191 u32 reg; 1192 1193 slice--; 1194 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev))) 1195 break; 1196 1197 dev_priv->l3_parity.which_slice &= ~(1<<slice); 1198 1199 reg = GEN7_L3CDERRST1 + (slice * 0x200); 1200 1201 error_status = I915_READ(reg); 1202 row = GEN7_PARITY_ERROR_ROW(error_status); 1203 bank = GEN7_PARITY_ERROR_BANK(error_status); 1204 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); 1205 1206 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); 1207 POSTING_READ(reg); 1208 1209 parity_event[0] = I915_L3_PARITY_UEVENT "=1"; 1210 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); 1211 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); 1212 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); 1213 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); 1214 parity_event[5] = NULL; 1215 1216 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj, 1217 KOBJ_CHANGE, parity_event); 1218 1219 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", 1220 slice, row, bank, subbank); 1221 1222 kfree(parity_event[4]); 1223 kfree(parity_event[3]); 1224 kfree(parity_event[2]); 1225 kfree(parity_event[1]); 1226 } 1227 1228 I915_WRITE(GEN7_MISCCPCTL, misccpctl); 1229 1230 out: 1231 WARN_ON(dev_priv->l3_parity.which_slice); 1232 spin_lock_irqsave(&dev_priv->irq_lock, flags); 1233 ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev)); 1234 spin_unlock_irqrestore(&dev_priv->irq_lock, flags); 1235 1236 mutex_unlock(&dev_priv->dev->struct_mutex); 1237 } 1238 1239 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir) 1240 { 1241 struct drm_i915_private *dev_priv = dev->dev_private; 1242 1243 if (!HAS_L3_DPF(dev)) 1244 return; 1245 1246 spin_lock(&dev_priv->irq_lock); 1247 ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev)); 1248 spin_unlock(&dev_priv->irq_lock); 1249 1250 iir &= GT_PARITY_ERROR(dev); 1251 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1) 1252 dev_priv->l3_parity.which_slice |= 1 << 1; 1253 1254 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) 1255 dev_priv->l3_parity.which_slice |= 1 << 0; 1256 1257 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); 1258 } 1259 1260 static void ilk_gt_irq_handler(struct drm_device *dev, 1261 struct drm_i915_private *dev_priv, 1262 u32 gt_iir) 1263 { 1264 if (gt_iir & 1265 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) 1266 notify_ring(dev, &dev_priv->ring[RCS]); 1267 if (gt_iir & ILK_BSD_USER_INTERRUPT) 1268 notify_ring(dev, &dev_priv->ring[VCS]); 1269 } 1270 1271 static void snb_gt_irq_handler(struct drm_device *dev, 1272 struct drm_i915_private *dev_priv, 1273 u32 gt_iir) 1274 { 1275 1276 if (gt_iir & 1277 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) 1278 notify_ring(dev, &dev_priv->ring[RCS]); 1279 if (gt_iir & GT_BSD_USER_INTERRUPT) 1280 notify_ring(dev, &dev_priv->ring[VCS]); 1281 if (gt_iir & GT_BLT_USER_INTERRUPT) 1282 notify_ring(dev, &dev_priv->ring[BCS]); 1283 1284 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | 1285 GT_BSD_CS_ERROR_INTERRUPT | 1286 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) { 1287 i915_handle_error(dev, false, "GT error interrupt 0x%08x", 1288 gt_iir); 1289 } 1290 1291 if (gt_iir & GT_PARITY_ERROR(dev)) 1292 ivybridge_parity_error_irq_handler(dev, gt_iir); 1293 } 1294 1295 static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev, 1296 struct drm_i915_private *dev_priv, 1297 u32 master_ctl) 1298 { 1299 u32 rcs, bcs, vcs; 1300 uint32_t tmp = 0; 1301 irqreturn_t ret = IRQ_NONE; 1302 1303 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { 1304 tmp = I915_READ(GEN8_GT_IIR(0)); 1305 if (tmp) { 1306 ret = IRQ_HANDLED; 1307 rcs = tmp >> GEN8_RCS_IRQ_SHIFT; 1308 bcs = tmp >> GEN8_BCS_IRQ_SHIFT; 1309 if (rcs & GT_RENDER_USER_INTERRUPT) 1310 notify_ring(dev, &dev_priv->ring[RCS]); 1311 if (bcs & GT_RENDER_USER_INTERRUPT) 1312 notify_ring(dev, &dev_priv->ring[BCS]); 1313 I915_WRITE(GEN8_GT_IIR(0), tmp); 1314 } else 1315 DRM_ERROR("The master control interrupt lied (GT0)!\n"); 1316 } 1317 1318 if (master_ctl & GEN8_GT_VCS1_IRQ) { 1319 tmp = I915_READ(GEN8_GT_IIR(1)); 1320 if (tmp) { 1321 ret = IRQ_HANDLED; 1322 vcs = tmp >> GEN8_VCS1_IRQ_SHIFT; 1323 if (vcs & GT_RENDER_USER_INTERRUPT) 1324 notify_ring(dev, &dev_priv->ring[VCS]); 1325 I915_WRITE(GEN8_GT_IIR(1), tmp); 1326 } else 1327 DRM_ERROR("The master control interrupt lied (GT1)!\n"); 1328 } 1329 1330 if (master_ctl & GEN8_GT_VECS_IRQ) { 1331 tmp = I915_READ(GEN8_GT_IIR(3)); 1332 if (tmp) { 1333 ret = IRQ_HANDLED; 1334 vcs = tmp >> GEN8_VECS_IRQ_SHIFT; 1335 if (vcs & GT_RENDER_USER_INTERRUPT) 1336 notify_ring(dev, &dev_priv->ring[VECS]); 1337 I915_WRITE(GEN8_GT_IIR(3), tmp); 1338 } else 1339 DRM_ERROR("The master control interrupt lied (GT3)!\n"); 1340 } 1341 1342 return ret; 1343 } 1344 1345 #define HPD_STORM_DETECT_PERIOD 1000 1346 #define HPD_STORM_THRESHOLD 5 1347 1348 static inline void intel_hpd_irq_handler(struct drm_device *dev, 1349 u32 hotplug_trigger, 1350 const u32 *hpd) 1351 { 1352 struct drm_i915_private *dev_priv = dev->dev_private; 1353 int i; 1354 bool storm_detected = false; 1355 1356 if (!hotplug_trigger) 1357 return; 1358 1359 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", 1360 hotplug_trigger); 1361 1362 spin_lock(&dev_priv->irq_lock); 1363 for (i = 1; i < HPD_NUM_PINS; i++) { 1364 1365 if (hpd[i] & hotplug_trigger && 1366 dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) { 1367 /* 1368 * On GMCH platforms the interrupt mask bits only 1369 * prevent irq generation, not the setting of the 1370 * hotplug bits itself. So only WARN about unexpected 1371 * interrupts on saner platforms. 1372 */ 1373 WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev), 1374 "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n", 1375 hotplug_trigger, i, hpd[i]); 1376 1377 continue; 1378 } 1379 1380 if (!(hpd[i] & hotplug_trigger) || 1381 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED) 1382 continue; 1383 1384 dev_priv->hpd_event_bits |= (1 << i); 1385 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies, 1386 dev_priv->hpd_stats[i].hpd_last_jiffies 1387 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) { 1388 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies; 1389 dev_priv->hpd_stats[i].hpd_cnt = 0; 1390 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i); 1391 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) { 1392 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED; 1393 dev_priv->hpd_event_bits &= ~(1 << i); 1394 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i); 1395 storm_detected = true; 1396 } else { 1397 dev_priv->hpd_stats[i].hpd_cnt++; 1398 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i, 1399 dev_priv->hpd_stats[i].hpd_cnt); 1400 } 1401 } 1402 1403 if (storm_detected) 1404 dev_priv->display.hpd_irq_setup(dev); 1405 spin_unlock(&dev_priv->irq_lock); 1406 1407 /* 1408 * Our hotplug handler can grab modeset locks (by calling down into the 1409 * fb helpers). Hence it must not be run on our own dev-priv->wq work 1410 * queue for otherwise the flush_work in the pageflip code will 1411 * deadlock. 1412 */ 1413 schedule_work(&dev_priv->hotplug_work); 1414 } 1415 1416 static void gmbus_irq_handler(struct drm_device *dev) 1417 { 1418 struct drm_i915_private *dev_priv = dev->dev_private; 1419 1420 wake_up_all(&dev_priv->gmbus_wait_queue); 1421 } 1422 1423 static void dp_aux_irq_handler(struct drm_device *dev) 1424 { 1425 struct drm_i915_private *dev_priv = dev->dev_private; 1426 1427 wake_up_all(&dev_priv->gmbus_wait_queue); 1428 } 1429 1430 #if defined(CONFIG_DEBUG_FS) 1431 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, 1432 uint32_t crc0, uint32_t crc1, 1433 uint32_t crc2, uint32_t crc3, 1434 uint32_t crc4) 1435 { 1436 struct drm_i915_private *dev_priv = dev->dev_private; 1437 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; 1438 struct intel_pipe_crc_entry *entry; 1439 int head, tail; 1440 1441 spin_lock(&pipe_crc->lock); 1442 1443 if (!pipe_crc->entries) { 1444 spin_unlock(&pipe_crc->lock); 1445 DRM_ERROR("spurious interrupt\n"); 1446 return; 1447 } 1448 1449 head = pipe_crc->head; 1450 tail = pipe_crc->tail; 1451 1452 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) { 1453 spin_unlock(&pipe_crc->lock); 1454 DRM_ERROR("CRC buffer overflowing\n"); 1455 return; 1456 } 1457 1458 entry = &pipe_crc->entries[head]; 1459 1460 entry->frame = dev->driver->get_vblank_counter(dev, pipe); 1461 entry->crc[0] = crc0; 1462 entry->crc[1] = crc1; 1463 entry->crc[2] = crc2; 1464 entry->crc[3] = crc3; 1465 entry->crc[4] = crc4; 1466 1467 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); 1468 pipe_crc->head = head; 1469 1470 spin_unlock(&pipe_crc->lock); 1471 1472 wake_up_interruptible(&pipe_crc->wq); 1473 } 1474 #else 1475 static inline void 1476 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, 1477 uint32_t crc0, uint32_t crc1, 1478 uint32_t crc2, uint32_t crc3, 1479 uint32_t crc4) {} 1480 #endif 1481 1482 1483 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) 1484 { 1485 struct drm_i915_private *dev_priv = dev->dev_private; 1486 1487 display_pipe_crc_irq_handler(dev, pipe, 1488 I915_READ(PIPE_CRC_RES_1_IVB(pipe)), 1489 0, 0, 0, 0); 1490 } 1491 1492 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) 1493 { 1494 struct drm_i915_private *dev_priv = dev->dev_private; 1495 1496 display_pipe_crc_irq_handler(dev, pipe, 1497 I915_READ(PIPE_CRC_RES_1_IVB(pipe)), 1498 I915_READ(PIPE_CRC_RES_2_IVB(pipe)), 1499 I915_READ(PIPE_CRC_RES_3_IVB(pipe)), 1500 I915_READ(PIPE_CRC_RES_4_IVB(pipe)), 1501 I915_READ(PIPE_CRC_RES_5_IVB(pipe))); 1502 } 1503 1504 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) 1505 { 1506 struct drm_i915_private *dev_priv = dev->dev_private; 1507 uint32_t res1, res2; 1508 1509 if (INTEL_INFO(dev)->gen >= 3) 1510 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe)); 1511 else 1512 res1 = 0; 1513 1514 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) 1515 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe)); 1516 else 1517 res2 = 0; 1518 1519 display_pipe_crc_irq_handler(dev, pipe, 1520 I915_READ(PIPE_CRC_RES_RED(pipe)), 1521 I915_READ(PIPE_CRC_RES_GREEN(pipe)), 1522 I915_READ(PIPE_CRC_RES_BLUE(pipe)), 1523 res1, res2); 1524 } 1525 1526 /* The RPS events need forcewake, so we add them to a work queue and mask their 1527 * IMR bits until the work is done. Other interrupts can be processed without 1528 * the work queue. */ 1529 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) 1530 { 1531 if (pm_iir & dev_priv->pm_rps_events) { 1532 spin_lock(&dev_priv->irq_lock); 1533 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events; 1534 snb_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); 1535 spin_unlock(&dev_priv->irq_lock); 1536 1537 queue_work(dev_priv->wq, &dev_priv->rps.work); 1538 } 1539 1540 if (HAS_VEBOX(dev_priv->dev)) { 1541 if (pm_iir & PM_VEBOX_USER_INTERRUPT) 1542 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]); 1543 1544 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) { 1545 i915_handle_error(dev_priv->dev, false, 1546 "VEBOX CS error interrupt 0x%08x", 1547 pm_iir); 1548 } 1549 } 1550 } 1551 1552 static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir) 1553 { 1554 struct drm_i915_private *dev_priv = dev->dev_private; 1555 u32 pipe_stats[I915_MAX_PIPES] = { }; 1556 int pipe; 1557 1558 spin_lock(&dev_priv->irq_lock); 1559 for_each_pipe(pipe) { 1560 int reg; 1561 u32 mask, iir_bit = 0; 1562 1563 /* 1564 * PIPESTAT bits get signalled even when the interrupt is 1565 * disabled with the mask bits, and some of the status bits do 1566 * not generate interrupts at all (like the underrun bit). Hence 1567 * we need to be careful that we only handle what we want to 1568 * handle. 1569 */ 1570 mask = 0; 1571 if (__cpu_fifo_underrun_reporting_enabled(dev, pipe)) 1572 mask |= PIPE_FIFO_UNDERRUN_STATUS; 1573 1574 switch (pipe) { 1575 case PIPE_A: 1576 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT; 1577 break; 1578 case PIPE_B: 1579 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; 1580 break; 1581 } 1582 if (iir & iir_bit) 1583 mask |= dev_priv->pipestat_irq_mask[pipe]; 1584 1585 if (!mask) 1586 continue; 1587 1588 reg = PIPESTAT(pipe); 1589 mask |= PIPESTAT_INT_ENABLE_MASK; 1590 pipe_stats[pipe] = I915_READ(reg) & mask; 1591 1592 /* 1593 * Clear the PIPE*STAT regs before the IIR 1594 */ 1595 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS | 1596 PIPESTAT_INT_STATUS_MASK)) 1597 I915_WRITE(reg, pipe_stats[pipe]); 1598 } 1599 spin_unlock(&dev_priv->irq_lock); 1600 1601 for_each_pipe(pipe) { 1602 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) 1603 drm_handle_vblank(dev, pipe); 1604 1605 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) { 1606 intel_prepare_page_flip(dev, pipe); 1607 intel_finish_page_flip(dev, pipe); 1608 } 1609 1610 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 1611 i9xx_pipe_crc_irq_handler(dev, pipe); 1612 1613 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && 1614 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) 1615 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); 1616 } 1617 1618 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) 1619 gmbus_irq_handler(dev); 1620 } 1621 1622 static irqreturn_t valleyview_irq_handler(int irq, void *arg) 1623 { 1624 struct drm_device *dev = (struct drm_device *) arg; 1625 struct drm_i915_private *dev_priv = dev->dev_private; 1626 u32 iir, gt_iir, pm_iir; 1627 irqreturn_t ret = IRQ_NONE; 1628 1629 while (true) { 1630 iir = I915_READ(VLV_IIR); 1631 gt_iir = I915_READ(GTIIR); 1632 pm_iir = I915_READ(GEN6_PMIIR); 1633 1634 if (gt_iir == 0 && pm_iir == 0 && iir == 0) 1635 goto out; 1636 1637 ret = IRQ_HANDLED; 1638 1639 snb_gt_irq_handler(dev, dev_priv, gt_iir); 1640 1641 valleyview_pipestat_irq_handler(dev, iir); 1642 1643 /* Consume port. Then clear IIR or we'll miss events */ 1644 if (iir & I915_DISPLAY_PORT_INTERRUPT) { 1645 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); 1646 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; 1647 1648 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915); 1649 1650 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) 1651 dp_aux_irq_handler(dev); 1652 1653 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); 1654 I915_READ(PORT_HOTPLUG_STAT); 1655 } 1656 1657 1658 if (pm_iir) 1659 gen6_rps_irq_handler(dev_priv, pm_iir); 1660 1661 I915_WRITE(GTIIR, gt_iir); 1662 I915_WRITE(GEN6_PMIIR, pm_iir); 1663 I915_WRITE(VLV_IIR, iir); 1664 } 1665 1666 out: 1667 return ret; 1668 } 1669 1670 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) 1671 { 1672 struct drm_i915_private *dev_priv = dev->dev_private; 1673 int pipe; 1674 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; 1675 1676 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx); 1677 1678 if (pch_iir & SDE_AUDIO_POWER_MASK) { 1679 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> 1680 SDE_AUDIO_POWER_SHIFT); 1681 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", 1682 port_name(port)); 1683 } 1684 1685 if (pch_iir & SDE_AUX_MASK) 1686 dp_aux_irq_handler(dev); 1687 1688 if (pch_iir & SDE_GMBUS) 1689 gmbus_irq_handler(dev); 1690 1691 if (pch_iir & SDE_AUDIO_HDCP_MASK) 1692 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); 1693 1694 if (pch_iir & SDE_AUDIO_TRANS_MASK) 1695 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); 1696 1697 if (pch_iir & SDE_POISON) 1698 DRM_ERROR("PCH poison interrupt\n"); 1699 1700 if (pch_iir & SDE_FDI_MASK) 1701 for_each_pipe(pipe) 1702 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", 1703 pipe_name(pipe), 1704 I915_READ(FDI_RX_IIR(pipe))); 1705 1706 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) 1707 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); 1708 1709 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) 1710 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); 1711 1712 if (pch_iir & SDE_TRANSA_FIFO_UNDER) 1713 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, 1714 false)) 1715 DRM_ERROR("PCH transcoder A FIFO underrun\n"); 1716 1717 if (pch_iir & SDE_TRANSB_FIFO_UNDER) 1718 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, 1719 false)) 1720 DRM_ERROR("PCH transcoder B FIFO underrun\n"); 1721 } 1722 1723 static void ivb_err_int_handler(struct drm_device *dev) 1724 { 1725 struct drm_i915_private *dev_priv = dev->dev_private; 1726 u32 err_int = I915_READ(GEN7_ERR_INT); 1727 enum pipe pipe; 1728 1729 if (err_int & ERR_INT_POISON) 1730 DRM_ERROR("Poison interrupt\n"); 1731 1732 for_each_pipe(pipe) { 1733 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) { 1734 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, 1735 false)) 1736 DRM_ERROR("Pipe %c FIFO underrun\n", 1737 pipe_name(pipe)); 1738 } 1739 1740 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { 1741 if (IS_IVYBRIDGE(dev)) 1742 ivb_pipe_crc_irq_handler(dev, pipe); 1743 else 1744 hsw_pipe_crc_irq_handler(dev, pipe); 1745 } 1746 } 1747 1748 I915_WRITE(GEN7_ERR_INT, err_int); 1749 } 1750 1751 static void cpt_serr_int_handler(struct drm_device *dev) 1752 { 1753 struct drm_i915_private *dev_priv = dev->dev_private; 1754 u32 serr_int = I915_READ(SERR_INT); 1755 1756 if (serr_int & SERR_INT_POISON) 1757 DRM_ERROR("PCH poison interrupt\n"); 1758 1759 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) 1760 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, 1761 false)) 1762 DRM_ERROR("PCH transcoder A FIFO underrun\n"); 1763 1764 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) 1765 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, 1766 false)) 1767 DRM_ERROR("PCH transcoder B FIFO underrun\n"); 1768 1769 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) 1770 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C, 1771 false)) 1772 DRM_ERROR("PCH transcoder C FIFO underrun\n"); 1773 1774 I915_WRITE(SERR_INT, serr_int); 1775 } 1776 1777 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) 1778 { 1779 struct drm_i915_private *dev_priv = dev->dev_private; 1780 int pipe; 1781 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; 1782 1783 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt); 1784 1785 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { 1786 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> 1787 SDE_AUDIO_POWER_SHIFT_CPT); 1788 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n", 1789 port_name(port)); 1790 } 1791 1792 if (pch_iir & SDE_AUX_MASK_CPT) 1793 dp_aux_irq_handler(dev); 1794 1795 if (pch_iir & SDE_GMBUS_CPT) 1796 gmbus_irq_handler(dev); 1797 1798 if (pch_iir & SDE_AUDIO_CP_REQ_CPT) 1799 DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); 1800 1801 if (pch_iir & SDE_AUDIO_CP_CHG_CPT) 1802 DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); 1803 1804 if (pch_iir & SDE_FDI_MASK_CPT) 1805 for_each_pipe(pipe) 1806 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", 1807 pipe_name(pipe), 1808 I915_READ(FDI_RX_IIR(pipe))); 1809 1810 if (pch_iir & SDE_ERROR_CPT) 1811 cpt_serr_int_handler(dev); 1812 } 1813 1814 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir) 1815 { 1816 struct drm_i915_private *dev_priv = dev->dev_private; 1817 enum pipe pipe; 1818 1819 if (de_iir & DE_AUX_CHANNEL_A) 1820 dp_aux_irq_handler(dev); 1821 1822 if (de_iir & DE_GSE) 1823 intel_opregion_asle_intr(dev); 1824 1825 if (de_iir & DE_POISON) 1826 DRM_ERROR("Poison interrupt\n"); 1827 1828 for_each_pipe(pipe) { 1829 if (de_iir & DE_PIPE_VBLANK(pipe)) 1830 drm_handle_vblank(dev, pipe); 1831 1832 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) 1833 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) 1834 DRM_ERROR("Pipe %c FIFO underrun\n", 1835 pipe_name(pipe)); 1836 1837 if (de_iir & DE_PIPE_CRC_DONE(pipe)) 1838 i9xx_pipe_crc_irq_handler(dev, pipe); 1839 1840 /* plane/pipes map 1:1 on ilk+ */ 1841 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) { 1842 intel_prepare_page_flip(dev, pipe); 1843 intel_finish_page_flip_plane(dev, pipe); 1844 } 1845 } 1846 1847 /* check event from PCH */ 1848 if (de_iir & DE_PCH_EVENT) { 1849 u32 pch_iir = I915_READ(SDEIIR); 1850 1851 if (HAS_PCH_CPT(dev)) 1852 cpt_irq_handler(dev, pch_iir); 1853 else 1854 ibx_irq_handler(dev, pch_iir); 1855 1856 /* should clear PCH hotplug event before clear CPU irq */ 1857 I915_WRITE(SDEIIR, pch_iir); 1858 } 1859 1860 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT) 1861 ironlake_rps_change_irq_handler(dev); 1862 } 1863 1864 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir) 1865 { 1866 struct drm_i915_private *dev_priv = dev->dev_private; 1867 enum pipe pipe; 1868 1869 if (de_iir & DE_ERR_INT_IVB) 1870 ivb_err_int_handler(dev); 1871 1872 if (de_iir & DE_AUX_CHANNEL_A_IVB) 1873 dp_aux_irq_handler(dev); 1874 1875 if (de_iir & DE_GSE_IVB) 1876 intel_opregion_asle_intr(dev); 1877 1878 for_each_pipe(pipe) { 1879 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe))) 1880 drm_handle_vblank(dev, pipe); 1881 1882 /* plane/pipes map 1:1 on ilk+ */ 1883 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) { 1884 intel_prepare_page_flip(dev, pipe); 1885 intel_finish_page_flip_plane(dev, pipe); 1886 } 1887 } 1888 1889 /* check event from PCH */ 1890 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) { 1891 u32 pch_iir = I915_READ(SDEIIR); 1892 1893 cpt_irq_handler(dev, pch_iir); 1894 1895 /* clear PCH hotplug event before clear CPU irq */ 1896 I915_WRITE(SDEIIR, pch_iir); 1897 } 1898 } 1899 1900 static irqreturn_t ironlake_irq_handler(int irq, void *arg) 1901 { 1902 struct drm_device *dev = (struct drm_device *) arg; 1903 struct drm_i915_private *dev_priv = dev->dev_private; 1904 u32 de_iir, gt_iir, de_ier, sde_ier = 0; 1905 irqreturn_t ret = IRQ_NONE; 1906 1907 /* We get interrupts on unclaimed registers, so check for this before we 1908 * do any I915_{READ,WRITE}. */ 1909 intel_uncore_check_errors(dev); 1910 1911 /* disable master interrupt before clearing iir */ 1912 de_ier = I915_READ(DEIER); 1913 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); 1914 POSTING_READ(DEIER); 1915 1916 /* Disable south interrupts. We'll only write to SDEIIR once, so further 1917 * interrupts will will be stored on its back queue, and then we'll be 1918 * able to process them after we restore SDEIER (as soon as we restore 1919 * it, we'll get an interrupt if SDEIIR still has something to process 1920 * due to its back queue). */ 1921 if (!HAS_PCH_NOP(dev)) { 1922 sde_ier = I915_READ(SDEIER); 1923 I915_WRITE(SDEIER, 0); 1924 POSTING_READ(SDEIER); 1925 } 1926 1927 gt_iir = I915_READ(GTIIR); 1928 if (gt_iir) { 1929 if (INTEL_INFO(dev)->gen >= 6) 1930 snb_gt_irq_handler(dev, dev_priv, gt_iir); 1931 else 1932 ilk_gt_irq_handler(dev, dev_priv, gt_iir); 1933 I915_WRITE(GTIIR, gt_iir); 1934 ret = IRQ_HANDLED; 1935 } 1936 1937 de_iir = I915_READ(DEIIR); 1938 if (de_iir) { 1939 if (INTEL_INFO(dev)->gen >= 7) 1940 ivb_display_irq_handler(dev, de_iir); 1941 else 1942 ilk_display_irq_handler(dev, de_iir); 1943 I915_WRITE(DEIIR, de_iir); 1944 ret = IRQ_HANDLED; 1945 } 1946 1947 if (INTEL_INFO(dev)->gen >= 6) { 1948 u32 pm_iir = I915_READ(GEN6_PMIIR); 1949 if (pm_iir) { 1950 gen6_rps_irq_handler(dev_priv, pm_iir); 1951 I915_WRITE(GEN6_PMIIR, pm_iir); 1952 ret = IRQ_HANDLED; 1953 } 1954 } 1955 1956 I915_WRITE(DEIER, de_ier); 1957 POSTING_READ(DEIER); 1958 if (!HAS_PCH_NOP(dev)) { 1959 I915_WRITE(SDEIER, sde_ier); 1960 POSTING_READ(SDEIER); 1961 } 1962 1963 return ret; 1964 } 1965 1966 static irqreturn_t gen8_irq_handler(int irq, void *arg) 1967 { 1968 struct drm_device *dev = arg; 1969 struct drm_i915_private *dev_priv = dev->dev_private; 1970 u32 master_ctl; 1971 irqreturn_t ret = IRQ_NONE; 1972 uint32_t tmp = 0; 1973 enum pipe pipe; 1974 1975 master_ctl = I915_READ(GEN8_MASTER_IRQ); 1976 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL; 1977 if (!master_ctl) 1978 return IRQ_NONE; 1979 1980 I915_WRITE(GEN8_MASTER_IRQ, 0); 1981 POSTING_READ(GEN8_MASTER_IRQ); 1982 1983 ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl); 1984 1985 if (master_ctl & GEN8_DE_MISC_IRQ) { 1986 tmp = I915_READ(GEN8_DE_MISC_IIR); 1987 if (tmp & GEN8_DE_MISC_GSE) 1988 intel_opregion_asle_intr(dev); 1989 else if (tmp) 1990 DRM_ERROR("Unexpected DE Misc interrupt\n"); 1991 else 1992 DRM_ERROR("The master control interrupt lied (DE MISC)!\n"); 1993 1994 if (tmp) { 1995 I915_WRITE(GEN8_DE_MISC_IIR, tmp); 1996 ret = IRQ_HANDLED; 1997 } 1998 } 1999 2000 if (master_ctl & GEN8_DE_PORT_IRQ) { 2001 tmp = I915_READ(GEN8_DE_PORT_IIR); 2002 if (tmp & GEN8_AUX_CHANNEL_A) 2003 dp_aux_irq_handler(dev); 2004 else if (tmp) 2005 DRM_ERROR("Unexpected DE Port interrupt\n"); 2006 else 2007 DRM_ERROR("The master control interrupt lied (DE PORT)!\n"); 2008 2009 if (tmp) { 2010 I915_WRITE(GEN8_DE_PORT_IIR, tmp); 2011 ret = IRQ_HANDLED; 2012 } 2013 } 2014 2015 for_each_pipe(pipe) { 2016 uint32_t pipe_iir; 2017 2018 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) 2019 continue; 2020 2021 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe)); 2022 if (pipe_iir & GEN8_PIPE_VBLANK) 2023 drm_handle_vblank(dev, pipe); 2024 2025 if (pipe_iir & GEN8_PIPE_FLIP_DONE) { 2026 intel_prepare_page_flip(dev, pipe); 2027 intel_finish_page_flip_plane(dev, pipe); 2028 } 2029 2030 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE) 2031 hsw_pipe_crc_irq_handler(dev, pipe); 2032 2033 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) { 2034 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, 2035 false)) 2036 DRM_ERROR("Pipe %c FIFO underrun\n", 2037 pipe_name(pipe)); 2038 } 2039 2040 if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) { 2041 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x", 2042 pipe_name(pipe), 2043 pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS); 2044 } 2045 2046 if (pipe_iir) { 2047 ret = IRQ_HANDLED; 2048 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir); 2049 } else 2050 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n"); 2051 } 2052 2053 if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) { 2054 /* 2055 * FIXME(BDW): Assume for now that the new interrupt handling 2056 * scheme also closed the SDE interrupt handling race we've seen 2057 * on older pch-split platforms. But this needs testing. 2058 */ 2059 u32 pch_iir = I915_READ(SDEIIR); 2060 2061 cpt_irq_handler(dev, pch_iir); 2062 2063 if (pch_iir) { 2064 I915_WRITE(SDEIIR, pch_iir); 2065 ret = IRQ_HANDLED; 2066 } 2067 } 2068 2069 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); 2070 POSTING_READ(GEN8_MASTER_IRQ); 2071 2072 return ret; 2073 } 2074 2075 static void i915_error_wake_up(struct drm_i915_private *dev_priv, 2076 bool reset_completed) 2077 { 2078 struct intel_ring_buffer *ring; 2079 int i; 2080 2081 /* 2082 * Notify all waiters for GPU completion events that reset state has 2083 * been changed, and that they need to restart their wait after 2084 * checking for potential errors (and bail out to drop locks if there is 2085 * a gpu reset pending so that i915_error_work_func can acquire them). 2086 */ 2087 2088 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */ 2089 for_each_ring(ring, dev_priv, i) 2090 wake_up_all(&ring->irq_queue); 2091 2092 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */ 2093 wake_up_all(&dev_priv->pending_flip_queue); 2094 2095 /* 2096 * Signal tasks blocked in i915_gem_wait_for_error that the pending 2097 * reset state is cleared. 2098 */ 2099 if (reset_completed) 2100 wake_up_all(&dev_priv->gpu_error.reset_queue); 2101 } 2102 2103 /** 2104 * i915_error_work_func - do process context error handling work 2105 * @work: work struct 2106 * 2107 * Fire an error uevent so userspace can see that a hang or error 2108 * was detected. 2109 */ 2110 static void i915_error_work_func(struct work_struct *work) 2111 { 2112 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error, 2113 work); 2114 struct drm_i915_private *dev_priv = 2115 container_of(error, struct drm_i915_private, gpu_error); 2116 struct drm_device *dev = dev_priv->dev; 2117 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL }; 2118 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL }; 2119 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL }; 2120 int ret; 2121 2122 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event); 2123 2124 /* 2125 * Note that there's only one work item which does gpu resets, so we 2126 * need not worry about concurrent gpu resets potentially incrementing 2127 * error->reset_counter twice. We only need to take care of another 2128 * racing irq/hangcheck declaring the gpu dead for a second time. A 2129 * quick check for that is good enough: schedule_work ensures the 2130 * correct ordering between hang detection and this work item, and since 2131 * the reset in-progress bit is only ever set by code outside of this 2132 * work we don't need to worry about any other races. 2133 */ 2134 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) { 2135 DRM_DEBUG_DRIVER("resetting chip\n"); 2136 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, 2137 reset_event); 2138 2139 /* 2140 * All state reset _must_ be completed before we update the 2141 * reset counter, for otherwise waiters might miss the reset 2142 * pending state and not properly drop locks, resulting in 2143 * deadlocks with the reset work. 2144 */ 2145 ret = i915_reset(dev); 2146 2147 intel_display_handle_reset(dev); 2148 2149 if (ret == 0) { 2150 /* 2151 * After all the gem state is reset, increment the reset 2152 * counter and wake up everyone waiting for the reset to 2153 * complete. 2154 * 2155 * Since unlock operations are a one-sided barrier only, 2156 * we need to insert a barrier here to order any seqno 2157 * updates before 2158 * the counter increment. 2159 */ 2160 smp_mb__before_atomic(); 2161 atomic_inc(&dev_priv->gpu_error.reset_counter); 2162 2163 kobject_uevent_env(&dev->primary->kdev->kobj, 2164 KOBJ_CHANGE, reset_done_event); 2165 } else { 2166 atomic_set_mask(I915_WEDGED, &error->reset_counter); 2167 } 2168 2169 /* 2170 * Note: The wake_up also serves as a memory barrier so that 2171 * waiters see the update value of the reset counter atomic_t. 2172 */ 2173 i915_error_wake_up(dev_priv, true); 2174 } 2175 } 2176 2177 static void i915_report_and_clear_eir(struct drm_device *dev) 2178 { 2179 struct drm_i915_private *dev_priv = dev->dev_private; 2180 uint32_t instdone[I915_NUM_INSTDONE_REG]; 2181 u32 eir = I915_READ(EIR); 2182 int pipe, i; 2183 2184 if (!eir) 2185 return; 2186 2187 pr_err("render error detected, EIR: 0x%08x\n", eir); 2188 2189 i915_get_extra_instdone(dev, instdone); 2190 2191 if (IS_G4X(dev)) { 2192 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { 2193 u32 ipeir = I915_READ(IPEIR_I965); 2194 2195 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); 2196 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); 2197 for (i = 0; i < ARRAY_SIZE(instdone); i++) 2198 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); 2199 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); 2200 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); 2201 I915_WRITE(IPEIR_I965, ipeir); 2202 POSTING_READ(IPEIR_I965); 2203 } 2204 if (eir & GM45_ERROR_PAGE_TABLE) { 2205 u32 pgtbl_err = I915_READ(PGTBL_ER); 2206 pr_err("page table error\n"); 2207 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); 2208 I915_WRITE(PGTBL_ER, pgtbl_err); 2209 POSTING_READ(PGTBL_ER); 2210 } 2211 } 2212 2213 if (!IS_GEN2(dev)) { 2214 if (eir & I915_ERROR_PAGE_TABLE) { 2215 u32 pgtbl_err = I915_READ(PGTBL_ER); 2216 pr_err("page table error\n"); 2217 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); 2218 I915_WRITE(PGTBL_ER, pgtbl_err); 2219 POSTING_READ(PGTBL_ER); 2220 } 2221 } 2222 2223 if (eir & I915_ERROR_MEMORY_REFRESH) { 2224 pr_err("memory refresh error:\n"); 2225 for_each_pipe(pipe) 2226 pr_err("pipe %c stat: 0x%08x\n", 2227 pipe_name(pipe), I915_READ(PIPESTAT(pipe))); 2228 /* pipestat has already been acked */ 2229 } 2230 if (eir & I915_ERROR_INSTRUCTION) { 2231 pr_err("instruction error\n"); 2232 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); 2233 for (i = 0; i < ARRAY_SIZE(instdone); i++) 2234 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); 2235 if (INTEL_INFO(dev)->gen < 4) { 2236 u32 ipeir = I915_READ(IPEIR); 2237 2238 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); 2239 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); 2240 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); 2241 I915_WRITE(IPEIR, ipeir); 2242 POSTING_READ(IPEIR); 2243 } else { 2244 u32 ipeir = I915_READ(IPEIR_I965); 2245 2246 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); 2247 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); 2248 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); 2249 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); 2250 I915_WRITE(IPEIR_I965, ipeir); 2251 POSTING_READ(IPEIR_I965); 2252 } 2253 } 2254 2255 I915_WRITE(EIR, eir); 2256 POSTING_READ(EIR); 2257 eir = I915_READ(EIR); 2258 if (eir) { 2259 /* 2260 * some errors might have become stuck, 2261 * mask them. 2262 */ 2263 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); 2264 I915_WRITE(EMR, I915_READ(EMR) | eir); 2265 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); 2266 } 2267 } 2268 2269 /** 2270 * i915_handle_error - handle an error interrupt 2271 * @dev: drm device 2272 * 2273 * Do some basic checking of regsiter state at error interrupt time and 2274 * dump it to the syslog. Also call i915_capture_error_state() to make 2275 * sure we get a record and make it available in debugfs. Fire a uevent 2276 * so userspace knows something bad happened (should trigger collection 2277 * of a ring dump etc.). 2278 */ 2279 void i915_handle_error(struct drm_device *dev, bool wedged, 2280 const char *fmt, ...) 2281 { 2282 struct drm_i915_private *dev_priv = dev->dev_private; 2283 va_list args; 2284 char error_msg[80]; 2285 2286 va_start(args, fmt); 2287 vscnprintf(error_msg, sizeof(error_msg), fmt, args); 2288 va_end(args); 2289 2290 i915_capture_error_state(dev, wedged, error_msg); 2291 i915_report_and_clear_eir(dev); 2292 2293 if (wedged) { 2294 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG, 2295 &dev_priv->gpu_error.reset_counter); 2296 2297 /* 2298 * Wakeup waiting processes so that the reset work function 2299 * i915_error_work_func doesn't deadlock trying to grab various 2300 * locks. By bumping the reset counter first, the woken 2301 * processes will see a reset in progress and back off, 2302 * releasing their locks and then wait for the reset completion. 2303 * We must do this for _all_ gpu waiters that might hold locks 2304 * that the reset work needs to acquire. 2305 * 2306 * Note: The wake_up serves as the required memory barrier to 2307 * ensure that the waiters see the updated value of the reset 2308 * counter atomic_t. 2309 */ 2310 i915_error_wake_up(dev_priv, false); 2311 } 2312 2313 /* 2314 * Our reset work can grab modeset locks (since it needs to reset the 2315 * state of outstanding pagelips). Hence it must not be run on our own 2316 * dev-priv->wq work queue for otherwise the flush_work in the pageflip 2317 * code will deadlock. 2318 */ 2319 schedule_work(&dev_priv->gpu_error.work); 2320 } 2321 2322 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe) 2323 { 2324 struct drm_i915_private *dev_priv = dev->dev_private; 2325 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 2326 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2327 struct drm_i915_gem_object *obj; 2328 struct intel_unpin_work *work; 2329 unsigned long flags; 2330 bool stall_detected; 2331 2332 /* Ignore early vblank irqs */ 2333 if (intel_crtc == NULL) 2334 return; 2335 2336 spin_lock_irqsave(&dev->event_lock, flags); 2337 work = intel_crtc->unpin_work; 2338 2339 if (work == NULL || 2340 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE || 2341 !work->enable_stall_check) { 2342 /* Either the pending flip IRQ arrived, or we're too early. Don't check */ 2343 spin_unlock_irqrestore(&dev->event_lock, flags); 2344 return; 2345 } 2346 2347 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ 2348 obj = work->pending_flip_obj; 2349 if (INTEL_INFO(dev)->gen >= 4) { 2350 int dspsurf = DSPSURF(intel_crtc->plane); 2351 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) == 2352 i915_gem_obj_ggtt_offset(obj); 2353 } else { 2354 int dspaddr = DSPADDR(intel_crtc->plane); 2355 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) + 2356 crtc->y * crtc->primary->fb->pitches[0] + 2357 crtc->x * crtc->primary->fb->bits_per_pixel/8); 2358 } 2359 2360 spin_unlock_irqrestore(&dev->event_lock, flags); 2361 2362 if (stall_detected) { 2363 DRM_DEBUG_DRIVER("Pageflip stall detected\n"); 2364 intel_prepare_page_flip(dev, intel_crtc->plane); 2365 } 2366 } 2367 2368 /* Called from drm generic code, passed 'crtc' which 2369 * we use as a pipe index 2370 */ 2371 static int i915_enable_vblank(struct drm_device *dev, int pipe) 2372 { 2373 struct drm_i915_private *dev_priv = dev->dev_private; 2374 unsigned long irqflags; 2375 2376 if (!i915_pipe_enabled(dev, pipe)) 2377 return -EINVAL; 2378 2379 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2380 if (INTEL_INFO(dev)->gen >= 4) 2381 i915_enable_pipestat(dev_priv, pipe, 2382 PIPE_START_VBLANK_INTERRUPT_STATUS); 2383 else 2384 i915_enable_pipestat(dev_priv, pipe, 2385 PIPE_VBLANK_INTERRUPT_STATUS); 2386 2387 /* maintain vblank delivery even in deep C-states */ 2388 if (INTEL_INFO(dev)->gen == 3) 2389 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS)); 2390 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 2391 2392 return 0; 2393 } 2394 2395 static int ironlake_enable_vblank(struct drm_device *dev, int pipe) 2396 { 2397 struct drm_i915_private *dev_priv = dev->dev_private; 2398 unsigned long irqflags; 2399 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : 2400 DE_PIPE_VBLANK(pipe); 2401 2402 if (!i915_pipe_enabled(dev, pipe)) 2403 return -EINVAL; 2404 2405 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2406 ironlake_enable_display_irq(dev_priv, bit); 2407 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 2408 2409 return 0; 2410 } 2411 2412 static int valleyview_enable_vblank(struct drm_device *dev, int pipe) 2413 { 2414 struct drm_i915_private *dev_priv = dev->dev_private; 2415 unsigned long irqflags; 2416 2417 if (!i915_pipe_enabled(dev, pipe)) 2418 return -EINVAL; 2419 2420 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2421 i915_enable_pipestat(dev_priv, pipe, 2422 PIPE_START_VBLANK_INTERRUPT_STATUS); 2423 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 2424 2425 return 0; 2426 } 2427 2428 static int gen8_enable_vblank(struct drm_device *dev, int pipe) 2429 { 2430 struct drm_i915_private *dev_priv = dev->dev_private; 2431 unsigned long irqflags; 2432 2433 if (!i915_pipe_enabled(dev, pipe)) 2434 return -EINVAL; 2435 2436 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2437 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK; 2438 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); 2439 POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); 2440 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 2441 return 0; 2442 } 2443 2444 /* Called from drm generic code, passed 'crtc' which 2445 * we use as a pipe index 2446 */ 2447 static void i915_disable_vblank(struct drm_device *dev, int pipe) 2448 { 2449 struct drm_i915_private *dev_priv = dev->dev_private; 2450 unsigned long irqflags; 2451 2452 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2453 if (INTEL_INFO(dev)->gen == 3) 2454 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS)); 2455 2456 i915_disable_pipestat(dev_priv, pipe, 2457 PIPE_VBLANK_INTERRUPT_STATUS | 2458 PIPE_START_VBLANK_INTERRUPT_STATUS); 2459 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 2460 } 2461 2462 static void ironlake_disable_vblank(struct drm_device *dev, int pipe) 2463 { 2464 struct drm_i915_private *dev_priv = dev->dev_private; 2465 unsigned long irqflags; 2466 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : 2467 DE_PIPE_VBLANK(pipe); 2468 2469 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2470 ironlake_disable_display_irq(dev_priv, bit); 2471 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 2472 } 2473 2474 static void valleyview_disable_vblank(struct drm_device *dev, int pipe) 2475 { 2476 struct drm_i915_private *dev_priv = dev->dev_private; 2477 unsigned long irqflags; 2478 2479 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2480 i915_disable_pipestat(dev_priv, pipe, 2481 PIPE_START_VBLANK_INTERRUPT_STATUS); 2482 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 2483 } 2484 2485 static void gen8_disable_vblank(struct drm_device *dev, int pipe) 2486 { 2487 struct drm_i915_private *dev_priv = dev->dev_private; 2488 unsigned long irqflags; 2489 2490 if (!i915_pipe_enabled(dev, pipe)) 2491 return; 2492 2493 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2494 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK; 2495 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); 2496 POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); 2497 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 2498 } 2499 2500 static u32 2501 ring_last_seqno(struct intel_ring_buffer *ring) 2502 { 2503 return list_entry(ring->request_list.prev, 2504 struct drm_i915_gem_request, list)->seqno; 2505 } 2506 2507 static bool 2508 ring_idle(struct intel_ring_buffer *ring, u32 seqno) 2509 { 2510 return (list_empty(&ring->request_list) || 2511 i915_seqno_passed(seqno, ring_last_seqno(ring))); 2512 } 2513 2514 static struct intel_ring_buffer * 2515 semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno) 2516 { 2517 struct drm_i915_private *dev_priv = ring->dev->dev_private; 2518 u32 cmd, ipehr, head; 2519 int i; 2520 2521 ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); 2522 if ((ipehr & ~(0x3 << 16)) != 2523 (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER)) 2524 return NULL; 2525 2526 /* 2527 * HEAD is likely pointing to the dword after the actual command, 2528 * so scan backwards until we find the MBOX. But limit it to just 3 2529 * dwords. Note that we don't care about ACTHD here since that might 2530 * point at at batch, and semaphores are always emitted into the 2531 * ringbuffer itself. 2532 */ 2533 head = I915_READ_HEAD(ring) & HEAD_ADDR; 2534 2535 for (i = 4; i; --i) { 2536 /* 2537 * Be paranoid and presume the hw has gone off into the wild - 2538 * our ring is smaller than what the hardware (and hence 2539 * HEAD_ADDR) allows. Also handles wrap-around. 2540 */ 2541 head &= ring->size - 1; 2542 2543 /* This here seems to blow up */ 2544 cmd = ioread32(ring->virtual_start + head); 2545 if (cmd == ipehr) 2546 break; 2547 2548 head -= 4; 2549 } 2550 2551 if (!i) 2552 return NULL; 2553 2554 *seqno = ioread32(ring->virtual_start + head + 4) + 1; 2555 return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3]; 2556 } 2557 2558 static int semaphore_passed(struct intel_ring_buffer *ring) 2559 { 2560 struct drm_i915_private *dev_priv = ring->dev->dev_private; 2561 struct intel_ring_buffer *signaller; 2562 u32 seqno, ctl; 2563 2564 ring->hangcheck.deadlock = true; 2565 2566 signaller = semaphore_waits_for(ring, &seqno); 2567 if (signaller == NULL || signaller->hangcheck.deadlock) 2568 return -1; 2569 2570 /* cursory check for an unkickable deadlock */ 2571 ctl = I915_READ_CTL(signaller); 2572 if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0) 2573 return -1; 2574 2575 return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno); 2576 } 2577 2578 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv) 2579 { 2580 struct intel_ring_buffer *ring; 2581 int i; 2582 2583 for_each_ring(ring, dev_priv, i) 2584 ring->hangcheck.deadlock = false; 2585 } 2586 2587 static enum intel_ring_hangcheck_action 2588 ring_stuck(struct intel_ring_buffer *ring, u64 acthd) 2589 { 2590 struct drm_device *dev = ring->dev; 2591 struct drm_i915_private *dev_priv = dev->dev_private; 2592 u32 tmp; 2593 2594 if (ring->hangcheck.acthd != acthd) 2595 return HANGCHECK_ACTIVE; 2596 2597 if (IS_GEN2(dev)) 2598 return HANGCHECK_HUNG; 2599 2600 /* Is the chip hanging on a WAIT_FOR_EVENT? 2601 * If so we can simply poke the RB_WAIT bit 2602 * and break the hang. This should work on 2603 * all but the second generation chipsets. 2604 */ 2605 tmp = I915_READ_CTL(ring); 2606 if (tmp & RING_WAIT) { 2607 i915_handle_error(dev, false, 2608 "Kicking stuck wait on %s", 2609 ring->name); 2610 I915_WRITE_CTL(ring, tmp); 2611 return HANGCHECK_KICK; 2612 } 2613 2614 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) { 2615 switch (semaphore_passed(ring)) { 2616 default: 2617 return HANGCHECK_HUNG; 2618 case 1: 2619 i915_handle_error(dev, false, 2620 "Kicking stuck semaphore on %s", 2621 ring->name); 2622 I915_WRITE_CTL(ring, tmp); 2623 return HANGCHECK_KICK; 2624 case 0: 2625 return HANGCHECK_WAIT; 2626 } 2627 } 2628 2629 return HANGCHECK_HUNG; 2630 } 2631 2632 /** 2633 * This is called when the chip hasn't reported back with completed 2634 * batchbuffers in a long time. We keep track per ring seqno progress and 2635 * if there are no progress, hangcheck score for that ring is increased. 2636 * Further, acthd is inspected to see if the ring is stuck. On stuck case 2637 * we kick the ring. If we see no progress on three subsequent calls 2638 * we assume chip is wedged and try to fix it by resetting the chip. 2639 */ 2640 static void i915_hangcheck_elapsed(unsigned long data) 2641 { 2642 struct drm_device *dev = (struct drm_device *)data; 2643 struct drm_i915_private *dev_priv = dev->dev_private; 2644 struct intel_ring_buffer *ring; 2645 int i; 2646 int busy_count = 0, rings_hung = 0; 2647 bool stuck[I915_NUM_RINGS] = { 0 }; 2648 #define BUSY 1 2649 #define KICK 5 2650 #define HUNG 20 2651 2652 if (!i915.enable_hangcheck) 2653 return; 2654 2655 for_each_ring(ring, dev_priv, i) { 2656 u64 acthd; 2657 u32 seqno; 2658 bool busy = true; 2659 2660 semaphore_clear_deadlocks(dev_priv); 2661 2662 seqno = ring->get_seqno(ring, false); 2663 acthd = intel_ring_get_active_head(ring); 2664 2665 if (ring->hangcheck.seqno == seqno) { 2666 if (ring_idle(ring, seqno)) { 2667 ring->hangcheck.action = HANGCHECK_IDLE; 2668 2669 if (waitqueue_active(&ring->irq_queue)) { 2670 /* Issue a wake-up to catch stuck h/w. */ 2671 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) { 2672 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring))) 2673 DRM_ERROR("Hangcheck timer elapsed... %s idle\n", 2674 ring->name); 2675 else 2676 DRM_INFO("Fake missed irq on %s\n", 2677 ring->name); 2678 wake_up_all(&ring->irq_queue); 2679 } 2680 /* Safeguard against driver failure */ 2681 ring->hangcheck.score += BUSY; 2682 } else 2683 busy = false; 2684 } else { 2685 /* We always increment the hangcheck score 2686 * if the ring is busy and still processing 2687 * the same request, so that no single request 2688 * can run indefinitely (such as a chain of 2689 * batches). The only time we do not increment 2690 * the hangcheck score on this ring, if this 2691 * ring is in a legitimate wait for another 2692 * ring. In that case the waiting ring is a 2693 * victim and we want to be sure we catch the 2694 * right culprit. Then every time we do kick 2695 * the ring, add a small increment to the 2696 * score so that we can catch a batch that is 2697 * being repeatedly kicked and so responsible 2698 * for stalling the machine. 2699 */ 2700 ring->hangcheck.action = ring_stuck(ring, 2701 acthd); 2702 2703 switch (ring->hangcheck.action) { 2704 case HANGCHECK_IDLE: 2705 case HANGCHECK_WAIT: 2706 break; 2707 case HANGCHECK_ACTIVE: 2708 ring->hangcheck.score += BUSY; 2709 break; 2710 case HANGCHECK_KICK: 2711 ring->hangcheck.score += KICK; 2712 break; 2713 case HANGCHECK_HUNG: 2714 ring->hangcheck.score += HUNG; 2715 stuck[i] = true; 2716 break; 2717 } 2718 } 2719 } else { 2720 ring->hangcheck.action = HANGCHECK_ACTIVE; 2721 2722 /* Gradually reduce the count so that we catch DoS 2723 * attempts across multiple batches. 2724 */ 2725 if (ring->hangcheck.score > 0) 2726 ring->hangcheck.score--; 2727 } 2728 2729 ring->hangcheck.seqno = seqno; 2730 ring->hangcheck.acthd = acthd; 2731 busy_count += busy; 2732 } 2733 2734 for_each_ring(ring, dev_priv, i) { 2735 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) { 2736 DRM_INFO("%s on %s\n", 2737 stuck[i] ? "stuck" : "no progress", 2738 ring->name); 2739 rings_hung++; 2740 } 2741 } 2742 2743 if (rings_hung) 2744 return i915_handle_error(dev, true, "Ring hung"); 2745 2746 if (busy_count) 2747 /* Reset timer case chip hangs without another request 2748 * being added */ 2749 i915_queue_hangcheck(dev); 2750 } 2751 2752 void i915_queue_hangcheck(struct drm_device *dev) 2753 { 2754 struct drm_i915_private *dev_priv = dev->dev_private; 2755 if (!i915.enable_hangcheck) 2756 return; 2757 2758 mod_timer(&dev_priv->gpu_error.hangcheck_timer, 2759 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); 2760 } 2761 2762 static void ibx_irq_preinstall(struct drm_device *dev) 2763 { 2764 struct drm_i915_private *dev_priv = dev->dev_private; 2765 2766 if (HAS_PCH_NOP(dev)) 2767 return; 2768 2769 /* south display irq */ 2770 I915_WRITE(SDEIMR, 0xffffffff); 2771 /* 2772 * SDEIER is also touched by the interrupt handler to work around missed 2773 * PCH interrupts. Hence we can't update it after the interrupt handler 2774 * is enabled - instead we unconditionally enable all PCH interrupt 2775 * sources here, but then only unmask them as needed with SDEIMR. 2776 */ 2777 I915_WRITE(SDEIER, 0xffffffff); 2778 POSTING_READ(SDEIER); 2779 } 2780 2781 static void gen5_gt_irq_preinstall(struct drm_device *dev) 2782 { 2783 struct drm_i915_private *dev_priv = dev->dev_private; 2784 2785 /* and GT */ 2786 I915_WRITE(GTIMR, 0xffffffff); 2787 I915_WRITE(GTIER, 0x0); 2788 POSTING_READ(GTIER); 2789 2790 if (INTEL_INFO(dev)->gen >= 6) { 2791 /* and PM */ 2792 I915_WRITE(GEN6_PMIMR, 0xffffffff); 2793 I915_WRITE(GEN6_PMIER, 0x0); 2794 POSTING_READ(GEN6_PMIER); 2795 } 2796 } 2797 2798 /* drm_dma.h hooks 2799 */ 2800 static void ironlake_irq_preinstall(struct drm_device *dev) 2801 { 2802 struct drm_i915_private *dev_priv = dev->dev_private; 2803 2804 I915_WRITE(HWSTAM, 0xeffe); 2805 2806 I915_WRITE(DEIMR, 0xffffffff); 2807 I915_WRITE(DEIER, 0x0); 2808 POSTING_READ(DEIER); 2809 2810 gen5_gt_irq_preinstall(dev); 2811 2812 ibx_irq_preinstall(dev); 2813 } 2814 2815 static void valleyview_irq_preinstall(struct drm_device *dev) 2816 { 2817 struct drm_i915_private *dev_priv = dev->dev_private; 2818 int pipe; 2819 2820 /* VLV magic */ 2821 I915_WRITE(VLV_IMR, 0); 2822 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0); 2823 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0); 2824 I915_WRITE(RING_IMR(BLT_RING_BASE), 0); 2825 2826 /* and GT */ 2827 I915_WRITE(GTIIR, I915_READ(GTIIR)); 2828 I915_WRITE(GTIIR, I915_READ(GTIIR)); 2829 2830 gen5_gt_irq_preinstall(dev); 2831 2832 I915_WRITE(DPINVGTT, 0xff); 2833 2834 I915_WRITE(PORT_HOTPLUG_EN, 0); 2835 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 2836 for_each_pipe(pipe) 2837 I915_WRITE(PIPESTAT(pipe), 0xffff); 2838 I915_WRITE(VLV_IIR, 0xffffffff); 2839 I915_WRITE(VLV_IMR, 0xffffffff); 2840 I915_WRITE(VLV_IER, 0x0); 2841 POSTING_READ(VLV_IER); 2842 } 2843 2844 static void gen8_irq_preinstall(struct drm_device *dev) 2845 { 2846 struct drm_i915_private *dev_priv = dev->dev_private; 2847 int pipe; 2848 2849 I915_WRITE(GEN8_MASTER_IRQ, 0); 2850 POSTING_READ(GEN8_MASTER_IRQ); 2851 2852 /* IIR can theoretically queue up two events. Be paranoid */ 2853 #define GEN8_IRQ_INIT_NDX(type, which) do { \ 2854 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ 2855 POSTING_READ(GEN8_##type##_IMR(which)); \ 2856 I915_WRITE(GEN8_##type##_IER(which), 0); \ 2857 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ 2858 POSTING_READ(GEN8_##type##_IIR(which)); \ 2859 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ 2860 } while (0) 2861 2862 #define GEN8_IRQ_INIT(type) do { \ 2863 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \ 2864 POSTING_READ(GEN8_##type##_IMR); \ 2865 I915_WRITE(GEN8_##type##_IER, 0); \ 2866 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \ 2867 POSTING_READ(GEN8_##type##_IIR); \ 2868 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \ 2869 } while (0) 2870 2871 GEN8_IRQ_INIT_NDX(GT, 0); 2872 GEN8_IRQ_INIT_NDX(GT, 1); 2873 GEN8_IRQ_INIT_NDX(GT, 2); 2874 GEN8_IRQ_INIT_NDX(GT, 3); 2875 2876 for_each_pipe(pipe) { 2877 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe); 2878 } 2879 2880 GEN8_IRQ_INIT(DE_PORT); 2881 GEN8_IRQ_INIT(DE_MISC); 2882 GEN8_IRQ_INIT(PCU); 2883 #undef GEN8_IRQ_INIT 2884 #undef GEN8_IRQ_INIT_NDX 2885 2886 POSTING_READ(GEN8_PCU_IIR); 2887 2888 ibx_irq_preinstall(dev); 2889 } 2890 2891 static void ibx_hpd_irq_setup(struct drm_device *dev) 2892 { 2893 struct drm_i915_private *dev_priv = dev->dev_private; 2894 struct drm_mode_config *mode_config = &dev->mode_config; 2895 struct intel_encoder *intel_encoder; 2896 u32 hotplug_irqs, hotplug, enabled_irqs = 0; 2897 2898 if (HAS_PCH_IBX(dev)) { 2899 hotplug_irqs = SDE_HOTPLUG_MASK; 2900 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) 2901 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) 2902 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin]; 2903 } else { 2904 hotplug_irqs = SDE_HOTPLUG_MASK_CPT; 2905 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) 2906 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) 2907 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin]; 2908 } 2909 2910 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); 2911 2912 /* 2913 * Enable digital hotplug on the PCH, and configure the DP short pulse 2914 * duration to 2ms (which is the minimum in the Display Port spec) 2915 * 2916 * This register is the same on all known PCH chips. 2917 */ 2918 hotplug = I915_READ(PCH_PORT_HOTPLUG); 2919 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); 2920 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; 2921 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; 2922 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; 2923 I915_WRITE(PCH_PORT_HOTPLUG, hotplug); 2924 } 2925 2926 static void ibx_irq_postinstall(struct drm_device *dev) 2927 { 2928 struct drm_i915_private *dev_priv = dev->dev_private; 2929 u32 mask; 2930 2931 if (HAS_PCH_NOP(dev)) 2932 return; 2933 2934 if (HAS_PCH_IBX(dev)) { 2935 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON; 2936 } else { 2937 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT; 2938 2939 I915_WRITE(SERR_INT, I915_READ(SERR_INT)); 2940 } 2941 2942 I915_WRITE(SDEIIR, I915_READ(SDEIIR)); 2943 I915_WRITE(SDEIMR, ~mask); 2944 } 2945 2946 static void gen5_gt_irq_postinstall(struct drm_device *dev) 2947 { 2948 struct drm_i915_private *dev_priv = dev->dev_private; 2949 u32 pm_irqs, gt_irqs; 2950 2951 pm_irqs = gt_irqs = 0; 2952 2953 dev_priv->gt_irq_mask = ~0; 2954 if (HAS_L3_DPF(dev)) { 2955 /* L3 parity interrupt is always unmasked. */ 2956 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev); 2957 gt_irqs |= GT_PARITY_ERROR(dev); 2958 } 2959 2960 gt_irqs |= GT_RENDER_USER_INTERRUPT; 2961 if (IS_GEN5(dev)) { 2962 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT | 2963 ILK_BSD_USER_INTERRUPT; 2964 } else { 2965 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; 2966 } 2967 2968 I915_WRITE(GTIIR, I915_READ(GTIIR)); 2969 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); 2970 I915_WRITE(GTIER, gt_irqs); 2971 POSTING_READ(GTIER); 2972 2973 if (INTEL_INFO(dev)->gen >= 6) { 2974 pm_irqs |= dev_priv->pm_rps_events; 2975 2976 if (HAS_VEBOX(dev)) 2977 pm_irqs |= PM_VEBOX_USER_INTERRUPT; 2978 2979 dev_priv->pm_irq_mask = 0xffffffff; 2980 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); 2981 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask); 2982 I915_WRITE(GEN6_PMIER, pm_irqs); 2983 POSTING_READ(GEN6_PMIER); 2984 } 2985 } 2986 2987 static int ironlake_irq_postinstall(struct drm_device *dev) 2988 { 2989 unsigned long irqflags; 2990 struct drm_i915_private *dev_priv = dev->dev_private; 2991 u32 display_mask, extra_mask; 2992 2993 if (INTEL_INFO(dev)->gen >= 7) { 2994 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | 2995 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB | 2996 DE_PLANEB_FLIP_DONE_IVB | 2997 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB); 2998 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | 2999 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB); 3000 3001 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT)); 3002 } else { 3003 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | 3004 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | 3005 DE_AUX_CHANNEL_A | 3006 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE | 3007 DE_POISON); 3008 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT | 3009 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN; 3010 } 3011 3012 dev_priv->irq_mask = ~display_mask; 3013 3014 /* should always can generate irq */ 3015 I915_WRITE(DEIIR, I915_READ(DEIIR)); 3016 I915_WRITE(DEIMR, dev_priv->irq_mask); 3017 I915_WRITE(DEIER, display_mask | extra_mask); 3018 POSTING_READ(DEIER); 3019 3020 gen5_gt_irq_postinstall(dev); 3021 3022 ibx_irq_postinstall(dev); 3023 3024 if (IS_IRONLAKE_M(dev)) { 3025 /* Enable PCU event interrupts 3026 * 3027 * spinlocking not required here for correctness since interrupt 3028 * setup is guaranteed to run in single-threaded context. But we 3029 * need it to make the assert_spin_locked happy. */ 3030 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 3031 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); 3032 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 3033 } 3034 3035 return 0; 3036 } 3037 3038 static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv) 3039 { 3040 u32 pipestat_mask; 3041 u32 iir_mask; 3042 3043 pipestat_mask = PIPESTAT_INT_STATUS_MASK | 3044 PIPE_FIFO_UNDERRUN_STATUS; 3045 3046 I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask); 3047 I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask); 3048 POSTING_READ(PIPESTAT(PIPE_A)); 3049 3050 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | 3051 PIPE_CRC_DONE_INTERRUPT_STATUS; 3052 3053 i915_enable_pipestat(dev_priv, PIPE_A, pipestat_mask | 3054 PIPE_GMBUS_INTERRUPT_STATUS); 3055 i915_enable_pipestat(dev_priv, PIPE_B, pipestat_mask); 3056 3057 iir_mask = I915_DISPLAY_PORT_INTERRUPT | 3058 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 3059 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; 3060 dev_priv->irq_mask &= ~iir_mask; 3061 3062 I915_WRITE(VLV_IIR, iir_mask); 3063 I915_WRITE(VLV_IIR, iir_mask); 3064 I915_WRITE(VLV_IMR, dev_priv->irq_mask); 3065 I915_WRITE(VLV_IER, ~dev_priv->irq_mask); 3066 POSTING_READ(VLV_IER); 3067 } 3068 3069 static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv) 3070 { 3071 u32 pipestat_mask; 3072 u32 iir_mask; 3073 3074 iir_mask = I915_DISPLAY_PORT_INTERRUPT | 3075 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 3076 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; 3077 3078 dev_priv->irq_mask |= iir_mask; 3079 I915_WRITE(VLV_IER, ~dev_priv->irq_mask); 3080 I915_WRITE(VLV_IMR, dev_priv->irq_mask); 3081 I915_WRITE(VLV_IIR, iir_mask); 3082 I915_WRITE(VLV_IIR, iir_mask); 3083 POSTING_READ(VLV_IIR); 3084 3085 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | 3086 PIPE_CRC_DONE_INTERRUPT_STATUS; 3087 3088 i915_disable_pipestat(dev_priv, PIPE_A, pipestat_mask | 3089 PIPE_GMBUS_INTERRUPT_STATUS); 3090 i915_disable_pipestat(dev_priv, PIPE_B, pipestat_mask); 3091 3092 pipestat_mask = PIPESTAT_INT_STATUS_MASK | 3093 PIPE_FIFO_UNDERRUN_STATUS; 3094 I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask); 3095 I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask); 3096 POSTING_READ(PIPESTAT(PIPE_A)); 3097 } 3098 3099 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) 3100 { 3101 assert_spin_locked(&dev_priv->irq_lock); 3102 3103 if (dev_priv->display_irqs_enabled) 3104 return; 3105 3106 dev_priv->display_irqs_enabled = true; 3107 3108 if (dev_priv->dev->irq_enabled) 3109 valleyview_display_irqs_install(dev_priv); 3110 } 3111 3112 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) 3113 { 3114 assert_spin_locked(&dev_priv->irq_lock); 3115 3116 if (!dev_priv->display_irqs_enabled) 3117 return; 3118 3119 dev_priv->display_irqs_enabled = false; 3120 3121 if (dev_priv->dev->irq_enabled) 3122 valleyview_display_irqs_uninstall(dev_priv); 3123 } 3124 3125 static int valleyview_irq_postinstall(struct drm_device *dev) 3126 { 3127 struct drm_i915_private *dev_priv = dev->dev_private; 3128 unsigned long irqflags; 3129 3130 dev_priv->irq_mask = ~0; 3131 3132 I915_WRITE(PORT_HOTPLUG_EN, 0); 3133 POSTING_READ(PORT_HOTPLUG_EN); 3134 3135 I915_WRITE(VLV_IMR, dev_priv->irq_mask); 3136 I915_WRITE(VLV_IER, ~dev_priv->irq_mask); 3137 I915_WRITE(VLV_IIR, 0xffffffff); 3138 POSTING_READ(VLV_IER); 3139 3140 /* Interrupt setup is already guaranteed to be single-threaded, this is 3141 * just to make the assert_spin_locked check happy. */ 3142 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 3143 if (dev_priv->display_irqs_enabled) 3144 valleyview_display_irqs_install(dev_priv); 3145 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 3146 3147 I915_WRITE(VLV_IIR, 0xffffffff); 3148 I915_WRITE(VLV_IIR, 0xffffffff); 3149 3150 gen5_gt_irq_postinstall(dev); 3151 3152 /* ack & enable invalid PTE error interrupts */ 3153 #if 0 /* FIXME: add support to irq handler for checking these bits */ 3154 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); 3155 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK); 3156 #endif 3157 3158 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); 3159 3160 return 0; 3161 } 3162 3163 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) 3164 { 3165 int i; 3166 3167 /* These are interrupts we'll toggle with the ring mask register */ 3168 uint32_t gt_interrupts[] = { 3169 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | 3170 GT_RENDER_L3_PARITY_ERROR_INTERRUPT | 3171 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT, 3172 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | 3173 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT, 3174 0, 3175 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT 3176 }; 3177 3178 for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++) { 3179 u32 tmp = I915_READ(GEN8_GT_IIR(i)); 3180 if (tmp) 3181 DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n", 3182 i, tmp); 3183 I915_WRITE(GEN8_GT_IMR(i), ~gt_interrupts[i]); 3184 I915_WRITE(GEN8_GT_IER(i), gt_interrupts[i]); 3185 } 3186 POSTING_READ(GEN8_GT_IER(0)); 3187 } 3188 3189 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) 3190 { 3191 struct drm_device *dev = dev_priv->dev; 3192 uint32_t de_pipe_masked = GEN8_PIPE_FLIP_DONE | 3193 GEN8_PIPE_CDCLK_CRC_DONE | 3194 GEN8_DE_PIPE_IRQ_FAULT_ERRORS; 3195 uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | 3196 GEN8_PIPE_FIFO_UNDERRUN; 3197 int pipe; 3198 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked; 3199 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; 3200 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; 3201 3202 for_each_pipe(pipe) { 3203 u32 tmp = I915_READ(GEN8_DE_PIPE_IIR(pipe)); 3204 if (tmp) 3205 DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n", 3206 pipe, tmp); 3207 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); 3208 I915_WRITE(GEN8_DE_PIPE_IER(pipe), de_pipe_enables); 3209 } 3210 POSTING_READ(GEN8_DE_PIPE_ISR(0)); 3211 3212 I915_WRITE(GEN8_DE_PORT_IMR, ~GEN8_AUX_CHANNEL_A); 3213 I915_WRITE(GEN8_DE_PORT_IER, GEN8_AUX_CHANNEL_A); 3214 POSTING_READ(GEN8_DE_PORT_IER); 3215 } 3216 3217 static int gen8_irq_postinstall(struct drm_device *dev) 3218 { 3219 struct drm_i915_private *dev_priv = dev->dev_private; 3220 3221 gen8_gt_irq_postinstall(dev_priv); 3222 gen8_de_irq_postinstall(dev_priv); 3223 3224 ibx_irq_postinstall(dev); 3225 3226 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); 3227 POSTING_READ(GEN8_MASTER_IRQ); 3228 3229 return 0; 3230 } 3231 3232 static void gen8_irq_uninstall(struct drm_device *dev) 3233 { 3234 struct drm_i915_private *dev_priv = dev->dev_private; 3235 int pipe; 3236 3237 if (!dev_priv) 3238 return; 3239 3240 I915_WRITE(GEN8_MASTER_IRQ, 0); 3241 3242 #define GEN8_IRQ_FINI_NDX(type, which) do { \ 3243 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ 3244 I915_WRITE(GEN8_##type##_IER(which), 0); \ 3245 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ 3246 } while (0) 3247 3248 #define GEN8_IRQ_FINI(type) do { \ 3249 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \ 3250 I915_WRITE(GEN8_##type##_IER, 0); \ 3251 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \ 3252 } while (0) 3253 3254 GEN8_IRQ_FINI_NDX(GT, 0); 3255 GEN8_IRQ_FINI_NDX(GT, 1); 3256 GEN8_IRQ_FINI_NDX(GT, 2); 3257 GEN8_IRQ_FINI_NDX(GT, 3); 3258 3259 for_each_pipe(pipe) { 3260 GEN8_IRQ_FINI_NDX(DE_PIPE, pipe); 3261 } 3262 3263 GEN8_IRQ_FINI(DE_PORT); 3264 GEN8_IRQ_FINI(DE_MISC); 3265 GEN8_IRQ_FINI(PCU); 3266 #undef GEN8_IRQ_FINI 3267 #undef GEN8_IRQ_FINI_NDX 3268 3269 POSTING_READ(GEN8_PCU_IIR); 3270 } 3271 3272 static void valleyview_irq_uninstall(struct drm_device *dev) 3273 { 3274 struct drm_i915_private *dev_priv = dev->dev_private; 3275 unsigned long irqflags; 3276 int pipe; 3277 3278 if (!dev_priv) 3279 return; 3280 3281 intel_hpd_irq_uninstall(dev_priv); 3282 3283 for_each_pipe(pipe) 3284 I915_WRITE(PIPESTAT(pipe), 0xffff); 3285 3286 I915_WRITE(HWSTAM, 0xffffffff); 3287 I915_WRITE(PORT_HOTPLUG_EN, 0); 3288 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 3289 3290 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 3291 if (dev_priv->display_irqs_enabled) 3292 valleyview_display_irqs_uninstall(dev_priv); 3293 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 3294 3295 dev_priv->irq_mask = 0; 3296 3297 I915_WRITE(VLV_IIR, 0xffffffff); 3298 I915_WRITE(VLV_IMR, 0xffffffff); 3299 I915_WRITE(VLV_IER, 0x0); 3300 POSTING_READ(VLV_IER); 3301 } 3302 3303 static void ironlake_irq_uninstall(struct drm_device *dev) 3304 { 3305 struct drm_i915_private *dev_priv = dev->dev_private; 3306 3307 if (!dev_priv) 3308 return; 3309 3310 intel_hpd_irq_uninstall(dev_priv); 3311 3312 I915_WRITE(HWSTAM, 0xffffffff); 3313 3314 I915_WRITE(DEIMR, 0xffffffff); 3315 I915_WRITE(DEIER, 0x0); 3316 I915_WRITE(DEIIR, I915_READ(DEIIR)); 3317 if (IS_GEN7(dev)) 3318 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT)); 3319 3320 I915_WRITE(GTIMR, 0xffffffff); 3321 I915_WRITE(GTIER, 0x0); 3322 I915_WRITE(GTIIR, I915_READ(GTIIR)); 3323 3324 if (HAS_PCH_NOP(dev)) 3325 return; 3326 3327 I915_WRITE(SDEIMR, 0xffffffff); 3328 I915_WRITE(SDEIER, 0x0); 3329 I915_WRITE(SDEIIR, I915_READ(SDEIIR)); 3330 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev)) 3331 I915_WRITE(SERR_INT, I915_READ(SERR_INT)); 3332 } 3333 3334 static void i8xx_irq_preinstall(struct drm_device * dev) 3335 { 3336 struct drm_i915_private *dev_priv = dev->dev_private; 3337 int pipe; 3338 3339 for_each_pipe(pipe) 3340 I915_WRITE(PIPESTAT(pipe), 0); 3341 I915_WRITE16(IMR, 0xffff); 3342 I915_WRITE16(IER, 0x0); 3343 POSTING_READ16(IER); 3344 } 3345 3346 static int i8xx_irq_postinstall(struct drm_device *dev) 3347 { 3348 struct drm_i915_private *dev_priv = dev->dev_private; 3349 unsigned long irqflags; 3350 3351 I915_WRITE16(EMR, 3352 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); 3353 3354 /* Unmask the interrupts that we always want on. */ 3355 dev_priv->irq_mask = 3356 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 3357 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 3358 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 3359 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | 3360 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); 3361 I915_WRITE16(IMR, dev_priv->irq_mask); 3362 3363 I915_WRITE16(IER, 3364 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 3365 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 3366 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | 3367 I915_USER_INTERRUPT); 3368 POSTING_READ16(IER); 3369 3370 /* Interrupt setup is already guaranteed to be single-threaded, this is 3371 * just to make the assert_spin_locked check happy. */ 3372 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 3373 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); 3374 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); 3375 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 3376 3377 return 0; 3378 } 3379 3380 /* 3381 * Returns true when a page flip has completed. 3382 */ 3383 static bool i8xx_handle_vblank(struct drm_device *dev, 3384 int plane, int pipe, u32 iir) 3385 { 3386 struct drm_i915_private *dev_priv = dev->dev_private; 3387 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); 3388 3389 if (!drm_handle_vblank(dev, pipe)) 3390 return false; 3391 3392 if ((iir & flip_pending) == 0) 3393 return false; 3394 3395 intel_prepare_page_flip(dev, plane); 3396 3397 /* We detect FlipDone by looking for the change in PendingFlip from '1' 3398 * to '0' on the following vblank, i.e. IIR has the Pendingflip 3399 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence 3400 * the flip is completed (no longer pending). Since this doesn't raise 3401 * an interrupt per se, we watch for the change at vblank. 3402 */ 3403 if (I915_READ16(ISR) & flip_pending) 3404 return false; 3405 3406 intel_finish_page_flip(dev, pipe); 3407 3408 return true; 3409 } 3410 3411 static irqreturn_t i8xx_irq_handler(int irq, void *arg) 3412 { 3413 struct drm_device *dev = (struct drm_device *) arg; 3414 struct drm_i915_private *dev_priv = dev->dev_private; 3415 u16 iir, new_iir; 3416 u32 pipe_stats[2]; 3417 unsigned long irqflags; 3418 int pipe; 3419 u16 flip_mask = 3420 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 3421 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; 3422 3423 iir = I915_READ16(IIR); 3424 if (iir == 0) 3425 return IRQ_NONE; 3426 3427 while (iir & ~flip_mask) { 3428 /* Can't rely on pipestat interrupt bit in iir as it might 3429 * have been cleared after the pipestat interrupt was received. 3430 * It doesn't set the bit in iir again, but it still produces 3431 * interrupts (for non-MSI). 3432 */ 3433 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 3434 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) 3435 i915_handle_error(dev, false, 3436 "Command parser error, iir 0x%08x", 3437 iir); 3438 3439 for_each_pipe(pipe) { 3440 int reg = PIPESTAT(pipe); 3441 pipe_stats[pipe] = I915_READ(reg); 3442 3443 /* 3444 * Clear the PIPE*STAT regs before the IIR 3445 */ 3446 if (pipe_stats[pipe] & 0x8000ffff) 3447 I915_WRITE(reg, pipe_stats[pipe]); 3448 } 3449 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 3450 3451 I915_WRITE16(IIR, iir & ~flip_mask); 3452 new_iir = I915_READ16(IIR); /* Flush posted writes */ 3453 3454 i915_update_dri1_breadcrumb(dev); 3455 3456 if (iir & I915_USER_INTERRUPT) 3457 notify_ring(dev, &dev_priv->ring[RCS]); 3458 3459 for_each_pipe(pipe) { 3460 int plane = pipe; 3461 if (HAS_FBC(dev)) 3462 plane = !plane; 3463 3464 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && 3465 i8xx_handle_vblank(dev, plane, pipe, iir)) 3466 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); 3467 3468 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 3469 i9xx_pipe_crc_irq_handler(dev, pipe); 3470 3471 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && 3472 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) 3473 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); 3474 } 3475 3476 iir = new_iir; 3477 } 3478 3479 return IRQ_HANDLED; 3480 } 3481 3482 static void i8xx_irq_uninstall(struct drm_device * dev) 3483 { 3484 struct drm_i915_private *dev_priv = dev->dev_private; 3485 int pipe; 3486 3487 for_each_pipe(pipe) { 3488 /* Clear enable bits; then clear status bits */ 3489 I915_WRITE(PIPESTAT(pipe), 0); 3490 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); 3491 } 3492 I915_WRITE16(IMR, 0xffff); 3493 I915_WRITE16(IER, 0x0); 3494 I915_WRITE16(IIR, I915_READ16(IIR)); 3495 } 3496 3497 static void i915_irq_preinstall(struct drm_device * dev) 3498 { 3499 struct drm_i915_private *dev_priv = dev->dev_private; 3500 int pipe; 3501 3502 if (I915_HAS_HOTPLUG(dev)) { 3503 I915_WRITE(PORT_HOTPLUG_EN, 0); 3504 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 3505 } 3506 3507 I915_WRITE16(HWSTAM, 0xeffe); 3508 for_each_pipe(pipe) 3509 I915_WRITE(PIPESTAT(pipe), 0); 3510 I915_WRITE(IMR, 0xffffffff); 3511 I915_WRITE(IER, 0x0); 3512 POSTING_READ(IER); 3513 } 3514 3515 static int i915_irq_postinstall(struct drm_device *dev) 3516 { 3517 struct drm_i915_private *dev_priv = dev->dev_private; 3518 u32 enable_mask; 3519 unsigned long irqflags; 3520 3521 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); 3522 3523 /* Unmask the interrupts that we always want on. */ 3524 dev_priv->irq_mask = 3525 ~(I915_ASLE_INTERRUPT | 3526 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 3527 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 3528 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 3529 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | 3530 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); 3531 3532 enable_mask = 3533 I915_ASLE_INTERRUPT | 3534 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 3535 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 3536 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | 3537 I915_USER_INTERRUPT; 3538 3539 if (I915_HAS_HOTPLUG(dev)) { 3540 I915_WRITE(PORT_HOTPLUG_EN, 0); 3541 POSTING_READ(PORT_HOTPLUG_EN); 3542 3543 /* Enable in IER... */ 3544 enable_mask |= I915_DISPLAY_PORT_INTERRUPT; 3545 /* and unmask in IMR */ 3546 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; 3547 } 3548 3549 I915_WRITE(IMR, dev_priv->irq_mask); 3550 I915_WRITE(IER, enable_mask); 3551 POSTING_READ(IER); 3552 3553 i915_enable_asle_pipestat(dev); 3554 3555 /* Interrupt setup is already guaranteed to be single-threaded, this is 3556 * just to make the assert_spin_locked check happy. */ 3557 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 3558 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); 3559 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); 3560 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 3561 3562 return 0; 3563 } 3564 3565 /* 3566 * Returns true when a page flip has completed. 3567 */ 3568 static bool i915_handle_vblank(struct drm_device *dev, 3569 int plane, int pipe, u32 iir) 3570 { 3571 struct drm_i915_private *dev_priv = dev->dev_private; 3572 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); 3573 3574 if (!drm_handle_vblank(dev, pipe)) 3575 return false; 3576 3577 if ((iir & flip_pending) == 0) 3578 return false; 3579 3580 intel_prepare_page_flip(dev, plane); 3581 3582 /* We detect FlipDone by looking for the change in PendingFlip from '1' 3583 * to '0' on the following vblank, i.e. IIR has the Pendingflip 3584 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence 3585 * the flip is completed (no longer pending). Since this doesn't raise 3586 * an interrupt per se, we watch for the change at vblank. 3587 */ 3588 if (I915_READ(ISR) & flip_pending) 3589 return false; 3590 3591 intel_finish_page_flip(dev, pipe); 3592 3593 return true; 3594 } 3595 3596 static irqreturn_t i915_irq_handler(int irq, void *arg) 3597 { 3598 struct drm_device *dev = (struct drm_device *) arg; 3599 struct drm_i915_private *dev_priv = dev->dev_private; 3600 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; 3601 unsigned long irqflags; 3602 u32 flip_mask = 3603 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 3604 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; 3605 int pipe, ret = IRQ_NONE; 3606 3607 iir = I915_READ(IIR); 3608 do { 3609 bool irq_received = (iir & ~flip_mask) != 0; 3610 bool blc_event = false; 3611 3612 /* Can't rely on pipestat interrupt bit in iir as it might 3613 * have been cleared after the pipestat interrupt was received. 3614 * It doesn't set the bit in iir again, but it still produces 3615 * interrupts (for non-MSI). 3616 */ 3617 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 3618 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) 3619 i915_handle_error(dev, false, 3620 "Command parser error, iir 0x%08x", 3621 iir); 3622 3623 for_each_pipe(pipe) { 3624 int reg = PIPESTAT(pipe); 3625 pipe_stats[pipe] = I915_READ(reg); 3626 3627 /* Clear the PIPE*STAT regs before the IIR */ 3628 if (pipe_stats[pipe] & 0x8000ffff) { 3629 I915_WRITE(reg, pipe_stats[pipe]); 3630 irq_received = true; 3631 } 3632 } 3633 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 3634 3635 if (!irq_received) 3636 break; 3637 3638 /* Consume port. Then clear IIR or we'll miss events */ 3639 if ((I915_HAS_HOTPLUG(dev)) && 3640 (iir & I915_DISPLAY_PORT_INTERRUPT)) { 3641 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); 3642 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; 3643 3644 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915); 3645 3646 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); 3647 POSTING_READ(PORT_HOTPLUG_STAT); 3648 } 3649 3650 I915_WRITE(IIR, iir & ~flip_mask); 3651 new_iir = I915_READ(IIR); /* Flush posted writes */ 3652 3653 if (iir & I915_USER_INTERRUPT) 3654 notify_ring(dev, &dev_priv->ring[RCS]); 3655 3656 for_each_pipe(pipe) { 3657 int plane = pipe; 3658 if (HAS_FBC(dev)) 3659 plane = !plane; 3660 3661 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && 3662 i915_handle_vblank(dev, plane, pipe, iir)) 3663 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); 3664 3665 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) 3666 blc_event = true; 3667 3668 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 3669 i9xx_pipe_crc_irq_handler(dev, pipe); 3670 3671 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && 3672 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) 3673 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); 3674 } 3675 3676 if (blc_event || (iir & I915_ASLE_INTERRUPT)) 3677 intel_opregion_asle_intr(dev); 3678 3679 /* With MSI, interrupts are only generated when iir 3680 * transitions from zero to nonzero. If another bit got 3681 * set while we were handling the existing iir bits, then 3682 * we would never get another interrupt. 3683 * 3684 * This is fine on non-MSI as well, as if we hit this path 3685 * we avoid exiting the interrupt handler only to generate 3686 * another one. 3687 * 3688 * Note that for MSI this could cause a stray interrupt report 3689 * if an interrupt landed in the time between writing IIR and 3690 * the posting read. This should be rare enough to never 3691 * trigger the 99% of 100,000 interrupts test for disabling 3692 * stray interrupts. 3693 */ 3694 ret = IRQ_HANDLED; 3695 iir = new_iir; 3696 } while (iir & ~flip_mask); 3697 3698 i915_update_dri1_breadcrumb(dev); 3699 3700 return ret; 3701 } 3702 3703 static void i915_irq_uninstall(struct drm_device * dev) 3704 { 3705 struct drm_i915_private *dev_priv = dev->dev_private; 3706 int pipe; 3707 3708 intel_hpd_irq_uninstall(dev_priv); 3709 3710 if (I915_HAS_HOTPLUG(dev)) { 3711 I915_WRITE(PORT_HOTPLUG_EN, 0); 3712 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 3713 } 3714 3715 I915_WRITE16(HWSTAM, 0xffff); 3716 for_each_pipe(pipe) { 3717 /* Clear enable bits; then clear status bits */ 3718 I915_WRITE(PIPESTAT(pipe), 0); 3719 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); 3720 } 3721 I915_WRITE(IMR, 0xffffffff); 3722 I915_WRITE(IER, 0x0); 3723 3724 I915_WRITE(IIR, I915_READ(IIR)); 3725 } 3726 3727 static void i965_irq_preinstall(struct drm_device * dev) 3728 { 3729 struct drm_i915_private *dev_priv = dev->dev_private; 3730 int pipe; 3731 3732 I915_WRITE(PORT_HOTPLUG_EN, 0); 3733 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 3734 3735 I915_WRITE(HWSTAM, 0xeffe); 3736 for_each_pipe(pipe) 3737 I915_WRITE(PIPESTAT(pipe), 0); 3738 I915_WRITE(IMR, 0xffffffff); 3739 I915_WRITE(IER, 0x0); 3740 POSTING_READ(IER); 3741 } 3742 3743 static int i965_irq_postinstall(struct drm_device *dev) 3744 { 3745 struct drm_i915_private *dev_priv = dev->dev_private; 3746 u32 enable_mask; 3747 u32 error_mask; 3748 unsigned long irqflags; 3749 3750 /* Unmask the interrupts that we always want on. */ 3751 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | 3752 I915_DISPLAY_PORT_INTERRUPT | 3753 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 3754 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 3755 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 3756 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | 3757 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); 3758 3759 enable_mask = ~dev_priv->irq_mask; 3760 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 3761 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); 3762 enable_mask |= I915_USER_INTERRUPT; 3763 3764 if (IS_G4X(dev)) 3765 enable_mask |= I915_BSD_USER_INTERRUPT; 3766 3767 /* Interrupt setup is already guaranteed to be single-threaded, this is 3768 * just to make the assert_spin_locked check happy. */ 3769 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 3770 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); 3771 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); 3772 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); 3773 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 3774 3775 /* 3776 * Enable some error detection, note the instruction error mask 3777 * bit is reserved, so we leave it masked. 3778 */ 3779 if (IS_G4X(dev)) { 3780 error_mask = ~(GM45_ERROR_PAGE_TABLE | 3781 GM45_ERROR_MEM_PRIV | 3782 GM45_ERROR_CP_PRIV | 3783 I915_ERROR_MEMORY_REFRESH); 3784 } else { 3785 error_mask = ~(I915_ERROR_PAGE_TABLE | 3786 I915_ERROR_MEMORY_REFRESH); 3787 } 3788 I915_WRITE(EMR, error_mask); 3789 3790 I915_WRITE(IMR, dev_priv->irq_mask); 3791 I915_WRITE(IER, enable_mask); 3792 POSTING_READ(IER); 3793 3794 I915_WRITE(PORT_HOTPLUG_EN, 0); 3795 POSTING_READ(PORT_HOTPLUG_EN); 3796 3797 i915_enable_asle_pipestat(dev); 3798 3799 return 0; 3800 } 3801 3802 static void i915_hpd_irq_setup(struct drm_device *dev) 3803 { 3804 struct drm_i915_private *dev_priv = dev->dev_private; 3805 struct drm_mode_config *mode_config = &dev->mode_config; 3806 struct intel_encoder *intel_encoder; 3807 u32 hotplug_en; 3808 3809 assert_spin_locked(&dev_priv->irq_lock); 3810 3811 if (I915_HAS_HOTPLUG(dev)) { 3812 hotplug_en = I915_READ(PORT_HOTPLUG_EN); 3813 hotplug_en &= ~HOTPLUG_INT_EN_MASK; 3814 /* Note HDMI and DP share hotplug bits */ 3815 /* enable bits are the same for all generations */ 3816 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) 3817 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) 3818 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin]; 3819 /* Programming the CRT detection parameters tends 3820 to generate a spurious hotplug event about three 3821 seconds later. So just do it once. 3822 */ 3823 if (IS_G4X(dev)) 3824 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; 3825 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK; 3826 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; 3827 3828 /* Ignore TV since it's buggy */ 3829 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); 3830 } 3831 } 3832 3833 static irqreturn_t i965_irq_handler(int irq, void *arg) 3834 { 3835 struct drm_device *dev = (struct drm_device *) arg; 3836 struct drm_i915_private *dev_priv = dev->dev_private; 3837 u32 iir, new_iir; 3838 u32 pipe_stats[I915_MAX_PIPES]; 3839 unsigned long irqflags; 3840 int ret = IRQ_NONE, pipe; 3841 u32 flip_mask = 3842 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 3843 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; 3844 3845 iir = I915_READ(IIR); 3846 3847 for (;;) { 3848 bool irq_received = (iir & ~flip_mask) != 0; 3849 bool blc_event = false; 3850 3851 /* Can't rely on pipestat interrupt bit in iir as it might 3852 * have been cleared after the pipestat interrupt was received. 3853 * It doesn't set the bit in iir again, but it still produces 3854 * interrupts (for non-MSI). 3855 */ 3856 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 3857 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) 3858 i915_handle_error(dev, false, 3859 "Command parser error, iir 0x%08x", 3860 iir); 3861 3862 for_each_pipe(pipe) { 3863 int reg = PIPESTAT(pipe); 3864 pipe_stats[pipe] = I915_READ(reg); 3865 3866 /* 3867 * Clear the PIPE*STAT regs before the IIR 3868 */ 3869 if (pipe_stats[pipe] & 0x8000ffff) { 3870 I915_WRITE(reg, pipe_stats[pipe]); 3871 irq_received = true; 3872 } 3873 } 3874 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 3875 3876 if (!irq_received) 3877 break; 3878 3879 ret = IRQ_HANDLED; 3880 3881 /* Consume port. Then clear IIR or we'll miss events */ 3882 if (iir & I915_DISPLAY_PORT_INTERRUPT) { 3883 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); 3884 u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ? 3885 HOTPLUG_INT_STATUS_G4X : 3886 HOTPLUG_INT_STATUS_I915); 3887 3888 intel_hpd_irq_handler(dev, hotplug_trigger, 3889 IS_G4X(dev) ? hpd_status_g4x : hpd_status_i915); 3890 3891 if (IS_G4X(dev) && 3892 (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)) 3893 dp_aux_irq_handler(dev); 3894 3895 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); 3896 I915_READ(PORT_HOTPLUG_STAT); 3897 } 3898 3899 I915_WRITE(IIR, iir & ~flip_mask); 3900 new_iir = I915_READ(IIR); /* Flush posted writes */ 3901 3902 if (iir & I915_USER_INTERRUPT) 3903 notify_ring(dev, &dev_priv->ring[RCS]); 3904 if (iir & I915_BSD_USER_INTERRUPT) 3905 notify_ring(dev, &dev_priv->ring[VCS]); 3906 3907 for_each_pipe(pipe) { 3908 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && 3909 i915_handle_vblank(dev, pipe, pipe, iir)) 3910 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); 3911 3912 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) 3913 blc_event = true; 3914 3915 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 3916 i9xx_pipe_crc_irq_handler(dev, pipe); 3917 3918 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && 3919 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) 3920 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); 3921 } 3922 3923 if (blc_event || (iir & I915_ASLE_INTERRUPT)) 3924 intel_opregion_asle_intr(dev); 3925 3926 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) 3927 gmbus_irq_handler(dev); 3928 3929 /* With MSI, interrupts are only generated when iir 3930 * transitions from zero to nonzero. If another bit got 3931 * set while we were handling the existing iir bits, then 3932 * we would never get another interrupt. 3933 * 3934 * This is fine on non-MSI as well, as if we hit this path 3935 * we avoid exiting the interrupt handler only to generate 3936 * another one. 3937 * 3938 * Note that for MSI this could cause a stray interrupt report 3939 * if an interrupt landed in the time between writing IIR and 3940 * the posting read. This should be rare enough to never 3941 * trigger the 99% of 100,000 interrupts test for disabling 3942 * stray interrupts. 3943 */ 3944 iir = new_iir; 3945 } 3946 3947 i915_update_dri1_breadcrumb(dev); 3948 3949 return ret; 3950 } 3951 3952 static void i965_irq_uninstall(struct drm_device * dev) 3953 { 3954 struct drm_i915_private *dev_priv = dev->dev_private; 3955 int pipe; 3956 3957 if (!dev_priv) 3958 return; 3959 3960 intel_hpd_irq_uninstall(dev_priv); 3961 3962 I915_WRITE(PORT_HOTPLUG_EN, 0); 3963 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 3964 3965 I915_WRITE(HWSTAM, 0xffffffff); 3966 for_each_pipe(pipe) 3967 I915_WRITE(PIPESTAT(pipe), 0); 3968 I915_WRITE(IMR, 0xffffffff); 3969 I915_WRITE(IER, 0x0); 3970 3971 for_each_pipe(pipe) 3972 I915_WRITE(PIPESTAT(pipe), 3973 I915_READ(PIPESTAT(pipe)) & 0x8000ffff); 3974 I915_WRITE(IIR, I915_READ(IIR)); 3975 } 3976 3977 static void intel_hpd_irq_reenable(unsigned long data) 3978 { 3979 struct drm_i915_private *dev_priv = (struct drm_i915_private *)data; 3980 struct drm_device *dev = dev_priv->dev; 3981 struct drm_mode_config *mode_config = &dev->mode_config; 3982 unsigned long irqflags; 3983 int i; 3984 3985 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 3986 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) { 3987 struct drm_connector *connector; 3988 3989 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED) 3990 continue; 3991 3992 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; 3993 3994 list_for_each_entry(connector, &mode_config->connector_list, head) { 3995 struct intel_connector *intel_connector = to_intel_connector(connector); 3996 3997 if (intel_connector->encoder->hpd_pin == i) { 3998 if (connector->polled != intel_connector->polled) 3999 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n", 4000 drm_get_connector_name(connector)); 4001 connector->polled = intel_connector->polled; 4002 if (!connector->polled) 4003 connector->polled = DRM_CONNECTOR_POLL_HPD; 4004 } 4005 } 4006 } 4007 if (dev_priv->display.hpd_irq_setup) 4008 dev_priv->display.hpd_irq_setup(dev); 4009 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 4010 } 4011 4012 void intel_irq_init(struct drm_device *dev) 4013 { 4014 struct drm_i915_private *dev_priv = dev->dev_private; 4015 4016 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); 4017 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func); 4018 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); 4019 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); 4020 4021 /* Let's track the enabled rps events */ 4022 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; 4023 4024 setup_timer(&dev_priv->gpu_error.hangcheck_timer, 4025 i915_hangcheck_elapsed, 4026 (unsigned long) dev); 4027 setup_timer(&dev_priv->hotplug_reenable_timer, intel_hpd_irq_reenable, 4028 (unsigned long) dev_priv); 4029 4030 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); 4031 4032 if (IS_GEN2(dev)) { 4033 dev->max_vblank_count = 0; 4034 dev->driver->get_vblank_counter = i8xx_get_vblank_counter; 4035 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { 4036 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ 4037 dev->driver->get_vblank_counter = gm45_get_vblank_counter; 4038 } else { 4039 dev->driver->get_vblank_counter = i915_get_vblank_counter; 4040 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ 4041 } 4042 4043 if (drm_core_check_feature(dev, DRIVER_MODESET)) { 4044 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; 4045 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; 4046 } 4047 4048 if (IS_VALLEYVIEW(dev)) { 4049 dev->driver->irq_handler = valleyview_irq_handler; 4050 dev->driver->irq_preinstall = valleyview_irq_preinstall; 4051 dev->driver->irq_postinstall = valleyview_irq_postinstall; 4052 dev->driver->irq_uninstall = valleyview_irq_uninstall; 4053 dev->driver->enable_vblank = valleyview_enable_vblank; 4054 dev->driver->disable_vblank = valleyview_disable_vblank; 4055 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; 4056 } else if (IS_GEN8(dev)) { 4057 dev->driver->irq_handler = gen8_irq_handler; 4058 dev->driver->irq_preinstall = gen8_irq_preinstall; 4059 dev->driver->irq_postinstall = gen8_irq_postinstall; 4060 dev->driver->irq_uninstall = gen8_irq_uninstall; 4061 dev->driver->enable_vblank = gen8_enable_vblank; 4062 dev->driver->disable_vblank = gen8_disable_vblank; 4063 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; 4064 } else if (HAS_PCH_SPLIT(dev)) { 4065 dev->driver->irq_handler = ironlake_irq_handler; 4066 dev->driver->irq_preinstall = ironlake_irq_preinstall; 4067 dev->driver->irq_postinstall = ironlake_irq_postinstall; 4068 dev->driver->irq_uninstall = ironlake_irq_uninstall; 4069 dev->driver->enable_vblank = ironlake_enable_vblank; 4070 dev->driver->disable_vblank = ironlake_disable_vblank; 4071 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; 4072 } else { 4073 if (INTEL_INFO(dev)->gen == 2) { 4074 dev->driver->irq_preinstall = i8xx_irq_preinstall; 4075 dev->driver->irq_postinstall = i8xx_irq_postinstall; 4076 dev->driver->irq_handler = i8xx_irq_handler; 4077 dev->driver->irq_uninstall = i8xx_irq_uninstall; 4078 } else if (INTEL_INFO(dev)->gen == 3) { 4079 dev->driver->irq_preinstall = i915_irq_preinstall; 4080 dev->driver->irq_postinstall = i915_irq_postinstall; 4081 dev->driver->irq_uninstall = i915_irq_uninstall; 4082 dev->driver->irq_handler = i915_irq_handler; 4083 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; 4084 } else { 4085 dev->driver->irq_preinstall = i965_irq_preinstall; 4086 dev->driver->irq_postinstall = i965_irq_postinstall; 4087 dev->driver->irq_uninstall = i965_irq_uninstall; 4088 dev->driver->irq_handler = i965_irq_handler; 4089 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; 4090 } 4091 dev->driver->enable_vblank = i915_enable_vblank; 4092 dev->driver->disable_vblank = i915_disable_vblank; 4093 } 4094 } 4095 4096 void intel_hpd_init(struct drm_device *dev) 4097 { 4098 struct drm_i915_private *dev_priv = dev->dev_private; 4099 struct drm_mode_config *mode_config = &dev->mode_config; 4100 struct drm_connector *connector; 4101 unsigned long irqflags; 4102 int i; 4103 4104 for (i = 1; i < HPD_NUM_PINS; i++) { 4105 dev_priv->hpd_stats[i].hpd_cnt = 0; 4106 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; 4107 } 4108 list_for_each_entry(connector, &mode_config->connector_list, head) { 4109 struct intel_connector *intel_connector = to_intel_connector(connector); 4110 connector->polled = intel_connector->polled; 4111 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE) 4112 connector->polled = DRM_CONNECTOR_POLL_HPD; 4113 } 4114 4115 /* Interrupt setup is already guaranteed to be single-threaded, this is 4116 * just to make the assert_spin_locked checks happy. */ 4117 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 4118 if (dev_priv->display.hpd_irq_setup) 4119 dev_priv->display.hpd_irq_setup(dev); 4120 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 4121 } 4122 4123 /* Disable interrupts so we can allow runtime PM. */ 4124 void hsw_runtime_pm_disable_interrupts(struct drm_device *dev) 4125 { 4126 struct drm_i915_private *dev_priv = dev->dev_private; 4127 unsigned long irqflags; 4128 4129 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 4130 4131 dev_priv->pm.regsave.deimr = I915_READ(DEIMR); 4132 dev_priv->pm.regsave.sdeimr = I915_READ(SDEIMR); 4133 dev_priv->pm.regsave.gtimr = I915_READ(GTIMR); 4134 dev_priv->pm.regsave.gtier = I915_READ(GTIER); 4135 dev_priv->pm.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR); 4136 4137 ironlake_disable_display_irq(dev_priv, 0xffffffff); 4138 ibx_disable_display_interrupt(dev_priv, 0xffffffff); 4139 ilk_disable_gt_irq(dev_priv, 0xffffffff); 4140 snb_disable_pm_irq(dev_priv, 0xffffffff); 4141 4142 dev_priv->pm.irqs_disabled = true; 4143 4144 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 4145 } 4146 4147 /* Restore interrupts so we can recover from runtime PM. */ 4148 void hsw_runtime_pm_restore_interrupts(struct drm_device *dev) 4149 { 4150 struct drm_i915_private *dev_priv = dev->dev_private; 4151 unsigned long irqflags; 4152 uint32_t val; 4153 4154 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 4155 4156 val = I915_READ(DEIMR); 4157 WARN(val != 0xffffffff, "DEIMR is 0x%08x\n", val); 4158 4159 val = I915_READ(SDEIMR); 4160 WARN(val != 0xffffffff, "SDEIMR is 0x%08x\n", val); 4161 4162 val = I915_READ(GTIMR); 4163 WARN(val != 0xffffffff, "GTIMR is 0x%08x\n", val); 4164 4165 val = I915_READ(GEN6_PMIMR); 4166 WARN(val != 0xffffffff, "GEN6_PMIMR is 0x%08x\n", val); 4167 4168 dev_priv->pm.irqs_disabled = false; 4169 4170 ironlake_enable_display_irq(dev_priv, ~dev_priv->pm.regsave.deimr); 4171 ibx_enable_display_interrupt(dev_priv, ~dev_priv->pm.regsave.sdeimr); 4172 ilk_enable_gt_irq(dev_priv, ~dev_priv->pm.regsave.gtimr); 4173 snb_enable_pm_irq(dev_priv, ~dev_priv->pm.regsave.gen6_pmimr); 4174 I915_WRITE(GTIER, dev_priv->pm.regsave.gtier); 4175 4176 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 4177 } 4178