1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- 2 */ 3 /* 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation the rights to use, copy, modify, merge, publish, 11 * distribute, sub license, and/or sell copies of the Software, and to 12 * permit persons to whom the Software is furnished to do so, subject to 13 * the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial portions 17 * of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 26 * 27 */ 28 29 #include <linux/sysrq.h> 30 #include <linux/slab.h> 31 #include "drmP.h" 32 #include "drm.h" 33 #include "i915_drm.h" 34 #include "i915_drv.h" 35 #include "i915_trace.h" 36 #include "intel_drv.h" 37 38 #define MAX_NOPID ((u32)~0) 39 40 /** 41 * Interrupts that are always left unmasked. 42 * 43 * Since pipe events are edge-triggered from the PIPESTAT register to IIR, 44 * we leave them always unmasked in IMR and then control enabling them through 45 * PIPESTAT alone. 46 */ 47 #define I915_INTERRUPT_ENABLE_FIX \ 48 (I915_ASLE_INTERRUPT | \ 49 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ 50 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \ 51 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \ 52 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \ 53 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) 54 55 /** Interrupts that we mask and unmask at runtime. */ 56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT) 57 58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\ 59 PIPE_VBLANK_INTERRUPT_STATUS) 60 61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\ 62 PIPE_VBLANK_INTERRUPT_ENABLE) 63 64 #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \ 65 DRM_I915_VBLANK_PIPE_B) 66 67 /* For display hotplug interrupt */ 68 static void 69 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) 70 { 71 if ((dev_priv->irq_mask & mask) != 0) { 72 dev_priv->irq_mask &= ~mask; 73 I915_WRITE(DEIMR, dev_priv->irq_mask); 74 POSTING_READ(DEIMR); 75 } 76 } 77 78 static inline void 79 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) 80 { 81 if ((dev_priv->irq_mask & mask) != mask) { 82 dev_priv->irq_mask |= mask; 83 I915_WRITE(DEIMR, dev_priv->irq_mask); 84 POSTING_READ(DEIMR); 85 } 86 } 87 88 void 89 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) 90 { 91 if ((dev_priv->pipestat[pipe] & mask) != mask) { 92 u32 reg = PIPESTAT(pipe); 93 94 dev_priv->pipestat[pipe] |= mask; 95 /* Enable the interrupt, clear any pending status */ 96 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); 97 POSTING_READ(reg); 98 } 99 } 100 101 void 102 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) 103 { 104 if ((dev_priv->pipestat[pipe] & mask) != 0) { 105 u32 reg = PIPESTAT(pipe); 106 107 dev_priv->pipestat[pipe] &= ~mask; 108 I915_WRITE(reg, dev_priv->pipestat[pipe]); 109 POSTING_READ(reg); 110 } 111 } 112 113 /** 114 * intel_enable_asle - enable ASLE interrupt for OpRegion 115 */ 116 void intel_enable_asle(struct drm_device *dev) 117 { 118 drm_i915_private_t *dev_priv = dev->dev_private; 119 unsigned long irqflags; 120 121 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 122 123 if (HAS_PCH_SPLIT(dev)) 124 ironlake_enable_display_irq(dev_priv, DE_GSE); 125 else { 126 i915_enable_pipestat(dev_priv, 1, 127 PIPE_LEGACY_BLC_EVENT_ENABLE); 128 if (INTEL_INFO(dev)->gen >= 4) 129 i915_enable_pipestat(dev_priv, 0, 130 PIPE_LEGACY_BLC_EVENT_ENABLE); 131 } 132 133 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 134 } 135 136 /** 137 * i915_pipe_enabled - check if a pipe is enabled 138 * @dev: DRM device 139 * @pipe: pipe to check 140 * 141 * Reading certain registers when the pipe is disabled can hang the chip. 142 * Use this routine to make sure the PLL is running and the pipe is active 143 * before reading such registers if unsure. 144 */ 145 static int 146 i915_pipe_enabled(struct drm_device *dev, int pipe) 147 { 148 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 149 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; 150 } 151 152 /* Called from drm generic code, passed a 'crtc', which 153 * we use as a pipe index 154 */ 155 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) 156 { 157 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 158 unsigned long high_frame; 159 unsigned long low_frame; 160 u32 high1, high2, low; 161 162 if (!i915_pipe_enabled(dev, pipe)) { 163 DRM_DEBUG_DRIVER("trying to get vblank count for disabled " 164 "pipe %c\n", pipe_name(pipe)); 165 return 0; 166 } 167 168 high_frame = PIPEFRAME(pipe); 169 low_frame = PIPEFRAMEPIXEL(pipe); 170 171 /* 172 * High & low register fields aren't synchronized, so make sure 173 * we get a low value that's stable across two reads of the high 174 * register. 175 */ 176 do { 177 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; 178 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK; 179 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; 180 } while (high1 != high2); 181 182 high1 >>= PIPE_FRAME_HIGH_SHIFT; 183 low >>= PIPE_FRAME_LOW_SHIFT; 184 return (high1 << 8) | low; 185 } 186 187 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) 188 { 189 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 190 int reg = PIPE_FRMCOUNT_GM45(pipe); 191 192 if (!i915_pipe_enabled(dev, pipe)) { 193 DRM_DEBUG_DRIVER("trying to get vblank count for disabled " 194 "pipe %c\n", pipe_name(pipe)); 195 return 0; 196 } 197 198 return I915_READ(reg); 199 } 200 201 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, 202 int *vpos, int *hpos) 203 { 204 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 205 u32 vbl = 0, position = 0; 206 int vbl_start, vbl_end, htotal, vtotal; 207 bool in_vbl = true; 208 int ret = 0; 209 210 if (!i915_pipe_enabled(dev, pipe)) { 211 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " 212 "pipe %c\n", pipe_name(pipe)); 213 return 0; 214 } 215 216 /* Get vtotal. */ 217 vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff); 218 219 if (INTEL_INFO(dev)->gen >= 4) { 220 /* No obvious pixelcount register. Only query vertical 221 * scanout position from Display scan line register. 222 */ 223 position = I915_READ(PIPEDSL(pipe)); 224 225 /* Decode into vertical scanout position. Don't have 226 * horizontal scanout position. 227 */ 228 *vpos = position & 0x1fff; 229 *hpos = 0; 230 } else { 231 /* Have access to pixelcount since start of frame. 232 * We can split this into vertical and horizontal 233 * scanout position. 234 */ 235 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; 236 237 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff); 238 *vpos = position / htotal; 239 *hpos = position - (*vpos * htotal); 240 } 241 242 /* Query vblank area. */ 243 vbl = I915_READ(VBLANK(pipe)); 244 245 /* Test position against vblank region. */ 246 vbl_start = vbl & 0x1fff; 247 vbl_end = (vbl >> 16) & 0x1fff; 248 249 if ((*vpos < vbl_start) || (*vpos > vbl_end)) 250 in_vbl = false; 251 252 /* Inside "upper part" of vblank area? Apply corrective offset: */ 253 if (in_vbl && (*vpos >= vbl_start)) 254 *vpos = *vpos - vtotal; 255 256 /* Readouts valid? */ 257 if (vbl > 0) 258 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; 259 260 /* In vblank? */ 261 if (in_vbl) 262 ret |= DRM_SCANOUTPOS_INVBL; 263 264 return ret; 265 } 266 267 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, 268 int *max_error, 269 struct timeval *vblank_time, 270 unsigned flags) 271 { 272 struct drm_i915_private *dev_priv = dev->dev_private; 273 struct drm_crtc *crtc; 274 275 if (pipe < 0 || pipe >= dev_priv->num_pipe) { 276 DRM_ERROR("Invalid crtc %d\n", pipe); 277 return -EINVAL; 278 } 279 280 /* Get drm_crtc to timestamp: */ 281 crtc = intel_get_crtc_for_pipe(dev, pipe); 282 if (crtc == NULL) { 283 DRM_ERROR("Invalid crtc %d\n", pipe); 284 return -EINVAL; 285 } 286 287 if (!crtc->enabled) { 288 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); 289 return -EBUSY; 290 } 291 292 /* Helper routine in DRM core does all the work: */ 293 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, 294 vblank_time, flags, 295 crtc); 296 } 297 298 /* 299 * Handle hotplug events outside the interrupt handler proper. 300 */ 301 static void i915_hotplug_work_func(struct work_struct *work) 302 { 303 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, 304 hotplug_work); 305 struct drm_device *dev = dev_priv->dev; 306 struct drm_mode_config *mode_config = &dev->mode_config; 307 struct intel_encoder *encoder; 308 309 DRM_DEBUG_KMS("running encoder hotplug functions\n"); 310 311 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) 312 if (encoder->hot_plug) 313 encoder->hot_plug(encoder); 314 315 /* Just fire off a uevent and let userspace tell us what to do */ 316 drm_helper_hpd_irq_event(dev); 317 } 318 319 static void i915_handle_rps_change(struct drm_device *dev) 320 { 321 drm_i915_private_t *dev_priv = dev->dev_private; 322 u32 busy_up, busy_down, max_avg, min_avg; 323 u8 new_delay = dev_priv->cur_delay; 324 325 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); 326 busy_up = I915_READ(RCPREVBSYTUPAVG); 327 busy_down = I915_READ(RCPREVBSYTDNAVG); 328 max_avg = I915_READ(RCBMAXAVG); 329 min_avg = I915_READ(RCBMINAVG); 330 331 /* Handle RCS change request from hw */ 332 if (busy_up > max_avg) { 333 if (dev_priv->cur_delay != dev_priv->max_delay) 334 new_delay = dev_priv->cur_delay - 1; 335 if (new_delay < dev_priv->max_delay) 336 new_delay = dev_priv->max_delay; 337 } else if (busy_down < min_avg) { 338 if (dev_priv->cur_delay != dev_priv->min_delay) 339 new_delay = dev_priv->cur_delay + 1; 340 if (new_delay > dev_priv->min_delay) 341 new_delay = dev_priv->min_delay; 342 } 343 344 if (ironlake_set_drps(dev, new_delay)) 345 dev_priv->cur_delay = new_delay; 346 347 return; 348 } 349 350 static void notify_ring(struct drm_device *dev, 351 struct intel_ring_buffer *ring) 352 { 353 struct drm_i915_private *dev_priv = dev->dev_private; 354 u32 seqno; 355 356 if (ring->obj == NULL) 357 return; 358 359 seqno = ring->get_seqno(ring); 360 trace_i915_gem_request_complete(ring, seqno); 361 362 ring->irq_seqno = seqno; 363 wake_up_all(&ring->irq_queue); 364 365 dev_priv->hangcheck_count = 0; 366 mod_timer(&dev_priv->hangcheck_timer, 367 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); 368 } 369 370 static void gen6_pm_rps_work(struct work_struct *work) 371 { 372 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, 373 rps_work); 374 u8 new_delay = dev_priv->cur_delay; 375 u32 pm_iir, pm_imr; 376 377 spin_lock_irq(&dev_priv->rps_lock); 378 pm_iir = dev_priv->pm_iir; 379 dev_priv->pm_iir = 0; 380 pm_imr = I915_READ(GEN6_PMIMR); 381 spin_unlock_irq(&dev_priv->rps_lock); 382 383 if (!pm_iir) 384 return; 385 386 mutex_lock(&dev_priv->dev->struct_mutex); 387 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { 388 if (dev_priv->cur_delay != dev_priv->max_delay) 389 new_delay = dev_priv->cur_delay + 1; 390 if (new_delay > dev_priv->max_delay) 391 new_delay = dev_priv->max_delay; 392 } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) { 393 gen6_gt_force_wake_get(dev_priv); 394 if (dev_priv->cur_delay != dev_priv->min_delay) 395 new_delay = dev_priv->cur_delay - 1; 396 if (new_delay < dev_priv->min_delay) { 397 new_delay = dev_priv->min_delay; 398 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 399 I915_READ(GEN6_RP_INTERRUPT_LIMITS) | 400 ((new_delay << 16) & 0x3f0000)); 401 } else { 402 /* Make sure we continue to get down interrupts 403 * until we hit the minimum frequency */ 404 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 405 I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000); 406 } 407 gen6_gt_force_wake_put(dev_priv); 408 } 409 410 gen6_set_rps(dev_priv->dev, new_delay); 411 dev_priv->cur_delay = new_delay; 412 413 /* 414 * rps_lock not held here because clearing is non-destructive. There is 415 * an *extremely* unlikely race with gen6_rps_enable() that is prevented 416 * by holding struct_mutex for the duration of the write. 417 */ 418 I915_WRITE(GEN6_PMIMR, pm_imr & ~pm_iir); 419 mutex_unlock(&dev_priv->dev->struct_mutex); 420 } 421 422 static void pch_irq_handler(struct drm_device *dev) 423 { 424 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 425 u32 pch_iir; 426 int pipe; 427 428 pch_iir = I915_READ(SDEIIR); 429 430 if (pch_iir & SDE_AUDIO_POWER_MASK) 431 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", 432 (pch_iir & SDE_AUDIO_POWER_MASK) >> 433 SDE_AUDIO_POWER_SHIFT); 434 435 if (pch_iir & SDE_GMBUS) 436 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n"); 437 438 if (pch_iir & SDE_AUDIO_HDCP_MASK) 439 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); 440 441 if (pch_iir & SDE_AUDIO_TRANS_MASK) 442 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); 443 444 if (pch_iir & SDE_POISON) 445 DRM_ERROR("PCH poison interrupt\n"); 446 447 if (pch_iir & SDE_FDI_MASK) 448 for_each_pipe(pipe) 449 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", 450 pipe_name(pipe), 451 I915_READ(FDI_RX_IIR(pipe))); 452 453 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) 454 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); 455 456 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) 457 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); 458 459 if (pch_iir & SDE_TRANSB_FIFO_UNDER) 460 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n"); 461 if (pch_iir & SDE_TRANSA_FIFO_UNDER) 462 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n"); 463 } 464 465 static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS) 466 { 467 struct drm_device *dev = (struct drm_device *) arg; 468 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 469 int ret = IRQ_NONE; 470 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir; 471 struct drm_i915_master_private *master_priv; 472 473 atomic_inc(&dev_priv->irq_received); 474 475 /* disable master interrupt before clearing iir */ 476 de_ier = I915_READ(DEIER); 477 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); 478 POSTING_READ(DEIER); 479 480 de_iir = I915_READ(DEIIR); 481 gt_iir = I915_READ(GTIIR); 482 pch_iir = I915_READ(SDEIIR); 483 pm_iir = I915_READ(GEN6_PMIIR); 484 485 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && pm_iir == 0) 486 goto done; 487 488 ret = IRQ_HANDLED; 489 490 if (dev->primary->master) { 491 master_priv = dev->primary->master->driver_priv; 492 if (master_priv->sarea_priv) 493 master_priv->sarea_priv->last_dispatch = 494 READ_BREADCRUMB(dev_priv); 495 } 496 497 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY)) 498 notify_ring(dev, &dev_priv->ring[RCS]); 499 if (gt_iir & GT_GEN6_BSD_USER_INTERRUPT) 500 notify_ring(dev, &dev_priv->ring[VCS]); 501 if (gt_iir & GT_BLT_USER_INTERRUPT) 502 notify_ring(dev, &dev_priv->ring[BCS]); 503 504 if (de_iir & DE_GSE_IVB) 505 intel_opregion_gse_intr(dev); 506 507 if (de_iir & DE_PLANEA_FLIP_DONE_IVB) { 508 intel_prepare_page_flip(dev, 0); 509 intel_finish_page_flip_plane(dev, 0); 510 } 511 512 if (de_iir & DE_PLANEB_FLIP_DONE_IVB) { 513 intel_prepare_page_flip(dev, 1); 514 intel_finish_page_flip_plane(dev, 1); 515 } 516 517 if (de_iir & DE_PIPEA_VBLANK_IVB) 518 drm_handle_vblank(dev, 0); 519 520 if (de_iir & DE_PIPEB_VBLANK_IVB) 521 drm_handle_vblank(dev, 1); 522 523 /* check event from PCH */ 524 if (de_iir & DE_PCH_EVENT_IVB) { 525 if (pch_iir & SDE_HOTPLUG_MASK_CPT) 526 queue_work(dev_priv->wq, &dev_priv->hotplug_work); 527 pch_irq_handler(dev); 528 } 529 530 if (pm_iir & GEN6_PM_DEFERRED_EVENTS) { 531 unsigned long flags; 532 spin_lock_irqsave(&dev_priv->rps_lock, flags); 533 WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n"); 534 I915_WRITE(GEN6_PMIMR, pm_iir); 535 dev_priv->pm_iir |= pm_iir; 536 spin_unlock_irqrestore(&dev_priv->rps_lock, flags); 537 queue_work(dev_priv->wq, &dev_priv->rps_work); 538 } 539 540 /* should clear PCH hotplug event before clear CPU irq */ 541 I915_WRITE(SDEIIR, pch_iir); 542 I915_WRITE(GTIIR, gt_iir); 543 I915_WRITE(DEIIR, de_iir); 544 I915_WRITE(GEN6_PMIIR, pm_iir); 545 546 done: 547 I915_WRITE(DEIER, de_ier); 548 POSTING_READ(DEIER); 549 550 return ret; 551 } 552 553 static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS) 554 { 555 struct drm_device *dev = (struct drm_device *) arg; 556 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 557 int ret = IRQ_NONE; 558 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir; 559 u32 hotplug_mask; 560 struct drm_i915_master_private *master_priv; 561 u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT; 562 563 atomic_inc(&dev_priv->irq_received); 564 565 if (IS_GEN6(dev)) 566 bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT; 567 568 /* disable master interrupt before clearing iir */ 569 de_ier = I915_READ(DEIER); 570 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); 571 POSTING_READ(DEIER); 572 573 de_iir = I915_READ(DEIIR); 574 gt_iir = I915_READ(GTIIR); 575 pch_iir = I915_READ(SDEIIR); 576 pm_iir = I915_READ(GEN6_PMIIR); 577 578 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && 579 (!IS_GEN6(dev) || pm_iir == 0)) 580 goto done; 581 582 if (HAS_PCH_CPT(dev)) 583 hotplug_mask = SDE_HOTPLUG_MASK_CPT; 584 else 585 hotplug_mask = SDE_HOTPLUG_MASK; 586 587 ret = IRQ_HANDLED; 588 589 if (dev->primary->master) { 590 master_priv = dev->primary->master->driver_priv; 591 if (master_priv->sarea_priv) 592 master_priv->sarea_priv->last_dispatch = 593 READ_BREADCRUMB(dev_priv); 594 } 595 596 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY)) 597 notify_ring(dev, &dev_priv->ring[RCS]); 598 if (gt_iir & bsd_usr_interrupt) 599 notify_ring(dev, &dev_priv->ring[VCS]); 600 if (gt_iir & GT_BLT_USER_INTERRUPT) 601 notify_ring(dev, &dev_priv->ring[BCS]); 602 603 if (de_iir & DE_GSE) 604 intel_opregion_gse_intr(dev); 605 606 if (de_iir & DE_PLANEA_FLIP_DONE) { 607 intel_prepare_page_flip(dev, 0); 608 intel_finish_page_flip_plane(dev, 0); 609 } 610 611 if (de_iir & DE_PLANEB_FLIP_DONE) { 612 intel_prepare_page_flip(dev, 1); 613 intel_finish_page_flip_plane(dev, 1); 614 } 615 616 if (de_iir & DE_PIPEA_VBLANK) 617 drm_handle_vblank(dev, 0); 618 619 if (de_iir & DE_PIPEB_VBLANK) 620 drm_handle_vblank(dev, 1); 621 622 /* check event from PCH */ 623 if (de_iir & DE_PCH_EVENT) { 624 if (pch_iir & hotplug_mask) 625 queue_work(dev_priv->wq, &dev_priv->hotplug_work); 626 pch_irq_handler(dev); 627 } 628 629 if (de_iir & DE_PCU_EVENT) { 630 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); 631 i915_handle_rps_change(dev); 632 } 633 634 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS) { 635 /* 636 * IIR bits should never already be set because IMR should 637 * prevent an interrupt from being shown in IIR. The warning 638 * displays a case where we've unsafely cleared 639 * dev_priv->pm_iir. Although missing an interrupt of the same 640 * type is not a problem, it displays a problem in the logic. 641 * 642 * The mask bit in IMR is cleared by rps_work. 643 */ 644 unsigned long flags; 645 spin_lock_irqsave(&dev_priv->rps_lock, flags); 646 WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n"); 647 I915_WRITE(GEN6_PMIMR, pm_iir); 648 dev_priv->pm_iir |= pm_iir; 649 spin_unlock_irqrestore(&dev_priv->rps_lock, flags); 650 queue_work(dev_priv->wq, &dev_priv->rps_work); 651 } 652 653 /* should clear PCH hotplug event before clear CPU irq */ 654 I915_WRITE(SDEIIR, pch_iir); 655 I915_WRITE(GTIIR, gt_iir); 656 I915_WRITE(DEIIR, de_iir); 657 I915_WRITE(GEN6_PMIIR, pm_iir); 658 659 done: 660 I915_WRITE(DEIER, de_ier); 661 POSTING_READ(DEIER); 662 663 return ret; 664 } 665 666 /** 667 * i915_error_work_func - do process context error handling work 668 * @work: work struct 669 * 670 * Fire an error uevent so userspace can see that a hang or error 671 * was detected. 672 */ 673 static void i915_error_work_func(struct work_struct *work) 674 { 675 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, 676 error_work); 677 struct drm_device *dev = dev_priv->dev; 678 char *error_event[] = { "ERROR=1", NULL }; 679 char *reset_event[] = { "RESET=1", NULL }; 680 char *reset_done_event[] = { "ERROR=0", NULL }; 681 682 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); 683 684 if (atomic_read(&dev_priv->mm.wedged)) { 685 DRM_DEBUG_DRIVER("resetting chip\n"); 686 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); 687 if (!i915_reset(dev, GRDOM_RENDER)) { 688 atomic_set(&dev_priv->mm.wedged, 0); 689 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event); 690 } 691 complete_all(&dev_priv->error_completion); 692 } 693 } 694 695 #ifdef CONFIG_DEBUG_FS 696 static struct drm_i915_error_object * 697 i915_error_object_create(struct drm_i915_private *dev_priv, 698 struct drm_i915_gem_object *src) 699 { 700 struct drm_i915_error_object *dst; 701 int page, page_count; 702 u32 reloc_offset; 703 704 if (src == NULL || src->pages == NULL) 705 return NULL; 706 707 page_count = src->base.size / PAGE_SIZE; 708 709 dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC); 710 if (dst == NULL) 711 return NULL; 712 713 reloc_offset = src->gtt_offset; 714 for (page = 0; page < page_count; page++) { 715 unsigned long flags; 716 void __iomem *s; 717 void *d; 718 719 d = kmalloc(PAGE_SIZE, GFP_ATOMIC); 720 if (d == NULL) 721 goto unwind; 722 723 local_irq_save(flags); 724 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, 725 reloc_offset); 726 memcpy_fromio(d, s, PAGE_SIZE); 727 io_mapping_unmap_atomic(s); 728 local_irq_restore(flags); 729 730 dst->pages[page] = d; 731 732 reloc_offset += PAGE_SIZE; 733 } 734 dst->page_count = page_count; 735 dst->gtt_offset = src->gtt_offset; 736 737 return dst; 738 739 unwind: 740 while (page--) 741 kfree(dst->pages[page]); 742 kfree(dst); 743 return NULL; 744 } 745 746 static void 747 i915_error_object_free(struct drm_i915_error_object *obj) 748 { 749 int page; 750 751 if (obj == NULL) 752 return; 753 754 for (page = 0; page < obj->page_count; page++) 755 kfree(obj->pages[page]); 756 757 kfree(obj); 758 } 759 760 static void 761 i915_error_state_free(struct drm_device *dev, 762 struct drm_i915_error_state *error) 763 { 764 int i; 765 766 for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++) 767 i915_error_object_free(error->batchbuffer[i]); 768 769 for (i = 0; i < ARRAY_SIZE(error->ringbuffer); i++) 770 i915_error_object_free(error->ringbuffer[i]); 771 772 kfree(error->active_bo); 773 kfree(error->overlay); 774 kfree(error); 775 } 776 777 static u32 capture_bo_list(struct drm_i915_error_buffer *err, 778 int count, 779 struct list_head *head) 780 { 781 struct drm_i915_gem_object *obj; 782 int i = 0; 783 784 list_for_each_entry(obj, head, mm_list) { 785 err->size = obj->base.size; 786 err->name = obj->base.name; 787 err->seqno = obj->last_rendering_seqno; 788 err->gtt_offset = obj->gtt_offset; 789 err->read_domains = obj->base.read_domains; 790 err->write_domain = obj->base.write_domain; 791 err->fence_reg = obj->fence_reg; 792 err->pinned = 0; 793 if (obj->pin_count > 0) 794 err->pinned = 1; 795 if (obj->user_pin_count > 0) 796 err->pinned = -1; 797 err->tiling = obj->tiling_mode; 798 err->dirty = obj->dirty; 799 err->purgeable = obj->madv != I915_MADV_WILLNEED; 800 err->ring = obj->ring ? obj->ring->id : 0; 801 err->cache_level = obj->cache_level; 802 803 if (++i == count) 804 break; 805 806 err++; 807 } 808 809 return i; 810 } 811 812 static void i915_gem_record_fences(struct drm_device *dev, 813 struct drm_i915_error_state *error) 814 { 815 struct drm_i915_private *dev_priv = dev->dev_private; 816 int i; 817 818 /* Fences */ 819 switch (INTEL_INFO(dev)->gen) { 820 case 6: 821 for (i = 0; i < 16; i++) 822 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8)); 823 break; 824 case 5: 825 case 4: 826 for (i = 0; i < 16; i++) 827 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8)); 828 break; 829 case 3: 830 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) 831 for (i = 0; i < 8; i++) 832 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4)); 833 case 2: 834 for (i = 0; i < 8; i++) 835 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); 836 break; 837 838 } 839 } 840 841 static struct drm_i915_error_object * 842 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv, 843 struct intel_ring_buffer *ring) 844 { 845 struct drm_i915_gem_object *obj; 846 u32 seqno; 847 848 if (!ring->get_seqno) 849 return NULL; 850 851 seqno = ring->get_seqno(ring); 852 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) { 853 if (obj->ring != ring) 854 continue; 855 856 if (i915_seqno_passed(seqno, obj->last_rendering_seqno)) 857 continue; 858 859 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0) 860 continue; 861 862 /* We need to copy these to an anonymous buffer as the simplest 863 * method to avoid being overwritten by userspace. 864 */ 865 return i915_error_object_create(dev_priv, obj); 866 } 867 868 return NULL; 869 } 870 871 /** 872 * i915_capture_error_state - capture an error record for later analysis 873 * @dev: drm device 874 * 875 * Should be called when an error is detected (either a hang or an error 876 * interrupt) to capture error state from the time of the error. Fills 877 * out a structure which becomes available in debugfs for user level tools 878 * to pick up. 879 */ 880 static void i915_capture_error_state(struct drm_device *dev) 881 { 882 struct drm_i915_private *dev_priv = dev->dev_private; 883 struct drm_i915_gem_object *obj; 884 struct drm_i915_error_state *error; 885 unsigned long flags; 886 int i, pipe; 887 888 spin_lock_irqsave(&dev_priv->error_lock, flags); 889 error = dev_priv->first_error; 890 spin_unlock_irqrestore(&dev_priv->error_lock, flags); 891 if (error) 892 return; 893 894 /* Account for pipe specific data like PIPE*STAT */ 895 error = kmalloc(sizeof(*error), GFP_ATOMIC); 896 if (!error) { 897 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); 898 return; 899 } 900 901 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n", 902 dev->primary->index); 903 904 error->seqno = dev_priv->ring[RCS].get_seqno(&dev_priv->ring[RCS]); 905 error->eir = I915_READ(EIR); 906 error->pgtbl_er = I915_READ(PGTBL_ER); 907 for_each_pipe(pipe) 908 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe)); 909 error->instpm = I915_READ(INSTPM); 910 error->error = 0; 911 if (INTEL_INFO(dev)->gen >= 6) { 912 error->error = I915_READ(ERROR_GEN6); 913 914 error->bcs_acthd = I915_READ(BCS_ACTHD); 915 error->bcs_ipehr = I915_READ(BCS_IPEHR); 916 error->bcs_ipeir = I915_READ(BCS_IPEIR); 917 error->bcs_instdone = I915_READ(BCS_INSTDONE); 918 error->bcs_seqno = 0; 919 if (dev_priv->ring[BCS].get_seqno) 920 error->bcs_seqno = dev_priv->ring[BCS].get_seqno(&dev_priv->ring[BCS]); 921 922 error->vcs_acthd = I915_READ(VCS_ACTHD); 923 error->vcs_ipehr = I915_READ(VCS_IPEHR); 924 error->vcs_ipeir = I915_READ(VCS_IPEIR); 925 error->vcs_instdone = I915_READ(VCS_INSTDONE); 926 error->vcs_seqno = 0; 927 if (dev_priv->ring[VCS].get_seqno) 928 error->vcs_seqno = dev_priv->ring[VCS].get_seqno(&dev_priv->ring[VCS]); 929 } 930 if (INTEL_INFO(dev)->gen >= 4) { 931 error->ipeir = I915_READ(IPEIR_I965); 932 error->ipehr = I915_READ(IPEHR_I965); 933 error->instdone = I915_READ(INSTDONE_I965); 934 error->instps = I915_READ(INSTPS); 935 error->instdone1 = I915_READ(INSTDONE1); 936 error->acthd = I915_READ(ACTHD_I965); 937 error->bbaddr = I915_READ64(BB_ADDR); 938 } else { 939 error->ipeir = I915_READ(IPEIR); 940 error->ipehr = I915_READ(IPEHR); 941 error->instdone = I915_READ(INSTDONE); 942 error->acthd = I915_READ(ACTHD); 943 error->bbaddr = 0; 944 } 945 i915_gem_record_fences(dev, error); 946 947 /* Record the active batch and ring buffers */ 948 for (i = 0; i < I915_NUM_RINGS; i++) { 949 error->batchbuffer[i] = 950 i915_error_first_batchbuffer(dev_priv, 951 &dev_priv->ring[i]); 952 953 error->ringbuffer[i] = 954 i915_error_object_create(dev_priv, 955 dev_priv->ring[i].obj); 956 } 957 958 /* Record buffers on the active and pinned lists. */ 959 error->active_bo = NULL; 960 error->pinned_bo = NULL; 961 962 i = 0; 963 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) 964 i++; 965 error->active_bo_count = i; 966 list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list) 967 i++; 968 error->pinned_bo_count = i - error->active_bo_count; 969 970 error->active_bo = NULL; 971 error->pinned_bo = NULL; 972 if (i) { 973 error->active_bo = kmalloc(sizeof(*error->active_bo)*i, 974 GFP_ATOMIC); 975 if (error->active_bo) 976 error->pinned_bo = 977 error->active_bo + error->active_bo_count; 978 } 979 980 if (error->active_bo) 981 error->active_bo_count = 982 capture_bo_list(error->active_bo, 983 error->active_bo_count, 984 &dev_priv->mm.active_list); 985 986 if (error->pinned_bo) 987 error->pinned_bo_count = 988 capture_bo_list(error->pinned_bo, 989 error->pinned_bo_count, 990 &dev_priv->mm.pinned_list); 991 992 do_gettimeofday(&error->time); 993 994 error->overlay = intel_overlay_capture_error_state(dev); 995 error->display = intel_display_capture_error_state(dev); 996 997 spin_lock_irqsave(&dev_priv->error_lock, flags); 998 if (dev_priv->first_error == NULL) { 999 dev_priv->first_error = error; 1000 error = NULL; 1001 } 1002 spin_unlock_irqrestore(&dev_priv->error_lock, flags); 1003 1004 if (error) 1005 i915_error_state_free(dev, error); 1006 } 1007 1008 void i915_destroy_error_state(struct drm_device *dev) 1009 { 1010 struct drm_i915_private *dev_priv = dev->dev_private; 1011 struct drm_i915_error_state *error; 1012 1013 spin_lock(&dev_priv->error_lock); 1014 error = dev_priv->first_error; 1015 dev_priv->first_error = NULL; 1016 spin_unlock(&dev_priv->error_lock); 1017 1018 if (error) 1019 i915_error_state_free(dev, error); 1020 } 1021 #else 1022 #define i915_capture_error_state(x) 1023 #endif 1024 1025 static void i915_report_and_clear_eir(struct drm_device *dev) 1026 { 1027 struct drm_i915_private *dev_priv = dev->dev_private; 1028 u32 eir = I915_READ(EIR); 1029 int pipe; 1030 1031 if (!eir) 1032 return; 1033 1034 printk(KERN_ERR "render error detected, EIR: 0x%08x\n", 1035 eir); 1036 1037 if (IS_G4X(dev)) { 1038 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { 1039 u32 ipeir = I915_READ(IPEIR_I965); 1040 1041 printk(KERN_ERR " IPEIR: 0x%08x\n", 1042 I915_READ(IPEIR_I965)); 1043 printk(KERN_ERR " IPEHR: 0x%08x\n", 1044 I915_READ(IPEHR_I965)); 1045 printk(KERN_ERR " INSTDONE: 0x%08x\n", 1046 I915_READ(INSTDONE_I965)); 1047 printk(KERN_ERR " INSTPS: 0x%08x\n", 1048 I915_READ(INSTPS)); 1049 printk(KERN_ERR " INSTDONE1: 0x%08x\n", 1050 I915_READ(INSTDONE1)); 1051 printk(KERN_ERR " ACTHD: 0x%08x\n", 1052 I915_READ(ACTHD_I965)); 1053 I915_WRITE(IPEIR_I965, ipeir); 1054 POSTING_READ(IPEIR_I965); 1055 } 1056 if (eir & GM45_ERROR_PAGE_TABLE) { 1057 u32 pgtbl_err = I915_READ(PGTBL_ER); 1058 printk(KERN_ERR "page table error\n"); 1059 printk(KERN_ERR " PGTBL_ER: 0x%08x\n", 1060 pgtbl_err); 1061 I915_WRITE(PGTBL_ER, pgtbl_err); 1062 POSTING_READ(PGTBL_ER); 1063 } 1064 } 1065 1066 if (!IS_GEN2(dev)) { 1067 if (eir & I915_ERROR_PAGE_TABLE) { 1068 u32 pgtbl_err = I915_READ(PGTBL_ER); 1069 printk(KERN_ERR "page table error\n"); 1070 printk(KERN_ERR " PGTBL_ER: 0x%08x\n", 1071 pgtbl_err); 1072 I915_WRITE(PGTBL_ER, pgtbl_err); 1073 POSTING_READ(PGTBL_ER); 1074 } 1075 } 1076 1077 if (eir & I915_ERROR_MEMORY_REFRESH) { 1078 printk(KERN_ERR "memory refresh error:\n"); 1079 for_each_pipe(pipe) 1080 printk(KERN_ERR "pipe %c stat: 0x%08x\n", 1081 pipe_name(pipe), I915_READ(PIPESTAT(pipe))); 1082 /* pipestat has already been acked */ 1083 } 1084 if (eir & I915_ERROR_INSTRUCTION) { 1085 printk(KERN_ERR "instruction error\n"); 1086 printk(KERN_ERR " INSTPM: 0x%08x\n", 1087 I915_READ(INSTPM)); 1088 if (INTEL_INFO(dev)->gen < 4) { 1089 u32 ipeir = I915_READ(IPEIR); 1090 1091 printk(KERN_ERR " IPEIR: 0x%08x\n", 1092 I915_READ(IPEIR)); 1093 printk(KERN_ERR " IPEHR: 0x%08x\n", 1094 I915_READ(IPEHR)); 1095 printk(KERN_ERR " INSTDONE: 0x%08x\n", 1096 I915_READ(INSTDONE)); 1097 printk(KERN_ERR " ACTHD: 0x%08x\n", 1098 I915_READ(ACTHD)); 1099 I915_WRITE(IPEIR, ipeir); 1100 POSTING_READ(IPEIR); 1101 } else { 1102 u32 ipeir = I915_READ(IPEIR_I965); 1103 1104 printk(KERN_ERR " IPEIR: 0x%08x\n", 1105 I915_READ(IPEIR_I965)); 1106 printk(KERN_ERR " IPEHR: 0x%08x\n", 1107 I915_READ(IPEHR_I965)); 1108 printk(KERN_ERR " INSTDONE: 0x%08x\n", 1109 I915_READ(INSTDONE_I965)); 1110 printk(KERN_ERR " INSTPS: 0x%08x\n", 1111 I915_READ(INSTPS)); 1112 printk(KERN_ERR " INSTDONE1: 0x%08x\n", 1113 I915_READ(INSTDONE1)); 1114 printk(KERN_ERR " ACTHD: 0x%08x\n", 1115 I915_READ(ACTHD_I965)); 1116 I915_WRITE(IPEIR_I965, ipeir); 1117 POSTING_READ(IPEIR_I965); 1118 } 1119 } 1120 1121 I915_WRITE(EIR, eir); 1122 POSTING_READ(EIR); 1123 eir = I915_READ(EIR); 1124 if (eir) { 1125 /* 1126 * some errors might have become stuck, 1127 * mask them. 1128 */ 1129 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); 1130 I915_WRITE(EMR, I915_READ(EMR) | eir); 1131 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); 1132 } 1133 } 1134 1135 /** 1136 * i915_handle_error - handle an error interrupt 1137 * @dev: drm device 1138 * 1139 * Do some basic checking of regsiter state at error interrupt time and 1140 * dump it to the syslog. Also call i915_capture_error_state() to make 1141 * sure we get a record and make it available in debugfs. Fire a uevent 1142 * so userspace knows something bad happened (should trigger collection 1143 * of a ring dump etc.). 1144 */ 1145 void i915_handle_error(struct drm_device *dev, bool wedged) 1146 { 1147 struct drm_i915_private *dev_priv = dev->dev_private; 1148 1149 i915_capture_error_state(dev); 1150 i915_report_and_clear_eir(dev); 1151 1152 if (wedged) { 1153 INIT_COMPLETION(dev_priv->error_completion); 1154 atomic_set(&dev_priv->mm.wedged, 1); 1155 1156 /* 1157 * Wakeup waiting processes so they don't hang 1158 */ 1159 wake_up_all(&dev_priv->ring[RCS].irq_queue); 1160 if (HAS_BSD(dev)) 1161 wake_up_all(&dev_priv->ring[VCS].irq_queue); 1162 if (HAS_BLT(dev)) 1163 wake_up_all(&dev_priv->ring[BCS].irq_queue); 1164 } 1165 1166 queue_work(dev_priv->wq, &dev_priv->error_work); 1167 } 1168 1169 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe) 1170 { 1171 drm_i915_private_t *dev_priv = dev->dev_private; 1172 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 1173 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1174 struct drm_i915_gem_object *obj; 1175 struct intel_unpin_work *work; 1176 unsigned long flags; 1177 bool stall_detected; 1178 1179 /* Ignore early vblank irqs */ 1180 if (intel_crtc == NULL) 1181 return; 1182 1183 spin_lock_irqsave(&dev->event_lock, flags); 1184 work = intel_crtc->unpin_work; 1185 1186 if (work == NULL || work->pending || !work->enable_stall_check) { 1187 /* Either the pending flip IRQ arrived, or we're too early. Don't check */ 1188 spin_unlock_irqrestore(&dev->event_lock, flags); 1189 return; 1190 } 1191 1192 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ 1193 obj = work->pending_flip_obj; 1194 if (INTEL_INFO(dev)->gen >= 4) { 1195 int dspsurf = DSPSURF(intel_crtc->plane); 1196 stall_detected = I915_READ(dspsurf) == obj->gtt_offset; 1197 } else { 1198 int dspaddr = DSPADDR(intel_crtc->plane); 1199 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset + 1200 crtc->y * crtc->fb->pitch + 1201 crtc->x * crtc->fb->bits_per_pixel/8); 1202 } 1203 1204 spin_unlock_irqrestore(&dev->event_lock, flags); 1205 1206 if (stall_detected) { 1207 DRM_DEBUG_DRIVER("Pageflip stall detected\n"); 1208 intel_prepare_page_flip(dev, intel_crtc->plane); 1209 } 1210 } 1211 1212 static irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) 1213 { 1214 struct drm_device *dev = (struct drm_device *) arg; 1215 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1216 struct drm_i915_master_private *master_priv; 1217 u32 iir, new_iir; 1218 u32 pipe_stats[I915_MAX_PIPES]; 1219 u32 vblank_status; 1220 int vblank = 0; 1221 unsigned long irqflags; 1222 int irq_received; 1223 int ret = IRQ_NONE, pipe; 1224 bool blc_event = false; 1225 1226 atomic_inc(&dev_priv->irq_received); 1227 1228 iir = I915_READ(IIR); 1229 1230 if (INTEL_INFO(dev)->gen >= 4) 1231 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS; 1232 else 1233 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS; 1234 1235 for (;;) { 1236 irq_received = iir != 0; 1237 1238 /* Can't rely on pipestat interrupt bit in iir as it might 1239 * have been cleared after the pipestat interrupt was received. 1240 * It doesn't set the bit in iir again, but it still produces 1241 * interrupts (for non-MSI). 1242 */ 1243 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1244 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) 1245 i915_handle_error(dev, false); 1246 1247 for_each_pipe(pipe) { 1248 int reg = PIPESTAT(pipe); 1249 pipe_stats[pipe] = I915_READ(reg); 1250 1251 /* 1252 * Clear the PIPE*STAT regs before the IIR 1253 */ 1254 if (pipe_stats[pipe] & 0x8000ffff) { 1255 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 1256 DRM_DEBUG_DRIVER("pipe %c underrun\n", 1257 pipe_name(pipe)); 1258 I915_WRITE(reg, pipe_stats[pipe]); 1259 irq_received = 1; 1260 } 1261 } 1262 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1263 1264 if (!irq_received) 1265 break; 1266 1267 ret = IRQ_HANDLED; 1268 1269 /* Consume port. Then clear IIR or we'll miss events */ 1270 if ((I915_HAS_HOTPLUG(dev)) && 1271 (iir & I915_DISPLAY_PORT_INTERRUPT)) { 1272 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); 1273 1274 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", 1275 hotplug_status); 1276 if (hotplug_status & dev_priv->hotplug_supported_mask) 1277 queue_work(dev_priv->wq, 1278 &dev_priv->hotplug_work); 1279 1280 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); 1281 I915_READ(PORT_HOTPLUG_STAT); 1282 } 1283 1284 I915_WRITE(IIR, iir); 1285 new_iir = I915_READ(IIR); /* Flush posted writes */ 1286 1287 if (dev->primary->master) { 1288 master_priv = dev->primary->master->driver_priv; 1289 if (master_priv->sarea_priv) 1290 master_priv->sarea_priv->last_dispatch = 1291 READ_BREADCRUMB(dev_priv); 1292 } 1293 1294 if (iir & I915_USER_INTERRUPT) 1295 notify_ring(dev, &dev_priv->ring[RCS]); 1296 if (iir & I915_BSD_USER_INTERRUPT) 1297 notify_ring(dev, &dev_priv->ring[VCS]); 1298 1299 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) { 1300 intel_prepare_page_flip(dev, 0); 1301 if (dev_priv->flip_pending_is_done) 1302 intel_finish_page_flip_plane(dev, 0); 1303 } 1304 1305 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) { 1306 intel_prepare_page_flip(dev, 1); 1307 if (dev_priv->flip_pending_is_done) 1308 intel_finish_page_flip_plane(dev, 1); 1309 } 1310 1311 for_each_pipe(pipe) { 1312 if (pipe_stats[pipe] & vblank_status && 1313 drm_handle_vblank(dev, pipe)) { 1314 vblank++; 1315 if (!dev_priv->flip_pending_is_done) { 1316 i915_pageflip_stall_check(dev, pipe); 1317 intel_finish_page_flip(dev, pipe); 1318 } 1319 } 1320 1321 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) 1322 blc_event = true; 1323 } 1324 1325 1326 if (blc_event || (iir & I915_ASLE_INTERRUPT)) 1327 intel_opregion_asle_intr(dev); 1328 1329 /* With MSI, interrupts are only generated when iir 1330 * transitions from zero to nonzero. If another bit got 1331 * set while we were handling the existing iir bits, then 1332 * we would never get another interrupt. 1333 * 1334 * This is fine on non-MSI as well, as if we hit this path 1335 * we avoid exiting the interrupt handler only to generate 1336 * another one. 1337 * 1338 * Note that for MSI this could cause a stray interrupt report 1339 * if an interrupt landed in the time between writing IIR and 1340 * the posting read. This should be rare enough to never 1341 * trigger the 99% of 100,000 interrupts test for disabling 1342 * stray interrupts. 1343 */ 1344 iir = new_iir; 1345 } 1346 1347 return ret; 1348 } 1349 1350 static int i915_emit_irq(struct drm_device * dev) 1351 { 1352 drm_i915_private_t *dev_priv = dev->dev_private; 1353 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; 1354 1355 i915_kernel_lost_context(dev); 1356 1357 DRM_DEBUG_DRIVER("\n"); 1358 1359 dev_priv->counter++; 1360 if (dev_priv->counter > 0x7FFFFFFFUL) 1361 dev_priv->counter = 1; 1362 if (master_priv->sarea_priv) 1363 master_priv->sarea_priv->last_enqueue = dev_priv->counter; 1364 1365 if (BEGIN_LP_RING(4) == 0) { 1366 OUT_RING(MI_STORE_DWORD_INDEX); 1367 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); 1368 OUT_RING(dev_priv->counter); 1369 OUT_RING(MI_USER_INTERRUPT); 1370 ADVANCE_LP_RING(); 1371 } 1372 1373 return dev_priv->counter; 1374 } 1375 1376 static int i915_wait_irq(struct drm_device * dev, int irq_nr) 1377 { 1378 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1379 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; 1380 int ret = 0; 1381 struct intel_ring_buffer *ring = LP_RING(dev_priv); 1382 1383 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr, 1384 READ_BREADCRUMB(dev_priv)); 1385 1386 if (READ_BREADCRUMB(dev_priv) >= irq_nr) { 1387 if (master_priv->sarea_priv) 1388 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); 1389 return 0; 1390 } 1391 1392 if (master_priv->sarea_priv) 1393 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; 1394 1395 if (ring->irq_get(ring)) { 1396 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ, 1397 READ_BREADCRUMB(dev_priv) >= irq_nr); 1398 ring->irq_put(ring); 1399 } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000)) 1400 ret = -EBUSY; 1401 1402 if (ret == -EBUSY) { 1403 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", 1404 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); 1405 } 1406 1407 return ret; 1408 } 1409 1410 /* Needs the lock as it touches the ring. 1411 */ 1412 int i915_irq_emit(struct drm_device *dev, void *data, 1413 struct drm_file *file_priv) 1414 { 1415 drm_i915_private_t *dev_priv = dev->dev_private; 1416 drm_i915_irq_emit_t *emit = data; 1417 int result; 1418 1419 if (!dev_priv || !LP_RING(dev_priv)->virtual_start) { 1420 DRM_ERROR("called with no initialization\n"); 1421 return -EINVAL; 1422 } 1423 1424 RING_LOCK_TEST_WITH_RETURN(dev, file_priv); 1425 1426 mutex_lock(&dev->struct_mutex); 1427 result = i915_emit_irq(dev); 1428 mutex_unlock(&dev->struct_mutex); 1429 1430 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { 1431 DRM_ERROR("copy_to_user\n"); 1432 return -EFAULT; 1433 } 1434 1435 return 0; 1436 } 1437 1438 /* Doesn't need the hardware lock. 1439 */ 1440 int i915_irq_wait(struct drm_device *dev, void *data, 1441 struct drm_file *file_priv) 1442 { 1443 drm_i915_private_t *dev_priv = dev->dev_private; 1444 drm_i915_irq_wait_t *irqwait = data; 1445 1446 if (!dev_priv) { 1447 DRM_ERROR("called with no initialization\n"); 1448 return -EINVAL; 1449 } 1450 1451 return i915_wait_irq(dev, irqwait->irq_seq); 1452 } 1453 1454 /* Called from drm generic code, passed 'crtc' which 1455 * we use as a pipe index 1456 */ 1457 static int i915_enable_vblank(struct drm_device *dev, int pipe) 1458 { 1459 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1460 unsigned long irqflags; 1461 1462 if (!i915_pipe_enabled(dev, pipe)) 1463 return -EINVAL; 1464 1465 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1466 if (INTEL_INFO(dev)->gen >= 4) 1467 i915_enable_pipestat(dev_priv, pipe, 1468 PIPE_START_VBLANK_INTERRUPT_ENABLE); 1469 else 1470 i915_enable_pipestat(dev_priv, pipe, 1471 PIPE_VBLANK_INTERRUPT_ENABLE); 1472 1473 /* maintain vblank delivery even in deep C-states */ 1474 if (dev_priv->info->gen == 3) 1475 I915_WRITE(INSTPM, INSTPM_AGPBUSY_DIS << 16); 1476 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1477 1478 return 0; 1479 } 1480 1481 static int ironlake_enable_vblank(struct drm_device *dev, int pipe) 1482 { 1483 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1484 unsigned long irqflags; 1485 1486 if (!i915_pipe_enabled(dev, pipe)) 1487 return -EINVAL; 1488 1489 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1490 ironlake_enable_display_irq(dev_priv, (pipe == 0) ? 1491 DE_PIPEA_VBLANK: DE_PIPEB_VBLANK); 1492 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1493 1494 return 0; 1495 } 1496 1497 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe) 1498 { 1499 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1500 unsigned long irqflags; 1501 1502 if (!i915_pipe_enabled(dev, pipe)) 1503 return -EINVAL; 1504 1505 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1506 ironlake_enable_display_irq(dev_priv, (pipe == 0) ? 1507 DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB); 1508 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1509 1510 return 0; 1511 } 1512 1513 /* Called from drm generic code, passed 'crtc' which 1514 * we use as a pipe index 1515 */ 1516 static void i915_disable_vblank(struct drm_device *dev, int pipe) 1517 { 1518 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1519 unsigned long irqflags; 1520 1521 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1522 if (dev_priv->info->gen == 3) 1523 I915_WRITE(INSTPM, 1524 INSTPM_AGPBUSY_DIS << 16 | INSTPM_AGPBUSY_DIS); 1525 1526 i915_disable_pipestat(dev_priv, pipe, 1527 PIPE_VBLANK_INTERRUPT_ENABLE | 1528 PIPE_START_VBLANK_INTERRUPT_ENABLE); 1529 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1530 } 1531 1532 static void ironlake_disable_vblank(struct drm_device *dev, int pipe) 1533 { 1534 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1535 unsigned long irqflags; 1536 1537 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1538 ironlake_disable_display_irq(dev_priv, (pipe == 0) ? 1539 DE_PIPEA_VBLANK: DE_PIPEB_VBLANK); 1540 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1541 } 1542 1543 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe) 1544 { 1545 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1546 unsigned long irqflags; 1547 1548 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1549 ironlake_disable_display_irq(dev_priv, (pipe == 0) ? 1550 DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB); 1551 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1552 } 1553 1554 /* Set the vblank monitor pipe 1555 */ 1556 int i915_vblank_pipe_set(struct drm_device *dev, void *data, 1557 struct drm_file *file_priv) 1558 { 1559 drm_i915_private_t *dev_priv = dev->dev_private; 1560 1561 if (!dev_priv) { 1562 DRM_ERROR("called with no initialization\n"); 1563 return -EINVAL; 1564 } 1565 1566 return 0; 1567 } 1568 1569 int i915_vblank_pipe_get(struct drm_device *dev, void *data, 1570 struct drm_file *file_priv) 1571 { 1572 drm_i915_private_t *dev_priv = dev->dev_private; 1573 drm_i915_vblank_pipe_t *pipe = data; 1574 1575 if (!dev_priv) { 1576 DRM_ERROR("called with no initialization\n"); 1577 return -EINVAL; 1578 } 1579 1580 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; 1581 1582 return 0; 1583 } 1584 1585 /** 1586 * Schedule buffer swap at given vertical blank. 1587 */ 1588 int i915_vblank_swap(struct drm_device *dev, void *data, 1589 struct drm_file *file_priv) 1590 { 1591 /* The delayed swap mechanism was fundamentally racy, and has been 1592 * removed. The model was that the client requested a delayed flip/swap 1593 * from the kernel, then waited for vblank before continuing to perform 1594 * rendering. The problem was that the kernel might wake the client 1595 * up before it dispatched the vblank swap (since the lock has to be 1596 * held while touching the ringbuffer), in which case the client would 1597 * clear and start the next frame before the swap occurred, and 1598 * flicker would occur in addition to likely missing the vblank. 1599 * 1600 * In the absence of this ioctl, userland falls back to a correct path 1601 * of waiting for a vblank, then dispatching the swap on its own. 1602 * Context switching to userland and back is plenty fast enough for 1603 * meeting the requirements of vblank swapping. 1604 */ 1605 return -EINVAL; 1606 } 1607 1608 static u32 1609 ring_last_seqno(struct intel_ring_buffer *ring) 1610 { 1611 return list_entry(ring->request_list.prev, 1612 struct drm_i915_gem_request, list)->seqno; 1613 } 1614 1615 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err) 1616 { 1617 if (list_empty(&ring->request_list) || 1618 i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) { 1619 /* Issue a wake-up to catch stuck h/w. */ 1620 if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) { 1621 DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n", 1622 ring->name, 1623 ring->waiting_seqno, 1624 ring->get_seqno(ring)); 1625 wake_up_all(&ring->irq_queue); 1626 *err = true; 1627 } 1628 return true; 1629 } 1630 return false; 1631 } 1632 1633 static bool kick_ring(struct intel_ring_buffer *ring) 1634 { 1635 struct drm_device *dev = ring->dev; 1636 struct drm_i915_private *dev_priv = dev->dev_private; 1637 u32 tmp = I915_READ_CTL(ring); 1638 if (tmp & RING_WAIT) { 1639 DRM_ERROR("Kicking stuck wait on %s\n", 1640 ring->name); 1641 I915_WRITE_CTL(ring, tmp); 1642 return true; 1643 } 1644 if (IS_GEN6(dev) && 1645 (tmp & RING_WAIT_SEMAPHORE)) { 1646 DRM_ERROR("Kicking stuck semaphore on %s\n", 1647 ring->name); 1648 I915_WRITE_CTL(ring, tmp); 1649 return true; 1650 } 1651 return false; 1652 } 1653 1654 /** 1655 * This is called when the chip hasn't reported back with completed 1656 * batchbuffers in a long time. The first time this is called we simply record 1657 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses 1658 * again, we assume the chip is wedged and try to fix it. 1659 */ 1660 void i915_hangcheck_elapsed(unsigned long data) 1661 { 1662 struct drm_device *dev = (struct drm_device *)data; 1663 drm_i915_private_t *dev_priv = dev->dev_private; 1664 uint32_t acthd, instdone, instdone1; 1665 bool err = false; 1666 1667 /* If all work is done then ACTHD clearly hasn't advanced. */ 1668 if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) && 1669 i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) && 1670 i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) { 1671 dev_priv->hangcheck_count = 0; 1672 if (err) 1673 goto repeat; 1674 return; 1675 } 1676 1677 if (INTEL_INFO(dev)->gen < 4) { 1678 acthd = I915_READ(ACTHD); 1679 instdone = I915_READ(INSTDONE); 1680 instdone1 = 0; 1681 } else { 1682 acthd = I915_READ(ACTHD_I965); 1683 instdone = I915_READ(INSTDONE_I965); 1684 instdone1 = I915_READ(INSTDONE1); 1685 } 1686 1687 if (dev_priv->last_acthd == acthd && 1688 dev_priv->last_instdone == instdone && 1689 dev_priv->last_instdone1 == instdone1) { 1690 if (dev_priv->hangcheck_count++ > 1) { 1691 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n"); 1692 1693 if (!IS_GEN2(dev)) { 1694 /* Is the chip hanging on a WAIT_FOR_EVENT? 1695 * If so we can simply poke the RB_WAIT bit 1696 * and break the hang. This should work on 1697 * all but the second generation chipsets. 1698 */ 1699 1700 if (kick_ring(&dev_priv->ring[RCS])) 1701 goto repeat; 1702 1703 if (HAS_BSD(dev) && 1704 kick_ring(&dev_priv->ring[VCS])) 1705 goto repeat; 1706 1707 if (HAS_BLT(dev) && 1708 kick_ring(&dev_priv->ring[BCS])) 1709 goto repeat; 1710 } 1711 1712 i915_handle_error(dev, true); 1713 return; 1714 } 1715 } else { 1716 dev_priv->hangcheck_count = 0; 1717 1718 dev_priv->last_acthd = acthd; 1719 dev_priv->last_instdone = instdone; 1720 dev_priv->last_instdone1 = instdone1; 1721 } 1722 1723 repeat: 1724 /* Reset timer case chip hangs without another request being added */ 1725 mod_timer(&dev_priv->hangcheck_timer, 1726 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); 1727 } 1728 1729 /* drm_dma.h hooks 1730 */ 1731 static void ironlake_irq_preinstall(struct drm_device *dev) 1732 { 1733 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1734 1735 atomic_set(&dev_priv->irq_received, 0); 1736 1737 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); 1738 INIT_WORK(&dev_priv->error_work, i915_error_work_func); 1739 if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) 1740 INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work); 1741 1742 I915_WRITE(HWSTAM, 0xeffe); 1743 if (IS_GEN6(dev) || IS_GEN7(dev)) { 1744 /* Workaround stalls observed on Sandy Bridge GPUs by 1745 * making the blitter command streamer generate a 1746 * write to the Hardware Status Page for 1747 * MI_USER_INTERRUPT. This appears to serialize the 1748 * previous seqno write out before the interrupt 1749 * happens. 1750 */ 1751 I915_WRITE(GEN6_BLITTER_HWSTAM, ~GEN6_BLITTER_USER_INTERRUPT); 1752 I915_WRITE(GEN6_BSD_HWSTAM, ~GEN6_BSD_USER_INTERRUPT); 1753 } 1754 1755 /* XXX hotplug from PCH */ 1756 1757 I915_WRITE(DEIMR, 0xffffffff); 1758 I915_WRITE(DEIER, 0x0); 1759 POSTING_READ(DEIER); 1760 1761 /* and GT */ 1762 I915_WRITE(GTIMR, 0xffffffff); 1763 I915_WRITE(GTIER, 0x0); 1764 POSTING_READ(GTIER); 1765 1766 /* south display irq */ 1767 I915_WRITE(SDEIMR, 0xffffffff); 1768 I915_WRITE(SDEIER, 0x0); 1769 POSTING_READ(SDEIER); 1770 } 1771 1772 static int ironlake_irq_postinstall(struct drm_device *dev) 1773 { 1774 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1775 /* enable kind of interrupts always enabled */ 1776 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | 1777 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE; 1778 u32 render_irqs; 1779 u32 hotplug_mask; 1780 1781 DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue); 1782 if (HAS_BSD(dev)) 1783 DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue); 1784 if (HAS_BLT(dev)) 1785 DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue); 1786 1787 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; 1788 dev_priv->irq_mask = ~display_mask; 1789 1790 /* should always can generate irq */ 1791 I915_WRITE(DEIIR, I915_READ(DEIIR)); 1792 I915_WRITE(DEIMR, dev_priv->irq_mask); 1793 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK); 1794 POSTING_READ(DEIER); 1795 1796 dev_priv->gt_irq_mask = ~0; 1797 1798 I915_WRITE(GTIIR, I915_READ(GTIIR)); 1799 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); 1800 1801 if (IS_GEN6(dev)) 1802 render_irqs = 1803 GT_USER_INTERRUPT | 1804 GT_GEN6_BSD_USER_INTERRUPT | 1805 GT_BLT_USER_INTERRUPT; 1806 else 1807 render_irqs = 1808 GT_USER_INTERRUPT | 1809 GT_PIPE_NOTIFY | 1810 GT_BSD_USER_INTERRUPT; 1811 I915_WRITE(GTIER, render_irqs); 1812 POSTING_READ(GTIER); 1813 1814 if (HAS_PCH_CPT(dev)) { 1815 hotplug_mask = (SDE_CRT_HOTPLUG_CPT | 1816 SDE_PORTB_HOTPLUG_CPT | 1817 SDE_PORTC_HOTPLUG_CPT | 1818 SDE_PORTD_HOTPLUG_CPT); 1819 } else { 1820 hotplug_mask = (SDE_CRT_HOTPLUG | 1821 SDE_PORTB_HOTPLUG | 1822 SDE_PORTC_HOTPLUG | 1823 SDE_PORTD_HOTPLUG | 1824 SDE_AUX_MASK); 1825 } 1826 1827 dev_priv->pch_irq_mask = ~hotplug_mask; 1828 1829 I915_WRITE(SDEIIR, I915_READ(SDEIIR)); 1830 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask); 1831 I915_WRITE(SDEIER, hotplug_mask); 1832 POSTING_READ(SDEIER); 1833 1834 if (IS_IRONLAKE_M(dev)) { 1835 /* Clear & enable PCU event interrupts */ 1836 I915_WRITE(DEIIR, DE_PCU_EVENT); 1837 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT); 1838 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); 1839 } 1840 1841 return 0; 1842 } 1843 1844 static int ivybridge_irq_postinstall(struct drm_device *dev) 1845 { 1846 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1847 /* enable kind of interrupts always enabled */ 1848 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | 1849 DE_PCH_EVENT_IVB | DE_PLANEA_FLIP_DONE_IVB | 1850 DE_PLANEB_FLIP_DONE_IVB; 1851 u32 render_irqs; 1852 u32 hotplug_mask; 1853 1854 DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue); 1855 if (HAS_BSD(dev)) 1856 DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue); 1857 if (HAS_BLT(dev)) 1858 DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue); 1859 1860 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; 1861 dev_priv->irq_mask = ~display_mask; 1862 1863 /* should always can generate irq */ 1864 I915_WRITE(DEIIR, I915_READ(DEIIR)); 1865 I915_WRITE(DEIMR, dev_priv->irq_mask); 1866 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK_IVB | 1867 DE_PIPEB_VBLANK_IVB); 1868 POSTING_READ(DEIER); 1869 1870 dev_priv->gt_irq_mask = ~0; 1871 1872 I915_WRITE(GTIIR, I915_READ(GTIIR)); 1873 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); 1874 1875 render_irqs = GT_USER_INTERRUPT | GT_GEN6_BSD_USER_INTERRUPT | 1876 GT_BLT_USER_INTERRUPT; 1877 I915_WRITE(GTIER, render_irqs); 1878 POSTING_READ(GTIER); 1879 1880 hotplug_mask = (SDE_CRT_HOTPLUG_CPT | 1881 SDE_PORTB_HOTPLUG_CPT | 1882 SDE_PORTC_HOTPLUG_CPT | 1883 SDE_PORTD_HOTPLUG_CPT); 1884 dev_priv->pch_irq_mask = ~hotplug_mask; 1885 1886 I915_WRITE(SDEIIR, I915_READ(SDEIIR)); 1887 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask); 1888 I915_WRITE(SDEIER, hotplug_mask); 1889 POSTING_READ(SDEIER); 1890 1891 return 0; 1892 } 1893 1894 static void i915_driver_irq_preinstall(struct drm_device * dev) 1895 { 1896 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1897 int pipe; 1898 1899 atomic_set(&dev_priv->irq_received, 0); 1900 1901 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); 1902 INIT_WORK(&dev_priv->error_work, i915_error_work_func); 1903 1904 if (I915_HAS_HOTPLUG(dev)) { 1905 I915_WRITE(PORT_HOTPLUG_EN, 0); 1906 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 1907 } 1908 1909 I915_WRITE(HWSTAM, 0xeffe); 1910 for_each_pipe(pipe) 1911 I915_WRITE(PIPESTAT(pipe), 0); 1912 I915_WRITE(IMR, 0xffffffff); 1913 I915_WRITE(IER, 0x0); 1914 POSTING_READ(IER); 1915 } 1916 1917 /* 1918 * Must be called after intel_modeset_init or hotplug interrupts won't be 1919 * enabled correctly. 1920 */ 1921 static int i915_driver_irq_postinstall(struct drm_device *dev) 1922 { 1923 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1924 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR; 1925 u32 error_mask; 1926 1927 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; 1928 1929 /* Unmask the interrupts that we always want on. */ 1930 dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX; 1931 1932 dev_priv->pipestat[0] = 0; 1933 dev_priv->pipestat[1] = 0; 1934 1935 if (I915_HAS_HOTPLUG(dev)) { 1936 /* Enable in IER... */ 1937 enable_mask |= I915_DISPLAY_PORT_INTERRUPT; 1938 /* and unmask in IMR */ 1939 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; 1940 } 1941 1942 /* 1943 * Enable some error detection, note the instruction error mask 1944 * bit is reserved, so we leave it masked. 1945 */ 1946 if (IS_G4X(dev)) { 1947 error_mask = ~(GM45_ERROR_PAGE_TABLE | 1948 GM45_ERROR_MEM_PRIV | 1949 GM45_ERROR_CP_PRIV | 1950 I915_ERROR_MEMORY_REFRESH); 1951 } else { 1952 error_mask = ~(I915_ERROR_PAGE_TABLE | 1953 I915_ERROR_MEMORY_REFRESH); 1954 } 1955 I915_WRITE(EMR, error_mask); 1956 1957 I915_WRITE(IMR, dev_priv->irq_mask); 1958 I915_WRITE(IER, enable_mask); 1959 POSTING_READ(IER); 1960 1961 if (I915_HAS_HOTPLUG(dev)) { 1962 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); 1963 1964 /* Note HDMI and DP share bits */ 1965 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) 1966 hotplug_en |= HDMIB_HOTPLUG_INT_EN; 1967 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) 1968 hotplug_en |= HDMIC_HOTPLUG_INT_EN; 1969 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) 1970 hotplug_en |= HDMID_HOTPLUG_INT_EN; 1971 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS) 1972 hotplug_en |= SDVOC_HOTPLUG_INT_EN; 1973 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS) 1974 hotplug_en |= SDVOB_HOTPLUG_INT_EN; 1975 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) { 1976 hotplug_en |= CRT_HOTPLUG_INT_EN; 1977 1978 /* Programming the CRT detection parameters tends 1979 to generate a spurious hotplug event about three 1980 seconds later. So just do it once. 1981 */ 1982 if (IS_G4X(dev)) 1983 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; 1984 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; 1985 } 1986 1987 /* Ignore TV since it's buggy */ 1988 1989 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); 1990 } 1991 1992 intel_opregion_enable_asle(dev); 1993 1994 return 0; 1995 } 1996 1997 static void ironlake_irq_uninstall(struct drm_device *dev) 1998 { 1999 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2000 2001 if (!dev_priv) 2002 return; 2003 2004 dev_priv->vblank_pipe = 0; 2005 2006 I915_WRITE(HWSTAM, 0xffffffff); 2007 2008 I915_WRITE(DEIMR, 0xffffffff); 2009 I915_WRITE(DEIER, 0x0); 2010 I915_WRITE(DEIIR, I915_READ(DEIIR)); 2011 2012 I915_WRITE(GTIMR, 0xffffffff); 2013 I915_WRITE(GTIER, 0x0); 2014 I915_WRITE(GTIIR, I915_READ(GTIIR)); 2015 } 2016 2017 static void i915_driver_irq_uninstall(struct drm_device * dev) 2018 { 2019 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2020 int pipe; 2021 2022 if (!dev_priv) 2023 return; 2024 2025 dev_priv->vblank_pipe = 0; 2026 2027 if (I915_HAS_HOTPLUG(dev)) { 2028 I915_WRITE(PORT_HOTPLUG_EN, 0); 2029 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 2030 } 2031 2032 I915_WRITE(HWSTAM, 0xffffffff); 2033 for_each_pipe(pipe) 2034 I915_WRITE(PIPESTAT(pipe), 0); 2035 I915_WRITE(IMR, 0xffffffff); 2036 I915_WRITE(IER, 0x0); 2037 2038 for_each_pipe(pipe) 2039 I915_WRITE(PIPESTAT(pipe), 2040 I915_READ(PIPESTAT(pipe)) & 0x8000ffff); 2041 I915_WRITE(IIR, I915_READ(IIR)); 2042 } 2043 2044 void intel_irq_init(struct drm_device *dev) 2045 { 2046 dev->driver->get_vblank_counter = i915_get_vblank_counter; 2047 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ 2048 if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) { 2049 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ 2050 dev->driver->get_vblank_counter = gm45_get_vblank_counter; 2051 } 2052 2053 2054 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; 2055 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; 2056 2057 if (IS_IVYBRIDGE(dev)) { 2058 /* Share pre & uninstall handlers with ILK/SNB */ 2059 dev->driver->irq_handler = ivybridge_irq_handler; 2060 dev->driver->irq_preinstall = ironlake_irq_preinstall; 2061 dev->driver->irq_postinstall = ivybridge_irq_postinstall; 2062 dev->driver->irq_uninstall = ironlake_irq_uninstall; 2063 dev->driver->enable_vblank = ivybridge_enable_vblank; 2064 dev->driver->disable_vblank = ivybridge_disable_vblank; 2065 } else if (HAS_PCH_SPLIT(dev)) { 2066 dev->driver->irq_handler = ironlake_irq_handler; 2067 dev->driver->irq_preinstall = ironlake_irq_preinstall; 2068 dev->driver->irq_postinstall = ironlake_irq_postinstall; 2069 dev->driver->irq_uninstall = ironlake_irq_uninstall; 2070 dev->driver->enable_vblank = ironlake_enable_vblank; 2071 dev->driver->disable_vblank = ironlake_disable_vblank; 2072 } else { 2073 dev->driver->irq_preinstall = i915_driver_irq_preinstall; 2074 dev->driver->irq_postinstall = i915_driver_irq_postinstall; 2075 dev->driver->irq_uninstall = i915_driver_irq_uninstall; 2076 dev->driver->irq_handler = i915_driver_irq_handler; 2077 dev->driver->enable_vblank = i915_enable_vblank; 2078 dev->driver->disable_vblank = i915_disable_vblank; 2079 } 2080 } 2081