1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- 2 */ 3 /* 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation the rights to use, copy, modify, merge, publish, 11 * distribute, sub license, and/or sell copies of the Software, and to 12 * permit persons to whom the Software is furnished to do so, subject to 13 * the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial portions 17 * of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 26 * 27 */ 28 29 #include <linux/sysrq.h> 30 #include <linux/slab.h> 31 #include "drmP.h" 32 #include "drm.h" 33 #include "i915_drm.h" 34 #include "i915_drv.h" 35 #include "i915_trace.h" 36 #include "intel_drv.h" 37 38 #define MAX_NOPID ((u32)~0) 39 40 /** 41 * Interrupts that are always left unmasked. 42 * 43 * Since pipe events are edge-triggered from the PIPESTAT register to IIR, 44 * we leave them always unmasked in IMR and then control enabling them through 45 * PIPESTAT alone. 46 */ 47 #define I915_INTERRUPT_ENABLE_FIX \ 48 (I915_ASLE_INTERRUPT | \ 49 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ 50 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \ 51 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \ 52 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \ 53 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) 54 55 /** Interrupts that we mask and unmask at runtime. */ 56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT) 57 58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\ 59 PIPE_VBLANK_INTERRUPT_STATUS) 60 61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\ 62 PIPE_VBLANK_INTERRUPT_ENABLE) 63 64 #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \ 65 DRM_I915_VBLANK_PIPE_B) 66 67 /* For display hotplug interrupt */ 68 static void 69 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) 70 { 71 if ((dev_priv->irq_mask & mask) != 0) { 72 dev_priv->irq_mask &= ~mask; 73 I915_WRITE(DEIMR, dev_priv->irq_mask); 74 POSTING_READ(DEIMR); 75 } 76 } 77 78 static inline void 79 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) 80 { 81 if ((dev_priv->irq_mask & mask) != mask) { 82 dev_priv->irq_mask |= mask; 83 I915_WRITE(DEIMR, dev_priv->irq_mask); 84 POSTING_READ(DEIMR); 85 } 86 } 87 88 void 89 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) 90 { 91 if ((dev_priv->pipestat[pipe] & mask) != mask) { 92 u32 reg = PIPESTAT(pipe); 93 94 dev_priv->pipestat[pipe] |= mask; 95 /* Enable the interrupt, clear any pending status */ 96 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); 97 POSTING_READ(reg); 98 } 99 } 100 101 void 102 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) 103 { 104 if ((dev_priv->pipestat[pipe] & mask) != 0) { 105 u32 reg = PIPESTAT(pipe); 106 107 dev_priv->pipestat[pipe] &= ~mask; 108 I915_WRITE(reg, dev_priv->pipestat[pipe]); 109 POSTING_READ(reg); 110 } 111 } 112 113 /** 114 * intel_enable_asle - enable ASLE interrupt for OpRegion 115 */ 116 void intel_enable_asle(struct drm_device *dev) 117 { 118 drm_i915_private_t *dev_priv = dev->dev_private; 119 unsigned long irqflags; 120 121 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 122 123 if (HAS_PCH_SPLIT(dev)) 124 ironlake_enable_display_irq(dev_priv, DE_GSE); 125 else { 126 i915_enable_pipestat(dev_priv, 1, 127 PIPE_LEGACY_BLC_EVENT_ENABLE); 128 if (INTEL_INFO(dev)->gen >= 4) 129 i915_enable_pipestat(dev_priv, 0, 130 PIPE_LEGACY_BLC_EVENT_ENABLE); 131 } 132 133 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 134 } 135 136 /** 137 * i915_pipe_enabled - check if a pipe is enabled 138 * @dev: DRM device 139 * @pipe: pipe to check 140 * 141 * Reading certain registers when the pipe is disabled can hang the chip. 142 * Use this routine to make sure the PLL is running and the pipe is active 143 * before reading such registers if unsure. 144 */ 145 static int 146 i915_pipe_enabled(struct drm_device *dev, int pipe) 147 { 148 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 149 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; 150 } 151 152 /* Called from drm generic code, passed a 'crtc', which 153 * we use as a pipe index 154 */ 155 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) 156 { 157 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 158 unsigned long high_frame; 159 unsigned long low_frame; 160 u32 high1, high2, low; 161 162 if (!i915_pipe_enabled(dev, pipe)) { 163 DRM_DEBUG_DRIVER("trying to get vblank count for disabled " 164 "pipe %c\n", pipe_name(pipe)); 165 return 0; 166 } 167 168 high_frame = PIPEFRAME(pipe); 169 low_frame = PIPEFRAMEPIXEL(pipe); 170 171 /* 172 * High & low register fields aren't synchronized, so make sure 173 * we get a low value that's stable across two reads of the high 174 * register. 175 */ 176 do { 177 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; 178 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK; 179 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; 180 } while (high1 != high2); 181 182 high1 >>= PIPE_FRAME_HIGH_SHIFT; 183 low >>= PIPE_FRAME_LOW_SHIFT; 184 return (high1 << 8) | low; 185 } 186 187 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) 188 { 189 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 190 int reg = PIPE_FRMCOUNT_GM45(pipe); 191 192 if (!i915_pipe_enabled(dev, pipe)) { 193 DRM_DEBUG_DRIVER("trying to get vblank count for disabled " 194 "pipe %c\n", pipe_name(pipe)); 195 return 0; 196 } 197 198 return I915_READ(reg); 199 } 200 201 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, 202 int *vpos, int *hpos) 203 { 204 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 205 u32 vbl = 0, position = 0; 206 int vbl_start, vbl_end, htotal, vtotal; 207 bool in_vbl = true; 208 int ret = 0; 209 210 if (!i915_pipe_enabled(dev, pipe)) { 211 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " 212 "pipe %c\n", pipe_name(pipe)); 213 return 0; 214 } 215 216 /* Get vtotal. */ 217 vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff); 218 219 if (INTEL_INFO(dev)->gen >= 4) { 220 /* No obvious pixelcount register. Only query vertical 221 * scanout position from Display scan line register. 222 */ 223 position = I915_READ(PIPEDSL(pipe)); 224 225 /* Decode into vertical scanout position. Don't have 226 * horizontal scanout position. 227 */ 228 *vpos = position & 0x1fff; 229 *hpos = 0; 230 } else { 231 /* Have access to pixelcount since start of frame. 232 * We can split this into vertical and horizontal 233 * scanout position. 234 */ 235 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; 236 237 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff); 238 *vpos = position / htotal; 239 *hpos = position - (*vpos * htotal); 240 } 241 242 /* Query vblank area. */ 243 vbl = I915_READ(VBLANK(pipe)); 244 245 /* Test position against vblank region. */ 246 vbl_start = vbl & 0x1fff; 247 vbl_end = (vbl >> 16) & 0x1fff; 248 249 if ((*vpos < vbl_start) || (*vpos > vbl_end)) 250 in_vbl = false; 251 252 /* Inside "upper part" of vblank area? Apply corrective offset: */ 253 if (in_vbl && (*vpos >= vbl_start)) 254 *vpos = *vpos - vtotal; 255 256 /* Readouts valid? */ 257 if (vbl > 0) 258 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; 259 260 /* In vblank? */ 261 if (in_vbl) 262 ret |= DRM_SCANOUTPOS_INVBL; 263 264 return ret; 265 } 266 267 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, 268 int *max_error, 269 struct timeval *vblank_time, 270 unsigned flags) 271 { 272 struct drm_i915_private *dev_priv = dev->dev_private; 273 struct drm_crtc *crtc; 274 275 if (pipe < 0 || pipe >= dev_priv->num_pipe) { 276 DRM_ERROR("Invalid crtc %d\n", pipe); 277 return -EINVAL; 278 } 279 280 /* Get drm_crtc to timestamp: */ 281 crtc = intel_get_crtc_for_pipe(dev, pipe); 282 if (crtc == NULL) { 283 DRM_ERROR("Invalid crtc %d\n", pipe); 284 return -EINVAL; 285 } 286 287 if (!crtc->enabled) { 288 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); 289 return -EBUSY; 290 } 291 292 /* Helper routine in DRM core does all the work: */ 293 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, 294 vblank_time, flags, 295 crtc); 296 } 297 298 /* 299 * Handle hotplug events outside the interrupt handler proper. 300 */ 301 static void i915_hotplug_work_func(struct work_struct *work) 302 { 303 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, 304 hotplug_work); 305 struct drm_device *dev = dev_priv->dev; 306 struct drm_mode_config *mode_config = &dev->mode_config; 307 struct intel_encoder *encoder; 308 309 mutex_lock(&mode_config->mutex); 310 DRM_DEBUG_KMS("running encoder hotplug functions\n"); 311 312 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) 313 if (encoder->hot_plug) 314 encoder->hot_plug(encoder); 315 316 mutex_unlock(&mode_config->mutex); 317 318 /* Just fire off a uevent and let userspace tell us what to do */ 319 drm_helper_hpd_irq_event(dev); 320 } 321 322 static void i915_handle_rps_change(struct drm_device *dev) 323 { 324 drm_i915_private_t *dev_priv = dev->dev_private; 325 u32 busy_up, busy_down, max_avg, min_avg; 326 u8 new_delay = dev_priv->cur_delay; 327 328 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); 329 busy_up = I915_READ(RCPREVBSYTUPAVG); 330 busy_down = I915_READ(RCPREVBSYTDNAVG); 331 max_avg = I915_READ(RCBMAXAVG); 332 min_avg = I915_READ(RCBMINAVG); 333 334 /* Handle RCS change request from hw */ 335 if (busy_up > max_avg) { 336 if (dev_priv->cur_delay != dev_priv->max_delay) 337 new_delay = dev_priv->cur_delay - 1; 338 if (new_delay < dev_priv->max_delay) 339 new_delay = dev_priv->max_delay; 340 } else if (busy_down < min_avg) { 341 if (dev_priv->cur_delay != dev_priv->min_delay) 342 new_delay = dev_priv->cur_delay + 1; 343 if (new_delay > dev_priv->min_delay) 344 new_delay = dev_priv->min_delay; 345 } 346 347 if (ironlake_set_drps(dev, new_delay)) 348 dev_priv->cur_delay = new_delay; 349 350 return; 351 } 352 353 static void notify_ring(struct drm_device *dev, 354 struct intel_ring_buffer *ring) 355 { 356 struct drm_i915_private *dev_priv = dev->dev_private; 357 u32 seqno; 358 359 if (ring->obj == NULL) 360 return; 361 362 seqno = ring->get_seqno(ring); 363 trace_i915_gem_request_complete(ring, seqno); 364 365 ring->irq_seqno = seqno; 366 wake_up_all(&ring->irq_queue); 367 if (i915_enable_hangcheck) { 368 dev_priv->hangcheck_count = 0; 369 mod_timer(&dev_priv->hangcheck_timer, 370 jiffies + 371 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); 372 } 373 } 374 375 static void gen6_pm_rps_work(struct work_struct *work) 376 { 377 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, 378 rps_work); 379 u8 new_delay = dev_priv->cur_delay; 380 u32 pm_iir, pm_imr; 381 382 spin_lock_irq(&dev_priv->rps_lock); 383 pm_iir = dev_priv->pm_iir; 384 dev_priv->pm_iir = 0; 385 pm_imr = I915_READ(GEN6_PMIMR); 386 I915_WRITE(GEN6_PMIMR, 0); 387 spin_unlock_irq(&dev_priv->rps_lock); 388 389 if (!pm_iir) 390 return; 391 392 mutex_lock(&dev_priv->dev->struct_mutex); 393 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { 394 if (dev_priv->cur_delay != dev_priv->max_delay) 395 new_delay = dev_priv->cur_delay + 1; 396 if (new_delay > dev_priv->max_delay) 397 new_delay = dev_priv->max_delay; 398 } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) { 399 gen6_gt_force_wake_get(dev_priv); 400 if (dev_priv->cur_delay != dev_priv->min_delay) 401 new_delay = dev_priv->cur_delay - 1; 402 if (new_delay < dev_priv->min_delay) { 403 new_delay = dev_priv->min_delay; 404 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 405 I915_READ(GEN6_RP_INTERRUPT_LIMITS) | 406 ((new_delay << 16) & 0x3f0000)); 407 } else { 408 /* Make sure we continue to get down interrupts 409 * until we hit the minimum frequency */ 410 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 411 I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000); 412 } 413 gen6_gt_force_wake_put(dev_priv); 414 } 415 416 gen6_set_rps(dev_priv->dev, new_delay); 417 dev_priv->cur_delay = new_delay; 418 419 /* 420 * rps_lock not held here because clearing is non-destructive. There is 421 * an *extremely* unlikely race with gen6_rps_enable() that is prevented 422 * by holding struct_mutex for the duration of the write. 423 */ 424 mutex_unlock(&dev_priv->dev->struct_mutex); 425 } 426 427 static void pch_irq_handler(struct drm_device *dev) 428 { 429 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 430 u32 pch_iir; 431 int pipe; 432 433 pch_iir = I915_READ(SDEIIR); 434 435 if (pch_iir & SDE_AUDIO_POWER_MASK) 436 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", 437 (pch_iir & SDE_AUDIO_POWER_MASK) >> 438 SDE_AUDIO_POWER_SHIFT); 439 440 if (pch_iir & SDE_GMBUS) 441 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n"); 442 443 if (pch_iir & SDE_AUDIO_HDCP_MASK) 444 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); 445 446 if (pch_iir & SDE_AUDIO_TRANS_MASK) 447 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); 448 449 if (pch_iir & SDE_POISON) 450 DRM_ERROR("PCH poison interrupt\n"); 451 452 if (pch_iir & SDE_FDI_MASK) 453 for_each_pipe(pipe) 454 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", 455 pipe_name(pipe), 456 I915_READ(FDI_RX_IIR(pipe))); 457 458 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) 459 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); 460 461 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) 462 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); 463 464 if (pch_iir & SDE_TRANSB_FIFO_UNDER) 465 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n"); 466 if (pch_iir & SDE_TRANSA_FIFO_UNDER) 467 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n"); 468 } 469 470 static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS) 471 { 472 struct drm_device *dev = (struct drm_device *) arg; 473 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 474 int ret = IRQ_NONE; 475 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir; 476 struct drm_i915_master_private *master_priv; 477 478 atomic_inc(&dev_priv->irq_received); 479 480 /* disable master interrupt before clearing iir */ 481 de_ier = I915_READ(DEIER); 482 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); 483 POSTING_READ(DEIER); 484 485 de_iir = I915_READ(DEIIR); 486 gt_iir = I915_READ(GTIIR); 487 pch_iir = I915_READ(SDEIIR); 488 pm_iir = I915_READ(GEN6_PMIIR); 489 490 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && pm_iir == 0) 491 goto done; 492 493 ret = IRQ_HANDLED; 494 495 if (dev->primary->master) { 496 master_priv = dev->primary->master->driver_priv; 497 if (master_priv->sarea_priv) 498 master_priv->sarea_priv->last_dispatch = 499 READ_BREADCRUMB(dev_priv); 500 } 501 502 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY)) 503 notify_ring(dev, &dev_priv->ring[RCS]); 504 if (gt_iir & GT_GEN6_BSD_USER_INTERRUPT) 505 notify_ring(dev, &dev_priv->ring[VCS]); 506 if (gt_iir & GT_BLT_USER_INTERRUPT) 507 notify_ring(dev, &dev_priv->ring[BCS]); 508 509 if (de_iir & DE_GSE_IVB) 510 intel_opregion_gse_intr(dev); 511 512 if (de_iir & DE_PLANEA_FLIP_DONE_IVB) { 513 intel_prepare_page_flip(dev, 0); 514 intel_finish_page_flip_plane(dev, 0); 515 } 516 517 if (de_iir & DE_PLANEB_FLIP_DONE_IVB) { 518 intel_prepare_page_flip(dev, 1); 519 intel_finish_page_flip_plane(dev, 1); 520 } 521 522 if (de_iir & DE_PIPEA_VBLANK_IVB) 523 drm_handle_vblank(dev, 0); 524 525 if (de_iir & DE_PIPEB_VBLANK_IVB) 526 drm_handle_vblank(dev, 1); 527 528 /* check event from PCH */ 529 if (de_iir & DE_PCH_EVENT_IVB) { 530 if (pch_iir & SDE_HOTPLUG_MASK_CPT) 531 queue_work(dev_priv->wq, &dev_priv->hotplug_work); 532 pch_irq_handler(dev); 533 } 534 535 if (pm_iir & GEN6_PM_DEFERRED_EVENTS) { 536 unsigned long flags; 537 spin_lock_irqsave(&dev_priv->rps_lock, flags); 538 WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n"); 539 dev_priv->pm_iir |= pm_iir; 540 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir); 541 POSTING_READ(GEN6_PMIMR); 542 spin_unlock_irqrestore(&dev_priv->rps_lock, flags); 543 queue_work(dev_priv->wq, &dev_priv->rps_work); 544 } 545 546 /* should clear PCH hotplug event before clear CPU irq */ 547 I915_WRITE(SDEIIR, pch_iir); 548 I915_WRITE(GTIIR, gt_iir); 549 I915_WRITE(DEIIR, de_iir); 550 I915_WRITE(GEN6_PMIIR, pm_iir); 551 552 done: 553 I915_WRITE(DEIER, de_ier); 554 POSTING_READ(DEIER); 555 556 return ret; 557 } 558 559 static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS) 560 { 561 struct drm_device *dev = (struct drm_device *) arg; 562 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 563 int ret = IRQ_NONE; 564 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir; 565 u32 hotplug_mask; 566 struct drm_i915_master_private *master_priv; 567 u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT; 568 569 atomic_inc(&dev_priv->irq_received); 570 571 if (IS_GEN6(dev)) 572 bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT; 573 574 /* disable master interrupt before clearing iir */ 575 de_ier = I915_READ(DEIER); 576 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); 577 POSTING_READ(DEIER); 578 579 de_iir = I915_READ(DEIIR); 580 gt_iir = I915_READ(GTIIR); 581 pch_iir = I915_READ(SDEIIR); 582 pm_iir = I915_READ(GEN6_PMIIR); 583 584 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && 585 (!IS_GEN6(dev) || pm_iir == 0)) 586 goto done; 587 588 if (HAS_PCH_CPT(dev)) 589 hotplug_mask = SDE_HOTPLUG_MASK_CPT; 590 else 591 hotplug_mask = SDE_HOTPLUG_MASK; 592 593 ret = IRQ_HANDLED; 594 595 if (dev->primary->master) { 596 master_priv = dev->primary->master->driver_priv; 597 if (master_priv->sarea_priv) 598 master_priv->sarea_priv->last_dispatch = 599 READ_BREADCRUMB(dev_priv); 600 } 601 602 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY)) 603 notify_ring(dev, &dev_priv->ring[RCS]); 604 if (gt_iir & bsd_usr_interrupt) 605 notify_ring(dev, &dev_priv->ring[VCS]); 606 if (gt_iir & GT_BLT_USER_INTERRUPT) 607 notify_ring(dev, &dev_priv->ring[BCS]); 608 609 if (de_iir & DE_GSE) 610 intel_opregion_gse_intr(dev); 611 612 if (de_iir & DE_PLANEA_FLIP_DONE) { 613 intel_prepare_page_flip(dev, 0); 614 intel_finish_page_flip_plane(dev, 0); 615 } 616 617 if (de_iir & DE_PLANEB_FLIP_DONE) { 618 intel_prepare_page_flip(dev, 1); 619 intel_finish_page_flip_plane(dev, 1); 620 } 621 622 if (de_iir & DE_PIPEA_VBLANK) 623 drm_handle_vblank(dev, 0); 624 625 if (de_iir & DE_PIPEB_VBLANK) 626 drm_handle_vblank(dev, 1); 627 628 /* check event from PCH */ 629 if (de_iir & DE_PCH_EVENT) { 630 if (pch_iir & hotplug_mask) 631 queue_work(dev_priv->wq, &dev_priv->hotplug_work); 632 pch_irq_handler(dev); 633 } 634 635 if (de_iir & DE_PCU_EVENT) { 636 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); 637 i915_handle_rps_change(dev); 638 } 639 640 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS) { 641 /* 642 * IIR bits should never already be set because IMR should 643 * prevent an interrupt from being shown in IIR. The warning 644 * displays a case where we've unsafely cleared 645 * dev_priv->pm_iir. Although missing an interrupt of the same 646 * type is not a problem, it displays a problem in the logic. 647 * 648 * The mask bit in IMR is cleared by rps_work. 649 */ 650 unsigned long flags; 651 spin_lock_irqsave(&dev_priv->rps_lock, flags); 652 WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n"); 653 dev_priv->pm_iir |= pm_iir; 654 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir); 655 POSTING_READ(GEN6_PMIMR); 656 spin_unlock_irqrestore(&dev_priv->rps_lock, flags); 657 queue_work(dev_priv->wq, &dev_priv->rps_work); 658 } 659 660 /* should clear PCH hotplug event before clear CPU irq */ 661 I915_WRITE(SDEIIR, pch_iir); 662 I915_WRITE(GTIIR, gt_iir); 663 I915_WRITE(DEIIR, de_iir); 664 I915_WRITE(GEN6_PMIIR, pm_iir); 665 666 done: 667 I915_WRITE(DEIER, de_ier); 668 POSTING_READ(DEIER); 669 670 return ret; 671 } 672 673 /** 674 * i915_error_work_func - do process context error handling work 675 * @work: work struct 676 * 677 * Fire an error uevent so userspace can see that a hang or error 678 * was detected. 679 */ 680 static void i915_error_work_func(struct work_struct *work) 681 { 682 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, 683 error_work); 684 struct drm_device *dev = dev_priv->dev; 685 char *error_event[] = { "ERROR=1", NULL }; 686 char *reset_event[] = { "RESET=1", NULL }; 687 char *reset_done_event[] = { "ERROR=0", NULL }; 688 689 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); 690 691 if (atomic_read(&dev_priv->mm.wedged)) { 692 DRM_DEBUG_DRIVER("resetting chip\n"); 693 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); 694 if (!i915_reset(dev, GRDOM_RENDER)) { 695 atomic_set(&dev_priv->mm.wedged, 0); 696 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event); 697 } 698 complete_all(&dev_priv->error_completion); 699 } 700 } 701 702 #ifdef CONFIG_DEBUG_FS 703 static struct drm_i915_error_object * 704 i915_error_object_create(struct drm_i915_private *dev_priv, 705 struct drm_i915_gem_object *src) 706 { 707 struct drm_i915_error_object *dst; 708 int page, page_count; 709 u32 reloc_offset; 710 711 if (src == NULL || src->pages == NULL) 712 return NULL; 713 714 page_count = src->base.size / PAGE_SIZE; 715 716 dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC); 717 if (dst == NULL) 718 return NULL; 719 720 reloc_offset = src->gtt_offset; 721 for (page = 0; page < page_count; page++) { 722 unsigned long flags; 723 void *d; 724 725 d = kmalloc(PAGE_SIZE, GFP_ATOMIC); 726 if (d == NULL) 727 goto unwind; 728 729 local_irq_save(flags); 730 if (reloc_offset < dev_priv->mm.gtt_mappable_end) { 731 void __iomem *s; 732 733 /* Simply ignore tiling or any overlapping fence. 734 * It's part of the error state, and this hopefully 735 * captures what the GPU read. 736 */ 737 738 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, 739 reloc_offset); 740 memcpy_fromio(d, s, PAGE_SIZE); 741 io_mapping_unmap_atomic(s); 742 } else { 743 void *s; 744 745 drm_clflush_pages(&src->pages[page], 1); 746 747 s = kmap_atomic(src->pages[page]); 748 memcpy(d, s, PAGE_SIZE); 749 kunmap_atomic(s); 750 751 drm_clflush_pages(&src->pages[page], 1); 752 } 753 local_irq_restore(flags); 754 755 dst->pages[page] = d; 756 757 reloc_offset += PAGE_SIZE; 758 } 759 dst->page_count = page_count; 760 dst->gtt_offset = src->gtt_offset; 761 762 return dst; 763 764 unwind: 765 while (page--) 766 kfree(dst->pages[page]); 767 kfree(dst); 768 return NULL; 769 } 770 771 static void 772 i915_error_object_free(struct drm_i915_error_object *obj) 773 { 774 int page; 775 776 if (obj == NULL) 777 return; 778 779 for (page = 0; page < obj->page_count; page++) 780 kfree(obj->pages[page]); 781 782 kfree(obj); 783 } 784 785 static void 786 i915_error_state_free(struct drm_device *dev, 787 struct drm_i915_error_state *error) 788 { 789 int i; 790 791 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 792 i915_error_object_free(error->ring[i].batchbuffer); 793 i915_error_object_free(error->ring[i].ringbuffer); 794 kfree(error->ring[i].requests); 795 } 796 797 kfree(error->active_bo); 798 kfree(error->overlay); 799 kfree(error); 800 } 801 802 static u32 capture_bo_list(struct drm_i915_error_buffer *err, 803 int count, 804 struct list_head *head) 805 { 806 struct drm_i915_gem_object *obj; 807 int i = 0; 808 809 list_for_each_entry(obj, head, mm_list) { 810 err->size = obj->base.size; 811 err->name = obj->base.name; 812 err->seqno = obj->last_rendering_seqno; 813 err->gtt_offset = obj->gtt_offset; 814 err->read_domains = obj->base.read_domains; 815 err->write_domain = obj->base.write_domain; 816 err->fence_reg = obj->fence_reg; 817 err->pinned = 0; 818 if (obj->pin_count > 0) 819 err->pinned = 1; 820 if (obj->user_pin_count > 0) 821 err->pinned = -1; 822 err->tiling = obj->tiling_mode; 823 err->dirty = obj->dirty; 824 err->purgeable = obj->madv != I915_MADV_WILLNEED; 825 err->ring = obj->ring ? obj->ring->id : -1; 826 err->cache_level = obj->cache_level; 827 828 if (++i == count) 829 break; 830 831 err++; 832 } 833 834 return i; 835 } 836 837 static void i915_gem_record_fences(struct drm_device *dev, 838 struct drm_i915_error_state *error) 839 { 840 struct drm_i915_private *dev_priv = dev->dev_private; 841 int i; 842 843 /* Fences */ 844 switch (INTEL_INFO(dev)->gen) { 845 case 7: 846 case 6: 847 for (i = 0; i < 16; i++) 848 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8)); 849 break; 850 case 5: 851 case 4: 852 for (i = 0; i < 16; i++) 853 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8)); 854 break; 855 case 3: 856 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) 857 for (i = 0; i < 8; i++) 858 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4)); 859 case 2: 860 for (i = 0; i < 8; i++) 861 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); 862 break; 863 864 } 865 } 866 867 static struct drm_i915_error_object * 868 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv, 869 struct intel_ring_buffer *ring) 870 { 871 struct drm_i915_gem_object *obj; 872 u32 seqno; 873 874 if (!ring->get_seqno) 875 return NULL; 876 877 seqno = ring->get_seqno(ring); 878 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) { 879 if (obj->ring != ring) 880 continue; 881 882 if (i915_seqno_passed(seqno, obj->last_rendering_seqno)) 883 continue; 884 885 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0) 886 continue; 887 888 /* We need to copy these to an anonymous buffer as the simplest 889 * method to avoid being overwritten by userspace. 890 */ 891 return i915_error_object_create(dev_priv, obj); 892 } 893 894 return NULL; 895 } 896 897 static void i915_record_ring_state(struct drm_device *dev, 898 struct drm_i915_error_state *error, 899 struct intel_ring_buffer *ring) 900 { 901 struct drm_i915_private *dev_priv = dev->dev_private; 902 903 if (INTEL_INFO(dev)->gen >= 6) { 904 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base)); 905 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring)); 906 error->semaphore_mboxes[ring->id][0] 907 = I915_READ(RING_SYNC_0(ring->mmio_base)); 908 error->semaphore_mboxes[ring->id][1] 909 = I915_READ(RING_SYNC_1(ring->mmio_base)); 910 } 911 912 if (INTEL_INFO(dev)->gen >= 4) { 913 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base)); 914 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base)); 915 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base)); 916 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base)); 917 if (ring->id == RCS) { 918 error->instdone1 = I915_READ(INSTDONE1); 919 error->bbaddr = I915_READ64(BB_ADDR); 920 } 921 } else { 922 error->ipeir[ring->id] = I915_READ(IPEIR); 923 error->ipehr[ring->id] = I915_READ(IPEHR); 924 error->instdone[ring->id] = I915_READ(INSTDONE); 925 } 926 927 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base)); 928 error->seqno[ring->id] = ring->get_seqno(ring); 929 error->acthd[ring->id] = intel_ring_get_active_head(ring); 930 error->head[ring->id] = I915_READ_HEAD(ring); 931 error->tail[ring->id] = I915_READ_TAIL(ring); 932 933 error->cpu_ring_head[ring->id] = ring->head; 934 error->cpu_ring_tail[ring->id] = ring->tail; 935 } 936 937 static void i915_gem_record_rings(struct drm_device *dev, 938 struct drm_i915_error_state *error) 939 { 940 struct drm_i915_private *dev_priv = dev->dev_private; 941 struct drm_i915_gem_request *request; 942 int i, count; 943 944 for (i = 0; i < I915_NUM_RINGS; i++) { 945 struct intel_ring_buffer *ring = &dev_priv->ring[i]; 946 947 if (ring->obj == NULL) 948 continue; 949 950 i915_record_ring_state(dev, error, ring); 951 952 error->ring[i].batchbuffer = 953 i915_error_first_batchbuffer(dev_priv, ring); 954 955 error->ring[i].ringbuffer = 956 i915_error_object_create(dev_priv, ring->obj); 957 958 count = 0; 959 list_for_each_entry(request, &ring->request_list, list) 960 count++; 961 962 error->ring[i].num_requests = count; 963 error->ring[i].requests = 964 kmalloc(count*sizeof(struct drm_i915_error_request), 965 GFP_ATOMIC); 966 if (error->ring[i].requests == NULL) { 967 error->ring[i].num_requests = 0; 968 continue; 969 } 970 971 count = 0; 972 list_for_each_entry(request, &ring->request_list, list) { 973 struct drm_i915_error_request *erq; 974 975 erq = &error->ring[i].requests[count++]; 976 erq->seqno = request->seqno; 977 erq->jiffies = request->emitted_jiffies; 978 erq->tail = request->tail; 979 } 980 } 981 } 982 983 /** 984 * i915_capture_error_state - capture an error record for later analysis 985 * @dev: drm device 986 * 987 * Should be called when an error is detected (either a hang or an error 988 * interrupt) to capture error state from the time of the error. Fills 989 * out a structure which becomes available in debugfs for user level tools 990 * to pick up. 991 */ 992 static void i915_capture_error_state(struct drm_device *dev) 993 { 994 struct drm_i915_private *dev_priv = dev->dev_private; 995 struct drm_i915_gem_object *obj; 996 struct drm_i915_error_state *error; 997 unsigned long flags; 998 int i, pipe; 999 1000 spin_lock_irqsave(&dev_priv->error_lock, flags); 1001 error = dev_priv->first_error; 1002 spin_unlock_irqrestore(&dev_priv->error_lock, flags); 1003 if (error) 1004 return; 1005 1006 /* Account for pipe specific data like PIPE*STAT */ 1007 error = kzalloc(sizeof(*error), GFP_ATOMIC); 1008 if (!error) { 1009 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); 1010 return; 1011 } 1012 1013 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n", 1014 dev->primary->index); 1015 1016 error->eir = I915_READ(EIR); 1017 error->pgtbl_er = I915_READ(PGTBL_ER); 1018 for_each_pipe(pipe) 1019 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe)); 1020 1021 if (INTEL_INFO(dev)->gen >= 6) { 1022 error->error = I915_READ(ERROR_GEN6); 1023 error->done_reg = I915_READ(DONE_REG); 1024 } 1025 1026 i915_gem_record_fences(dev, error); 1027 i915_gem_record_rings(dev, error); 1028 1029 /* Record buffers on the active and pinned lists. */ 1030 error->active_bo = NULL; 1031 error->pinned_bo = NULL; 1032 1033 i = 0; 1034 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) 1035 i++; 1036 error->active_bo_count = i; 1037 list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list) 1038 i++; 1039 error->pinned_bo_count = i - error->active_bo_count; 1040 1041 error->active_bo = NULL; 1042 error->pinned_bo = NULL; 1043 if (i) { 1044 error->active_bo = kmalloc(sizeof(*error->active_bo)*i, 1045 GFP_ATOMIC); 1046 if (error->active_bo) 1047 error->pinned_bo = 1048 error->active_bo + error->active_bo_count; 1049 } 1050 1051 if (error->active_bo) 1052 error->active_bo_count = 1053 capture_bo_list(error->active_bo, 1054 error->active_bo_count, 1055 &dev_priv->mm.active_list); 1056 1057 if (error->pinned_bo) 1058 error->pinned_bo_count = 1059 capture_bo_list(error->pinned_bo, 1060 error->pinned_bo_count, 1061 &dev_priv->mm.pinned_list); 1062 1063 do_gettimeofday(&error->time); 1064 1065 error->overlay = intel_overlay_capture_error_state(dev); 1066 error->display = intel_display_capture_error_state(dev); 1067 1068 spin_lock_irqsave(&dev_priv->error_lock, flags); 1069 if (dev_priv->first_error == NULL) { 1070 dev_priv->first_error = error; 1071 error = NULL; 1072 } 1073 spin_unlock_irqrestore(&dev_priv->error_lock, flags); 1074 1075 if (error) 1076 i915_error_state_free(dev, error); 1077 } 1078 1079 void i915_destroy_error_state(struct drm_device *dev) 1080 { 1081 struct drm_i915_private *dev_priv = dev->dev_private; 1082 struct drm_i915_error_state *error; 1083 unsigned long flags; 1084 1085 spin_lock_irqsave(&dev_priv->error_lock, flags); 1086 error = dev_priv->first_error; 1087 dev_priv->first_error = NULL; 1088 spin_unlock_irqrestore(&dev_priv->error_lock, flags); 1089 1090 if (error) 1091 i915_error_state_free(dev, error); 1092 } 1093 #else 1094 #define i915_capture_error_state(x) 1095 #endif 1096 1097 static void i915_report_and_clear_eir(struct drm_device *dev) 1098 { 1099 struct drm_i915_private *dev_priv = dev->dev_private; 1100 u32 eir = I915_READ(EIR); 1101 int pipe; 1102 1103 if (!eir) 1104 return; 1105 1106 printk(KERN_ERR "render error detected, EIR: 0x%08x\n", 1107 eir); 1108 1109 if (IS_G4X(dev)) { 1110 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { 1111 u32 ipeir = I915_READ(IPEIR_I965); 1112 1113 printk(KERN_ERR " IPEIR: 0x%08x\n", 1114 I915_READ(IPEIR_I965)); 1115 printk(KERN_ERR " IPEHR: 0x%08x\n", 1116 I915_READ(IPEHR_I965)); 1117 printk(KERN_ERR " INSTDONE: 0x%08x\n", 1118 I915_READ(INSTDONE_I965)); 1119 printk(KERN_ERR " INSTPS: 0x%08x\n", 1120 I915_READ(INSTPS)); 1121 printk(KERN_ERR " INSTDONE1: 0x%08x\n", 1122 I915_READ(INSTDONE1)); 1123 printk(KERN_ERR " ACTHD: 0x%08x\n", 1124 I915_READ(ACTHD_I965)); 1125 I915_WRITE(IPEIR_I965, ipeir); 1126 POSTING_READ(IPEIR_I965); 1127 } 1128 if (eir & GM45_ERROR_PAGE_TABLE) { 1129 u32 pgtbl_err = I915_READ(PGTBL_ER); 1130 printk(KERN_ERR "page table error\n"); 1131 printk(KERN_ERR " PGTBL_ER: 0x%08x\n", 1132 pgtbl_err); 1133 I915_WRITE(PGTBL_ER, pgtbl_err); 1134 POSTING_READ(PGTBL_ER); 1135 } 1136 } 1137 1138 if (!IS_GEN2(dev)) { 1139 if (eir & I915_ERROR_PAGE_TABLE) { 1140 u32 pgtbl_err = I915_READ(PGTBL_ER); 1141 printk(KERN_ERR "page table error\n"); 1142 printk(KERN_ERR " PGTBL_ER: 0x%08x\n", 1143 pgtbl_err); 1144 I915_WRITE(PGTBL_ER, pgtbl_err); 1145 POSTING_READ(PGTBL_ER); 1146 } 1147 } 1148 1149 if (eir & I915_ERROR_MEMORY_REFRESH) { 1150 printk(KERN_ERR "memory refresh error:\n"); 1151 for_each_pipe(pipe) 1152 printk(KERN_ERR "pipe %c stat: 0x%08x\n", 1153 pipe_name(pipe), I915_READ(PIPESTAT(pipe))); 1154 /* pipestat has already been acked */ 1155 } 1156 if (eir & I915_ERROR_INSTRUCTION) { 1157 printk(KERN_ERR "instruction error\n"); 1158 printk(KERN_ERR " INSTPM: 0x%08x\n", 1159 I915_READ(INSTPM)); 1160 if (INTEL_INFO(dev)->gen < 4) { 1161 u32 ipeir = I915_READ(IPEIR); 1162 1163 printk(KERN_ERR " IPEIR: 0x%08x\n", 1164 I915_READ(IPEIR)); 1165 printk(KERN_ERR " IPEHR: 0x%08x\n", 1166 I915_READ(IPEHR)); 1167 printk(KERN_ERR " INSTDONE: 0x%08x\n", 1168 I915_READ(INSTDONE)); 1169 printk(KERN_ERR " ACTHD: 0x%08x\n", 1170 I915_READ(ACTHD)); 1171 I915_WRITE(IPEIR, ipeir); 1172 POSTING_READ(IPEIR); 1173 } else { 1174 u32 ipeir = I915_READ(IPEIR_I965); 1175 1176 printk(KERN_ERR " IPEIR: 0x%08x\n", 1177 I915_READ(IPEIR_I965)); 1178 printk(KERN_ERR " IPEHR: 0x%08x\n", 1179 I915_READ(IPEHR_I965)); 1180 printk(KERN_ERR " INSTDONE: 0x%08x\n", 1181 I915_READ(INSTDONE_I965)); 1182 printk(KERN_ERR " INSTPS: 0x%08x\n", 1183 I915_READ(INSTPS)); 1184 printk(KERN_ERR " INSTDONE1: 0x%08x\n", 1185 I915_READ(INSTDONE1)); 1186 printk(KERN_ERR " ACTHD: 0x%08x\n", 1187 I915_READ(ACTHD_I965)); 1188 I915_WRITE(IPEIR_I965, ipeir); 1189 POSTING_READ(IPEIR_I965); 1190 } 1191 } 1192 1193 I915_WRITE(EIR, eir); 1194 POSTING_READ(EIR); 1195 eir = I915_READ(EIR); 1196 if (eir) { 1197 /* 1198 * some errors might have become stuck, 1199 * mask them. 1200 */ 1201 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); 1202 I915_WRITE(EMR, I915_READ(EMR) | eir); 1203 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); 1204 } 1205 } 1206 1207 /** 1208 * i915_handle_error - handle an error interrupt 1209 * @dev: drm device 1210 * 1211 * Do some basic checking of regsiter state at error interrupt time and 1212 * dump it to the syslog. Also call i915_capture_error_state() to make 1213 * sure we get a record and make it available in debugfs. Fire a uevent 1214 * so userspace knows something bad happened (should trigger collection 1215 * of a ring dump etc.). 1216 */ 1217 void i915_handle_error(struct drm_device *dev, bool wedged) 1218 { 1219 struct drm_i915_private *dev_priv = dev->dev_private; 1220 1221 i915_capture_error_state(dev); 1222 i915_report_and_clear_eir(dev); 1223 1224 if (wedged) { 1225 INIT_COMPLETION(dev_priv->error_completion); 1226 atomic_set(&dev_priv->mm.wedged, 1); 1227 1228 /* 1229 * Wakeup waiting processes so they don't hang 1230 */ 1231 wake_up_all(&dev_priv->ring[RCS].irq_queue); 1232 if (HAS_BSD(dev)) 1233 wake_up_all(&dev_priv->ring[VCS].irq_queue); 1234 if (HAS_BLT(dev)) 1235 wake_up_all(&dev_priv->ring[BCS].irq_queue); 1236 } 1237 1238 queue_work(dev_priv->wq, &dev_priv->error_work); 1239 } 1240 1241 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe) 1242 { 1243 drm_i915_private_t *dev_priv = dev->dev_private; 1244 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 1245 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1246 struct drm_i915_gem_object *obj; 1247 struct intel_unpin_work *work; 1248 unsigned long flags; 1249 bool stall_detected; 1250 1251 /* Ignore early vblank irqs */ 1252 if (intel_crtc == NULL) 1253 return; 1254 1255 spin_lock_irqsave(&dev->event_lock, flags); 1256 work = intel_crtc->unpin_work; 1257 1258 if (work == NULL || work->pending || !work->enable_stall_check) { 1259 /* Either the pending flip IRQ arrived, or we're too early. Don't check */ 1260 spin_unlock_irqrestore(&dev->event_lock, flags); 1261 return; 1262 } 1263 1264 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ 1265 obj = work->pending_flip_obj; 1266 if (INTEL_INFO(dev)->gen >= 4) { 1267 int dspsurf = DSPSURF(intel_crtc->plane); 1268 stall_detected = I915_READ(dspsurf) == obj->gtt_offset; 1269 } else { 1270 int dspaddr = DSPADDR(intel_crtc->plane); 1271 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset + 1272 crtc->y * crtc->fb->pitches[0] + 1273 crtc->x * crtc->fb->bits_per_pixel/8); 1274 } 1275 1276 spin_unlock_irqrestore(&dev->event_lock, flags); 1277 1278 if (stall_detected) { 1279 DRM_DEBUG_DRIVER("Pageflip stall detected\n"); 1280 intel_prepare_page_flip(dev, intel_crtc->plane); 1281 } 1282 } 1283 1284 static irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) 1285 { 1286 struct drm_device *dev = (struct drm_device *) arg; 1287 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1288 struct drm_i915_master_private *master_priv; 1289 u32 iir, new_iir; 1290 u32 pipe_stats[I915_MAX_PIPES]; 1291 u32 vblank_status; 1292 int vblank = 0; 1293 unsigned long irqflags; 1294 int irq_received; 1295 int ret = IRQ_NONE, pipe; 1296 bool blc_event = false; 1297 1298 atomic_inc(&dev_priv->irq_received); 1299 1300 iir = I915_READ(IIR); 1301 1302 if (INTEL_INFO(dev)->gen >= 4) 1303 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS; 1304 else 1305 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS; 1306 1307 for (;;) { 1308 irq_received = iir != 0; 1309 1310 /* Can't rely on pipestat interrupt bit in iir as it might 1311 * have been cleared after the pipestat interrupt was received. 1312 * It doesn't set the bit in iir again, but it still produces 1313 * interrupts (for non-MSI). 1314 */ 1315 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1316 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) 1317 i915_handle_error(dev, false); 1318 1319 for_each_pipe(pipe) { 1320 int reg = PIPESTAT(pipe); 1321 pipe_stats[pipe] = I915_READ(reg); 1322 1323 /* 1324 * Clear the PIPE*STAT regs before the IIR 1325 */ 1326 if (pipe_stats[pipe] & 0x8000ffff) { 1327 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 1328 DRM_DEBUG_DRIVER("pipe %c underrun\n", 1329 pipe_name(pipe)); 1330 I915_WRITE(reg, pipe_stats[pipe]); 1331 irq_received = 1; 1332 } 1333 } 1334 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1335 1336 if (!irq_received) 1337 break; 1338 1339 ret = IRQ_HANDLED; 1340 1341 /* Consume port. Then clear IIR or we'll miss events */ 1342 if ((I915_HAS_HOTPLUG(dev)) && 1343 (iir & I915_DISPLAY_PORT_INTERRUPT)) { 1344 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); 1345 1346 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", 1347 hotplug_status); 1348 if (hotplug_status & dev_priv->hotplug_supported_mask) 1349 queue_work(dev_priv->wq, 1350 &dev_priv->hotplug_work); 1351 1352 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); 1353 I915_READ(PORT_HOTPLUG_STAT); 1354 } 1355 1356 I915_WRITE(IIR, iir); 1357 new_iir = I915_READ(IIR); /* Flush posted writes */ 1358 1359 if (dev->primary->master) { 1360 master_priv = dev->primary->master->driver_priv; 1361 if (master_priv->sarea_priv) 1362 master_priv->sarea_priv->last_dispatch = 1363 READ_BREADCRUMB(dev_priv); 1364 } 1365 1366 if (iir & I915_USER_INTERRUPT) 1367 notify_ring(dev, &dev_priv->ring[RCS]); 1368 if (iir & I915_BSD_USER_INTERRUPT) 1369 notify_ring(dev, &dev_priv->ring[VCS]); 1370 1371 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) { 1372 intel_prepare_page_flip(dev, 0); 1373 if (dev_priv->flip_pending_is_done) 1374 intel_finish_page_flip_plane(dev, 0); 1375 } 1376 1377 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) { 1378 intel_prepare_page_flip(dev, 1); 1379 if (dev_priv->flip_pending_is_done) 1380 intel_finish_page_flip_plane(dev, 1); 1381 } 1382 1383 for_each_pipe(pipe) { 1384 if (pipe_stats[pipe] & vblank_status && 1385 drm_handle_vblank(dev, pipe)) { 1386 vblank++; 1387 if (!dev_priv->flip_pending_is_done) { 1388 i915_pageflip_stall_check(dev, pipe); 1389 intel_finish_page_flip(dev, pipe); 1390 } 1391 } 1392 1393 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) 1394 blc_event = true; 1395 } 1396 1397 1398 if (blc_event || (iir & I915_ASLE_INTERRUPT)) 1399 intel_opregion_asle_intr(dev); 1400 1401 /* With MSI, interrupts are only generated when iir 1402 * transitions from zero to nonzero. If another bit got 1403 * set while we were handling the existing iir bits, then 1404 * we would never get another interrupt. 1405 * 1406 * This is fine on non-MSI as well, as if we hit this path 1407 * we avoid exiting the interrupt handler only to generate 1408 * another one. 1409 * 1410 * Note that for MSI this could cause a stray interrupt report 1411 * if an interrupt landed in the time between writing IIR and 1412 * the posting read. This should be rare enough to never 1413 * trigger the 99% of 100,000 interrupts test for disabling 1414 * stray interrupts. 1415 */ 1416 iir = new_iir; 1417 } 1418 1419 return ret; 1420 } 1421 1422 static int i915_emit_irq(struct drm_device * dev) 1423 { 1424 drm_i915_private_t *dev_priv = dev->dev_private; 1425 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; 1426 1427 i915_kernel_lost_context(dev); 1428 1429 DRM_DEBUG_DRIVER("\n"); 1430 1431 dev_priv->counter++; 1432 if (dev_priv->counter > 0x7FFFFFFFUL) 1433 dev_priv->counter = 1; 1434 if (master_priv->sarea_priv) 1435 master_priv->sarea_priv->last_enqueue = dev_priv->counter; 1436 1437 if (BEGIN_LP_RING(4) == 0) { 1438 OUT_RING(MI_STORE_DWORD_INDEX); 1439 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); 1440 OUT_RING(dev_priv->counter); 1441 OUT_RING(MI_USER_INTERRUPT); 1442 ADVANCE_LP_RING(); 1443 } 1444 1445 return dev_priv->counter; 1446 } 1447 1448 static int i915_wait_irq(struct drm_device * dev, int irq_nr) 1449 { 1450 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1451 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; 1452 int ret = 0; 1453 struct intel_ring_buffer *ring = LP_RING(dev_priv); 1454 1455 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr, 1456 READ_BREADCRUMB(dev_priv)); 1457 1458 if (READ_BREADCRUMB(dev_priv) >= irq_nr) { 1459 if (master_priv->sarea_priv) 1460 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); 1461 return 0; 1462 } 1463 1464 if (master_priv->sarea_priv) 1465 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; 1466 1467 if (ring->irq_get(ring)) { 1468 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ, 1469 READ_BREADCRUMB(dev_priv) >= irq_nr); 1470 ring->irq_put(ring); 1471 } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000)) 1472 ret = -EBUSY; 1473 1474 if (ret == -EBUSY) { 1475 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", 1476 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); 1477 } 1478 1479 return ret; 1480 } 1481 1482 /* Needs the lock as it touches the ring. 1483 */ 1484 int i915_irq_emit(struct drm_device *dev, void *data, 1485 struct drm_file *file_priv) 1486 { 1487 drm_i915_private_t *dev_priv = dev->dev_private; 1488 drm_i915_irq_emit_t *emit = data; 1489 int result; 1490 1491 if (!dev_priv || !LP_RING(dev_priv)->virtual_start) { 1492 DRM_ERROR("called with no initialization\n"); 1493 return -EINVAL; 1494 } 1495 1496 RING_LOCK_TEST_WITH_RETURN(dev, file_priv); 1497 1498 mutex_lock(&dev->struct_mutex); 1499 result = i915_emit_irq(dev); 1500 mutex_unlock(&dev->struct_mutex); 1501 1502 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { 1503 DRM_ERROR("copy_to_user\n"); 1504 return -EFAULT; 1505 } 1506 1507 return 0; 1508 } 1509 1510 /* Doesn't need the hardware lock. 1511 */ 1512 int i915_irq_wait(struct drm_device *dev, void *data, 1513 struct drm_file *file_priv) 1514 { 1515 drm_i915_private_t *dev_priv = dev->dev_private; 1516 drm_i915_irq_wait_t *irqwait = data; 1517 1518 if (!dev_priv) { 1519 DRM_ERROR("called with no initialization\n"); 1520 return -EINVAL; 1521 } 1522 1523 return i915_wait_irq(dev, irqwait->irq_seq); 1524 } 1525 1526 /* Called from drm generic code, passed 'crtc' which 1527 * we use as a pipe index 1528 */ 1529 static int i915_enable_vblank(struct drm_device *dev, int pipe) 1530 { 1531 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1532 unsigned long irqflags; 1533 1534 if (!i915_pipe_enabled(dev, pipe)) 1535 return -EINVAL; 1536 1537 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1538 if (INTEL_INFO(dev)->gen >= 4) 1539 i915_enable_pipestat(dev_priv, pipe, 1540 PIPE_START_VBLANK_INTERRUPT_ENABLE); 1541 else 1542 i915_enable_pipestat(dev_priv, pipe, 1543 PIPE_VBLANK_INTERRUPT_ENABLE); 1544 1545 /* maintain vblank delivery even in deep C-states */ 1546 if (dev_priv->info->gen == 3) 1547 I915_WRITE(INSTPM, INSTPM_AGPBUSY_DIS << 16); 1548 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1549 1550 return 0; 1551 } 1552 1553 static int ironlake_enable_vblank(struct drm_device *dev, int pipe) 1554 { 1555 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1556 unsigned long irqflags; 1557 1558 if (!i915_pipe_enabled(dev, pipe)) 1559 return -EINVAL; 1560 1561 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1562 ironlake_enable_display_irq(dev_priv, (pipe == 0) ? 1563 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK); 1564 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1565 1566 return 0; 1567 } 1568 1569 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe) 1570 { 1571 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1572 unsigned long irqflags; 1573 1574 if (!i915_pipe_enabled(dev, pipe)) 1575 return -EINVAL; 1576 1577 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1578 ironlake_enable_display_irq(dev_priv, (pipe == 0) ? 1579 DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB); 1580 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1581 1582 return 0; 1583 } 1584 1585 /* Called from drm generic code, passed 'crtc' which 1586 * we use as a pipe index 1587 */ 1588 static void i915_disable_vblank(struct drm_device *dev, int pipe) 1589 { 1590 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1591 unsigned long irqflags; 1592 1593 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1594 if (dev_priv->info->gen == 3) 1595 I915_WRITE(INSTPM, 1596 INSTPM_AGPBUSY_DIS << 16 | INSTPM_AGPBUSY_DIS); 1597 1598 i915_disable_pipestat(dev_priv, pipe, 1599 PIPE_VBLANK_INTERRUPT_ENABLE | 1600 PIPE_START_VBLANK_INTERRUPT_ENABLE); 1601 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1602 } 1603 1604 static void ironlake_disable_vblank(struct drm_device *dev, int pipe) 1605 { 1606 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1607 unsigned long irqflags; 1608 1609 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1610 ironlake_disable_display_irq(dev_priv, (pipe == 0) ? 1611 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK); 1612 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1613 } 1614 1615 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe) 1616 { 1617 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1618 unsigned long irqflags; 1619 1620 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1621 ironlake_disable_display_irq(dev_priv, (pipe == 0) ? 1622 DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB); 1623 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1624 } 1625 1626 /* Set the vblank monitor pipe 1627 */ 1628 int i915_vblank_pipe_set(struct drm_device *dev, void *data, 1629 struct drm_file *file_priv) 1630 { 1631 drm_i915_private_t *dev_priv = dev->dev_private; 1632 1633 if (!dev_priv) { 1634 DRM_ERROR("called with no initialization\n"); 1635 return -EINVAL; 1636 } 1637 1638 return 0; 1639 } 1640 1641 int i915_vblank_pipe_get(struct drm_device *dev, void *data, 1642 struct drm_file *file_priv) 1643 { 1644 drm_i915_private_t *dev_priv = dev->dev_private; 1645 drm_i915_vblank_pipe_t *pipe = data; 1646 1647 if (!dev_priv) { 1648 DRM_ERROR("called with no initialization\n"); 1649 return -EINVAL; 1650 } 1651 1652 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; 1653 1654 return 0; 1655 } 1656 1657 /** 1658 * Schedule buffer swap at given vertical blank. 1659 */ 1660 int i915_vblank_swap(struct drm_device *dev, void *data, 1661 struct drm_file *file_priv) 1662 { 1663 /* The delayed swap mechanism was fundamentally racy, and has been 1664 * removed. The model was that the client requested a delayed flip/swap 1665 * from the kernel, then waited for vblank before continuing to perform 1666 * rendering. The problem was that the kernel might wake the client 1667 * up before it dispatched the vblank swap (since the lock has to be 1668 * held while touching the ringbuffer), in which case the client would 1669 * clear and start the next frame before the swap occurred, and 1670 * flicker would occur in addition to likely missing the vblank. 1671 * 1672 * In the absence of this ioctl, userland falls back to a correct path 1673 * of waiting for a vblank, then dispatching the swap on its own. 1674 * Context switching to userland and back is plenty fast enough for 1675 * meeting the requirements of vblank swapping. 1676 */ 1677 return -EINVAL; 1678 } 1679 1680 static u32 1681 ring_last_seqno(struct intel_ring_buffer *ring) 1682 { 1683 return list_entry(ring->request_list.prev, 1684 struct drm_i915_gem_request, list)->seqno; 1685 } 1686 1687 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err) 1688 { 1689 if (list_empty(&ring->request_list) || 1690 i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) { 1691 /* Issue a wake-up to catch stuck h/w. */ 1692 if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) { 1693 DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n", 1694 ring->name, 1695 ring->waiting_seqno, 1696 ring->get_seqno(ring)); 1697 wake_up_all(&ring->irq_queue); 1698 *err = true; 1699 } 1700 return true; 1701 } 1702 return false; 1703 } 1704 1705 static bool kick_ring(struct intel_ring_buffer *ring) 1706 { 1707 struct drm_device *dev = ring->dev; 1708 struct drm_i915_private *dev_priv = dev->dev_private; 1709 u32 tmp = I915_READ_CTL(ring); 1710 if (tmp & RING_WAIT) { 1711 DRM_ERROR("Kicking stuck wait on %s\n", 1712 ring->name); 1713 I915_WRITE_CTL(ring, tmp); 1714 return true; 1715 } 1716 return false; 1717 } 1718 1719 /** 1720 * This is called when the chip hasn't reported back with completed 1721 * batchbuffers in a long time. The first time this is called we simply record 1722 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses 1723 * again, we assume the chip is wedged and try to fix it. 1724 */ 1725 void i915_hangcheck_elapsed(unsigned long data) 1726 { 1727 struct drm_device *dev = (struct drm_device *)data; 1728 drm_i915_private_t *dev_priv = dev->dev_private; 1729 uint32_t acthd, instdone, instdone1, acthd_bsd, acthd_blt; 1730 bool err = false; 1731 1732 if (!i915_enable_hangcheck) 1733 return; 1734 1735 /* If all work is done then ACTHD clearly hasn't advanced. */ 1736 if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) && 1737 i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) && 1738 i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) { 1739 dev_priv->hangcheck_count = 0; 1740 if (err) 1741 goto repeat; 1742 return; 1743 } 1744 1745 if (INTEL_INFO(dev)->gen < 4) { 1746 instdone = I915_READ(INSTDONE); 1747 instdone1 = 0; 1748 } else { 1749 instdone = I915_READ(INSTDONE_I965); 1750 instdone1 = I915_READ(INSTDONE1); 1751 } 1752 acthd = intel_ring_get_active_head(&dev_priv->ring[RCS]); 1753 acthd_bsd = HAS_BSD(dev) ? 1754 intel_ring_get_active_head(&dev_priv->ring[VCS]) : 0; 1755 acthd_blt = HAS_BLT(dev) ? 1756 intel_ring_get_active_head(&dev_priv->ring[BCS]) : 0; 1757 1758 if (dev_priv->last_acthd == acthd && 1759 dev_priv->last_acthd_bsd == acthd_bsd && 1760 dev_priv->last_acthd_blt == acthd_blt && 1761 dev_priv->last_instdone == instdone && 1762 dev_priv->last_instdone1 == instdone1) { 1763 if (dev_priv->hangcheck_count++ > 1) { 1764 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n"); 1765 i915_handle_error(dev, true); 1766 1767 if (!IS_GEN2(dev)) { 1768 /* Is the chip hanging on a WAIT_FOR_EVENT? 1769 * If so we can simply poke the RB_WAIT bit 1770 * and break the hang. This should work on 1771 * all but the second generation chipsets. 1772 */ 1773 if (kick_ring(&dev_priv->ring[RCS])) 1774 goto repeat; 1775 1776 if (HAS_BSD(dev) && 1777 kick_ring(&dev_priv->ring[VCS])) 1778 goto repeat; 1779 1780 if (HAS_BLT(dev) && 1781 kick_ring(&dev_priv->ring[BCS])) 1782 goto repeat; 1783 } 1784 1785 return; 1786 } 1787 } else { 1788 dev_priv->hangcheck_count = 0; 1789 1790 dev_priv->last_acthd = acthd; 1791 dev_priv->last_acthd_bsd = acthd_bsd; 1792 dev_priv->last_acthd_blt = acthd_blt; 1793 dev_priv->last_instdone = instdone; 1794 dev_priv->last_instdone1 = instdone1; 1795 } 1796 1797 repeat: 1798 /* Reset timer case chip hangs without another request being added */ 1799 mod_timer(&dev_priv->hangcheck_timer, 1800 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); 1801 } 1802 1803 /* drm_dma.h hooks 1804 */ 1805 static void ironlake_irq_preinstall(struct drm_device *dev) 1806 { 1807 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1808 1809 atomic_set(&dev_priv->irq_received, 0); 1810 1811 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); 1812 INIT_WORK(&dev_priv->error_work, i915_error_work_func); 1813 if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) 1814 INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work); 1815 1816 I915_WRITE(HWSTAM, 0xeffe); 1817 1818 /* XXX hotplug from PCH */ 1819 1820 I915_WRITE(DEIMR, 0xffffffff); 1821 I915_WRITE(DEIER, 0x0); 1822 POSTING_READ(DEIER); 1823 1824 /* and GT */ 1825 I915_WRITE(GTIMR, 0xffffffff); 1826 I915_WRITE(GTIER, 0x0); 1827 POSTING_READ(GTIER); 1828 1829 /* south display irq */ 1830 I915_WRITE(SDEIMR, 0xffffffff); 1831 I915_WRITE(SDEIER, 0x0); 1832 POSTING_READ(SDEIER); 1833 } 1834 1835 /* 1836 * Enable digital hotplug on the PCH, and configure the DP short pulse 1837 * duration to 2ms (which is the minimum in the Display Port spec) 1838 * 1839 * This register is the same on all known PCH chips. 1840 */ 1841 1842 static void ironlake_enable_pch_hotplug(struct drm_device *dev) 1843 { 1844 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1845 u32 hotplug; 1846 1847 hotplug = I915_READ(PCH_PORT_HOTPLUG); 1848 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); 1849 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; 1850 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; 1851 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; 1852 I915_WRITE(PCH_PORT_HOTPLUG, hotplug); 1853 } 1854 1855 static int ironlake_irq_postinstall(struct drm_device *dev) 1856 { 1857 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1858 /* enable kind of interrupts always enabled */ 1859 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | 1860 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE; 1861 u32 render_irqs; 1862 u32 hotplug_mask; 1863 1864 DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue); 1865 if (HAS_BSD(dev)) 1866 DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue); 1867 if (HAS_BLT(dev)) 1868 DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue); 1869 1870 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; 1871 dev_priv->irq_mask = ~display_mask; 1872 1873 /* should always can generate irq */ 1874 I915_WRITE(DEIIR, I915_READ(DEIIR)); 1875 I915_WRITE(DEIMR, dev_priv->irq_mask); 1876 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK); 1877 POSTING_READ(DEIER); 1878 1879 dev_priv->gt_irq_mask = ~0; 1880 1881 I915_WRITE(GTIIR, I915_READ(GTIIR)); 1882 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); 1883 1884 if (IS_GEN6(dev)) 1885 render_irqs = 1886 GT_USER_INTERRUPT | 1887 GT_GEN6_BSD_USER_INTERRUPT | 1888 GT_BLT_USER_INTERRUPT; 1889 else 1890 render_irqs = 1891 GT_USER_INTERRUPT | 1892 GT_PIPE_NOTIFY | 1893 GT_BSD_USER_INTERRUPT; 1894 I915_WRITE(GTIER, render_irqs); 1895 POSTING_READ(GTIER); 1896 1897 if (HAS_PCH_CPT(dev)) { 1898 hotplug_mask = (SDE_CRT_HOTPLUG_CPT | 1899 SDE_PORTB_HOTPLUG_CPT | 1900 SDE_PORTC_HOTPLUG_CPT | 1901 SDE_PORTD_HOTPLUG_CPT); 1902 } else { 1903 hotplug_mask = (SDE_CRT_HOTPLUG | 1904 SDE_PORTB_HOTPLUG | 1905 SDE_PORTC_HOTPLUG | 1906 SDE_PORTD_HOTPLUG | 1907 SDE_AUX_MASK); 1908 } 1909 1910 dev_priv->pch_irq_mask = ~hotplug_mask; 1911 1912 I915_WRITE(SDEIIR, I915_READ(SDEIIR)); 1913 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask); 1914 I915_WRITE(SDEIER, hotplug_mask); 1915 POSTING_READ(SDEIER); 1916 1917 ironlake_enable_pch_hotplug(dev); 1918 1919 if (IS_IRONLAKE_M(dev)) { 1920 /* Clear & enable PCU event interrupts */ 1921 I915_WRITE(DEIIR, DE_PCU_EVENT); 1922 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT); 1923 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); 1924 } 1925 1926 return 0; 1927 } 1928 1929 static int ivybridge_irq_postinstall(struct drm_device *dev) 1930 { 1931 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1932 /* enable kind of interrupts always enabled */ 1933 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | 1934 DE_PCH_EVENT_IVB | DE_PLANEA_FLIP_DONE_IVB | 1935 DE_PLANEB_FLIP_DONE_IVB; 1936 u32 render_irqs; 1937 u32 hotplug_mask; 1938 1939 DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue); 1940 if (HAS_BSD(dev)) 1941 DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue); 1942 if (HAS_BLT(dev)) 1943 DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue); 1944 1945 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; 1946 dev_priv->irq_mask = ~display_mask; 1947 1948 /* should always can generate irq */ 1949 I915_WRITE(DEIIR, I915_READ(DEIIR)); 1950 I915_WRITE(DEIMR, dev_priv->irq_mask); 1951 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK_IVB | 1952 DE_PIPEB_VBLANK_IVB); 1953 POSTING_READ(DEIER); 1954 1955 dev_priv->gt_irq_mask = ~0; 1956 1957 I915_WRITE(GTIIR, I915_READ(GTIIR)); 1958 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); 1959 1960 render_irqs = GT_USER_INTERRUPT | GT_GEN6_BSD_USER_INTERRUPT | 1961 GT_BLT_USER_INTERRUPT; 1962 I915_WRITE(GTIER, render_irqs); 1963 POSTING_READ(GTIER); 1964 1965 hotplug_mask = (SDE_CRT_HOTPLUG_CPT | 1966 SDE_PORTB_HOTPLUG_CPT | 1967 SDE_PORTC_HOTPLUG_CPT | 1968 SDE_PORTD_HOTPLUG_CPT); 1969 dev_priv->pch_irq_mask = ~hotplug_mask; 1970 1971 I915_WRITE(SDEIIR, I915_READ(SDEIIR)); 1972 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask); 1973 I915_WRITE(SDEIER, hotplug_mask); 1974 POSTING_READ(SDEIER); 1975 1976 ironlake_enable_pch_hotplug(dev); 1977 1978 return 0; 1979 } 1980 1981 static void i915_driver_irq_preinstall(struct drm_device * dev) 1982 { 1983 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1984 int pipe; 1985 1986 atomic_set(&dev_priv->irq_received, 0); 1987 1988 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); 1989 INIT_WORK(&dev_priv->error_work, i915_error_work_func); 1990 1991 if (I915_HAS_HOTPLUG(dev)) { 1992 I915_WRITE(PORT_HOTPLUG_EN, 0); 1993 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 1994 } 1995 1996 I915_WRITE(HWSTAM, 0xeffe); 1997 for_each_pipe(pipe) 1998 I915_WRITE(PIPESTAT(pipe), 0); 1999 I915_WRITE(IMR, 0xffffffff); 2000 I915_WRITE(IER, 0x0); 2001 POSTING_READ(IER); 2002 } 2003 2004 /* 2005 * Must be called after intel_modeset_init or hotplug interrupts won't be 2006 * enabled correctly. 2007 */ 2008 static int i915_driver_irq_postinstall(struct drm_device *dev) 2009 { 2010 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2011 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR; 2012 u32 error_mask; 2013 2014 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; 2015 2016 /* Unmask the interrupts that we always want on. */ 2017 dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX; 2018 2019 dev_priv->pipestat[0] = 0; 2020 dev_priv->pipestat[1] = 0; 2021 2022 if (I915_HAS_HOTPLUG(dev)) { 2023 /* Enable in IER... */ 2024 enable_mask |= I915_DISPLAY_PORT_INTERRUPT; 2025 /* and unmask in IMR */ 2026 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; 2027 } 2028 2029 /* 2030 * Enable some error detection, note the instruction error mask 2031 * bit is reserved, so we leave it masked. 2032 */ 2033 if (IS_G4X(dev)) { 2034 error_mask = ~(GM45_ERROR_PAGE_TABLE | 2035 GM45_ERROR_MEM_PRIV | 2036 GM45_ERROR_CP_PRIV | 2037 I915_ERROR_MEMORY_REFRESH); 2038 } else { 2039 error_mask = ~(I915_ERROR_PAGE_TABLE | 2040 I915_ERROR_MEMORY_REFRESH); 2041 } 2042 I915_WRITE(EMR, error_mask); 2043 2044 I915_WRITE(IMR, dev_priv->irq_mask); 2045 I915_WRITE(IER, enable_mask); 2046 POSTING_READ(IER); 2047 2048 if (I915_HAS_HOTPLUG(dev)) { 2049 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); 2050 2051 /* Note HDMI and DP share bits */ 2052 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) 2053 hotplug_en |= HDMIB_HOTPLUG_INT_EN; 2054 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) 2055 hotplug_en |= HDMIC_HOTPLUG_INT_EN; 2056 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) 2057 hotplug_en |= HDMID_HOTPLUG_INT_EN; 2058 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS) 2059 hotplug_en |= SDVOC_HOTPLUG_INT_EN; 2060 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS) 2061 hotplug_en |= SDVOB_HOTPLUG_INT_EN; 2062 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) { 2063 hotplug_en |= CRT_HOTPLUG_INT_EN; 2064 2065 /* Programming the CRT detection parameters tends 2066 to generate a spurious hotplug event about three 2067 seconds later. So just do it once. 2068 */ 2069 if (IS_G4X(dev)) 2070 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; 2071 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; 2072 } 2073 2074 /* Ignore TV since it's buggy */ 2075 2076 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); 2077 } 2078 2079 intel_opregion_enable_asle(dev); 2080 2081 return 0; 2082 } 2083 2084 static void ironlake_irq_uninstall(struct drm_device *dev) 2085 { 2086 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2087 2088 if (!dev_priv) 2089 return; 2090 2091 dev_priv->vblank_pipe = 0; 2092 2093 I915_WRITE(HWSTAM, 0xffffffff); 2094 2095 I915_WRITE(DEIMR, 0xffffffff); 2096 I915_WRITE(DEIER, 0x0); 2097 I915_WRITE(DEIIR, I915_READ(DEIIR)); 2098 2099 I915_WRITE(GTIMR, 0xffffffff); 2100 I915_WRITE(GTIER, 0x0); 2101 I915_WRITE(GTIIR, I915_READ(GTIIR)); 2102 2103 I915_WRITE(SDEIMR, 0xffffffff); 2104 I915_WRITE(SDEIER, 0x0); 2105 I915_WRITE(SDEIIR, I915_READ(SDEIIR)); 2106 } 2107 2108 static void i915_driver_irq_uninstall(struct drm_device * dev) 2109 { 2110 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2111 int pipe; 2112 2113 if (!dev_priv) 2114 return; 2115 2116 dev_priv->vblank_pipe = 0; 2117 2118 if (I915_HAS_HOTPLUG(dev)) { 2119 I915_WRITE(PORT_HOTPLUG_EN, 0); 2120 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 2121 } 2122 2123 I915_WRITE(HWSTAM, 0xffffffff); 2124 for_each_pipe(pipe) 2125 I915_WRITE(PIPESTAT(pipe), 0); 2126 I915_WRITE(IMR, 0xffffffff); 2127 I915_WRITE(IER, 0x0); 2128 2129 for_each_pipe(pipe) 2130 I915_WRITE(PIPESTAT(pipe), 2131 I915_READ(PIPESTAT(pipe)) & 0x8000ffff); 2132 I915_WRITE(IIR, I915_READ(IIR)); 2133 } 2134 2135 void intel_irq_init(struct drm_device *dev) 2136 { 2137 dev->driver->get_vblank_counter = i915_get_vblank_counter; 2138 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ 2139 if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) { 2140 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ 2141 dev->driver->get_vblank_counter = gm45_get_vblank_counter; 2142 } 2143 2144 if (drm_core_check_feature(dev, DRIVER_MODESET)) 2145 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; 2146 else 2147 dev->driver->get_vblank_timestamp = NULL; 2148 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; 2149 2150 if (IS_IVYBRIDGE(dev)) { 2151 /* Share pre & uninstall handlers with ILK/SNB */ 2152 dev->driver->irq_handler = ivybridge_irq_handler; 2153 dev->driver->irq_preinstall = ironlake_irq_preinstall; 2154 dev->driver->irq_postinstall = ivybridge_irq_postinstall; 2155 dev->driver->irq_uninstall = ironlake_irq_uninstall; 2156 dev->driver->enable_vblank = ivybridge_enable_vblank; 2157 dev->driver->disable_vblank = ivybridge_disable_vblank; 2158 } else if (HAS_PCH_SPLIT(dev)) { 2159 dev->driver->irq_handler = ironlake_irq_handler; 2160 dev->driver->irq_preinstall = ironlake_irq_preinstall; 2161 dev->driver->irq_postinstall = ironlake_irq_postinstall; 2162 dev->driver->irq_uninstall = ironlake_irq_uninstall; 2163 dev->driver->enable_vblank = ironlake_enable_vblank; 2164 dev->driver->disable_vblank = ironlake_disable_vblank; 2165 } else { 2166 dev->driver->irq_preinstall = i915_driver_irq_preinstall; 2167 dev->driver->irq_postinstall = i915_driver_irq_postinstall; 2168 dev->driver->irq_uninstall = i915_driver_irq_uninstall; 2169 dev->driver->irq_handler = i915_driver_irq_handler; 2170 dev->driver->enable_vblank = i915_enable_vblank; 2171 dev->driver->disable_vblank = i915_disable_vblank; 2172 } 2173 } 2174