1 /*
2  * SPDX-License-Identifier: MIT
3  *
4  * Copyright � 2008-2018 Intel Corporation
5  */
6 
7 #ifndef _I915_GPU_ERROR_H_
8 #define _I915_GPU_ERROR_H_
9 
10 #include <linux/atomic.h>
11 #include <linux/kref.h>
12 #include <linux/ktime.h>
13 #include <linux/sched.h>
14 
15 #include <drm/drm_mm.h>
16 
17 #include "gt/intel_engine.h"
18 #include "gt/uc/intel_uc_fw.h"
19 
20 #include "intel_device_info.h"
21 
22 #include "i915_gem.h"
23 #include "i915_gem_gtt.h"
24 #include "i915_params.h"
25 #include "i915_scheduler.h"
26 
27 struct drm_i915_private;
28 struct intel_overlay_error_state;
29 struct intel_display_error_state;
30 
31 struct i915_gpu_state {
32 	struct kref ref;
33 	ktime_t time;
34 	ktime_t boottime;
35 	ktime_t uptime;
36 	unsigned long capture;
37 	unsigned long epoch;
38 
39 	struct drm_i915_private *i915;
40 
41 	char error_msg[128];
42 	bool simulated;
43 	bool awake;
44 	bool wakelock;
45 	bool suspended;
46 	int iommu;
47 	u32 reset_count;
48 	u32 suspend_count;
49 	struct intel_device_info device_info;
50 	struct intel_runtime_info runtime_info;
51 	struct intel_driver_caps driver_caps;
52 	struct i915_params params;
53 
54 	struct i915_error_uc {
55 		struct intel_uc_fw guc_fw;
56 		struct intel_uc_fw huc_fw;
57 		struct drm_i915_error_object *guc_log;
58 	} uc;
59 
60 	/* Generic register state */
61 	u32 eir;
62 	u32 pgtbl_er;
63 	u32 ier;
64 	u32 gtier[6], ngtier;
65 	u32 ccid;
66 	u32 derrmr;
67 	u32 forcewake;
68 	u32 error; /* gen6+ */
69 	u32 err_int; /* gen7 */
70 	u32 fault_data0; /* gen8, gen9 */
71 	u32 fault_data1; /* gen8, gen9 */
72 	u32 done_reg;
73 	u32 gac_eco;
74 	u32 gam_ecochk;
75 	u32 gab_ctl;
76 	u32 gfx_mode;
77 
78 	u32 nfence;
79 	u64 fence[I915_MAX_NUM_FENCES];
80 	struct intel_overlay_error_state *overlay;
81 	struct intel_display_error_state *display;
82 
83 	struct drm_i915_error_engine {
84 		const struct intel_engine_cs *engine;
85 
86 		/* Software tracked state */
87 		bool idle;
88 		unsigned long hangcheck_timestamp;
89 		int num_requests;
90 		u32 reset_count;
91 
92 		/* position of active request inside the ring */
93 		u32 rq_head, rq_post, rq_tail;
94 
95 		/* our own tracking of ring head and tail */
96 		u32 cpu_ring_head;
97 		u32 cpu_ring_tail;
98 
99 		/* Register state */
100 		u32 start;
101 		u32 tail;
102 		u32 head;
103 		u32 ctl;
104 		u32 mode;
105 		u32 hws;
106 		u32 ipeir;
107 		u32 ipehr;
108 		u32 bbstate;
109 		u32 instpm;
110 		u32 instps;
111 		u64 bbaddr;
112 		u64 acthd;
113 		u32 fault_reg;
114 		u64 faddr;
115 		u32 rc_psmi; /* sleep state */
116 		struct intel_instdone instdone;
117 
118 		struct drm_i915_error_context {
119 			char comm[TASK_COMM_LEN];
120 			pid_t pid;
121 			u32 hw_id;
122 			int active;
123 			int guilty;
124 			struct i915_sched_attr sched_attr;
125 		} context;
126 
127 		struct drm_i915_error_object {
128 			u64 gtt_offset;
129 			u64 gtt_size;
130 			int num_pages;
131 			int page_count;
132 			int unused;
133 			u32 *pages[0];
134 		} *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
135 
136 		struct drm_i915_error_object **user_bo;
137 		long user_bo_count;
138 
139 		struct drm_i915_error_object *wa_ctx;
140 		struct drm_i915_error_object *default_state;
141 
142 		struct drm_i915_error_request {
143 			unsigned long flags;
144 			long jiffies;
145 			pid_t pid;
146 			u32 context;
147 			u32 seqno;
148 			u32 start;
149 			u32 head;
150 			u32 tail;
151 			struct i915_sched_attr sched_attr;
152 		} *requests, execlist[EXECLIST_MAX_PORTS];
153 		unsigned int num_ports;
154 
155 		struct {
156 			u32 gfx_mode;
157 			union {
158 				u64 pdp[4];
159 				u32 pp_dir_base;
160 			};
161 		} vm_info;
162 
163 		struct drm_i915_error_engine *next;
164 	} *engine;
165 
166 	struct scatterlist *sgl, *fit;
167 };
168 
169 struct i915_gpu_error {
170 	/* For reset and error_state handling. */
171 	spinlock_t lock;
172 	/* Protected by the above dev->gpu_error.lock. */
173 	struct i915_gpu_state *first_error;
174 
175 	atomic_t pending_fb_pin;
176 
177 	/** Number of times the device has been reset (global) */
178 	atomic_t reset_count;
179 
180 	/** Number of times an engine has been reset */
181 	atomic_t reset_engine_count[I915_NUM_ENGINES];
182 };
183 
184 struct drm_i915_error_state_buf {
185 	struct drm_i915_private *i915;
186 	struct scatterlist *sgl, *cur, *end;
187 
188 	char *buf;
189 	size_t bytes;
190 	size_t size;
191 	loff_t iter;
192 
193 	int err;
194 };
195 
196 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
197 
198 __printf(2, 3)
199 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
200 
201 struct i915_gpu_state *i915_capture_gpu_state(struct drm_i915_private *i915);
202 void i915_capture_error_state(struct drm_i915_private *dev_priv,
203 			      intel_engine_mask_t engine_mask,
204 			      const char *error_msg);
205 
206 static inline struct i915_gpu_state *
207 i915_gpu_state_get(struct i915_gpu_state *gpu)
208 {
209 	kref_get(&gpu->ref);
210 	return gpu;
211 }
212 
213 ssize_t i915_gpu_state_copy_to_buffer(struct i915_gpu_state *error,
214 				      char *buf, loff_t offset, size_t count);
215 
216 void __i915_gpu_state_free(struct kref *kref);
217 static inline void i915_gpu_state_put(struct i915_gpu_state *gpu)
218 {
219 	if (gpu)
220 		kref_put(&gpu->ref, __i915_gpu_state_free);
221 }
222 
223 struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915);
224 void i915_reset_error_state(struct drm_i915_private *i915);
225 void i915_disable_error_state(struct drm_i915_private *i915, int err);
226 
227 #else
228 
229 static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
230 					    u32 engine_mask,
231 					    const char *error_msg)
232 {
233 }
234 
235 static inline struct i915_gpu_state *
236 i915_first_error_state(struct drm_i915_private *i915)
237 {
238 	return ERR_PTR(-ENODEV);
239 }
240 
241 static inline void i915_reset_error_state(struct drm_i915_private *i915)
242 {
243 }
244 
245 static inline void i915_disable_error_state(struct drm_i915_private *i915,
246 					    int err)
247 {
248 }
249 
250 #endif /* IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) */
251 
252 #endif /* _I915_GPU_ERROR_H_ */
253