1 /* 2 * SPDX-License-Identifier: MIT 3 * 4 * Copyright © 2008-2018 Intel Corporation 5 */ 6 7 #ifndef _I915_GPU_ERROR_H_ 8 #define _I915_GPU_ERROR_H_ 9 10 #include <linux/atomic.h> 11 #include <linux/kref.h> 12 #include <linux/ktime.h> 13 #include <linux/sched.h> 14 15 #include <drm/drm_mm.h> 16 17 #include "gt/intel_engine.h" 18 #include "gt/intel_gt_types.h" 19 #include "gt/uc/intel_uc_fw.h" 20 21 #include "intel_device_info.h" 22 23 #include "i915_gem.h" 24 #include "i915_gem_gtt.h" 25 #include "i915_params.h" 26 #include "i915_scheduler.h" 27 28 struct drm_i915_private; 29 struct i915_vma_compress; 30 struct intel_engine_capture_vma; 31 struct intel_overlay_error_state; 32 33 struct i915_vma_coredump { 34 struct i915_vma_coredump *next; 35 36 char name[20]; 37 38 u64 gtt_offset; 39 u64 gtt_size; 40 u32 gtt_page_sizes; 41 42 int unused; 43 struct list_head page_list; 44 }; 45 46 struct i915_request_coredump { 47 unsigned long flags; 48 pid_t pid; 49 u32 context; 50 u32 seqno; 51 u32 head; 52 u32 tail; 53 struct i915_sched_attr sched_attr; 54 }; 55 56 struct __guc_capture_parsed_output; 57 58 struct intel_engine_coredump { 59 const struct intel_engine_cs *engine; 60 61 bool hung; 62 bool simulated; 63 u32 reset_count; 64 65 /* position of active request inside the ring */ 66 u32 rq_head, rq_post, rq_tail; 67 68 /* Register state */ 69 u32 ccid; 70 u32 start; 71 u32 tail; 72 u32 head; 73 u32 ctl; 74 u32 mode; 75 u32 hws; 76 u32 ipeir; 77 u32 ipehr; 78 u32 esr; 79 u32 bbstate; 80 u32 instpm; 81 u32 instps; 82 u64 bbaddr; 83 u64 acthd; 84 u32 fault_reg; 85 u64 faddr; 86 u32 rc_psmi; /* sleep state */ 87 u32 nopid; 88 u32 excc; 89 u32 cmd_cctl; 90 u32 cscmdop; 91 u32 ctx_sr_ctl; 92 u32 dma_faddr_hi; 93 u32 dma_faddr_lo; 94 struct intel_instdone instdone; 95 96 /* GuC matched capture-lists info */ 97 struct intel_guc_state_capture *capture; 98 struct __guc_capture_parsed_output *guc_capture_node; 99 100 struct i915_gem_context_coredump { 101 char comm[TASK_COMM_LEN]; 102 103 u64 total_runtime; 104 u64 avg_runtime; 105 106 pid_t pid; 107 int active; 108 int guilty; 109 struct i915_sched_attr sched_attr; 110 } context; 111 112 struct i915_vma_coredump *vma; 113 114 struct i915_request_coredump execlist[EXECLIST_MAX_PORTS]; 115 unsigned int num_ports; 116 117 struct { 118 u32 gfx_mode; 119 union { 120 u64 pdp[4]; 121 u32 pp_dir_base; 122 }; 123 } vm_info; 124 125 struct intel_engine_coredump *next; 126 }; 127 128 struct intel_gt_coredump { 129 const struct intel_gt *_gt; 130 bool awake; 131 bool simulated; 132 133 struct intel_gt_info info; 134 135 /* Generic register state */ 136 u32 eir; 137 u32 pgtbl_er; 138 u32 ier; 139 u32 gtier[6], ngtier; 140 u32 forcewake; 141 u32 error; /* gen6+ */ 142 u32 err_int; /* gen7 */ 143 u32 fault_data0; /* gen8, gen9 */ 144 u32 fault_data1; /* gen8, gen9 */ 145 u32 done_reg; 146 u32 gac_eco; 147 u32 gam_ecochk; 148 u32 gab_ctl; 149 u32 gfx_mode; 150 u32 gtt_cache; 151 u32 aux_err; /* gen12 */ 152 u32 gam_done; /* gen12 */ 153 154 /* Display related */ 155 u32 derrmr; 156 u32 sfc_done[I915_MAX_SFC]; /* gen12 */ 157 158 u32 nfence; 159 u64 fence[I915_MAX_NUM_FENCES]; 160 161 struct intel_engine_coredump *engine; 162 163 struct intel_uc_coredump { 164 struct intel_uc_fw guc_fw; 165 struct intel_uc_fw huc_fw; 166 struct i915_vma_coredump *guc_log; 167 bool is_guc_capture; 168 } *uc; 169 170 struct intel_gt_coredump *next; 171 }; 172 173 struct i915_gpu_coredump { 174 struct kref ref; 175 ktime_t time; 176 ktime_t boottime; 177 ktime_t uptime; 178 unsigned long capture; 179 180 struct drm_i915_private *i915; 181 182 struct intel_gt_coredump *gt; 183 184 char error_msg[128]; 185 bool simulated; 186 bool wakelock; 187 bool suspended; 188 int iommu; 189 u32 reset_count; 190 u32 suspend_count; 191 192 struct intel_device_info device_info; 193 struct intel_runtime_info runtime_info; 194 struct intel_driver_caps driver_caps; 195 struct i915_params params; 196 197 struct intel_overlay_error_state *overlay; 198 199 struct scatterlist *sgl, *fit; 200 }; 201 202 struct i915_gpu_error { 203 /* For reset and error_state handling. */ 204 spinlock_t lock; 205 /* Protected by the above dev->gpu_error.lock. */ 206 struct i915_gpu_coredump *first_error; 207 208 atomic_t pending_fb_pin; 209 210 /** Number of times the device has been reset (global) */ 211 atomic_t reset_count; 212 213 /** Number of times an engine has been reset */ 214 atomic_t reset_engine_count[I915_NUM_ENGINES]; 215 }; 216 217 struct drm_i915_error_state_buf { 218 struct drm_i915_private *i915; 219 struct scatterlist *sgl, *cur, *end; 220 221 char *buf; 222 size_t bytes; 223 size_t size; 224 loff_t iter; 225 226 int err; 227 }; 228 229 static inline u32 i915_reset_count(struct i915_gpu_error *error) 230 { 231 return atomic_read(&error->reset_count); 232 } 233 234 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error, 235 const struct intel_engine_cs *engine) 236 { 237 return atomic_read(&error->reset_engine_count[engine->uabi_class]); 238 } 239 240 #define CORE_DUMP_FLAG_NONE 0x0 241 #define CORE_DUMP_FLAG_IS_GUC_CAPTURE BIT(0) 242 243 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 244 245 __printf(2, 3) 246 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); 247 void intel_gpu_error_print_vma(struct drm_i915_error_state_buf *m, 248 const struct intel_engine_cs *engine, 249 const struct i915_vma_coredump *vma); 250 struct i915_vma_coredump * 251 intel_gpu_error_find_batch(const struct intel_engine_coredump *ee); 252 253 struct i915_gpu_coredump *i915_gpu_coredump(struct intel_gt *gt, 254 intel_engine_mask_t engine_mask, u32 dump_flags); 255 void i915_capture_error_state(struct intel_gt *gt, 256 intel_engine_mask_t engine_mask, u32 dump_flags); 257 258 struct i915_gpu_coredump * 259 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp); 260 261 struct intel_gt_coredump * 262 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp, u32 dump_flags); 263 264 struct intel_engine_coredump * 265 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp, u32 dump_flags); 266 267 struct intel_engine_capture_vma * 268 intel_engine_coredump_add_request(struct intel_engine_coredump *ee, 269 struct i915_request *rq, 270 gfp_t gfp); 271 272 void intel_engine_coredump_add_vma(struct intel_engine_coredump *ee, 273 struct intel_engine_capture_vma *capture, 274 struct i915_vma_compress *compress); 275 276 struct i915_vma_compress * 277 i915_vma_capture_prepare(struct intel_gt_coredump *gt); 278 279 void i915_vma_capture_finish(struct intel_gt_coredump *gt, 280 struct i915_vma_compress *compress); 281 282 void i915_error_state_store(struct i915_gpu_coredump *error); 283 284 static inline struct i915_gpu_coredump * 285 i915_gpu_coredump_get(struct i915_gpu_coredump *gpu) 286 { 287 kref_get(&gpu->ref); 288 return gpu; 289 } 290 291 ssize_t 292 i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error, 293 char *buf, loff_t offset, size_t count); 294 295 void __i915_gpu_coredump_free(struct kref *kref); 296 static inline void i915_gpu_coredump_put(struct i915_gpu_coredump *gpu) 297 { 298 if (gpu) 299 kref_put(&gpu->ref, __i915_gpu_coredump_free); 300 } 301 302 struct i915_gpu_coredump *i915_first_error_state(struct drm_i915_private *i915); 303 void i915_reset_error_state(struct drm_i915_private *i915); 304 void i915_disable_error_state(struct drm_i915_private *i915, int err); 305 306 #else 307 308 __printf(2, 3) 309 static inline void 310 i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) 311 { 312 } 313 314 static inline void 315 i915_capture_error_state(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags) 316 { 317 } 318 319 static inline struct i915_gpu_coredump * 320 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp) 321 { 322 return NULL; 323 } 324 325 static inline struct intel_gt_coredump * 326 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp, u32 dump_flags) 327 { 328 return NULL; 329 } 330 331 static inline struct intel_engine_coredump * 332 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp, u32 dump_flags) 333 { 334 return NULL; 335 } 336 337 static inline struct intel_engine_capture_vma * 338 intel_engine_coredump_add_request(struct intel_engine_coredump *ee, 339 struct i915_request *rq, 340 gfp_t gfp) 341 { 342 return NULL; 343 } 344 345 static inline void 346 intel_engine_coredump_add_vma(struct intel_engine_coredump *ee, 347 struct intel_engine_capture_vma *capture, 348 struct i915_vma_compress *compress) 349 { 350 } 351 352 static inline struct i915_vma_compress * 353 i915_vma_capture_prepare(struct intel_gt_coredump *gt) 354 { 355 return NULL; 356 } 357 358 static inline void 359 i915_vma_capture_finish(struct intel_gt_coredump *gt, 360 struct i915_vma_compress *compress) 361 { 362 } 363 364 static inline void 365 i915_error_state_store(struct i915_gpu_coredump *error) 366 { 367 } 368 369 static inline void i915_gpu_coredump_put(struct i915_gpu_coredump *gpu) 370 { 371 } 372 373 static inline struct i915_gpu_coredump * 374 i915_first_error_state(struct drm_i915_private *i915) 375 { 376 return ERR_PTR(-ENODEV); 377 } 378 379 static inline void i915_reset_error_state(struct drm_i915_private *i915) 380 { 381 } 382 383 static inline void i915_disable_error_state(struct drm_i915_private *i915, 384 int err) 385 { 386 } 387 388 #endif /* IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) */ 389 390 #endif /* _I915_GPU_ERROR_H_ */ 391