1 /* 2 * SPDX-License-Identifier: MIT 3 * 4 * Copyright � 2008-2018 Intel Corporation 5 */ 6 7 #ifndef _I915_GPU_ERROR_H_ 8 #define _I915_GPU_ERROR_H_ 9 10 #include <linux/atomic.h> 11 #include <linux/kref.h> 12 #include <linux/ktime.h> 13 #include <linux/sched.h> 14 15 #include <drm/drm_mm.h> 16 17 #include "gt/intel_engine.h" 18 #include "gt/uc/intel_uc_fw.h" 19 20 #include "intel_device_info.h" 21 22 #include "i915_gem.h" 23 #include "i915_gem_gtt.h" 24 #include "i915_params.h" 25 #include "i915_scheduler.h" 26 27 struct drm_i915_private; 28 struct intel_overlay_error_state; 29 struct intel_display_error_state; 30 31 struct i915_gpu_state { 32 struct kref ref; 33 ktime_t time; 34 ktime_t boottime; 35 ktime_t uptime; 36 unsigned long capture; 37 unsigned long epoch; 38 39 struct drm_i915_private *i915; 40 41 char error_msg[128]; 42 bool simulated; 43 bool awake; 44 bool wakelock; 45 bool suspended; 46 int iommu; 47 u32 reset_count; 48 u32 suspend_count; 49 struct intel_device_info device_info; 50 struct intel_runtime_info runtime_info; 51 struct intel_driver_caps driver_caps; 52 struct i915_params params; 53 54 struct i915_error_uc { 55 struct intel_uc_fw guc_fw; 56 struct intel_uc_fw huc_fw; 57 struct drm_i915_error_object *guc_log; 58 } uc; 59 60 /* Generic register state */ 61 u32 eir; 62 u32 pgtbl_er; 63 u32 ier; 64 u32 gtier[6], ngtier; 65 u32 ccid; 66 u32 derrmr; 67 u32 forcewake; 68 u32 error; /* gen6+ */ 69 u32 err_int; /* gen7 */ 70 u32 fault_data0; /* gen8, gen9 */ 71 u32 fault_data1; /* gen8, gen9 */ 72 u32 done_reg; 73 u32 gac_eco; 74 u32 gam_ecochk; 75 u32 gab_ctl; 76 u32 gfx_mode; 77 78 u32 nfence; 79 u64 fence[I915_MAX_NUM_FENCES]; 80 struct intel_overlay_error_state *overlay; 81 struct intel_display_error_state *display; 82 83 struct drm_i915_error_engine { 84 int engine_id; 85 /* Software tracked state */ 86 bool idle; 87 unsigned long hangcheck_timestamp; 88 int num_requests; 89 u32 reset_count; 90 91 /* position of active request inside the ring */ 92 u32 rq_head, rq_post, rq_tail; 93 94 /* our own tracking of ring head and tail */ 95 u32 cpu_ring_head; 96 u32 cpu_ring_tail; 97 98 /* Register state */ 99 u32 start; 100 u32 tail; 101 u32 head; 102 u32 ctl; 103 u32 mode; 104 u32 hws; 105 u32 ipeir; 106 u32 ipehr; 107 u32 bbstate; 108 u32 instpm; 109 u32 instps; 110 u64 bbaddr; 111 u64 acthd; 112 u32 fault_reg; 113 u64 faddr; 114 u32 rc_psmi; /* sleep state */ 115 struct intel_instdone instdone; 116 117 struct drm_i915_error_context { 118 char comm[TASK_COMM_LEN]; 119 pid_t pid; 120 u32 hw_id; 121 int active; 122 int guilty; 123 struct i915_sched_attr sched_attr; 124 } context; 125 126 struct drm_i915_error_object { 127 u64 gtt_offset; 128 u64 gtt_size; 129 int num_pages; 130 int page_count; 131 int unused; 132 u32 *pages[0]; 133 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page; 134 135 struct drm_i915_error_object **user_bo; 136 long user_bo_count; 137 138 struct drm_i915_error_object *wa_ctx; 139 struct drm_i915_error_object *default_state; 140 141 struct drm_i915_error_request { 142 unsigned long flags; 143 long jiffies; 144 pid_t pid; 145 u32 context; 146 u32 seqno; 147 u32 start; 148 u32 head; 149 u32 tail; 150 struct i915_sched_attr sched_attr; 151 } *requests, execlist[EXECLIST_MAX_PORTS]; 152 unsigned int num_ports; 153 154 struct { 155 u32 gfx_mode; 156 union { 157 u64 pdp[4]; 158 u32 pp_dir_base; 159 }; 160 } vm_info; 161 } engine[I915_NUM_ENGINES]; 162 163 struct scatterlist *sgl, *fit; 164 }; 165 166 struct i915_gpu_error { 167 /* For reset and error_state handling. */ 168 spinlock_t lock; 169 /* Protected by the above dev->gpu_error.lock. */ 170 struct i915_gpu_state *first_error; 171 172 atomic_t pending_fb_pin; 173 174 /** Number of times the device has been reset (global) */ 175 atomic_t reset_count; 176 177 /** Number of times an engine has been reset */ 178 atomic_t reset_engine_count[I915_NUM_ENGINES]; 179 }; 180 181 struct drm_i915_error_state_buf { 182 struct drm_i915_private *i915; 183 struct scatterlist *sgl, *cur, *end; 184 185 char *buf; 186 size_t bytes; 187 size_t size; 188 loff_t iter; 189 190 int err; 191 }; 192 193 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 194 195 __printf(2, 3) 196 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); 197 198 struct i915_gpu_state *i915_capture_gpu_state(struct drm_i915_private *i915); 199 void i915_capture_error_state(struct drm_i915_private *dev_priv, 200 intel_engine_mask_t engine_mask, 201 const char *error_msg); 202 203 static inline struct i915_gpu_state * 204 i915_gpu_state_get(struct i915_gpu_state *gpu) 205 { 206 kref_get(&gpu->ref); 207 return gpu; 208 } 209 210 ssize_t i915_gpu_state_copy_to_buffer(struct i915_gpu_state *error, 211 char *buf, loff_t offset, size_t count); 212 213 void __i915_gpu_state_free(struct kref *kref); 214 static inline void i915_gpu_state_put(struct i915_gpu_state *gpu) 215 { 216 if (gpu) 217 kref_put(&gpu->ref, __i915_gpu_state_free); 218 } 219 220 struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915); 221 void i915_reset_error_state(struct drm_i915_private *i915); 222 void i915_disable_error_state(struct drm_i915_private *i915, int err); 223 224 #else 225 226 static inline void i915_capture_error_state(struct drm_i915_private *dev_priv, 227 u32 engine_mask, 228 const char *error_msg) 229 { 230 } 231 232 static inline struct i915_gpu_state * 233 i915_first_error_state(struct drm_i915_private *i915) 234 { 235 return ERR_PTR(-ENODEV); 236 } 237 238 static inline void i915_reset_error_state(struct drm_i915_private *i915) 239 { 240 } 241 242 static inline void i915_disable_error_state(struct drm_i915_private *i915, 243 int err) 244 { 245 } 246 247 #endif /* IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) */ 248 249 #endif /* _I915_GPU_ERROR_H_ */ 250