1d897a111SMichal Wajdeczko /* 2d897a111SMichal Wajdeczko * SPDX-License-Identifier: MIT 3d897a111SMichal Wajdeczko * 4d897a111SMichal Wajdeczko * Copyright � 2008-2018 Intel Corporation 5d897a111SMichal Wajdeczko */ 6d897a111SMichal Wajdeczko 7d897a111SMichal Wajdeczko #ifndef _I915_GPU_ERROR_H_ 8d897a111SMichal Wajdeczko #define _I915_GPU_ERROR_H_ 9d897a111SMichal Wajdeczko 10d897a111SMichal Wajdeczko #include <linux/kref.h> 11d897a111SMichal Wajdeczko #include <linux/ktime.h> 12d897a111SMichal Wajdeczko #include <linux/sched.h> 13d897a111SMichal Wajdeczko 14d897a111SMichal Wajdeczko #include <drm/drm_mm.h> 15d897a111SMichal Wajdeczko 16d897a111SMichal Wajdeczko #include "intel_device_info.h" 17d897a111SMichal Wajdeczko #include "intel_ringbuffer.h" 18d897a111SMichal Wajdeczko #include "intel_uc_fw.h" 19d897a111SMichal Wajdeczko 20d897a111SMichal Wajdeczko #include "i915_gem.h" 21d897a111SMichal Wajdeczko #include "i915_gem_gtt.h" 22d897a111SMichal Wajdeczko #include "i915_params.h" 23d897a111SMichal Wajdeczko 24d897a111SMichal Wajdeczko struct drm_i915_private; 25d897a111SMichal Wajdeczko struct intel_overlay_error_state; 26d897a111SMichal Wajdeczko struct intel_display_error_state; 27d897a111SMichal Wajdeczko 28d897a111SMichal Wajdeczko struct i915_gpu_state { 29d897a111SMichal Wajdeczko struct kref ref; 30d897a111SMichal Wajdeczko ktime_t time; 31d897a111SMichal Wajdeczko ktime_t boottime; 32d897a111SMichal Wajdeczko ktime_t uptime; 33d897a111SMichal Wajdeczko 34d897a111SMichal Wajdeczko struct drm_i915_private *i915; 35d897a111SMichal Wajdeczko 36d897a111SMichal Wajdeczko char error_msg[128]; 37d897a111SMichal Wajdeczko bool simulated; 38d897a111SMichal Wajdeczko bool awake; 39d897a111SMichal Wajdeczko bool wakelock; 40d897a111SMichal Wajdeczko bool suspended; 41d897a111SMichal Wajdeczko int iommu; 42d897a111SMichal Wajdeczko u32 reset_count; 43d897a111SMichal Wajdeczko u32 suspend_count; 44d897a111SMichal Wajdeczko struct intel_device_info device_info; 45d897a111SMichal Wajdeczko struct intel_driver_caps driver_caps; 46d897a111SMichal Wajdeczko struct i915_params params; 47d897a111SMichal Wajdeczko 48d897a111SMichal Wajdeczko struct i915_error_uc { 49d897a111SMichal Wajdeczko struct intel_uc_fw guc_fw; 50d897a111SMichal Wajdeczko struct intel_uc_fw huc_fw; 51d897a111SMichal Wajdeczko struct drm_i915_error_object *guc_log; 52d897a111SMichal Wajdeczko } uc; 53d897a111SMichal Wajdeczko 54d897a111SMichal Wajdeczko /* Generic register state */ 55d897a111SMichal Wajdeczko u32 eir; 56d897a111SMichal Wajdeczko u32 pgtbl_er; 57d897a111SMichal Wajdeczko u32 ier; 58d897a111SMichal Wajdeczko u32 gtier[4], ngtier; 59d897a111SMichal Wajdeczko u32 ccid; 60d897a111SMichal Wajdeczko u32 derrmr; 61d897a111SMichal Wajdeczko u32 forcewake; 62d897a111SMichal Wajdeczko u32 error; /* gen6+ */ 63d897a111SMichal Wajdeczko u32 err_int; /* gen7 */ 64d897a111SMichal Wajdeczko u32 fault_data0; /* gen8, gen9 */ 65d897a111SMichal Wajdeczko u32 fault_data1; /* gen8, gen9 */ 66d897a111SMichal Wajdeczko u32 done_reg; 67d897a111SMichal Wajdeczko u32 gac_eco; 68d897a111SMichal Wajdeczko u32 gam_ecochk; 69d897a111SMichal Wajdeczko u32 gab_ctl; 70d897a111SMichal Wajdeczko u32 gfx_mode; 71d897a111SMichal Wajdeczko 72d897a111SMichal Wajdeczko u32 nfence; 73d897a111SMichal Wajdeczko u64 fence[I915_MAX_NUM_FENCES]; 74d897a111SMichal Wajdeczko struct intel_overlay_error_state *overlay; 75d897a111SMichal Wajdeczko struct intel_display_error_state *display; 76d897a111SMichal Wajdeczko 77d897a111SMichal Wajdeczko struct drm_i915_error_engine { 78d897a111SMichal Wajdeczko int engine_id; 79d897a111SMichal Wajdeczko /* Software tracked state */ 80d897a111SMichal Wajdeczko bool idle; 81d897a111SMichal Wajdeczko bool waiting; 82d897a111SMichal Wajdeczko int num_waiters; 83d897a111SMichal Wajdeczko unsigned long hangcheck_timestamp; 84d897a111SMichal Wajdeczko bool hangcheck_stalled; 85d897a111SMichal Wajdeczko enum intel_engine_hangcheck_action hangcheck_action; 86d897a111SMichal Wajdeczko struct i915_address_space *vm; 87d897a111SMichal Wajdeczko int num_requests; 88d897a111SMichal Wajdeczko u32 reset_count; 89d897a111SMichal Wajdeczko 90d897a111SMichal Wajdeczko /* position of active request inside the ring */ 91d897a111SMichal Wajdeczko u32 rq_head, rq_post, rq_tail; 92d897a111SMichal Wajdeczko 93d897a111SMichal Wajdeczko /* our own tracking of ring head and tail */ 94d897a111SMichal Wajdeczko u32 cpu_ring_head; 95d897a111SMichal Wajdeczko u32 cpu_ring_tail; 96d897a111SMichal Wajdeczko 97d897a111SMichal Wajdeczko u32 last_seqno; 98d897a111SMichal Wajdeczko 99d897a111SMichal Wajdeczko /* Register state */ 100d897a111SMichal Wajdeczko u32 start; 101d897a111SMichal Wajdeczko u32 tail; 102d897a111SMichal Wajdeczko u32 head; 103d897a111SMichal Wajdeczko u32 ctl; 104d897a111SMichal Wajdeczko u32 mode; 105d897a111SMichal Wajdeczko u32 hws; 106d897a111SMichal Wajdeczko u32 ipeir; 107d897a111SMichal Wajdeczko u32 ipehr; 108d897a111SMichal Wajdeczko u32 bbstate; 109d897a111SMichal Wajdeczko u32 instpm; 110d897a111SMichal Wajdeczko u32 instps; 111d897a111SMichal Wajdeczko u32 seqno; 112d897a111SMichal Wajdeczko u64 bbaddr; 113d897a111SMichal Wajdeczko u64 acthd; 114d897a111SMichal Wajdeczko u32 fault_reg; 115d897a111SMichal Wajdeczko u64 faddr; 116d897a111SMichal Wajdeczko u32 rc_psmi; /* sleep state */ 117d897a111SMichal Wajdeczko u32 semaphore_mboxes[I915_NUM_ENGINES - 1]; 118d897a111SMichal Wajdeczko struct intel_instdone instdone; 119d897a111SMichal Wajdeczko 120d897a111SMichal Wajdeczko struct drm_i915_error_context { 121d897a111SMichal Wajdeczko char comm[TASK_COMM_LEN]; 122d897a111SMichal Wajdeczko pid_t pid; 123d897a111SMichal Wajdeczko u32 handle; 124d897a111SMichal Wajdeczko u32 hw_id; 125d897a111SMichal Wajdeczko int priority; 126d897a111SMichal Wajdeczko int ban_score; 127d897a111SMichal Wajdeczko int active; 128d897a111SMichal Wajdeczko int guilty; 129d897a111SMichal Wajdeczko bool bannable; 130d897a111SMichal Wajdeczko } context; 131d897a111SMichal Wajdeczko 132d897a111SMichal Wajdeczko struct drm_i915_error_object { 133d897a111SMichal Wajdeczko u64 gtt_offset; 134d897a111SMichal Wajdeczko u64 gtt_size; 135d897a111SMichal Wajdeczko int page_count; 136d897a111SMichal Wajdeczko int unused; 137d897a111SMichal Wajdeczko u32 *pages[0]; 138d897a111SMichal Wajdeczko } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page; 139d897a111SMichal Wajdeczko 140d897a111SMichal Wajdeczko struct drm_i915_error_object **user_bo; 141d897a111SMichal Wajdeczko long user_bo_count; 142d897a111SMichal Wajdeczko 143d897a111SMichal Wajdeczko struct drm_i915_error_object *wa_ctx; 144d897a111SMichal Wajdeczko struct drm_i915_error_object *default_state; 145d897a111SMichal Wajdeczko 146d897a111SMichal Wajdeczko struct drm_i915_error_request { 147d897a111SMichal Wajdeczko long jiffies; 148d897a111SMichal Wajdeczko pid_t pid; 149d897a111SMichal Wajdeczko u32 context; 150d897a111SMichal Wajdeczko int priority; 151d897a111SMichal Wajdeczko int ban_score; 152d897a111SMichal Wajdeczko u32 seqno; 153d897a111SMichal Wajdeczko u32 head; 154d897a111SMichal Wajdeczko u32 tail; 155d897a111SMichal Wajdeczko } *requests, execlist[EXECLIST_MAX_PORTS]; 156d897a111SMichal Wajdeczko unsigned int num_ports; 157d897a111SMichal Wajdeczko 158d897a111SMichal Wajdeczko struct drm_i915_error_waiter { 159d897a111SMichal Wajdeczko char comm[TASK_COMM_LEN]; 160d897a111SMichal Wajdeczko pid_t pid; 161d897a111SMichal Wajdeczko u32 seqno; 162d897a111SMichal Wajdeczko } *waiters; 163d897a111SMichal Wajdeczko 164d897a111SMichal Wajdeczko struct { 165d897a111SMichal Wajdeczko u32 gfx_mode; 166d897a111SMichal Wajdeczko union { 167d897a111SMichal Wajdeczko u64 pdp[4]; 168d897a111SMichal Wajdeczko u32 pp_dir_base; 169d897a111SMichal Wajdeczko }; 170d897a111SMichal Wajdeczko } vm_info; 171d897a111SMichal Wajdeczko } engine[I915_NUM_ENGINES]; 172d897a111SMichal Wajdeczko 173d897a111SMichal Wajdeczko struct drm_i915_error_buffer { 174d897a111SMichal Wajdeczko u32 size; 175d897a111SMichal Wajdeczko u32 name; 176d897a111SMichal Wajdeczko u32 rseqno[I915_NUM_ENGINES], wseqno; 177d897a111SMichal Wajdeczko u64 gtt_offset; 178d897a111SMichal Wajdeczko u32 read_domains; 179d897a111SMichal Wajdeczko u32 write_domain; 180d897a111SMichal Wajdeczko s32 fence_reg:I915_MAX_NUM_FENCE_BITS; 181d897a111SMichal Wajdeczko u32 tiling:2; 182d897a111SMichal Wajdeczko u32 dirty:1; 183d897a111SMichal Wajdeczko u32 purgeable:1; 184d897a111SMichal Wajdeczko u32 userptr:1; 185d897a111SMichal Wajdeczko s32 engine:4; 186d897a111SMichal Wajdeczko u32 cache_level:3; 187d897a111SMichal Wajdeczko } *active_bo[I915_NUM_ENGINES], *pinned_bo; 188d897a111SMichal Wajdeczko u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count; 189d897a111SMichal Wajdeczko struct i915_address_space *active_vm[I915_NUM_ENGINES]; 190d897a111SMichal Wajdeczko }; 191d897a111SMichal Wajdeczko 192d897a111SMichal Wajdeczko struct i915_gpu_error { 193d897a111SMichal Wajdeczko /* For hangcheck timer */ 194d897a111SMichal Wajdeczko #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ 195d897a111SMichal Wajdeczko #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) 196d897a111SMichal Wajdeczko 197d897a111SMichal Wajdeczko struct delayed_work hangcheck_work; 198d897a111SMichal Wajdeczko 199d897a111SMichal Wajdeczko /* For reset and error_state handling. */ 200d897a111SMichal Wajdeczko spinlock_t lock; 201d897a111SMichal Wajdeczko /* Protected by the above dev->gpu_error.lock. */ 202d897a111SMichal Wajdeczko struct i915_gpu_state *first_error; 203d897a111SMichal Wajdeczko 204d897a111SMichal Wajdeczko atomic_t pending_fb_pin; 205d897a111SMichal Wajdeczko 206d897a111SMichal Wajdeczko unsigned long missed_irq_rings; 207d897a111SMichal Wajdeczko 208d897a111SMichal Wajdeczko /** 209d897a111SMichal Wajdeczko * State variable controlling the reset flow and count 210d897a111SMichal Wajdeczko * 211d897a111SMichal Wajdeczko * This is a counter which gets incremented when reset is triggered, 212d897a111SMichal Wajdeczko * 213d897a111SMichal Wajdeczko * Before the reset commences, the I915_RESET_BACKOFF bit is set 214d897a111SMichal Wajdeczko * meaning that any waiters holding onto the struct_mutex should 215d897a111SMichal Wajdeczko * relinquish the lock immediately in order for the reset to start. 216d897a111SMichal Wajdeczko * 217d897a111SMichal Wajdeczko * If reset is not completed successfully, the I915_WEDGE bit is 218d897a111SMichal Wajdeczko * set meaning that hardware is terminally sour and there is no 219d897a111SMichal Wajdeczko * recovery. All waiters on the reset_queue will be woken when 220d897a111SMichal Wajdeczko * that happens. 221d897a111SMichal Wajdeczko * 222d897a111SMichal Wajdeczko * This counter is used by the wait_seqno code to notice that reset 223d897a111SMichal Wajdeczko * event happened and it needs to restart the entire ioctl (since most 224d897a111SMichal Wajdeczko * likely the seqno it waited for won't ever signal anytime soon). 225d897a111SMichal Wajdeczko * 226d897a111SMichal Wajdeczko * This is important for lock-free wait paths, where no contended lock 227d897a111SMichal Wajdeczko * naturally enforces the correct ordering between the bail-out of the 228d897a111SMichal Wajdeczko * waiter and the gpu reset work code. 229d897a111SMichal Wajdeczko */ 230d897a111SMichal Wajdeczko unsigned long reset_count; 231d897a111SMichal Wajdeczko 232d897a111SMichal Wajdeczko /** 233d897a111SMichal Wajdeczko * flags: Control various stages of the GPU reset 234d897a111SMichal Wajdeczko * 235d897a111SMichal Wajdeczko * #I915_RESET_BACKOFF - When we start a reset, we want to stop any 236d897a111SMichal Wajdeczko * other users acquiring the struct_mutex. To do this we set the 237d897a111SMichal Wajdeczko * #I915_RESET_BACKOFF bit in the error flags when we detect a reset 238d897a111SMichal Wajdeczko * and then check for that bit before acquiring the struct_mutex (in 239d897a111SMichal Wajdeczko * i915_mutex_lock_interruptible()?). I915_RESET_BACKOFF serves a 240d897a111SMichal Wajdeczko * secondary role in preventing two concurrent global reset attempts. 241d897a111SMichal Wajdeczko * 242d897a111SMichal Wajdeczko * #I915_RESET_HANDOFF - To perform the actual GPU reset, we need the 243d897a111SMichal Wajdeczko * struct_mutex. We try to acquire the struct_mutex in the reset worker, 244d897a111SMichal Wajdeczko * but it may be held by some long running waiter (that we cannot 245d897a111SMichal Wajdeczko * interrupt without causing trouble). Once we are ready to do the GPU 246d897a111SMichal Wajdeczko * reset, we set the I915_RESET_HANDOFF bit and wakeup any waiters. If 247d897a111SMichal Wajdeczko * they already hold the struct_mutex and want to participate they can 248d897a111SMichal Wajdeczko * inspect the bit and do the reset directly, otherwise the worker 249d897a111SMichal Wajdeczko * waits for the struct_mutex. 250d897a111SMichal Wajdeczko * 251d897a111SMichal Wajdeczko * #I915_RESET_ENGINE[num_engines] - Since the driver doesn't need to 252d897a111SMichal Wajdeczko * acquire the struct_mutex to reset an engine, we need an explicit 253d897a111SMichal Wajdeczko * flag to prevent two concurrent reset attempts in the same engine. 254d897a111SMichal Wajdeczko * As the number of engines continues to grow, allocate the flags from 255d897a111SMichal Wajdeczko * the most significant bits. 256d897a111SMichal Wajdeczko * 257d897a111SMichal Wajdeczko * #I915_WEDGED - If reset fails and we can no longer use the GPU, 258d897a111SMichal Wajdeczko * we set the #I915_WEDGED bit. Prior to command submission, e.g. 259d897a111SMichal Wajdeczko * i915_request_alloc(), this bit is checked and the sequence 260d897a111SMichal Wajdeczko * aborted (with -EIO reported to userspace) if set. 261d897a111SMichal Wajdeczko */ 262d897a111SMichal Wajdeczko unsigned long flags; 263d897a111SMichal Wajdeczko #define I915_RESET_BACKOFF 0 264d897a111SMichal Wajdeczko #define I915_RESET_HANDOFF 1 265d897a111SMichal Wajdeczko #define I915_RESET_MODESET 2 266d897a111SMichal Wajdeczko #define I915_WEDGED (BITS_PER_LONG - 1) 267d897a111SMichal Wajdeczko #define I915_RESET_ENGINE (I915_WEDGED - I915_NUM_ENGINES) 268d897a111SMichal Wajdeczko 269d897a111SMichal Wajdeczko /** Number of times an engine has been reset */ 270d897a111SMichal Wajdeczko u32 reset_engine_count[I915_NUM_ENGINES]; 271d897a111SMichal Wajdeczko 272ce800754SChris Wilson /** Reason for the current *global* reset */ 273ce800754SChris Wilson const char *reason; 274ce800754SChris Wilson 275d897a111SMichal Wajdeczko /** 276d897a111SMichal Wajdeczko * Waitqueue to signal when a hang is detected. Used to for waiters 277d897a111SMichal Wajdeczko * to release the struct_mutex for the reset to procede. 278d897a111SMichal Wajdeczko */ 279d897a111SMichal Wajdeczko wait_queue_head_t wait_queue; 280d897a111SMichal Wajdeczko 281d897a111SMichal Wajdeczko /** 282d897a111SMichal Wajdeczko * Waitqueue to signal when the reset has completed. Used by clients 283d897a111SMichal Wajdeczko * that wait for dev_priv->mm.wedged to settle. 284d897a111SMichal Wajdeczko */ 285d897a111SMichal Wajdeczko wait_queue_head_t reset_queue; 286d897a111SMichal Wajdeczko 287d897a111SMichal Wajdeczko /* For missed irq/seqno simulation. */ 288d897a111SMichal Wajdeczko unsigned long test_irq_rings; 289d897a111SMichal Wajdeczko }; 290d897a111SMichal Wajdeczko 291d897a111SMichal Wajdeczko struct drm_i915_error_state_buf { 292d897a111SMichal Wajdeczko struct drm_i915_private *i915; 293d897a111SMichal Wajdeczko unsigned int bytes; 294d897a111SMichal Wajdeczko unsigned int size; 295d897a111SMichal Wajdeczko int err; 296d897a111SMichal Wajdeczko u8 *buf; 297d897a111SMichal Wajdeczko loff_t start; 298d897a111SMichal Wajdeczko loff_t pos; 299d897a111SMichal Wajdeczko }; 300d897a111SMichal Wajdeczko 301d897a111SMichal Wajdeczko #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 302d897a111SMichal Wajdeczko 303d897a111SMichal Wajdeczko __printf(2, 3) 304d897a111SMichal Wajdeczko void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); 305d897a111SMichal Wajdeczko int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, 306d897a111SMichal Wajdeczko const struct i915_gpu_state *gpu); 307d897a111SMichal Wajdeczko int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, 308d897a111SMichal Wajdeczko struct drm_i915_private *i915, 309d897a111SMichal Wajdeczko size_t count, loff_t pos); 310d897a111SMichal Wajdeczko 311d897a111SMichal Wajdeczko static inline void 312d897a111SMichal Wajdeczko i915_error_state_buf_release(struct drm_i915_error_state_buf *eb) 313d897a111SMichal Wajdeczko { 314d897a111SMichal Wajdeczko kfree(eb->buf); 315d897a111SMichal Wajdeczko } 316d897a111SMichal Wajdeczko 317d897a111SMichal Wajdeczko struct i915_gpu_state *i915_capture_gpu_state(struct drm_i915_private *i915); 318d897a111SMichal Wajdeczko void i915_capture_error_state(struct drm_i915_private *dev_priv, 319d897a111SMichal Wajdeczko u32 engine_mask, 320d897a111SMichal Wajdeczko const char *error_msg); 321d897a111SMichal Wajdeczko 322d897a111SMichal Wajdeczko static inline struct i915_gpu_state * 323d897a111SMichal Wajdeczko i915_gpu_state_get(struct i915_gpu_state *gpu) 324d897a111SMichal Wajdeczko { 325d897a111SMichal Wajdeczko kref_get(&gpu->ref); 326d897a111SMichal Wajdeczko return gpu; 327d897a111SMichal Wajdeczko } 328d897a111SMichal Wajdeczko 329d897a111SMichal Wajdeczko void __i915_gpu_state_free(struct kref *kref); 330d897a111SMichal Wajdeczko static inline void i915_gpu_state_put(struct i915_gpu_state *gpu) 331d897a111SMichal Wajdeczko { 332d897a111SMichal Wajdeczko if (gpu) 333d897a111SMichal Wajdeczko kref_put(&gpu->ref, __i915_gpu_state_free); 334d897a111SMichal Wajdeczko } 335d897a111SMichal Wajdeczko 336d897a111SMichal Wajdeczko struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915); 337d897a111SMichal Wajdeczko void i915_reset_error_state(struct drm_i915_private *i915); 338d897a111SMichal Wajdeczko 339d897a111SMichal Wajdeczko #else 340d897a111SMichal Wajdeczko 341d897a111SMichal Wajdeczko static inline void i915_capture_error_state(struct drm_i915_private *dev_priv, 342d897a111SMichal Wajdeczko u32 engine_mask, 343d897a111SMichal Wajdeczko const char *error_msg) 344d897a111SMichal Wajdeczko { 345d897a111SMichal Wajdeczko } 346d897a111SMichal Wajdeczko 347d897a111SMichal Wajdeczko static inline struct i915_gpu_state * 348d897a111SMichal Wajdeczko i915_first_error_state(struct drm_i915_private *i915) 349d897a111SMichal Wajdeczko { 350d897a111SMichal Wajdeczko return NULL; 351d897a111SMichal Wajdeczko } 352d897a111SMichal Wajdeczko 353d897a111SMichal Wajdeczko static inline void i915_reset_error_state(struct drm_i915_private *i915) 354d897a111SMichal Wajdeczko { 355d897a111SMichal Wajdeczko } 356d897a111SMichal Wajdeczko 357d897a111SMichal Wajdeczko #endif /* IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) */ 358d897a111SMichal Wajdeczko 359d897a111SMichal Wajdeczko #endif /* _I915_GPU_ERROR_H_ */ 360