1 /*
2  * Copyright (c) 2008 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Authors:
24  *    Eric Anholt <eric@anholt.net>
25  *    Keith Packard <keithp@keithp.com>
26  *    Mika Kuoppala <mika.kuoppala@intel.com>
27  *
28  */
29 
30 #include <linux/ascii85.h>
31 #include <linux/highmem.h>
32 #include <linux/nmi.h>
33 #include <linux/pagevec.h>
34 #include <linux/scatterlist.h>
35 #include <linux/string_helpers.h>
36 #include <linux/utsname.h>
37 #include <linux/zlib.h>
38 
39 #include <drm/drm_cache.h>
40 #include <drm/drm_print.h>
41 
42 #include "display/intel_dmc.h"
43 #include "display/intel_overlay.h"
44 
45 #include "gem/i915_gem_context.h"
46 #include "gem/i915_gem_lmem.h"
47 #include "gt/intel_engine_regs.h"
48 #include "gt/intel_gt.h"
49 #include "gt/intel_gt_mcr.h"
50 #include "gt/intel_gt_pm.h"
51 #include "gt/intel_gt_regs.h"
52 #include "gt/uc/intel_guc_capture.h"
53 
54 #include "i915_driver.h"
55 #include "i915_drv.h"
56 #include "i915_gpu_error.h"
57 #include "i915_memcpy.h"
58 #include "i915_scatterlist.h"
59 #include "i915_utils.h"
60 
61 #define ALLOW_FAIL (__GFP_KSWAPD_RECLAIM | __GFP_RETRY_MAYFAIL | __GFP_NOWARN)
62 #define ATOMIC_MAYFAIL (GFP_ATOMIC | __GFP_NOWARN)
63 
64 static void __sg_set_buf(struct scatterlist *sg,
65 			 void *addr, unsigned int len, loff_t it)
66 {
67 	sg->page_link = (unsigned long)virt_to_page(addr);
68 	sg->offset = offset_in_page(addr);
69 	sg->length = len;
70 	sg->dma_address = it;
71 }
72 
73 static bool __i915_error_grow(struct drm_i915_error_state_buf *e, size_t len)
74 {
75 	if (!len)
76 		return false;
77 
78 	if (e->bytes + len + 1 <= e->size)
79 		return true;
80 
81 	if (e->bytes) {
82 		__sg_set_buf(e->cur++, e->buf, e->bytes, e->iter);
83 		e->iter += e->bytes;
84 		e->buf = NULL;
85 		e->bytes = 0;
86 	}
87 
88 	if (e->cur == e->end) {
89 		struct scatterlist *sgl;
90 
91 		sgl = (typeof(sgl))__get_free_page(ALLOW_FAIL);
92 		if (!sgl) {
93 			e->err = -ENOMEM;
94 			return false;
95 		}
96 
97 		if (e->cur) {
98 			e->cur->offset = 0;
99 			e->cur->length = 0;
100 			e->cur->page_link =
101 				(unsigned long)sgl | SG_CHAIN;
102 		} else {
103 			e->sgl = sgl;
104 		}
105 
106 		e->cur = sgl;
107 		e->end = sgl + SG_MAX_SINGLE_ALLOC - 1;
108 	}
109 
110 	e->size = ALIGN(len + 1, SZ_64K);
111 	e->buf = kmalloc(e->size, ALLOW_FAIL);
112 	if (!e->buf) {
113 		e->size = PAGE_ALIGN(len + 1);
114 		e->buf = kmalloc(e->size, GFP_KERNEL);
115 	}
116 	if (!e->buf) {
117 		e->err = -ENOMEM;
118 		return false;
119 	}
120 
121 	return true;
122 }
123 
124 __printf(2, 0)
125 static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
126 			       const char *fmt, va_list args)
127 {
128 	va_list ap;
129 	int len;
130 
131 	if (e->err)
132 		return;
133 
134 	va_copy(ap, args);
135 	len = vsnprintf(NULL, 0, fmt, ap);
136 	va_end(ap);
137 	if (len <= 0) {
138 		e->err = len;
139 		return;
140 	}
141 
142 	if (!__i915_error_grow(e, len))
143 		return;
144 
145 	GEM_BUG_ON(e->bytes >= e->size);
146 	len = vscnprintf(e->buf + e->bytes, e->size - e->bytes, fmt, args);
147 	if (len < 0) {
148 		e->err = len;
149 		return;
150 	}
151 	e->bytes += len;
152 }
153 
154 static void i915_error_puts(struct drm_i915_error_state_buf *e, const char *str)
155 {
156 	unsigned len;
157 
158 	if (e->err || !str)
159 		return;
160 
161 	len = strlen(str);
162 	if (!__i915_error_grow(e, len))
163 		return;
164 
165 	GEM_BUG_ON(e->bytes + len > e->size);
166 	memcpy(e->buf + e->bytes, str, len);
167 	e->bytes += len;
168 }
169 
170 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
171 #define err_puts(e, s) i915_error_puts(e, s)
172 
173 static void __i915_printfn_error(struct drm_printer *p, struct va_format *vaf)
174 {
175 	i915_error_vprintf(p->arg, vaf->fmt, *vaf->va);
176 }
177 
178 static inline struct drm_printer
179 i915_error_printer(struct drm_i915_error_state_buf *e)
180 {
181 	struct drm_printer p = {
182 		.printfn = __i915_printfn_error,
183 		.arg = e,
184 	};
185 	return p;
186 }
187 
188 /* single threaded page allocator with a reserved stash for emergencies */
189 static void pool_fini(struct pagevec *pv)
190 {
191 	pagevec_release(pv);
192 }
193 
194 static int pool_refill(struct pagevec *pv, gfp_t gfp)
195 {
196 	while (pagevec_space(pv)) {
197 		struct page *p;
198 
199 		p = alloc_page(gfp);
200 		if (!p)
201 			return -ENOMEM;
202 
203 		pagevec_add(pv, p);
204 	}
205 
206 	return 0;
207 }
208 
209 static int pool_init(struct pagevec *pv, gfp_t gfp)
210 {
211 	int err;
212 
213 	pagevec_init(pv);
214 
215 	err = pool_refill(pv, gfp);
216 	if (err)
217 		pool_fini(pv);
218 
219 	return err;
220 }
221 
222 static void *pool_alloc(struct pagevec *pv, gfp_t gfp)
223 {
224 	struct page *p;
225 
226 	p = alloc_page(gfp);
227 	if (!p && pagevec_count(pv))
228 		p = pv->pages[--pv->nr];
229 
230 	return p ? page_address(p) : NULL;
231 }
232 
233 static void pool_free(struct pagevec *pv, void *addr)
234 {
235 	struct page *p = virt_to_page(addr);
236 
237 	if (pagevec_space(pv))
238 		pagevec_add(pv, p);
239 	else
240 		__free_page(p);
241 }
242 
243 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR
244 
245 struct i915_vma_compress {
246 	struct pagevec pool;
247 	struct z_stream_s zstream;
248 	void *tmp;
249 };
250 
251 static bool compress_init(struct i915_vma_compress *c)
252 {
253 	struct z_stream_s *zstream = &c->zstream;
254 
255 	if (pool_init(&c->pool, ALLOW_FAIL))
256 		return false;
257 
258 	zstream->workspace =
259 		kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL),
260 			ALLOW_FAIL);
261 	if (!zstream->workspace) {
262 		pool_fini(&c->pool);
263 		return false;
264 	}
265 
266 	c->tmp = NULL;
267 	if (i915_has_memcpy_from_wc())
268 		c->tmp = pool_alloc(&c->pool, ALLOW_FAIL);
269 
270 	return true;
271 }
272 
273 static bool compress_start(struct i915_vma_compress *c)
274 {
275 	struct z_stream_s *zstream = &c->zstream;
276 	void *workspace = zstream->workspace;
277 
278 	memset(zstream, 0, sizeof(*zstream));
279 	zstream->workspace = workspace;
280 
281 	return zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) == Z_OK;
282 }
283 
284 static void *compress_next_page(struct i915_vma_compress *c,
285 				struct i915_vma_coredump *dst)
286 {
287 	void *page_addr;
288 	struct page *page;
289 
290 	page_addr = pool_alloc(&c->pool, ALLOW_FAIL);
291 	if (!page_addr)
292 		return ERR_PTR(-ENOMEM);
293 
294 	page = virt_to_page(page_addr);
295 	list_add_tail(&page->lru, &dst->page_list);
296 	return page_addr;
297 }
298 
299 static int compress_page(struct i915_vma_compress *c,
300 			 void *src,
301 			 struct i915_vma_coredump *dst,
302 			 bool wc)
303 {
304 	struct z_stream_s *zstream = &c->zstream;
305 
306 	zstream->next_in = src;
307 	if (wc && c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))
308 		zstream->next_in = c->tmp;
309 	zstream->avail_in = PAGE_SIZE;
310 
311 	do {
312 		if (zstream->avail_out == 0) {
313 			zstream->next_out = compress_next_page(c, dst);
314 			if (IS_ERR(zstream->next_out))
315 				return PTR_ERR(zstream->next_out);
316 
317 			zstream->avail_out = PAGE_SIZE;
318 		}
319 
320 		if (zlib_deflate(zstream, Z_NO_FLUSH) != Z_OK)
321 			return -EIO;
322 
323 		cond_resched();
324 	} while (zstream->avail_in);
325 
326 	/* Fallback to uncompressed if we increase size? */
327 	if (0 && zstream->total_out > zstream->total_in)
328 		return -E2BIG;
329 
330 	return 0;
331 }
332 
333 static int compress_flush(struct i915_vma_compress *c,
334 			  struct i915_vma_coredump *dst)
335 {
336 	struct z_stream_s *zstream = &c->zstream;
337 
338 	do {
339 		switch (zlib_deflate(zstream, Z_FINISH)) {
340 		case Z_OK: /* more space requested */
341 			zstream->next_out = compress_next_page(c, dst);
342 			if (IS_ERR(zstream->next_out))
343 				return PTR_ERR(zstream->next_out);
344 
345 			zstream->avail_out = PAGE_SIZE;
346 			break;
347 
348 		case Z_STREAM_END:
349 			goto end;
350 
351 		default: /* any error */
352 			return -EIO;
353 		}
354 	} while (1);
355 
356 end:
357 	memset(zstream->next_out, 0, zstream->avail_out);
358 	dst->unused = zstream->avail_out;
359 	return 0;
360 }
361 
362 static void compress_finish(struct i915_vma_compress *c)
363 {
364 	zlib_deflateEnd(&c->zstream);
365 }
366 
367 static void compress_fini(struct i915_vma_compress *c)
368 {
369 	kfree(c->zstream.workspace);
370 	if (c->tmp)
371 		pool_free(&c->pool, c->tmp);
372 	pool_fini(&c->pool);
373 }
374 
375 static void err_compression_marker(struct drm_i915_error_state_buf *m)
376 {
377 	err_puts(m, ":");
378 }
379 
380 #else
381 
382 struct i915_vma_compress {
383 	struct pagevec pool;
384 };
385 
386 static bool compress_init(struct i915_vma_compress *c)
387 {
388 	return pool_init(&c->pool, ALLOW_FAIL) == 0;
389 }
390 
391 static bool compress_start(struct i915_vma_compress *c)
392 {
393 	return true;
394 }
395 
396 static int compress_page(struct i915_vma_compress *c,
397 			 void *src,
398 			 struct i915_vma_coredump *dst,
399 			 bool wc)
400 {
401 	void *ptr;
402 
403 	ptr = pool_alloc(&c->pool, ALLOW_FAIL);
404 	if (!ptr)
405 		return -ENOMEM;
406 
407 	if (!(wc && i915_memcpy_from_wc(ptr, src, PAGE_SIZE)))
408 		memcpy(ptr, src, PAGE_SIZE);
409 	list_add_tail(&virt_to_page(ptr)->lru, &dst->page_list);
410 	cond_resched();
411 
412 	return 0;
413 }
414 
415 static int compress_flush(struct i915_vma_compress *c,
416 			  struct i915_vma_coredump *dst)
417 {
418 	return 0;
419 }
420 
421 static void compress_finish(struct i915_vma_compress *c)
422 {
423 }
424 
425 static void compress_fini(struct i915_vma_compress *c)
426 {
427 	pool_fini(&c->pool);
428 }
429 
430 static void err_compression_marker(struct drm_i915_error_state_buf *m)
431 {
432 	err_puts(m, "~");
433 }
434 
435 #endif
436 
437 static void error_print_instdone(struct drm_i915_error_state_buf *m,
438 				 const struct intel_engine_coredump *ee)
439 {
440 	int slice;
441 	int subslice;
442 	int iter;
443 
444 	err_printf(m, "  INSTDONE: 0x%08x\n",
445 		   ee->instdone.instdone);
446 
447 	if (ee->engine->class != RENDER_CLASS || GRAPHICS_VER(m->i915) <= 3)
448 		return;
449 
450 	err_printf(m, "  SC_INSTDONE: 0x%08x\n",
451 		   ee->instdone.slice_common);
452 
453 	if (GRAPHICS_VER(m->i915) <= 6)
454 		return;
455 
456 	for_each_ss_steering(iter, ee->engine->gt, slice, subslice)
457 		err_printf(m, "  SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
458 			   slice, subslice,
459 			   ee->instdone.sampler[slice][subslice]);
460 
461 	for_each_ss_steering(iter, ee->engine->gt, slice, subslice)
462 		err_printf(m, "  ROW_INSTDONE[%d][%d]: 0x%08x\n",
463 			   slice, subslice,
464 			   ee->instdone.row[slice][subslice]);
465 
466 	if (GRAPHICS_VER(m->i915) < 12)
467 		return;
468 
469 	if (GRAPHICS_VER_FULL(m->i915) >= IP_VER(12, 55)) {
470 		for_each_ss_steering(iter, ee->engine->gt, slice, subslice)
471 			err_printf(m, "  GEOM_SVGUNIT_INSTDONE[%d][%d]: 0x%08x\n",
472 				   slice, subslice,
473 				   ee->instdone.geom_svg[slice][subslice]);
474 	}
475 
476 	err_printf(m, "  SC_INSTDONE_EXTRA: 0x%08x\n",
477 		   ee->instdone.slice_common_extra[0]);
478 	err_printf(m, "  SC_INSTDONE_EXTRA2: 0x%08x\n",
479 		   ee->instdone.slice_common_extra[1]);
480 }
481 
482 static void error_print_request(struct drm_i915_error_state_buf *m,
483 				const char *prefix,
484 				const struct i915_request_coredump *erq)
485 {
486 	if (!erq->seqno)
487 		return;
488 
489 	err_printf(m, "%s pid %d, seqno %8x:%08x%s%s, prio %d, head %08x, tail %08x\n",
490 		   prefix, erq->pid, erq->context, erq->seqno,
491 		   test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
492 			    &erq->flags) ? "!" : "",
493 		   test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
494 			    &erq->flags) ? "+" : "",
495 		   erq->sched_attr.priority,
496 		   erq->head, erq->tail);
497 }
498 
499 static void error_print_context(struct drm_i915_error_state_buf *m,
500 				const char *header,
501 				const struct i915_gem_context_coredump *ctx)
502 {
503 	err_printf(m, "%s%s[%d] prio %d, guilty %d active %d, runtime total %lluns, avg %lluns\n",
504 		   header, ctx->comm, ctx->pid, ctx->sched_attr.priority,
505 		   ctx->guilty, ctx->active,
506 		   ctx->total_runtime, ctx->avg_runtime);
507 }
508 
509 static struct i915_vma_coredump *
510 __find_vma(struct i915_vma_coredump *vma, const char *name)
511 {
512 	while (vma) {
513 		if (strcmp(vma->name, name) == 0)
514 			return vma;
515 		vma = vma->next;
516 	}
517 
518 	return NULL;
519 }
520 
521 struct i915_vma_coredump *
522 intel_gpu_error_find_batch(const struct intel_engine_coredump *ee)
523 {
524 	return __find_vma(ee->vma, "batch");
525 }
526 
527 static void error_print_engine(struct drm_i915_error_state_buf *m,
528 			       const struct intel_engine_coredump *ee)
529 {
530 	struct i915_vma_coredump *batch;
531 	int n;
532 
533 	err_printf(m, "%s command stream:\n", ee->engine->name);
534 	err_printf(m, "  CCID:  0x%08x\n", ee->ccid);
535 	err_printf(m, "  START: 0x%08x\n", ee->start);
536 	err_printf(m, "  HEAD:  0x%08x [0x%08x]\n", ee->head, ee->rq_head);
537 	err_printf(m, "  TAIL:  0x%08x [0x%08x, 0x%08x]\n",
538 		   ee->tail, ee->rq_post, ee->rq_tail);
539 	err_printf(m, "  CTL:   0x%08x\n", ee->ctl);
540 	err_printf(m, "  MODE:  0x%08x\n", ee->mode);
541 	err_printf(m, "  HWS:   0x%08x\n", ee->hws);
542 	err_printf(m, "  ACTHD: 0x%08x %08x\n",
543 		   (u32)(ee->acthd>>32), (u32)ee->acthd);
544 	err_printf(m, "  IPEIR: 0x%08x\n", ee->ipeir);
545 	err_printf(m, "  IPEHR: 0x%08x\n", ee->ipehr);
546 	err_printf(m, "  ESR:   0x%08x\n", ee->esr);
547 
548 	error_print_instdone(m, ee);
549 
550 	batch = intel_gpu_error_find_batch(ee);
551 	if (batch) {
552 		u64 start = batch->gtt_offset;
553 		u64 end = start + batch->gtt_size;
554 
555 		err_printf(m, "  batch: [0x%08x_%08x, 0x%08x_%08x]\n",
556 			   upper_32_bits(start), lower_32_bits(start),
557 			   upper_32_bits(end), lower_32_bits(end));
558 	}
559 	if (GRAPHICS_VER(m->i915) >= 4) {
560 		err_printf(m, "  BBADDR: 0x%08x_%08x\n",
561 			   (u32)(ee->bbaddr>>32), (u32)ee->bbaddr);
562 		err_printf(m, "  BB_STATE: 0x%08x\n", ee->bbstate);
563 		err_printf(m, "  INSTPS: 0x%08x\n", ee->instps);
564 	}
565 	err_printf(m, "  INSTPM: 0x%08x\n", ee->instpm);
566 	err_printf(m, "  FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),
567 		   lower_32_bits(ee->faddr));
568 	if (GRAPHICS_VER(m->i915) >= 6) {
569 		err_printf(m, "  RC PSMI: 0x%08x\n", ee->rc_psmi);
570 		err_printf(m, "  FAULT_REG: 0x%08x\n", ee->fault_reg);
571 	}
572 	if (GRAPHICS_VER(m->i915) >= 11) {
573 		err_printf(m, "  NOPID: 0x%08x\n", ee->nopid);
574 		err_printf(m, "  EXCC: 0x%08x\n", ee->excc);
575 		err_printf(m, "  CMD_CCTL: 0x%08x\n", ee->cmd_cctl);
576 		err_printf(m, "  CSCMDOP: 0x%08x\n", ee->cscmdop);
577 		err_printf(m, "  CTX_SR_CTL: 0x%08x\n", ee->ctx_sr_ctl);
578 		err_printf(m, "  DMA_FADDR_HI: 0x%08x\n", ee->dma_faddr_hi);
579 		err_printf(m, "  DMA_FADDR_LO: 0x%08x\n", ee->dma_faddr_lo);
580 	}
581 	if (HAS_PPGTT(m->i915)) {
582 		err_printf(m, "  GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
583 
584 		if (GRAPHICS_VER(m->i915) >= 8) {
585 			int i;
586 			for (i = 0; i < 4; i++)
587 				err_printf(m, "  PDP%d: 0x%016llx\n",
588 					   i, ee->vm_info.pdp[i]);
589 		} else {
590 			err_printf(m, "  PP_DIR_BASE: 0x%08x\n",
591 				   ee->vm_info.pp_dir_base);
592 		}
593 	}
594 
595 	for (n = 0; n < ee->num_ports; n++) {
596 		err_printf(m, "  ELSP[%d]:", n);
597 		error_print_request(m, " ", &ee->execlist[n]);
598 	}
599 }
600 
601 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
602 {
603 	va_list args;
604 
605 	va_start(args, f);
606 	i915_error_vprintf(e, f, args);
607 	va_end(args);
608 }
609 
610 void intel_gpu_error_print_vma(struct drm_i915_error_state_buf *m,
611 			       const struct intel_engine_cs *engine,
612 			       const struct i915_vma_coredump *vma)
613 {
614 	char out[ASCII85_BUFSZ];
615 	struct page *page;
616 
617 	if (!vma)
618 		return;
619 
620 	err_printf(m, "%s --- %s = 0x%08x %08x\n",
621 		   engine ? engine->name : "global", vma->name,
622 		   upper_32_bits(vma->gtt_offset),
623 		   lower_32_bits(vma->gtt_offset));
624 
625 	if (vma->gtt_page_sizes > I915_GTT_PAGE_SIZE_4K)
626 		err_printf(m, "gtt_page_sizes = 0x%08x\n", vma->gtt_page_sizes);
627 
628 	err_compression_marker(m);
629 	list_for_each_entry(page, &vma->page_list, lru) {
630 		int i, len;
631 		const u32 *addr = page_address(page);
632 
633 		len = PAGE_SIZE;
634 		if (page == list_last_entry(&vma->page_list, typeof(*page), lru))
635 			len -= vma->unused;
636 		len = ascii85_encode_len(len);
637 
638 		for (i = 0; i < len; i++)
639 			err_puts(m, ascii85_encode(addr[i], out));
640 	}
641 	err_puts(m, "\n");
642 }
643 
644 static void err_print_capabilities(struct drm_i915_error_state_buf *m,
645 				   struct i915_gpu_coredump *error)
646 {
647 	struct drm_printer p = i915_error_printer(m);
648 
649 	intel_device_info_print(&error->device_info, &error->runtime_info, &p);
650 	intel_driver_caps_print(&error->driver_caps, &p);
651 }
652 
653 static void err_print_params(struct drm_i915_error_state_buf *m,
654 			     const struct i915_params *params)
655 {
656 	struct drm_printer p = i915_error_printer(m);
657 
658 	i915_params_dump(params, &p);
659 }
660 
661 static void err_print_pciid(struct drm_i915_error_state_buf *m,
662 			    struct drm_i915_private *i915)
663 {
664 	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
665 
666 	err_printf(m, "PCI ID: 0x%04x\n", pdev->device);
667 	err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision);
668 	err_printf(m, "PCI Subsystem: %04x:%04x\n",
669 		   pdev->subsystem_vendor,
670 		   pdev->subsystem_device);
671 }
672 
673 static void err_print_guc_ctb(struct drm_i915_error_state_buf *m,
674 			      const char *name,
675 			      const struct intel_ctb_coredump *ctb)
676 {
677 	if (!ctb->size)
678 		return;
679 
680 	err_printf(m, "GuC %s CTB: raw: 0x%08X, 0x%08X/%08X, cached: 0x%08X/%08X, desc = 0x%08X, buf = 0x%08X x 0x%08X\n",
681 		   name, ctb->raw_status, ctb->raw_head, ctb->raw_tail,
682 		   ctb->head, ctb->tail, ctb->desc_offset, ctb->cmds_offset, ctb->size);
683 }
684 
685 static void err_print_uc(struct drm_i915_error_state_buf *m,
686 			 const struct intel_uc_coredump *error_uc)
687 {
688 	struct drm_printer p = i915_error_printer(m);
689 
690 	intel_uc_fw_dump(&error_uc->guc_fw, &p);
691 	intel_uc_fw_dump(&error_uc->huc_fw, &p);
692 	err_printf(m, "GuC timestamp: 0x%08x\n", error_uc->guc.timestamp);
693 	intel_gpu_error_print_vma(m, NULL, error_uc->guc.vma_log);
694 	err_printf(m, "GuC CTB fence: %d\n", error_uc->guc.last_fence);
695 	err_print_guc_ctb(m, "Send", error_uc->guc.ctb + 0);
696 	err_print_guc_ctb(m, "Recv", error_uc->guc.ctb + 1);
697 	intel_gpu_error_print_vma(m, NULL, error_uc->guc.vma_ctb);
698 }
699 
700 static void err_free_sgl(struct scatterlist *sgl)
701 {
702 	while (sgl) {
703 		struct scatterlist *sg;
704 
705 		for (sg = sgl; !sg_is_chain(sg); sg++) {
706 			kfree(sg_virt(sg));
707 			if (sg_is_last(sg))
708 				break;
709 		}
710 
711 		sg = sg_is_last(sg) ? NULL : sg_chain_ptr(sg);
712 		free_page((unsigned long)sgl);
713 		sgl = sg;
714 	}
715 }
716 
717 static void err_print_gt_info(struct drm_i915_error_state_buf *m,
718 			      struct intel_gt_coredump *gt)
719 {
720 	struct drm_printer p = i915_error_printer(m);
721 
722 	intel_gt_info_print(&gt->info, &p);
723 	intel_sseu_print_topology(gt->_gt->i915, &gt->info.sseu, &p);
724 }
725 
726 static void err_print_gt_display(struct drm_i915_error_state_buf *m,
727 				 struct intel_gt_coredump *gt)
728 {
729 	err_printf(m, "IER: 0x%08x\n", gt->ier);
730 	err_printf(m, "DERRMR: 0x%08x\n", gt->derrmr);
731 }
732 
733 static void err_print_gt_global_nonguc(struct drm_i915_error_state_buf *m,
734 				       struct intel_gt_coredump *gt)
735 {
736 	int i;
737 
738 	err_printf(m, "GT awake: %s\n", str_yes_no(gt->awake));
739 	err_printf(m, "CS timestamp frequency: %u Hz, %d ns\n",
740 		   gt->clock_frequency, gt->clock_period_ns);
741 	err_printf(m, "EIR: 0x%08x\n", gt->eir);
742 	err_printf(m, "PGTBL_ER: 0x%08x\n", gt->pgtbl_er);
743 
744 	for (i = 0; i < gt->ngtier; i++)
745 		err_printf(m, "GTIER[%d]: 0x%08x\n", i, gt->gtier[i]);
746 }
747 
748 static void err_print_gt_global(struct drm_i915_error_state_buf *m,
749 				struct intel_gt_coredump *gt)
750 {
751 	err_printf(m, "FORCEWAKE: 0x%08x\n", gt->forcewake);
752 
753 	if (IS_GRAPHICS_VER(m->i915, 6, 11)) {
754 		err_printf(m, "ERROR: 0x%08x\n", gt->error);
755 		err_printf(m, "DONE_REG: 0x%08x\n", gt->done_reg);
756 	}
757 
758 	if (GRAPHICS_VER(m->i915) >= 8)
759 		err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
760 			   gt->fault_data1, gt->fault_data0);
761 
762 	if (GRAPHICS_VER(m->i915) == 7)
763 		err_printf(m, "ERR_INT: 0x%08x\n", gt->err_int);
764 
765 	if (IS_GRAPHICS_VER(m->i915, 8, 11))
766 		err_printf(m, "GTT_CACHE_EN: 0x%08x\n", gt->gtt_cache);
767 
768 	if (GRAPHICS_VER(m->i915) == 12)
769 		err_printf(m, "AUX_ERR_DBG: 0x%08x\n", gt->aux_err);
770 
771 	if (GRAPHICS_VER(m->i915) >= 12) {
772 		int i;
773 
774 		for (i = 0; i < I915_MAX_SFC; i++) {
775 			/*
776 			 * SFC_DONE resides in the VD forcewake domain, so it
777 			 * only exists if the corresponding VCS engine is
778 			 * present.
779 			 */
780 			if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 ||
781 			    !HAS_ENGINE(gt->_gt, _VCS(i * 2)))
782 				continue;
783 
784 			err_printf(m, "  SFC_DONE[%d]: 0x%08x\n", i,
785 				   gt->sfc_done[i]);
786 		}
787 
788 		err_printf(m, "  GAM_DONE: 0x%08x\n", gt->gam_done);
789 	}
790 }
791 
792 static void err_print_gt_fences(struct drm_i915_error_state_buf *m,
793 				struct intel_gt_coredump *gt)
794 {
795 	int i;
796 
797 	for (i = 0; i < gt->nfence; i++)
798 		err_printf(m, "  fence[%d] = %08llx\n", i, gt->fence[i]);
799 }
800 
801 static void err_print_gt_engines(struct drm_i915_error_state_buf *m,
802 				 struct intel_gt_coredump *gt)
803 {
804 	const struct intel_engine_coredump *ee;
805 
806 	for (ee = gt->engine; ee; ee = ee->next) {
807 		const struct i915_vma_coredump *vma;
808 
809 		if (ee->guc_capture_node)
810 			intel_guc_capture_print_engine_node(m, ee);
811 		else
812 			error_print_engine(m, ee);
813 
814 		err_printf(m, "  hung: %u\n", ee->hung);
815 		err_printf(m, "  engine reset count: %u\n", ee->reset_count);
816 		error_print_context(m, "  Active context: ", &ee->context);
817 
818 		for (vma = ee->vma; vma; vma = vma->next)
819 			intel_gpu_error_print_vma(m, ee->engine, vma);
820 	}
821 
822 }
823 
824 static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
825 			       struct i915_gpu_coredump *error)
826 {
827 	const struct intel_engine_coredump *ee;
828 	struct timespec64 ts;
829 
830 	if (*error->error_msg)
831 		err_printf(m, "%s\n", error->error_msg);
832 	err_printf(m, "Kernel: %s %s\n",
833 		   init_utsname()->release,
834 		   init_utsname()->machine);
835 	err_printf(m, "Driver: %s\n", DRIVER_DATE);
836 	ts = ktime_to_timespec64(error->time);
837 	err_printf(m, "Time: %lld s %ld us\n",
838 		   (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
839 	ts = ktime_to_timespec64(error->boottime);
840 	err_printf(m, "Boottime: %lld s %ld us\n",
841 		   (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
842 	ts = ktime_to_timespec64(error->uptime);
843 	err_printf(m, "Uptime: %lld s %ld us\n",
844 		   (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
845 	err_printf(m, "Capture: %lu jiffies; %d ms ago\n",
846 		   error->capture, jiffies_to_msecs(jiffies - error->capture));
847 
848 	for (ee = error->gt ? error->gt->engine : NULL; ee; ee = ee->next)
849 		err_printf(m, "Active process (on ring %s): %s [%d]\n",
850 			   ee->engine->name,
851 			   ee->context.comm,
852 			   ee->context.pid);
853 
854 	err_printf(m, "Reset count: %u\n", error->reset_count);
855 	err_printf(m, "Suspend count: %u\n", error->suspend_count);
856 	err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform));
857 	err_printf(m, "Subplatform: 0x%x\n",
858 		   intel_subplatform(&error->runtime_info,
859 				     error->device_info.platform));
860 	err_print_pciid(m, m->i915);
861 
862 	err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
863 
864 	intel_dmc_print_error_state(m, m->i915);
865 
866 	err_printf(m, "RPM wakelock: %s\n", str_yes_no(error->wakelock));
867 	err_printf(m, "PM suspended: %s\n", str_yes_no(error->suspended));
868 
869 	if (error->gt) {
870 		bool print_guc_capture = false;
871 
872 		if (error->gt->uc && error->gt->uc->guc.is_guc_capture)
873 			print_guc_capture = true;
874 
875 		err_print_gt_display(m, error->gt);
876 		err_print_gt_global_nonguc(m, error->gt);
877 		err_print_gt_fences(m, error->gt);
878 
879 		/*
880 		 * GuC dumped global, eng-class and eng-instance registers together
881 		 * as part of engine state dump so we print in err_print_gt_engines
882 		 */
883 		if (!print_guc_capture)
884 			err_print_gt_global(m, error->gt);
885 
886 		err_print_gt_engines(m, error->gt);
887 
888 		if (error->gt->uc)
889 			err_print_uc(m, error->gt->uc);
890 
891 		err_print_gt_info(m, error->gt);
892 	}
893 
894 	if (error->overlay)
895 		intel_overlay_print_error_state(m, error->overlay);
896 
897 	err_print_capabilities(m, error);
898 	err_print_params(m, &error->params);
899 }
900 
901 static int err_print_to_sgl(struct i915_gpu_coredump *error)
902 {
903 	struct drm_i915_error_state_buf m;
904 
905 	if (IS_ERR(error))
906 		return PTR_ERR(error);
907 
908 	if (READ_ONCE(error->sgl))
909 		return 0;
910 
911 	memset(&m, 0, sizeof(m));
912 	m.i915 = error->i915;
913 
914 	__err_print_to_sgl(&m, error);
915 
916 	if (m.buf) {
917 		__sg_set_buf(m.cur++, m.buf, m.bytes, m.iter);
918 		m.bytes = 0;
919 		m.buf = NULL;
920 	}
921 	if (m.cur) {
922 		GEM_BUG_ON(m.end < m.cur);
923 		sg_mark_end(m.cur - 1);
924 	}
925 	GEM_BUG_ON(m.sgl && !m.cur);
926 
927 	if (m.err) {
928 		err_free_sgl(m.sgl);
929 		return m.err;
930 	}
931 
932 	if (cmpxchg(&error->sgl, NULL, m.sgl))
933 		err_free_sgl(m.sgl);
934 
935 	return 0;
936 }
937 
938 ssize_t i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error,
939 					 char *buf, loff_t off, size_t rem)
940 {
941 	struct scatterlist *sg;
942 	size_t count;
943 	loff_t pos;
944 	int err;
945 
946 	if (!error || !rem)
947 		return 0;
948 
949 	err = err_print_to_sgl(error);
950 	if (err)
951 		return err;
952 
953 	sg = READ_ONCE(error->fit);
954 	if (!sg || off < sg->dma_address)
955 		sg = error->sgl;
956 	if (!sg)
957 		return 0;
958 
959 	pos = sg->dma_address;
960 	count = 0;
961 	do {
962 		size_t len, start;
963 
964 		if (sg_is_chain(sg)) {
965 			sg = sg_chain_ptr(sg);
966 			GEM_BUG_ON(sg_is_chain(sg));
967 		}
968 
969 		len = sg->length;
970 		if (pos + len <= off) {
971 			pos += len;
972 			continue;
973 		}
974 
975 		start = sg->offset;
976 		if (pos < off) {
977 			GEM_BUG_ON(off - pos > len);
978 			len -= off - pos;
979 			start += off - pos;
980 			pos = off;
981 		}
982 
983 		len = min(len, rem);
984 		GEM_BUG_ON(!len || len > sg->length);
985 
986 		memcpy(buf, page_address(sg_page(sg)) + start, len);
987 
988 		count += len;
989 		pos += len;
990 
991 		buf += len;
992 		rem -= len;
993 		if (!rem) {
994 			WRITE_ONCE(error->fit, sg);
995 			break;
996 		}
997 	} while (!sg_is_last(sg++));
998 
999 	return count;
1000 }
1001 
1002 static void i915_vma_coredump_free(struct i915_vma_coredump *vma)
1003 {
1004 	while (vma) {
1005 		struct i915_vma_coredump *next = vma->next;
1006 		struct page *page, *n;
1007 
1008 		list_for_each_entry_safe(page, n, &vma->page_list, lru) {
1009 			list_del_init(&page->lru);
1010 			__free_page(page);
1011 		}
1012 
1013 		kfree(vma);
1014 		vma = next;
1015 	}
1016 }
1017 
1018 static void cleanup_params(struct i915_gpu_coredump *error)
1019 {
1020 	i915_params_free(&error->params);
1021 }
1022 
1023 static void cleanup_uc(struct intel_uc_coredump *uc)
1024 {
1025 	kfree(uc->guc_fw.file_selected.path);
1026 	kfree(uc->huc_fw.file_selected.path);
1027 	kfree(uc->guc_fw.file_wanted.path);
1028 	kfree(uc->huc_fw.file_wanted.path);
1029 	i915_vma_coredump_free(uc->guc.vma_log);
1030 	i915_vma_coredump_free(uc->guc.vma_ctb);
1031 
1032 	kfree(uc);
1033 }
1034 
1035 static void cleanup_gt(struct intel_gt_coredump *gt)
1036 {
1037 	while (gt->engine) {
1038 		struct intel_engine_coredump *ee = gt->engine;
1039 
1040 		gt->engine = ee->next;
1041 
1042 		i915_vma_coredump_free(ee->vma);
1043 		intel_guc_capture_free_node(ee);
1044 		kfree(ee);
1045 	}
1046 
1047 	if (gt->uc)
1048 		cleanup_uc(gt->uc);
1049 
1050 	kfree(gt);
1051 }
1052 
1053 void __i915_gpu_coredump_free(struct kref *error_ref)
1054 {
1055 	struct i915_gpu_coredump *error =
1056 		container_of(error_ref, typeof(*error), ref);
1057 
1058 	while (error->gt) {
1059 		struct intel_gt_coredump *gt = error->gt;
1060 
1061 		error->gt = gt->next;
1062 		cleanup_gt(gt);
1063 	}
1064 
1065 	kfree(error->overlay);
1066 
1067 	cleanup_params(error);
1068 
1069 	err_free_sgl(error->sgl);
1070 	kfree(error);
1071 }
1072 
1073 static struct i915_vma_coredump *
1074 i915_vma_coredump_create(const struct intel_gt *gt,
1075 			 const struct i915_vma_resource *vma_res,
1076 			 struct i915_vma_compress *compress,
1077 			 const char *name)
1078 
1079 {
1080 	struct i915_ggtt *ggtt = gt->ggtt;
1081 	const u64 slot = ggtt->error_capture.start;
1082 	struct i915_vma_coredump *dst;
1083 	struct sgt_iter iter;
1084 	int ret;
1085 
1086 	might_sleep();
1087 
1088 	if (!vma_res || !vma_res->bi.pages || !compress)
1089 		return NULL;
1090 
1091 	dst = kmalloc(sizeof(*dst), ALLOW_FAIL);
1092 	if (!dst)
1093 		return NULL;
1094 
1095 	if (!compress_start(compress)) {
1096 		kfree(dst);
1097 		return NULL;
1098 	}
1099 
1100 	INIT_LIST_HEAD(&dst->page_list);
1101 	strcpy(dst->name, name);
1102 	dst->next = NULL;
1103 
1104 	dst->gtt_offset = vma_res->start;
1105 	dst->gtt_size = vma_res->node_size;
1106 	dst->gtt_page_sizes = vma_res->page_sizes_gtt;
1107 	dst->unused = 0;
1108 
1109 	ret = -EINVAL;
1110 	if (drm_mm_node_allocated(&ggtt->error_capture)) {
1111 		void __iomem *s;
1112 		dma_addr_t dma;
1113 
1114 		for_each_sgt_daddr(dma, iter, vma_res->bi.pages) {
1115 			mutex_lock(&ggtt->error_mutex);
1116 			if (ggtt->vm.raw_insert_page)
1117 				ggtt->vm.raw_insert_page(&ggtt->vm, dma, slot,
1118 							 I915_CACHE_NONE, 0);
1119 			else
1120 				ggtt->vm.insert_page(&ggtt->vm, dma, slot,
1121 						     I915_CACHE_NONE, 0);
1122 			mb();
1123 
1124 			s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE);
1125 			ret = compress_page(compress,
1126 					    (void  __force *)s, dst,
1127 					    true);
1128 			io_mapping_unmap(s);
1129 
1130 			mb();
1131 			ggtt->vm.clear_range(&ggtt->vm, slot, PAGE_SIZE);
1132 			mutex_unlock(&ggtt->error_mutex);
1133 			if (ret)
1134 				break;
1135 		}
1136 	} else if (vma_res->bi.lmem) {
1137 		struct intel_memory_region *mem = vma_res->mr;
1138 		dma_addr_t dma;
1139 
1140 		for_each_sgt_daddr(dma, iter, vma_res->bi.pages) {
1141 			dma_addr_t offset = dma - mem->region.start;
1142 			void __iomem *s;
1143 
1144 			if (offset + PAGE_SIZE > mem->io_size) {
1145 				ret = -EINVAL;
1146 				break;
1147 			}
1148 
1149 			s = io_mapping_map_wc(&mem->iomap, offset, PAGE_SIZE);
1150 			ret = compress_page(compress,
1151 					    (void __force *)s, dst,
1152 					    true);
1153 			io_mapping_unmap(s);
1154 			if (ret)
1155 				break;
1156 		}
1157 	} else {
1158 		struct page *page;
1159 
1160 		for_each_sgt_page(page, iter, vma_res->bi.pages) {
1161 			void *s;
1162 
1163 			drm_clflush_pages(&page, 1);
1164 
1165 			s = kmap(page);
1166 			ret = compress_page(compress, s, dst, false);
1167 			kunmap(page);
1168 
1169 			drm_clflush_pages(&page, 1);
1170 
1171 			if (ret)
1172 				break;
1173 		}
1174 	}
1175 
1176 	if (ret || compress_flush(compress, dst)) {
1177 		struct page *page, *n;
1178 
1179 		list_for_each_entry_safe_reverse(page, n, &dst->page_list, lru) {
1180 			list_del_init(&page->lru);
1181 			pool_free(&compress->pool, page_address(page));
1182 		}
1183 
1184 		kfree(dst);
1185 		dst = NULL;
1186 	}
1187 	compress_finish(compress);
1188 
1189 	return dst;
1190 }
1191 
1192 static void gt_record_fences(struct intel_gt_coredump *gt)
1193 {
1194 	struct i915_ggtt *ggtt = gt->_gt->ggtt;
1195 	struct intel_uncore *uncore = gt->_gt->uncore;
1196 	int i;
1197 
1198 	if (GRAPHICS_VER(uncore->i915) >= 6) {
1199 		for (i = 0; i < ggtt->num_fences; i++)
1200 			gt->fence[i] =
1201 				intel_uncore_read64(uncore,
1202 						    FENCE_REG_GEN6_LO(i));
1203 	} else if (GRAPHICS_VER(uncore->i915) >= 4) {
1204 		for (i = 0; i < ggtt->num_fences; i++)
1205 			gt->fence[i] =
1206 				intel_uncore_read64(uncore,
1207 						    FENCE_REG_965_LO(i));
1208 	} else {
1209 		for (i = 0; i < ggtt->num_fences; i++)
1210 			gt->fence[i] =
1211 				intel_uncore_read(uncore, FENCE_REG(i));
1212 	}
1213 	gt->nfence = i;
1214 }
1215 
1216 static void engine_record_registers(struct intel_engine_coredump *ee)
1217 {
1218 	const struct intel_engine_cs *engine = ee->engine;
1219 	struct drm_i915_private *i915 = engine->i915;
1220 
1221 	if (GRAPHICS_VER(i915) >= 6) {
1222 		ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL);
1223 
1224 		if (GRAPHICS_VER(i915) >= 12)
1225 			ee->fault_reg = intel_uncore_read(engine->uncore,
1226 							  GEN12_RING_FAULT_REG);
1227 		else if (GRAPHICS_VER(i915) >= 8)
1228 			ee->fault_reg = intel_uncore_read(engine->uncore,
1229 							  GEN8_RING_FAULT_REG);
1230 		else
1231 			ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine);
1232 	}
1233 
1234 	if (GRAPHICS_VER(i915) >= 4) {
1235 		ee->esr = ENGINE_READ(engine, RING_ESR);
1236 		ee->faddr = ENGINE_READ(engine, RING_DMA_FADD);
1237 		ee->ipeir = ENGINE_READ(engine, RING_IPEIR);
1238 		ee->ipehr = ENGINE_READ(engine, RING_IPEHR);
1239 		ee->instps = ENGINE_READ(engine, RING_INSTPS);
1240 		ee->bbaddr = ENGINE_READ(engine, RING_BBADDR);
1241 		ee->ccid = ENGINE_READ(engine, CCID);
1242 		if (GRAPHICS_VER(i915) >= 8) {
1243 			ee->faddr |= (u64)ENGINE_READ(engine, RING_DMA_FADD_UDW) << 32;
1244 			ee->bbaddr |= (u64)ENGINE_READ(engine, RING_BBADDR_UDW) << 32;
1245 		}
1246 		ee->bbstate = ENGINE_READ(engine, RING_BBSTATE);
1247 	} else {
1248 		ee->faddr = ENGINE_READ(engine, DMA_FADD_I8XX);
1249 		ee->ipeir = ENGINE_READ(engine, IPEIR);
1250 		ee->ipehr = ENGINE_READ(engine, IPEHR);
1251 	}
1252 
1253 	if (GRAPHICS_VER(i915) >= 11) {
1254 		ee->cmd_cctl = ENGINE_READ(engine, RING_CMD_CCTL);
1255 		ee->cscmdop = ENGINE_READ(engine, RING_CSCMDOP);
1256 		ee->ctx_sr_ctl = ENGINE_READ(engine, RING_CTX_SR_CTL);
1257 		ee->dma_faddr_hi = ENGINE_READ(engine, RING_DMA_FADD_UDW);
1258 		ee->dma_faddr_lo = ENGINE_READ(engine, RING_DMA_FADD);
1259 		ee->nopid = ENGINE_READ(engine, RING_NOPID);
1260 		ee->excc = ENGINE_READ(engine, RING_EXCC);
1261 	}
1262 
1263 	intel_engine_get_instdone(engine, &ee->instdone);
1264 
1265 	ee->instpm = ENGINE_READ(engine, RING_INSTPM);
1266 	ee->acthd = intel_engine_get_active_head(engine);
1267 	ee->start = ENGINE_READ(engine, RING_START);
1268 	ee->head = ENGINE_READ(engine, RING_HEAD);
1269 	ee->tail = ENGINE_READ(engine, RING_TAIL);
1270 	ee->ctl = ENGINE_READ(engine, RING_CTL);
1271 	if (GRAPHICS_VER(i915) > 2)
1272 		ee->mode = ENGINE_READ(engine, RING_MI_MODE);
1273 
1274 	if (!HWS_NEEDS_PHYSICAL(i915)) {
1275 		i915_reg_t mmio;
1276 
1277 		if (GRAPHICS_VER(i915) == 7) {
1278 			switch (engine->id) {
1279 			default:
1280 				MISSING_CASE(engine->id);
1281 				fallthrough;
1282 			case RCS0:
1283 				mmio = RENDER_HWS_PGA_GEN7;
1284 				break;
1285 			case BCS0:
1286 				mmio = BLT_HWS_PGA_GEN7;
1287 				break;
1288 			case VCS0:
1289 				mmio = BSD_HWS_PGA_GEN7;
1290 				break;
1291 			case VECS0:
1292 				mmio = VEBOX_HWS_PGA_GEN7;
1293 				break;
1294 			}
1295 		} else if (GRAPHICS_VER(engine->i915) == 6) {
1296 			mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
1297 		} else {
1298 			/* XXX: gen8 returns to sanity */
1299 			mmio = RING_HWS_PGA(engine->mmio_base);
1300 		}
1301 
1302 		ee->hws = intel_uncore_read(engine->uncore, mmio);
1303 	}
1304 
1305 	ee->reset_count = i915_reset_engine_count(&i915->gpu_error, engine);
1306 
1307 	if (HAS_PPGTT(i915)) {
1308 		int i;
1309 
1310 		ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7);
1311 
1312 		if (GRAPHICS_VER(i915) == 6) {
1313 			ee->vm_info.pp_dir_base =
1314 				ENGINE_READ(engine, RING_PP_DIR_BASE_READ);
1315 		} else if (GRAPHICS_VER(i915) == 7) {
1316 			ee->vm_info.pp_dir_base =
1317 				ENGINE_READ(engine, RING_PP_DIR_BASE);
1318 		} else if (GRAPHICS_VER(i915) >= 8) {
1319 			u32 base = engine->mmio_base;
1320 
1321 			for (i = 0; i < 4; i++) {
1322 				ee->vm_info.pdp[i] =
1323 					intel_uncore_read(engine->uncore,
1324 							  GEN8_RING_PDP_UDW(base, i));
1325 				ee->vm_info.pdp[i] <<= 32;
1326 				ee->vm_info.pdp[i] |=
1327 					intel_uncore_read(engine->uncore,
1328 							  GEN8_RING_PDP_LDW(base, i));
1329 			}
1330 		}
1331 	}
1332 }
1333 
1334 static void record_request(const struct i915_request *request,
1335 			   struct i915_request_coredump *erq)
1336 {
1337 	erq->flags = request->fence.flags;
1338 	erq->context = request->fence.context;
1339 	erq->seqno = request->fence.seqno;
1340 	erq->sched_attr = request->sched.attr;
1341 	erq->head = request->head;
1342 	erq->tail = request->tail;
1343 
1344 	erq->pid = 0;
1345 	rcu_read_lock();
1346 	if (!intel_context_is_closed(request->context)) {
1347 		const struct i915_gem_context *ctx;
1348 
1349 		ctx = rcu_dereference(request->context->gem_context);
1350 		if (ctx)
1351 			erq->pid = pid_nr(ctx->pid);
1352 	}
1353 	rcu_read_unlock();
1354 }
1355 
1356 static void engine_record_execlists(struct intel_engine_coredump *ee)
1357 {
1358 	const struct intel_engine_execlists * const el = &ee->engine->execlists;
1359 	struct i915_request * const *port = el->active;
1360 	unsigned int n = 0;
1361 
1362 	while (*port)
1363 		record_request(*port++, &ee->execlist[n++]);
1364 
1365 	ee->num_ports = n;
1366 }
1367 
1368 static bool record_context(struct i915_gem_context_coredump *e,
1369 			   const struct i915_request *rq)
1370 {
1371 	struct i915_gem_context *ctx;
1372 	struct task_struct *task;
1373 	bool simulated;
1374 
1375 	rcu_read_lock();
1376 	ctx = rcu_dereference(rq->context->gem_context);
1377 	if (ctx && !kref_get_unless_zero(&ctx->ref))
1378 		ctx = NULL;
1379 	rcu_read_unlock();
1380 	if (!ctx)
1381 		return true;
1382 
1383 	rcu_read_lock();
1384 	task = pid_task(ctx->pid, PIDTYPE_PID);
1385 	if (task) {
1386 		strcpy(e->comm, task->comm);
1387 		e->pid = task->pid;
1388 	}
1389 	rcu_read_unlock();
1390 
1391 	e->sched_attr = ctx->sched;
1392 	e->guilty = atomic_read(&ctx->guilty_count);
1393 	e->active = atomic_read(&ctx->active_count);
1394 
1395 	e->total_runtime = intel_context_get_total_runtime_ns(rq->context);
1396 	e->avg_runtime = intel_context_get_avg_runtime_ns(rq->context);
1397 
1398 	simulated = i915_gem_context_no_error_capture(ctx);
1399 
1400 	i915_gem_context_put(ctx);
1401 	return simulated;
1402 }
1403 
1404 struct intel_engine_capture_vma {
1405 	struct intel_engine_capture_vma *next;
1406 	struct i915_vma_resource *vma_res;
1407 	char name[16];
1408 	bool lockdep_cookie;
1409 };
1410 
1411 static struct intel_engine_capture_vma *
1412 capture_vma_snapshot(struct intel_engine_capture_vma *next,
1413 		     struct i915_vma_resource *vma_res,
1414 		     gfp_t gfp, const char *name)
1415 {
1416 	struct intel_engine_capture_vma *c;
1417 
1418 	if (!vma_res)
1419 		return next;
1420 
1421 	c = kmalloc(sizeof(*c), gfp);
1422 	if (!c)
1423 		return next;
1424 
1425 	if (!i915_vma_resource_hold(vma_res, &c->lockdep_cookie)) {
1426 		kfree(c);
1427 		return next;
1428 	}
1429 
1430 	strcpy(c->name, name);
1431 	c->vma_res = i915_vma_resource_get(vma_res);
1432 
1433 	c->next = next;
1434 	return c;
1435 }
1436 
1437 static struct intel_engine_capture_vma *
1438 capture_vma(struct intel_engine_capture_vma *next,
1439 	    struct i915_vma *vma,
1440 	    const char *name,
1441 	    gfp_t gfp)
1442 {
1443 	if (!vma)
1444 		return next;
1445 
1446 	/*
1447 	 * If the vma isn't pinned, then the vma should be snapshotted
1448 	 * to a struct i915_vma_snapshot at command submission time.
1449 	 * Not here.
1450 	 */
1451 	if (GEM_WARN_ON(!i915_vma_is_pinned(vma)))
1452 		return next;
1453 
1454 	next = capture_vma_snapshot(next, vma->resource, gfp, name);
1455 
1456 	return next;
1457 }
1458 
1459 static struct intel_engine_capture_vma *
1460 capture_user(struct intel_engine_capture_vma *capture,
1461 	     const struct i915_request *rq,
1462 	     gfp_t gfp)
1463 {
1464 	struct i915_capture_list *c;
1465 
1466 	for (c = rq->capture_list; c; c = c->next)
1467 		capture = capture_vma_snapshot(capture, c->vma_res, gfp,
1468 					       "user");
1469 
1470 	return capture;
1471 }
1472 
1473 static void add_vma(struct intel_engine_coredump *ee,
1474 		    struct i915_vma_coredump *vma)
1475 {
1476 	if (vma) {
1477 		vma->next = ee->vma;
1478 		ee->vma = vma;
1479 	}
1480 }
1481 
1482 static struct i915_vma_coredump *
1483 create_vma_coredump(const struct intel_gt *gt, struct i915_vma *vma,
1484 		    const char *name, struct i915_vma_compress *compress)
1485 {
1486 	struct i915_vma_coredump *ret = NULL;
1487 	struct i915_vma_resource *vma_res;
1488 	bool lockdep_cookie;
1489 
1490 	if (!vma)
1491 		return NULL;
1492 
1493 	vma_res = vma->resource;
1494 
1495 	if (i915_vma_resource_hold(vma_res, &lockdep_cookie)) {
1496 		ret = i915_vma_coredump_create(gt, vma_res, compress, name);
1497 		i915_vma_resource_unhold(vma_res, lockdep_cookie);
1498 	}
1499 
1500 	return ret;
1501 }
1502 
1503 static void add_vma_coredump(struct intel_engine_coredump *ee,
1504 			     const struct intel_gt *gt,
1505 			     struct i915_vma *vma,
1506 			     const char *name,
1507 			     struct i915_vma_compress *compress)
1508 {
1509 	add_vma(ee, create_vma_coredump(gt, vma, name, compress));
1510 }
1511 
1512 struct intel_engine_coredump *
1513 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp, u32 dump_flags)
1514 {
1515 	struct intel_engine_coredump *ee;
1516 
1517 	ee = kzalloc(sizeof(*ee), gfp);
1518 	if (!ee)
1519 		return NULL;
1520 
1521 	ee->engine = engine;
1522 
1523 	if (!(dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE)) {
1524 		engine_record_registers(ee);
1525 		engine_record_execlists(ee);
1526 	}
1527 
1528 	return ee;
1529 }
1530 
1531 struct intel_engine_capture_vma *
1532 intel_engine_coredump_add_request(struct intel_engine_coredump *ee,
1533 				  struct i915_request *rq,
1534 				  gfp_t gfp)
1535 {
1536 	struct intel_engine_capture_vma *vma = NULL;
1537 
1538 	ee->simulated |= record_context(&ee->context, rq);
1539 	if (ee->simulated)
1540 		return NULL;
1541 
1542 	/*
1543 	 * We need to copy these to an anonymous buffer
1544 	 * as the simplest method to avoid being overwritten
1545 	 * by userspace.
1546 	 */
1547 	vma = capture_vma_snapshot(vma, rq->batch_res, gfp, "batch");
1548 	vma = capture_user(vma, rq, gfp);
1549 	vma = capture_vma(vma, rq->ring->vma, "ring", gfp);
1550 	vma = capture_vma(vma, rq->context->state, "HW context", gfp);
1551 
1552 	ee->rq_head = rq->head;
1553 	ee->rq_post = rq->postfix;
1554 	ee->rq_tail = rq->tail;
1555 
1556 	return vma;
1557 }
1558 
1559 void
1560 intel_engine_coredump_add_vma(struct intel_engine_coredump *ee,
1561 			      struct intel_engine_capture_vma *capture,
1562 			      struct i915_vma_compress *compress)
1563 {
1564 	const struct intel_engine_cs *engine = ee->engine;
1565 
1566 	while (capture) {
1567 		struct intel_engine_capture_vma *this = capture;
1568 		struct i915_vma_resource *vma_res = this->vma_res;
1569 
1570 		add_vma(ee,
1571 			i915_vma_coredump_create(engine->gt, vma_res,
1572 						 compress, this->name));
1573 
1574 		i915_vma_resource_unhold(vma_res, this->lockdep_cookie);
1575 		i915_vma_resource_put(vma_res);
1576 
1577 		capture = this->next;
1578 		kfree(this);
1579 	}
1580 
1581 	add_vma_coredump(ee, engine->gt, engine->status_page.vma,
1582 			 "HW Status", compress);
1583 
1584 	add_vma_coredump(ee, engine->gt, engine->wa_ctx.vma,
1585 			 "WA context", compress);
1586 }
1587 
1588 static struct intel_engine_coredump *
1589 capture_engine(struct intel_engine_cs *engine,
1590 	       struct i915_vma_compress *compress,
1591 	       u32 dump_flags)
1592 {
1593 	struct intel_engine_capture_vma *capture = NULL;
1594 	struct intel_engine_coredump *ee;
1595 	struct intel_context *ce;
1596 	struct i915_request *rq = NULL;
1597 	unsigned long flags;
1598 
1599 	ee = intel_engine_coredump_alloc(engine, ALLOW_FAIL, dump_flags);
1600 	if (!ee)
1601 		return NULL;
1602 
1603 	ce = intel_engine_get_hung_context(engine);
1604 	if (ce) {
1605 		intel_engine_clear_hung_context(engine);
1606 		rq = intel_context_find_active_request(ce);
1607 		if (!rq || !i915_request_started(rq))
1608 			goto no_request_capture;
1609 	} else {
1610 		/*
1611 		 * Getting here with GuC enabled means it is a forced error capture
1612 		 * with no actual hang. So, no need to attempt the execlist search.
1613 		 */
1614 		if (!intel_uc_uses_guc_submission(&engine->gt->uc)) {
1615 			spin_lock_irqsave(&engine->sched_engine->lock, flags);
1616 			rq = intel_engine_execlist_find_hung_request(engine);
1617 			spin_unlock_irqrestore(&engine->sched_engine->lock,
1618 					       flags);
1619 		}
1620 	}
1621 	if (rq)
1622 		rq = i915_request_get_rcu(rq);
1623 
1624 	if (!rq)
1625 		goto no_request_capture;
1626 
1627 	capture = intel_engine_coredump_add_request(ee, rq, ATOMIC_MAYFAIL);
1628 	if (!capture) {
1629 		i915_request_put(rq);
1630 		goto no_request_capture;
1631 	}
1632 	if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE)
1633 		intel_guc_capture_get_matching_node(engine->gt, ee, ce);
1634 
1635 	intel_engine_coredump_add_vma(ee, capture, compress);
1636 	i915_request_put(rq);
1637 
1638 	return ee;
1639 
1640 no_request_capture:
1641 	kfree(ee);
1642 	return NULL;
1643 }
1644 
1645 static void
1646 gt_record_engines(struct intel_gt_coredump *gt,
1647 		  intel_engine_mask_t engine_mask,
1648 		  struct i915_vma_compress *compress,
1649 		  u32 dump_flags)
1650 {
1651 	struct intel_engine_cs *engine;
1652 	enum intel_engine_id id;
1653 
1654 	for_each_engine(engine, gt->_gt, id) {
1655 		struct intel_engine_coredump *ee;
1656 
1657 		/* Refill our page pool before entering atomic section */
1658 		pool_refill(&compress->pool, ALLOW_FAIL);
1659 
1660 		ee = capture_engine(engine, compress, dump_flags);
1661 		if (!ee)
1662 			continue;
1663 
1664 		ee->hung = engine->mask & engine_mask;
1665 
1666 		gt->simulated |= ee->simulated;
1667 		if (ee->simulated) {
1668 			if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE)
1669 				intel_guc_capture_free_node(ee);
1670 			kfree(ee);
1671 			continue;
1672 		}
1673 
1674 		ee->next = gt->engine;
1675 		gt->engine = ee;
1676 	}
1677 }
1678 
1679 static void gt_record_guc_ctb(struct intel_ctb_coredump *saved,
1680 			      const struct intel_guc_ct_buffer *ctb,
1681 			      const void *blob_ptr, struct intel_guc *guc)
1682 {
1683 	if (!ctb || !ctb->desc)
1684 		return;
1685 
1686 	saved->raw_status = ctb->desc->status;
1687 	saved->raw_head = ctb->desc->head;
1688 	saved->raw_tail = ctb->desc->tail;
1689 	saved->head = ctb->head;
1690 	saved->tail = ctb->tail;
1691 	saved->size = ctb->size;
1692 	saved->desc_offset = ((void *)ctb->desc) - blob_ptr;
1693 	saved->cmds_offset = ((void *)ctb->cmds) - blob_ptr;
1694 }
1695 
1696 static struct intel_uc_coredump *
1697 gt_record_uc(struct intel_gt_coredump *gt,
1698 	     struct i915_vma_compress *compress)
1699 {
1700 	const struct intel_uc *uc = &gt->_gt->uc;
1701 	struct intel_uc_coredump *error_uc;
1702 
1703 	error_uc = kzalloc(sizeof(*error_uc), ALLOW_FAIL);
1704 	if (!error_uc)
1705 		return NULL;
1706 
1707 	memcpy(&error_uc->guc_fw, &uc->guc.fw, sizeof(uc->guc.fw));
1708 	memcpy(&error_uc->huc_fw, &uc->huc.fw, sizeof(uc->huc.fw));
1709 
1710 	error_uc->guc_fw.file_selected.path = kstrdup(uc->guc.fw.file_selected.path, ALLOW_FAIL);
1711 	error_uc->huc_fw.file_selected.path = kstrdup(uc->huc.fw.file_selected.path, ALLOW_FAIL);
1712 	error_uc->guc_fw.file_wanted.path = kstrdup(uc->guc.fw.file_wanted.path, ALLOW_FAIL);
1713 	error_uc->huc_fw.file_wanted.path = kstrdup(uc->huc.fw.file_wanted.path, ALLOW_FAIL);
1714 
1715 	/*
1716 	 * Save the GuC log and include a timestamp reference for converting the
1717 	 * log times to system times (in conjunction with the error->boottime and
1718 	 * gt->clock_frequency fields saved elsewhere).
1719 	 */
1720 	error_uc->guc.timestamp = intel_uncore_read(gt->_gt->uncore, GUCPMTIMESTAMP);
1721 	error_uc->guc.vma_log = create_vma_coredump(gt->_gt, uc->guc.log.vma,
1722 						    "GuC log buffer", compress);
1723 	error_uc->guc.vma_ctb = create_vma_coredump(gt->_gt, uc->guc.ct.vma,
1724 						    "GuC CT buffer", compress);
1725 	error_uc->guc.last_fence = uc->guc.ct.requests.last_fence;
1726 	gt_record_guc_ctb(error_uc->guc.ctb + 0, &uc->guc.ct.ctbs.send,
1727 			  uc->guc.ct.ctbs.send.desc, (struct intel_guc *)&uc->guc);
1728 	gt_record_guc_ctb(error_uc->guc.ctb + 1, &uc->guc.ct.ctbs.recv,
1729 			  uc->guc.ct.ctbs.send.desc, (struct intel_guc *)&uc->guc);
1730 
1731 	return error_uc;
1732 }
1733 
1734 /* Capture display registers. */
1735 static void gt_record_display_regs(struct intel_gt_coredump *gt)
1736 {
1737 	struct intel_uncore *uncore = gt->_gt->uncore;
1738 	struct drm_i915_private *i915 = uncore->i915;
1739 
1740 	if (GRAPHICS_VER(i915) >= 6)
1741 		gt->derrmr = intel_uncore_read(uncore, DERRMR);
1742 
1743 	if (GRAPHICS_VER(i915) >= 8)
1744 		gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER);
1745 	else if (IS_VALLEYVIEW(i915))
1746 		gt->ier = intel_uncore_read(uncore, VLV_IER);
1747 	else if (HAS_PCH_SPLIT(i915))
1748 		gt->ier = intel_uncore_read(uncore, DEIER);
1749 	else if (GRAPHICS_VER(i915) == 2)
1750 		gt->ier = intel_uncore_read16(uncore, GEN2_IER);
1751 	else
1752 		gt->ier = intel_uncore_read(uncore, GEN2_IER);
1753 }
1754 
1755 /* Capture all other registers that GuC doesn't capture. */
1756 static void gt_record_global_nonguc_regs(struct intel_gt_coredump *gt)
1757 {
1758 	struct intel_uncore *uncore = gt->_gt->uncore;
1759 	struct drm_i915_private *i915 = uncore->i915;
1760 	int i;
1761 
1762 	if (IS_VALLEYVIEW(i915)) {
1763 		gt->gtier[0] = intel_uncore_read(uncore, GTIER);
1764 		gt->ngtier = 1;
1765 	} else if (GRAPHICS_VER(i915) >= 11) {
1766 		gt->gtier[0] =
1767 			intel_uncore_read(uncore,
1768 					  GEN11_RENDER_COPY_INTR_ENABLE);
1769 		gt->gtier[1] =
1770 			intel_uncore_read(uncore, GEN11_VCS_VECS_INTR_ENABLE);
1771 		gt->gtier[2] =
1772 			intel_uncore_read(uncore, GEN11_GUC_SG_INTR_ENABLE);
1773 		gt->gtier[3] =
1774 			intel_uncore_read(uncore,
1775 					  GEN11_GPM_WGBOXPERF_INTR_ENABLE);
1776 		gt->gtier[4] =
1777 			intel_uncore_read(uncore,
1778 					  GEN11_CRYPTO_RSVD_INTR_ENABLE);
1779 		gt->gtier[5] =
1780 			intel_uncore_read(uncore,
1781 					  GEN11_GUNIT_CSME_INTR_ENABLE);
1782 		gt->ngtier = 6;
1783 	} else if (GRAPHICS_VER(i915) >= 8) {
1784 		for (i = 0; i < 4; i++)
1785 			gt->gtier[i] =
1786 				intel_uncore_read(uncore, GEN8_GT_IER(i));
1787 		gt->ngtier = 4;
1788 	} else if (HAS_PCH_SPLIT(i915)) {
1789 		gt->gtier[0] = intel_uncore_read(uncore, GTIER);
1790 		gt->ngtier = 1;
1791 	}
1792 
1793 	gt->eir = intel_uncore_read(uncore, EIR);
1794 	gt->pgtbl_er = intel_uncore_read(uncore, PGTBL_ER);
1795 }
1796 
1797 /*
1798  * Capture all registers that relate to workload submission.
1799  * NOTE: In GuC submission, when GuC resets an engine, it can dump these for us
1800  */
1801 static void gt_record_global_regs(struct intel_gt_coredump *gt)
1802 {
1803 	struct intel_uncore *uncore = gt->_gt->uncore;
1804 	struct drm_i915_private *i915 = uncore->i915;
1805 	int i;
1806 
1807 	/*
1808 	 * General organization
1809 	 * 1. Registers specific to a single generation
1810 	 * 2. Registers which belong to multiple generations
1811 	 * 3. Feature specific registers.
1812 	 * 4. Everything else
1813 	 * Please try to follow the order.
1814 	 */
1815 
1816 	/* 1: Registers specific to a single generation */
1817 	if (IS_VALLEYVIEW(i915))
1818 		gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_VLV);
1819 
1820 	if (GRAPHICS_VER(i915) == 7)
1821 		gt->err_int = intel_uncore_read(uncore, GEN7_ERR_INT);
1822 
1823 	if (GRAPHICS_VER(i915) >= 12) {
1824 		gt->fault_data0 = intel_uncore_read(uncore,
1825 						    GEN12_FAULT_TLB_DATA0);
1826 		gt->fault_data1 = intel_uncore_read(uncore,
1827 						    GEN12_FAULT_TLB_DATA1);
1828 	} else if (GRAPHICS_VER(i915) >= 8) {
1829 		gt->fault_data0 = intel_uncore_read(uncore,
1830 						    GEN8_FAULT_TLB_DATA0);
1831 		gt->fault_data1 = intel_uncore_read(uncore,
1832 						    GEN8_FAULT_TLB_DATA1);
1833 	}
1834 
1835 	if (GRAPHICS_VER(i915) == 6) {
1836 		gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE);
1837 		gt->gab_ctl = intel_uncore_read(uncore, GAB_CTL);
1838 		gt->gfx_mode = intel_uncore_read(uncore, GFX_MODE);
1839 	}
1840 
1841 	/* 2: Registers which belong to multiple generations */
1842 	if (GRAPHICS_VER(i915) >= 7)
1843 		gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_MT);
1844 
1845 	if (GRAPHICS_VER(i915) >= 6) {
1846 		if (GRAPHICS_VER(i915) < 12) {
1847 			gt->error = intel_uncore_read(uncore, ERROR_GEN6);
1848 			gt->done_reg = intel_uncore_read(uncore, DONE_REG);
1849 		}
1850 	}
1851 
1852 	/* 3: Feature specific registers */
1853 	if (IS_GRAPHICS_VER(i915, 6, 7)) {
1854 		gt->gam_ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
1855 		gt->gac_eco = intel_uncore_read(uncore, GAC_ECO_BITS);
1856 	}
1857 
1858 	if (IS_GRAPHICS_VER(i915, 8, 11))
1859 		gt->gtt_cache = intel_uncore_read(uncore, HSW_GTT_CACHE_EN);
1860 
1861 	if (GRAPHICS_VER(i915) == 12)
1862 		gt->aux_err = intel_uncore_read(uncore, GEN12_AUX_ERR_DBG);
1863 
1864 	if (GRAPHICS_VER(i915) >= 12) {
1865 		for (i = 0; i < I915_MAX_SFC; i++) {
1866 			/*
1867 			 * SFC_DONE resides in the VD forcewake domain, so it
1868 			 * only exists if the corresponding VCS engine is
1869 			 * present.
1870 			 */
1871 			if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 ||
1872 			    !HAS_ENGINE(gt->_gt, _VCS(i * 2)))
1873 				continue;
1874 
1875 			gt->sfc_done[i] =
1876 				intel_uncore_read(uncore, GEN12_SFC_DONE(i));
1877 		}
1878 
1879 		gt->gam_done = intel_uncore_read(uncore, GEN12_GAM_DONE);
1880 	}
1881 }
1882 
1883 static void gt_record_info(struct intel_gt_coredump *gt)
1884 {
1885 	memcpy(&gt->info, &gt->_gt->info, sizeof(struct intel_gt_info));
1886 	gt->clock_frequency = gt->_gt->clock_frequency;
1887 	gt->clock_period_ns = gt->_gt->clock_period_ns;
1888 }
1889 
1890 /*
1891  * Generate a semi-unique error code. The code is not meant to have meaning, The
1892  * code's only purpose is to try to prevent false duplicated bug reports by
1893  * grossly estimating a GPU error state.
1894  *
1895  * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
1896  * the hang if we could strip the GTT offset information from it.
1897  *
1898  * It's only a small step better than a random number in its current form.
1899  */
1900 static u32 generate_ecode(const struct intel_engine_coredump *ee)
1901 {
1902 	/*
1903 	 * IPEHR would be an ideal way to detect errors, as it's the gross
1904 	 * measure of "the command that hung." However, has some very common
1905 	 * synchronization commands which almost always appear in the case
1906 	 * strictly a client bug. Use instdone to differentiate those some.
1907 	 */
1908 	return ee ? ee->ipehr ^ ee->instdone.instdone : 0;
1909 }
1910 
1911 static const char *error_msg(struct i915_gpu_coredump *error)
1912 {
1913 	struct intel_engine_coredump *first = NULL;
1914 	unsigned int hung_classes = 0;
1915 	struct intel_gt_coredump *gt;
1916 	int len;
1917 
1918 	for (gt = error->gt; gt; gt = gt->next) {
1919 		struct intel_engine_coredump *cs;
1920 
1921 		for (cs = gt->engine; cs; cs = cs->next) {
1922 			if (cs->hung) {
1923 				hung_classes |= BIT(cs->engine->uabi_class);
1924 				if (!first)
1925 					first = cs;
1926 			}
1927 		}
1928 	}
1929 
1930 	len = scnprintf(error->error_msg, sizeof(error->error_msg),
1931 			"GPU HANG: ecode %d:%x:%08x",
1932 			GRAPHICS_VER(error->i915), hung_classes,
1933 			generate_ecode(first));
1934 	if (first && first->context.pid) {
1935 		/* Just show the first executing process, more is confusing */
1936 		len += scnprintf(error->error_msg + len,
1937 				 sizeof(error->error_msg) - len,
1938 				 ", in %s [%d]",
1939 				 first->context.comm, first->context.pid);
1940 	}
1941 
1942 	return error->error_msg;
1943 }
1944 
1945 static void capture_gen(struct i915_gpu_coredump *error)
1946 {
1947 	struct drm_i915_private *i915 = error->i915;
1948 
1949 	error->wakelock = atomic_read(&i915->runtime_pm.wakeref_count);
1950 	error->suspended = i915->runtime_pm.suspended;
1951 
1952 	error->iommu = i915_vtd_active(i915);
1953 	error->reset_count = i915_reset_count(&i915->gpu_error);
1954 	error->suspend_count = i915->suspend_count;
1955 
1956 	i915_params_copy(&error->params, &i915->params);
1957 	memcpy(&error->device_info,
1958 	       INTEL_INFO(i915),
1959 	       sizeof(error->device_info));
1960 	memcpy(&error->runtime_info,
1961 	       RUNTIME_INFO(i915),
1962 	       sizeof(error->runtime_info));
1963 	error->driver_caps = i915->caps;
1964 }
1965 
1966 struct i915_gpu_coredump *
1967 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp)
1968 {
1969 	struct i915_gpu_coredump *error;
1970 
1971 	if (!i915->params.error_capture)
1972 		return NULL;
1973 
1974 	error = kzalloc(sizeof(*error), gfp);
1975 	if (!error)
1976 		return NULL;
1977 
1978 	kref_init(&error->ref);
1979 	error->i915 = i915;
1980 
1981 	error->time = ktime_get_real();
1982 	error->boottime = ktime_get_boottime();
1983 	error->uptime = ktime_sub(ktime_get(), to_gt(i915)->last_init_time);
1984 	error->capture = jiffies;
1985 
1986 	capture_gen(error);
1987 
1988 	return error;
1989 }
1990 
1991 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x))
1992 
1993 struct intel_gt_coredump *
1994 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp, u32 dump_flags)
1995 {
1996 	struct intel_gt_coredump *gc;
1997 
1998 	gc = kzalloc(sizeof(*gc), gfp);
1999 	if (!gc)
2000 		return NULL;
2001 
2002 	gc->_gt = gt;
2003 	gc->awake = intel_gt_pm_is_awake(gt);
2004 
2005 	gt_record_display_regs(gc);
2006 	gt_record_global_nonguc_regs(gc);
2007 
2008 	/*
2009 	 * GuC dumps global, eng-class and eng-instance registers
2010 	 * (that can change as part of engine state during execution)
2011 	 * before an engine is reset due to a hung context.
2012 	 * GuC captures and reports all three groups of registers
2013 	 * together as a single set before the engine is reset.
2014 	 * Thus, if GuC triggered the context reset we retrieve
2015 	 * the register values as part of gt_record_engines.
2016 	 */
2017 	if (!(dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE))
2018 		gt_record_global_regs(gc);
2019 
2020 	gt_record_fences(gc);
2021 
2022 	return gc;
2023 }
2024 
2025 struct i915_vma_compress *
2026 i915_vma_capture_prepare(struct intel_gt_coredump *gt)
2027 {
2028 	struct i915_vma_compress *compress;
2029 
2030 	compress = kmalloc(sizeof(*compress), ALLOW_FAIL);
2031 	if (!compress)
2032 		return NULL;
2033 
2034 	if (!compress_init(compress)) {
2035 		kfree(compress);
2036 		return NULL;
2037 	}
2038 
2039 	return compress;
2040 }
2041 
2042 void i915_vma_capture_finish(struct intel_gt_coredump *gt,
2043 			     struct i915_vma_compress *compress)
2044 {
2045 	if (!compress)
2046 		return;
2047 
2048 	compress_fini(compress);
2049 	kfree(compress);
2050 }
2051 
2052 static struct i915_gpu_coredump *
2053 __i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags)
2054 {
2055 	struct drm_i915_private *i915 = gt->i915;
2056 	struct i915_gpu_coredump *error;
2057 
2058 	/* Check if GPU capture has been disabled */
2059 	error = READ_ONCE(i915->gpu_error.first_error);
2060 	if (IS_ERR(error))
2061 		return error;
2062 
2063 	error = i915_gpu_coredump_alloc(i915, ALLOW_FAIL);
2064 	if (!error)
2065 		return ERR_PTR(-ENOMEM);
2066 
2067 	error->gt = intel_gt_coredump_alloc(gt, ALLOW_FAIL, dump_flags);
2068 	if (error->gt) {
2069 		struct i915_vma_compress *compress;
2070 
2071 		compress = i915_vma_capture_prepare(error->gt);
2072 		if (!compress) {
2073 			kfree(error->gt);
2074 			kfree(error);
2075 			return ERR_PTR(-ENOMEM);
2076 		}
2077 
2078 		if (INTEL_INFO(i915)->has_gt_uc) {
2079 			error->gt->uc = gt_record_uc(error->gt, compress);
2080 			if (error->gt->uc) {
2081 				if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE)
2082 					error->gt->uc->guc.is_guc_capture = true;
2083 				else
2084 					GEM_BUG_ON(error->gt->uc->guc.is_guc_capture);
2085 			}
2086 		}
2087 
2088 		gt_record_info(error->gt);
2089 		gt_record_engines(error->gt, engine_mask, compress, dump_flags);
2090 
2091 
2092 		i915_vma_capture_finish(error->gt, compress);
2093 
2094 		error->simulated |= error->gt->simulated;
2095 	}
2096 
2097 	error->overlay = intel_overlay_capture_error_state(i915);
2098 
2099 	return error;
2100 }
2101 
2102 struct i915_gpu_coredump *
2103 i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags)
2104 {
2105 	static DEFINE_MUTEX(capture_mutex);
2106 	int ret = mutex_lock_interruptible(&capture_mutex);
2107 	struct i915_gpu_coredump *dump;
2108 
2109 	if (ret)
2110 		return ERR_PTR(ret);
2111 
2112 	dump = __i915_gpu_coredump(gt, engine_mask, dump_flags);
2113 	mutex_unlock(&capture_mutex);
2114 
2115 	return dump;
2116 }
2117 
2118 void i915_error_state_store(struct i915_gpu_coredump *error)
2119 {
2120 	struct drm_i915_private *i915;
2121 	static bool warned;
2122 
2123 	if (IS_ERR_OR_NULL(error))
2124 		return;
2125 
2126 	i915 = error->i915;
2127 	drm_info(&i915->drm, "%s\n", error_msg(error));
2128 
2129 	if (error->simulated ||
2130 	    cmpxchg(&i915->gpu_error.first_error, NULL, error))
2131 		return;
2132 
2133 	i915_gpu_coredump_get(error);
2134 
2135 	if (!xchg(&warned, true) &&
2136 	    ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) {
2137 		pr_info("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
2138 		pr_info("Please file a _new_ bug report at https://gitlab.freedesktop.org/drm/intel/issues/new.\n");
2139 		pr_info("Please see https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs for details.\n");
2140 		pr_info("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
2141 		pr_info("The GPU crash dump is required to analyze GPU hangs, so please always attach it.\n");
2142 		pr_info("GPU crash dump saved to /sys/class/drm/card%d/error\n",
2143 			i915->drm.primary->index);
2144 	}
2145 }
2146 
2147 /**
2148  * i915_capture_error_state - capture an error record for later analysis
2149  * @gt: intel_gt which originated the hang
2150  * @engine_mask: hung engines
2151  *
2152  *
2153  * Should be called when an error is detected (either a hang or an error
2154  * interrupt) to capture error state from the time of the error.  Fills
2155  * out a structure which becomes available in debugfs for user level tools
2156  * to pick up.
2157  */
2158 void i915_capture_error_state(struct intel_gt *gt,
2159 			      intel_engine_mask_t engine_mask, u32 dump_flags)
2160 {
2161 	struct i915_gpu_coredump *error;
2162 
2163 	error = i915_gpu_coredump(gt, engine_mask, dump_flags);
2164 	if (IS_ERR(error)) {
2165 		cmpxchg(&gt->i915->gpu_error.first_error, NULL, error);
2166 		return;
2167 	}
2168 
2169 	i915_error_state_store(error);
2170 	i915_gpu_coredump_put(error);
2171 }
2172 
2173 struct i915_gpu_coredump *
2174 i915_first_error_state(struct drm_i915_private *i915)
2175 {
2176 	struct i915_gpu_coredump *error;
2177 
2178 	spin_lock_irq(&i915->gpu_error.lock);
2179 	error = i915->gpu_error.first_error;
2180 	if (!IS_ERR_OR_NULL(error))
2181 		i915_gpu_coredump_get(error);
2182 	spin_unlock_irq(&i915->gpu_error.lock);
2183 
2184 	return error;
2185 }
2186 
2187 void i915_reset_error_state(struct drm_i915_private *i915)
2188 {
2189 	struct i915_gpu_coredump *error;
2190 
2191 	spin_lock_irq(&i915->gpu_error.lock);
2192 	error = i915->gpu_error.first_error;
2193 	if (error != ERR_PTR(-ENODEV)) /* if disabled, always disabled */
2194 		i915->gpu_error.first_error = NULL;
2195 	spin_unlock_irq(&i915->gpu_error.lock);
2196 
2197 	if (!IS_ERR_OR_NULL(error))
2198 		i915_gpu_coredump_put(error);
2199 }
2200 
2201 void i915_disable_error_state(struct drm_i915_private *i915, int err)
2202 {
2203 	spin_lock_irq(&i915->gpu_error.lock);
2204 	if (!i915->gpu_error.first_error)
2205 		i915->gpu_error.first_error = ERR_PTR(err);
2206 	spin_unlock_irq(&i915->gpu_error.lock);
2207 }
2208