1 /* 2 * Copyright (c) 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * Mika Kuoppala <mika.kuoppala@intel.com> 27 * 28 */ 29 30 #include <linux/ascii85.h> 31 #include <linux/highmem.h> 32 #include <linux/nmi.h> 33 #include <linux/pagevec.h> 34 #include <linux/scatterlist.h> 35 #include <linux/string_helpers.h> 36 #include <linux/utsname.h> 37 #include <linux/zlib.h> 38 39 #include <drm/drm_cache.h> 40 #include <drm/drm_print.h> 41 42 #include "display/intel_dmc.h" 43 #include "display/intel_overlay.h" 44 45 #include "gem/i915_gem_context.h" 46 #include "gem/i915_gem_lmem.h" 47 #include "gt/intel_engine_regs.h" 48 #include "gt/intel_gt.h" 49 #include "gt/intel_gt_pm.h" 50 #include "gt/intel_gt_regs.h" 51 #include "gt/uc/intel_guc_capture.h" 52 53 #include "i915_driver.h" 54 #include "i915_drv.h" 55 #include "i915_gpu_error.h" 56 #include "i915_memcpy.h" 57 #include "i915_scatterlist.h" 58 #include "i915_utils.h" 59 60 #define ALLOW_FAIL (__GFP_KSWAPD_RECLAIM | __GFP_RETRY_MAYFAIL | __GFP_NOWARN) 61 #define ATOMIC_MAYFAIL (GFP_ATOMIC | __GFP_NOWARN) 62 63 static void __sg_set_buf(struct scatterlist *sg, 64 void *addr, unsigned int len, loff_t it) 65 { 66 sg->page_link = (unsigned long)virt_to_page(addr); 67 sg->offset = offset_in_page(addr); 68 sg->length = len; 69 sg->dma_address = it; 70 } 71 72 static bool __i915_error_grow(struct drm_i915_error_state_buf *e, size_t len) 73 { 74 if (!len) 75 return false; 76 77 if (e->bytes + len + 1 <= e->size) 78 return true; 79 80 if (e->bytes) { 81 __sg_set_buf(e->cur++, e->buf, e->bytes, e->iter); 82 e->iter += e->bytes; 83 e->buf = NULL; 84 e->bytes = 0; 85 } 86 87 if (e->cur == e->end) { 88 struct scatterlist *sgl; 89 90 sgl = (typeof(sgl))__get_free_page(ALLOW_FAIL); 91 if (!sgl) { 92 e->err = -ENOMEM; 93 return false; 94 } 95 96 if (e->cur) { 97 e->cur->offset = 0; 98 e->cur->length = 0; 99 e->cur->page_link = 100 (unsigned long)sgl | SG_CHAIN; 101 } else { 102 e->sgl = sgl; 103 } 104 105 e->cur = sgl; 106 e->end = sgl + SG_MAX_SINGLE_ALLOC - 1; 107 } 108 109 e->size = ALIGN(len + 1, SZ_64K); 110 e->buf = kmalloc(e->size, ALLOW_FAIL); 111 if (!e->buf) { 112 e->size = PAGE_ALIGN(len + 1); 113 e->buf = kmalloc(e->size, GFP_KERNEL); 114 } 115 if (!e->buf) { 116 e->err = -ENOMEM; 117 return false; 118 } 119 120 return true; 121 } 122 123 __printf(2, 0) 124 static void i915_error_vprintf(struct drm_i915_error_state_buf *e, 125 const char *fmt, va_list args) 126 { 127 va_list ap; 128 int len; 129 130 if (e->err) 131 return; 132 133 va_copy(ap, args); 134 len = vsnprintf(NULL, 0, fmt, ap); 135 va_end(ap); 136 if (len <= 0) { 137 e->err = len; 138 return; 139 } 140 141 if (!__i915_error_grow(e, len)) 142 return; 143 144 GEM_BUG_ON(e->bytes >= e->size); 145 len = vscnprintf(e->buf + e->bytes, e->size - e->bytes, fmt, args); 146 if (len < 0) { 147 e->err = len; 148 return; 149 } 150 e->bytes += len; 151 } 152 153 static void i915_error_puts(struct drm_i915_error_state_buf *e, const char *str) 154 { 155 unsigned len; 156 157 if (e->err || !str) 158 return; 159 160 len = strlen(str); 161 if (!__i915_error_grow(e, len)) 162 return; 163 164 GEM_BUG_ON(e->bytes + len > e->size); 165 memcpy(e->buf + e->bytes, str, len); 166 e->bytes += len; 167 } 168 169 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) 170 #define err_puts(e, s) i915_error_puts(e, s) 171 172 static void __i915_printfn_error(struct drm_printer *p, struct va_format *vaf) 173 { 174 i915_error_vprintf(p->arg, vaf->fmt, *vaf->va); 175 } 176 177 static inline struct drm_printer 178 i915_error_printer(struct drm_i915_error_state_buf *e) 179 { 180 struct drm_printer p = { 181 .printfn = __i915_printfn_error, 182 .arg = e, 183 }; 184 return p; 185 } 186 187 /* single threaded page allocator with a reserved stash for emergencies */ 188 static void pool_fini(struct pagevec *pv) 189 { 190 pagevec_release(pv); 191 } 192 193 static int pool_refill(struct pagevec *pv, gfp_t gfp) 194 { 195 while (pagevec_space(pv)) { 196 struct page *p; 197 198 p = alloc_page(gfp); 199 if (!p) 200 return -ENOMEM; 201 202 pagevec_add(pv, p); 203 } 204 205 return 0; 206 } 207 208 static int pool_init(struct pagevec *pv, gfp_t gfp) 209 { 210 int err; 211 212 pagevec_init(pv); 213 214 err = pool_refill(pv, gfp); 215 if (err) 216 pool_fini(pv); 217 218 return err; 219 } 220 221 static void *pool_alloc(struct pagevec *pv, gfp_t gfp) 222 { 223 struct page *p; 224 225 p = alloc_page(gfp); 226 if (!p && pagevec_count(pv)) 227 p = pv->pages[--pv->nr]; 228 229 return p ? page_address(p) : NULL; 230 } 231 232 static void pool_free(struct pagevec *pv, void *addr) 233 { 234 struct page *p = virt_to_page(addr); 235 236 if (pagevec_space(pv)) 237 pagevec_add(pv, p); 238 else 239 __free_page(p); 240 } 241 242 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR 243 244 struct i915_vma_compress { 245 struct pagevec pool; 246 struct z_stream_s zstream; 247 void *tmp; 248 }; 249 250 static bool compress_init(struct i915_vma_compress *c) 251 { 252 struct z_stream_s *zstream = &c->zstream; 253 254 if (pool_init(&c->pool, ALLOW_FAIL)) 255 return false; 256 257 zstream->workspace = 258 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL), 259 ALLOW_FAIL); 260 if (!zstream->workspace) { 261 pool_fini(&c->pool); 262 return false; 263 } 264 265 c->tmp = NULL; 266 if (i915_has_memcpy_from_wc()) 267 c->tmp = pool_alloc(&c->pool, ALLOW_FAIL); 268 269 return true; 270 } 271 272 static bool compress_start(struct i915_vma_compress *c) 273 { 274 struct z_stream_s *zstream = &c->zstream; 275 void *workspace = zstream->workspace; 276 277 memset(zstream, 0, sizeof(*zstream)); 278 zstream->workspace = workspace; 279 280 return zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) == Z_OK; 281 } 282 283 static void *compress_next_page(struct i915_vma_compress *c, 284 struct i915_vma_coredump *dst) 285 { 286 void *page_addr; 287 struct page *page; 288 289 page_addr = pool_alloc(&c->pool, ALLOW_FAIL); 290 if (!page_addr) 291 return ERR_PTR(-ENOMEM); 292 293 page = virt_to_page(page_addr); 294 list_add_tail(&page->lru, &dst->page_list); 295 return page_addr; 296 } 297 298 static int compress_page(struct i915_vma_compress *c, 299 void *src, 300 struct i915_vma_coredump *dst, 301 bool wc) 302 { 303 struct z_stream_s *zstream = &c->zstream; 304 305 zstream->next_in = src; 306 if (wc && c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE)) 307 zstream->next_in = c->tmp; 308 zstream->avail_in = PAGE_SIZE; 309 310 do { 311 if (zstream->avail_out == 0) { 312 zstream->next_out = compress_next_page(c, dst); 313 if (IS_ERR(zstream->next_out)) 314 return PTR_ERR(zstream->next_out); 315 316 zstream->avail_out = PAGE_SIZE; 317 } 318 319 if (zlib_deflate(zstream, Z_NO_FLUSH) != Z_OK) 320 return -EIO; 321 322 cond_resched(); 323 } while (zstream->avail_in); 324 325 /* Fallback to uncompressed if we increase size? */ 326 if (0 && zstream->total_out > zstream->total_in) 327 return -E2BIG; 328 329 return 0; 330 } 331 332 static int compress_flush(struct i915_vma_compress *c, 333 struct i915_vma_coredump *dst) 334 { 335 struct z_stream_s *zstream = &c->zstream; 336 337 do { 338 switch (zlib_deflate(zstream, Z_FINISH)) { 339 case Z_OK: /* more space requested */ 340 zstream->next_out = compress_next_page(c, dst); 341 if (IS_ERR(zstream->next_out)) 342 return PTR_ERR(zstream->next_out); 343 344 zstream->avail_out = PAGE_SIZE; 345 break; 346 347 case Z_STREAM_END: 348 goto end; 349 350 default: /* any error */ 351 return -EIO; 352 } 353 } while (1); 354 355 end: 356 memset(zstream->next_out, 0, zstream->avail_out); 357 dst->unused = zstream->avail_out; 358 return 0; 359 } 360 361 static void compress_finish(struct i915_vma_compress *c) 362 { 363 zlib_deflateEnd(&c->zstream); 364 } 365 366 static void compress_fini(struct i915_vma_compress *c) 367 { 368 kfree(c->zstream.workspace); 369 if (c->tmp) 370 pool_free(&c->pool, c->tmp); 371 pool_fini(&c->pool); 372 } 373 374 static void err_compression_marker(struct drm_i915_error_state_buf *m) 375 { 376 err_puts(m, ":"); 377 } 378 379 #else 380 381 struct i915_vma_compress { 382 struct pagevec pool; 383 }; 384 385 static bool compress_init(struct i915_vma_compress *c) 386 { 387 return pool_init(&c->pool, ALLOW_FAIL) == 0; 388 } 389 390 static bool compress_start(struct i915_vma_compress *c) 391 { 392 return true; 393 } 394 395 static int compress_page(struct i915_vma_compress *c, 396 void *src, 397 struct i915_vma_coredump *dst, 398 bool wc) 399 { 400 void *ptr; 401 402 ptr = pool_alloc(&c->pool, ALLOW_FAIL); 403 if (!ptr) 404 return -ENOMEM; 405 406 if (!(wc && i915_memcpy_from_wc(ptr, src, PAGE_SIZE))) 407 memcpy(ptr, src, PAGE_SIZE); 408 list_add_tail(&virt_to_page(ptr)->lru, &dst->page_list); 409 cond_resched(); 410 411 return 0; 412 } 413 414 static int compress_flush(struct i915_vma_compress *c, 415 struct i915_vma_coredump *dst) 416 { 417 return 0; 418 } 419 420 static void compress_finish(struct i915_vma_compress *c) 421 { 422 } 423 424 static void compress_fini(struct i915_vma_compress *c) 425 { 426 pool_fini(&c->pool); 427 } 428 429 static void err_compression_marker(struct drm_i915_error_state_buf *m) 430 { 431 err_puts(m, "~"); 432 } 433 434 #endif 435 436 static void error_print_instdone(struct drm_i915_error_state_buf *m, 437 const struct intel_engine_coredump *ee) 438 { 439 const struct sseu_dev_info *sseu = &ee->engine->gt->info.sseu; 440 int slice; 441 int subslice; 442 int iter; 443 444 err_printf(m, " INSTDONE: 0x%08x\n", 445 ee->instdone.instdone); 446 447 if (ee->engine->class != RENDER_CLASS || GRAPHICS_VER(m->i915) <= 3) 448 return; 449 450 err_printf(m, " SC_INSTDONE: 0x%08x\n", 451 ee->instdone.slice_common); 452 453 if (GRAPHICS_VER(m->i915) <= 6) 454 return; 455 456 if (GRAPHICS_VER_FULL(m->i915) >= IP_VER(12, 50)) { 457 for_each_instdone_gslice_dss_xehp(m->i915, sseu, iter, slice, subslice) 458 err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n", 459 slice, subslice, 460 ee->instdone.sampler[slice][subslice]); 461 462 for_each_instdone_gslice_dss_xehp(m->i915, sseu, iter, slice, subslice) 463 err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n", 464 slice, subslice, 465 ee->instdone.row[slice][subslice]); 466 } else { 467 for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice) 468 err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n", 469 slice, subslice, 470 ee->instdone.sampler[slice][subslice]); 471 472 for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice) 473 err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n", 474 slice, subslice, 475 ee->instdone.row[slice][subslice]); 476 } 477 478 if (GRAPHICS_VER(m->i915) < 12) 479 return; 480 481 if (GRAPHICS_VER_FULL(m->i915) >= IP_VER(12, 55)) { 482 for_each_instdone_gslice_dss_xehp(m->i915, sseu, iter, slice, subslice) 483 err_printf(m, " GEOM_SVGUNIT_INSTDONE[%d][%d]: 0x%08x\n", 484 slice, subslice, 485 ee->instdone.geom_svg[slice][subslice]); 486 } 487 488 err_printf(m, " SC_INSTDONE_EXTRA: 0x%08x\n", 489 ee->instdone.slice_common_extra[0]); 490 err_printf(m, " SC_INSTDONE_EXTRA2: 0x%08x\n", 491 ee->instdone.slice_common_extra[1]); 492 } 493 494 static void error_print_request(struct drm_i915_error_state_buf *m, 495 const char *prefix, 496 const struct i915_request_coredump *erq) 497 { 498 if (!erq->seqno) 499 return; 500 501 err_printf(m, "%s pid %d, seqno %8x:%08x%s%s, prio %d, head %08x, tail %08x\n", 502 prefix, erq->pid, erq->context, erq->seqno, 503 test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, 504 &erq->flags) ? "!" : "", 505 test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, 506 &erq->flags) ? "+" : "", 507 erq->sched_attr.priority, 508 erq->head, erq->tail); 509 } 510 511 static void error_print_context(struct drm_i915_error_state_buf *m, 512 const char *header, 513 const struct i915_gem_context_coredump *ctx) 514 { 515 err_printf(m, "%s%s[%d] prio %d, guilty %d active %d, runtime total %lluns, avg %lluns\n", 516 header, ctx->comm, ctx->pid, ctx->sched_attr.priority, 517 ctx->guilty, ctx->active, 518 ctx->total_runtime, ctx->avg_runtime); 519 } 520 521 static struct i915_vma_coredump * 522 __find_vma(struct i915_vma_coredump *vma, const char *name) 523 { 524 while (vma) { 525 if (strcmp(vma->name, name) == 0) 526 return vma; 527 vma = vma->next; 528 } 529 530 return NULL; 531 } 532 533 struct i915_vma_coredump * 534 intel_gpu_error_find_batch(const struct intel_engine_coredump *ee) 535 { 536 return __find_vma(ee->vma, "batch"); 537 } 538 539 static void error_print_engine(struct drm_i915_error_state_buf *m, 540 const struct intel_engine_coredump *ee) 541 { 542 struct i915_vma_coredump *batch; 543 int n; 544 545 err_printf(m, "%s command stream:\n", ee->engine->name); 546 err_printf(m, " CCID: 0x%08x\n", ee->ccid); 547 err_printf(m, " START: 0x%08x\n", ee->start); 548 err_printf(m, " HEAD: 0x%08x [0x%08x]\n", ee->head, ee->rq_head); 549 err_printf(m, " TAIL: 0x%08x [0x%08x, 0x%08x]\n", 550 ee->tail, ee->rq_post, ee->rq_tail); 551 err_printf(m, " CTL: 0x%08x\n", ee->ctl); 552 err_printf(m, " MODE: 0x%08x\n", ee->mode); 553 err_printf(m, " HWS: 0x%08x\n", ee->hws); 554 err_printf(m, " ACTHD: 0x%08x %08x\n", 555 (u32)(ee->acthd>>32), (u32)ee->acthd); 556 err_printf(m, " IPEIR: 0x%08x\n", ee->ipeir); 557 err_printf(m, " IPEHR: 0x%08x\n", ee->ipehr); 558 err_printf(m, " ESR: 0x%08x\n", ee->esr); 559 560 error_print_instdone(m, ee); 561 562 batch = intel_gpu_error_find_batch(ee); 563 if (batch) { 564 u64 start = batch->gtt_offset; 565 u64 end = start + batch->gtt_size; 566 567 err_printf(m, " batch: [0x%08x_%08x, 0x%08x_%08x]\n", 568 upper_32_bits(start), lower_32_bits(start), 569 upper_32_bits(end), lower_32_bits(end)); 570 } 571 if (GRAPHICS_VER(m->i915) >= 4) { 572 err_printf(m, " BBADDR: 0x%08x_%08x\n", 573 (u32)(ee->bbaddr>>32), (u32)ee->bbaddr); 574 err_printf(m, " BB_STATE: 0x%08x\n", ee->bbstate); 575 err_printf(m, " INSTPS: 0x%08x\n", ee->instps); 576 } 577 err_printf(m, " INSTPM: 0x%08x\n", ee->instpm); 578 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr), 579 lower_32_bits(ee->faddr)); 580 if (GRAPHICS_VER(m->i915) >= 6) { 581 err_printf(m, " RC PSMI: 0x%08x\n", ee->rc_psmi); 582 err_printf(m, " FAULT_REG: 0x%08x\n", ee->fault_reg); 583 } 584 if (HAS_PPGTT(m->i915)) { 585 err_printf(m, " GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode); 586 587 if (GRAPHICS_VER(m->i915) >= 8) { 588 int i; 589 for (i = 0; i < 4; i++) 590 err_printf(m, " PDP%d: 0x%016llx\n", 591 i, ee->vm_info.pdp[i]); 592 } else { 593 err_printf(m, " PP_DIR_BASE: 0x%08x\n", 594 ee->vm_info.pp_dir_base); 595 } 596 } 597 598 for (n = 0; n < ee->num_ports; n++) { 599 err_printf(m, " ELSP[%d]:", n); 600 error_print_request(m, " ", &ee->execlist[n]); 601 } 602 } 603 604 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) 605 { 606 va_list args; 607 608 va_start(args, f); 609 i915_error_vprintf(e, f, args); 610 va_end(args); 611 } 612 613 void intel_gpu_error_print_vma(struct drm_i915_error_state_buf *m, 614 const struct intel_engine_cs *engine, 615 const struct i915_vma_coredump *vma) 616 { 617 char out[ASCII85_BUFSZ]; 618 struct page *page; 619 620 if (!vma) 621 return; 622 623 err_printf(m, "%s --- %s = 0x%08x %08x\n", 624 engine ? engine->name : "global", vma->name, 625 upper_32_bits(vma->gtt_offset), 626 lower_32_bits(vma->gtt_offset)); 627 628 if (vma->gtt_page_sizes > I915_GTT_PAGE_SIZE_4K) 629 err_printf(m, "gtt_page_sizes = 0x%08x\n", vma->gtt_page_sizes); 630 631 err_compression_marker(m); 632 list_for_each_entry(page, &vma->page_list, lru) { 633 int i, len; 634 const u32 *addr = page_address(page); 635 636 len = PAGE_SIZE; 637 if (page == list_last_entry(&vma->page_list, typeof(*page), lru)) 638 len -= vma->unused; 639 len = ascii85_encode_len(len); 640 641 for (i = 0; i < len; i++) 642 err_puts(m, ascii85_encode(addr[i], out)); 643 } 644 err_puts(m, "\n"); 645 } 646 647 static void err_print_capabilities(struct drm_i915_error_state_buf *m, 648 struct i915_gpu_coredump *error) 649 { 650 struct drm_printer p = i915_error_printer(m); 651 652 intel_device_info_print_static(&error->device_info, &p); 653 intel_device_info_print_runtime(&error->runtime_info, &p); 654 intel_driver_caps_print(&error->driver_caps, &p); 655 } 656 657 static void err_print_params(struct drm_i915_error_state_buf *m, 658 const struct i915_params *params) 659 { 660 struct drm_printer p = i915_error_printer(m); 661 662 i915_params_dump(params, &p); 663 } 664 665 static void err_print_pciid(struct drm_i915_error_state_buf *m, 666 struct drm_i915_private *i915) 667 { 668 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 669 670 err_printf(m, "PCI ID: 0x%04x\n", pdev->device); 671 err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision); 672 err_printf(m, "PCI Subsystem: %04x:%04x\n", 673 pdev->subsystem_vendor, 674 pdev->subsystem_device); 675 } 676 677 static void err_print_uc(struct drm_i915_error_state_buf *m, 678 const struct intel_uc_coredump *error_uc) 679 { 680 struct drm_printer p = i915_error_printer(m); 681 682 intel_uc_fw_dump(&error_uc->guc_fw, &p); 683 intel_uc_fw_dump(&error_uc->huc_fw, &p); 684 intel_gpu_error_print_vma(m, NULL, error_uc->guc_log); 685 } 686 687 static void err_free_sgl(struct scatterlist *sgl) 688 { 689 while (sgl) { 690 struct scatterlist *sg; 691 692 for (sg = sgl; !sg_is_chain(sg); sg++) { 693 kfree(sg_virt(sg)); 694 if (sg_is_last(sg)) 695 break; 696 } 697 698 sg = sg_is_last(sg) ? NULL : sg_chain_ptr(sg); 699 free_page((unsigned long)sgl); 700 sgl = sg; 701 } 702 } 703 704 static void err_print_gt_info(struct drm_i915_error_state_buf *m, 705 struct intel_gt_coredump *gt) 706 { 707 struct drm_printer p = i915_error_printer(m); 708 709 intel_gt_info_print(>->info, &p); 710 intel_sseu_print_topology(gt->_gt->i915, >->info.sseu, &p); 711 } 712 713 static void err_print_gt_display(struct drm_i915_error_state_buf *m, 714 struct intel_gt_coredump *gt) 715 { 716 err_printf(m, "IER: 0x%08x\n", gt->ier); 717 err_printf(m, "DERRMR: 0x%08x\n", gt->derrmr); 718 } 719 720 static void err_print_gt_global_nonguc(struct drm_i915_error_state_buf *m, 721 struct intel_gt_coredump *gt) 722 { 723 int i; 724 725 err_printf(m, "GT awake: %s\n", str_yes_no(gt->awake)); 726 err_printf(m, "EIR: 0x%08x\n", gt->eir); 727 err_printf(m, "PGTBL_ER: 0x%08x\n", gt->pgtbl_er); 728 729 for (i = 0; i < gt->ngtier; i++) 730 err_printf(m, "GTIER[%d]: 0x%08x\n", i, gt->gtier[i]); 731 } 732 733 static void err_print_gt_global(struct drm_i915_error_state_buf *m, 734 struct intel_gt_coredump *gt) 735 { 736 err_printf(m, "FORCEWAKE: 0x%08x\n", gt->forcewake); 737 738 if (IS_GRAPHICS_VER(m->i915, 6, 11)) { 739 err_printf(m, "ERROR: 0x%08x\n", gt->error); 740 err_printf(m, "DONE_REG: 0x%08x\n", gt->done_reg); 741 } 742 743 if (GRAPHICS_VER(m->i915) >= 8) 744 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n", 745 gt->fault_data1, gt->fault_data0); 746 747 if (GRAPHICS_VER(m->i915) == 7) 748 err_printf(m, "ERR_INT: 0x%08x\n", gt->err_int); 749 750 if (IS_GRAPHICS_VER(m->i915, 8, 11)) 751 err_printf(m, "GTT_CACHE_EN: 0x%08x\n", gt->gtt_cache); 752 753 if (GRAPHICS_VER(m->i915) == 12) 754 err_printf(m, "AUX_ERR_DBG: 0x%08x\n", gt->aux_err); 755 756 if (GRAPHICS_VER(m->i915) >= 12) { 757 int i; 758 759 for (i = 0; i < I915_MAX_SFC; i++) { 760 /* 761 * SFC_DONE resides in the VD forcewake domain, so it 762 * only exists if the corresponding VCS engine is 763 * present. 764 */ 765 if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 || 766 !HAS_ENGINE(gt->_gt, _VCS(i * 2))) 767 continue; 768 769 err_printf(m, " SFC_DONE[%d]: 0x%08x\n", i, 770 gt->sfc_done[i]); 771 } 772 773 err_printf(m, " GAM_DONE: 0x%08x\n", gt->gam_done); 774 } 775 } 776 777 static void err_print_gt_fences(struct drm_i915_error_state_buf *m, 778 struct intel_gt_coredump *gt) 779 { 780 int i; 781 782 for (i = 0; i < gt->nfence; i++) 783 err_printf(m, " fence[%d] = %08llx\n", i, gt->fence[i]); 784 } 785 786 static void err_print_gt_engines(struct drm_i915_error_state_buf *m, 787 struct intel_gt_coredump *gt) 788 { 789 const struct intel_engine_coredump *ee; 790 791 for (ee = gt->engine; ee; ee = ee->next) { 792 const struct i915_vma_coredump *vma; 793 794 if (ee->guc_capture_node) 795 intel_guc_capture_print_engine_node(m, ee); 796 else 797 error_print_engine(m, ee); 798 799 err_printf(m, " hung: %u\n", ee->hung); 800 err_printf(m, " engine reset count: %u\n", ee->reset_count); 801 error_print_context(m, " Active context: ", &ee->context); 802 803 for (vma = ee->vma; vma; vma = vma->next) 804 intel_gpu_error_print_vma(m, ee->engine, vma); 805 } 806 807 } 808 809 static void __err_print_to_sgl(struct drm_i915_error_state_buf *m, 810 struct i915_gpu_coredump *error) 811 { 812 const struct intel_engine_coredump *ee; 813 struct timespec64 ts; 814 815 if (*error->error_msg) 816 err_printf(m, "%s\n", error->error_msg); 817 err_printf(m, "Kernel: %s %s\n", 818 init_utsname()->release, 819 init_utsname()->machine); 820 err_printf(m, "Driver: %s\n", DRIVER_DATE); 821 ts = ktime_to_timespec64(error->time); 822 err_printf(m, "Time: %lld s %ld us\n", 823 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 824 ts = ktime_to_timespec64(error->boottime); 825 err_printf(m, "Boottime: %lld s %ld us\n", 826 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 827 ts = ktime_to_timespec64(error->uptime); 828 err_printf(m, "Uptime: %lld s %ld us\n", 829 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 830 err_printf(m, "Capture: %lu jiffies; %d ms ago\n", 831 error->capture, jiffies_to_msecs(jiffies - error->capture)); 832 833 for (ee = error->gt ? error->gt->engine : NULL; ee; ee = ee->next) 834 err_printf(m, "Active process (on ring %s): %s [%d]\n", 835 ee->engine->name, 836 ee->context.comm, 837 ee->context.pid); 838 839 err_printf(m, "Reset count: %u\n", error->reset_count); 840 err_printf(m, "Suspend count: %u\n", error->suspend_count); 841 err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform)); 842 err_printf(m, "Subplatform: 0x%x\n", 843 intel_subplatform(&error->runtime_info, 844 error->device_info.platform)); 845 err_print_pciid(m, m->i915); 846 847 err_printf(m, "IOMMU enabled?: %d\n", error->iommu); 848 849 intel_dmc_print_error_state(m, m->i915); 850 851 err_printf(m, "RPM wakelock: %s\n", str_yes_no(error->wakelock)); 852 err_printf(m, "PM suspended: %s\n", str_yes_no(error->suspended)); 853 854 if (error->gt) { 855 bool print_guc_capture = false; 856 857 if (error->gt->uc && error->gt->uc->is_guc_capture) 858 print_guc_capture = true; 859 860 err_print_gt_display(m, error->gt); 861 err_print_gt_global_nonguc(m, error->gt); 862 err_print_gt_fences(m, error->gt); 863 864 /* 865 * GuC dumped global, eng-class and eng-instance registers together 866 * as part of engine state dump so we print in err_print_gt_engines 867 */ 868 if (!print_guc_capture) 869 err_print_gt_global(m, error->gt); 870 871 err_print_gt_engines(m, error->gt); 872 873 if (error->gt->uc) 874 err_print_uc(m, error->gt->uc); 875 876 err_print_gt_info(m, error->gt); 877 } 878 879 if (error->overlay) 880 intel_overlay_print_error_state(m, error->overlay); 881 882 err_print_capabilities(m, error); 883 err_print_params(m, &error->params); 884 } 885 886 static int err_print_to_sgl(struct i915_gpu_coredump *error) 887 { 888 struct drm_i915_error_state_buf m; 889 890 if (IS_ERR(error)) 891 return PTR_ERR(error); 892 893 if (READ_ONCE(error->sgl)) 894 return 0; 895 896 memset(&m, 0, sizeof(m)); 897 m.i915 = error->i915; 898 899 __err_print_to_sgl(&m, error); 900 901 if (m.buf) { 902 __sg_set_buf(m.cur++, m.buf, m.bytes, m.iter); 903 m.bytes = 0; 904 m.buf = NULL; 905 } 906 if (m.cur) { 907 GEM_BUG_ON(m.end < m.cur); 908 sg_mark_end(m.cur - 1); 909 } 910 GEM_BUG_ON(m.sgl && !m.cur); 911 912 if (m.err) { 913 err_free_sgl(m.sgl); 914 return m.err; 915 } 916 917 if (cmpxchg(&error->sgl, NULL, m.sgl)) 918 err_free_sgl(m.sgl); 919 920 return 0; 921 } 922 923 ssize_t i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error, 924 char *buf, loff_t off, size_t rem) 925 { 926 struct scatterlist *sg; 927 size_t count; 928 loff_t pos; 929 int err; 930 931 if (!error || !rem) 932 return 0; 933 934 err = err_print_to_sgl(error); 935 if (err) 936 return err; 937 938 sg = READ_ONCE(error->fit); 939 if (!sg || off < sg->dma_address) 940 sg = error->sgl; 941 if (!sg) 942 return 0; 943 944 pos = sg->dma_address; 945 count = 0; 946 do { 947 size_t len, start; 948 949 if (sg_is_chain(sg)) { 950 sg = sg_chain_ptr(sg); 951 GEM_BUG_ON(sg_is_chain(sg)); 952 } 953 954 len = sg->length; 955 if (pos + len <= off) { 956 pos += len; 957 continue; 958 } 959 960 start = sg->offset; 961 if (pos < off) { 962 GEM_BUG_ON(off - pos > len); 963 len -= off - pos; 964 start += off - pos; 965 pos = off; 966 } 967 968 len = min(len, rem); 969 GEM_BUG_ON(!len || len > sg->length); 970 971 memcpy(buf, page_address(sg_page(sg)) + start, len); 972 973 count += len; 974 pos += len; 975 976 buf += len; 977 rem -= len; 978 if (!rem) { 979 WRITE_ONCE(error->fit, sg); 980 break; 981 } 982 } while (!sg_is_last(sg++)); 983 984 return count; 985 } 986 987 static void i915_vma_coredump_free(struct i915_vma_coredump *vma) 988 { 989 while (vma) { 990 struct i915_vma_coredump *next = vma->next; 991 struct page *page, *n; 992 993 list_for_each_entry_safe(page, n, &vma->page_list, lru) { 994 list_del_init(&page->lru); 995 __free_page(page); 996 } 997 998 kfree(vma); 999 vma = next; 1000 } 1001 } 1002 1003 static void cleanup_params(struct i915_gpu_coredump *error) 1004 { 1005 i915_params_free(&error->params); 1006 } 1007 1008 static void cleanup_uc(struct intel_uc_coredump *uc) 1009 { 1010 kfree(uc->guc_fw.path); 1011 kfree(uc->huc_fw.path); 1012 i915_vma_coredump_free(uc->guc_log); 1013 1014 kfree(uc); 1015 } 1016 1017 static void cleanup_gt(struct intel_gt_coredump *gt) 1018 { 1019 while (gt->engine) { 1020 struct intel_engine_coredump *ee = gt->engine; 1021 1022 gt->engine = ee->next; 1023 1024 i915_vma_coredump_free(ee->vma); 1025 intel_guc_capture_free_node(ee); 1026 kfree(ee); 1027 } 1028 1029 if (gt->uc) 1030 cleanup_uc(gt->uc); 1031 1032 kfree(gt); 1033 } 1034 1035 void __i915_gpu_coredump_free(struct kref *error_ref) 1036 { 1037 struct i915_gpu_coredump *error = 1038 container_of(error_ref, typeof(*error), ref); 1039 1040 while (error->gt) { 1041 struct intel_gt_coredump *gt = error->gt; 1042 1043 error->gt = gt->next; 1044 cleanup_gt(gt); 1045 } 1046 1047 kfree(error->overlay); 1048 1049 cleanup_params(error); 1050 1051 err_free_sgl(error->sgl); 1052 kfree(error); 1053 } 1054 1055 static struct i915_vma_coredump * 1056 i915_vma_coredump_create(const struct intel_gt *gt, 1057 const struct i915_vma_resource *vma_res, 1058 struct i915_vma_compress *compress, 1059 const char *name) 1060 1061 { 1062 struct i915_ggtt *ggtt = gt->ggtt; 1063 const u64 slot = ggtt->error_capture.start; 1064 struct i915_vma_coredump *dst; 1065 struct sgt_iter iter; 1066 int ret; 1067 1068 might_sleep(); 1069 1070 if (!vma_res || !vma_res->bi.pages || !compress) 1071 return NULL; 1072 1073 dst = kmalloc(sizeof(*dst), ALLOW_FAIL); 1074 if (!dst) 1075 return NULL; 1076 1077 if (!compress_start(compress)) { 1078 kfree(dst); 1079 return NULL; 1080 } 1081 1082 INIT_LIST_HEAD(&dst->page_list); 1083 strcpy(dst->name, name); 1084 dst->next = NULL; 1085 1086 dst->gtt_offset = vma_res->start; 1087 dst->gtt_size = vma_res->node_size; 1088 dst->gtt_page_sizes = vma_res->page_sizes_gtt; 1089 dst->unused = 0; 1090 1091 ret = -EINVAL; 1092 if (drm_mm_node_allocated(&ggtt->error_capture)) { 1093 void __iomem *s; 1094 dma_addr_t dma; 1095 1096 for_each_sgt_daddr(dma, iter, vma_res->bi.pages) { 1097 mutex_lock(&ggtt->error_mutex); 1098 ggtt->vm.insert_page(&ggtt->vm, dma, slot, 1099 I915_CACHE_NONE, 0); 1100 mb(); 1101 1102 s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE); 1103 ret = compress_page(compress, 1104 (void __force *)s, dst, 1105 true); 1106 io_mapping_unmap(s); 1107 1108 mb(); 1109 ggtt->vm.clear_range(&ggtt->vm, slot, PAGE_SIZE); 1110 mutex_unlock(&ggtt->error_mutex); 1111 if (ret) 1112 break; 1113 } 1114 } else if (vma_res->bi.lmem) { 1115 struct intel_memory_region *mem = vma_res->mr; 1116 dma_addr_t dma; 1117 1118 for_each_sgt_daddr(dma, iter, vma_res->bi.pages) { 1119 void __iomem *s; 1120 1121 s = io_mapping_map_wc(&mem->iomap, 1122 dma - mem->region.start, 1123 PAGE_SIZE); 1124 ret = compress_page(compress, 1125 (void __force *)s, dst, 1126 true); 1127 io_mapping_unmap(s); 1128 if (ret) 1129 break; 1130 } 1131 } else { 1132 struct page *page; 1133 1134 for_each_sgt_page(page, iter, vma_res->bi.pages) { 1135 void *s; 1136 1137 drm_clflush_pages(&page, 1); 1138 1139 s = kmap(page); 1140 ret = compress_page(compress, s, dst, false); 1141 kunmap(page); 1142 1143 drm_clflush_pages(&page, 1); 1144 1145 if (ret) 1146 break; 1147 } 1148 } 1149 1150 if (ret || compress_flush(compress, dst)) { 1151 struct page *page, *n; 1152 1153 list_for_each_entry_safe_reverse(page, n, &dst->page_list, lru) { 1154 list_del_init(&page->lru); 1155 pool_free(&compress->pool, page_address(page)); 1156 } 1157 1158 kfree(dst); 1159 dst = NULL; 1160 } 1161 compress_finish(compress); 1162 1163 return dst; 1164 } 1165 1166 static void gt_record_fences(struct intel_gt_coredump *gt) 1167 { 1168 struct i915_ggtt *ggtt = gt->_gt->ggtt; 1169 struct intel_uncore *uncore = gt->_gt->uncore; 1170 int i; 1171 1172 if (GRAPHICS_VER(uncore->i915) >= 6) { 1173 for (i = 0; i < ggtt->num_fences; i++) 1174 gt->fence[i] = 1175 intel_uncore_read64(uncore, 1176 FENCE_REG_GEN6_LO(i)); 1177 } else if (GRAPHICS_VER(uncore->i915) >= 4) { 1178 for (i = 0; i < ggtt->num_fences; i++) 1179 gt->fence[i] = 1180 intel_uncore_read64(uncore, 1181 FENCE_REG_965_LO(i)); 1182 } else { 1183 for (i = 0; i < ggtt->num_fences; i++) 1184 gt->fence[i] = 1185 intel_uncore_read(uncore, FENCE_REG(i)); 1186 } 1187 gt->nfence = i; 1188 } 1189 1190 static void engine_record_registers(struct intel_engine_coredump *ee) 1191 { 1192 const struct intel_engine_cs *engine = ee->engine; 1193 struct drm_i915_private *i915 = engine->i915; 1194 1195 if (GRAPHICS_VER(i915) >= 6) { 1196 ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL); 1197 1198 if (GRAPHICS_VER(i915) >= 12) 1199 ee->fault_reg = intel_uncore_read(engine->uncore, 1200 GEN12_RING_FAULT_REG); 1201 else if (GRAPHICS_VER(i915) >= 8) 1202 ee->fault_reg = intel_uncore_read(engine->uncore, 1203 GEN8_RING_FAULT_REG); 1204 else 1205 ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine); 1206 } 1207 1208 if (GRAPHICS_VER(i915) >= 4) { 1209 ee->esr = ENGINE_READ(engine, RING_ESR); 1210 ee->faddr = ENGINE_READ(engine, RING_DMA_FADD); 1211 ee->ipeir = ENGINE_READ(engine, RING_IPEIR); 1212 ee->ipehr = ENGINE_READ(engine, RING_IPEHR); 1213 ee->instps = ENGINE_READ(engine, RING_INSTPS); 1214 ee->bbaddr = ENGINE_READ(engine, RING_BBADDR); 1215 ee->ccid = ENGINE_READ(engine, CCID); 1216 if (GRAPHICS_VER(i915) >= 8) { 1217 ee->faddr |= (u64)ENGINE_READ(engine, RING_DMA_FADD_UDW) << 32; 1218 ee->bbaddr |= (u64)ENGINE_READ(engine, RING_BBADDR_UDW) << 32; 1219 } 1220 ee->bbstate = ENGINE_READ(engine, RING_BBSTATE); 1221 } else { 1222 ee->faddr = ENGINE_READ(engine, DMA_FADD_I8XX); 1223 ee->ipeir = ENGINE_READ(engine, IPEIR); 1224 ee->ipehr = ENGINE_READ(engine, IPEHR); 1225 } 1226 1227 intel_engine_get_instdone(engine, &ee->instdone); 1228 1229 ee->instpm = ENGINE_READ(engine, RING_INSTPM); 1230 ee->acthd = intel_engine_get_active_head(engine); 1231 ee->start = ENGINE_READ(engine, RING_START); 1232 ee->head = ENGINE_READ(engine, RING_HEAD); 1233 ee->tail = ENGINE_READ(engine, RING_TAIL); 1234 ee->ctl = ENGINE_READ(engine, RING_CTL); 1235 if (GRAPHICS_VER(i915) > 2) 1236 ee->mode = ENGINE_READ(engine, RING_MI_MODE); 1237 1238 if (!HWS_NEEDS_PHYSICAL(i915)) { 1239 i915_reg_t mmio; 1240 1241 if (GRAPHICS_VER(i915) == 7) { 1242 switch (engine->id) { 1243 default: 1244 MISSING_CASE(engine->id); 1245 fallthrough; 1246 case RCS0: 1247 mmio = RENDER_HWS_PGA_GEN7; 1248 break; 1249 case BCS0: 1250 mmio = BLT_HWS_PGA_GEN7; 1251 break; 1252 case VCS0: 1253 mmio = BSD_HWS_PGA_GEN7; 1254 break; 1255 case VECS0: 1256 mmio = VEBOX_HWS_PGA_GEN7; 1257 break; 1258 } 1259 } else if (GRAPHICS_VER(engine->i915) == 6) { 1260 mmio = RING_HWS_PGA_GEN6(engine->mmio_base); 1261 } else { 1262 /* XXX: gen8 returns to sanity */ 1263 mmio = RING_HWS_PGA(engine->mmio_base); 1264 } 1265 1266 ee->hws = intel_uncore_read(engine->uncore, mmio); 1267 } 1268 1269 ee->reset_count = i915_reset_engine_count(&i915->gpu_error, engine); 1270 1271 if (HAS_PPGTT(i915)) { 1272 int i; 1273 1274 ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7); 1275 1276 if (GRAPHICS_VER(i915) == 6) { 1277 ee->vm_info.pp_dir_base = 1278 ENGINE_READ(engine, RING_PP_DIR_BASE_READ); 1279 } else if (GRAPHICS_VER(i915) == 7) { 1280 ee->vm_info.pp_dir_base = 1281 ENGINE_READ(engine, RING_PP_DIR_BASE); 1282 } else if (GRAPHICS_VER(i915) >= 8) { 1283 u32 base = engine->mmio_base; 1284 1285 for (i = 0; i < 4; i++) { 1286 ee->vm_info.pdp[i] = 1287 intel_uncore_read(engine->uncore, 1288 GEN8_RING_PDP_UDW(base, i)); 1289 ee->vm_info.pdp[i] <<= 32; 1290 ee->vm_info.pdp[i] |= 1291 intel_uncore_read(engine->uncore, 1292 GEN8_RING_PDP_LDW(base, i)); 1293 } 1294 } 1295 } 1296 } 1297 1298 static void record_request(const struct i915_request *request, 1299 struct i915_request_coredump *erq) 1300 { 1301 erq->flags = request->fence.flags; 1302 erq->context = request->fence.context; 1303 erq->seqno = request->fence.seqno; 1304 erq->sched_attr = request->sched.attr; 1305 erq->head = request->head; 1306 erq->tail = request->tail; 1307 1308 erq->pid = 0; 1309 rcu_read_lock(); 1310 if (!intel_context_is_closed(request->context)) { 1311 const struct i915_gem_context *ctx; 1312 1313 ctx = rcu_dereference(request->context->gem_context); 1314 if (ctx) 1315 erq->pid = pid_nr(ctx->pid); 1316 } 1317 rcu_read_unlock(); 1318 } 1319 1320 static void engine_record_execlists(struct intel_engine_coredump *ee) 1321 { 1322 const struct intel_engine_execlists * const el = &ee->engine->execlists; 1323 struct i915_request * const *port = el->active; 1324 unsigned int n = 0; 1325 1326 while (*port) 1327 record_request(*port++, &ee->execlist[n++]); 1328 1329 ee->num_ports = n; 1330 } 1331 1332 static bool record_context(struct i915_gem_context_coredump *e, 1333 const struct i915_request *rq) 1334 { 1335 struct i915_gem_context *ctx; 1336 struct task_struct *task; 1337 bool simulated; 1338 1339 rcu_read_lock(); 1340 ctx = rcu_dereference(rq->context->gem_context); 1341 if (ctx && !kref_get_unless_zero(&ctx->ref)) 1342 ctx = NULL; 1343 rcu_read_unlock(); 1344 if (!ctx) 1345 return true; 1346 1347 rcu_read_lock(); 1348 task = pid_task(ctx->pid, PIDTYPE_PID); 1349 if (task) { 1350 strcpy(e->comm, task->comm); 1351 e->pid = task->pid; 1352 } 1353 rcu_read_unlock(); 1354 1355 e->sched_attr = ctx->sched; 1356 e->guilty = atomic_read(&ctx->guilty_count); 1357 e->active = atomic_read(&ctx->active_count); 1358 1359 e->total_runtime = intel_context_get_total_runtime_ns(rq->context); 1360 e->avg_runtime = intel_context_get_avg_runtime_ns(rq->context); 1361 1362 simulated = i915_gem_context_no_error_capture(ctx); 1363 1364 i915_gem_context_put(ctx); 1365 return simulated; 1366 } 1367 1368 struct intel_engine_capture_vma { 1369 struct intel_engine_capture_vma *next; 1370 struct i915_vma_resource *vma_res; 1371 char name[16]; 1372 bool lockdep_cookie; 1373 }; 1374 1375 static struct intel_engine_capture_vma * 1376 capture_vma_snapshot(struct intel_engine_capture_vma *next, 1377 struct i915_vma_resource *vma_res, 1378 gfp_t gfp, const char *name) 1379 { 1380 struct intel_engine_capture_vma *c; 1381 1382 if (!vma_res) 1383 return next; 1384 1385 c = kmalloc(sizeof(*c), gfp); 1386 if (!c) 1387 return next; 1388 1389 if (!i915_vma_resource_hold(vma_res, &c->lockdep_cookie)) { 1390 kfree(c); 1391 return next; 1392 } 1393 1394 strcpy(c->name, name); 1395 c->vma_res = i915_vma_resource_get(vma_res); 1396 1397 c->next = next; 1398 return c; 1399 } 1400 1401 static struct intel_engine_capture_vma * 1402 capture_vma(struct intel_engine_capture_vma *next, 1403 struct i915_vma *vma, 1404 const char *name, 1405 gfp_t gfp) 1406 { 1407 if (!vma) 1408 return next; 1409 1410 /* 1411 * If the vma isn't pinned, then the vma should be snapshotted 1412 * to a struct i915_vma_snapshot at command submission time. 1413 * Not here. 1414 */ 1415 if (GEM_WARN_ON(!i915_vma_is_pinned(vma))) 1416 return next; 1417 1418 next = capture_vma_snapshot(next, vma->resource, gfp, name); 1419 1420 return next; 1421 } 1422 1423 static struct intel_engine_capture_vma * 1424 capture_user(struct intel_engine_capture_vma *capture, 1425 const struct i915_request *rq, 1426 gfp_t gfp) 1427 { 1428 struct i915_capture_list *c; 1429 1430 for (c = rq->capture_list; c; c = c->next) 1431 capture = capture_vma_snapshot(capture, c->vma_res, gfp, 1432 "user"); 1433 1434 return capture; 1435 } 1436 1437 static void add_vma(struct intel_engine_coredump *ee, 1438 struct i915_vma_coredump *vma) 1439 { 1440 if (vma) { 1441 vma->next = ee->vma; 1442 ee->vma = vma; 1443 } 1444 } 1445 1446 static struct i915_vma_coredump * 1447 create_vma_coredump(const struct intel_gt *gt, struct i915_vma *vma, 1448 const char *name, struct i915_vma_compress *compress) 1449 { 1450 struct i915_vma_coredump *ret = NULL; 1451 struct i915_vma_resource *vma_res; 1452 bool lockdep_cookie; 1453 1454 if (!vma) 1455 return NULL; 1456 1457 vma_res = vma->resource; 1458 1459 if (i915_vma_resource_hold(vma_res, &lockdep_cookie)) { 1460 ret = i915_vma_coredump_create(gt, vma_res, compress, name); 1461 i915_vma_resource_unhold(vma_res, lockdep_cookie); 1462 } 1463 1464 return ret; 1465 } 1466 1467 static void add_vma_coredump(struct intel_engine_coredump *ee, 1468 const struct intel_gt *gt, 1469 struct i915_vma *vma, 1470 const char *name, 1471 struct i915_vma_compress *compress) 1472 { 1473 add_vma(ee, create_vma_coredump(gt, vma, name, compress)); 1474 } 1475 1476 struct intel_engine_coredump * 1477 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp, u32 dump_flags) 1478 { 1479 struct intel_engine_coredump *ee; 1480 1481 ee = kzalloc(sizeof(*ee), gfp); 1482 if (!ee) 1483 return NULL; 1484 1485 ee->engine = engine; 1486 1487 if (!(dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE)) { 1488 engine_record_registers(ee); 1489 engine_record_execlists(ee); 1490 } 1491 1492 return ee; 1493 } 1494 1495 struct intel_engine_capture_vma * 1496 intel_engine_coredump_add_request(struct intel_engine_coredump *ee, 1497 struct i915_request *rq, 1498 gfp_t gfp) 1499 { 1500 struct intel_engine_capture_vma *vma = NULL; 1501 1502 ee->simulated |= record_context(&ee->context, rq); 1503 if (ee->simulated) 1504 return NULL; 1505 1506 /* 1507 * We need to copy these to an anonymous buffer 1508 * as the simplest method to avoid being overwritten 1509 * by userspace. 1510 */ 1511 vma = capture_vma_snapshot(vma, rq->batch_res, gfp, "batch"); 1512 vma = capture_user(vma, rq, gfp); 1513 vma = capture_vma(vma, rq->ring->vma, "ring", gfp); 1514 vma = capture_vma(vma, rq->context->state, "HW context", gfp); 1515 1516 ee->rq_head = rq->head; 1517 ee->rq_post = rq->postfix; 1518 ee->rq_tail = rq->tail; 1519 1520 return vma; 1521 } 1522 1523 void 1524 intel_engine_coredump_add_vma(struct intel_engine_coredump *ee, 1525 struct intel_engine_capture_vma *capture, 1526 struct i915_vma_compress *compress) 1527 { 1528 const struct intel_engine_cs *engine = ee->engine; 1529 1530 while (capture) { 1531 struct intel_engine_capture_vma *this = capture; 1532 struct i915_vma_resource *vma_res = this->vma_res; 1533 1534 add_vma(ee, 1535 i915_vma_coredump_create(engine->gt, vma_res, 1536 compress, this->name)); 1537 1538 i915_vma_resource_unhold(vma_res, this->lockdep_cookie); 1539 i915_vma_resource_put(vma_res); 1540 1541 capture = this->next; 1542 kfree(this); 1543 } 1544 1545 add_vma_coredump(ee, engine->gt, engine->status_page.vma, 1546 "HW Status", compress); 1547 1548 add_vma_coredump(ee, engine->gt, engine->wa_ctx.vma, 1549 "WA context", compress); 1550 } 1551 1552 static struct intel_engine_coredump * 1553 capture_engine(struct intel_engine_cs *engine, 1554 struct i915_vma_compress *compress, 1555 u32 dump_flags) 1556 { 1557 struct intel_engine_capture_vma *capture = NULL; 1558 struct intel_engine_coredump *ee; 1559 struct intel_context *ce; 1560 struct i915_request *rq = NULL; 1561 unsigned long flags; 1562 1563 ee = intel_engine_coredump_alloc(engine, ALLOW_FAIL, dump_flags); 1564 if (!ee) 1565 return NULL; 1566 1567 ce = intel_engine_get_hung_context(engine); 1568 if (ce) { 1569 intel_engine_clear_hung_context(engine); 1570 rq = intel_context_find_active_request(ce); 1571 if (!rq || !i915_request_started(rq)) 1572 goto no_request_capture; 1573 } else { 1574 /* 1575 * Getting here with GuC enabled means it is a forced error capture 1576 * with no actual hang. So, no need to attempt the execlist search. 1577 */ 1578 if (!intel_uc_uses_guc_submission(&engine->gt->uc)) { 1579 spin_lock_irqsave(&engine->sched_engine->lock, flags); 1580 rq = intel_engine_execlist_find_hung_request(engine); 1581 spin_unlock_irqrestore(&engine->sched_engine->lock, 1582 flags); 1583 } 1584 } 1585 if (rq) 1586 rq = i915_request_get_rcu(rq); 1587 1588 if (!rq) 1589 goto no_request_capture; 1590 1591 capture = intel_engine_coredump_add_request(ee, rq, ATOMIC_MAYFAIL); 1592 if (!capture) { 1593 i915_request_put(rq); 1594 goto no_request_capture; 1595 } 1596 if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE) 1597 intel_guc_capture_get_matching_node(engine->gt, ee, ce); 1598 1599 intel_engine_coredump_add_vma(ee, capture, compress); 1600 i915_request_put(rq); 1601 1602 return ee; 1603 1604 no_request_capture: 1605 kfree(ee); 1606 return NULL; 1607 } 1608 1609 static void 1610 gt_record_engines(struct intel_gt_coredump *gt, 1611 intel_engine_mask_t engine_mask, 1612 struct i915_vma_compress *compress, 1613 u32 dump_flags) 1614 { 1615 struct intel_engine_cs *engine; 1616 enum intel_engine_id id; 1617 1618 for_each_engine(engine, gt->_gt, id) { 1619 struct intel_engine_coredump *ee; 1620 1621 /* Refill our page pool before entering atomic section */ 1622 pool_refill(&compress->pool, ALLOW_FAIL); 1623 1624 ee = capture_engine(engine, compress, dump_flags); 1625 if (!ee) 1626 continue; 1627 1628 ee->hung = engine->mask & engine_mask; 1629 1630 gt->simulated |= ee->simulated; 1631 if (ee->simulated) { 1632 if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE) 1633 intel_guc_capture_free_node(ee); 1634 kfree(ee); 1635 continue; 1636 } 1637 1638 ee->next = gt->engine; 1639 gt->engine = ee; 1640 } 1641 } 1642 1643 static struct intel_uc_coredump * 1644 gt_record_uc(struct intel_gt_coredump *gt, 1645 struct i915_vma_compress *compress) 1646 { 1647 const struct intel_uc *uc = >->_gt->uc; 1648 struct intel_uc_coredump *error_uc; 1649 1650 error_uc = kzalloc(sizeof(*error_uc), ALLOW_FAIL); 1651 if (!error_uc) 1652 return NULL; 1653 1654 memcpy(&error_uc->guc_fw, &uc->guc.fw, sizeof(uc->guc.fw)); 1655 memcpy(&error_uc->huc_fw, &uc->huc.fw, sizeof(uc->huc.fw)); 1656 1657 /* Non-default firmware paths will be specified by the modparam. 1658 * As modparams are generally accesible from the userspace make 1659 * explicit copies of the firmware paths. 1660 */ 1661 error_uc->guc_fw.path = kstrdup(uc->guc.fw.path, ALLOW_FAIL); 1662 error_uc->huc_fw.path = kstrdup(uc->huc.fw.path, ALLOW_FAIL); 1663 error_uc->guc_log = create_vma_coredump(gt->_gt, uc->guc.log.vma, 1664 "GuC log buffer", compress); 1665 1666 return error_uc; 1667 } 1668 1669 /* Capture display registers. */ 1670 static void gt_record_display_regs(struct intel_gt_coredump *gt) 1671 { 1672 struct intel_uncore *uncore = gt->_gt->uncore; 1673 struct drm_i915_private *i915 = uncore->i915; 1674 1675 if (GRAPHICS_VER(i915) >= 6) 1676 gt->derrmr = intel_uncore_read(uncore, DERRMR); 1677 1678 if (GRAPHICS_VER(i915) >= 8) 1679 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER); 1680 else if (IS_VALLEYVIEW(i915)) 1681 gt->ier = intel_uncore_read(uncore, VLV_IER); 1682 else if (HAS_PCH_SPLIT(i915)) 1683 gt->ier = intel_uncore_read(uncore, DEIER); 1684 else if (GRAPHICS_VER(i915) == 2) 1685 gt->ier = intel_uncore_read16(uncore, GEN2_IER); 1686 else 1687 gt->ier = intel_uncore_read(uncore, GEN2_IER); 1688 } 1689 1690 /* Capture all other registers that GuC doesn't capture. */ 1691 static void gt_record_global_nonguc_regs(struct intel_gt_coredump *gt) 1692 { 1693 struct intel_uncore *uncore = gt->_gt->uncore; 1694 struct drm_i915_private *i915 = uncore->i915; 1695 int i; 1696 1697 if (IS_VALLEYVIEW(i915)) { 1698 gt->gtier[0] = intel_uncore_read(uncore, GTIER); 1699 gt->ngtier = 1; 1700 } else if (GRAPHICS_VER(i915) >= 11) { 1701 gt->gtier[0] = 1702 intel_uncore_read(uncore, 1703 GEN11_RENDER_COPY_INTR_ENABLE); 1704 gt->gtier[1] = 1705 intel_uncore_read(uncore, GEN11_VCS_VECS_INTR_ENABLE); 1706 gt->gtier[2] = 1707 intel_uncore_read(uncore, GEN11_GUC_SG_INTR_ENABLE); 1708 gt->gtier[3] = 1709 intel_uncore_read(uncore, 1710 GEN11_GPM_WGBOXPERF_INTR_ENABLE); 1711 gt->gtier[4] = 1712 intel_uncore_read(uncore, 1713 GEN11_CRYPTO_RSVD_INTR_ENABLE); 1714 gt->gtier[5] = 1715 intel_uncore_read(uncore, 1716 GEN11_GUNIT_CSME_INTR_ENABLE); 1717 gt->ngtier = 6; 1718 } else if (GRAPHICS_VER(i915) >= 8) { 1719 for (i = 0; i < 4; i++) 1720 gt->gtier[i] = 1721 intel_uncore_read(uncore, GEN8_GT_IER(i)); 1722 gt->ngtier = 4; 1723 } else if (HAS_PCH_SPLIT(i915)) { 1724 gt->gtier[0] = intel_uncore_read(uncore, GTIER); 1725 gt->ngtier = 1; 1726 } 1727 1728 gt->eir = intel_uncore_read(uncore, EIR); 1729 gt->pgtbl_er = intel_uncore_read(uncore, PGTBL_ER); 1730 } 1731 1732 /* 1733 * Capture all registers that relate to workload submission. 1734 * NOTE: In GuC submission, when GuC resets an engine, it can dump these for us 1735 */ 1736 static void gt_record_global_regs(struct intel_gt_coredump *gt) 1737 { 1738 struct intel_uncore *uncore = gt->_gt->uncore; 1739 struct drm_i915_private *i915 = uncore->i915; 1740 int i; 1741 1742 /* 1743 * General organization 1744 * 1. Registers specific to a single generation 1745 * 2. Registers which belong to multiple generations 1746 * 3. Feature specific registers. 1747 * 4. Everything else 1748 * Please try to follow the order. 1749 */ 1750 1751 /* 1: Registers specific to a single generation */ 1752 if (IS_VALLEYVIEW(i915)) 1753 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_VLV); 1754 1755 if (GRAPHICS_VER(i915) == 7) 1756 gt->err_int = intel_uncore_read(uncore, GEN7_ERR_INT); 1757 1758 if (GRAPHICS_VER(i915) >= 12) { 1759 gt->fault_data0 = intel_uncore_read(uncore, 1760 GEN12_FAULT_TLB_DATA0); 1761 gt->fault_data1 = intel_uncore_read(uncore, 1762 GEN12_FAULT_TLB_DATA1); 1763 } else if (GRAPHICS_VER(i915) >= 8) { 1764 gt->fault_data0 = intel_uncore_read(uncore, 1765 GEN8_FAULT_TLB_DATA0); 1766 gt->fault_data1 = intel_uncore_read(uncore, 1767 GEN8_FAULT_TLB_DATA1); 1768 } 1769 1770 if (GRAPHICS_VER(i915) == 6) { 1771 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE); 1772 gt->gab_ctl = intel_uncore_read(uncore, GAB_CTL); 1773 gt->gfx_mode = intel_uncore_read(uncore, GFX_MODE); 1774 } 1775 1776 /* 2: Registers which belong to multiple generations */ 1777 if (GRAPHICS_VER(i915) >= 7) 1778 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_MT); 1779 1780 if (GRAPHICS_VER(i915) >= 6) { 1781 if (GRAPHICS_VER(i915) < 12) { 1782 gt->error = intel_uncore_read(uncore, ERROR_GEN6); 1783 gt->done_reg = intel_uncore_read(uncore, DONE_REG); 1784 } 1785 } 1786 1787 /* 3: Feature specific registers */ 1788 if (IS_GRAPHICS_VER(i915, 6, 7)) { 1789 gt->gam_ecochk = intel_uncore_read(uncore, GAM_ECOCHK); 1790 gt->gac_eco = intel_uncore_read(uncore, GAC_ECO_BITS); 1791 } 1792 1793 if (IS_GRAPHICS_VER(i915, 8, 11)) 1794 gt->gtt_cache = intel_uncore_read(uncore, HSW_GTT_CACHE_EN); 1795 1796 if (GRAPHICS_VER(i915) == 12) 1797 gt->aux_err = intel_uncore_read(uncore, GEN12_AUX_ERR_DBG); 1798 1799 if (GRAPHICS_VER(i915) >= 12) { 1800 for (i = 0; i < I915_MAX_SFC; i++) { 1801 /* 1802 * SFC_DONE resides in the VD forcewake domain, so it 1803 * only exists if the corresponding VCS engine is 1804 * present. 1805 */ 1806 if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 || 1807 !HAS_ENGINE(gt->_gt, _VCS(i * 2))) 1808 continue; 1809 1810 gt->sfc_done[i] = 1811 intel_uncore_read(uncore, GEN12_SFC_DONE(i)); 1812 } 1813 1814 gt->gam_done = intel_uncore_read(uncore, GEN12_GAM_DONE); 1815 } 1816 } 1817 1818 static void gt_record_info(struct intel_gt_coredump *gt) 1819 { 1820 memcpy(>->info, >->_gt->info, sizeof(struct intel_gt_info)); 1821 } 1822 1823 /* 1824 * Generate a semi-unique error code. The code is not meant to have meaning, The 1825 * code's only purpose is to try to prevent false duplicated bug reports by 1826 * grossly estimating a GPU error state. 1827 * 1828 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine 1829 * the hang if we could strip the GTT offset information from it. 1830 * 1831 * It's only a small step better than a random number in its current form. 1832 */ 1833 static u32 generate_ecode(const struct intel_engine_coredump *ee) 1834 { 1835 /* 1836 * IPEHR would be an ideal way to detect errors, as it's the gross 1837 * measure of "the command that hung." However, has some very common 1838 * synchronization commands which almost always appear in the case 1839 * strictly a client bug. Use instdone to differentiate those some. 1840 */ 1841 return ee ? ee->ipehr ^ ee->instdone.instdone : 0; 1842 } 1843 1844 static const char *error_msg(struct i915_gpu_coredump *error) 1845 { 1846 struct intel_engine_coredump *first = NULL; 1847 unsigned int hung_classes = 0; 1848 struct intel_gt_coredump *gt; 1849 int len; 1850 1851 for (gt = error->gt; gt; gt = gt->next) { 1852 struct intel_engine_coredump *cs; 1853 1854 for (cs = gt->engine; cs; cs = cs->next) { 1855 if (cs->hung) { 1856 hung_classes |= BIT(cs->engine->uabi_class); 1857 if (!first) 1858 first = cs; 1859 } 1860 } 1861 } 1862 1863 len = scnprintf(error->error_msg, sizeof(error->error_msg), 1864 "GPU HANG: ecode %d:%x:%08x", 1865 GRAPHICS_VER(error->i915), hung_classes, 1866 generate_ecode(first)); 1867 if (first && first->context.pid) { 1868 /* Just show the first executing process, more is confusing */ 1869 len += scnprintf(error->error_msg + len, 1870 sizeof(error->error_msg) - len, 1871 ", in %s [%d]", 1872 first->context.comm, first->context.pid); 1873 } 1874 1875 return error->error_msg; 1876 } 1877 1878 static void capture_gen(struct i915_gpu_coredump *error) 1879 { 1880 struct drm_i915_private *i915 = error->i915; 1881 1882 error->wakelock = atomic_read(&i915->runtime_pm.wakeref_count); 1883 error->suspended = i915->runtime_pm.suspended; 1884 1885 error->iommu = i915_vtd_active(i915); 1886 error->reset_count = i915_reset_count(&i915->gpu_error); 1887 error->suspend_count = i915->suspend_count; 1888 1889 i915_params_copy(&error->params, &i915->params); 1890 memcpy(&error->device_info, 1891 INTEL_INFO(i915), 1892 sizeof(error->device_info)); 1893 memcpy(&error->runtime_info, 1894 RUNTIME_INFO(i915), 1895 sizeof(error->runtime_info)); 1896 error->driver_caps = i915->caps; 1897 } 1898 1899 struct i915_gpu_coredump * 1900 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp) 1901 { 1902 struct i915_gpu_coredump *error; 1903 1904 if (!i915->params.error_capture) 1905 return NULL; 1906 1907 error = kzalloc(sizeof(*error), gfp); 1908 if (!error) 1909 return NULL; 1910 1911 kref_init(&error->ref); 1912 error->i915 = i915; 1913 1914 error->time = ktime_get_real(); 1915 error->boottime = ktime_get_boottime(); 1916 error->uptime = ktime_sub(ktime_get(), to_gt(i915)->last_init_time); 1917 error->capture = jiffies; 1918 1919 capture_gen(error); 1920 1921 return error; 1922 } 1923 1924 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x)) 1925 1926 struct intel_gt_coredump * 1927 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp, u32 dump_flags) 1928 { 1929 struct intel_gt_coredump *gc; 1930 1931 gc = kzalloc(sizeof(*gc), gfp); 1932 if (!gc) 1933 return NULL; 1934 1935 gc->_gt = gt; 1936 gc->awake = intel_gt_pm_is_awake(gt); 1937 1938 gt_record_display_regs(gc); 1939 gt_record_global_nonguc_regs(gc); 1940 1941 /* 1942 * GuC dumps global, eng-class and eng-instance registers 1943 * (that can change as part of engine state during execution) 1944 * before an engine is reset due to a hung context. 1945 * GuC captures and reports all three groups of registers 1946 * together as a single set before the engine is reset. 1947 * Thus, if GuC triggered the context reset we retrieve 1948 * the register values as part of gt_record_engines. 1949 */ 1950 if (!(dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE)) 1951 gt_record_global_regs(gc); 1952 1953 gt_record_fences(gc); 1954 1955 return gc; 1956 } 1957 1958 struct i915_vma_compress * 1959 i915_vma_capture_prepare(struct intel_gt_coredump *gt) 1960 { 1961 struct i915_vma_compress *compress; 1962 1963 compress = kmalloc(sizeof(*compress), ALLOW_FAIL); 1964 if (!compress) 1965 return NULL; 1966 1967 if (!compress_init(compress)) { 1968 kfree(compress); 1969 return NULL; 1970 } 1971 1972 return compress; 1973 } 1974 1975 void i915_vma_capture_finish(struct intel_gt_coredump *gt, 1976 struct i915_vma_compress *compress) 1977 { 1978 if (!compress) 1979 return; 1980 1981 compress_fini(compress); 1982 kfree(compress); 1983 } 1984 1985 static struct i915_gpu_coredump * 1986 __i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags) 1987 { 1988 struct drm_i915_private *i915 = gt->i915; 1989 struct i915_gpu_coredump *error; 1990 1991 /* Check if GPU capture has been disabled */ 1992 error = READ_ONCE(i915->gpu_error.first_error); 1993 if (IS_ERR(error)) 1994 return error; 1995 1996 error = i915_gpu_coredump_alloc(i915, ALLOW_FAIL); 1997 if (!error) 1998 return ERR_PTR(-ENOMEM); 1999 2000 error->gt = intel_gt_coredump_alloc(gt, ALLOW_FAIL, dump_flags); 2001 if (error->gt) { 2002 struct i915_vma_compress *compress; 2003 2004 compress = i915_vma_capture_prepare(error->gt); 2005 if (!compress) { 2006 kfree(error->gt); 2007 kfree(error); 2008 return ERR_PTR(-ENOMEM); 2009 } 2010 2011 if (INTEL_INFO(i915)->has_gt_uc) { 2012 error->gt->uc = gt_record_uc(error->gt, compress); 2013 if (error->gt->uc) { 2014 if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE) 2015 error->gt->uc->is_guc_capture = true; 2016 else 2017 GEM_BUG_ON(error->gt->uc->is_guc_capture); 2018 } 2019 } 2020 2021 gt_record_info(error->gt); 2022 gt_record_engines(error->gt, engine_mask, compress, dump_flags); 2023 2024 2025 i915_vma_capture_finish(error->gt, compress); 2026 2027 error->simulated |= error->gt->simulated; 2028 } 2029 2030 error->overlay = intel_overlay_capture_error_state(i915); 2031 2032 return error; 2033 } 2034 2035 struct i915_gpu_coredump * 2036 i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags) 2037 { 2038 static DEFINE_MUTEX(capture_mutex); 2039 int ret = mutex_lock_interruptible(&capture_mutex); 2040 struct i915_gpu_coredump *dump; 2041 2042 if (ret) 2043 return ERR_PTR(ret); 2044 2045 dump = __i915_gpu_coredump(gt, engine_mask, dump_flags); 2046 mutex_unlock(&capture_mutex); 2047 2048 return dump; 2049 } 2050 2051 void i915_error_state_store(struct i915_gpu_coredump *error) 2052 { 2053 struct drm_i915_private *i915; 2054 static bool warned; 2055 2056 if (IS_ERR_OR_NULL(error)) 2057 return; 2058 2059 i915 = error->i915; 2060 drm_info(&i915->drm, "%s\n", error_msg(error)); 2061 2062 if (error->simulated || 2063 cmpxchg(&i915->gpu_error.first_error, NULL, error)) 2064 return; 2065 2066 i915_gpu_coredump_get(error); 2067 2068 if (!xchg(&warned, true) && 2069 ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) { 2070 pr_info("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n"); 2071 pr_info("Please file a _new_ bug report at https://gitlab.freedesktop.org/drm/intel/issues/new.\n"); 2072 pr_info("Please see https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs for details.\n"); 2073 pr_info("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n"); 2074 pr_info("The GPU crash dump is required to analyze GPU hangs, so please always attach it.\n"); 2075 pr_info("GPU crash dump saved to /sys/class/drm/card%d/error\n", 2076 i915->drm.primary->index); 2077 } 2078 } 2079 2080 /** 2081 * i915_capture_error_state - capture an error record for later analysis 2082 * @gt: intel_gt which originated the hang 2083 * @engine_mask: hung engines 2084 * 2085 * 2086 * Should be called when an error is detected (either a hang or an error 2087 * interrupt) to capture error state from the time of the error. Fills 2088 * out a structure which becomes available in debugfs for user level tools 2089 * to pick up. 2090 */ 2091 void i915_capture_error_state(struct intel_gt *gt, 2092 intel_engine_mask_t engine_mask, u32 dump_flags) 2093 { 2094 struct i915_gpu_coredump *error; 2095 2096 error = i915_gpu_coredump(gt, engine_mask, dump_flags); 2097 if (IS_ERR(error)) { 2098 cmpxchg(>->i915->gpu_error.first_error, NULL, error); 2099 return; 2100 } 2101 2102 i915_error_state_store(error); 2103 i915_gpu_coredump_put(error); 2104 } 2105 2106 struct i915_gpu_coredump * 2107 i915_first_error_state(struct drm_i915_private *i915) 2108 { 2109 struct i915_gpu_coredump *error; 2110 2111 spin_lock_irq(&i915->gpu_error.lock); 2112 error = i915->gpu_error.first_error; 2113 if (!IS_ERR_OR_NULL(error)) 2114 i915_gpu_coredump_get(error); 2115 spin_unlock_irq(&i915->gpu_error.lock); 2116 2117 return error; 2118 } 2119 2120 void i915_reset_error_state(struct drm_i915_private *i915) 2121 { 2122 struct i915_gpu_coredump *error; 2123 2124 spin_lock_irq(&i915->gpu_error.lock); 2125 error = i915->gpu_error.first_error; 2126 if (error != ERR_PTR(-ENODEV)) /* if disabled, always disabled */ 2127 i915->gpu_error.first_error = NULL; 2128 spin_unlock_irq(&i915->gpu_error.lock); 2129 2130 if (!IS_ERR_OR_NULL(error)) 2131 i915_gpu_coredump_put(error); 2132 } 2133 2134 void i915_disable_error_state(struct drm_i915_private *i915, int err) 2135 { 2136 spin_lock_irq(&i915->gpu_error.lock); 2137 if (!i915->gpu_error.first_error) 2138 i915->gpu_error.first_error = ERR_PTR(err); 2139 spin_unlock_irq(&i915->gpu_error.lock); 2140 } 2141