1 /* 2 * Copyright (c) 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * Mika Kuoppala <mika.kuoppala@intel.com> 27 * 28 */ 29 30 #include <linux/ascii85.h> 31 #include <linux/nmi.h> 32 #include <linux/scatterlist.h> 33 #include <linux/stop_machine.h> 34 #include <linux/utsname.h> 35 #include <linux/zlib.h> 36 37 #include <drm/drm_print.h> 38 39 #include "i915_gpu_error.h" 40 #include "i915_drv.h" 41 42 static inline const struct intel_engine_cs * 43 engine_lookup(const struct drm_i915_private *i915, unsigned int id) 44 { 45 if (id >= I915_NUM_ENGINES) 46 return NULL; 47 48 return i915->engine[id]; 49 } 50 51 static inline const char * 52 __engine_name(const struct intel_engine_cs *engine) 53 { 54 return engine ? engine->name : ""; 55 } 56 57 static const char * 58 engine_name(const struct drm_i915_private *i915, unsigned int id) 59 { 60 return __engine_name(engine_lookup(i915, id)); 61 } 62 63 static const char *tiling_flag(int tiling) 64 { 65 switch (tiling) { 66 default: 67 case I915_TILING_NONE: return ""; 68 case I915_TILING_X: return " X"; 69 case I915_TILING_Y: return " Y"; 70 } 71 } 72 73 static const char *dirty_flag(int dirty) 74 { 75 return dirty ? " dirty" : ""; 76 } 77 78 static const char *purgeable_flag(int purgeable) 79 { 80 return purgeable ? " purgeable" : ""; 81 } 82 83 static void __sg_set_buf(struct scatterlist *sg, 84 void *addr, unsigned int len, loff_t it) 85 { 86 sg->page_link = (unsigned long)virt_to_page(addr); 87 sg->offset = offset_in_page(addr); 88 sg->length = len; 89 sg->dma_address = it; 90 } 91 92 static bool __i915_error_grow(struct drm_i915_error_state_buf *e, size_t len) 93 { 94 if (!len) 95 return false; 96 97 if (e->bytes + len + 1 <= e->size) 98 return true; 99 100 if (e->bytes) { 101 __sg_set_buf(e->cur++, e->buf, e->bytes, e->iter); 102 e->iter += e->bytes; 103 e->buf = NULL; 104 e->bytes = 0; 105 } 106 107 if (e->cur == e->end) { 108 struct scatterlist *sgl; 109 110 sgl = (typeof(sgl))__get_free_page(GFP_KERNEL); 111 if (!sgl) { 112 e->err = -ENOMEM; 113 return false; 114 } 115 116 if (e->cur) { 117 e->cur->offset = 0; 118 e->cur->length = 0; 119 e->cur->page_link = 120 (unsigned long)sgl | SG_CHAIN; 121 } else { 122 e->sgl = sgl; 123 } 124 125 e->cur = sgl; 126 e->end = sgl + SG_MAX_SINGLE_ALLOC - 1; 127 } 128 129 e->size = ALIGN(len + 1, SZ_64K); 130 e->buf = kmalloc(e->size, GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY); 131 if (!e->buf) { 132 e->size = PAGE_ALIGN(len + 1); 133 e->buf = kmalloc(e->size, GFP_KERNEL); 134 } 135 if (!e->buf) { 136 e->err = -ENOMEM; 137 return false; 138 } 139 140 return true; 141 } 142 143 __printf(2, 0) 144 static void i915_error_vprintf(struct drm_i915_error_state_buf *e, 145 const char *fmt, va_list args) 146 { 147 va_list ap; 148 int len; 149 150 if (e->err) 151 return; 152 153 va_copy(ap, args); 154 len = vsnprintf(NULL, 0, fmt, ap); 155 va_end(ap); 156 if (len <= 0) { 157 e->err = len; 158 return; 159 } 160 161 if (!__i915_error_grow(e, len)) 162 return; 163 164 GEM_BUG_ON(e->bytes >= e->size); 165 len = vscnprintf(e->buf + e->bytes, e->size - e->bytes, fmt, args); 166 if (len < 0) { 167 e->err = len; 168 return; 169 } 170 e->bytes += len; 171 } 172 173 static void i915_error_puts(struct drm_i915_error_state_buf *e, const char *str) 174 { 175 unsigned len; 176 177 if (e->err || !str) 178 return; 179 180 len = strlen(str); 181 if (!__i915_error_grow(e, len)) 182 return; 183 184 GEM_BUG_ON(e->bytes + len > e->size); 185 memcpy(e->buf + e->bytes, str, len); 186 e->bytes += len; 187 } 188 189 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) 190 #define err_puts(e, s) i915_error_puts(e, s) 191 192 static void __i915_printfn_error(struct drm_printer *p, struct va_format *vaf) 193 { 194 i915_error_vprintf(p->arg, vaf->fmt, *vaf->va); 195 } 196 197 static inline struct drm_printer 198 i915_error_printer(struct drm_i915_error_state_buf *e) 199 { 200 struct drm_printer p = { 201 .printfn = __i915_printfn_error, 202 .arg = e, 203 }; 204 return p; 205 } 206 207 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR 208 209 struct compress { 210 struct z_stream_s zstream; 211 void *tmp; 212 }; 213 214 static bool compress_init(struct compress *c) 215 { 216 struct z_stream_s *zstream = memset(&c->zstream, 0, sizeof(c->zstream)); 217 218 zstream->workspace = 219 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL), 220 GFP_ATOMIC | __GFP_NOWARN); 221 if (!zstream->workspace) 222 return false; 223 224 if (zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) != Z_OK) { 225 kfree(zstream->workspace); 226 return false; 227 } 228 229 c->tmp = NULL; 230 if (i915_has_memcpy_from_wc()) 231 c->tmp = (void *)__get_free_page(GFP_ATOMIC | __GFP_NOWARN); 232 233 return true; 234 } 235 236 static void *compress_next_page(struct drm_i915_error_object *dst) 237 { 238 unsigned long page; 239 240 if (dst->page_count >= dst->num_pages) 241 return ERR_PTR(-ENOSPC); 242 243 page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN); 244 if (!page) 245 return ERR_PTR(-ENOMEM); 246 247 return dst->pages[dst->page_count++] = (void *)page; 248 } 249 250 static int compress_page(struct compress *c, 251 void *src, 252 struct drm_i915_error_object *dst) 253 { 254 struct z_stream_s *zstream = &c->zstream; 255 256 zstream->next_in = src; 257 if (c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE)) 258 zstream->next_in = c->tmp; 259 zstream->avail_in = PAGE_SIZE; 260 261 do { 262 if (zstream->avail_out == 0) { 263 zstream->next_out = compress_next_page(dst); 264 if (IS_ERR(zstream->next_out)) 265 return PTR_ERR(zstream->next_out); 266 267 zstream->avail_out = PAGE_SIZE; 268 } 269 270 if (zlib_deflate(zstream, Z_NO_FLUSH) != Z_OK) 271 return -EIO; 272 273 touch_nmi_watchdog(); 274 } while (zstream->avail_in); 275 276 /* Fallback to uncompressed if we increase size? */ 277 if (0 && zstream->total_out > zstream->total_in) 278 return -E2BIG; 279 280 return 0; 281 } 282 283 static int compress_flush(struct compress *c, 284 struct drm_i915_error_object *dst) 285 { 286 struct z_stream_s *zstream = &c->zstream; 287 288 do { 289 switch (zlib_deflate(zstream, Z_FINISH)) { 290 case Z_OK: /* more space requested */ 291 zstream->next_out = compress_next_page(dst); 292 if (IS_ERR(zstream->next_out)) 293 return PTR_ERR(zstream->next_out); 294 295 zstream->avail_out = PAGE_SIZE; 296 break; 297 298 case Z_STREAM_END: 299 goto end; 300 301 default: /* any error */ 302 return -EIO; 303 } 304 } while (1); 305 306 end: 307 memset(zstream->next_out, 0, zstream->avail_out); 308 dst->unused = zstream->avail_out; 309 return 0; 310 } 311 312 static void compress_fini(struct compress *c, 313 struct drm_i915_error_object *dst) 314 { 315 struct z_stream_s *zstream = &c->zstream; 316 317 zlib_deflateEnd(zstream); 318 kfree(zstream->workspace); 319 if (c->tmp) 320 free_page((unsigned long)c->tmp); 321 } 322 323 static void err_compression_marker(struct drm_i915_error_state_buf *m) 324 { 325 err_puts(m, ":"); 326 } 327 328 #else 329 330 struct compress { 331 }; 332 333 static bool compress_init(struct compress *c) 334 { 335 return true; 336 } 337 338 static int compress_page(struct compress *c, 339 void *src, 340 struct drm_i915_error_object *dst) 341 { 342 unsigned long page; 343 void *ptr; 344 345 page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN); 346 if (!page) 347 return -ENOMEM; 348 349 ptr = (void *)page; 350 if (!i915_memcpy_from_wc(ptr, src, PAGE_SIZE)) 351 memcpy(ptr, src, PAGE_SIZE); 352 dst->pages[dst->page_count++] = ptr; 353 354 return 0; 355 } 356 357 static int compress_flush(struct compress *c, 358 struct drm_i915_error_object *dst) 359 { 360 return 0; 361 } 362 363 static void compress_fini(struct compress *c, 364 struct drm_i915_error_object *dst) 365 { 366 } 367 368 static void err_compression_marker(struct drm_i915_error_state_buf *m) 369 { 370 err_puts(m, "~"); 371 } 372 373 #endif 374 375 static void print_error_buffers(struct drm_i915_error_state_buf *m, 376 const char *name, 377 struct drm_i915_error_buffer *err, 378 int count) 379 { 380 err_printf(m, "%s [%d]:\n", name, count); 381 382 while (count--) { 383 err_printf(m, " %08x_%08x %8u %02x %02x", 384 upper_32_bits(err->gtt_offset), 385 lower_32_bits(err->gtt_offset), 386 err->size, 387 err->read_domains, 388 err->write_domain); 389 err_puts(m, tiling_flag(err->tiling)); 390 err_puts(m, dirty_flag(err->dirty)); 391 err_puts(m, purgeable_flag(err->purgeable)); 392 err_puts(m, err->userptr ? " userptr" : ""); 393 err_puts(m, i915_cache_level_str(m->i915, err->cache_level)); 394 395 if (err->name) 396 err_printf(m, " (name: %d)", err->name); 397 if (err->fence_reg != I915_FENCE_REG_NONE) 398 err_printf(m, " (fence: %d)", err->fence_reg); 399 400 err_puts(m, "\n"); 401 err++; 402 } 403 } 404 405 static void error_print_instdone(struct drm_i915_error_state_buf *m, 406 const struct drm_i915_error_engine *ee) 407 { 408 int slice; 409 int subslice; 410 411 err_printf(m, " INSTDONE: 0x%08x\n", 412 ee->instdone.instdone); 413 414 if (ee->engine_id != RCS0 || INTEL_GEN(m->i915) <= 3) 415 return; 416 417 err_printf(m, " SC_INSTDONE: 0x%08x\n", 418 ee->instdone.slice_common); 419 420 if (INTEL_GEN(m->i915) <= 6) 421 return; 422 423 for_each_instdone_slice_subslice(m->i915, slice, subslice) 424 err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n", 425 slice, subslice, 426 ee->instdone.sampler[slice][subslice]); 427 428 for_each_instdone_slice_subslice(m->i915, slice, subslice) 429 err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n", 430 slice, subslice, 431 ee->instdone.row[slice][subslice]); 432 } 433 434 static void error_print_request(struct drm_i915_error_state_buf *m, 435 const char *prefix, 436 const struct drm_i915_error_request *erq, 437 const unsigned long epoch) 438 { 439 if (!erq->seqno) 440 return; 441 442 err_printf(m, "%s pid %d, seqno %8x:%08x%s%s, prio %d, emitted %dms, start %08x, head %08x, tail %08x\n", 443 prefix, erq->pid, erq->context, erq->seqno, 444 test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, 445 &erq->flags) ? "!" : "", 446 test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, 447 &erq->flags) ? "+" : "", 448 erq->sched_attr.priority, 449 jiffies_to_msecs(erq->jiffies - epoch), 450 erq->start, erq->head, erq->tail); 451 } 452 453 static void error_print_context(struct drm_i915_error_state_buf *m, 454 const char *header, 455 const struct drm_i915_error_context *ctx) 456 { 457 err_printf(m, "%s%s[%d] hw_id %d, prio %d, guilty %d active %d\n", 458 header, ctx->comm, ctx->pid, ctx->hw_id, 459 ctx->sched_attr.priority, ctx->guilty, ctx->active); 460 } 461 462 static void error_print_engine(struct drm_i915_error_state_buf *m, 463 const struct drm_i915_error_engine *ee, 464 const unsigned long epoch) 465 { 466 int n; 467 468 err_printf(m, "%s command stream:\n", 469 engine_name(m->i915, ee->engine_id)); 470 err_printf(m, " IDLE?: %s\n", yesno(ee->idle)); 471 err_printf(m, " START: 0x%08x\n", ee->start); 472 err_printf(m, " HEAD: 0x%08x [0x%08x]\n", ee->head, ee->rq_head); 473 err_printf(m, " TAIL: 0x%08x [0x%08x, 0x%08x]\n", 474 ee->tail, ee->rq_post, ee->rq_tail); 475 err_printf(m, " CTL: 0x%08x\n", ee->ctl); 476 err_printf(m, " MODE: 0x%08x\n", ee->mode); 477 err_printf(m, " HWS: 0x%08x\n", ee->hws); 478 err_printf(m, " ACTHD: 0x%08x %08x\n", 479 (u32)(ee->acthd>>32), (u32)ee->acthd); 480 err_printf(m, " IPEIR: 0x%08x\n", ee->ipeir); 481 err_printf(m, " IPEHR: 0x%08x\n", ee->ipehr); 482 483 error_print_instdone(m, ee); 484 485 if (ee->batchbuffer) { 486 u64 start = ee->batchbuffer->gtt_offset; 487 u64 end = start + ee->batchbuffer->gtt_size; 488 489 err_printf(m, " batch: [0x%08x_%08x, 0x%08x_%08x]\n", 490 upper_32_bits(start), lower_32_bits(start), 491 upper_32_bits(end), lower_32_bits(end)); 492 } 493 if (INTEL_GEN(m->i915) >= 4) { 494 err_printf(m, " BBADDR: 0x%08x_%08x\n", 495 (u32)(ee->bbaddr>>32), (u32)ee->bbaddr); 496 err_printf(m, " BB_STATE: 0x%08x\n", ee->bbstate); 497 err_printf(m, " INSTPS: 0x%08x\n", ee->instps); 498 } 499 err_printf(m, " INSTPM: 0x%08x\n", ee->instpm); 500 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr), 501 lower_32_bits(ee->faddr)); 502 if (INTEL_GEN(m->i915) >= 6) { 503 err_printf(m, " RC PSMI: 0x%08x\n", ee->rc_psmi); 504 err_printf(m, " FAULT_REG: 0x%08x\n", ee->fault_reg); 505 } 506 if (HAS_PPGTT(m->i915)) { 507 err_printf(m, " GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode); 508 509 if (INTEL_GEN(m->i915) >= 8) { 510 int i; 511 for (i = 0; i < 4; i++) 512 err_printf(m, " PDP%d: 0x%016llx\n", 513 i, ee->vm_info.pdp[i]); 514 } else { 515 err_printf(m, " PP_DIR_BASE: 0x%08x\n", 516 ee->vm_info.pp_dir_base); 517 } 518 } 519 err_printf(m, " ring->head: 0x%08x\n", ee->cpu_ring_head); 520 err_printf(m, " ring->tail: 0x%08x\n", ee->cpu_ring_tail); 521 err_printf(m, " hangcheck timestamp: %dms (%lu%s)\n", 522 jiffies_to_msecs(ee->hangcheck_timestamp - epoch), 523 ee->hangcheck_timestamp, 524 ee->hangcheck_timestamp == epoch ? "; epoch" : ""); 525 err_printf(m, " engine reset count: %u\n", ee->reset_count); 526 527 for (n = 0; n < ee->num_ports; n++) { 528 err_printf(m, " ELSP[%d]:", n); 529 error_print_request(m, " ", &ee->execlist[n], epoch); 530 } 531 532 error_print_context(m, " Active context: ", &ee->context); 533 } 534 535 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) 536 { 537 va_list args; 538 539 va_start(args, f); 540 i915_error_vprintf(e, f, args); 541 va_end(args); 542 } 543 544 static void print_error_obj(struct drm_i915_error_state_buf *m, 545 struct intel_engine_cs *engine, 546 const char *name, 547 struct drm_i915_error_object *obj) 548 { 549 char out[ASCII85_BUFSZ]; 550 int page; 551 552 if (!obj) 553 return; 554 555 if (name) { 556 err_printf(m, "%s --- %s = 0x%08x %08x\n", 557 engine ? engine->name : "global", name, 558 upper_32_bits(obj->gtt_offset), 559 lower_32_bits(obj->gtt_offset)); 560 } 561 562 err_compression_marker(m); 563 for (page = 0; page < obj->page_count; page++) { 564 int i, len; 565 566 len = PAGE_SIZE; 567 if (page == obj->page_count - 1) 568 len -= obj->unused; 569 len = ascii85_encode_len(len); 570 571 for (i = 0; i < len; i++) 572 err_puts(m, ascii85_encode(obj->pages[page][i], out)); 573 } 574 err_puts(m, "\n"); 575 } 576 577 static void err_print_capabilities(struct drm_i915_error_state_buf *m, 578 const struct intel_device_info *info, 579 const struct intel_runtime_info *runtime, 580 const struct intel_driver_caps *caps) 581 { 582 struct drm_printer p = i915_error_printer(m); 583 584 intel_device_info_dump_flags(info, &p); 585 intel_driver_caps_print(caps, &p); 586 intel_device_info_dump_topology(&runtime->sseu, &p); 587 } 588 589 static void err_print_params(struct drm_i915_error_state_buf *m, 590 const struct i915_params *params) 591 { 592 struct drm_printer p = i915_error_printer(m); 593 594 i915_params_dump(params, &p); 595 } 596 597 static void err_print_pciid(struct drm_i915_error_state_buf *m, 598 struct drm_i915_private *i915) 599 { 600 struct pci_dev *pdev = i915->drm.pdev; 601 602 err_printf(m, "PCI ID: 0x%04x\n", pdev->device); 603 err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision); 604 err_printf(m, "PCI Subsystem: %04x:%04x\n", 605 pdev->subsystem_vendor, 606 pdev->subsystem_device); 607 } 608 609 static void err_print_uc(struct drm_i915_error_state_buf *m, 610 const struct i915_error_uc *error_uc) 611 { 612 struct drm_printer p = i915_error_printer(m); 613 const struct i915_gpu_state *error = 614 container_of(error_uc, typeof(*error), uc); 615 616 if (!error->device_info.has_guc) 617 return; 618 619 intel_uc_fw_dump(&error_uc->guc_fw, &p); 620 intel_uc_fw_dump(&error_uc->huc_fw, &p); 621 print_error_obj(m, NULL, "GuC log buffer", error_uc->guc_log); 622 } 623 624 static void err_free_sgl(struct scatterlist *sgl) 625 { 626 while (sgl) { 627 struct scatterlist *sg; 628 629 for (sg = sgl; !sg_is_chain(sg); sg++) { 630 kfree(sg_virt(sg)); 631 if (sg_is_last(sg)) 632 break; 633 } 634 635 sg = sg_is_last(sg) ? NULL : sg_chain_ptr(sg); 636 free_page((unsigned long)sgl); 637 sgl = sg; 638 } 639 } 640 641 static void __err_print_to_sgl(struct drm_i915_error_state_buf *m, 642 struct i915_gpu_state *error) 643 { 644 struct drm_i915_error_object *obj; 645 struct timespec64 ts; 646 int i, j; 647 648 if (*error->error_msg) 649 err_printf(m, "%s\n", error->error_msg); 650 err_printf(m, "Kernel: %s %s\n", 651 init_utsname()->release, 652 init_utsname()->machine); 653 ts = ktime_to_timespec64(error->time); 654 err_printf(m, "Time: %lld s %ld us\n", 655 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 656 ts = ktime_to_timespec64(error->boottime); 657 err_printf(m, "Boottime: %lld s %ld us\n", 658 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 659 ts = ktime_to_timespec64(error->uptime); 660 err_printf(m, "Uptime: %lld s %ld us\n", 661 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 662 err_printf(m, "Epoch: %lu jiffies (%u HZ)\n", error->epoch, HZ); 663 err_printf(m, "Capture: %lu jiffies; %d ms ago, %d ms after epoch\n", 664 error->capture, 665 jiffies_to_msecs(jiffies - error->capture), 666 jiffies_to_msecs(error->capture - error->epoch)); 667 668 for (i = 0; i < ARRAY_SIZE(error->engine); i++) { 669 if (!error->engine[i].context.pid) 670 continue; 671 672 err_printf(m, "Active process (on ring %s): %s [%d]\n", 673 engine_name(m->i915, i), 674 error->engine[i].context.comm, 675 error->engine[i].context.pid); 676 } 677 err_printf(m, "Reset count: %u\n", error->reset_count); 678 err_printf(m, "Suspend count: %u\n", error->suspend_count); 679 err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform)); 680 err_print_pciid(m, m->i915); 681 682 err_printf(m, "IOMMU enabled?: %d\n", error->iommu); 683 684 if (HAS_CSR(m->i915)) { 685 struct intel_csr *csr = &m->i915->csr; 686 687 err_printf(m, "DMC loaded: %s\n", 688 yesno(csr->dmc_payload != NULL)); 689 err_printf(m, "DMC fw version: %d.%d\n", 690 CSR_VERSION_MAJOR(csr->version), 691 CSR_VERSION_MINOR(csr->version)); 692 } 693 694 err_printf(m, "GT awake: %s\n", yesno(error->awake)); 695 err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock)); 696 err_printf(m, "PM suspended: %s\n", yesno(error->suspended)); 697 err_printf(m, "EIR: 0x%08x\n", error->eir); 698 err_printf(m, "IER: 0x%08x\n", error->ier); 699 for (i = 0; i < error->ngtier; i++) 700 err_printf(m, "GTIER[%d]: 0x%08x\n", i, error->gtier[i]); 701 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er); 702 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake); 703 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr); 704 err_printf(m, "CCID: 0x%08x\n", error->ccid); 705 706 for (i = 0; i < error->nfence; i++) 707 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]); 708 709 if (INTEL_GEN(m->i915) >= 6) { 710 err_printf(m, "ERROR: 0x%08x\n", error->error); 711 712 if (INTEL_GEN(m->i915) >= 8) 713 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n", 714 error->fault_data1, error->fault_data0); 715 716 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); 717 } 718 719 if (IS_GEN(m->i915, 7)) 720 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int); 721 722 for (i = 0; i < ARRAY_SIZE(error->engine); i++) { 723 if (error->engine[i].engine_id != -1) 724 error_print_engine(m, &error->engine[i], error->epoch); 725 } 726 727 for (i = 0; i < ARRAY_SIZE(error->active_vm); i++) { 728 char buf[128]; 729 int len, first = 1; 730 731 if (!error->active_vm[i]) 732 break; 733 734 len = scnprintf(buf, sizeof(buf), "Active ("); 735 for (j = 0; j < ARRAY_SIZE(error->engine); j++) { 736 if (error->engine[j].vm != error->active_vm[i]) 737 continue; 738 739 len += scnprintf(buf + len, sizeof(buf), "%s%s", 740 first ? "" : ", ", 741 m->i915->engine[j]->name); 742 first = 0; 743 } 744 scnprintf(buf + len, sizeof(buf), ")"); 745 print_error_buffers(m, buf, 746 error->active_bo[i], 747 error->active_bo_count[i]); 748 } 749 750 print_error_buffers(m, "Pinned (global)", 751 error->pinned_bo, 752 error->pinned_bo_count); 753 754 for (i = 0; i < ARRAY_SIZE(error->engine); i++) { 755 const struct drm_i915_error_engine *ee = &error->engine[i]; 756 757 obj = ee->batchbuffer; 758 if (obj) { 759 err_puts(m, m->i915->engine[i]->name); 760 if (ee->context.pid) 761 err_printf(m, " (submitted by %s [%d])", 762 ee->context.comm, 763 ee->context.pid); 764 err_printf(m, " --- gtt_offset = 0x%08x %08x\n", 765 upper_32_bits(obj->gtt_offset), 766 lower_32_bits(obj->gtt_offset)); 767 print_error_obj(m, m->i915->engine[i], NULL, obj); 768 } 769 770 for (j = 0; j < ee->user_bo_count; j++) 771 print_error_obj(m, m->i915->engine[i], 772 "user", ee->user_bo[j]); 773 774 if (ee->num_requests) { 775 err_printf(m, "%s --- %d requests\n", 776 m->i915->engine[i]->name, 777 ee->num_requests); 778 for (j = 0; j < ee->num_requests; j++) 779 error_print_request(m, " ", 780 &ee->requests[j], 781 error->epoch); 782 } 783 784 print_error_obj(m, m->i915->engine[i], 785 "ringbuffer", ee->ringbuffer); 786 787 print_error_obj(m, m->i915->engine[i], 788 "HW Status", ee->hws_page); 789 790 print_error_obj(m, m->i915->engine[i], 791 "HW context", ee->ctx); 792 793 print_error_obj(m, m->i915->engine[i], 794 "WA context", ee->wa_ctx); 795 796 print_error_obj(m, m->i915->engine[i], 797 "WA batchbuffer", ee->wa_batchbuffer); 798 799 print_error_obj(m, m->i915->engine[i], 800 "NULL context", ee->default_state); 801 } 802 803 if (error->overlay) 804 intel_overlay_print_error_state(m, error->overlay); 805 806 if (error->display) 807 intel_display_print_error_state(m, error->display); 808 809 err_print_capabilities(m, &error->device_info, &error->runtime_info, 810 &error->driver_caps); 811 err_print_params(m, &error->params); 812 err_print_uc(m, &error->uc); 813 } 814 815 static int err_print_to_sgl(struct i915_gpu_state *error) 816 { 817 struct drm_i915_error_state_buf m; 818 819 if (IS_ERR(error)) 820 return PTR_ERR(error); 821 822 if (READ_ONCE(error->sgl)) 823 return 0; 824 825 memset(&m, 0, sizeof(m)); 826 m.i915 = error->i915; 827 828 __err_print_to_sgl(&m, error); 829 830 if (m.buf) { 831 __sg_set_buf(m.cur++, m.buf, m.bytes, m.iter); 832 m.bytes = 0; 833 m.buf = NULL; 834 } 835 if (m.cur) { 836 GEM_BUG_ON(m.end < m.cur); 837 sg_mark_end(m.cur - 1); 838 } 839 GEM_BUG_ON(m.sgl && !m.cur); 840 841 if (m.err) { 842 err_free_sgl(m.sgl); 843 return m.err; 844 } 845 846 if (cmpxchg(&error->sgl, NULL, m.sgl)) 847 err_free_sgl(m.sgl); 848 849 return 0; 850 } 851 852 ssize_t i915_gpu_state_copy_to_buffer(struct i915_gpu_state *error, 853 char *buf, loff_t off, size_t rem) 854 { 855 struct scatterlist *sg; 856 size_t count; 857 loff_t pos; 858 int err; 859 860 if (!error || !rem) 861 return 0; 862 863 err = err_print_to_sgl(error); 864 if (err) 865 return err; 866 867 sg = READ_ONCE(error->fit); 868 if (!sg || off < sg->dma_address) 869 sg = error->sgl; 870 if (!sg) 871 return 0; 872 873 pos = sg->dma_address; 874 count = 0; 875 do { 876 size_t len, start; 877 878 if (sg_is_chain(sg)) { 879 sg = sg_chain_ptr(sg); 880 GEM_BUG_ON(sg_is_chain(sg)); 881 } 882 883 len = sg->length; 884 if (pos + len <= off) { 885 pos += len; 886 continue; 887 } 888 889 start = sg->offset; 890 if (pos < off) { 891 GEM_BUG_ON(off - pos > len); 892 len -= off - pos; 893 start += off - pos; 894 pos = off; 895 } 896 897 len = min(len, rem); 898 GEM_BUG_ON(!len || len > sg->length); 899 900 memcpy(buf, page_address(sg_page(sg)) + start, len); 901 902 count += len; 903 pos += len; 904 905 buf += len; 906 rem -= len; 907 if (!rem) { 908 WRITE_ONCE(error->fit, sg); 909 break; 910 } 911 } while (!sg_is_last(sg++)); 912 913 return count; 914 } 915 916 static void i915_error_object_free(struct drm_i915_error_object *obj) 917 { 918 int page; 919 920 if (obj == NULL) 921 return; 922 923 for (page = 0; page < obj->page_count; page++) 924 free_page((unsigned long)obj->pages[page]); 925 926 kfree(obj); 927 } 928 929 930 static void cleanup_params(struct i915_gpu_state *error) 931 { 932 i915_params_free(&error->params); 933 } 934 935 static void cleanup_uc_state(struct i915_gpu_state *error) 936 { 937 struct i915_error_uc *error_uc = &error->uc; 938 939 kfree(error_uc->guc_fw.path); 940 kfree(error_uc->huc_fw.path); 941 i915_error_object_free(error_uc->guc_log); 942 } 943 944 void __i915_gpu_state_free(struct kref *error_ref) 945 { 946 struct i915_gpu_state *error = 947 container_of(error_ref, typeof(*error), ref); 948 long i, j; 949 950 for (i = 0; i < ARRAY_SIZE(error->engine); i++) { 951 struct drm_i915_error_engine *ee = &error->engine[i]; 952 953 for (j = 0; j < ee->user_bo_count; j++) 954 i915_error_object_free(ee->user_bo[j]); 955 kfree(ee->user_bo); 956 957 i915_error_object_free(ee->batchbuffer); 958 i915_error_object_free(ee->wa_batchbuffer); 959 i915_error_object_free(ee->ringbuffer); 960 i915_error_object_free(ee->hws_page); 961 i915_error_object_free(ee->ctx); 962 i915_error_object_free(ee->wa_ctx); 963 964 kfree(ee->requests); 965 } 966 967 for (i = 0; i < ARRAY_SIZE(error->active_bo); i++) 968 kfree(error->active_bo[i]); 969 kfree(error->pinned_bo); 970 971 kfree(error->overlay); 972 kfree(error->display); 973 974 cleanup_params(error); 975 cleanup_uc_state(error); 976 977 err_free_sgl(error->sgl); 978 kfree(error); 979 } 980 981 static struct drm_i915_error_object * 982 i915_error_object_create(struct drm_i915_private *i915, 983 struct i915_vma *vma) 984 { 985 struct i915_ggtt *ggtt = &i915->ggtt; 986 const u64 slot = ggtt->error_capture.start; 987 struct drm_i915_error_object *dst; 988 struct compress compress; 989 unsigned long num_pages; 990 struct sgt_iter iter; 991 dma_addr_t dma; 992 int ret; 993 994 if (!vma || !vma->pages) 995 return NULL; 996 997 num_pages = min_t(u64, vma->size, vma->obj->base.size) >> PAGE_SHIFT; 998 num_pages = DIV_ROUND_UP(10 * num_pages, 8); /* worstcase zlib growth */ 999 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), 1000 GFP_ATOMIC | __GFP_NOWARN); 1001 if (!dst) 1002 return NULL; 1003 1004 dst->gtt_offset = vma->node.start; 1005 dst->gtt_size = vma->node.size; 1006 dst->num_pages = num_pages; 1007 dst->page_count = 0; 1008 dst->unused = 0; 1009 1010 if (!compress_init(&compress)) { 1011 kfree(dst); 1012 return NULL; 1013 } 1014 1015 ret = -EINVAL; 1016 for_each_sgt_dma(dma, iter, vma->pages) { 1017 void __iomem *s; 1018 1019 ggtt->vm.insert_page(&ggtt->vm, dma, slot, I915_CACHE_NONE, 0); 1020 1021 s = io_mapping_map_atomic_wc(&ggtt->iomap, slot); 1022 ret = compress_page(&compress, (void __force *)s, dst); 1023 io_mapping_unmap_atomic(s); 1024 if (ret) 1025 break; 1026 } 1027 1028 if (ret || compress_flush(&compress, dst)) { 1029 while (dst->page_count--) 1030 free_page((unsigned long)dst->pages[dst->page_count]); 1031 kfree(dst); 1032 dst = NULL; 1033 } 1034 1035 compress_fini(&compress, dst); 1036 return dst; 1037 } 1038 1039 static void capture_bo(struct drm_i915_error_buffer *err, 1040 struct i915_vma *vma) 1041 { 1042 struct drm_i915_gem_object *obj = vma->obj; 1043 1044 err->size = obj->base.size; 1045 err->name = obj->base.name; 1046 1047 err->gtt_offset = vma->node.start; 1048 err->read_domains = obj->read_domains; 1049 err->write_domain = obj->write_domain; 1050 err->fence_reg = vma->fence ? vma->fence->id : -1; 1051 err->tiling = i915_gem_object_get_tiling(obj); 1052 err->dirty = obj->mm.dirty; 1053 err->purgeable = obj->mm.madv != I915_MADV_WILLNEED; 1054 err->userptr = obj->userptr.mm != NULL; 1055 err->cache_level = obj->cache_level; 1056 } 1057 1058 static u32 capture_error_bo(struct drm_i915_error_buffer *err, 1059 int count, struct list_head *head, 1060 unsigned int flags) 1061 #define ACTIVE_ONLY BIT(0) 1062 #define PINNED_ONLY BIT(1) 1063 { 1064 struct i915_vma *vma; 1065 int i = 0; 1066 1067 list_for_each_entry(vma, head, vm_link) { 1068 if (!vma->obj) 1069 continue; 1070 1071 if (flags & ACTIVE_ONLY && !i915_vma_is_active(vma)) 1072 continue; 1073 1074 if (flags & PINNED_ONLY && !i915_vma_is_pinned(vma)) 1075 continue; 1076 1077 capture_bo(err++, vma); 1078 if (++i == count) 1079 break; 1080 } 1081 1082 return i; 1083 } 1084 1085 /* 1086 * Generate a semi-unique error code. The code is not meant to have meaning, The 1087 * code's only purpose is to try to prevent false duplicated bug reports by 1088 * grossly estimating a GPU error state. 1089 * 1090 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine 1091 * the hang if we could strip the GTT offset information from it. 1092 * 1093 * It's only a small step better than a random number in its current form. 1094 */ 1095 static u32 i915_error_generate_code(struct i915_gpu_state *error, 1096 unsigned long engine_mask) 1097 { 1098 /* 1099 * IPEHR would be an ideal way to detect errors, as it's the gross 1100 * measure of "the command that hung." However, has some very common 1101 * synchronization commands which almost always appear in the case 1102 * strictly a client bug. Use instdone to differentiate those some. 1103 */ 1104 if (engine_mask) { 1105 struct drm_i915_error_engine *ee = 1106 &error->engine[ffs(engine_mask)]; 1107 1108 return ee->ipehr ^ ee->instdone.instdone; 1109 } 1110 1111 return 0; 1112 } 1113 1114 static void gem_record_fences(struct i915_gpu_state *error) 1115 { 1116 struct drm_i915_private *dev_priv = error->i915; 1117 int i; 1118 1119 if (INTEL_GEN(dev_priv) >= 6) { 1120 for (i = 0; i < dev_priv->num_fence_regs; i++) 1121 error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i)); 1122 } else if (INTEL_GEN(dev_priv) >= 4) { 1123 for (i = 0; i < dev_priv->num_fence_regs; i++) 1124 error->fence[i] = I915_READ64(FENCE_REG_965_LO(i)); 1125 } else { 1126 for (i = 0; i < dev_priv->num_fence_regs; i++) 1127 error->fence[i] = I915_READ(FENCE_REG(i)); 1128 } 1129 error->nfence = i; 1130 } 1131 1132 static void error_record_engine_registers(struct i915_gpu_state *error, 1133 struct intel_engine_cs *engine, 1134 struct drm_i915_error_engine *ee) 1135 { 1136 struct drm_i915_private *dev_priv = engine->i915; 1137 1138 if (INTEL_GEN(dev_priv) >= 6) { 1139 ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL); 1140 if (INTEL_GEN(dev_priv) >= 8) 1141 ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG); 1142 else 1143 ee->fault_reg = I915_READ(RING_FAULT_REG(engine)); 1144 } 1145 1146 if (INTEL_GEN(dev_priv) >= 4) { 1147 ee->faddr = ENGINE_READ(engine, RING_DMA_FADD); 1148 ee->ipeir = ENGINE_READ(engine, RING_IPEIR); 1149 ee->ipehr = ENGINE_READ(engine, RING_IPEHR); 1150 ee->instps = ENGINE_READ(engine, RING_INSTPS); 1151 ee->bbaddr = ENGINE_READ(engine, RING_BBADDR); 1152 if (INTEL_GEN(dev_priv) >= 8) { 1153 ee->faddr |= (u64)ENGINE_READ(engine, RING_DMA_FADD_UDW) << 32; 1154 ee->bbaddr |= (u64)ENGINE_READ(engine, RING_BBADDR_UDW) << 32; 1155 } 1156 ee->bbstate = ENGINE_READ(engine, RING_BBSTATE); 1157 } else { 1158 ee->faddr = ENGINE_READ(engine, DMA_FADD_I8XX); 1159 ee->ipeir = ENGINE_READ(engine, IPEIR); 1160 ee->ipehr = ENGINE_READ(engine, IPEHR); 1161 } 1162 1163 intel_engine_get_instdone(engine, &ee->instdone); 1164 1165 ee->instpm = ENGINE_READ(engine, RING_INSTPM); 1166 ee->acthd = intel_engine_get_active_head(engine); 1167 ee->start = ENGINE_READ(engine, RING_START); 1168 ee->head = ENGINE_READ(engine, RING_HEAD); 1169 ee->tail = ENGINE_READ(engine, RING_TAIL); 1170 ee->ctl = ENGINE_READ(engine, RING_CTL); 1171 if (INTEL_GEN(dev_priv) > 2) 1172 ee->mode = ENGINE_READ(engine, RING_MI_MODE); 1173 1174 if (!HWS_NEEDS_PHYSICAL(dev_priv)) { 1175 i915_reg_t mmio; 1176 1177 if (IS_GEN(dev_priv, 7)) { 1178 switch (engine->id) { 1179 default: 1180 MISSING_CASE(engine->id); 1181 case RCS0: 1182 mmio = RENDER_HWS_PGA_GEN7; 1183 break; 1184 case BCS0: 1185 mmio = BLT_HWS_PGA_GEN7; 1186 break; 1187 case VCS0: 1188 mmio = BSD_HWS_PGA_GEN7; 1189 break; 1190 case VECS0: 1191 mmio = VEBOX_HWS_PGA_GEN7; 1192 break; 1193 } 1194 } else if (IS_GEN(engine->i915, 6)) { 1195 mmio = RING_HWS_PGA_GEN6(engine->mmio_base); 1196 } else { 1197 /* XXX: gen8 returns to sanity */ 1198 mmio = RING_HWS_PGA(engine->mmio_base); 1199 } 1200 1201 ee->hws = I915_READ(mmio); 1202 } 1203 1204 ee->idle = intel_engine_is_idle(engine); 1205 if (!ee->idle) 1206 ee->hangcheck_timestamp = engine->hangcheck.action_timestamp; 1207 ee->reset_count = i915_reset_engine_count(&dev_priv->gpu_error, 1208 engine); 1209 1210 if (HAS_PPGTT(dev_priv)) { 1211 int i; 1212 1213 ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine)); 1214 1215 if (IS_GEN(dev_priv, 6)) 1216 ee->vm_info.pp_dir_base = 1217 ENGINE_READ(engine, RING_PP_DIR_BASE_READ); 1218 else if (IS_GEN(dev_priv, 7)) 1219 ee->vm_info.pp_dir_base = 1220 ENGINE_READ(engine, RING_PP_DIR_BASE); 1221 else if (INTEL_GEN(dev_priv) >= 8) 1222 for (i = 0; i < 4; i++) { 1223 ee->vm_info.pdp[i] = 1224 I915_READ(GEN8_RING_PDP_UDW(engine, i)); 1225 ee->vm_info.pdp[i] <<= 32; 1226 ee->vm_info.pdp[i] |= 1227 I915_READ(GEN8_RING_PDP_LDW(engine, i)); 1228 } 1229 } 1230 } 1231 1232 static void record_request(struct i915_request *request, 1233 struct drm_i915_error_request *erq) 1234 { 1235 struct i915_gem_context *ctx = request->gem_context; 1236 1237 erq->flags = request->fence.flags; 1238 erq->context = request->fence.context; 1239 erq->seqno = request->fence.seqno; 1240 erq->sched_attr = request->sched.attr; 1241 erq->jiffies = request->emitted_jiffies; 1242 erq->start = i915_ggtt_offset(request->ring->vma); 1243 erq->head = request->head; 1244 erq->tail = request->tail; 1245 1246 rcu_read_lock(); 1247 erq->pid = ctx->pid ? pid_nr(ctx->pid) : 0; 1248 rcu_read_unlock(); 1249 } 1250 1251 static void engine_record_requests(struct intel_engine_cs *engine, 1252 struct i915_request *first, 1253 struct drm_i915_error_engine *ee) 1254 { 1255 struct i915_request *request; 1256 int count; 1257 1258 count = 0; 1259 request = first; 1260 list_for_each_entry_from(request, &engine->timeline.requests, link) 1261 count++; 1262 if (!count) 1263 return; 1264 1265 ee->requests = kcalloc(count, sizeof(*ee->requests), GFP_ATOMIC); 1266 if (!ee->requests) 1267 return; 1268 1269 ee->num_requests = count; 1270 1271 count = 0; 1272 request = first; 1273 list_for_each_entry_from(request, &engine->timeline.requests, link) { 1274 if (count >= ee->num_requests) { 1275 /* 1276 * If the ring request list was changed in 1277 * between the point where the error request 1278 * list was created and dimensioned and this 1279 * point then just exit early to avoid crashes. 1280 * 1281 * We don't need to communicate that the 1282 * request list changed state during error 1283 * state capture and that the error state is 1284 * slightly incorrect as a consequence since we 1285 * are typically only interested in the request 1286 * list state at the point of error state 1287 * capture, not in any changes happening during 1288 * the capture. 1289 */ 1290 break; 1291 } 1292 1293 record_request(request, &ee->requests[count++]); 1294 } 1295 ee->num_requests = count; 1296 } 1297 1298 static void error_record_engine_execlists(struct intel_engine_cs *engine, 1299 struct drm_i915_error_engine *ee) 1300 { 1301 const struct intel_engine_execlists * const execlists = &engine->execlists; 1302 unsigned int n; 1303 1304 for (n = 0; n < execlists_num_ports(execlists); n++) { 1305 struct i915_request *rq = port_request(&execlists->port[n]); 1306 1307 if (!rq) 1308 break; 1309 1310 record_request(rq, &ee->execlist[n]); 1311 } 1312 1313 ee->num_ports = n; 1314 } 1315 1316 static void record_context(struct drm_i915_error_context *e, 1317 struct i915_gem_context *ctx) 1318 { 1319 if (ctx->pid) { 1320 struct task_struct *task; 1321 1322 rcu_read_lock(); 1323 task = pid_task(ctx->pid, PIDTYPE_PID); 1324 if (task) { 1325 strcpy(e->comm, task->comm); 1326 e->pid = task->pid; 1327 } 1328 rcu_read_unlock(); 1329 } 1330 1331 e->hw_id = ctx->hw_id; 1332 e->sched_attr = ctx->sched; 1333 e->guilty = atomic_read(&ctx->guilty_count); 1334 e->active = atomic_read(&ctx->active_count); 1335 } 1336 1337 static void request_record_user_bo(struct i915_request *request, 1338 struct drm_i915_error_engine *ee) 1339 { 1340 struct i915_capture_list *c; 1341 struct drm_i915_error_object **bo; 1342 long count, max; 1343 1344 max = 0; 1345 for (c = request->capture_list; c; c = c->next) 1346 max++; 1347 if (!max) 1348 return; 1349 1350 bo = kmalloc_array(max, sizeof(*bo), GFP_ATOMIC); 1351 if (!bo) { 1352 /* If we can't capture everything, try to capture something. */ 1353 max = min_t(long, max, PAGE_SIZE / sizeof(*bo)); 1354 bo = kmalloc_array(max, sizeof(*bo), GFP_ATOMIC); 1355 } 1356 if (!bo) 1357 return; 1358 1359 count = 0; 1360 for (c = request->capture_list; c; c = c->next) { 1361 bo[count] = i915_error_object_create(request->i915, c->vma); 1362 if (!bo[count]) 1363 break; 1364 if (++count == max) 1365 break; 1366 } 1367 1368 ee->user_bo = bo; 1369 ee->user_bo_count = count; 1370 } 1371 1372 static struct drm_i915_error_object * 1373 capture_object(struct drm_i915_private *dev_priv, 1374 struct drm_i915_gem_object *obj) 1375 { 1376 if (obj && i915_gem_object_has_pages(obj)) { 1377 struct i915_vma fake = { 1378 .node = { .start = U64_MAX, .size = obj->base.size }, 1379 .size = obj->base.size, 1380 .pages = obj->mm.pages, 1381 .obj = obj, 1382 }; 1383 1384 return i915_error_object_create(dev_priv, &fake); 1385 } else { 1386 return NULL; 1387 } 1388 } 1389 1390 static void gem_record_rings(struct i915_gpu_state *error) 1391 { 1392 struct drm_i915_private *i915 = error->i915; 1393 struct i915_ggtt *ggtt = &i915->ggtt; 1394 int i; 1395 1396 for (i = 0; i < I915_NUM_ENGINES; i++) { 1397 struct intel_engine_cs *engine = i915->engine[i]; 1398 struct drm_i915_error_engine *ee = &error->engine[i]; 1399 struct i915_request *request; 1400 1401 ee->engine_id = -1; 1402 1403 if (!engine) 1404 continue; 1405 1406 ee->engine_id = i; 1407 1408 error_record_engine_registers(error, engine, ee); 1409 error_record_engine_execlists(engine, ee); 1410 1411 request = intel_engine_find_active_request(engine); 1412 if (request) { 1413 struct i915_gem_context *ctx = request->gem_context; 1414 struct intel_ring *ring; 1415 1416 ee->vm = ctx->ppgtt ? &ctx->ppgtt->vm : &ggtt->vm; 1417 1418 record_context(&ee->context, ctx); 1419 1420 /* We need to copy these to an anonymous buffer 1421 * as the simplest method to avoid being overwritten 1422 * by userspace. 1423 */ 1424 ee->batchbuffer = 1425 i915_error_object_create(i915, request->batch); 1426 1427 if (HAS_BROKEN_CS_TLB(i915)) 1428 ee->wa_batchbuffer = 1429 i915_error_object_create(i915, 1430 i915->gt.scratch); 1431 request_record_user_bo(request, ee); 1432 1433 ee->ctx = 1434 i915_error_object_create(i915, 1435 request->hw_context->state); 1436 1437 error->simulated |= 1438 i915_gem_context_no_error_capture(ctx); 1439 1440 ee->rq_head = request->head; 1441 ee->rq_post = request->postfix; 1442 ee->rq_tail = request->tail; 1443 1444 ring = request->ring; 1445 ee->cpu_ring_head = ring->head; 1446 ee->cpu_ring_tail = ring->tail; 1447 ee->ringbuffer = 1448 i915_error_object_create(i915, ring->vma); 1449 1450 engine_record_requests(engine, request, ee); 1451 } 1452 1453 ee->hws_page = 1454 i915_error_object_create(i915, 1455 engine->status_page.vma); 1456 1457 ee->wa_ctx = i915_error_object_create(i915, engine->wa_ctx.vma); 1458 1459 ee->default_state = capture_object(i915, engine->default_state); 1460 } 1461 } 1462 1463 static void gem_capture_vm(struct i915_gpu_state *error, 1464 struct i915_address_space *vm, 1465 int idx) 1466 { 1467 struct drm_i915_error_buffer *active_bo; 1468 struct i915_vma *vma; 1469 int count; 1470 1471 count = 0; 1472 list_for_each_entry(vma, &vm->bound_list, vm_link) 1473 if (i915_vma_is_active(vma)) 1474 count++; 1475 1476 active_bo = NULL; 1477 if (count) 1478 active_bo = kcalloc(count, sizeof(*active_bo), GFP_ATOMIC); 1479 if (active_bo) 1480 count = capture_error_bo(active_bo, 1481 count, &vm->bound_list, 1482 ACTIVE_ONLY); 1483 else 1484 count = 0; 1485 1486 error->active_vm[idx] = vm; 1487 error->active_bo[idx] = active_bo; 1488 error->active_bo_count[idx] = count; 1489 } 1490 1491 static void capture_active_buffers(struct i915_gpu_state *error) 1492 { 1493 int cnt = 0, i, j; 1494 1495 BUILD_BUG_ON(ARRAY_SIZE(error->engine) > ARRAY_SIZE(error->active_bo)); 1496 BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_vm)); 1497 BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_bo_count)); 1498 1499 /* Scan each engine looking for unique active contexts/vm */ 1500 for (i = 0; i < ARRAY_SIZE(error->engine); i++) { 1501 struct drm_i915_error_engine *ee = &error->engine[i]; 1502 bool found; 1503 1504 if (!ee->vm) 1505 continue; 1506 1507 found = false; 1508 for (j = 0; j < i && !found; j++) 1509 found = error->engine[j].vm == ee->vm; 1510 if (!found) 1511 gem_capture_vm(error, ee->vm, cnt++); 1512 } 1513 } 1514 1515 static void capture_pinned_buffers(struct i915_gpu_state *error) 1516 { 1517 struct i915_address_space *vm = &error->i915->ggtt.vm; 1518 struct drm_i915_error_buffer *bo; 1519 struct i915_vma *vma; 1520 int count; 1521 1522 count = 0; 1523 list_for_each_entry(vma, &vm->bound_list, vm_link) 1524 count++; 1525 1526 bo = NULL; 1527 if (count) 1528 bo = kcalloc(count, sizeof(*bo), GFP_ATOMIC); 1529 if (!bo) 1530 return; 1531 1532 error->pinned_bo_count = 1533 capture_error_bo(bo, count, &vm->bound_list, PINNED_ONLY); 1534 error->pinned_bo = bo; 1535 } 1536 1537 static void capture_uc_state(struct i915_gpu_state *error) 1538 { 1539 struct drm_i915_private *i915 = error->i915; 1540 struct i915_error_uc *error_uc = &error->uc; 1541 1542 /* Capturing uC state won't be useful if there is no GuC */ 1543 if (!error->device_info.has_guc) 1544 return; 1545 1546 error_uc->guc_fw = i915->guc.fw; 1547 error_uc->huc_fw = i915->huc.fw; 1548 1549 /* Non-default firmware paths will be specified by the modparam. 1550 * As modparams are generally accesible from the userspace make 1551 * explicit copies of the firmware paths. 1552 */ 1553 error_uc->guc_fw.path = kstrdup(i915->guc.fw.path, GFP_ATOMIC); 1554 error_uc->huc_fw.path = kstrdup(i915->huc.fw.path, GFP_ATOMIC); 1555 error_uc->guc_log = i915_error_object_create(i915, i915->guc.log.vma); 1556 } 1557 1558 /* Capture all registers which don't fit into another category. */ 1559 static void capture_reg_state(struct i915_gpu_state *error) 1560 { 1561 struct drm_i915_private *dev_priv = error->i915; 1562 int i; 1563 1564 /* General organization 1565 * 1. Registers specific to a single generation 1566 * 2. Registers which belong to multiple generations 1567 * 3. Feature specific registers. 1568 * 4. Everything else 1569 * Please try to follow the order. 1570 */ 1571 1572 /* 1: Registers specific to a single generation */ 1573 if (IS_VALLEYVIEW(dev_priv)) { 1574 error->gtier[0] = I915_READ(GTIER); 1575 error->ier = I915_READ(VLV_IER); 1576 error->forcewake = I915_READ_FW(FORCEWAKE_VLV); 1577 } 1578 1579 if (IS_GEN(dev_priv, 7)) 1580 error->err_int = I915_READ(GEN7_ERR_INT); 1581 1582 if (INTEL_GEN(dev_priv) >= 8) { 1583 error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0); 1584 error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1); 1585 } 1586 1587 if (IS_GEN(dev_priv, 6)) { 1588 error->forcewake = I915_READ_FW(FORCEWAKE); 1589 error->gab_ctl = I915_READ(GAB_CTL); 1590 error->gfx_mode = I915_READ(GFX_MODE); 1591 } 1592 1593 /* 2: Registers which belong to multiple generations */ 1594 if (INTEL_GEN(dev_priv) >= 7) 1595 error->forcewake = I915_READ_FW(FORCEWAKE_MT); 1596 1597 if (INTEL_GEN(dev_priv) >= 6) { 1598 error->derrmr = I915_READ(DERRMR); 1599 error->error = I915_READ(ERROR_GEN6); 1600 error->done_reg = I915_READ(DONE_REG); 1601 } 1602 1603 if (INTEL_GEN(dev_priv) >= 5) 1604 error->ccid = I915_READ(CCID(RENDER_RING_BASE)); 1605 1606 /* 3: Feature specific registers */ 1607 if (IS_GEN_RANGE(dev_priv, 6, 7)) { 1608 error->gam_ecochk = I915_READ(GAM_ECOCHK); 1609 error->gac_eco = I915_READ(GAC_ECO_BITS); 1610 } 1611 1612 /* 4: Everything else */ 1613 if (INTEL_GEN(dev_priv) >= 11) { 1614 error->ier = I915_READ(GEN8_DE_MISC_IER); 1615 error->gtier[0] = I915_READ(GEN11_RENDER_COPY_INTR_ENABLE); 1616 error->gtier[1] = I915_READ(GEN11_VCS_VECS_INTR_ENABLE); 1617 error->gtier[2] = I915_READ(GEN11_GUC_SG_INTR_ENABLE); 1618 error->gtier[3] = I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE); 1619 error->gtier[4] = I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE); 1620 error->gtier[5] = I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE); 1621 error->ngtier = 6; 1622 } else if (INTEL_GEN(dev_priv) >= 8) { 1623 error->ier = I915_READ(GEN8_DE_MISC_IER); 1624 for (i = 0; i < 4; i++) 1625 error->gtier[i] = I915_READ(GEN8_GT_IER(i)); 1626 error->ngtier = 4; 1627 } else if (HAS_PCH_SPLIT(dev_priv)) { 1628 error->ier = I915_READ(DEIER); 1629 error->gtier[0] = I915_READ(GTIER); 1630 error->ngtier = 1; 1631 } else if (IS_GEN(dev_priv, 2)) { 1632 error->ier = I915_READ16(IER); 1633 } else if (!IS_VALLEYVIEW(dev_priv)) { 1634 error->ier = I915_READ(IER); 1635 } 1636 error->eir = I915_READ(EIR); 1637 error->pgtbl_er = I915_READ(PGTBL_ER); 1638 } 1639 1640 static const char * 1641 error_msg(struct i915_gpu_state *error, unsigned long engines, const char *msg) 1642 { 1643 int len; 1644 int i; 1645 1646 for (i = 0; i < ARRAY_SIZE(error->engine); i++) 1647 if (!error->engine[i].context.pid) 1648 engines &= ~BIT(i); 1649 1650 len = scnprintf(error->error_msg, sizeof(error->error_msg), 1651 "GPU HANG: ecode %d:%lx:0x%08x", 1652 INTEL_GEN(error->i915), engines, 1653 i915_error_generate_code(error, engines)); 1654 if (engines) { 1655 /* Just show the first executing process, more is confusing */ 1656 i = __ffs(engines); 1657 len += scnprintf(error->error_msg + len, 1658 sizeof(error->error_msg) - len, 1659 ", in %s [%d]", 1660 error->engine[i].context.comm, 1661 error->engine[i].context.pid); 1662 } 1663 if (msg) 1664 len += scnprintf(error->error_msg + len, 1665 sizeof(error->error_msg) - len, 1666 ", %s", msg); 1667 1668 return error->error_msg; 1669 } 1670 1671 static void capture_gen_state(struct i915_gpu_state *error) 1672 { 1673 struct drm_i915_private *i915 = error->i915; 1674 1675 error->awake = i915->gt.awake; 1676 error->wakelock = atomic_read(&i915->runtime_pm.wakeref_count); 1677 error->suspended = i915->runtime_pm.suspended; 1678 1679 error->iommu = -1; 1680 #ifdef CONFIG_INTEL_IOMMU 1681 error->iommu = intel_iommu_gfx_mapped; 1682 #endif 1683 error->reset_count = i915_reset_count(&i915->gpu_error); 1684 error->suspend_count = i915->suspend_count; 1685 1686 memcpy(&error->device_info, 1687 INTEL_INFO(i915), 1688 sizeof(error->device_info)); 1689 memcpy(&error->runtime_info, 1690 RUNTIME_INFO(i915), 1691 sizeof(error->runtime_info)); 1692 error->driver_caps = i915->caps; 1693 } 1694 1695 static void capture_params(struct i915_gpu_state *error) 1696 { 1697 i915_params_copy(&error->params, &i915_modparams); 1698 } 1699 1700 static unsigned long capture_find_epoch(const struct i915_gpu_state *error) 1701 { 1702 unsigned long epoch = error->capture; 1703 int i; 1704 1705 for (i = 0; i < ARRAY_SIZE(error->engine); i++) { 1706 const struct drm_i915_error_engine *ee = &error->engine[i]; 1707 1708 if (ee->hangcheck_timestamp && 1709 time_before(ee->hangcheck_timestamp, epoch)) 1710 epoch = ee->hangcheck_timestamp; 1711 } 1712 1713 return epoch; 1714 } 1715 1716 static void capture_finish(struct i915_gpu_state *error) 1717 { 1718 struct i915_ggtt *ggtt = &error->i915->ggtt; 1719 const u64 slot = ggtt->error_capture.start; 1720 1721 ggtt->vm.clear_range(&ggtt->vm, slot, PAGE_SIZE); 1722 } 1723 1724 static int capture(void *data) 1725 { 1726 struct i915_gpu_state *error = data; 1727 1728 error->time = ktime_get_real(); 1729 error->boottime = ktime_get_boottime(); 1730 error->uptime = ktime_sub(ktime_get(), 1731 error->i915->gt.last_init_time); 1732 error->capture = jiffies; 1733 1734 capture_params(error); 1735 capture_gen_state(error); 1736 capture_uc_state(error); 1737 capture_reg_state(error); 1738 gem_record_fences(error); 1739 gem_record_rings(error); 1740 capture_active_buffers(error); 1741 capture_pinned_buffers(error); 1742 1743 error->overlay = intel_overlay_capture_error_state(error->i915); 1744 error->display = intel_display_capture_error_state(error->i915); 1745 1746 error->epoch = capture_find_epoch(error); 1747 1748 capture_finish(error); 1749 return 0; 1750 } 1751 1752 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x)) 1753 1754 struct i915_gpu_state * 1755 i915_capture_gpu_state(struct drm_i915_private *i915) 1756 { 1757 struct i915_gpu_state *error; 1758 1759 /* Check if GPU capture has been disabled */ 1760 error = READ_ONCE(i915->gpu_error.first_error); 1761 if (IS_ERR(error)) 1762 return error; 1763 1764 error = kzalloc(sizeof(*error), GFP_ATOMIC); 1765 if (!error) { 1766 i915_disable_error_state(i915, -ENOMEM); 1767 return ERR_PTR(-ENOMEM); 1768 } 1769 1770 kref_init(&error->ref); 1771 error->i915 = i915; 1772 1773 stop_machine(capture, error, NULL); 1774 1775 return error; 1776 } 1777 1778 /** 1779 * i915_capture_error_state - capture an error record for later analysis 1780 * @i915: i915 device 1781 * @engine_mask: the mask of engines triggering the hang 1782 * @msg: a message to insert into the error capture header 1783 * 1784 * Should be called when an error is detected (either a hang or an error 1785 * interrupt) to capture error state from the time of the error. Fills 1786 * out a structure which becomes available in debugfs for user level tools 1787 * to pick up. 1788 */ 1789 void i915_capture_error_state(struct drm_i915_private *i915, 1790 unsigned long engine_mask, 1791 const char *msg) 1792 { 1793 static bool warned; 1794 struct i915_gpu_state *error; 1795 unsigned long flags; 1796 1797 if (!i915_modparams.error_capture) 1798 return; 1799 1800 if (READ_ONCE(i915->gpu_error.first_error)) 1801 return; 1802 1803 error = i915_capture_gpu_state(i915); 1804 if (IS_ERR(error)) 1805 return; 1806 1807 dev_info(i915->drm.dev, "%s\n", error_msg(error, engine_mask, msg)); 1808 1809 if (!error->simulated) { 1810 spin_lock_irqsave(&i915->gpu_error.lock, flags); 1811 if (!i915->gpu_error.first_error) { 1812 i915->gpu_error.first_error = error; 1813 error = NULL; 1814 } 1815 spin_unlock_irqrestore(&i915->gpu_error.lock, flags); 1816 } 1817 1818 if (error) { 1819 __i915_gpu_state_free(&error->ref); 1820 return; 1821 } 1822 1823 if (!warned && 1824 ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) { 1825 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n"); 1826 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n"); 1827 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n"); 1828 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n"); 1829 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", 1830 i915->drm.primary->index); 1831 warned = true; 1832 } 1833 } 1834 1835 struct i915_gpu_state * 1836 i915_first_error_state(struct drm_i915_private *i915) 1837 { 1838 struct i915_gpu_state *error; 1839 1840 spin_lock_irq(&i915->gpu_error.lock); 1841 error = i915->gpu_error.first_error; 1842 if (!IS_ERR_OR_NULL(error)) 1843 i915_gpu_state_get(error); 1844 spin_unlock_irq(&i915->gpu_error.lock); 1845 1846 return error; 1847 } 1848 1849 void i915_reset_error_state(struct drm_i915_private *i915) 1850 { 1851 struct i915_gpu_state *error; 1852 1853 spin_lock_irq(&i915->gpu_error.lock); 1854 error = i915->gpu_error.first_error; 1855 if (error != ERR_PTR(-ENODEV)) /* if disabled, always disabled */ 1856 i915->gpu_error.first_error = NULL; 1857 spin_unlock_irq(&i915->gpu_error.lock); 1858 1859 if (!IS_ERR_OR_NULL(error)) 1860 i915_gpu_state_put(error); 1861 } 1862 1863 void i915_disable_error_state(struct drm_i915_private *i915, int err) 1864 { 1865 spin_lock_irq(&i915->gpu_error.lock); 1866 if (!i915->gpu_error.first_error) 1867 i915->gpu_error.first_error = ERR_PTR(err); 1868 spin_unlock_irq(&i915->gpu_error.lock); 1869 } 1870