1 /* 2 * Copyright (c) 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * Mika Kuoppala <mika.kuoppala@intel.com> 27 * 28 */ 29 30 #include <generated/utsrelease.h> 31 #include <linux/stop_machine.h> 32 #include <linux/zlib.h> 33 #include "i915_drv.h" 34 35 static const char *engine_str(int engine) 36 { 37 switch (engine) { 38 case RCS: return "render"; 39 case VCS: return "bsd"; 40 case BCS: return "blt"; 41 case VECS: return "vebox"; 42 case VCS2: return "bsd2"; 43 default: return ""; 44 } 45 } 46 47 static const char *tiling_flag(int tiling) 48 { 49 switch (tiling) { 50 default: 51 case I915_TILING_NONE: return ""; 52 case I915_TILING_X: return " X"; 53 case I915_TILING_Y: return " Y"; 54 } 55 } 56 57 static const char *dirty_flag(int dirty) 58 { 59 return dirty ? " dirty" : ""; 60 } 61 62 static const char *purgeable_flag(int purgeable) 63 { 64 return purgeable ? " purgeable" : ""; 65 } 66 67 static bool __i915_error_ok(struct drm_i915_error_state_buf *e) 68 { 69 70 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) { 71 e->err = -ENOSPC; 72 return false; 73 } 74 75 if (e->bytes == e->size - 1 || e->err) 76 return false; 77 78 return true; 79 } 80 81 static bool __i915_error_seek(struct drm_i915_error_state_buf *e, 82 unsigned len) 83 { 84 if (e->pos + len <= e->start) { 85 e->pos += len; 86 return false; 87 } 88 89 /* First vsnprintf needs to fit in its entirety for memmove */ 90 if (len >= e->size) { 91 e->err = -EIO; 92 return false; 93 } 94 95 return true; 96 } 97 98 static void __i915_error_advance(struct drm_i915_error_state_buf *e, 99 unsigned len) 100 { 101 /* If this is first printf in this window, adjust it so that 102 * start position matches start of the buffer 103 */ 104 105 if (e->pos < e->start) { 106 const size_t off = e->start - e->pos; 107 108 /* Should not happen but be paranoid */ 109 if (off > len || e->bytes) { 110 e->err = -EIO; 111 return; 112 } 113 114 memmove(e->buf, e->buf + off, len - off); 115 e->bytes = len - off; 116 e->pos = e->start; 117 return; 118 } 119 120 e->bytes += len; 121 e->pos += len; 122 } 123 124 __printf(2, 0) 125 static void i915_error_vprintf(struct drm_i915_error_state_buf *e, 126 const char *f, va_list args) 127 { 128 unsigned len; 129 130 if (!__i915_error_ok(e)) 131 return; 132 133 /* Seek the first printf which is hits start position */ 134 if (e->pos < e->start) { 135 va_list tmp; 136 137 va_copy(tmp, args); 138 len = vsnprintf(NULL, 0, f, tmp); 139 va_end(tmp); 140 141 if (!__i915_error_seek(e, len)) 142 return; 143 } 144 145 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args); 146 if (len >= e->size - e->bytes) 147 len = e->size - e->bytes - 1; 148 149 __i915_error_advance(e, len); 150 } 151 152 static void i915_error_puts(struct drm_i915_error_state_buf *e, 153 const char *str) 154 { 155 unsigned len; 156 157 if (!__i915_error_ok(e)) 158 return; 159 160 len = strlen(str); 161 162 /* Seek the first printf which is hits start position */ 163 if (e->pos < e->start) { 164 if (!__i915_error_seek(e, len)) 165 return; 166 } 167 168 if (len >= e->size - e->bytes) 169 len = e->size - e->bytes - 1; 170 memcpy(e->buf + e->bytes, str, len); 171 172 __i915_error_advance(e, len); 173 } 174 175 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) 176 #define err_puts(e, s) i915_error_puts(e, s) 177 178 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR 179 180 struct compress { 181 struct z_stream_s zstream; 182 void *tmp; 183 }; 184 185 static bool compress_init(struct compress *c) 186 { 187 struct z_stream_s *zstream = memset(&c->zstream, 0, sizeof(c->zstream)); 188 189 zstream->workspace = 190 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL), 191 GFP_ATOMIC | __GFP_NOWARN); 192 if (!zstream->workspace) 193 return false; 194 195 if (zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) != Z_OK) { 196 kfree(zstream->workspace); 197 return false; 198 } 199 200 c->tmp = NULL; 201 if (i915_has_memcpy_from_wc()) 202 c->tmp = (void *)__get_free_page(GFP_ATOMIC | __GFP_NOWARN); 203 204 return true; 205 } 206 207 static int compress_page(struct compress *c, 208 void *src, 209 struct drm_i915_error_object *dst) 210 { 211 struct z_stream_s *zstream = &c->zstream; 212 213 zstream->next_in = src; 214 if (c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE)) 215 zstream->next_in = c->tmp; 216 zstream->avail_in = PAGE_SIZE; 217 218 do { 219 if (zstream->avail_out == 0) { 220 unsigned long page; 221 222 page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN); 223 if (!page) 224 return -ENOMEM; 225 226 dst->pages[dst->page_count++] = (void *)page; 227 228 zstream->next_out = (void *)page; 229 zstream->avail_out = PAGE_SIZE; 230 } 231 232 if (zlib_deflate(zstream, Z_SYNC_FLUSH) != Z_OK) 233 return -EIO; 234 } while (zstream->avail_in); 235 236 /* Fallback to uncompressed if we increase size? */ 237 if (0 && zstream->total_out > zstream->total_in) 238 return -E2BIG; 239 240 return 0; 241 } 242 243 static void compress_fini(struct compress *c, 244 struct drm_i915_error_object *dst) 245 { 246 struct z_stream_s *zstream = &c->zstream; 247 248 if (dst) { 249 zlib_deflate(zstream, Z_FINISH); 250 dst->unused = zstream->avail_out; 251 } 252 253 zlib_deflateEnd(zstream); 254 kfree(zstream->workspace); 255 256 if (c->tmp) 257 free_page((unsigned long)c->tmp); 258 } 259 260 static void err_compression_marker(struct drm_i915_error_state_buf *m) 261 { 262 err_puts(m, ":"); 263 } 264 265 #else 266 267 struct compress { 268 }; 269 270 static bool compress_init(struct compress *c) 271 { 272 return true; 273 } 274 275 static int compress_page(struct compress *c, 276 void *src, 277 struct drm_i915_error_object *dst) 278 { 279 unsigned long page; 280 void *ptr; 281 282 page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN); 283 if (!page) 284 return -ENOMEM; 285 286 ptr = (void *)page; 287 if (!i915_memcpy_from_wc(ptr, src, PAGE_SIZE)) 288 memcpy(ptr, src, PAGE_SIZE); 289 dst->pages[dst->page_count++] = ptr; 290 291 return 0; 292 } 293 294 static void compress_fini(struct compress *c, 295 struct drm_i915_error_object *dst) 296 { 297 } 298 299 static void err_compression_marker(struct drm_i915_error_state_buf *m) 300 { 301 err_puts(m, "~"); 302 } 303 304 #endif 305 306 static void print_error_buffers(struct drm_i915_error_state_buf *m, 307 const char *name, 308 struct drm_i915_error_buffer *err, 309 int count) 310 { 311 int i; 312 313 err_printf(m, "%s [%d]:\n", name, count); 314 315 while (count--) { 316 err_printf(m, " %08x_%08x %8u %02x %02x [ ", 317 upper_32_bits(err->gtt_offset), 318 lower_32_bits(err->gtt_offset), 319 err->size, 320 err->read_domains, 321 err->write_domain); 322 for (i = 0; i < I915_NUM_ENGINES; i++) 323 err_printf(m, "%02x ", err->rseqno[i]); 324 325 err_printf(m, "] %02x", err->wseqno); 326 err_puts(m, tiling_flag(err->tiling)); 327 err_puts(m, dirty_flag(err->dirty)); 328 err_puts(m, purgeable_flag(err->purgeable)); 329 err_puts(m, err->userptr ? " userptr" : ""); 330 err_puts(m, err->engine != -1 ? " " : ""); 331 err_puts(m, engine_str(err->engine)); 332 err_puts(m, i915_cache_level_str(m->i915, err->cache_level)); 333 334 if (err->name) 335 err_printf(m, " (name: %d)", err->name); 336 if (err->fence_reg != I915_FENCE_REG_NONE) 337 err_printf(m, " (fence: %d)", err->fence_reg); 338 339 err_puts(m, "\n"); 340 err++; 341 } 342 } 343 344 static void error_print_instdone(struct drm_i915_error_state_buf *m, 345 const struct drm_i915_error_engine *ee) 346 { 347 int slice; 348 int subslice; 349 350 err_printf(m, " INSTDONE: 0x%08x\n", 351 ee->instdone.instdone); 352 353 if (ee->engine_id != RCS || INTEL_GEN(m->i915) <= 3) 354 return; 355 356 err_printf(m, " SC_INSTDONE: 0x%08x\n", 357 ee->instdone.slice_common); 358 359 if (INTEL_GEN(m->i915) <= 6) 360 return; 361 362 for_each_instdone_slice_subslice(m->i915, slice, subslice) 363 err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n", 364 slice, subslice, 365 ee->instdone.sampler[slice][subslice]); 366 367 for_each_instdone_slice_subslice(m->i915, slice, subslice) 368 err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n", 369 slice, subslice, 370 ee->instdone.row[slice][subslice]); 371 } 372 373 static void error_print_request(struct drm_i915_error_state_buf *m, 374 const char *prefix, 375 const struct drm_i915_error_request *erq) 376 { 377 if (!erq->seqno) 378 return; 379 380 err_printf(m, "%s pid %d, ban score %d, seqno %8x:%08x, emitted %dms ago, head %08x, tail %08x\n", 381 prefix, erq->pid, erq->ban_score, 382 erq->context, erq->seqno, 383 jiffies_to_msecs(jiffies - erq->jiffies), 384 erq->head, erq->tail); 385 } 386 387 static void error_print_context(struct drm_i915_error_state_buf *m, 388 const char *header, 389 const struct drm_i915_error_context *ctx) 390 { 391 err_printf(m, "%s%s[%d] user_handle %d hw_id %d, ban score %d guilty %d active %d\n", 392 header, ctx->comm, ctx->pid, ctx->handle, ctx->hw_id, 393 ctx->ban_score, ctx->guilty, ctx->active); 394 } 395 396 static void error_print_engine(struct drm_i915_error_state_buf *m, 397 const struct drm_i915_error_engine *ee) 398 { 399 err_printf(m, "%s command stream:\n", engine_str(ee->engine_id)); 400 err_printf(m, " START: 0x%08x\n", ee->start); 401 err_printf(m, " HEAD: 0x%08x [0x%08x]\n", ee->head, ee->rq_head); 402 err_printf(m, " TAIL: 0x%08x [0x%08x, 0x%08x]\n", 403 ee->tail, ee->rq_post, ee->rq_tail); 404 err_printf(m, " CTL: 0x%08x\n", ee->ctl); 405 err_printf(m, " MODE: 0x%08x\n", ee->mode); 406 err_printf(m, " HWS: 0x%08x\n", ee->hws); 407 err_printf(m, " ACTHD: 0x%08x %08x\n", 408 (u32)(ee->acthd>>32), (u32)ee->acthd); 409 err_printf(m, " IPEIR: 0x%08x\n", ee->ipeir); 410 err_printf(m, " IPEHR: 0x%08x\n", ee->ipehr); 411 412 error_print_instdone(m, ee); 413 414 if (ee->batchbuffer) { 415 u64 start = ee->batchbuffer->gtt_offset; 416 u64 end = start + ee->batchbuffer->gtt_size; 417 418 err_printf(m, " batch: [0x%08x_%08x, 0x%08x_%08x]\n", 419 upper_32_bits(start), lower_32_bits(start), 420 upper_32_bits(end), lower_32_bits(end)); 421 } 422 if (INTEL_GEN(m->i915) >= 4) { 423 err_printf(m, " BBADDR: 0x%08x_%08x\n", 424 (u32)(ee->bbaddr>>32), (u32)ee->bbaddr); 425 err_printf(m, " BB_STATE: 0x%08x\n", ee->bbstate); 426 err_printf(m, " INSTPS: 0x%08x\n", ee->instps); 427 } 428 err_printf(m, " INSTPM: 0x%08x\n", ee->instpm); 429 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr), 430 lower_32_bits(ee->faddr)); 431 if (INTEL_GEN(m->i915) >= 6) { 432 err_printf(m, " RC PSMI: 0x%08x\n", ee->rc_psmi); 433 err_printf(m, " FAULT_REG: 0x%08x\n", ee->fault_reg); 434 err_printf(m, " SYNC_0: 0x%08x\n", 435 ee->semaphore_mboxes[0]); 436 err_printf(m, " SYNC_1: 0x%08x\n", 437 ee->semaphore_mboxes[1]); 438 if (HAS_VEBOX(m->i915)) 439 err_printf(m, " SYNC_2: 0x%08x\n", 440 ee->semaphore_mboxes[2]); 441 } 442 if (USES_PPGTT(m->i915)) { 443 err_printf(m, " GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode); 444 445 if (INTEL_GEN(m->i915) >= 8) { 446 int i; 447 for (i = 0; i < 4; i++) 448 err_printf(m, " PDP%d: 0x%016llx\n", 449 i, ee->vm_info.pdp[i]); 450 } else { 451 err_printf(m, " PP_DIR_BASE: 0x%08x\n", 452 ee->vm_info.pp_dir_base); 453 } 454 } 455 err_printf(m, " seqno: 0x%08x\n", ee->seqno); 456 err_printf(m, " last_seqno: 0x%08x\n", ee->last_seqno); 457 err_printf(m, " waiting: %s\n", yesno(ee->waiting)); 458 err_printf(m, " ring->head: 0x%08x\n", ee->cpu_ring_head); 459 err_printf(m, " ring->tail: 0x%08x\n", ee->cpu_ring_tail); 460 err_printf(m, " hangcheck stall: %s\n", yesno(ee->hangcheck_stalled)); 461 err_printf(m, " hangcheck action: %s\n", 462 hangcheck_action_to_str(ee->hangcheck_action)); 463 err_printf(m, " hangcheck action timestamp: %lu, %u ms ago\n", 464 ee->hangcheck_timestamp, 465 jiffies_to_msecs(jiffies - ee->hangcheck_timestamp)); 466 467 error_print_request(m, " ELSP[0]: ", &ee->execlist[0]); 468 error_print_request(m, " ELSP[1]: ", &ee->execlist[1]); 469 error_print_context(m, " Active context: ", &ee->context); 470 } 471 472 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) 473 { 474 va_list args; 475 476 va_start(args, f); 477 i915_error_vprintf(e, f, args); 478 va_end(args); 479 } 480 481 static int 482 ascii85_encode_len(int len) 483 { 484 return DIV_ROUND_UP(len, 4); 485 } 486 487 static bool 488 ascii85_encode(u32 in, char *out) 489 { 490 int i; 491 492 if (in == 0) 493 return false; 494 495 out[5] = '\0'; 496 for (i = 5; i--; ) { 497 out[i] = '!' + in % 85; 498 in /= 85; 499 } 500 501 return true; 502 } 503 504 static void print_error_obj(struct drm_i915_error_state_buf *m, 505 struct intel_engine_cs *engine, 506 const char *name, 507 struct drm_i915_error_object *obj) 508 { 509 char out[6]; 510 int page; 511 512 if (!obj) 513 return; 514 515 if (name) { 516 err_printf(m, "%s --- %s = 0x%08x %08x\n", 517 engine ? engine->name : "global", name, 518 upper_32_bits(obj->gtt_offset), 519 lower_32_bits(obj->gtt_offset)); 520 } 521 522 err_compression_marker(m); 523 for (page = 0; page < obj->page_count; page++) { 524 int i, len; 525 526 len = PAGE_SIZE; 527 if (page == obj->page_count - 1) 528 len -= obj->unused; 529 len = ascii85_encode_len(len); 530 531 for (i = 0; i < len; i++) { 532 if (ascii85_encode(obj->pages[page][i], out)) 533 err_puts(m, out); 534 else 535 err_puts(m, "z"); 536 } 537 } 538 err_puts(m, "\n"); 539 } 540 541 static void err_print_capabilities(struct drm_i915_error_state_buf *m, 542 const struct intel_device_info *info) 543 { 544 #define PRINT_FLAG(x) err_printf(m, #x ": %s\n", yesno(info->x)) 545 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG); 546 #undef PRINT_FLAG 547 } 548 549 static __always_inline void err_print_param(struct drm_i915_error_state_buf *m, 550 const char *name, 551 const char *type, 552 const void *x) 553 { 554 if (!__builtin_strcmp(type, "bool")) 555 err_printf(m, "i915.%s=%s\n", name, yesno(*(const bool *)x)); 556 else if (!__builtin_strcmp(type, "int")) 557 err_printf(m, "i915.%s=%d\n", name, *(const int *)x); 558 else if (!__builtin_strcmp(type, "unsigned int")) 559 err_printf(m, "i915.%s=%u\n", name, *(const unsigned int *)x); 560 else if (!__builtin_strcmp(type, "char *")) 561 err_printf(m, "i915.%s=%s\n", name, *(const char **)x); 562 else 563 BUILD_BUG(); 564 } 565 566 static void err_print_params(struct drm_i915_error_state_buf *m, 567 const struct i915_params *p) 568 { 569 #define PRINT(T, x) err_print_param(m, #x, #T, &p->x); 570 I915_PARAMS_FOR_EACH(PRINT); 571 #undef PRINT 572 } 573 574 static void err_print_pciid(struct drm_i915_error_state_buf *m, 575 struct drm_i915_private *i915) 576 { 577 struct pci_dev *pdev = i915->drm.pdev; 578 579 err_printf(m, "PCI ID: 0x%04x\n", pdev->device); 580 err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision); 581 err_printf(m, "PCI Subsystem: %04x:%04x\n", 582 pdev->subsystem_vendor, 583 pdev->subsystem_device); 584 } 585 586 int i915_error_state_to_str(struct drm_i915_error_state_buf *m, 587 const struct i915_gpu_state *error) 588 { 589 struct drm_i915_private *dev_priv = m->i915; 590 struct drm_i915_error_object *obj; 591 int i, j; 592 593 if (!error) { 594 err_printf(m, "No error state collected\n"); 595 return 0; 596 } 597 598 if (*error->error_msg) 599 err_printf(m, "%s\n", error->error_msg); 600 err_printf(m, "Kernel: " UTS_RELEASE "\n"); 601 err_printf(m, "Time: %ld s %ld us\n", 602 error->time.tv_sec, error->time.tv_usec); 603 err_printf(m, "Boottime: %ld s %ld us\n", 604 error->boottime.tv_sec, error->boottime.tv_usec); 605 err_printf(m, "Uptime: %ld s %ld us\n", 606 error->uptime.tv_sec, error->uptime.tv_usec); 607 608 for (i = 0; i < ARRAY_SIZE(error->engine); i++) { 609 if (error->engine[i].hangcheck_stalled && 610 error->engine[i].context.pid) { 611 err_printf(m, "Active process (on ring %s): %s [%d], score %d\n", 612 engine_str(i), 613 error->engine[i].context.comm, 614 error->engine[i].context.pid, 615 error->engine[i].context.ban_score); 616 } 617 } 618 err_printf(m, "Reset count: %u\n", error->reset_count); 619 err_printf(m, "Suspend count: %u\n", error->suspend_count); 620 err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform)); 621 err_print_pciid(m, error->i915); 622 623 err_printf(m, "IOMMU enabled?: %d\n", error->iommu); 624 625 if (HAS_CSR(dev_priv)) { 626 struct intel_csr *csr = &dev_priv->csr; 627 628 err_printf(m, "DMC loaded: %s\n", 629 yesno(csr->dmc_payload != NULL)); 630 err_printf(m, "DMC fw version: %d.%d\n", 631 CSR_VERSION_MAJOR(csr->version), 632 CSR_VERSION_MINOR(csr->version)); 633 } 634 635 err_printf(m, "GT awake: %s\n", yesno(error->awake)); 636 err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock)); 637 err_printf(m, "PM suspended: %s\n", yesno(error->suspended)); 638 err_printf(m, "EIR: 0x%08x\n", error->eir); 639 err_printf(m, "IER: 0x%08x\n", error->ier); 640 for (i = 0; i < error->ngtier; i++) 641 err_printf(m, "GTIER[%d]: 0x%08x\n", i, error->gtier[i]); 642 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er); 643 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake); 644 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr); 645 err_printf(m, "CCID: 0x%08x\n", error->ccid); 646 err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings); 647 648 for (i = 0; i < error->nfence; i++) 649 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]); 650 651 if (INTEL_GEN(dev_priv) >= 6) { 652 err_printf(m, "ERROR: 0x%08x\n", error->error); 653 654 if (INTEL_GEN(dev_priv) >= 8) 655 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n", 656 error->fault_data1, error->fault_data0); 657 658 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); 659 } 660 661 if (IS_GEN7(dev_priv)) 662 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int); 663 664 for (i = 0; i < ARRAY_SIZE(error->engine); i++) { 665 if (error->engine[i].engine_id != -1) 666 error_print_engine(m, &error->engine[i]); 667 } 668 669 for (i = 0; i < ARRAY_SIZE(error->active_vm); i++) { 670 char buf[128]; 671 int len, first = 1; 672 673 if (!error->active_vm[i]) 674 break; 675 676 len = scnprintf(buf, sizeof(buf), "Active ("); 677 for (j = 0; j < ARRAY_SIZE(error->engine); j++) { 678 if (error->engine[j].vm != error->active_vm[i]) 679 continue; 680 681 len += scnprintf(buf + len, sizeof(buf), "%s%s", 682 first ? "" : ", ", 683 dev_priv->engine[j]->name); 684 first = 0; 685 } 686 scnprintf(buf + len, sizeof(buf), ")"); 687 print_error_buffers(m, buf, 688 error->active_bo[i], 689 error->active_bo_count[i]); 690 } 691 692 print_error_buffers(m, "Pinned (global)", 693 error->pinned_bo, 694 error->pinned_bo_count); 695 696 for (i = 0; i < ARRAY_SIZE(error->engine); i++) { 697 const struct drm_i915_error_engine *ee = &error->engine[i]; 698 699 obj = ee->batchbuffer; 700 if (obj) { 701 err_puts(m, dev_priv->engine[i]->name); 702 if (ee->context.pid) 703 err_printf(m, " (submitted by %s [%d], ctx %d [%d], score %d)", 704 ee->context.comm, 705 ee->context.pid, 706 ee->context.handle, 707 ee->context.hw_id, 708 ee->context.ban_score); 709 err_printf(m, " --- gtt_offset = 0x%08x %08x\n", 710 upper_32_bits(obj->gtt_offset), 711 lower_32_bits(obj->gtt_offset)); 712 print_error_obj(m, dev_priv->engine[i], NULL, obj); 713 } 714 715 for (j = 0; j < ee->user_bo_count; j++) 716 print_error_obj(m, dev_priv->engine[i], 717 "user", ee->user_bo[j]); 718 719 if (ee->num_requests) { 720 err_printf(m, "%s --- %d requests\n", 721 dev_priv->engine[i]->name, 722 ee->num_requests); 723 for (j = 0; j < ee->num_requests; j++) 724 error_print_request(m, " ", &ee->requests[j]); 725 } 726 727 if (IS_ERR(ee->waiters)) { 728 err_printf(m, "%s --- ? waiters [unable to acquire spinlock]\n", 729 dev_priv->engine[i]->name); 730 } else if (ee->num_waiters) { 731 err_printf(m, "%s --- %d waiters\n", 732 dev_priv->engine[i]->name, 733 ee->num_waiters); 734 for (j = 0; j < ee->num_waiters; j++) { 735 err_printf(m, " seqno 0x%08x for %s [%d]\n", 736 ee->waiters[j].seqno, 737 ee->waiters[j].comm, 738 ee->waiters[j].pid); 739 } 740 } 741 742 print_error_obj(m, dev_priv->engine[i], 743 "ringbuffer", ee->ringbuffer); 744 745 print_error_obj(m, dev_priv->engine[i], 746 "HW Status", ee->hws_page); 747 748 print_error_obj(m, dev_priv->engine[i], 749 "HW context", ee->ctx); 750 751 print_error_obj(m, dev_priv->engine[i], 752 "WA context", ee->wa_ctx); 753 754 print_error_obj(m, dev_priv->engine[i], 755 "WA batchbuffer", ee->wa_batchbuffer); 756 } 757 758 print_error_obj(m, NULL, "Semaphores", error->semaphore); 759 760 print_error_obj(m, NULL, "GuC log buffer", error->guc_log); 761 762 if (error->overlay) 763 intel_overlay_print_error_state(m, error->overlay); 764 765 if (error->display) 766 intel_display_print_error_state(m, error->display); 767 768 err_print_capabilities(m, &error->device_info); 769 err_print_params(m, &error->params); 770 771 if (m->bytes == 0 && m->err) 772 return m->err; 773 774 return 0; 775 } 776 777 int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf, 778 struct drm_i915_private *i915, 779 size_t count, loff_t pos) 780 { 781 memset(ebuf, 0, sizeof(*ebuf)); 782 ebuf->i915 = i915; 783 784 /* We need to have enough room to store any i915_error_state printf 785 * so that we can move it to start position. 786 */ 787 ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE; 788 ebuf->buf = kmalloc(ebuf->size, 789 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN); 790 791 if (ebuf->buf == NULL) { 792 ebuf->size = PAGE_SIZE; 793 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY); 794 } 795 796 if (ebuf->buf == NULL) { 797 ebuf->size = 128; 798 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY); 799 } 800 801 if (ebuf->buf == NULL) 802 return -ENOMEM; 803 804 ebuf->start = pos; 805 806 return 0; 807 } 808 809 static void i915_error_object_free(struct drm_i915_error_object *obj) 810 { 811 int page; 812 813 if (obj == NULL) 814 return; 815 816 for (page = 0; page < obj->page_count; page++) 817 free_page((unsigned long)obj->pages[page]); 818 819 kfree(obj); 820 } 821 822 static __always_inline void free_param(const char *type, void *x) 823 { 824 if (!__builtin_strcmp(type, "char *")) 825 kfree(*(void **)x); 826 } 827 828 void __i915_gpu_state_free(struct kref *error_ref) 829 { 830 struct i915_gpu_state *error = 831 container_of(error_ref, typeof(*error), ref); 832 long i, j; 833 834 for (i = 0; i < ARRAY_SIZE(error->engine); i++) { 835 struct drm_i915_error_engine *ee = &error->engine[i]; 836 837 for (j = 0; j < ee->user_bo_count; j++) 838 i915_error_object_free(ee->user_bo[j]); 839 kfree(ee->user_bo); 840 841 i915_error_object_free(ee->batchbuffer); 842 i915_error_object_free(ee->wa_batchbuffer); 843 i915_error_object_free(ee->ringbuffer); 844 i915_error_object_free(ee->hws_page); 845 i915_error_object_free(ee->ctx); 846 i915_error_object_free(ee->wa_ctx); 847 848 kfree(ee->requests); 849 if (!IS_ERR_OR_NULL(ee->waiters)) 850 kfree(ee->waiters); 851 } 852 853 i915_error_object_free(error->semaphore); 854 i915_error_object_free(error->guc_log); 855 856 for (i = 0; i < ARRAY_SIZE(error->active_bo); i++) 857 kfree(error->active_bo[i]); 858 kfree(error->pinned_bo); 859 860 kfree(error->overlay); 861 kfree(error->display); 862 863 #define FREE(T, x) free_param(#T, &error->params.x); 864 I915_PARAMS_FOR_EACH(FREE); 865 #undef FREE 866 867 kfree(error); 868 } 869 870 static struct drm_i915_error_object * 871 i915_error_object_create(struct drm_i915_private *i915, 872 struct i915_vma *vma) 873 { 874 struct i915_ggtt *ggtt = &i915->ggtt; 875 const u64 slot = ggtt->error_capture.start; 876 struct drm_i915_error_object *dst; 877 struct compress compress; 878 unsigned long num_pages; 879 struct sgt_iter iter; 880 dma_addr_t dma; 881 882 if (!vma) 883 return NULL; 884 885 num_pages = min_t(u64, vma->size, vma->obj->base.size) >> PAGE_SHIFT; 886 num_pages = DIV_ROUND_UP(10 * num_pages, 8); /* worstcase zlib growth */ 887 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), 888 GFP_ATOMIC | __GFP_NOWARN); 889 if (!dst) 890 return NULL; 891 892 dst->gtt_offset = vma->node.start; 893 dst->gtt_size = vma->node.size; 894 dst->page_count = 0; 895 dst->unused = 0; 896 897 if (!compress_init(&compress)) { 898 kfree(dst); 899 return NULL; 900 } 901 902 for_each_sgt_dma(dma, iter, vma->pages) { 903 void __iomem *s; 904 int ret; 905 906 ggtt->base.insert_page(&ggtt->base, dma, slot, 907 I915_CACHE_NONE, 0); 908 909 s = io_mapping_map_atomic_wc(&ggtt->mappable, slot); 910 ret = compress_page(&compress, (void __force *)s, dst); 911 io_mapping_unmap_atomic(s); 912 913 if (ret) 914 goto unwind; 915 } 916 goto out; 917 918 unwind: 919 while (dst->page_count--) 920 free_page((unsigned long)dst->pages[dst->page_count]); 921 kfree(dst); 922 dst = NULL; 923 924 out: 925 compress_fini(&compress, dst); 926 ggtt->base.clear_range(&ggtt->base, slot, PAGE_SIZE); 927 return dst; 928 } 929 930 /* The error capture is special as tries to run underneath the normal 931 * locking rules - so we use the raw version of the i915_gem_active lookup. 932 */ 933 static inline uint32_t 934 __active_get_seqno(struct i915_gem_active *active) 935 { 936 struct drm_i915_gem_request *request; 937 938 request = __i915_gem_active_peek(active); 939 return request ? request->global_seqno : 0; 940 } 941 942 static inline int 943 __active_get_engine_id(struct i915_gem_active *active) 944 { 945 struct drm_i915_gem_request *request; 946 947 request = __i915_gem_active_peek(active); 948 return request ? request->engine->id : -1; 949 } 950 951 static void capture_bo(struct drm_i915_error_buffer *err, 952 struct i915_vma *vma) 953 { 954 struct drm_i915_gem_object *obj = vma->obj; 955 int i; 956 957 err->size = obj->base.size; 958 err->name = obj->base.name; 959 960 for (i = 0; i < I915_NUM_ENGINES; i++) 961 err->rseqno[i] = __active_get_seqno(&vma->last_read[i]); 962 err->wseqno = __active_get_seqno(&obj->frontbuffer_write); 963 err->engine = __active_get_engine_id(&obj->frontbuffer_write); 964 965 err->gtt_offset = vma->node.start; 966 err->read_domains = obj->base.read_domains; 967 err->write_domain = obj->base.write_domain; 968 err->fence_reg = vma->fence ? vma->fence->id : -1; 969 err->tiling = i915_gem_object_get_tiling(obj); 970 err->dirty = obj->mm.dirty; 971 err->purgeable = obj->mm.madv != I915_MADV_WILLNEED; 972 err->userptr = obj->userptr.mm != NULL; 973 err->cache_level = obj->cache_level; 974 } 975 976 static u32 capture_error_bo(struct drm_i915_error_buffer *err, 977 int count, struct list_head *head, 978 bool pinned_only) 979 { 980 struct i915_vma *vma; 981 int i = 0; 982 983 list_for_each_entry(vma, head, vm_link) { 984 if (pinned_only && !i915_vma_is_pinned(vma)) 985 continue; 986 987 capture_bo(err++, vma); 988 if (++i == count) 989 break; 990 } 991 992 return i; 993 } 994 995 /* Generate a semi-unique error code. The code is not meant to have meaning, The 996 * code's only purpose is to try to prevent false duplicated bug reports by 997 * grossly estimating a GPU error state. 998 * 999 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine 1000 * the hang if we could strip the GTT offset information from it. 1001 * 1002 * It's only a small step better than a random number in its current form. 1003 */ 1004 static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv, 1005 struct i915_gpu_state *error, 1006 int *engine_id) 1007 { 1008 uint32_t error_code = 0; 1009 int i; 1010 1011 /* IPEHR would be an ideal way to detect errors, as it's the gross 1012 * measure of "the command that hung." However, has some very common 1013 * synchronization commands which almost always appear in the case 1014 * strictly a client bug. Use instdone to differentiate those some. 1015 */ 1016 for (i = 0; i < I915_NUM_ENGINES; i++) { 1017 if (error->engine[i].hangcheck_stalled) { 1018 if (engine_id) 1019 *engine_id = i; 1020 1021 return error->engine[i].ipehr ^ 1022 error->engine[i].instdone.instdone; 1023 } 1024 } 1025 1026 return error_code; 1027 } 1028 1029 static void i915_gem_record_fences(struct drm_i915_private *dev_priv, 1030 struct i915_gpu_state *error) 1031 { 1032 int i; 1033 1034 if (INTEL_GEN(dev_priv) >= 6) { 1035 for (i = 0; i < dev_priv->num_fence_regs; i++) 1036 error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i)); 1037 } else if (INTEL_GEN(dev_priv) >= 4) { 1038 for (i = 0; i < dev_priv->num_fence_regs; i++) 1039 error->fence[i] = I915_READ64(FENCE_REG_965_LO(i)); 1040 } else { 1041 for (i = 0; i < dev_priv->num_fence_regs; i++) 1042 error->fence[i] = I915_READ(FENCE_REG(i)); 1043 } 1044 error->nfence = i; 1045 } 1046 1047 static inline u32 1048 gen8_engine_sync_index(struct intel_engine_cs *engine, 1049 struct intel_engine_cs *other) 1050 { 1051 int idx; 1052 1053 /* 1054 * rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2; 1055 * vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs; 1056 * bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs; 1057 * vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs; 1058 * vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs; 1059 */ 1060 1061 idx = (other - engine) - 1; 1062 if (idx < 0) 1063 idx += I915_NUM_ENGINES; 1064 1065 return idx; 1066 } 1067 1068 static void gen8_record_semaphore_state(struct i915_gpu_state *error, 1069 struct intel_engine_cs *engine, 1070 struct drm_i915_error_engine *ee) 1071 { 1072 struct drm_i915_private *dev_priv = engine->i915; 1073 struct intel_engine_cs *to; 1074 enum intel_engine_id id; 1075 1076 if (!error->semaphore) 1077 return; 1078 1079 for_each_engine(to, dev_priv, id) { 1080 int idx; 1081 u16 signal_offset; 1082 u32 *tmp; 1083 1084 if (engine == to) 1085 continue; 1086 1087 signal_offset = 1088 (GEN8_SIGNAL_OFFSET(engine, id) & (PAGE_SIZE - 1)) / 4; 1089 tmp = error->semaphore->pages[0]; 1090 idx = gen8_engine_sync_index(engine, to); 1091 1092 ee->semaphore_mboxes[idx] = tmp[signal_offset]; 1093 } 1094 } 1095 1096 static void gen6_record_semaphore_state(struct intel_engine_cs *engine, 1097 struct drm_i915_error_engine *ee) 1098 { 1099 struct drm_i915_private *dev_priv = engine->i915; 1100 1101 ee->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(engine->mmio_base)); 1102 ee->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(engine->mmio_base)); 1103 if (HAS_VEBOX(dev_priv)) 1104 ee->semaphore_mboxes[2] = 1105 I915_READ(RING_SYNC_2(engine->mmio_base)); 1106 } 1107 1108 static void error_record_engine_waiters(struct intel_engine_cs *engine, 1109 struct drm_i915_error_engine *ee) 1110 { 1111 struct intel_breadcrumbs *b = &engine->breadcrumbs; 1112 struct drm_i915_error_waiter *waiter; 1113 struct rb_node *rb; 1114 int count; 1115 1116 ee->num_waiters = 0; 1117 ee->waiters = NULL; 1118 1119 if (RB_EMPTY_ROOT(&b->waiters)) 1120 return; 1121 1122 if (!spin_trylock_irq(&b->rb_lock)) { 1123 ee->waiters = ERR_PTR(-EDEADLK); 1124 return; 1125 } 1126 1127 count = 0; 1128 for (rb = rb_first(&b->waiters); rb != NULL; rb = rb_next(rb)) 1129 count++; 1130 spin_unlock_irq(&b->rb_lock); 1131 1132 waiter = NULL; 1133 if (count) 1134 waiter = kmalloc_array(count, 1135 sizeof(struct drm_i915_error_waiter), 1136 GFP_ATOMIC); 1137 if (!waiter) 1138 return; 1139 1140 if (!spin_trylock_irq(&b->rb_lock)) { 1141 kfree(waiter); 1142 ee->waiters = ERR_PTR(-EDEADLK); 1143 return; 1144 } 1145 1146 ee->waiters = waiter; 1147 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { 1148 struct intel_wait *w = rb_entry(rb, typeof(*w), node); 1149 1150 strcpy(waiter->comm, w->tsk->comm); 1151 waiter->pid = w->tsk->pid; 1152 waiter->seqno = w->seqno; 1153 waiter++; 1154 1155 if (++ee->num_waiters == count) 1156 break; 1157 } 1158 spin_unlock_irq(&b->rb_lock); 1159 } 1160 1161 static void error_record_engine_registers(struct i915_gpu_state *error, 1162 struct intel_engine_cs *engine, 1163 struct drm_i915_error_engine *ee) 1164 { 1165 struct drm_i915_private *dev_priv = engine->i915; 1166 1167 if (INTEL_GEN(dev_priv) >= 6) { 1168 ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base)); 1169 ee->fault_reg = I915_READ(RING_FAULT_REG(engine)); 1170 if (INTEL_GEN(dev_priv) >= 8) 1171 gen8_record_semaphore_state(error, engine, ee); 1172 else 1173 gen6_record_semaphore_state(engine, ee); 1174 } 1175 1176 if (INTEL_GEN(dev_priv) >= 4) { 1177 ee->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base)); 1178 ee->ipeir = I915_READ(RING_IPEIR(engine->mmio_base)); 1179 ee->ipehr = I915_READ(RING_IPEHR(engine->mmio_base)); 1180 ee->instps = I915_READ(RING_INSTPS(engine->mmio_base)); 1181 ee->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base)); 1182 if (INTEL_GEN(dev_priv) >= 8) { 1183 ee->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32; 1184 ee->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32; 1185 } 1186 ee->bbstate = I915_READ(RING_BBSTATE(engine->mmio_base)); 1187 } else { 1188 ee->faddr = I915_READ(DMA_FADD_I8XX); 1189 ee->ipeir = I915_READ(IPEIR); 1190 ee->ipehr = I915_READ(IPEHR); 1191 } 1192 1193 intel_engine_get_instdone(engine, &ee->instdone); 1194 1195 ee->waiting = intel_engine_has_waiter(engine); 1196 ee->instpm = I915_READ(RING_INSTPM(engine->mmio_base)); 1197 ee->acthd = intel_engine_get_active_head(engine); 1198 ee->seqno = intel_engine_get_seqno(engine); 1199 ee->last_seqno = intel_engine_last_submit(engine); 1200 ee->start = I915_READ_START(engine); 1201 ee->head = I915_READ_HEAD(engine); 1202 ee->tail = I915_READ_TAIL(engine); 1203 ee->ctl = I915_READ_CTL(engine); 1204 if (INTEL_GEN(dev_priv) > 2) 1205 ee->mode = I915_READ_MODE(engine); 1206 1207 if (!HWS_NEEDS_PHYSICAL(dev_priv)) { 1208 i915_reg_t mmio; 1209 1210 if (IS_GEN7(dev_priv)) { 1211 switch (engine->id) { 1212 default: 1213 case RCS: 1214 mmio = RENDER_HWS_PGA_GEN7; 1215 break; 1216 case BCS: 1217 mmio = BLT_HWS_PGA_GEN7; 1218 break; 1219 case VCS: 1220 mmio = BSD_HWS_PGA_GEN7; 1221 break; 1222 case VECS: 1223 mmio = VEBOX_HWS_PGA_GEN7; 1224 break; 1225 } 1226 } else if (IS_GEN6(engine->i915)) { 1227 mmio = RING_HWS_PGA_GEN6(engine->mmio_base); 1228 } else { 1229 /* XXX: gen8 returns to sanity */ 1230 mmio = RING_HWS_PGA(engine->mmio_base); 1231 } 1232 1233 ee->hws = I915_READ(mmio); 1234 } 1235 1236 ee->hangcheck_timestamp = engine->hangcheck.action_timestamp; 1237 ee->hangcheck_action = engine->hangcheck.action; 1238 ee->hangcheck_stalled = engine->hangcheck.stalled; 1239 1240 if (USES_PPGTT(dev_priv)) { 1241 int i; 1242 1243 ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine)); 1244 1245 if (IS_GEN6(dev_priv)) 1246 ee->vm_info.pp_dir_base = 1247 I915_READ(RING_PP_DIR_BASE_READ(engine)); 1248 else if (IS_GEN7(dev_priv)) 1249 ee->vm_info.pp_dir_base = 1250 I915_READ(RING_PP_DIR_BASE(engine)); 1251 else if (INTEL_GEN(dev_priv) >= 8) 1252 for (i = 0; i < 4; i++) { 1253 ee->vm_info.pdp[i] = 1254 I915_READ(GEN8_RING_PDP_UDW(engine, i)); 1255 ee->vm_info.pdp[i] <<= 32; 1256 ee->vm_info.pdp[i] |= 1257 I915_READ(GEN8_RING_PDP_LDW(engine, i)); 1258 } 1259 } 1260 } 1261 1262 static void record_request(struct drm_i915_gem_request *request, 1263 struct drm_i915_error_request *erq) 1264 { 1265 erq->context = request->ctx->hw_id; 1266 erq->ban_score = request->ctx->ban_score; 1267 erq->seqno = request->global_seqno; 1268 erq->jiffies = request->emitted_jiffies; 1269 erq->head = request->head; 1270 erq->tail = request->tail; 1271 1272 rcu_read_lock(); 1273 erq->pid = request->ctx->pid ? pid_nr(request->ctx->pid) : 0; 1274 rcu_read_unlock(); 1275 } 1276 1277 static void engine_record_requests(struct intel_engine_cs *engine, 1278 struct drm_i915_gem_request *first, 1279 struct drm_i915_error_engine *ee) 1280 { 1281 struct drm_i915_gem_request *request; 1282 int count; 1283 1284 count = 0; 1285 request = first; 1286 list_for_each_entry_from(request, &engine->timeline->requests, link) 1287 count++; 1288 if (!count) 1289 return; 1290 1291 ee->requests = kcalloc(count, sizeof(*ee->requests), GFP_ATOMIC); 1292 if (!ee->requests) 1293 return; 1294 1295 ee->num_requests = count; 1296 1297 count = 0; 1298 request = first; 1299 list_for_each_entry_from(request, &engine->timeline->requests, link) { 1300 if (count >= ee->num_requests) { 1301 /* 1302 * If the ring request list was changed in 1303 * between the point where the error request 1304 * list was created and dimensioned and this 1305 * point then just exit early to avoid crashes. 1306 * 1307 * We don't need to communicate that the 1308 * request list changed state during error 1309 * state capture and that the error state is 1310 * slightly incorrect as a consequence since we 1311 * are typically only interested in the request 1312 * list state at the point of error state 1313 * capture, not in any changes happening during 1314 * the capture. 1315 */ 1316 break; 1317 } 1318 1319 record_request(request, &ee->requests[count++]); 1320 } 1321 ee->num_requests = count; 1322 } 1323 1324 static void error_record_engine_execlists(struct intel_engine_cs *engine, 1325 struct drm_i915_error_engine *ee) 1326 { 1327 const struct execlist_port *port = engine->execlist_port; 1328 unsigned int n; 1329 1330 for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++) { 1331 struct drm_i915_gem_request *rq = port_request(&port[n]); 1332 1333 if (!rq) 1334 break; 1335 1336 record_request(rq, &ee->execlist[n]); 1337 } 1338 } 1339 1340 static void record_context(struct drm_i915_error_context *e, 1341 struct i915_gem_context *ctx) 1342 { 1343 if (ctx->pid) { 1344 struct task_struct *task; 1345 1346 rcu_read_lock(); 1347 task = pid_task(ctx->pid, PIDTYPE_PID); 1348 if (task) { 1349 strcpy(e->comm, task->comm); 1350 e->pid = task->pid; 1351 } 1352 rcu_read_unlock(); 1353 } 1354 1355 e->handle = ctx->user_handle; 1356 e->hw_id = ctx->hw_id; 1357 e->ban_score = ctx->ban_score; 1358 e->guilty = ctx->guilty_count; 1359 e->active = ctx->active_count; 1360 } 1361 1362 static void request_record_user_bo(struct drm_i915_gem_request *request, 1363 struct drm_i915_error_engine *ee) 1364 { 1365 struct i915_gem_capture_list *c; 1366 struct drm_i915_error_object **bo; 1367 long count; 1368 1369 count = 0; 1370 for (c = request->capture_list; c; c = c->next) 1371 count++; 1372 1373 bo = NULL; 1374 if (count) 1375 bo = kcalloc(count, sizeof(*bo), GFP_ATOMIC); 1376 if (!bo) 1377 return; 1378 1379 count = 0; 1380 for (c = request->capture_list; c; c = c->next) { 1381 bo[count] = i915_error_object_create(request->i915, c->vma); 1382 if (!bo[count]) 1383 break; 1384 count++; 1385 } 1386 1387 ee->user_bo = bo; 1388 ee->user_bo_count = count; 1389 } 1390 1391 static void i915_gem_record_rings(struct drm_i915_private *dev_priv, 1392 struct i915_gpu_state *error) 1393 { 1394 struct i915_ggtt *ggtt = &dev_priv->ggtt; 1395 int i; 1396 1397 error->semaphore = 1398 i915_error_object_create(dev_priv, dev_priv->semaphore); 1399 1400 for (i = 0; i < I915_NUM_ENGINES; i++) { 1401 struct intel_engine_cs *engine = dev_priv->engine[i]; 1402 struct drm_i915_error_engine *ee = &error->engine[i]; 1403 struct drm_i915_gem_request *request; 1404 1405 ee->engine_id = -1; 1406 1407 if (!engine) 1408 continue; 1409 1410 ee->engine_id = i; 1411 1412 error_record_engine_registers(error, engine, ee); 1413 error_record_engine_waiters(engine, ee); 1414 error_record_engine_execlists(engine, ee); 1415 1416 request = i915_gem_find_active_request(engine); 1417 if (request) { 1418 struct intel_ring *ring; 1419 1420 ee->vm = request->ctx->ppgtt ? 1421 &request->ctx->ppgtt->base : &ggtt->base; 1422 1423 record_context(&ee->context, request->ctx); 1424 1425 /* We need to copy these to an anonymous buffer 1426 * as the simplest method to avoid being overwritten 1427 * by userspace. 1428 */ 1429 ee->batchbuffer = 1430 i915_error_object_create(dev_priv, 1431 request->batch); 1432 1433 if (HAS_BROKEN_CS_TLB(dev_priv)) 1434 ee->wa_batchbuffer = 1435 i915_error_object_create(dev_priv, 1436 engine->scratch); 1437 request_record_user_bo(request, ee); 1438 1439 ee->ctx = 1440 i915_error_object_create(dev_priv, 1441 request->ctx->engine[i].state); 1442 1443 error->simulated |= 1444 i915_gem_context_no_error_capture(request->ctx); 1445 1446 ee->rq_head = request->head; 1447 ee->rq_post = request->postfix; 1448 ee->rq_tail = request->tail; 1449 1450 ring = request->ring; 1451 ee->cpu_ring_head = ring->head; 1452 ee->cpu_ring_tail = ring->tail; 1453 ee->ringbuffer = 1454 i915_error_object_create(dev_priv, ring->vma); 1455 1456 engine_record_requests(engine, request, ee); 1457 } 1458 1459 ee->hws_page = 1460 i915_error_object_create(dev_priv, 1461 engine->status_page.vma); 1462 1463 ee->wa_ctx = 1464 i915_error_object_create(dev_priv, engine->wa_ctx.vma); 1465 } 1466 } 1467 1468 static void i915_gem_capture_vm(struct drm_i915_private *dev_priv, 1469 struct i915_gpu_state *error, 1470 struct i915_address_space *vm, 1471 int idx) 1472 { 1473 struct drm_i915_error_buffer *active_bo; 1474 struct i915_vma *vma; 1475 int count; 1476 1477 count = 0; 1478 list_for_each_entry(vma, &vm->active_list, vm_link) 1479 count++; 1480 1481 active_bo = NULL; 1482 if (count) 1483 active_bo = kcalloc(count, sizeof(*active_bo), GFP_ATOMIC); 1484 if (active_bo) 1485 count = capture_error_bo(active_bo, count, &vm->active_list, false); 1486 else 1487 count = 0; 1488 1489 error->active_vm[idx] = vm; 1490 error->active_bo[idx] = active_bo; 1491 error->active_bo_count[idx] = count; 1492 } 1493 1494 static void i915_capture_active_buffers(struct drm_i915_private *dev_priv, 1495 struct i915_gpu_state *error) 1496 { 1497 int cnt = 0, i, j; 1498 1499 BUILD_BUG_ON(ARRAY_SIZE(error->engine) > ARRAY_SIZE(error->active_bo)); 1500 BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_vm)); 1501 BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_bo_count)); 1502 1503 /* Scan each engine looking for unique active contexts/vm */ 1504 for (i = 0; i < ARRAY_SIZE(error->engine); i++) { 1505 struct drm_i915_error_engine *ee = &error->engine[i]; 1506 bool found; 1507 1508 if (!ee->vm) 1509 continue; 1510 1511 found = false; 1512 for (j = 0; j < i && !found; j++) 1513 found = error->engine[j].vm == ee->vm; 1514 if (!found) 1515 i915_gem_capture_vm(dev_priv, error, ee->vm, cnt++); 1516 } 1517 } 1518 1519 static void i915_capture_pinned_buffers(struct drm_i915_private *dev_priv, 1520 struct i915_gpu_state *error) 1521 { 1522 struct i915_address_space *vm = &dev_priv->ggtt.base; 1523 struct drm_i915_error_buffer *bo; 1524 struct i915_vma *vma; 1525 int count_inactive, count_active; 1526 1527 count_inactive = 0; 1528 list_for_each_entry(vma, &vm->active_list, vm_link) 1529 count_inactive++; 1530 1531 count_active = 0; 1532 list_for_each_entry(vma, &vm->inactive_list, vm_link) 1533 count_active++; 1534 1535 bo = NULL; 1536 if (count_inactive + count_active) 1537 bo = kcalloc(count_inactive + count_active, 1538 sizeof(*bo), GFP_ATOMIC); 1539 if (!bo) 1540 return; 1541 1542 count_inactive = capture_error_bo(bo, count_inactive, 1543 &vm->active_list, true); 1544 count_active = capture_error_bo(bo + count_inactive, count_active, 1545 &vm->inactive_list, true); 1546 error->pinned_bo_count = count_inactive + count_active; 1547 error->pinned_bo = bo; 1548 } 1549 1550 static void i915_gem_capture_guc_log_buffer(struct drm_i915_private *dev_priv, 1551 struct i915_gpu_state *error) 1552 { 1553 /* Capturing log buf contents won't be useful if logging was disabled */ 1554 if (!dev_priv->guc.log.vma || (i915.guc_log_level < 0)) 1555 return; 1556 1557 error->guc_log = i915_error_object_create(dev_priv, 1558 dev_priv->guc.log.vma); 1559 } 1560 1561 /* Capture all registers which don't fit into another category. */ 1562 static void i915_capture_reg_state(struct drm_i915_private *dev_priv, 1563 struct i915_gpu_state *error) 1564 { 1565 int i; 1566 1567 /* General organization 1568 * 1. Registers specific to a single generation 1569 * 2. Registers which belong to multiple generations 1570 * 3. Feature specific registers. 1571 * 4. Everything else 1572 * Please try to follow the order. 1573 */ 1574 1575 /* 1: Registers specific to a single generation */ 1576 if (IS_VALLEYVIEW(dev_priv)) { 1577 error->gtier[0] = I915_READ(GTIER); 1578 error->ier = I915_READ(VLV_IER); 1579 error->forcewake = I915_READ_FW(FORCEWAKE_VLV); 1580 } 1581 1582 if (IS_GEN7(dev_priv)) 1583 error->err_int = I915_READ(GEN7_ERR_INT); 1584 1585 if (INTEL_GEN(dev_priv) >= 8) { 1586 error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0); 1587 error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1); 1588 } 1589 1590 if (IS_GEN6(dev_priv)) { 1591 error->forcewake = I915_READ_FW(FORCEWAKE); 1592 error->gab_ctl = I915_READ(GAB_CTL); 1593 error->gfx_mode = I915_READ(GFX_MODE); 1594 } 1595 1596 /* 2: Registers which belong to multiple generations */ 1597 if (INTEL_GEN(dev_priv) >= 7) 1598 error->forcewake = I915_READ_FW(FORCEWAKE_MT); 1599 1600 if (INTEL_GEN(dev_priv) >= 6) { 1601 error->derrmr = I915_READ(DERRMR); 1602 error->error = I915_READ(ERROR_GEN6); 1603 error->done_reg = I915_READ(DONE_REG); 1604 } 1605 1606 if (INTEL_GEN(dev_priv) >= 5) 1607 error->ccid = I915_READ(CCID); 1608 1609 /* 3: Feature specific registers */ 1610 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { 1611 error->gam_ecochk = I915_READ(GAM_ECOCHK); 1612 error->gac_eco = I915_READ(GAC_ECO_BITS); 1613 } 1614 1615 /* 4: Everything else */ 1616 if (INTEL_GEN(dev_priv) >= 8) { 1617 error->ier = I915_READ(GEN8_DE_MISC_IER); 1618 for (i = 0; i < 4; i++) 1619 error->gtier[i] = I915_READ(GEN8_GT_IER(i)); 1620 error->ngtier = 4; 1621 } else if (HAS_PCH_SPLIT(dev_priv)) { 1622 error->ier = I915_READ(DEIER); 1623 error->gtier[0] = I915_READ(GTIER); 1624 error->ngtier = 1; 1625 } else if (IS_GEN2(dev_priv)) { 1626 error->ier = I915_READ16(IER); 1627 } else if (!IS_VALLEYVIEW(dev_priv)) { 1628 error->ier = I915_READ(IER); 1629 } 1630 error->eir = I915_READ(EIR); 1631 error->pgtbl_er = I915_READ(PGTBL_ER); 1632 } 1633 1634 static void i915_error_capture_msg(struct drm_i915_private *dev_priv, 1635 struct i915_gpu_state *error, 1636 u32 engine_mask, 1637 const char *error_msg) 1638 { 1639 u32 ecode; 1640 int engine_id = -1, len; 1641 1642 ecode = i915_error_generate_code(dev_priv, error, &engine_id); 1643 1644 len = scnprintf(error->error_msg, sizeof(error->error_msg), 1645 "GPU HANG: ecode %d:%d:0x%08x", 1646 INTEL_GEN(dev_priv), engine_id, ecode); 1647 1648 if (engine_id != -1 && error->engine[engine_id].context.pid) 1649 len += scnprintf(error->error_msg + len, 1650 sizeof(error->error_msg) - len, 1651 ", in %s [%d]", 1652 error->engine[engine_id].context.comm, 1653 error->engine[engine_id].context.pid); 1654 1655 scnprintf(error->error_msg + len, sizeof(error->error_msg) - len, 1656 ", reason: %s, action: %s", 1657 error_msg, 1658 engine_mask ? "reset" : "continue"); 1659 } 1660 1661 static void i915_capture_gen_state(struct drm_i915_private *dev_priv, 1662 struct i915_gpu_state *error) 1663 { 1664 error->awake = dev_priv->gt.awake; 1665 error->wakelock = atomic_read(&dev_priv->pm.wakeref_count); 1666 error->suspended = dev_priv->pm.suspended; 1667 1668 error->iommu = -1; 1669 #ifdef CONFIG_INTEL_IOMMU 1670 error->iommu = intel_iommu_gfx_mapped; 1671 #endif 1672 error->reset_count = i915_reset_count(&dev_priv->gpu_error); 1673 error->suspend_count = dev_priv->suspend_count; 1674 1675 memcpy(&error->device_info, 1676 INTEL_INFO(dev_priv), 1677 sizeof(error->device_info)); 1678 } 1679 1680 static __always_inline void dup_param(const char *type, void *x) 1681 { 1682 if (!__builtin_strcmp(type, "char *")) 1683 *(void **)x = kstrdup(*(void **)x, GFP_ATOMIC); 1684 } 1685 1686 static int capture(void *data) 1687 { 1688 struct i915_gpu_state *error = data; 1689 1690 do_gettimeofday(&error->time); 1691 error->boottime = ktime_to_timeval(ktime_get_boottime()); 1692 error->uptime = 1693 ktime_to_timeval(ktime_sub(ktime_get(), 1694 error->i915->gt.last_init_time)); 1695 1696 error->params = i915; 1697 #define DUP(T, x) dup_param(#T, &error->params.x); 1698 I915_PARAMS_FOR_EACH(DUP); 1699 #undef DUP 1700 1701 i915_capture_gen_state(error->i915, error); 1702 i915_capture_reg_state(error->i915, error); 1703 i915_gem_record_fences(error->i915, error); 1704 i915_gem_record_rings(error->i915, error); 1705 i915_capture_active_buffers(error->i915, error); 1706 i915_capture_pinned_buffers(error->i915, error); 1707 i915_gem_capture_guc_log_buffer(error->i915, error); 1708 1709 error->overlay = intel_overlay_capture_error_state(error->i915); 1710 error->display = intel_display_capture_error_state(error->i915); 1711 1712 return 0; 1713 } 1714 1715 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x)) 1716 1717 struct i915_gpu_state * 1718 i915_capture_gpu_state(struct drm_i915_private *i915) 1719 { 1720 struct i915_gpu_state *error; 1721 1722 error = kzalloc(sizeof(*error), GFP_ATOMIC); 1723 if (!error) 1724 return NULL; 1725 1726 kref_init(&error->ref); 1727 error->i915 = i915; 1728 1729 stop_machine(capture, error, NULL); 1730 1731 return error; 1732 } 1733 1734 /** 1735 * i915_capture_error_state - capture an error record for later analysis 1736 * @dev: drm device 1737 * 1738 * Should be called when an error is detected (either a hang or an error 1739 * interrupt) to capture error state from the time of the error. Fills 1740 * out a structure which becomes available in debugfs for user level tools 1741 * to pick up. 1742 */ 1743 void i915_capture_error_state(struct drm_i915_private *dev_priv, 1744 u32 engine_mask, 1745 const char *error_msg) 1746 { 1747 static bool warned; 1748 struct i915_gpu_state *error; 1749 unsigned long flags; 1750 1751 if (!i915.error_capture) 1752 return; 1753 1754 if (READ_ONCE(dev_priv->gpu_error.first_error)) 1755 return; 1756 1757 error = i915_capture_gpu_state(dev_priv); 1758 if (!error) { 1759 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); 1760 return; 1761 } 1762 1763 i915_error_capture_msg(dev_priv, error, engine_mask, error_msg); 1764 DRM_INFO("%s\n", error->error_msg); 1765 1766 if (!error->simulated) { 1767 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); 1768 if (!dev_priv->gpu_error.first_error) { 1769 dev_priv->gpu_error.first_error = error; 1770 error = NULL; 1771 } 1772 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); 1773 } 1774 1775 if (error) { 1776 __i915_gpu_state_free(&error->ref); 1777 return; 1778 } 1779 1780 if (!warned && 1781 ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) { 1782 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n"); 1783 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n"); 1784 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n"); 1785 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n"); 1786 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", 1787 dev_priv->drm.primary->index); 1788 warned = true; 1789 } 1790 } 1791 1792 struct i915_gpu_state * 1793 i915_first_error_state(struct drm_i915_private *i915) 1794 { 1795 struct i915_gpu_state *error; 1796 1797 spin_lock_irq(&i915->gpu_error.lock); 1798 error = i915->gpu_error.first_error; 1799 if (error) 1800 i915_gpu_state_get(error); 1801 spin_unlock_irq(&i915->gpu_error.lock); 1802 1803 return error; 1804 } 1805 1806 void i915_reset_error_state(struct drm_i915_private *i915) 1807 { 1808 struct i915_gpu_state *error; 1809 1810 spin_lock_irq(&i915->gpu_error.lock); 1811 error = i915->gpu_error.first_error; 1812 i915->gpu_error.first_error = NULL; 1813 spin_unlock_irq(&i915->gpu_error.lock); 1814 1815 i915_gpu_state_put(error); 1816 } 1817