1 /* 2 * Copyright (c) 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * Mika Kuoppala <mika.kuoppala@intel.com> 27 * 28 */ 29 30 #include <generated/utsrelease.h> 31 #include "i915_drv.h" 32 33 static const char *yesno(int v) 34 { 35 return v ? "yes" : "no"; 36 } 37 38 static const char *ring_str(int ring) 39 { 40 switch (ring) { 41 case RCS: return "render"; 42 case VCS: return "bsd"; 43 case BCS: return "blt"; 44 case VECS: return "vebox"; 45 default: return ""; 46 } 47 } 48 49 static const char *pin_flag(int pinned) 50 { 51 if (pinned > 0) 52 return " P"; 53 else if (pinned < 0) 54 return " p"; 55 else 56 return ""; 57 } 58 59 static const char *tiling_flag(int tiling) 60 { 61 switch (tiling) { 62 default: 63 case I915_TILING_NONE: return ""; 64 case I915_TILING_X: return " X"; 65 case I915_TILING_Y: return " Y"; 66 } 67 } 68 69 static const char *dirty_flag(int dirty) 70 { 71 return dirty ? " dirty" : ""; 72 } 73 74 static const char *purgeable_flag(int purgeable) 75 { 76 return purgeable ? " purgeable" : ""; 77 } 78 79 static bool __i915_error_ok(struct drm_i915_error_state_buf *e) 80 { 81 82 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) { 83 e->err = -ENOSPC; 84 return false; 85 } 86 87 if (e->bytes == e->size - 1 || e->err) 88 return false; 89 90 return true; 91 } 92 93 static bool __i915_error_seek(struct drm_i915_error_state_buf *e, 94 unsigned len) 95 { 96 if (e->pos + len <= e->start) { 97 e->pos += len; 98 return false; 99 } 100 101 /* First vsnprintf needs to fit in its entirety for memmove */ 102 if (len >= e->size) { 103 e->err = -EIO; 104 return false; 105 } 106 107 return true; 108 } 109 110 static void __i915_error_advance(struct drm_i915_error_state_buf *e, 111 unsigned len) 112 { 113 /* If this is first printf in this window, adjust it so that 114 * start position matches start of the buffer 115 */ 116 117 if (e->pos < e->start) { 118 const size_t off = e->start - e->pos; 119 120 /* Should not happen but be paranoid */ 121 if (off > len || e->bytes) { 122 e->err = -EIO; 123 return; 124 } 125 126 memmove(e->buf, e->buf + off, len - off); 127 e->bytes = len - off; 128 e->pos = e->start; 129 return; 130 } 131 132 e->bytes += len; 133 e->pos += len; 134 } 135 136 static void i915_error_vprintf(struct drm_i915_error_state_buf *e, 137 const char *f, va_list args) 138 { 139 unsigned len; 140 141 if (!__i915_error_ok(e)) 142 return; 143 144 /* Seek the first printf which is hits start position */ 145 if (e->pos < e->start) { 146 va_list tmp; 147 148 va_copy(tmp, args); 149 len = vsnprintf(NULL, 0, f, tmp); 150 va_end(tmp); 151 152 if (!__i915_error_seek(e, len)) 153 return; 154 } 155 156 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args); 157 if (len >= e->size - e->bytes) 158 len = e->size - e->bytes - 1; 159 160 __i915_error_advance(e, len); 161 } 162 163 static void i915_error_puts(struct drm_i915_error_state_buf *e, 164 const char *str) 165 { 166 unsigned len; 167 168 if (!__i915_error_ok(e)) 169 return; 170 171 len = strlen(str); 172 173 /* Seek the first printf which is hits start position */ 174 if (e->pos < e->start) { 175 if (!__i915_error_seek(e, len)) 176 return; 177 } 178 179 if (len >= e->size - e->bytes) 180 len = e->size - e->bytes - 1; 181 memcpy(e->buf + e->bytes, str, len); 182 183 __i915_error_advance(e, len); 184 } 185 186 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) 187 #define err_puts(e, s) i915_error_puts(e, s) 188 189 static void print_error_buffers(struct drm_i915_error_state_buf *m, 190 const char *name, 191 struct drm_i915_error_buffer *err, 192 int count) 193 { 194 err_printf(m, "%s [%d]:\n", name, count); 195 196 while (count--) { 197 err_printf(m, " %08x %8u %02x %02x %x %x", 198 err->gtt_offset, 199 err->size, 200 err->read_domains, 201 err->write_domain, 202 err->rseqno, err->wseqno); 203 err_puts(m, pin_flag(err->pinned)); 204 err_puts(m, tiling_flag(err->tiling)); 205 err_puts(m, dirty_flag(err->dirty)); 206 err_puts(m, purgeable_flag(err->purgeable)); 207 err_puts(m, err->ring != -1 ? " " : ""); 208 err_puts(m, ring_str(err->ring)); 209 err_puts(m, i915_cache_level_str(err->cache_level)); 210 211 if (err->name) 212 err_printf(m, " (name: %d)", err->name); 213 if (err->fence_reg != I915_FENCE_REG_NONE) 214 err_printf(m, " (fence: %d)", err->fence_reg); 215 216 err_puts(m, "\n"); 217 err++; 218 } 219 } 220 221 static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a) 222 { 223 switch (a) { 224 case HANGCHECK_IDLE: 225 return "idle"; 226 case HANGCHECK_WAIT: 227 return "wait"; 228 case HANGCHECK_ACTIVE: 229 return "active"; 230 case HANGCHECK_KICK: 231 return "kick"; 232 case HANGCHECK_HUNG: 233 return "hung"; 234 } 235 236 return "unknown"; 237 } 238 239 static void i915_ring_error_state(struct drm_i915_error_state_buf *m, 240 struct drm_device *dev, 241 struct drm_i915_error_ring *ring) 242 { 243 if (!ring->valid) 244 return; 245 246 err_printf(m, " HEAD: 0x%08x\n", ring->head); 247 err_printf(m, " TAIL: 0x%08x\n", ring->tail); 248 err_printf(m, " CTL: 0x%08x\n", ring->ctl); 249 err_printf(m, " HWS: 0x%08x\n", ring->hws); 250 err_printf(m, " ACTHD: 0x%08x %08x\n", (u32)(ring->acthd>>32), (u32)ring->acthd); 251 err_printf(m, " IPEIR: 0x%08x\n", ring->ipeir); 252 err_printf(m, " IPEHR: 0x%08x\n", ring->ipehr); 253 err_printf(m, " INSTDONE: 0x%08x\n", ring->instdone); 254 if (INTEL_INFO(dev)->gen >= 4) { 255 err_printf(m, " BBADDR: 0x%08x %08x\n", (u32)(ring->bbaddr>>32), (u32)ring->bbaddr); 256 err_printf(m, " BB_STATE: 0x%08x\n", ring->bbstate); 257 err_printf(m, " INSTPS: 0x%08x\n", ring->instps); 258 } 259 err_printf(m, " INSTPM: 0x%08x\n", ring->instpm); 260 err_printf(m, " FADDR: 0x%08x\n", ring->faddr); 261 if (INTEL_INFO(dev)->gen >= 6) { 262 err_printf(m, " RC PSMI: 0x%08x\n", ring->rc_psmi); 263 err_printf(m, " FAULT_REG: 0x%08x\n", ring->fault_reg); 264 err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n", 265 ring->semaphore_mboxes[0], 266 ring->semaphore_seqno[0]); 267 err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n", 268 ring->semaphore_mboxes[1], 269 ring->semaphore_seqno[1]); 270 if (HAS_VEBOX(dev)) { 271 err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n", 272 ring->semaphore_mboxes[2], 273 ring->semaphore_seqno[2]); 274 } 275 } 276 if (USES_PPGTT(dev)) { 277 err_printf(m, " GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode); 278 279 if (INTEL_INFO(dev)->gen >= 8) { 280 int i; 281 for (i = 0; i < 4; i++) 282 err_printf(m, " PDP%d: 0x%016llx\n", 283 i, ring->vm_info.pdp[i]); 284 } else { 285 err_printf(m, " PP_DIR_BASE: 0x%08x\n", 286 ring->vm_info.pp_dir_base); 287 } 288 } 289 err_printf(m, " seqno: 0x%08x\n", ring->seqno); 290 err_printf(m, " waiting: %s\n", yesno(ring->waiting)); 291 err_printf(m, " ring->head: 0x%08x\n", ring->cpu_ring_head); 292 err_printf(m, " ring->tail: 0x%08x\n", ring->cpu_ring_tail); 293 err_printf(m, " hangcheck: %s [%d]\n", 294 hangcheck_action_to_str(ring->hangcheck_action), 295 ring->hangcheck_score); 296 } 297 298 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) 299 { 300 va_list args; 301 302 va_start(args, f); 303 i915_error_vprintf(e, f, args); 304 va_end(args); 305 } 306 307 static void print_error_obj(struct drm_i915_error_state_buf *m, 308 struct drm_i915_error_object *obj) 309 { 310 int page, offset, elt; 311 312 for (page = offset = 0; page < obj->page_count; page++) { 313 for (elt = 0; elt < PAGE_SIZE/4; elt++) { 314 err_printf(m, "%08x : %08x\n", offset, 315 obj->pages[page][elt]); 316 offset += 4; 317 } 318 } 319 } 320 321 int i915_error_state_to_str(struct drm_i915_error_state_buf *m, 322 const struct i915_error_state_file_priv *error_priv) 323 { 324 struct drm_device *dev = error_priv->dev; 325 struct drm_i915_private *dev_priv = dev->dev_private; 326 struct drm_i915_error_state *error = error_priv->error; 327 int i, j, offset, elt; 328 int max_hangcheck_score; 329 330 if (!error) { 331 err_printf(m, "no error state collected\n"); 332 goto out; 333 } 334 335 err_printf(m, "%s\n", error->error_msg); 336 err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec, 337 error->time.tv_usec); 338 err_printf(m, "Kernel: " UTS_RELEASE "\n"); 339 max_hangcheck_score = 0; 340 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 341 if (error->ring[i].hangcheck_score > max_hangcheck_score) 342 max_hangcheck_score = error->ring[i].hangcheck_score; 343 } 344 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 345 if (error->ring[i].hangcheck_score == max_hangcheck_score && 346 error->ring[i].pid != -1) { 347 err_printf(m, "Active process (on ring %s): %s [%d]\n", 348 ring_str(i), 349 error->ring[i].comm, 350 error->ring[i].pid); 351 } 352 } 353 err_printf(m, "Reset count: %u\n", error->reset_count); 354 err_printf(m, "Suspend count: %u\n", error->suspend_count); 355 err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device); 356 err_printf(m, "EIR: 0x%08x\n", error->eir); 357 err_printf(m, "IER: 0x%08x\n", error->ier); 358 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er); 359 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake); 360 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr); 361 err_printf(m, "CCID: 0x%08x\n", error->ccid); 362 err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings); 363 364 for (i = 0; i < dev_priv->num_fence_regs; i++) 365 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]); 366 367 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++) 368 err_printf(m, " INSTDONE_%d: 0x%08x\n", i, 369 error->extra_instdone[i]); 370 371 if (INTEL_INFO(dev)->gen >= 6) { 372 err_printf(m, "ERROR: 0x%08x\n", error->error); 373 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); 374 } 375 376 if (INTEL_INFO(dev)->gen == 7) 377 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int); 378 379 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 380 err_printf(m, "%s command stream:\n", ring_str(i)); 381 i915_ring_error_state(m, dev, &error->ring[i]); 382 } 383 384 if (error->active_bo) 385 print_error_buffers(m, "Active", 386 error->active_bo[0], 387 error->active_bo_count[0]); 388 389 if (error->pinned_bo) 390 print_error_buffers(m, "Pinned", 391 error->pinned_bo[0], 392 error->pinned_bo_count[0]); 393 394 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 395 struct drm_i915_error_object *obj; 396 397 obj = error->ring[i].batchbuffer; 398 if (obj) { 399 err_puts(m, dev_priv->ring[i].name); 400 if (error->ring[i].pid != -1) 401 err_printf(m, " (submitted by %s [%d])", 402 error->ring[i].comm, 403 error->ring[i].pid); 404 err_printf(m, " --- gtt_offset = 0x%08x\n", 405 obj->gtt_offset); 406 print_error_obj(m, obj); 407 } 408 409 obj = error->ring[i].wa_batchbuffer; 410 if (obj) { 411 err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n", 412 dev_priv->ring[i].name, obj->gtt_offset); 413 print_error_obj(m, obj); 414 } 415 416 if (error->ring[i].num_requests) { 417 err_printf(m, "%s --- %d requests\n", 418 dev_priv->ring[i].name, 419 error->ring[i].num_requests); 420 for (j = 0; j < error->ring[i].num_requests; j++) { 421 err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n", 422 error->ring[i].requests[j].seqno, 423 error->ring[i].requests[j].jiffies, 424 error->ring[i].requests[j].tail); 425 } 426 } 427 428 if ((obj = error->ring[i].ringbuffer)) { 429 err_printf(m, "%s --- ringbuffer = 0x%08x\n", 430 dev_priv->ring[i].name, 431 obj->gtt_offset); 432 print_error_obj(m, obj); 433 } 434 435 if ((obj = error->ring[i].hws_page)) { 436 err_printf(m, "%s --- HW Status = 0x%08x\n", 437 dev_priv->ring[i].name, 438 obj->gtt_offset); 439 offset = 0; 440 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) { 441 err_printf(m, "[%04x] %08x %08x %08x %08x\n", 442 offset, 443 obj->pages[0][elt], 444 obj->pages[0][elt+1], 445 obj->pages[0][elt+2], 446 obj->pages[0][elt+3]); 447 offset += 16; 448 } 449 } 450 451 if ((obj = error->ring[i].ctx)) { 452 err_printf(m, "%s --- HW Context = 0x%08x\n", 453 dev_priv->ring[i].name, 454 obj->gtt_offset); 455 offset = 0; 456 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) { 457 err_printf(m, "[%04x] %08x %08x %08x %08x\n", 458 offset, 459 obj->pages[0][elt], 460 obj->pages[0][elt+1], 461 obj->pages[0][elt+2], 462 obj->pages[0][elt+3]); 463 offset += 16; 464 } 465 } 466 } 467 468 if (error->overlay) 469 intel_overlay_print_error_state(m, error->overlay); 470 471 if (error->display) 472 intel_display_print_error_state(m, dev, error->display); 473 474 out: 475 if (m->bytes == 0 && m->err) 476 return m->err; 477 478 return 0; 479 } 480 481 int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf, 482 size_t count, loff_t pos) 483 { 484 memset(ebuf, 0, sizeof(*ebuf)); 485 486 /* We need to have enough room to store any i915_error_state printf 487 * so that we can move it to start position. 488 */ 489 ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE; 490 ebuf->buf = kmalloc(ebuf->size, 491 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN); 492 493 if (ebuf->buf == NULL) { 494 ebuf->size = PAGE_SIZE; 495 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY); 496 } 497 498 if (ebuf->buf == NULL) { 499 ebuf->size = 128; 500 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY); 501 } 502 503 if (ebuf->buf == NULL) 504 return -ENOMEM; 505 506 ebuf->start = pos; 507 508 return 0; 509 } 510 511 static void i915_error_object_free(struct drm_i915_error_object *obj) 512 { 513 int page; 514 515 if (obj == NULL) 516 return; 517 518 for (page = 0; page < obj->page_count; page++) 519 kfree(obj->pages[page]); 520 521 kfree(obj); 522 } 523 524 static void i915_error_state_free(struct kref *error_ref) 525 { 526 struct drm_i915_error_state *error = container_of(error_ref, 527 typeof(*error), ref); 528 int i; 529 530 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 531 i915_error_object_free(error->ring[i].batchbuffer); 532 i915_error_object_free(error->ring[i].ringbuffer); 533 i915_error_object_free(error->ring[i].hws_page); 534 i915_error_object_free(error->ring[i].ctx); 535 kfree(error->ring[i].requests); 536 } 537 538 kfree(error->active_bo); 539 kfree(error->overlay); 540 kfree(error->display); 541 kfree(error); 542 } 543 544 static struct drm_i915_error_object * 545 i915_error_object_create_sized(struct drm_i915_private *dev_priv, 546 struct drm_i915_gem_object *src, 547 struct i915_address_space *vm, 548 const int num_pages) 549 { 550 struct drm_i915_error_object *dst; 551 int i; 552 u32 reloc_offset; 553 554 if (src == NULL || src->pages == NULL) 555 return NULL; 556 557 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC); 558 if (dst == NULL) 559 return NULL; 560 561 reloc_offset = dst->gtt_offset = i915_gem_obj_offset(src, vm); 562 for (i = 0; i < num_pages; i++) { 563 unsigned long flags; 564 void *d; 565 566 d = kmalloc(PAGE_SIZE, GFP_ATOMIC); 567 if (d == NULL) 568 goto unwind; 569 570 local_irq_save(flags); 571 if (src->cache_level == I915_CACHE_NONE && 572 reloc_offset < dev_priv->gtt.mappable_end && 573 src->has_global_gtt_mapping && 574 i915_is_ggtt(vm)) { 575 void __iomem *s; 576 577 /* Simply ignore tiling or any overlapping fence. 578 * It's part of the error state, and this hopefully 579 * captures what the GPU read. 580 */ 581 582 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable, 583 reloc_offset); 584 memcpy_fromio(d, s, PAGE_SIZE); 585 io_mapping_unmap_atomic(s); 586 } else if (src->stolen) { 587 unsigned long offset; 588 589 offset = dev_priv->mm.stolen_base; 590 offset += src->stolen->start; 591 offset += i << PAGE_SHIFT; 592 593 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE); 594 } else { 595 struct page *page; 596 void *s; 597 598 page = i915_gem_object_get_page(src, i); 599 600 drm_clflush_pages(&page, 1); 601 602 s = kmap_atomic(page); 603 memcpy(d, s, PAGE_SIZE); 604 kunmap_atomic(s); 605 606 drm_clflush_pages(&page, 1); 607 } 608 local_irq_restore(flags); 609 610 dst->pages[i] = d; 611 612 reloc_offset += PAGE_SIZE; 613 } 614 dst->page_count = num_pages; 615 616 return dst; 617 618 unwind: 619 while (i--) 620 kfree(dst->pages[i]); 621 kfree(dst); 622 return NULL; 623 } 624 #define i915_error_object_create(dev_priv, src, vm) \ 625 i915_error_object_create_sized((dev_priv), (src), (vm), \ 626 (src)->base.size>>PAGE_SHIFT) 627 628 #define i915_error_ggtt_object_create(dev_priv, src) \ 629 i915_error_object_create_sized((dev_priv), (src), &(dev_priv)->gtt.base, \ 630 (src)->base.size>>PAGE_SHIFT) 631 632 static void capture_bo(struct drm_i915_error_buffer *err, 633 struct drm_i915_gem_object *obj) 634 { 635 err->size = obj->base.size; 636 err->name = obj->base.name; 637 err->rseqno = obj->last_read_seqno; 638 err->wseqno = obj->last_write_seqno; 639 err->gtt_offset = i915_gem_obj_ggtt_offset(obj); 640 err->read_domains = obj->base.read_domains; 641 err->write_domain = obj->base.write_domain; 642 err->fence_reg = obj->fence_reg; 643 err->pinned = 0; 644 if (i915_gem_obj_is_pinned(obj)) 645 err->pinned = 1; 646 if (obj->user_pin_count > 0) 647 err->pinned = -1; 648 err->tiling = obj->tiling_mode; 649 err->dirty = obj->dirty; 650 err->purgeable = obj->madv != I915_MADV_WILLNEED; 651 err->ring = obj->ring ? obj->ring->id : -1; 652 err->cache_level = obj->cache_level; 653 } 654 655 static u32 capture_active_bo(struct drm_i915_error_buffer *err, 656 int count, struct list_head *head) 657 { 658 struct i915_vma *vma; 659 int i = 0; 660 661 list_for_each_entry(vma, head, mm_list) { 662 capture_bo(err++, vma->obj); 663 if (++i == count) 664 break; 665 } 666 667 return i; 668 } 669 670 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err, 671 int count, struct list_head *head) 672 { 673 struct drm_i915_gem_object *obj; 674 int i = 0; 675 676 list_for_each_entry(obj, head, global_list) { 677 if (!i915_gem_obj_is_pinned(obj)) 678 continue; 679 680 capture_bo(err++, obj); 681 if (++i == count) 682 break; 683 } 684 685 return i; 686 } 687 688 /* Generate a semi-unique error code. The code is not meant to have meaning, The 689 * code's only purpose is to try to prevent false duplicated bug reports by 690 * grossly estimating a GPU error state. 691 * 692 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine 693 * the hang if we could strip the GTT offset information from it. 694 * 695 * It's only a small step better than a random number in its current form. 696 */ 697 static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv, 698 struct drm_i915_error_state *error, 699 int *ring_id) 700 { 701 uint32_t error_code = 0; 702 int i; 703 704 /* IPEHR would be an ideal way to detect errors, as it's the gross 705 * measure of "the command that hung." However, has some very common 706 * synchronization commands which almost always appear in the case 707 * strictly a client bug. Use instdone to differentiate those some. 708 */ 709 for (i = 0; i < I915_NUM_RINGS; i++) { 710 if (error->ring[i].hangcheck_action == HANGCHECK_HUNG) { 711 if (ring_id) 712 *ring_id = i; 713 714 return error->ring[i].ipehr ^ error->ring[i].instdone; 715 } 716 } 717 718 return error_code; 719 } 720 721 static void i915_gem_record_fences(struct drm_device *dev, 722 struct drm_i915_error_state *error) 723 { 724 struct drm_i915_private *dev_priv = dev->dev_private; 725 int i; 726 727 /* Fences */ 728 switch (INTEL_INFO(dev)->gen) { 729 case 8: 730 case 7: 731 case 6: 732 for (i = 0; i < dev_priv->num_fence_regs; i++) 733 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8)); 734 break; 735 case 5: 736 case 4: 737 for (i = 0; i < 16; i++) 738 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8)); 739 break; 740 case 3: 741 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) 742 for (i = 0; i < 8; i++) 743 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4)); 744 case 2: 745 for (i = 0; i < 8; i++) 746 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); 747 break; 748 749 default: 750 BUG(); 751 } 752 } 753 754 static void i915_record_ring_state(struct drm_device *dev, 755 struct intel_ring_buffer *ring, 756 struct drm_i915_error_ring *ering) 757 { 758 struct drm_i915_private *dev_priv = dev->dev_private; 759 760 if (INTEL_INFO(dev)->gen >= 6) { 761 ering->rc_psmi = I915_READ(ring->mmio_base + 0x50); 762 ering->fault_reg = I915_READ(RING_FAULT_REG(ring)); 763 ering->semaphore_mboxes[0] 764 = I915_READ(RING_SYNC_0(ring->mmio_base)); 765 ering->semaphore_mboxes[1] 766 = I915_READ(RING_SYNC_1(ring->mmio_base)); 767 ering->semaphore_seqno[0] = ring->sync_seqno[0]; 768 ering->semaphore_seqno[1] = ring->sync_seqno[1]; 769 } 770 771 if (HAS_VEBOX(dev)) { 772 ering->semaphore_mboxes[2] = 773 I915_READ(RING_SYNC_2(ring->mmio_base)); 774 ering->semaphore_seqno[2] = ring->sync_seqno[2]; 775 } 776 777 if (INTEL_INFO(dev)->gen >= 4) { 778 ering->faddr = I915_READ(RING_DMA_FADD(ring->mmio_base)); 779 ering->ipeir = I915_READ(RING_IPEIR(ring->mmio_base)); 780 ering->ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); 781 ering->instdone = I915_READ(RING_INSTDONE(ring->mmio_base)); 782 ering->instps = I915_READ(RING_INSTPS(ring->mmio_base)); 783 ering->bbaddr = I915_READ(RING_BBADDR(ring->mmio_base)); 784 if (INTEL_INFO(dev)->gen >= 8) 785 ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(ring->mmio_base)) << 32; 786 ering->bbstate = I915_READ(RING_BBSTATE(ring->mmio_base)); 787 } else { 788 ering->faddr = I915_READ(DMA_FADD_I8XX); 789 ering->ipeir = I915_READ(IPEIR); 790 ering->ipehr = I915_READ(IPEHR); 791 ering->instdone = I915_READ(INSTDONE); 792 } 793 794 ering->waiting = waitqueue_active(&ring->irq_queue); 795 ering->instpm = I915_READ(RING_INSTPM(ring->mmio_base)); 796 ering->seqno = ring->get_seqno(ring, false); 797 ering->acthd = intel_ring_get_active_head(ring); 798 ering->head = I915_READ_HEAD(ring); 799 ering->tail = I915_READ_TAIL(ring); 800 ering->ctl = I915_READ_CTL(ring); 801 802 if (I915_NEED_GFX_HWS(dev)) { 803 int mmio; 804 805 if (IS_GEN7(dev)) { 806 switch (ring->id) { 807 default: 808 case RCS: 809 mmio = RENDER_HWS_PGA_GEN7; 810 break; 811 case BCS: 812 mmio = BLT_HWS_PGA_GEN7; 813 break; 814 case VCS: 815 mmio = BSD_HWS_PGA_GEN7; 816 break; 817 case VECS: 818 mmio = VEBOX_HWS_PGA_GEN7; 819 break; 820 } 821 } else if (IS_GEN6(ring->dev)) { 822 mmio = RING_HWS_PGA_GEN6(ring->mmio_base); 823 } else { 824 /* XXX: gen8 returns to sanity */ 825 mmio = RING_HWS_PGA(ring->mmio_base); 826 } 827 828 ering->hws = I915_READ(mmio); 829 } 830 831 ering->cpu_ring_head = ring->head; 832 ering->cpu_ring_tail = ring->tail; 833 834 ering->hangcheck_score = ring->hangcheck.score; 835 ering->hangcheck_action = ring->hangcheck.action; 836 837 if (USES_PPGTT(dev)) { 838 int i; 839 840 ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(ring)); 841 842 switch (INTEL_INFO(dev)->gen) { 843 case 8: 844 for (i = 0; i < 4; i++) { 845 ering->vm_info.pdp[i] = 846 I915_READ(GEN8_RING_PDP_UDW(ring, i)); 847 ering->vm_info.pdp[i] <<= 32; 848 ering->vm_info.pdp[i] |= 849 I915_READ(GEN8_RING_PDP_LDW(ring, i)); 850 } 851 break; 852 case 7: 853 ering->vm_info.pp_dir_base = 854 I915_READ(RING_PP_DIR_BASE(ring)); 855 break; 856 case 6: 857 ering->vm_info.pp_dir_base = 858 I915_READ(RING_PP_DIR_BASE_READ(ring)); 859 break; 860 } 861 } 862 } 863 864 865 static void i915_gem_record_active_context(struct intel_ring_buffer *ring, 866 struct drm_i915_error_state *error, 867 struct drm_i915_error_ring *ering) 868 { 869 struct drm_i915_private *dev_priv = ring->dev->dev_private; 870 struct drm_i915_gem_object *obj; 871 872 /* Currently render ring is the only HW context user */ 873 if (ring->id != RCS || !error->ccid) 874 return; 875 876 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { 877 if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) { 878 ering->ctx = i915_error_object_create_sized(dev_priv, 879 obj, 880 &dev_priv->gtt.base, 881 1); 882 break; 883 } 884 } 885 } 886 887 static void i915_gem_record_rings(struct drm_device *dev, 888 struct drm_i915_error_state *error) 889 { 890 struct drm_i915_private *dev_priv = dev->dev_private; 891 struct drm_i915_gem_request *request; 892 int i, count; 893 894 for (i = 0; i < I915_NUM_RINGS; i++) { 895 struct intel_ring_buffer *ring = &dev_priv->ring[i]; 896 897 if (ring->dev == NULL) 898 continue; 899 900 error->ring[i].valid = true; 901 902 i915_record_ring_state(dev, ring, &error->ring[i]); 903 904 error->ring[i].pid = -1; 905 request = i915_gem_find_active_request(ring); 906 if (request) { 907 /* We need to copy these to an anonymous buffer 908 * as the simplest method to avoid being overwritten 909 * by userspace. 910 */ 911 error->ring[i].batchbuffer = 912 i915_error_object_create(dev_priv, 913 request->batch_obj, 914 request->ctx ? 915 request->ctx->vm : 916 &dev_priv->gtt.base); 917 918 if (HAS_BROKEN_CS_TLB(dev_priv->dev) && 919 ring->scratch.obj) 920 error->ring[i].wa_batchbuffer = 921 i915_error_ggtt_object_create(dev_priv, 922 ring->scratch.obj); 923 924 if (request->file_priv) { 925 struct task_struct *task; 926 927 rcu_read_lock(); 928 task = pid_task(request->file_priv->file->pid, 929 PIDTYPE_PID); 930 if (task) { 931 strcpy(error->ring[i].comm, task->comm); 932 error->ring[i].pid = task->pid; 933 } 934 rcu_read_unlock(); 935 } 936 } 937 938 error->ring[i].ringbuffer = 939 i915_error_ggtt_object_create(dev_priv, ring->obj); 940 941 if (ring->status_page.obj) 942 error->ring[i].hws_page = 943 i915_error_ggtt_object_create(dev_priv, ring->status_page.obj); 944 945 i915_gem_record_active_context(ring, error, &error->ring[i]); 946 947 count = 0; 948 list_for_each_entry(request, &ring->request_list, list) 949 count++; 950 951 error->ring[i].num_requests = count; 952 error->ring[i].requests = 953 kcalloc(count, sizeof(*error->ring[i].requests), 954 GFP_ATOMIC); 955 if (error->ring[i].requests == NULL) { 956 error->ring[i].num_requests = 0; 957 continue; 958 } 959 960 count = 0; 961 list_for_each_entry(request, &ring->request_list, list) { 962 struct drm_i915_error_request *erq; 963 964 erq = &error->ring[i].requests[count++]; 965 erq->seqno = request->seqno; 966 erq->jiffies = request->emitted_jiffies; 967 erq->tail = request->tail; 968 } 969 } 970 } 971 972 /* FIXME: Since pin count/bound list is global, we duplicate what we capture per 973 * VM. 974 */ 975 static void i915_gem_capture_vm(struct drm_i915_private *dev_priv, 976 struct drm_i915_error_state *error, 977 struct i915_address_space *vm, 978 const int ndx) 979 { 980 struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL; 981 struct drm_i915_gem_object *obj; 982 struct i915_vma *vma; 983 int i; 984 985 i = 0; 986 list_for_each_entry(vma, &vm->active_list, mm_list) 987 i++; 988 error->active_bo_count[ndx] = i; 989 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) 990 if (i915_gem_obj_is_pinned(obj)) 991 i++; 992 error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx]; 993 994 if (i) { 995 active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC); 996 if (active_bo) 997 pinned_bo = active_bo + error->active_bo_count[ndx]; 998 } 999 1000 if (active_bo) 1001 error->active_bo_count[ndx] = 1002 capture_active_bo(active_bo, 1003 error->active_bo_count[ndx], 1004 &vm->active_list); 1005 1006 if (pinned_bo) 1007 error->pinned_bo_count[ndx] = 1008 capture_pinned_bo(pinned_bo, 1009 error->pinned_bo_count[ndx], 1010 &dev_priv->mm.bound_list); 1011 error->active_bo[ndx] = active_bo; 1012 error->pinned_bo[ndx] = pinned_bo; 1013 } 1014 1015 static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv, 1016 struct drm_i915_error_state *error) 1017 { 1018 struct i915_address_space *vm; 1019 int cnt = 0, i = 0; 1020 1021 list_for_each_entry(vm, &dev_priv->vm_list, global_link) 1022 cnt++; 1023 1024 error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC); 1025 error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC); 1026 error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count), 1027 GFP_ATOMIC); 1028 error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count), 1029 GFP_ATOMIC); 1030 1031 list_for_each_entry(vm, &dev_priv->vm_list, global_link) 1032 i915_gem_capture_vm(dev_priv, error, vm, i++); 1033 } 1034 1035 /* Capture all registers which don't fit into another category. */ 1036 static void i915_capture_reg_state(struct drm_i915_private *dev_priv, 1037 struct drm_i915_error_state *error) 1038 { 1039 struct drm_device *dev = dev_priv->dev; 1040 int pipe; 1041 1042 /* General organization 1043 * 1. Registers specific to a single generation 1044 * 2. Registers which belong to multiple generations 1045 * 3. Feature specific registers. 1046 * 4. Everything else 1047 * Please try to follow the order. 1048 */ 1049 1050 /* 1: Registers specific to a single generation */ 1051 if (IS_VALLEYVIEW(dev)) { 1052 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER); 1053 error->forcewake = I915_READ(FORCEWAKE_VLV); 1054 } 1055 1056 if (IS_GEN7(dev)) 1057 error->err_int = I915_READ(GEN7_ERR_INT); 1058 1059 if (IS_GEN6(dev)) { 1060 error->forcewake = I915_READ(FORCEWAKE); 1061 error->gab_ctl = I915_READ(GAB_CTL); 1062 error->gfx_mode = I915_READ(GFX_MODE); 1063 } 1064 1065 if (IS_GEN2(dev)) 1066 error->ier = I915_READ16(IER); 1067 1068 /* 2: Registers which belong to multiple generations */ 1069 if (INTEL_INFO(dev)->gen >= 7) 1070 error->forcewake = I915_READ(FORCEWAKE_MT); 1071 1072 if (INTEL_INFO(dev)->gen >= 6) { 1073 error->derrmr = I915_READ(DERRMR); 1074 error->error = I915_READ(ERROR_GEN6); 1075 error->done_reg = I915_READ(DONE_REG); 1076 } 1077 1078 /* 3: Feature specific registers */ 1079 if (IS_GEN6(dev) || IS_GEN7(dev)) { 1080 error->gam_ecochk = I915_READ(GAM_ECOCHK); 1081 error->gac_eco = I915_READ(GAC_ECO_BITS); 1082 } 1083 1084 /* 4: Everything else */ 1085 if (HAS_HW_CONTEXTS(dev)) 1086 error->ccid = I915_READ(CCID); 1087 1088 if (HAS_PCH_SPLIT(dev)) 1089 error->ier = I915_READ(DEIER) | I915_READ(GTIER); 1090 else { 1091 error->ier = I915_READ(IER); 1092 for_each_pipe(pipe) 1093 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe)); 1094 } 1095 1096 /* 4: Everything else */ 1097 error->eir = I915_READ(EIR); 1098 error->pgtbl_er = I915_READ(PGTBL_ER); 1099 1100 i915_get_extra_instdone(dev, error->extra_instdone); 1101 } 1102 1103 static void i915_error_capture_msg(struct drm_device *dev, 1104 struct drm_i915_error_state *error, 1105 bool wedged, 1106 const char *error_msg) 1107 { 1108 struct drm_i915_private *dev_priv = dev->dev_private; 1109 u32 ecode; 1110 int ring_id = -1, len; 1111 1112 ecode = i915_error_generate_code(dev_priv, error, &ring_id); 1113 1114 len = scnprintf(error->error_msg, sizeof(error->error_msg), 1115 "GPU HANG: ecode %d:0x%08x", ring_id, ecode); 1116 1117 if (ring_id != -1 && error->ring[ring_id].pid != -1) 1118 len += scnprintf(error->error_msg + len, 1119 sizeof(error->error_msg) - len, 1120 ", in %s [%d]", 1121 error->ring[ring_id].comm, 1122 error->ring[ring_id].pid); 1123 1124 scnprintf(error->error_msg + len, sizeof(error->error_msg) - len, 1125 ", reason: %s, action: %s", 1126 error_msg, 1127 wedged ? "reset" : "continue"); 1128 } 1129 1130 static void i915_capture_gen_state(struct drm_i915_private *dev_priv, 1131 struct drm_i915_error_state *error) 1132 { 1133 error->reset_count = i915_reset_count(&dev_priv->gpu_error); 1134 error->suspend_count = dev_priv->suspend_count; 1135 } 1136 1137 /** 1138 * i915_capture_error_state - capture an error record for later analysis 1139 * @dev: drm device 1140 * 1141 * Should be called when an error is detected (either a hang or an error 1142 * interrupt) to capture error state from the time of the error. Fills 1143 * out a structure which becomes available in debugfs for user level tools 1144 * to pick up. 1145 */ 1146 void i915_capture_error_state(struct drm_device *dev, bool wedged, 1147 const char *error_msg) 1148 { 1149 static bool warned; 1150 struct drm_i915_private *dev_priv = dev->dev_private; 1151 struct drm_i915_error_state *error; 1152 unsigned long flags; 1153 1154 /* Account for pipe specific data like PIPE*STAT */ 1155 error = kzalloc(sizeof(*error), GFP_ATOMIC); 1156 if (!error) { 1157 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); 1158 return; 1159 } 1160 1161 kref_init(&error->ref); 1162 1163 i915_capture_gen_state(dev_priv, error); 1164 i915_capture_reg_state(dev_priv, error); 1165 i915_gem_capture_buffers(dev_priv, error); 1166 i915_gem_record_fences(dev, error); 1167 i915_gem_record_rings(dev, error); 1168 1169 do_gettimeofday(&error->time); 1170 1171 error->overlay = intel_overlay_capture_error_state(dev); 1172 error->display = intel_display_capture_error_state(dev); 1173 1174 i915_error_capture_msg(dev, error, wedged, error_msg); 1175 DRM_INFO("%s\n", error->error_msg); 1176 1177 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); 1178 if (dev_priv->gpu_error.first_error == NULL) { 1179 dev_priv->gpu_error.first_error = error; 1180 error = NULL; 1181 } 1182 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); 1183 1184 if (error) { 1185 i915_error_state_free(&error->ref); 1186 return; 1187 } 1188 1189 if (!warned) { 1190 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n"); 1191 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n"); 1192 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n"); 1193 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n"); 1194 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", dev->primary->index); 1195 warned = true; 1196 } 1197 } 1198 1199 void i915_error_state_get(struct drm_device *dev, 1200 struct i915_error_state_file_priv *error_priv) 1201 { 1202 struct drm_i915_private *dev_priv = dev->dev_private; 1203 unsigned long flags; 1204 1205 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); 1206 error_priv->error = dev_priv->gpu_error.first_error; 1207 if (error_priv->error) 1208 kref_get(&error_priv->error->ref); 1209 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); 1210 1211 } 1212 1213 void i915_error_state_put(struct i915_error_state_file_priv *error_priv) 1214 { 1215 if (error_priv->error) 1216 kref_put(&error_priv->error->ref, i915_error_state_free); 1217 } 1218 1219 void i915_destroy_error_state(struct drm_device *dev) 1220 { 1221 struct drm_i915_private *dev_priv = dev->dev_private; 1222 struct drm_i915_error_state *error; 1223 unsigned long flags; 1224 1225 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); 1226 error = dev_priv->gpu_error.first_error; 1227 dev_priv->gpu_error.first_error = NULL; 1228 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); 1229 1230 if (error) 1231 kref_put(&error->ref, i915_error_state_free); 1232 } 1233 1234 const char *i915_cache_level_str(int type) 1235 { 1236 switch (type) { 1237 case I915_CACHE_NONE: return " uncached"; 1238 case I915_CACHE_LLC: return " snooped or LLC"; 1239 case I915_CACHE_L3_LLC: return " L3+LLC"; 1240 case I915_CACHE_WT: return " WT"; 1241 default: return ""; 1242 } 1243 } 1244 1245 /* NB: please notice the memset */ 1246 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone) 1247 { 1248 struct drm_i915_private *dev_priv = dev->dev_private; 1249 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG); 1250 1251 switch (INTEL_INFO(dev)->gen) { 1252 case 2: 1253 case 3: 1254 instdone[0] = I915_READ(INSTDONE); 1255 break; 1256 case 4: 1257 case 5: 1258 case 6: 1259 instdone[0] = I915_READ(INSTDONE_I965); 1260 instdone[1] = I915_READ(INSTDONE1); 1261 break; 1262 default: 1263 WARN_ONCE(1, "Unsupported platform\n"); 1264 case 7: 1265 case 8: 1266 instdone[0] = I915_READ(GEN7_INSTDONE_1); 1267 instdone[1] = I915_READ(GEN7_SC_INSTDONE); 1268 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE); 1269 instdone[3] = I915_READ(GEN7_ROW_INSTDONE); 1270 break; 1271 } 1272 } 1273