1 /* 2 * Copyright (c) 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * Mika Kuoppala <mika.kuoppala@intel.com> 27 * 28 */ 29 30 #include <generated/utsrelease.h> 31 #include "i915_drv.h" 32 33 static const char *ring_str(int ring) 34 { 35 switch (ring) { 36 case RCS: return "render"; 37 case VCS: return "bsd"; 38 case BCS: return "blt"; 39 case VECS: return "vebox"; 40 case VCS2: return "bsd2"; 41 default: return ""; 42 } 43 } 44 45 static const char *pin_flag(int pinned) 46 { 47 if (pinned > 0) 48 return " P"; 49 else if (pinned < 0) 50 return " p"; 51 else 52 return ""; 53 } 54 55 static const char *tiling_flag(int tiling) 56 { 57 switch (tiling) { 58 default: 59 case I915_TILING_NONE: return ""; 60 case I915_TILING_X: return " X"; 61 case I915_TILING_Y: return " Y"; 62 } 63 } 64 65 static const char *dirty_flag(int dirty) 66 { 67 return dirty ? " dirty" : ""; 68 } 69 70 static const char *purgeable_flag(int purgeable) 71 { 72 return purgeable ? " purgeable" : ""; 73 } 74 75 static bool __i915_error_ok(struct drm_i915_error_state_buf *e) 76 { 77 78 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) { 79 e->err = -ENOSPC; 80 return false; 81 } 82 83 if (e->bytes == e->size - 1 || e->err) 84 return false; 85 86 return true; 87 } 88 89 static bool __i915_error_seek(struct drm_i915_error_state_buf *e, 90 unsigned len) 91 { 92 if (e->pos + len <= e->start) { 93 e->pos += len; 94 return false; 95 } 96 97 /* First vsnprintf needs to fit in its entirety for memmove */ 98 if (len >= e->size) { 99 e->err = -EIO; 100 return false; 101 } 102 103 return true; 104 } 105 106 static void __i915_error_advance(struct drm_i915_error_state_buf *e, 107 unsigned len) 108 { 109 /* If this is first printf in this window, adjust it so that 110 * start position matches start of the buffer 111 */ 112 113 if (e->pos < e->start) { 114 const size_t off = e->start - e->pos; 115 116 /* Should not happen but be paranoid */ 117 if (off > len || e->bytes) { 118 e->err = -EIO; 119 return; 120 } 121 122 memmove(e->buf, e->buf + off, len - off); 123 e->bytes = len - off; 124 e->pos = e->start; 125 return; 126 } 127 128 e->bytes += len; 129 e->pos += len; 130 } 131 132 static void i915_error_vprintf(struct drm_i915_error_state_buf *e, 133 const char *f, va_list args) 134 { 135 unsigned len; 136 137 if (!__i915_error_ok(e)) 138 return; 139 140 /* Seek the first printf which is hits start position */ 141 if (e->pos < e->start) { 142 va_list tmp; 143 144 va_copy(tmp, args); 145 len = vsnprintf(NULL, 0, f, tmp); 146 va_end(tmp); 147 148 if (!__i915_error_seek(e, len)) 149 return; 150 } 151 152 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args); 153 if (len >= e->size - e->bytes) 154 len = e->size - e->bytes - 1; 155 156 __i915_error_advance(e, len); 157 } 158 159 static void i915_error_puts(struct drm_i915_error_state_buf *e, 160 const char *str) 161 { 162 unsigned len; 163 164 if (!__i915_error_ok(e)) 165 return; 166 167 len = strlen(str); 168 169 /* Seek the first printf which is hits start position */ 170 if (e->pos < e->start) { 171 if (!__i915_error_seek(e, len)) 172 return; 173 } 174 175 if (len >= e->size - e->bytes) 176 len = e->size - e->bytes - 1; 177 memcpy(e->buf + e->bytes, str, len); 178 179 __i915_error_advance(e, len); 180 } 181 182 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) 183 #define err_puts(e, s) i915_error_puts(e, s) 184 185 static void print_error_buffers(struct drm_i915_error_state_buf *m, 186 const char *name, 187 struct drm_i915_error_buffer *err, 188 int count) 189 { 190 int i; 191 192 err_printf(m, " %s [%d]:\n", name, count); 193 194 while (count--) { 195 err_printf(m, " %08x_%08x %8u %02x %02x [ ", 196 upper_32_bits(err->gtt_offset), 197 lower_32_bits(err->gtt_offset), 198 err->size, 199 err->read_domains, 200 err->write_domain); 201 for (i = 0; i < I915_NUM_ENGINES; i++) 202 err_printf(m, "%02x ", err->rseqno[i]); 203 204 err_printf(m, "] %02x", err->wseqno); 205 err_puts(m, pin_flag(err->pinned)); 206 err_puts(m, tiling_flag(err->tiling)); 207 err_puts(m, dirty_flag(err->dirty)); 208 err_puts(m, purgeable_flag(err->purgeable)); 209 err_puts(m, err->userptr ? " userptr" : ""); 210 err_puts(m, err->ring != -1 ? " " : ""); 211 err_puts(m, ring_str(err->ring)); 212 err_puts(m, i915_cache_level_str(m->i915, err->cache_level)); 213 214 if (err->name) 215 err_printf(m, " (name: %d)", err->name); 216 if (err->fence_reg != I915_FENCE_REG_NONE) 217 err_printf(m, " (fence: %d)", err->fence_reg); 218 219 err_puts(m, "\n"); 220 err++; 221 } 222 } 223 224 static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a) 225 { 226 switch (a) { 227 case HANGCHECK_IDLE: 228 return "idle"; 229 case HANGCHECK_WAIT: 230 return "wait"; 231 case HANGCHECK_ACTIVE: 232 return "active"; 233 case HANGCHECK_KICK: 234 return "kick"; 235 case HANGCHECK_HUNG: 236 return "hung"; 237 } 238 239 return "unknown"; 240 } 241 242 static void i915_ring_error_state(struct drm_i915_error_state_buf *m, 243 struct drm_device *dev, 244 struct drm_i915_error_state *error, 245 int ring_idx) 246 { 247 struct drm_i915_error_ring *ring = &error->ring[ring_idx]; 248 249 if (!ring->valid) 250 return; 251 252 err_printf(m, "%s command stream:\n", ring_str(ring_idx)); 253 err_printf(m, " START: 0x%08x\n", ring->start); 254 err_printf(m, " HEAD: 0x%08x\n", ring->head); 255 err_printf(m, " TAIL: 0x%08x\n", ring->tail); 256 err_printf(m, " CTL: 0x%08x\n", ring->ctl); 257 err_printf(m, " HWS: 0x%08x\n", ring->hws); 258 err_printf(m, " ACTHD: 0x%08x %08x\n", (u32)(ring->acthd>>32), (u32)ring->acthd); 259 err_printf(m, " IPEIR: 0x%08x\n", ring->ipeir); 260 err_printf(m, " IPEHR: 0x%08x\n", ring->ipehr); 261 err_printf(m, " INSTDONE: 0x%08x\n", ring->instdone); 262 if (INTEL_INFO(dev)->gen >= 4) { 263 err_printf(m, " BBADDR: 0x%08x %08x\n", (u32)(ring->bbaddr>>32), (u32)ring->bbaddr); 264 err_printf(m, " BB_STATE: 0x%08x\n", ring->bbstate); 265 err_printf(m, " INSTPS: 0x%08x\n", ring->instps); 266 } 267 err_printf(m, " INSTPM: 0x%08x\n", ring->instpm); 268 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ring->faddr), 269 lower_32_bits(ring->faddr)); 270 if (INTEL_INFO(dev)->gen >= 6) { 271 err_printf(m, " RC PSMI: 0x%08x\n", ring->rc_psmi); 272 err_printf(m, " FAULT_REG: 0x%08x\n", ring->fault_reg); 273 err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n", 274 ring->semaphore_mboxes[0], 275 ring->semaphore_seqno[0]); 276 err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n", 277 ring->semaphore_mboxes[1], 278 ring->semaphore_seqno[1]); 279 if (HAS_VEBOX(dev)) { 280 err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n", 281 ring->semaphore_mboxes[2], 282 ring->semaphore_seqno[2]); 283 } 284 } 285 if (USES_PPGTT(dev)) { 286 err_printf(m, " GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode); 287 288 if (INTEL_INFO(dev)->gen >= 8) { 289 int i; 290 for (i = 0; i < 4; i++) 291 err_printf(m, " PDP%d: 0x%016llx\n", 292 i, ring->vm_info.pdp[i]); 293 } else { 294 err_printf(m, " PP_DIR_BASE: 0x%08x\n", 295 ring->vm_info.pp_dir_base); 296 } 297 } 298 err_printf(m, " seqno: 0x%08x\n", ring->seqno); 299 err_printf(m, " last_seqno: 0x%08x\n", ring->last_seqno); 300 err_printf(m, " waiting: %s\n", yesno(ring->waiting)); 301 err_printf(m, " ring->head: 0x%08x\n", ring->cpu_ring_head); 302 err_printf(m, " ring->tail: 0x%08x\n", ring->cpu_ring_tail); 303 err_printf(m, " hangcheck: %s [%d]\n", 304 hangcheck_action_to_str(ring->hangcheck_action), 305 ring->hangcheck_score); 306 } 307 308 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) 309 { 310 va_list args; 311 312 va_start(args, f); 313 i915_error_vprintf(e, f, args); 314 va_end(args); 315 } 316 317 static void print_error_obj(struct drm_i915_error_state_buf *m, 318 struct drm_i915_error_object *obj) 319 { 320 int page, offset, elt; 321 322 for (page = offset = 0; page < obj->page_count; page++) { 323 for (elt = 0; elt < PAGE_SIZE/4; elt++) { 324 err_printf(m, "%08x : %08x\n", offset, 325 obj->pages[page][elt]); 326 offset += 4; 327 } 328 } 329 } 330 331 int i915_error_state_to_str(struct drm_i915_error_state_buf *m, 332 const struct i915_error_state_file_priv *error_priv) 333 { 334 struct drm_device *dev = error_priv->dev; 335 struct drm_i915_private *dev_priv = dev->dev_private; 336 struct drm_i915_error_state *error = error_priv->error; 337 struct drm_i915_error_object *obj; 338 int i, j, offset, elt; 339 int max_hangcheck_score; 340 341 if (!error) { 342 err_printf(m, "no error state collected\n"); 343 goto out; 344 } 345 346 err_printf(m, "%s\n", error->error_msg); 347 err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec, 348 error->time.tv_usec); 349 err_printf(m, "Kernel: " UTS_RELEASE "\n"); 350 max_hangcheck_score = 0; 351 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 352 if (error->ring[i].hangcheck_score > max_hangcheck_score) 353 max_hangcheck_score = error->ring[i].hangcheck_score; 354 } 355 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 356 if (error->ring[i].hangcheck_score == max_hangcheck_score && 357 error->ring[i].pid != -1) { 358 err_printf(m, "Active process (on ring %s): %s [%d]\n", 359 ring_str(i), 360 error->ring[i].comm, 361 error->ring[i].pid); 362 } 363 } 364 err_printf(m, "Reset count: %u\n", error->reset_count); 365 err_printf(m, "Suspend count: %u\n", error->suspend_count); 366 err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device); 367 err_printf(m, "PCI Revision: 0x%02x\n", dev->pdev->revision); 368 err_printf(m, "PCI Subsystem: %04x:%04x\n", 369 dev->pdev->subsystem_vendor, 370 dev->pdev->subsystem_device); 371 err_printf(m, "IOMMU enabled?: %d\n", error->iommu); 372 373 if (HAS_CSR(dev)) { 374 struct intel_csr *csr = &dev_priv->csr; 375 376 err_printf(m, "DMC loaded: %s\n", 377 yesno(csr->dmc_payload != NULL)); 378 err_printf(m, "DMC fw version: %d.%d\n", 379 CSR_VERSION_MAJOR(csr->version), 380 CSR_VERSION_MINOR(csr->version)); 381 } 382 383 err_printf(m, "EIR: 0x%08x\n", error->eir); 384 err_printf(m, "IER: 0x%08x\n", error->ier); 385 if (INTEL_INFO(dev)->gen >= 8) { 386 for (i = 0; i < 4; i++) 387 err_printf(m, "GTIER gt %d: 0x%08x\n", i, 388 error->gtier[i]); 389 } else if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev)) 390 err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]); 391 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er); 392 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake); 393 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr); 394 err_printf(m, "CCID: 0x%08x\n", error->ccid); 395 err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings); 396 397 for (i = 0; i < dev_priv->num_fence_regs; i++) 398 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]); 399 400 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++) 401 err_printf(m, " INSTDONE_%d: 0x%08x\n", i, 402 error->extra_instdone[i]); 403 404 if (INTEL_INFO(dev)->gen >= 6) { 405 err_printf(m, "ERROR: 0x%08x\n", error->error); 406 407 if (INTEL_INFO(dev)->gen >= 8) 408 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n", 409 error->fault_data1, error->fault_data0); 410 411 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); 412 } 413 414 if (INTEL_INFO(dev)->gen == 7) 415 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int); 416 417 for (i = 0; i < ARRAY_SIZE(error->ring); i++) 418 i915_ring_error_state(m, dev, error, i); 419 420 for (i = 0; i < error->vm_count; i++) { 421 err_printf(m, "vm[%d]\n", i); 422 423 print_error_buffers(m, "Active", 424 error->active_bo[i], 425 error->active_bo_count[i]); 426 427 print_error_buffers(m, "Pinned", 428 error->pinned_bo[i], 429 error->pinned_bo_count[i]); 430 } 431 432 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 433 obj = error->ring[i].batchbuffer; 434 if (obj) { 435 err_puts(m, dev_priv->engine[i].name); 436 if (error->ring[i].pid != -1) 437 err_printf(m, " (submitted by %s [%d])", 438 error->ring[i].comm, 439 error->ring[i].pid); 440 err_printf(m, " --- gtt_offset = 0x%08x %08x\n", 441 upper_32_bits(obj->gtt_offset), 442 lower_32_bits(obj->gtt_offset)); 443 print_error_obj(m, obj); 444 } 445 446 obj = error->ring[i].wa_batchbuffer; 447 if (obj) { 448 err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n", 449 dev_priv->engine[i].name, 450 lower_32_bits(obj->gtt_offset)); 451 print_error_obj(m, obj); 452 } 453 454 if (error->ring[i].num_requests) { 455 err_printf(m, "%s --- %d requests\n", 456 dev_priv->engine[i].name, 457 error->ring[i].num_requests); 458 for (j = 0; j < error->ring[i].num_requests; j++) { 459 err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n", 460 error->ring[i].requests[j].seqno, 461 error->ring[i].requests[j].jiffies, 462 error->ring[i].requests[j].tail); 463 } 464 } 465 466 if ((obj = error->ring[i].ringbuffer)) { 467 err_printf(m, "%s --- ringbuffer = 0x%08x\n", 468 dev_priv->engine[i].name, 469 lower_32_bits(obj->gtt_offset)); 470 print_error_obj(m, obj); 471 } 472 473 if ((obj = error->ring[i].hws_page)) { 474 u64 hws_offset = obj->gtt_offset; 475 u32 *hws_page = &obj->pages[0][0]; 476 477 if (i915.enable_execlists) { 478 hws_offset += LRC_PPHWSP_PN * PAGE_SIZE; 479 hws_page = &obj->pages[LRC_PPHWSP_PN][0]; 480 } 481 err_printf(m, "%s --- HW Status = 0x%08llx\n", 482 dev_priv->engine[i].name, hws_offset); 483 offset = 0; 484 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) { 485 err_printf(m, "[%04x] %08x %08x %08x %08x\n", 486 offset, 487 hws_page[elt], 488 hws_page[elt+1], 489 hws_page[elt+2], 490 hws_page[elt+3]); 491 offset += 16; 492 } 493 } 494 495 obj = error->ring[i].wa_ctx; 496 if (obj) { 497 u64 wa_ctx_offset = obj->gtt_offset; 498 u32 *wa_ctx_page = &obj->pages[0][0]; 499 struct intel_engine_cs *engine = &dev_priv->engine[RCS]; 500 u32 wa_ctx_size = (engine->wa_ctx.indirect_ctx.size + 501 engine->wa_ctx.per_ctx.size); 502 503 err_printf(m, "%s --- WA ctx batch buffer = 0x%08llx\n", 504 dev_priv->engine[i].name, wa_ctx_offset); 505 offset = 0; 506 for (elt = 0; elt < wa_ctx_size; elt += 4) { 507 err_printf(m, "[%04x] %08x %08x %08x %08x\n", 508 offset, 509 wa_ctx_page[elt + 0], 510 wa_ctx_page[elt + 1], 511 wa_ctx_page[elt + 2], 512 wa_ctx_page[elt + 3]); 513 offset += 16; 514 } 515 } 516 517 if ((obj = error->ring[i].ctx)) { 518 err_printf(m, "%s --- HW Context = 0x%08x\n", 519 dev_priv->engine[i].name, 520 lower_32_bits(obj->gtt_offset)); 521 print_error_obj(m, obj); 522 } 523 } 524 525 if ((obj = error->semaphore_obj)) { 526 err_printf(m, "Semaphore page = 0x%08x\n", 527 lower_32_bits(obj->gtt_offset)); 528 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) { 529 err_printf(m, "[%04x] %08x %08x %08x %08x\n", 530 elt * 4, 531 obj->pages[0][elt], 532 obj->pages[0][elt+1], 533 obj->pages[0][elt+2], 534 obj->pages[0][elt+3]); 535 } 536 } 537 538 if (error->overlay) 539 intel_overlay_print_error_state(m, error->overlay); 540 541 if (error->display) 542 intel_display_print_error_state(m, dev, error->display); 543 544 out: 545 if (m->bytes == 0 && m->err) 546 return m->err; 547 548 return 0; 549 } 550 551 int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf, 552 struct drm_i915_private *i915, 553 size_t count, loff_t pos) 554 { 555 memset(ebuf, 0, sizeof(*ebuf)); 556 ebuf->i915 = i915; 557 558 /* We need to have enough room to store any i915_error_state printf 559 * so that we can move it to start position. 560 */ 561 ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE; 562 ebuf->buf = kmalloc(ebuf->size, 563 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN); 564 565 if (ebuf->buf == NULL) { 566 ebuf->size = PAGE_SIZE; 567 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY); 568 } 569 570 if (ebuf->buf == NULL) { 571 ebuf->size = 128; 572 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY); 573 } 574 575 if (ebuf->buf == NULL) 576 return -ENOMEM; 577 578 ebuf->start = pos; 579 580 return 0; 581 } 582 583 static void i915_error_object_free(struct drm_i915_error_object *obj) 584 { 585 int page; 586 587 if (obj == NULL) 588 return; 589 590 for (page = 0; page < obj->page_count; page++) 591 kfree(obj->pages[page]); 592 593 kfree(obj); 594 } 595 596 static void i915_error_state_free(struct kref *error_ref) 597 { 598 struct drm_i915_error_state *error = container_of(error_ref, 599 typeof(*error), ref); 600 int i; 601 602 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 603 i915_error_object_free(error->ring[i].batchbuffer); 604 i915_error_object_free(error->ring[i].wa_batchbuffer); 605 i915_error_object_free(error->ring[i].ringbuffer); 606 i915_error_object_free(error->ring[i].hws_page); 607 i915_error_object_free(error->ring[i].ctx); 608 kfree(error->ring[i].requests); 609 i915_error_object_free(error->ring[i].wa_ctx); 610 } 611 612 i915_error_object_free(error->semaphore_obj); 613 614 for (i = 0; i < error->vm_count; i++) 615 kfree(error->active_bo[i]); 616 617 kfree(error->active_bo); 618 kfree(error->active_bo_count); 619 kfree(error->pinned_bo); 620 kfree(error->pinned_bo_count); 621 kfree(error->overlay); 622 kfree(error->display); 623 kfree(error); 624 } 625 626 static struct drm_i915_error_object * 627 i915_error_object_create(struct drm_i915_private *dev_priv, 628 struct drm_i915_gem_object *src, 629 struct i915_address_space *vm) 630 { 631 struct i915_ggtt *ggtt = &dev_priv->ggtt; 632 struct drm_i915_error_object *dst; 633 struct i915_vma *vma = NULL; 634 int num_pages; 635 bool use_ggtt; 636 int i = 0; 637 u64 reloc_offset; 638 639 if (src == NULL || src->pages == NULL) 640 return NULL; 641 642 num_pages = src->base.size >> PAGE_SHIFT; 643 644 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC); 645 if (dst == NULL) 646 return NULL; 647 648 if (i915_gem_obj_bound(src, vm)) 649 dst->gtt_offset = i915_gem_obj_offset(src, vm); 650 else 651 dst->gtt_offset = -1; 652 653 reloc_offset = dst->gtt_offset; 654 if (i915_is_ggtt(vm)) 655 vma = i915_gem_obj_to_ggtt(src); 656 use_ggtt = (src->cache_level == I915_CACHE_NONE && 657 vma && (vma->bound & GLOBAL_BIND) && 658 reloc_offset + num_pages * PAGE_SIZE <= ggtt->mappable_end); 659 660 /* Cannot access stolen address directly, try to use the aperture */ 661 if (src->stolen) { 662 use_ggtt = true; 663 664 if (!(vma && vma->bound & GLOBAL_BIND)) 665 goto unwind; 666 667 reloc_offset = i915_gem_obj_ggtt_offset(src); 668 if (reloc_offset + num_pages * PAGE_SIZE > ggtt->mappable_end) 669 goto unwind; 670 } 671 672 /* Cannot access snooped pages through the aperture */ 673 if (use_ggtt && src->cache_level != I915_CACHE_NONE && 674 !HAS_LLC(dev_priv)) 675 goto unwind; 676 677 dst->page_count = num_pages; 678 while (num_pages--) { 679 unsigned long flags; 680 void *d; 681 682 d = kmalloc(PAGE_SIZE, GFP_ATOMIC); 683 if (d == NULL) 684 goto unwind; 685 686 local_irq_save(flags); 687 if (use_ggtt) { 688 void __iomem *s; 689 690 /* Simply ignore tiling or any overlapping fence. 691 * It's part of the error state, and this hopefully 692 * captures what the GPU read. 693 */ 694 695 s = io_mapping_map_atomic_wc(ggtt->mappable, 696 reloc_offset); 697 memcpy_fromio(d, s, PAGE_SIZE); 698 io_mapping_unmap_atomic(s); 699 } else { 700 struct page *page; 701 void *s; 702 703 page = i915_gem_object_get_page(src, i); 704 705 drm_clflush_pages(&page, 1); 706 707 s = kmap_atomic(page); 708 memcpy(d, s, PAGE_SIZE); 709 kunmap_atomic(s); 710 711 drm_clflush_pages(&page, 1); 712 } 713 local_irq_restore(flags); 714 715 dst->pages[i++] = d; 716 reloc_offset += PAGE_SIZE; 717 } 718 719 return dst; 720 721 unwind: 722 while (i--) 723 kfree(dst->pages[i]); 724 kfree(dst); 725 return NULL; 726 } 727 #define i915_error_ggtt_object_create(dev_priv, src) \ 728 i915_error_object_create((dev_priv), (src), &(dev_priv)->ggtt.base) 729 730 static void capture_bo(struct drm_i915_error_buffer *err, 731 struct i915_vma *vma) 732 { 733 struct drm_i915_gem_object *obj = vma->obj; 734 int i; 735 736 err->size = obj->base.size; 737 err->name = obj->base.name; 738 for (i = 0; i < I915_NUM_ENGINES; i++) 739 err->rseqno[i] = i915_gem_request_get_seqno(obj->last_read_req[i]); 740 err->wseqno = i915_gem_request_get_seqno(obj->last_write_req); 741 err->gtt_offset = vma->node.start; 742 err->read_domains = obj->base.read_domains; 743 err->write_domain = obj->base.write_domain; 744 err->fence_reg = obj->fence_reg; 745 err->pinned = 0; 746 if (i915_gem_obj_is_pinned(obj)) 747 err->pinned = 1; 748 err->tiling = obj->tiling_mode; 749 err->dirty = obj->dirty; 750 err->purgeable = obj->madv != I915_MADV_WILLNEED; 751 err->userptr = obj->userptr.mm != NULL; 752 err->ring = obj->last_write_req ? 753 i915_gem_request_get_engine(obj->last_write_req)->id : -1; 754 err->cache_level = obj->cache_level; 755 } 756 757 static u32 capture_active_bo(struct drm_i915_error_buffer *err, 758 int count, struct list_head *head) 759 { 760 struct i915_vma *vma; 761 int i = 0; 762 763 list_for_each_entry(vma, head, vm_link) { 764 capture_bo(err++, vma); 765 if (++i == count) 766 break; 767 } 768 769 return i; 770 } 771 772 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err, 773 int count, struct list_head *head, 774 struct i915_address_space *vm) 775 { 776 struct drm_i915_gem_object *obj; 777 struct drm_i915_error_buffer * const first = err; 778 struct drm_i915_error_buffer * const last = err + count; 779 780 list_for_each_entry(obj, head, global_list) { 781 struct i915_vma *vma; 782 783 if (err == last) 784 break; 785 786 list_for_each_entry(vma, &obj->vma_list, obj_link) 787 if (vma->vm == vm && vma->pin_count > 0) 788 capture_bo(err++, vma); 789 } 790 791 return err - first; 792 } 793 794 /* Generate a semi-unique error code. The code is not meant to have meaning, The 795 * code's only purpose is to try to prevent false duplicated bug reports by 796 * grossly estimating a GPU error state. 797 * 798 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine 799 * the hang if we could strip the GTT offset information from it. 800 * 801 * It's only a small step better than a random number in its current form. 802 */ 803 static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv, 804 struct drm_i915_error_state *error, 805 int *ring_id) 806 { 807 uint32_t error_code = 0; 808 int i; 809 810 /* IPEHR would be an ideal way to detect errors, as it's the gross 811 * measure of "the command that hung." However, has some very common 812 * synchronization commands which almost always appear in the case 813 * strictly a client bug. Use instdone to differentiate those some. 814 */ 815 for (i = 0; i < I915_NUM_ENGINES; i++) { 816 if (error->ring[i].hangcheck_action == HANGCHECK_HUNG) { 817 if (ring_id) 818 *ring_id = i; 819 820 return error->ring[i].ipehr ^ error->ring[i].instdone; 821 } 822 } 823 824 return error_code; 825 } 826 827 static void i915_gem_record_fences(struct drm_device *dev, 828 struct drm_i915_error_state *error) 829 { 830 struct drm_i915_private *dev_priv = dev->dev_private; 831 int i; 832 833 if (IS_GEN3(dev) || IS_GEN2(dev)) { 834 for (i = 0; i < dev_priv->num_fence_regs; i++) 835 error->fence[i] = I915_READ(FENCE_REG(i)); 836 } else if (IS_GEN5(dev) || IS_GEN4(dev)) { 837 for (i = 0; i < dev_priv->num_fence_regs; i++) 838 error->fence[i] = I915_READ64(FENCE_REG_965_LO(i)); 839 } else if (INTEL_INFO(dev)->gen >= 6) { 840 for (i = 0; i < dev_priv->num_fence_regs; i++) 841 error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i)); 842 } 843 } 844 845 846 static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv, 847 struct drm_i915_error_state *error, 848 struct intel_engine_cs *engine, 849 struct drm_i915_error_ring *ering) 850 { 851 struct intel_engine_cs *to; 852 enum intel_engine_id id; 853 854 if (!i915_semaphore_is_enabled(dev_priv->dev)) 855 return; 856 857 if (!error->semaphore_obj) 858 error->semaphore_obj = 859 i915_error_ggtt_object_create(dev_priv, 860 dev_priv->semaphore_obj); 861 862 for_each_engine_id(to, dev_priv, id) { 863 int idx; 864 u16 signal_offset; 865 u32 *tmp; 866 867 if (engine == to) 868 continue; 869 870 signal_offset = (GEN8_SIGNAL_OFFSET(engine, id) & (PAGE_SIZE - 1)) 871 / 4; 872 tmp = error->semaphore_obj->pages[0]; 873 idx = intel_ring_sync_index(engine, to); 874 875 ering->semaphore_mboxes[idx] = tmp[signal_offset]; 876 ering->semaphore_seqno[idx] = engine->semaphore.sync_seqno[idx]; 877 } 878 } 879 880 static void gen6_record_semaphore_state(struct drm_i915_private *dev_priv, 881 struct intel_engine_cs *engine, 882 struct drm_i915_error_ring *ering) 883 { 884 ering->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(engine->mmio_base)); 885 ering->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(engine->mmio_base)); 886 ering->semaphore_seqno[0] = engine->semaphore.sync_seqno[0]; 887 ering->semaphore_seqno[1] = engine->semaphore.sync_seqno[1]; 888 889 if (HAS_VEBOX(dev_priv)) { 890 ering->semaphore_mboxes[2] = 891 I915_READ(RING_SYNC_2(engine->mmio_base)); 892 ering->semaphore_seqno[2] = engine->semaphore.sync_seqno[2]; 893 } 894 } 895 896 static void i915_record_ring_state(struct drm_device *dev, 897 struct drm_i915_error_state *error, 898 struct intel_engine_cs *engine, 899 struct drm_i915_error_ring *ering) 900 { 901 struct drm_i915_private *dev_priv = dev->dev_private; 902 903 if (INTEL_INFO(dev)->gen >= 6) { 904 ering->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base)); 905 ering->fault_reg = I915_READ(RING_FAULT_REG(engine)); 906 if (INTEL_INFO(dev)->gen >= 8) 907 gen8_record_semaphore_state(dev_priv, error, engine, 908 ering); 909 else 910 gen6_record_semaphore_state(dev_priv, engine, ering); 911 } 912 913 if (INTEL_INFO(dev)->gen >= 4) { 914 ering->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base)); 915 ering->ipeir = I915_READ(RING_IPEIR(engine->mmio_base)); 916 ering->ipehr = I915_READ(RING_IPEHR(engine->mmio_base)); 917 ering->instdone = I915_READ(RING_INSTDONE(engine->mmio_base)); 918 ering->instps = I915_READ(RING_INSTPS(engine->mmio_base)); 919 ering->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base)); 920 if (INTEL_INFO(dev)->gen >= 8) { 921 ering->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32; 922 ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32; 923 } 924 ering->bbstate = I915_READ(RING_BBSTATE(engine->mmio_base)); 925 } else { 926 ering->faddr = I915_READ(DMA_FADD_I8XX); 927 ering->ipeir = I915_READ(IPEIR); 928 ering->ipehr = I915_READ(IPEHR); 929 ering->instdone = I915_READ(GEN2_INSTDONE); 930 } 931 932 ering->waiting = waitqueue_active(&engine->irq_queue); 933 ering->instpm = I915_READ(RING_INSTPM(engine->mmio_base)); 934 ering->acthd = intel_ring_get_active_head(engine); 935 ering->seqno = engine->get_seqno(engine); 936 ering->last_seqno = engine->last_submitted_seqno; 937 ering->start = I915_READ_START(engine); 938 ering->head = I915_READ_HEAD(engine); 939 ering->tail = I915_READ_TAIL(engine); 940 ering->ctl = I915_READ_CTL(engine); 941 942 if (I915_NEED_GFX_HWS(dev)) { 943 i915_reg_t mmio; 944 945 if (IS_GEN7(dev)) { 946 switch (engine->id) { 947 default: 948 case RCS: 949 mmio = RENDER_HWS_PGA_GEN7; 950 break; 951 case BCS: 952 mmio = BLT_HWS_PGA_GEN7; 953 break; 954 case VCS: 955 mmio = BSD_HWS_PGA_GEN7; 956 break; 957 case VECS: 958 mmio = VEBOX_HWS_PGA_GEN7; 959 break; 960 } 961 } else if (IS_GEN6(engine->dev)) { 962 mmio = RING_HWS_PGA_GEN6(engine->mmio_base); 963 } else { 964 /* XXX: gen8 returns to sanity */ 965 mmio = RING_HWS_PGA(engine->mmio_base); 966 } 967 968 ering->hws = I915_READ(mmio); 969 } 970 971 ering->hangcheck_score = engine->hangcheck.score; 972 ering->hangcheck_action = engine->hangcheck.action; 973 974 if (USES_PPGTT(dev)) { 975 int i; 976 977 ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine)); 978 979 if (IS_GEN6(dev)) 980 ering->vm_info.pp_dir_base = 981 I915_READ(RING_PP_DIR_BASE_READ(engine)); 982 else if (IS_GEN7(dev)) 983 ering->vm_info.pp_dir_base = 984 I915_READ(RING_PP_DIR_BASE(engine)); 985 else if (INTEL_INFO(dev)->gen >= 8) 986 for (i = 0; i < 4; i++) { 987 ering->vm_info.pdp[i] = 988 I915_READ(GEN8_RING_PDP_UDW(engine, i)); 989 ering->vm_info.pdp[i] <<= 32; 990 ering->vm_info.pdp[i] |= 991 I915_READ(GEN8_RING_PDP_LDW(engine, i)); 992 } 993 } 994 } 995 996 997 static void i915_gem_record_active_context(struct intel_engine_cs *engine, 998 struct drm_i915_error_state *error, 999 struct drm_i915_error_ring *ering) 1000 { 1001 struct drm_i915_private *dev_priv = engine->dev->dev_private; 1002 struct drm_i915_gem_object *obj; 1003 1004 /* Currently render ring is the only HW context user */ 1005 if (engine->id != RCS || !error->ccid) 1006 return; 1007 1008 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { 1009 if (!i915_gem_obj_ggtt_bound(obj)) 1010 continue; 1011 1012 if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) { 1013 ering->ctx = i915_error_ggtt_object_create(dev_priv, obj); 1014 break; 1015 } 1016 } 1017 } 1018 1019 static void i915_gem_record_rings(struct drm_device *dev, 1020 struct drm_i915_error_state *error) 1021 { 1022 struct drm_i915_private *dev_priv = to_i915(dev); 1023 struct i915_ggtt *ggtt = &dev_priv->ggtt; 1024 struct drm_i915_gem_request *request; 1025 int i, count; 1026 1027 for (i = 0; i < I915_NUM_ENGINES; i++) { 1028 struct intel_engine_cs *engine = &dev_priv->engine[i]; 1029 struct intel_ringbuffer *rbuf; 1030 1031 error->ring[i].pid = -1; 1032 1033 if (engine->dev == NULL) 1034 continue; 1035 1036 error->ring[i].valid = true; 1037 1038 i915_record_ring_state(dev, error, engine, &error->ring[i]); 1039 1040 request = i915_gem_find_active_request(engine); 1041 if (request) { 1042 struct i915_address_space *vm; 1043 1044 vm = request->ctx && request->ctx->ppgtt ? 1045 &request->ctx->ppgtt->base : 1046 &ggtt->base; 1047 1048 /* We need to copy these to an anonymous buffer 1049 * as the simplest method to avoid being overwritten 1050 * by userspace. 1051 */ 1052 error->ring[i].batchbuffer = 1053 i915_error_object_create(dev_priv, 1054 request->batch_obj, 1055 vm); 1056 1057 if (HAS_BROKEN_CS_TLB(dev_priv)) 1058 error->ring[i].wa_batchbuffer = 1059 i915_error_ggtt_object_create(dev_priv, 1060 engine->scratch.obj); 1061 1062 if (request->pid) { 1063 struct task_struct *task; 1064 1065 rcu_read_lock(); 1066 task = pid_task(request->pid, PIDTYPE_PID); 1067 if (task) { 1068 strcpy(error->ring[i].comm, task->comm); 1069 error->ring[i].pid = task->pid; 1070 } 1071 rcu_read_unlock(); 1072 } 1073 } 1074 1075 if (i915.enable_execlists) { 1076 /* TODO: This is only a small fix to keep basic error 1077 * capture working, but we need to add more information 1078 * for it to be useful (e.g. dump the context being 1079 * executed). 1080 */ 1081 if (request) 1082 rbuf = request->ctx->engine[engine->id].ringbuf; 1083 else 1084 rbuf = dev_priv->kernel_context->engine[engine->id].ringbuf; 1085 } else 1086 rbuf = engine->buffer; 1087 1088 error->ring[i].cpu_ring_head = rbuf->head; 1089 error->ring[i].cpu_ring_tail = rbuf->tail; 1090 1091 error->ring[i].ringbuffer = 1092 i915_error_ggtt_object_create(dev_priv, rbuf->obj); 1093 1094 error->ring[i].hws_page = 1095 i915_error_ggtt_object_create(dev_priv, 1096 engine->status_page.obj); 1097 1098 if (engine->wa_ctx.obj) { 1099 error->ring[i].wa_ctx = 1100 i915_error_ggtt_object_create(dev_priv, 1101 engine->wa_ctx.obj); 1102 } 1103 1104 i915_gem_record_active_context(engine, error, &error->ring[i]); 1105 1106 count = 0; 1107 list_for_each_entry(request, &engine->request_list, list) 1108 count++; 1109 1110 error->ring[i].num_requests = count; 1111 error->ring[i].requests = 1112 kcalloc(count, sizeof(*error->ring[i].requests), 1113 GFP_ATOMIC); 1114 if (error->ring[i].requests == NULL) { 1115 error->ring[i].num_requests = 0; 1116 continue; 1117 } 1118 1119 count = 0; 1120 list_for_each_entry(request, &engine->request_list, list) { 1121 struct drm_i915_error_request *erq; 1122 1123 if (count >= error->ring[i].num_requests) { 1124 /* 1125 * If the ring request list was changed in 1126 * between the point where the error request 1127 * list was created and dimensioned and this 1128 * point then just exit early to avoid crashes. 1129 * 1130 * We don't need to communicate that the 1131 * request list changed state during error 1132 * state capture and that the error state is 1133 * slightly incorrect as a consequence since we 1134 * are typically only interested in the request 1135 * list state at the point of error state 1136 * capture, not in any changes happening during 1137 * the capture. 1138 */ 1139 break; 1140 } 1141 1142 erq = &error->ring[i].requests[count++]; 1143 erq->seqno = request->seqno; 1144 erq->jiffies = request->emitted_jiffies; 1145 erq->tail = request->postfix; 1146 } 1147 } 1148 } 1149 1150 /* FIXME: Since pin count/bound list is global, we duplicate what we capture per 1151 * VM. 1152 */ 1153 static void i915_gem_capture_vm(struct drm_i915_private *dev_priv, 1154 struct drm_i915_error_state *error, 1155 struct i915_address_space *vm, 1156 const int ndx) 1157 { 1158 struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL; 1159 struct drm_i915_gem_object *obj; 1160 struct i915_vma *vma; 1161 int i; 1162 1163 i = 0; 1164 list_for_each_entry(vma, &vm->active_list, vm_link) 1165 i++; 1166 error->active_bo_count[ndx] = i; 1167 1168 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { 1169 list_for_each_entry(vma, &obj->vma_list, obj_link) 1170 if (vma->vm == vm && vma->pin_count > 0) 1171 i++; 1172 } 1173 error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx]; 1174 1175 if (i) { 1176 active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC); 1177 if (active_bo) 1178 pinned_bo = active_bo + error->active_bo_count[ndx]; 1179 } 1180 1181 if (active_bo) 1182 error->active_bo_count[ndx] = 1183 capture_active_bo(active_bo, 1184 error->active_bo_count[ndx], 1185 &vm->active_list); 1186 1187 if (pinned_bo) 1188 error->pinned_bo_count[ndx] = 1189 capture_pinned_bo(pinned_bo, 1190 error->pinned_bo_count[ndx], 1191 &dev_priv->mm.bound_list, vm); 1192 error->active_bo[ndx] = active_bo; 1193 error->pinned_bo[ndx] = pinned_bo; 1194 } 1195 1196 static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv, 1197 struct drm_i915_error_state *error) 1198 { 1199 struct i915_address_space *vm; 1200 int cnt = 0, i = 0; 1201 1202 list_for_each_entry(vm, &dev_priv->vm_list, global_link) 1203 cnt++; 1204 1205 error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC); 1206 error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC); 1207 error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count), 1208 GFP_ATOMIC); 1209 error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count), 1210 GFP_ATOMIC); 1211 1212 if (error->active_bo == NULL || 1213 error->pinned_bo == NULL || 1214 error->active_bo_count == NULL || 1215 error->pinned_bo_count == NULL) { 1216 kfree(error->active_bo); 1217 kfree(error->active_bo_count); 1218 kfree(error->pinned_bo); 1219 kfree(error->pinned_bo_count); 1220 1221 error->active_bo = NULL; 1222 error->active_bo_count = NULL; 1223 error->pinned_bo = NULL; 1224 error->pinned_bo_count = NULL; 1225 } else { 1226 list_for_each_entry(vm, &dev_priv->vm_list, global_link) 1227 i915_gem_capture_vm(dev_priv, error, vm, i++); 1228 1229 error->vm_count = cnt; 1230 } 1231 } 1232 1233 /* Capture all registers which don't fit into another category. */ 1234 static void i915_capture_reg_state(struct drm_i915_private *dev_priv, 1235 struct drm_i915_error_state *error) 1236 { 1237 struct drm_device *dev = dev_priv->dev; 1238 int i; 1239 1240 /* General organization 1241 * 1. Registers specific to a single generation 1242 * 2. Registers which belong to multiple generations 1243 * 3. Feature specific registers. 1244 * 4. Everything else 1245 * Please try to follow the order. 1246 */ 1247 1248 /* 1: Registers specific to a single generation */ 1249 if (IS_VALLEYVIEW(dev)) { 1250 error->gtier[0] = I915_READ(GTIER); 1251 error->ier = I915_READ(VLV_IER); 1252 error->forcewake = I915_READ_FW(FORCEWAKE_VLV); 1253 } 1254 1255 if (IS_GEN7(dev)) 1256 error->err_int = I915_READ(GEN7_ERR_INT); 1257 1258 if (INTEL_INFO(dev)->gen >= 8) { 1259 error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0); 1260 error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1); 1261 } 1262 1263 if (IS_GEN6(dev)) { 1264 error->forcewake = I915_READ_FW(FORCEWAKE); 1265 error->gab_ctl = I915_READ(GAB_CTL); 1266 error->gfx_mode = I915_READ(GFX_MODE); 1267 } 1268 1269 /* 2: Registers which belong to multiple generations */ 1270 if (INTEL_INFO(dev)->gen >= 7) 1271 error->forcewake = I915_READ_FW(FORCEWAKE_MT); 1272 1273 if (INTEL_INFO(dev)->gen >= 6) { 1274 error->derrmr = I915_READ(DERRMR); 1275 error->error = I915_READ(ERROR_GEN6); 1276 error->done_reg = I915_READ(DONE_REG); 1277 } 1278 1279 /* 3: Feature specific registers */ 1280 if (IS_GEN6(dev) || IS_GEN7(dev)) { 1281 error->gam_ecochk = I915_READ(GAM_ECOCHK); 1282 error->gac_eco = I915_READ(GAC_ECO_BITS); 1283 } 1284 1285 /* 4: Everything else */ 1286 if (HAS_HW_CONTEXTS(dev)) 1287 error->ccid = I915_READ(CCID); 1288 1289 if (INTEL_INFO(dev)->gen >= 8) { 1290 error->ier = I915_READ(GEN8_DE_MISC_IER); 1291 for (i = 0; i < 4; i++) 1292 error->gtier[i] = I915_READ(GEN8_GT_IER(i)); 1293 } else if (HAS_PCH_SPLIT(dev)) { 1294 error->ier = I915_READ(DEIER); 1295 error->gtier[0] = I915_READ(GTIER); 1296 } else if (IS_GEN2(dev)) { 1297 error->ier = I915_READ16(IER); 1298 } else if (!IS_VALLEYVIEW(dev)) { 1299 error->ier = I915_READ(IER); 1300 } 1301 error->eir = I915_READ(EIR); 1302 error->pgtbl_er = I915_READ(PGTBL_ER); 1303 1304 i915_get_extra_instdone(dev, error->extra_instdone); 1305 } 1306 1307 static void i915_error_capture_msg(struct drm_device *dev, 1308 struct drm_i915_error_state *error, 1309 u32 engine_mask, 1310 const char *error_msg) 1311 { 1312 struct drm_i915_private *dev_priv = dev->dev_private; 1313 u32 ecode; 1314 int ring_id = -1, len; 1315 1316 ecode = i915_error_generate_code(dev_priv, error, &ring_id); 1317 1318 len = scnprintf(error->error_msg, sizeof(error->error_msg), 1319 "GPU HANG: ecode %d:%d:0x%08x", 1320 INTEL_INFO(dev)->gen, ring_id, ecode); 1321 1322 if (ring_id != -1 && error->ring[ring_id].pid != -1) 1323 len += scnprintf(error->error_msg + len, 1324 sizeof(error->error_msg) - len, 1325 ", in %s [%d]", 1326 error->ring[ring_id].comm, 1327 error->ring[ring_id].pid); 1328 1329 scnprintf(error->error_msg + len, sizeof(error->error_msg) - len, 1330 ", reason: %s, action: %s", 1331 error_msg, 1332 engine_mask ? "reset" : "continue"); 1333 } 1334 1335 static void i915_capture_gen_state(struct drm_i915_private *dev_priv, 1336 struct drm_i915_error_state *error) 1337 { 1338 error->iommu = -1; 1339 #ifdef CONFIG_INTEL_IOMMU 1340 error->iommu = intel_iommu_gfx_mapped; 1341 #endif 1342 error->reset_count = i915_reset_count(&dev_priv->gpu_error); 1343 error->suspend_count = dev_priv->suspend_count; 1344 } 1345 1346 /** 1347 * i915_capture_error_state - capture an error record for later analysis 1348 * @dev: drm device 1349 * 1350 * Should be called when an error is detected (either a hang or an error 1351 * interrupt) to capture error state from the time of the error. Fills 1352 * out a structure which becomes available in debugfs for user level tools 1353 * to pick up. 1354 */ 1355 void i915_capture_error_state(struct drm_device *dev, u32 engine_mask, 1356 const char *error_msg) 1357 { 1358 static bool warned; 1359 struct drm_i915_private *dev_priv = dev->dev_private; 1360 struct drm_i915_error_state *error; 1361 unsigned long flags; 1362 1363 /* Account for pipe specific data like PIPE*STAT */ 1364 error = kzalloc(sizeof(*error), GFP_ATOMIC); 1365 if (!error) { 1366 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); 1367 return; 1368 } 1369 1370 kref_init(&error->ref); 1371 1372 i915_capture_gen_state(dev_priv, error); 1373 i915_capture_reg_state(dev_priv, error); 1374 i915_gem_capture_buffers(dev_priv, error); 1375 i915_gem_record_fences(dev, error); 1376 i915_gem_record_rings(dev, error); 1377 1378 do_gettimeofday(&error->time); 1379 1380 error->overlay = intel_overlay_capture_error_state(dev); 1381 error->display = intel_display_capture_error_state(dev); 1382 1383 i915_error_capture_msg(dev, error, engine_mask, error_msg); 1384 DRM_INFO("%s\n", error->error_msg); 1385 1386 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); 1387 if (dev_priv->gpu_error.first_error == NULL) { 1388 dev_priv->gpu_error.first_error = error; 1389 error = NULL; 1390 } 1391 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); 1392 1393 if (error) { 1394 i915_error_state_free(&error->ref); 1395 return; 1396 } 1397 1398 if (!warned) { 1399 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n"); 1400 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n"); 1401 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n"); 1402 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n"); 1403 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", dev->primary->index); 1404 warned = true; 1405 } 1406 } 1407 1408 void i915_error_state_get(struct drm_device *dev, 1409 struct i915_error_state_file_priv *error_priv) 1410 { 1411 struct drm_i915_private *dev_priv = dev->dev_private; 1412 1413 spin_lock_irq(&dev_priv->gpu_error.lock); 1414 error_priv->error = dev_priv->gpu_error.first_error; 1415 if (error_priv->error) 1416 kref_get(&error_priv->error->ref); 1417 spin_unlock_irq(&dev_priv->gpu_error.lock); 1418 1419 } 1420 1421 void i915_error_state_put(struct i915_error_state_file_priv *error_priv) 1422 { 1423 if (error_priv->error) 1424 kref_put(&error_priv->error->ref, i915_error_state_free); 1425 } 1426 1427 void i915_destroy_error_state(struct drm_device *dev) 1428 { 1429 struct drm_i915_private *dev_priv = dev->dev_private; 1430 struct drm_i915_error_state *error; 1431 1432 spin_lock_irq(&dev_priv->gpu_error.lock); 1433 error = dev_priv->gpu_error.first_error; 1434 dev_priv->gpu_error.first_error = NULL; 1435 spin_unlock_irq(&dev_priv->gpu_error.lock); 1436 1437 if (error) 1438 kref_put(&error->ref, i915_error_state_free); 1439 } 1440 1441 const char *i915_cache_level_str(struct drm_i915_private *i915, int type) 1442 { 1443 switch (type) { 1444 case I915_CACHE_NONE: return " uncached"; 1445 case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped"; 1446 case I915_CACHE_L3_LLC: return " L3+LLC"; 1447 case I915_CACHE_WT: return " WT"; 1448 default: return ""; 1449 } 1450 } 1451 1452 /* NB: please notice the memset */ 1453 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone) 1454 { 1455 struct drm_i915_private *dev_priv = dev->dev_private; 1456 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG); 1457 1458 if (IS_GEN2(dev) || IS_GEN3(dev)) 1459 instdone[0] = I915_READ(GEN2_INSTDONE); 1460 else if (IS_GEN4(dev) || IS_GEN5(dev) || IS_GEN6(dev)) { 1461 instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE)); 1462 instdone[1] = I915_READ(GEN4_INSTDONE1); 1463 } else if (INTEL_INFO(dev)->gen >= 7) { 1464 instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE)); 1465 instdone[1] = I915_READ(GEN7_SC_INSTDONE); 1466 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE); 1467 instdone[3] = I915_READ(GEN7_ROW_INSTDONE); 1468 } 1469 } 1470