1 /* 2 * Copyright (c) 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * Mika Kuoppala <mika.kuoppala@intel.com> 27 * 28 */ 29 30 #include <linux/ascii85.h> 31 #include <linux/nmi.h> 32 #include <linux/pagevec.h> 33 #include <linux/scatterlist.h> 34 #include <linux/utsname.h> 35 #include <linux/zlib.h> 36 37 #include <drm/drm_print.h> 38 39 #include "display/intel_atomic.h" 40 #include "display/intel_csr.h" 41 #include "display/intel_overlay.h" 42 43 #include "gem/i915_gem_context.h" 44 #include "gem/i915_gem_lmem.h" 45 #include "gt/intel_gt_pm.h" 46 47 #include "i915_drv.h" 48 #include "i915_gpu_error.h" 49 #include "i915_memcpy.h" 50 #include "i915_scatterlist.h" 51 52 #define ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN) 53 #define ATOMIC_MAYFAIL (GFP_ATOMIC | __GFP_NOWARN) 54 55 static void __sg_set_buf(struct scatterlist *sg, 56 void *addr, unsigned int len, loff_t it) 57 { 58 sg->page_link = (unsigned long)virt_to_page(addr); 59 sg->offset = offset_in_page(addr); 60 sg->length = len; 61 sg->dma_address = it; 62 } 63 64 static bool __i915_error_grow(struct drm_i915_error_state_buf *e, size_t len) 65 { 66 if (!len) 67 return false; 68 69 if (e->bytes + len + 1 <= e->size) 70 return true; 71 72 if (e->bytes) { 73 __sg_set_buf(e->cur++, e->buf, e->bytes, e->iter); 74 e->iter += e->bytes; 75 e->buf = NULL; 76 e->bytes = 0; 77 } 78 79 if (e->cur == e->end) { 80 struct scatterlist *sgl; 81 82 sgl = (typeof(sgl))__get_free_page(ALLOW_FAIL); 83 if (!sgl) { 84 e->err = -ENOMEM; 85 return false; 86 } 87 88 if (e->cur) { 89 e->cur->offset = 0; 90 e->cur->length = 0; 91 e->cur->page_link = 92 (unsigned long)sgl | SG_CHAIN; 93 } else { 94 e->sgl = sgl; 95 } 96 97 e->cur = sgl; 98 e->end = sgl + SG_MAX_SINGLE_ALLOC - 1; 99 } 100 101 e->size = ALIGN(len + 1, SZ_64K); 102 e->buf = kmalloc(e->size, ALLOW_FAIL); 103 if (!e->buf) { 104 e->size = PAGE_ALIGN(len + 1); 105 e->buf = kmalloc(e->size, GFP_KERNEL); 106 } 107 if (!e->buf) { 108 e->err = -ENOMEM; 109 return false; 110 } 111 112 return true; 113 } 114 115 __printf(2, 0) 116 static void i915_error_vprintf(struct drm_i915_error_state_buf *e, 117 const char *fmt, va_list args) 118 { 119 va_list ap; 120 int len; 121 122 if (e->err) 123 return; 124 125 va_copy(ap, args); 126 len = vsnprintf(NULL, 0, fmt, ap); 127 va_end(ap); 128 if (len <= 0) { 129 e->err = len; 130 return; 131 } 132 133 if (!__i915_error_grow(e, len)) 134 return; 135 136 GEM_BUG_ON(e->bytes >= e->size); 137 len = vscnprintf(e->buf + e->bytes, e->size - e->bytes, fmt, args); 138 if (len < 0) { 139 e->err = len; 140 return; 141 } 142 e->bytes += len; 143 } 144 145 static void i915_error_puts(struct drm_i915_error_state_buf *e, const char *str) 146 { 147 unsigned len; 148 149 if (e->err || !str) 150 return; 151 152 len = strlen(str); 153 if (!__i915_error_grow(e, len)) 154 return; 155 156 GEM_BUG_ON(e->bytes + len > e->size); 157 memcpy(e->buf + e->bytes, str, len); 158 e->bytes += len; 159 } 160 161 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) 162 #define err_puts(e, s) i915_error_puts(e, s) 163 164 static void __i915_printfn_error(struct drm_printer *p, struct va_format *vaf) 165 { 166 i915_error_vprintf(p->arg, vaf->fmt, *vaf->va); 167 } 168 169 static inline struct drm_printer 170 i915_error_printer(struct drm_i915_error_state_buf *e) 171 { 172 struct drm_printer p = { 173 .printfn = __i915_printfn_error, 174 .arg = e, 175 }; 176 return p; 177 } 178 179 /* single threaded page allocator with a reserved stash for emergencies */ 180 static void pool_fini(struct pagevec *pv) 181 { 182 pagevec_release(pv); 183 } 184 185 static int pool_refill(struct pagevec *pv, gfp_t gfp) 186 { 187 while (pagevec_space(pv)) { 188 struct page *p; 189 190 p = alloc_page(gfp); 191 if (!p) 192 return -ENOMEM; 193 194 pagevec_add(pv, p); 195 } 196 197 return 0; 198 } 199 200 static int pool_init(struct pagevec *pv, gfp_t gfp) 201 { 202 int err; 203 204 pagevec_init(pv); 205 206 err = pool_refill(pv, gfp); 207 if (err) 208 pool_fini(pv); 209 210 return err; 211 } 212 213 static void *pool_alloc(struct pagevec *pv, gfp_t gfp) 214 { 215 struct page *p; 216 217 p = alloc_page(gfp); 218 if (!p && pagevec_count(pv)) 219 p = pv->pages[--pv->nr]; 220 221 return p ? page_address(p) : NULL; 222 } 223 224 static void pool_free(struct pagevec *pv, void *addr) 225 { 226 struct page *p = virt_to_page(addr); 227 228 if (pagevec_space(pv)) 229 pagevec_add(pv, p); 230 else 231 __free_page(p); 232 } 233 234 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR 235 236 struct i915_vma_compress { 237 struct pagevec pool; 238 struct z_stream_s zstream; 239 void *tmp; 240 }; 241 242 static bool compress_init(struct i915_vma_compress *c) 243 { 244 struct z_stream_s *zstream = &c->zstream; 245 246 if (pool_init(&c->pool, ALLOW_FAIL)) 247 return false; 248 249 zstream->workspace = 250 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL), 251 ALLOW_FAIL); 252 if (!zstream->workspace) { 253 pool_fini(&c->pool); 254 return false; 255 } 256 257 c->tmp = NULL; 258 if (i915_has_memcpy_from_wc()) 259 c->tmp = pool_alloc(&c->pool, ALLOW_FAIL); 260 261 return true; 262 } 263 264 static bool compress_start(struct i915_vma_compress *c) 265 { 266 struct z_stream_s *zstream = &c->zstream; 267 void *workspace = zstream->workspace; 268 269 memset(zstream, 0, sizeof(*zstream)); 270 zstream->workspace = workspace; 271 272 return zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) == Z_OK; 273 } 274 275 static void *compress_next_page(struct i915_vma_compress *c, 276 struct i915_vma_coredump *dst) 277 { 278 void *page; 279 280 if (dst->page_count >= dst->num_pages) 281 return ERR_PTR(-ENOSPC); 282 283 page = pool_alloc(&c->pool, ALLOW_FAIL); 284 if (!page) 285 return ERR_PTR(-ENOMEM); 286 287 return dst->pages[dst->page_count++] = page; 288 } 289 290 static int compress_page(struct i915_vma_compress *c, 291 void *src, 292 struct i915_vma_coredump *dst, 293 bool wc) 294 { 295 struct z_stream_s *zstream = &c->zstream; 296 297 zstream->next_in = src; 298 if (wc && c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE)) 299 zstream->next_in = c->tmp; 300 zstream->avail_in = PAGE_SIZE; 301 302 do { 303 if (zstream->avail_out == 0) { 304 zstream->next_out = compress_next_page(c, dst); 305 if (IS_ERR(zstream->next_out)) 306 return PTR_ERR(zstream->next_out); 307 308 zstream->avail_out = PAGE_SIZE; 309 } 310 311 if (zlib_deflate(zstream, Z_NO_FLUSH) != Z_OK) 312 return -EIO; 313 } while (zstream->avail_in); 314 315 /* Fallback to uncompressed if we increase size? */ 316 if (0 && zstream->total_out > zstream->total_in) 317 return -E2BIG; 318 319 return 0; 320 } 321 322 static int compress_flush(struct i915_vma_compress *c, 323 struct i915_vma_coredump *dst) 324 { 325 struct z_stream_s *zstream = &c->zstream; 326 327 do { 328 switch (zlib_deflate(zstream, Z_FINISH)) { 329 case Z_OK: /* more space requested */ 330 zstream->next_out = compress_next_page(c, dst); 331 if (IS_ERR(zstream->next_out)) 332 return PTR_ERR(zstream->next_out); 333 334 zstream->avail_out = PAGE_SIZE; 335 break; 336 337 case Z_STREAM_END: 338 goto end; 339 340 default: /* any error */ 341 return -EIO; 342 } 343 } while (1); 344 345 end: 346 memset(zstream->next_out, 0, zstream->avail_out); 347 dst->unused = zstream->avail_out; 348 return 0; 349 } 350 351 static void compress_finish(struct i915_vma_compress *c) 352 { 353 zlib_deflateEnd(&c->zstream); 354 } 355 356 static void compress_fini(struct i915_vma_compress *c) 357 { 358 kfree(c->zstream.workspace); 359 if (c->tmp) 360 pool_free(&c->pool, c->tmp); 361 pool_fini(&c->pool); 362 } 363 364 static void err_compression_marker(struct drm_i915_error_state_buf *m) 365 { 366 err_puts(m, ":"); 367 } 368 369 #else 370 371 struct i915_vma_compress { 372 struct pagevec pool; 373 }; 374 375 static bool compress_init(struct i915_vma_compress *c) 376 { 377 return pool_init(&c->pool, ALLOW_FAIL) == 0; 378 } 379 380 static bool compress_start(struct i915_vma_compress *c) 381 { 382 return true; 383 } 384 385 static int compress_page(struct i915_vma_compress *c, 386 void *src, 387 struct i915_vma_coredump *dst, 388 bool wc) 389 { 390 void *ptr; 391 392 ptr = pool_alloc(&c->pool, ALLOW_FAIL); 393 if (!ptr) 394 return -ENOMEM; 395 396 if (!(wc && i915_memcpy_from_wc(ptr, src, PAGE_SIZE))) 397 memcpy(ptr, src, PAGE_SIZE); 398 dst->pages[dst->page_count++] = ptr; 399 400 return 0; 401 } 402 403 static int compress_flush(struct i915_vma_compress *c, 404 struct i915_vma_coredump *dst) 405 { 406 return 0; 407 } 408 409 static void compress_finish(struct i915_vma_compress *c) 410 { 411 } 412 413 static void compress_fini(struct i915_vma_compress *c) 414 { 415 pool_fini(&c->pool); 416 } 417 418 static void err_compression_marker(struct drm_i915_error_state_buf *m) 419 { 420 err_puts(m, "~"); 421 } 422 423 #endif 424 425 static void error_print_instdone(struct drm_i915_error_state_buf *m, 426 const struct intel_engine_coredump *ee) 427 { 428 const struct sseu_dev_info *sseu = &RUNTIME_INFO(m->i915)->sseu; 429 int slice; 430 int subslice; 431 432 err_printf(m, " INSTDONE: 0x%08x\n", 433 ee->instdone.instdone); 434 435 if (ee->engine->class != RENDER_CLASS || INTEL_GEN(m->i915) <= 3) 436 return; 437 438 err_printf(m, " SC_INSTDONE: 0x%08x\n", 439 ee->instdone.slice_common); 440 441 if (INTEL_GEN(m->i915) <= 6) 442 return; 443 444 for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice) 445 err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n", 446 slice, subslice, 447 ee->instdone.sampler[slice][subslice]); 448 449 for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice) 450 err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n", 451 slice, subslice, 452 ee->instdone.row[slice][subslice]); 453 454 if (INTEL_GEN(m->i915) < 12) 455 return; 456 457 err_printf(m, " SC_INSTDONE_EXTRA: 0x%08x\n", 458 ee->instdone.slice_common_extra[0]); 459 err_printf(m, " SC_INSTDONE_EXTRA2: 0x%08x\n", 460 ee->instdone.slice_common_extra[1]); 461 } 462 463 static void error_print_request(struct drm_i915_error_state_buf *m, 464 const char *prefix, 465 const struct i915_request_coredump *erq) 466 { 467 if (!erq->seqno) 468 return; 469 470 err_printf(m, "%s pid %d, seqno %8x:%08x%s%s, prio %d, start %08x, head %08x, tail %08x\n", 471 prefix, erq->pid, erq->context, erq->seqno, 472 test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, 473 &erq->flags) ? "!" : "", 474 test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, 475 &erq->flags) ? "+" : "", 476 erq->sched_attr.priority, 477 erq->start, erq->head, erq->tail); 478 } 479 480 static void error_print_context(struct drm_i915_error_state_buf *m, 481 const char *header, 482 const struct i915_gem_context_coredump *ctx) 483 { 484 const u32 period = RUNTIME_INFO(m->i915)->cs_timestamp_period_ns; 485 486 err_printf(m, "%s%s[%d] prio %d, guilty %d active %d, runtime total %lluns, avg %lluns\n", 487 header, ctx->comm, ctx->pid, ctx->sched_attr.priority, 488 ctx->guilty, ctx->active, 489 ctx->total_runtime * period, 490 mul_u32_u32(ctx->avg_runtime, period)); 491 } 492 493 static struct i915_vma_coredump * 494 __find_vma(struct i915_vma_coredump *vma, const char *name) 495 { 496 while (vma) { 497 if (strcmp(vma->name, name) == 0) 498 return vma; 499 vma = vma->next; 500 } 501 502 return NULL; 503 } 504 505 static struct i915_vma_coredump * 506 find_batch(const struct intel_engine_coredump *ee) 507 { 508 return __find_vma(ee->vma, "batch"); 509 } 510 511 static void error_print_engine(struct drm_i915_error_state_buf *m, 512 const struct intel_engine_coredump *ee) 513 { 514 struct i915_vma_coredump *batch; 515 int n; 516 517 err_printf(m, "%s command stream:\n", ee->engine->name); 518 err_printf(m, " CCID: 0x%08x\n", ee->ccid); 519 err_printf(m, " START: 0x%08x\n", ee->start); 520 err_printf(m, " HEAD: 0x%08x [0x%08x]\n", ee->head, ee->rq_head); 521 err_printf(m, " TAIL: 0x%08x [0x%08x, 0x%08x]\n", 522 ee->tail, ee->rq_post, ee->rq_tail); 523 err_printf(m, " CTL: 0x%08x\n", ee->ctl); 524 err_printf(m, " MODE: 0x%08x\n", ee->mode); 525 err_printf(m, " HWS: 0x%08x\n", ee->hws); 526 err_printf(m, " ACTHD: 0x%08x %08x\n", 527 (u32)(ee->acthd>>32), (u32)ee->acthd); 528 err_printf(m, " IPEIR: 0x%08x\n", ee->ipeir); 529 err_printf(m, " IPEHR: 0x%08x\n", ee->ipehr); 530 err_printf(m, " ESR: 0x%08x\n", ee->esr); 531 532 error_print_instdone(m, ee); 533 534 batch = find_batch(ee); 535 if (batch) { 536 u64 start = batch->gtt_offset; 537 u64 end = start + batch->gtt_size; 538 539 err_printf(m, " batch: [0x%08x_%08x, 0x%08x_%08x]\n", 540 upper_32_bits(start), lower_32_bits(start), 541 upper_32_bits(end), lower_32_bits(end)); 542 } 543 if (INTEL_GEN(m->i915) >= 4) { 544 err_printf(m, " BBADDR: 0x%08x_%08x\n", 545 (u32)(ee->bbaddr>>32), (u32)ee->bbaddr); 546 err_printf(m, " BB_STATE: 0x%08x\n", ee->bbstate); 547 err_printf(m, " INSTPS: 0x%08x\n", ee->instps); 548 } 549 err_printf(m, " INSTPM: 0x%08x\n", ee->instpm); 550 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr), 551 lower_32_bits(ee->faddr)); 552 if (INTEL_GEN(m->i915) >= 6) { 553 err_printf(m, " RC PSMI: 0x%08x\n", ee->rc_psmi); 554 err_printf(m, " FAULT_REG: 0x%08x\n", ee->fault_reg); 555 } 556 if (HAS_PPGTT(m->i915)) { 557 err_printf(m, " GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode); 558 559 if (INTEL_GEN(m->i915) >= 8) { 560 int i; 561 for (i = 0; i < 4; i++) 562 err_printf(m, " PDP%d: 0x%016llx\n", 563 i, ee->vm_info.pdp[i]); 564 } else { 565 err_printf(m, " PP_DIR_BASE: 0x%08x\n", 566 ee->vm_info.pp_dir_base); 567 } 568 } 569 err_printf(m, " engine reset count: %u\n", ee->reset_count); 570 571 for (n = 0; n < ee->num_ports; n++) { 572 err_printf(m, " ELSP[%d]:", n); 573 error_print_request(m, " ", &ee->execlist[n]); 574 } 575 576 error_print_context(m, " Active context: ", &ee->context); 577 } 578 579 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) 580 { 581 va_list args; 582 583 va_start(args, f); 584 i915_error_vprintf(e, f, args); 585 va_end(args); 586 } 587 588 static void print_error_vma(struct drm_i915_error_state_buf *m, 589 const struct intel_engine_cs *engine, 590 const struct i915_vma_coredump *vma) 591 { 592 char out[ASCII85_BUFSZ]; 593 int page; 594 595 if (!vma) 596 return; 597 598 err_printf(m, "%s --- %s = 0x%08x %08x\n", 599 engine ? engine->name : "global", vma->name, 600 upper_32_bits(vma->gtt_offset), 601 lower_32_bits(vma->gtt_offset)); 602 603 if (vma->gtt_page_sizes > I915_GTT_PAGE_SIZE_4K) 604 err_printf(m, "gtt_page_sizes = 0x%08x\n", vma->gtt_page_sizes); 605 606 err_compression_marker(m); 607 for (page = 0; page < vma->page_count; page++) { 608 int i, len; 609 610 len = PAGE_SIZE; 611 if (page == vma->page_count - 1) 612 len -= vma->unused; 613 len = ascii85_encode_len(len); 614 615 for (i = 0; i < len; i++) 616 err_puts(m, ascii85_encode(vma->pages[page][i], out)); 617 } 618 err_puts(m, "\n"); 619 } 620 621 static void err_print_capabilities(struct drm_i915_error_state_buf *m, 622 const struct intel_device_info *info, 623 const struct intel_runtime_info *runtime, 624 const struct intel_driver_caps *caps) 625 { 626 struct drm_printer p = i915_error_printer(m); 627 628 intel_device_info_print_static(info, &p); 629 intel_device_info_print_runtime(runtime, &p); 630 intel_device_info_print_topology(&runtime->sseu, &p); 631 intel_driver_caps_print(caps, &p); 632 } 633 634 static void err_print_params(struct drm_i915_error_state_buf *m, 635 const struct i915_params *params) 636 { 637 struct drm_printer p = i915_error_printer(m); 638 639 i915_params_dump(params, &p); 640 } 641 642 static void err_print_pciid(struct drm_i915_error_state_buf *m, 643 struct drm_i915_private *i915) 644 { 645 struct pci_dev *pdev = i915->drm.pdev; 646 647 err_printf(m, "PCI ID: 0x%04x\n", pdev->device); 648 err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision); 649 err_printf(m, "PCI Subsystem: %04x:%04x\n", 650 pdev->subsystem_vendor, 651 pdev->subsystem_device); 652 } 653 654 static void err_print_uc(struct drm_i915_error_state_buf *m, 655 const struct intel_uc_coredump *error_uc) 656 { 657 struct drm_printer p = i915_error_printer(m); 658 659 intel_uc_fw_dump(&error_uc->guc_fw, &p); 660 intel_uc_fw_dump(&error_uc->huc_fw, &p); 661 print_error_vma(m, NULL, error_uc->guc_log); 662 } 663 664 static void err_free_sgl(struct scatterlist *sgl) 665 { 666 while (sgl) { 667 struct scatterlist *sg; 668 669 for (sg = sgl; !sg_is_chain(sg); sg++) { 670 kfree(sg_virt(sg)); 671 if (sg_is_last(sg)) 672 break; 673 } 674 675 sg = sg_is_last(sg) ? NULL : sg_chain_ptr(sg); 676 free_page((unsigned long)sgl); 677 sgl = sg; 678 } 679 } 680 681 static void err_print_gt(struct drm_i915_error_state_buf *m, 682 struct intel_gt_coredump *gt) 683 { 684 const struct intel_engine_coredump *ee; 685 int i; 686 687 err_printf(m, "GT awake: %s\n", yesno(gt->awake)); 688 err_printf(m, "EIR: 0x%08x\n", gt->eir); 689 err_printf(m, "IER: 0x%08x\n", gt->ier); 690 for (i = 0; i < gt->ngtier; i++) 691 err_printf(m, "GTIER[%d]: 0x%08x\n", i, gt->gtier[i]); 692 err_printf(m, "PGTBL_ER: 0x%08x\n", gt->pgtbl_er); 693 err_printf(m, "FORCEWAKE: 0x%08x\n", gt->forcewake); 694 err_printf(m, "DERRMR: 0x%08x\n", gt->derrmr); 695 696 for (i = 0; i < gt->nfence; i++) 697 err_printf(m, " fence[%d] = %08llx\n", i, gt->fence[i]); 698 699 if (IS_GEN_RANGE(m->i915, 6, 11)) { 700 err_printf(m, "ERROR: 0x%08x\n", gt->error); 701 err_printf(m, "DONE_REG: 0x%08x\n", gt->done_reg); 702 } 703 704 if (INTEL_GEN(m->i915) >= 8) 705 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n", 706 gt->fault_data1, gt->fault_data0); 707 708 if (IS_GEN(m->i915, 7)) 709 err_printf(m, "ERR_INT: 0x%08x\n", gt->err_int); 710 711 if (IS_GEN_RANGE(m->i915, 8, 11)) 712 err_printf(m, "GTT_CACHE_EN: 0x%08x\n", gt->gtt_cache); 713 714 if (IS_GEN(m->i915, 12)) 715 err_printf(m, "AUX_ERR_DBG: 0x%08x\n", gt->aux_err); 716 717 if (INTEL_GEN(m->i915) >= 12) { 718 int i; 719 720 for (i = 0; i < GEN12_SFC_DONE_MAX; i++) 721 err_printf(m, " SFC_DONE[%d]: 0x%08x\n", i, 722 gt->sfc_done[i]); 723 724 err_printf(m, " GAM_DONE: 0x%08x\n", gt->gam_done); 725 } 726 727 for (ee = gt->engine; ee; ee = ee->next) { 728 const struct i915_vma_coredump *vma; 729 730 error_print_engine(m, ee); 731 for (vma = ee->vma; vma; vma = vma->next) 732 print_error_vma(m, ee->engine, vma); 733 } 734 735 if (gt->uc) 736 err_print_uc(m, gt->uc); 737 } 738 739 static void __err_print_to_sgl(struct drm_i915_error_state_buf *m, 740 struct i915_gpu_coredump *error) 741 { 742 const struct intel_engine_coredump *ee; 743 struct timespec64 ts; 744 745 if (*error->error_msg) 746 err_printf(m, "%s\n", error->error_msg); 747 err_printf(m, "Kernel: %s %s\n", 748 init_utsname()->release, 749 init_utsname()->machine); 750 err_printf(m, "Driver: %s\n", DRIVER_DATE); 751 ts = ktime_to_timespec64(error->time); 752 err_printf(m, "Time: %lld s %ld us\n", 753 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 754 ts = ktime_to_timespec64(error->boottime); 755 err_printf(m, "Boottime: %lld s %ld us\n", 756 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 757 ts = ktime_to_timespec64(error->uptime); 758 err_printf(m, "Uptime: %lld s %ld us\n", 759 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 760 err_printf(m, "Capture: %lu jiffies; %d ms ago\n", 761 error->capture, jiffies_to_msecs(jiffies - error->capture)); 762 763 for (ee = error->gt ? error->gt->engine : NULL; ee; ee = ee->next) 764 err_printf(m, "Active process (on ring %s): %s [%d]\n", 765 ee->engine->name, 766 ee->context.comm, 767 ee->context.pid); 768 769 err_printf(m, "Reset count: %u\n", error->reset_count); 770 err_printf(m, "Suspend count: %u\n", error->suspend_count); 771 err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform)); 772 err_printf(m, "Subplatform: 0x%x\n", 773 intel_subplatform(&error->runtime_info, 774 error->device_info.platform)); 775 err_print_pciid(m, m->i915); 776 777 err_printf(m, "IOMMU enabled?: %d\n", error->iommu); 778 779 if (HAS_CSR(m->i915)) { 780 struct intel_csr *csr = &m->i915->csr; 781 782 err_printf(m, "DMC loaded: %s\n", 783 yesno(csr->dmc_payload != NULL)); 784 err_printf(m, "DMC fw version: %d.%d\n", 785 CSR_VERSION_MAJOR(csr->version), 786 CSR_VERSION_MINOR(csr->version)); 787 } 788 789 err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock)); 790 err_printf(m, "PM suspended: %s\n", yesno(error->suspended)); 791 792 if (error->gt) 793 err_print_gt(m, error->gt); 794 795 if (error->overlay) 796 intel_overlay_print_error_state(m, error->overlay); 797 798 if (error->display) 799 intel_display_print_error_state(m, error->display); 800 801 err_print_capabilities(m, &error->device_info, &error->runtime_info, 802 &error->driver_caps); 803 err_print_params(m, &error->params); 804 } 805 806 static int err_print_to_sgl(struct i915_gpu_coredump *error) 807 { 808 struct drm_i915_error_state_buf m; 809 810 if (IS_ERR(error)) 811 return PTR_ERR(error); 812 813 if (READ_ONCE(error->sgl)) 814 return 0; 815 816 memset(&m, 0, sizeof(m)); 817 m.i915 = error->i915; 818 819 __err_print_to_sgl(&m, error); 820 821 if (m.buf) { 822 __sg_set_buf(m.cur++, m.buf, m.bytes, m.iter); 823 m.bytes = 0; 824 m.buf = NULL; 825 } 826 if (m.cur) { 827 GEM_BUG_ON(m.end < m.cur); 828 sg_mark_end(m.cur - 1); 829 } 830 GEM_BUG_ON(m.sgl && !m.cur); 831 832 if (m.err) { 833 err_free_sgl(m.sgl); 834 return m.err; 835 } 836 837 if (cmpxchg(&error->sgl, NULL, m.sgl)) 838 err_free_sgl(m.sgl); 839 840 return 0; 841 } 842 843 ssize_t i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error, 844 char *buf, loff_t off, size_t rem) 845 { 846 struct scatterlist *sg; 847 size_t count; 848 loff_t pos; 849 int err; 850 851 if (!error || !rem) 852 return 0; 853 854 err = err_print_to_sgl(error); 855 if (err) 856 return err; 857 858 sg = READ_ONCE(error->fit); 859 if (!sg || off < sg->dma_address) 860 sg = error->sgl; 861 if (!sg) 862 return 0; 863 864 pos = sg->dma_address; 865 count = 0; 866 do { 867 size_t len, start; 868 869 if (sg_is_chain(sg)) { 870 sg = sg_chain_ptr(sg); 871 GEM_BUG_ON(sg_is_chain(sg)); 872 } 873 874 len = sg->length; 875 if (pos + len <= off) { 876 pos += len; 877 continue; 878 } 879 880 start = sg->offset; 881 if (pos < off) { 882 GEM_BUG_ON(off - pos > len); 883 len -= off - pos; 884 start += off - pos; 885 pos = off; 886 } 887 888 len = min(len, rem); 889 GEM_BUG_ON(!len || len > sg->length); 890 891 memcpy(buf, page_address(sg_page(sg)) + start, len); 892 893 count += len; 894 pos += len; 895 896 buf += len; 897 rem -= len; 898 if (!rem) { 899 WRITE_ONCE(error->fit, sg); 900 break; 901 } 902 } while (!sg_is_last(sg++)); 903 904 return count; 905 } 906 907 static void i915_vma_coredump_free(struct i915_vma_coredump *vma) 908 { 909 while (vma) { 910 struct i915_vma_coredump *next = vma->next; 911 int page; 912 913 for (page = 0; page < vma->page_count; page++) 914 free_page((unsigned long)vma->pages[page]); 915 916 kfree(vma); 917 vma = next; 918 } 919 } 920 921 static void cleanup_params(struct i915_gpu_coredump *error) 922 { 923 i915_params_free(&error->params); 924 } 925 926 static void cleanup_uc(struct intel_uc_coredump *uc) 927 { 928 kfree(uc->guc_fw.path); 929 kfree(uc->huc_fw.path); 930 i915_vma_coredump_free(uc->guc_log); 931 932 kfree(uc); 933 } 934 935 static void cleanup_gt(struct intel_gt_coredump *gt) 936 { 937 while (gt->engine) { 938 struct intel_engine_coredump *ee = gt->engine; 939 940 gt->engine = ee->next; 941 942 i915_vma_coredump_free(ee->vma); 943 kfree(ee); 944 } 945 946 if (gt->uc) 947 cleanup_uc(gt->uc); 948 949 kfree(gt); 950 } 951 952 void __i915_gpu_coredump_free(struct kref *error_ref) 953 { 954 struct i915_gpu_coredump *error = 955 container_of(error_ref, typeof(*error), ref); 956 957 while (error->gt) { 958 struct intel_gt_coredump *gt = error->gt; 959 960 error->gt = gt->next; 961 cleanup_gt(gt); 962 } 963 964 kfree(error->overlay); 965 kfree(error->display); 966 967 cleanup_params(error); 968 969 err_free_sgl(error->sgl); 970 kfree(error); 971 } 972 973 static struct i915_vma_coredump * 974 i915_vma_coredump_create(const struct intel_gt *gt, 975 const struct i915_vma *vma, 976 const char *name, 977 struct i915_vma_compress *compress) 978 { 979 struct i915_ggtt *ggtt = gt->ggtt; 980 const u64 slot = ggtt->error_capture.start; 981 struct i915_vma_coredump *dst; 982 unsigned long num_pages; 983 struct sgt_iter iter; 984 int ret; 985 986 might_sleep(); 987 988 if (!vma || !vma->pages || !compress) 989 return NULL; 990 991 num_pages = min_t(u64, vma->size, vma->obj->base.size) >> PAGE_SHIFT; 992 num_pages = DIV_ROUND_UP(10 * num_pages, 8); /* worstcase zlib growth */ 993 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), ALLOW_FAIL); 994 if (!dst) 995 return NULL; 996 997 if (!compress_start(compress)) { 998 kfree(dst); 999 return NULL; 1000 } 1001 1002 strcpy(dst->name, name); 1003 dst->next = NULL; 1004 1005 dst->gtt_offset = vma->node.start; 1006 dst->gtt_size = vma->node.size; 1007 dst->gtt_page_sizes = vma->page_sizes.gtt; 1008 dst->num_pages = num_pages; 1009 dst->page_count = 0; 1010 dst->unused = 0; 1011 1012 ret = -EINVAL; 1013 if (drm_mm_node_allocated(&ggtt->error_capture)) { 1014 void __iomem *s; 1015 dma_addr_t dma; 1016 1017 for_each_sgt_daddr(dma, iter, vma->pages) { 1018 ggtt->vm.insert_page(&ggtt->vm, dma, slot, 1019 I915_CACHE_NONE, 0); 1020 mb(); 1021 1022 s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE); 1023 ret = compress_page(compress, 1024 (void __force *)s, dst, 1025 true); 1026 io_mapping_unmap(s); 1027 if (ret) 1028 break; 1029 } 1030 } else if (i915_gem_object_is_lmem(vma->obj)) { 1031 struct intel_memory_region *mem = vma->obj->mm.region; 1032 dma_addr_t dma; 1033 1034 for_each_sgt_daddr(dma, iter, vma->pages) { 1035 void __iomem *s; 1036 1037 s = io_mapping_map_wc(&mem->iomap, dma, PAGE_SIZE); 1038 ret = compress_page(compress, 1039 (void __force *)s, dst, 1040 true); 1041 io_mapping_unmap(s); 1042 if (ret) 1043 break; 1044 } 1045 } else { 1046 struct page *page; 1047 1048 for_each_sgt_page(page, iter, vma->pages) { 1049 void *s; 1050 1051 drm_clflush_pages(&page, 1); 1052 1053 s = kmap(page); 1054 ret = compress_page(compress, s, dst, false); 1055 kunmap(page); 1056 1057 drm_clflush_pages(&page, 1); 1058 1059 if (ret) 1060 break; 1061 } 1062 } 1063 1064 if (ret || compress_flush(compress, dst)) { 1065 while (dst->page_count--) 1066 pool_free(&compress->pool, dst->pages[dst->page_count]); 1067 kfree(dst); 1068 dst = NULL; 1069 } 1070 compress_finish(compress); 1071 1072 return dst; 1073 } 1074 1075 static void gt_record_fences(struct intel_gt_coredump *gt) 1076 { 1077 struct i915_ggtt *ggtt = gt->_gt->ggtt; 1078 struct intel_uncore *uncore = gt->_gt->uncore; 1079 int i; 1080 1081 if (INTEL_GEN(uncore->i915) >= 6) { 1082 for (i = 0; i < ggtt->num_fences; i++) 1083 gt->fence[i] = 1084 intel_uncore_read64(uncore, 1085 FENCE_REG_GEN6_LO(i)); 1086 } else if (INTEL_GEN(uncore->i915) >= 4) { 1087 for (i = 0; i < ggtt->num_fences; i++) 1088 gt->fence[i] = 1089 intel_uncore_read64(uncore, 1090 FENCE_REG_965_LO(i)); 1091 } else { 1092 for (i = 0; i < ggtt->num_fences; i++) 1093 gt->fence[i] = 1094 intel_uncore_read(uncore, FENCE_REG(i)); 1095 } 1096 gt->nfence = i; 1097 } 1098 1099 static void engine_record_registers(struct intel_engine_coredump *ee) 1100 { 1101 const struct intel_engine_cs *engine = ee->engine; 1102 struct drm_i915_private *i915 = engine->i915; 1103 1104 if (INTEL_GEN(i915) >= 6) { 1105 ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL); 1106 1107 if (INTEL_GEN(i915) >= 12) 1108 ee->fault_reg = intel_uncore_read(engine->uncore, 1109 GEN12_RING_FAULT_REG); 1110 else if (INTEL_GEN(i915) >= 8) 1111 ee->fault_reg = intel_uncore_read(engine->uncore, 1112 GEN8_RING_FAULT_REG); 1113 else 1114 ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine); 1115 } 1116 1117 if (INTEL_GEN(i915) >= 4) { 1118 ee->esr = ENGINE_READ(engine, RING_ESR); 1119 ee->faddr = ENGINE_READ(engine, RING_DMA_FADD); 1120 ee->ipeir = ENGINE_READ(engine, RING_IPEIR); 1121 ee->ipehr = ENGINE_READ(engine, RING_IPEHR); 1122 ee->instps = ENGINE_READ(engine, RING_INSTPS); 1123 ee->bbaddr = ENGINE_READ(engine, RING_BBADDR); 1124 ee->ccid = ENGINE_READ(engine, CCID); 1125 if (INTEL_GEN(i915) >= 8) { 1126 ee->faddr |= (u64)ENGINE_READ(engine, RING_DMA_FADD_UDW) << 32; 1127 ee->bbaddr |= (u64)ENGINE_READ(engine, RING_BBADDR_UDW) << 32; 1128 } 1129 ee->bbstate = ENGINE_READ(engine, RING_BBSTATE); 1130 } else { 1131 ee->faddr = ENGINE_READ(engine, DMA_FADD_I8XX); 1132 ee->ipeir = ENGINE_READ(engine, IPEIR); 1133 ee->ipehr = ENGINE_READ(engine, IPEHR); 1134 } 1135 1136 intel_engine_get_instdone(engine, &ee->instdone); 1137 1138 ee->instpm = ENGINE_READ(engine, RING_INSTPM); 1139 ee->acthd = intel_engine_get_active_head(engine); 1140 ee->start = ENGINE_READ(engine, RING_START); 1141 ee->head = ENGINE_READ(engine, RING_HEAD); 1142 ee->tail = ENGINE_READ(engine, RING_TAIL); 1143 ee->ctl = ENGINE_READ(engine, RING_CTL); 1144 if (INTEL_GEN(i915) > 2) 1145 ee->mode = ENGINE_READ(engine, RING_MI_MODE); 1146 1147 if (!HWS_NEEDS_PHYSICAL(i915)) { 1148 i915_reg_t mmio; 1149 1150 if (IS_GEN(i915, 7)) { 1151 switch (engine->id) { 1152 default: 1153 MISSING_CASE(engine->id); 1154 /* fall through */ 1155 case RCS0: 1156 mmio = RENDER_HWS_PGA_GEN7; 1157 break; 1158 case BCS0: 1159 mmio = BLT_HWS_PGA_GEN7; 1160 break; 1161 case VCS0: 1162 mmio = BSD_HWS_PGA_GEN7; 1163 break; 1164 case VECS0: 1165 mmio = VEBOX_HWS_PGA_GEN7; 1166 break; 1167 } 1168 } else if (IS_GEN(engine->i915, 6)) { 1169 mmio = RING_HWS_PGA_GEN6(engine->mmio_base); 1170 } else { 1171 /* XXX: gen8 returns to sanity */ 1172 mmio = RING_HWS_PGA(engine->mmio_base); 1173 } 1174 1175 ee->hws = intel_uncore_read(engine->uncore, mmio); 1176 } 1177 1178 ee->reset_count = i915_reset_engine_count(&i915->gpu_error, engine); 1179 1180 if (HAS_PPGTT(i915)) { 1181 int i; 1182 1183 ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7); 1184 1185 if (IS_GEN(i915, 6)) { 1186 ee->vm_info.pp_dir_base = 1187 ENGINE_READ(engine, RING_PP_DIR_BASE_READ); 1188 } else if (IS_GEN(i915, 7)) { 1189 ee->vm_info.pp_dir_base = 1190 ENGINE_READ(engine, RING_PP_DIR_BASE); 1191 } else if (INTEL_GEN(i915) >= 8) { 1192 u32 base = engine->mmio_base; 1193 1194 for (i = 0; i < 4; i++) { 1195 ee->vm_info.pdp[i] = 1196 intel_uncore_read(engine->uncore, 1197 GEN8_RING_PDP_UDW(base, i)); 1198 ee->vm_info.pdp[i] <<= 32; 1199 ee->vm_info.pdp[i] |= 1200 intel_uncore_read(engine->uncore, 1201 GEN8_RING_PDP_LDW(base, i)); 1202 } 1203 } 1204 } 1205 } 1206 1207 static void record_request(const struct i915_request *request, 1208 struct i915_request_coredump *erq) 1209 { 1210 const struct i915_gem_context *ctx; 1211 1212 erq->flags = request->fence.flags; 1213 erq->context = request->fence.context; 1214 erq->seqno = request->fence.seqno; 1215 erq->sched_attr = request->sched.attr; 1216 erq->start = i915_ggtt_offset(request->ring->vma); 1217 erq->head = request->head; 1218 erq->tail = request->tail; 1219 1220 erq->pid = 0; 1221 rcu_read_lock(); 1222 ctx = rcu_dereference(request->context->gem_context); 1223 if (ctx) 1224 erq->pid = pid_nr(ctx->pid); 1225 rcu_read_unlock(); 1226 } 1227 1228 static void engine_record_execlists(struct intel_engine_coredump *ee) 1229 { 1230 const struct intel_engine_execlists * const el = &ee->engine->execlists; 1231 struct i915_request * const *port = el->active; 1232 unsigned int n = 0; 1233 1234 while (*port) 1235 record_request(*port++, &ee->execlist[n++]); 1236 1237 ee->num_ports = n; 1238 } 1239 1240 static bool record_context(struct i915_gem_context_coredump *e, 1241 const struct i915_request *rq) 1242 { 1243 struct i915_gem_context *ctx; 1244 struct task_struct *task; 1245 bool simulated; 1246 1247 rcu_read_lock(); 1248 ctx = rcu_dereference(rq->context->gem_context); 1249 if (ctx && !kref_get_unless_zero(&ctx->ref)) 1250 ctx = NULL; 1251 rcu_read_unlock(); 1252 if (!ctx) 1253 return true; 1254 1255 rcu_read_lock(); 1256 task = pid_task(ctx->pid, PIDTYPE_PID); 1257 if (task) { 1258 strcpy(e->comm, task->comm); 1259 e->pid = task->pid; 1260 } 1261 rcu_read_unlock(); 1262 1263 e->sched_attr = ctx->sched; 1264 e->guilty = atomic_read(&ctx->guilty_count); 1265 e->active = atomic_read(&ctx->active_count); 1266 1267 e->total_runtime = rq->context->runtime.total; 1268 e->avg_runtime = ewma_runtime_read(&rq->context->runtime.avg); 1269 1270 simulated = i915_gem_context_no_error_capture(ctx); 1271 1272 i915_gem_context_put(ctx); 1273 return simulated; 1274 } 1275 1276 struct intel_engine_capture_vma { 1277 struct intel_engine_capture_vma *next; 1278 struct i915_vma *vma; 1279 char name[16]; 1280 }; 1281 1282 static struct intel_engine_capture_vma * 1283 capture_vma(struct intel_engine_capture_vma *next, 1284 struct i915_vma *vma, 1285 const char *name, 1286 gfp_t gfp) 1287 { 1288 struct intel_engine_capture_vma *c; 1289 1290 if (!vma) 1291 return next; 1292 1293 c = kmalloc(sizeof(*c), gfp); 1294 if (!c) 1295 return next; 1296 1297 if (!i915_active_acquire_if_busy(&vma->active)) { 1298 kfree(c); 1299 return next; 1300 } 1301 1302 strcpy(c->name, name); 1303 c->vma = i915_vma_get(vma); 1304 1305 c->next = next; 1306 return c; 1307 } 1308 1309 static struct intel_engine_capture_vma * 1310 capture_user(struct intel_engine_capture_vma *capture, 1311 const struct i915_request *rq, 1312 gfp_t gfp) 1313 { 1314 struct i915_capture_list *c; 1315 1316 for (c = rq->capture_list; c; c = c->next) 1317 capture = capture_vma(capture, c->vma, "user", gfp); 1318 1319 return capture; 1320 } 1321 1322 static struct i915_vma_coredump * 1323 capture_object(const struct intel_gt *gt, 1324 struct drm_i915_gem_object *obj, 1325 const char *name, 1326 struct i915_vma_compress *compress) 1327 { 1328 if (obj && i915_gem_object_has_pages(obj)) { 1329 struct i915_vma fake = { 1330 .node = { .start = U64_MAX, .size = obj->base.size }, 1331 .size = obj->base.size, 1332 .pages = obj->mm.pages, 1333 .obj = obj, 1334 }; 1335 1336 return i915_vma_coredump_create(gt, &fake, name, compress); 1337 } else { 1338 return NULL; 1339 } 1340 } 1341 1342 static void add_vma(struct intel_engine_coredump *ee, 1343 struct i915_vma_coredump *vma) 1344 { 1345 if (vma) { 1346 vma->next = ee->vma; 1347 ee->vma = vma; 1348 } 1349 } 1350 1351 struct intel_engine_coredump * 1352 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp) 1353 { 1354 struct intel_engine_coredump *ee; 1355 1356 ee = kzalloc(sizeof(*ee), gfp); 1357 if (!ee) 1358 return NULL; 1359 1360 ee->engine = engine; 1361 1362 engine_record_registers(ee); 1363 engine_record_execlists(ee); 1364 1365 return ee; 1366 } 1367 1368 struct intel_engine_capture_vma * 1369 intel_engine_coredump_add_request(struct intel_engine_coredump *ee, 1370 struct i915_request *rq, 1371 gfp_t gfp) 1372 { 1373 struct intel_engine_capture_vma *vma = NULL; 1374 1375 ee->simulated |= record_context(&ee->context, rq); 1376 if (ee->simulated) 1377 return NULL; 1378 1379 /* 1380 * We need to copy these to an anonymous buffer 1381 * as the simplest method to avoid being overwritten 1382 * by userspace. 1383 */ 1384 vma = capture_vma(vma, rq->batch, "batch", gfp); 1385 vma = capture_user(vma, rq, gfp); 1386 vma = capture_vma(vma, rq->ring->vma, "ring", gfp); 1387 vma = capture_vma(vma, rq->context->state, "HW context", gfp); 1388 1389 ee->rq_head = rq->head; 1390 ee->rq_post = rq->postfix; 1391 ee->rq_tail = rq->tail; 1392 1393 return vma; 1394 } 1395 1396 void 1397 intel_engine_coredump_add_vma(struct intel_engine_coredump *ee, 1398 struct intel_engine_capture_vma *capture, 1399 struct i915_vma_compress *compress) 1400 { 1401 const struct intel_engine_cs *engine = ee->engine; 1402 1403 while (capture) { 1404 struct intel_engine_capture_vma *this = capture; 1405 struct i915_vma *vma = this->vma; 1406 1407 add_vma(ee, 1408 i915_vma_coredump_create(engine->gt, 1409 vma, this->name, 1410 compress)); 1411 1412 i915_active_release(&vma->active); 1413 i915_vma_put(vma); 1414 1415 capture = this->next; 1416 kfree(this); 1417 } 1418 1419 add_vma(ee, 1420 i915_vma_coredump_create(engine->gt, 1421 engine->status_page.vma, 1422 "HW Status", 1423 compress)); 1424 1425 add_vma(ee, 1426 i915_vma_coredump_create(engine->gt, 1427 engine->wa_ctx.vma, 1428 "WA context", 1429 compress)); 1430 1431 add_vma(ee, 1432 capture_object(engine->gt, 1433 engine->default_state, 1434 "NULL context", 1435 compress)); 1436 } 1437 1438 static struct intel_engine_coredump * 1439 capture_engine(struct intel_engine_cs *engine, 1440 struct i915_vma_compress *compress) 1441 { 1442 struct intel_engine_capture_vma *capture = NULL; 1443 struct intel_engine_coredump *ee; 1444 struct i915_request *rq; 1445 unsigned long flags; 1446 1447 ee = intel_engine_coredump_alloc(engine, GFP_KERNEL); 1448 if (!ee) 1449 return NULL; 1450 1451 spin_lock_irqsave(&engine->active.lock, flags); 1452 rq = intel_engine_find_active_request(engine); 1453 if (rq) 1454 capture = intel_engine_coredump_add_request(ee, rq, 1455 ATOMIC_MAYFAIL); 1456 spin_unlock_irqrestore(&engine->active.lock, flags); 1457 if (!capture) { 1458 kfree(ee); 1459 return NULL; 1460 } 1461 1462 intel_engine_coredump_add_vma(ee, capture, compress); 1463 1464 return ee; 1465 } 1466 1467 static void 1468 gt_record_engines(struct intel_gt_coredump *gt, 1469 struct i915_vma_compress *compress) 1470 { 1471 struct intel_engine_cs *engine; 1472 enum intel_engine_id id; 1473 1474 for_each_engine(engine, gt->_gt, id) { 1475 struct intel_engine_coredump *ee; 1476 1477 /* Refill our page pool before entering atomic section */ 1478 pool_refill(&compress->pool, ALLOW_FAIL); 1479 1480 ee = capture_engine(engine, compress); 1481 if (!ee) 1482 continue; 1483 1484 gt->simulated |= ee->simulated; 1485 if (ee->simulated) { 1486 kfree(ee); 1487 continue; 1488 } 1489 1490 ee->next = gt->engine; 1491 gt->engine = ee; 1492 } 1493 } 1494 1495 static struct intel_uc_coredump * 1496 gt_record_uc(struct intel_gt_coredump *gt, 1497 struct i915_vma_compress *compress) 1498 { 1499 const struct intel_uc *uc = >->_gt->uc; 1500 struct intel_uc_coredump *error_uc; 1501 1502 error_uc = kzalloc(sizeof(*error_uc), ALLOW_FAIL); 1503 if (!error_uc) 1504 return NULL; 1505 1506 memcpy(&error_uc->guc_fw, &uc->guc.fw, sizeof(uc->guc.fw)); 1507 memcpy(&error_uc->huc_fw, &uc->huc.fw, sizeof(uc->huc.fw)); 1508 1509 /* Non-default firmware paths will be specified by the modparam. 1510 * As modparams are generally accesible from the userspace make 1511 * explicit copies of the firmware paths. 1512 */ 1513 error_uc->guc_fw.path = kstrdup(uc->guc.fw.path, ALLOW_FAIL); 1514 error_uc->huc_fw.path = kstrdup(uc->huc.fw.path, ALLOW_FAIL); 1515 error_uc->guc_log = 1516 i915_vma_coredump_create(gt->_gt, 1517 uc->guc.log.vma, "GuC log buffer", 1518 compress); 1519 1520 return error_uc; 1521 } 1522 1523 static void gt_capture_prepare(struct intel_gt_coredump *gt) 1524 { 1525 struct i915_ggtt *ggtt = gt->_gt->ggtt; 1526 1527 mutex_lock(&ggtt->error_mutex); 1528 } 1529 1530 static void gt_capture_finish(struct intel_gt_coredump *gt) 1531 { 1532 struct i915_ggtt *ggtt = gt->_gt->ggtt; 1533 1534 if (drm_mm_node_allocated(&ggtt->error_capture)) 1535 ggtt->vm.clear_range(&ggtt->vm, 1536 ggtt->error_capture.start, 1537 PAGE_SIZE); 1538 1539 mutex_unlock(&ggtt->error_mutex); 1540 } 1541 1542 /* Capture all registers which don't fit into another category. */ 1543 static void gt_record_regs(struct intel_gt_coredump *gt) 1544 { 1545 struct intel_uncore *uncore = gt->_gt->uncore; 1546 struct drm_i915_private *i915 = uncore->i915; 1547 int i; 1548 1549 /* 1550 * General organization 1551 * 1. Registers specific to a single generation 1552 * 2. Registers which belong to multiple generations 1553 * 3. Feature specific registers. 1554 * 4. Everything else 1555 * Please try to follow the order. 1556 */ 1557 1558 /* 1: Registers specific to a single generation */ 1559 if (IS_VALLEYVIEW(i915)) { 1560 gt->gtier[0] = intel_uncore_read(uncore, GTIER); 1561 gt->ier = intel_uncore_read(uncore, VLV_IER); 1562 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_VLV); 1563 } 1564 1565 if (IS_GEN(i915, 7)) 1566 gt->err_int = intel_uncore_read(uncore, GEN7_ERR_INT); 1567 1568 if (INTEL_GEN(i915) >= 12) { 1569 gt->fault_data0 = intel_uncore_read(uncore, 1570 GEN12_FAULT_TLB_DATA0); 1571 gt->fault_data1 = intel_uncore_read(uncore, 1572 GEN12_FAULT_TLB_DATA1); 1573 } else if (INTEL_GEN(i915) >= 8) { 1574 gt->fault_data0 = intel_uncore_read(uncore, 1575 GEN8_FAULT_TLB_DATA0); 1576 gt->fault_data1 = intel_uncore_read(uncore, 1577 GEN8_FAULT_TLB_DATA1); 1578 } 1579 1580 if (IS_GEN(i915, 6)) { 1581 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE); 1582 gt->gab_ctl = intel_uncore_read(uncore, GAB_CTL); 1583 gt->gfx_mode = intel_uncore_read(uncore, GFX_MODE); 1584 } 1585 1586 /* 2: Registers which belong to multiple generations */ 1587 if (INTEL_GEN(i915) >= 7) 1588 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_MT); 1589 1590 if (INTEL_GEN(i915) >= 6) { 1591 gt->derrmr = intel_uncore_read(uncore, DERRMR); 1592 if (INTEL_GEN(i915) < 12) { 1593 gt->error = intel_uncore_read(uncore, ERROR_GEN6); 1594 gt->done_reg = intel_uncore_read(uncore, DONE_REG); 1595 } 1596 } 1597 1598 /* 3: Feature specific registers */ 1599 if (IS_GEN_RANGE(i915, 6, 7)) { 1600 gt->gam_ecochk = intel_uncore_read(uncore, GAM_ECOCHK); 1601 gt->gac_eco = intel_uncore_read(uncore, GAC_ECO_BITS); 1602 } 1603 1604 if (IS_GEN_RANGE(i915, 8, 11)) 1605 gt->gtt_cache = intel_uncore_read(uncore, HSW_GTT_CACHE_EN); 1606 1607 if (IS_GEN(i915, 12)) 1608 gt->aux_err = intel_uncore_read(uncore, GEN12_AUX_ERR_DBG); 1609 1610 if (INTEL_GEN(i915) >= 12) { 1611 for (i = 0; i < GEN12_SFC_DONE_MAX; i++) { 1612 gt->sfc_done[i] = 1613 intel_uncore_read(uncore, GEN12_SFC_DONE(i)); 1614 } 1615 1616 gt->gam_done = intel_uncore_read(uncore, GEN12_GAM_DONE); 1617 } 1618 1619 /* 4: Everything else */ 1620 if (INTEL_GEN(i915) >= 11) { 1621 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER); 1622 gt->gtier[0] = 1623 intel_uncore_read(uncore, 1624 GEN11_RENDER_COPY_INTR_ENABLE); 1625 gt->gtier[1] = 1626 intel_uncore_read(uncore, GEN11_VCS_VECS_INTR_ENABLE); 1627 gt->gtier[2] = 1628 intel_uncore_read(uncore, GEN11_GUC_SG_INTR_ENABLE); 1629 gt->gtier[3] = 1630 intel_uncore_read(uncore, 1631 GEN11_GPM_WGBOXPERF_INTR_ENABLE); 1632 gt->gtier[4] = 1633 intel_uncore_read(uncore, 1634 GEN11_CRYPTO_RSVD_INTR_ENABLE); 1635 gt->gtier[5] = 1636 intel_uncore_read(uncore, 1637 GEN11_GUNIT_CSME_INTR_ENABLE); 1638 gt->ngtier = 6; 1639 } else if (INTEL_GEN(i915) >= 8) { 1640 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER); 1641 for (i = 0; i < 4; i++) 1642 gt->gtier[i] = 1643 intel_uncore_read(uncore, GEN8_GT_IER(i)); 1644 gt->ngtier = 4; 1645 } else if (HAS_PCH_SPLIT(i915)) { 1646 gt->ier = intel_uncore_read(uncore, DEIER); 1647 gt->gtier[0] = intel_uncore_read(uncore, GTIER); 1648 gt->ngtier = 1; 1649 } else if (IS_GEN(i915, 2)) { 1650 gt->ier = intel_uncore_read16(uncore, GEN2_IER); 1651 } else if (!IS_VALLEYVIEW(i915)) { 1652 gt->ier = intel_uncore_read(uncore, GEN2_IER); 1653 } 1654 gt->eir = intel_uncore_read(uncore, EIR); 1655 gt->pgtbl_er = intel_uncore_read(uncore, PGTBL_ER); 1656 } 1657 1658 /* 1659 * Generate a semi-unique error code. The code is not meant to have meaning, The 1660 * code's only purpose is to try to prevent false duplicated bug reports by 1661 * grossly estimating a GPU error state. 1662 * 1663 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine 1664 * the hang if we could strip the GTT offset information from it. 1665 * 1666 * It's only a small step better than a random number in its current form. 1667 */ 1668 static u32 generate_ecode(const struct intel_engine_coredump *ee) 1669 { 1670 /* 1671 * IPEHR would be an ideal way to detect errors, as it's the gross 1672 * measure of "the command that hung." However, has some very common 1673 * synchronization commands which almost always appear in the case 1674 * strictly a client bug. Use instdone to differentiate those some. 1675 */ 1676 return ee ? ee->ipehr ^ ee->instdone.instdone : 0; 1677 } 1678 1679 static const char *error_msg(struct i915_gpu_coredump *error) 1680 { 1681 struct intel_engine_coredump *first = NULL; 1682 struct intel_gt_coredump *gt; 1683 intel_engine_mask_t engines; 1684 int len; 1685 1686 engines = 0; 1687 for (gt = error->gt; gt; gt = gt->next) { 1688 struct intel_engine_coredump *cs; 1689 1690 if (gt->engine && !first) 1691 first = gt->engine; 1692 1693 for (cs = gt->engine; cs; cs = cs->next) 1694 engines |= cs->engine->mask; 1695 } 1696 1697 len = scnprintf(error->error_msg, sizeof(error->error_msg), 1698 "GPU HANG: ecode %d:%x:%08x", 1699 INTEL_GEN(error->i915), engines, 1700 generate_ecode(first)); 1701 if (first && first->context.pid) { 1702 /* Just show the first executing process, more is confusing */ 1703 len += scnprintf(error->error_msg + len, 1704 sizeof(error->error_msg) - len, 1705 ", in %s [%d]", 1706 first->context.comm, first->context.pid); 1707 } 1708 1709 return error->error_msg; 1710 } 1711 1712 static void capture_gen(struct i915_gpu_coredump *error) 1713 { 1714 struct drm_i915_private *i915 = error->i915; 1715 1716 error->wakelock = atomic_read(&i915->runtime_pm.wakeref_count); 1717 error->suspended = i915->runtime_pm.suspended; 1718 1719 error->iommu = -1; 1720 #ifdef CONFIG_INTEL_IOMMU 1721 error->iommu = intel_iommu_gfx_mapped; 1722 #endif 1723 error->reset_count = i915_reset_count(&i915->gpu_error); 1724 error->suspend_count = i915->suspend_count; 1725 1726 i915_params_copy(&error->params, &i915_modparams); 1727 memcpy(&error->device_info, 1728 INTEL_INFO(i915), 1729 sizeof(error->device_info)); 1730 memcpy(&error->runtime_info, 1731 RUNTIME_INFO(i915), 1732 sizeof(error->runtime_info)); 1733 error->driver_caps = i915->caps; 1734 } 1735 1736 struct i915_gpu_coredump * 1737 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp) 1738 { 1739 struct i915_gpu_coredump *error; 1740 1741 if (!i915_modparams.error_capture) 1742 return NULL; 1743 1744 error = kzalloc(sizeof(*error), gfp); 1745 if (!error) 1746 return NULL; 1747 1748 kref_init(&error->ref); 1749 error->i915 = i915; 1750 1751 error->time = ktime_get_real(); 1752 error->boottime = ktime_get_boottime(); 1753 error->uptime = ktime_sub(ktime_get(), i915->gt.last_init_time); 1754 error->capture = jiffies; 1755 1756 capture_gen(error); 1757 1758 return error; 1759 } 1760 1761 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x)) 1762 1763 struct intel_gt_coredump * 1764 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp) 1765 { 1766 struct intel_gt_coredump *gc; 1767 1768 gc = kzalloc(sizeof(*gc), gfp); 1769 if (!gc) 1770 return NULL; 1771 1772 gc->_gt = gt; 1773 gc->awake = intel_gt_pm_is_awake(gt); 1774 1775 gt_record_regs(gc); 1776 gt_record_fences(gc); 1777 1778 return gc; 1779 } 1780 1781 struct i915_vma_compress * 1782 i915_vma_capture_prepare(struct intel_gt_coredump *gt) 1783 { 1784 struct i915_vma_compress *compress; 1785 1786 compress = kmalloc(sizeof(*compress), ALLOW_FAIL); 1787 if (!compress) 1788 return NULL; 1789 1790 if (!compress_init(compress)) { 1791 kfree(compress); 1792 return NULL; 1793 } 1794 1795 gt_capture_prepare(gt); 1796 1797 return compress; 1798 } 1799 1800 void i915_vma_capture_finish(struct intel_gt_coredump *gt, 1801 struct i915_vma_compress *compress) 1802 { 1803 if (!compress) 1804 return; 1805 1806 gt_capture_finish(gt); 1807 1808 compress_fini(compress); 1809 kfree(compress); 1810 } 1811 1812 struct i915_gpu_coredump *i915_gpu_coredump(struct drm_i915_private *i915) 1813 { 1814 struct i915_gpu_coredump *error; 1815 1816 /* Check if GPU capture has been disabled */ 1817 error = READ_ONCE(i915->gpu_error.first_error); 1818 if (IS_ERR(error)) 1819 return error; 1820 1821 error = i915_gpu_coredump_alloc(i915, ALLOW_FAIL); 1822 if (!error) 1823 return ERR_PTR(-ENOMEM); 1824 1825 error->gt = intel_gt_coredump_alloc(&i915->gt, ALLOW_FAIL); 1826 if (error->gt) { 1827 struct i915_vma_compress *compress; 1828 1829 compress = i915_vma_capture_prepare(error->gt); 1830 if (!compress) { 1831 kfree(error->gt); 1832 kfree(error); 1833 return ERR_PTR(-ENOMEM); 1834 } 1835 1836 gt_record_engines(error->gt, compress); 1837 1838 if (INTEL_INFO(i915)->has_gt_uc) 1839 error->gt->uc = gt_record_uc(error->gt, compress); 1840 1841 i915_vma_capture_finish(error->gt, compress); 1842 1843 error->simulated |= error->gt->simulated; 1844 } 1845 1846 error->overlay = intel_overlay_capture_error_state(i915); 1847 error->display = intel_display_capture_error_state(i915); 1848 1849 return error; 1850 } 1851 1852 void i915_error_state_store(struct i915_gpu_coredump *error) 1853 { 1854 struct drm_i915_private *i915; 1855 static bool warned; 1856 1857 if (IS_ERR_OR_NULL(error)) 1858 return; 1859 1860 i915 = error->i915; 1861 dev_info(i915->drm.dev, "%s\n", error_msg(error)); 1862 1863 if (error->simulated || 1864 cmpxchg(&i915->gpu_error.first_error, NULL, error)) 1865 return; 1866 1867 i915_gpu_coredump_get(error); 1868 1869 if (!xchg(&warned, true) && 1870 ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) { 1871 pr_info("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n"); 1872 pr_info("Please file a _new_ bug report at https://gitlab.freedesktop.org/drm/intel/issues/new.\n"); 1873 pr_info("Please see https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs for details.\n"); 1874 pr_info("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n"); 1875 pr_info("The GPU crash dump is required to analyze GPU hangs, so please always attach it.\n"); 1876 pr_info("GPU crash dump saved to /sys/class/drm/card%d/error\n", 1877 i915->drm.primary->index); 1878 } 1879 } 1880 1881 /** 1882 * i915_capture_error_state - capture an error record for later analysis 1883 * @i915: i915 device 1884 * 1885 * Should be called when an error is detected (either a hang or an error 1886 * interrupt) to capture error state from the time of the error. Fills 1887 * out a structure which becomes available in debugfs for user level tools 1888 * to pick up. 1889 */ 1890 void i915_capture_error_state(struct drm_i915_private *i915) 1891 { 1892 struct i915_gpu_coredump *error; 1893 1894 error = i915_gpu_coredump(i915); 1895 if (IS_ERR(error)) { 1896 cmpxchg(&i915->gpu_error.first_error, NULL, error); 1897 return; 1898 } 1899 1900 i915_error_state_store(error); 1901 i915_gpu_coredump_put(error); 1902 } 1903 1904 struct i915_gpu_coredump * 1905 i915_first_error_state(struct drm_i915_private *i915) 1906 { 1907 struct i915_gpu_coredump *error; 1908 1909 spin_lock_irq(&i915->gpu_error.lock); 1910 error = i915->gpu_error.first_error; 1911 if (!IS_ERR_OR_NULL(error)) 1912 i915_gpu_coredump_get(error); 1913 spin_unlock_irq(&i915->gpu_error.lock); 1914 1915 return error; 1916 } 1917 1918 void i915_reset_error_state(struct drm_i915_private *i915) 1919 { 1920 struct i915_gpu_coredump *error; 1921 1922 spin_lock_irq(&i915->gpu_error.lock); 1923 error = i915->gpu_error.first_error; 1924 if (error != ERR_PTR(-ENODEV)) /* if disabled, always disabled */ 1925 i915->gpu_error.first_error = NULL; 1926 spin_unlock_irq(&i915->gpu_error.lock); 1927 1928 if (!IS_ERR_OR_NULL(error)) 1929 i915_gpu_coredump_put(error); 1930 } 1931 1932 void i915_disable_error_state(struct drm_i915_private *i915, int err) 1933 { 1934 spin_lock_irq(&i915->gpu_error.lock); 1935 if (!i915->gpu_error.first_error) 1936 i915->gpu_error.first_error = ERR_PTR(err); 1937 spin_unlock_irq(&i915->gpu_error.lock); 1938 } 1939