1 /* 2 * Copyright (c) 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * Mika Kuoppala <mika.kuoppala@intel.com> 27 * 28 */ 29 30 #include <linux/ascii85.h> 31 #include <linux/highmem.h> 32 #include <linux/nmi.h> 33 #include <linux/pagevec.h> 34 #include <linux/scatterlist.h> 35 #include <linux/string_helpers.h> 36 #include <linux/utsname.h> 37 #include <linux/zlib.h> 38 39 #include <drm/drm_cache.h> 40 #include <drm/drm_print.h> 41 42 #include "display/intel_dmc.h" 43 #include "display/intel_overlay.h" 44 45 #include "gem/i915_gem_context.h" 46 #include "gem/i915_gem_lmem.h" 47 #include "gt/intel_engine_regs.h" 48 #include "gt/intel_gt.h" 49 #include "gt/intel_gt_mcr.h" 50 #include "gt/intel_gt_pm.h" 51 #include "gt/intel_gt_regs.h" 52 #include "gt/uc/intel_guc_capture.h" 53 54 #include "i915_driver.h" 55 #include "i915_drv.h" 56 #include "i915_gpu_error.h" 57 #include "i915_memcpy.h" 58 #include "i915_scatterlist.h" 59 #include "i915_utils.h" 60 61 #define ALLOW_FAIL (__GFP_KSWAPD_RECLAIM | __GFP_RETRY_MAYFAIL | __GFP_NOWARN) 62 #define ATOMIC_MAYFAIL (GFP_ATOMIC | __GFP_NOWARN) 63 64 static void __sg_set_buf(struct scatterlist *sg, 65 void *addr, unsigned int len, loff_t it) 66 { 67 sg->page_link = (unsigned long)virt_to_page(addr); 68 sg->offset = offset_in_page(addr); 69 sg->length = len; 70 sg->dma_address = it; 71 } 72 73 static bool __i915_error_grow(struct drm_i915_error_state_buf *e, size_t len) 74 { 75 if (!len) 76 return false; 77 78 if (e->bytes + len + 1 <= e->size) 79 return true; 80 81 if (e->bytes) { 82 __sg_set_buf(e->cur++, e->buf, e->bytes, e->iter); 83 e->iter += e->bytes; 84 e->buf = NULL; 85 e->bytes = 0; 86 } 87 88 if (e->cur == e->end) { 89 struct scatterlist *sgl; 90 91 sgl = (typeof(sgl))__get_free_page(ALLOW_FAIL); 92 if (!sgl) { 93 e->err = -ENOMEM; 94 return false; 95 } 96 97 if (e->cur) { 98 e->cur->offset = 0; 99 e->cur->length = 0; 100 e->cur->page_link = 101 (unsigned long)sgl | SG_CHAIN; 102 } else { 103 e->sgl = sgl; 104 } 105 106 e->cur = sgl; 107 e->end = sgl + SG_MAX_SINGLE_ALLOC - 1; 108 } 109 110 e->size = ALIGN(len + 1, SZ_64K); 111 e->buf = kmalloc(e->size, ALLOW_FAIL); 112 if (!e->buf) { 113 e->size = PAGE_ALIGN(len + 1); 114 e->buf = kmalloc(e->size, GFP_KERNEL); 115 } 116 if (!e->buf) { 117 e->err = -ENOMEM; 118 return false; 119 } 120 121 return true; 122 } 123 124 __printf(2, 0) 125 static void i915_error_vprintf(struct drm_i915_error_state_buf *e, 126 const char *fmt, va_list args) 127 { 128 va_list ap; 129 int len; 130 131 if (e->err) 132 return; 133 134 va_copy(ap, args); 135 len = vsnprintf(NULL, 0, fmt, ap); 136 va_end(ap); 137 if (len <= 0) { 138 e->err = len; 139 return; 140 } 141 142 if (!__i915_error_grow(e, len)) 143 return; 144 145 GEM_BUG_ON(e->bytes >= e->size); 146 len = vscnprintf(e->buf + e->bytes, e->size - e->bytes, fmt, args); 147 if (len < 0) { 148 e->err = len; 149 return; 150 } 151 e->bytes += len; 152 } 153 154 static void i915_error_puts(struct drm_i915_error_state_buf *e, const char *str) 155 { 156 unsigned len; 157 158 if (e->err || !str) 159 return; 160 161 len = strlen(str); 162 if (!__i915_error_grow(e, len)) 163 return; 164 165 GEM_BUG_ON(e->bytes + len > e->size); 166 memcpy(e->buf + e->bytes, str, len); 167 e->bytes += len; 168 } 169 170 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) 171 #define err_puts(e, s) i915_error_puts(e, s) 172 173 static void __i915_printfn_error(struct drm_printer *p, struct va_format *vaf) 174 { 175 i915_error_vprintf(p->arg, vaf->fmt, *vaf->va); 176 } 177 178 static inline struct drm_printer 179 i915_error_printer(struct drm_i915_error_state_buf *e) 180 { 181 struct drm_printer p = { 182 .printfn = __i915_printfn_error, 183 .arg = e, 184 }; 185 return p; 186 } 187 188 /* single threaded page allocator with a reserved stash for emergencies */ 189 static void pool_fini(struct pagevec *pv) 190 { 191 pagevec_release(pv); 192 } 193 194 static int pool_refill(struct pagevec *pv, gfp_t gfp) 195 { 196 while (pagevec_space(pv)) { 197 struct page *p; 198 199 p = alloc_page(gfp); 200 if (!p) 201 return -ENOMEM; 202 203 pagevec_add(pv, p); 204 } 205 206 return 0; 207 } 208 209 static int pool_init(struct pagevec *pv, gfp_t gfp) 210 { 211 int err; 212 213 pagevec_init(pv); 214 215 err = pool_refill(pv, gfp); 216 if (err) 217 pool_fini(pv); 218 219 return err; 220 } 221 222 static void *pool_alloc(struct pagevec *pv, gfp_t gfp) 223 { 224 struct page *p; 225 226 p = alloc_page(gfp); 227 if (!p && pagevec_count(pv)) 228 p = pv->pages[--pv->nr]; 229 230 return p ? page_address(p) : NULL; 231 } 232 233 static void pool_free(struct pagevec *pv, void *addr) 234 { 235 struct page *p = virt_to_page(addr); 236 237 if (pagevec_space(pv)) 238 pagevec_add(pv, p); 239 else 240 __free_page(p); 241 } 242 243 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR 244 245 struct i915_vma_compress { 246 struct pagevec pool; 247 struct z_stream_s zstream; 248 void *tmp; 249 }; 250 251 static bool compress_init(struct i915_vma_compress *c) 252 { 253 struct z_stream_s *zstream = &c->zstream; 254 255 if (pool_init(&c->pool, ALLOW_FAIL)) 256 return false; 257 258 zstream->workspace = 259 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL), 260 ALLOW_FAIL); 261 if (!zstream->workspace) { 262 pool_fini(&c->pool); 263 return false; 264 } 265 266 c->tmp = NULL; 267 if (i915_has_memcpy_from_wc()) 268 c->tmp = pool_alloc(&c->pool, ALLOW_FAIL); 269 270 return true; 271 } 272 273 static bool compress_start(struct i915_vma_compress *c) 274 { 275 struct z_stream_s *zstream = &c->zstream; 276 void *workspace = zstream->workspace; 277 278 memset(zstream, 0, sizeof(*zstream)); 279 zstream->workspace = workspace; 280 281 return zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) == Z_OK; 282 } 283 284 static void *compress_next_page(struct i915_vma_compress *c, 285 struct i915_vma_coredump *dst) 286 { 287 void *page_addr; 288 struct page *page; 289 290 page_addr = pool_alloc(&c->pool, ALLOW_FAIL); 291 if (!page_addr) 292 return ERR_PTR(-ENOMEM); 293 294 page = virt_to_page(page_addr); 295 list_add_tail(&page->lru, &dst->page_list); 296 return page_addr; 297 } 298 299 static int compress_page(struct i915_vma_compress *c, 300 void *src, 301 struct i915_vma_coredump *dst, 302 bool wc) 303 { 304 struct z_stream_s *zstream = &c->zstream; 305 306 zstream->next_in = src; 307 if (wc && c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE)) 308 zstream->next_in = c->tmp; 309 zstream->avail_in = PAGE_SIZE; 310 311 do { 312 if (zstream->avail_out == 0) { 313 zstream->next_out = compress_next_page(c, dst); 314 if (IS_ERR(zstream->next_out)) 315 return PTR_ERR(zstream->next_out); 316 317 zstream->avail_out = PAGE_SIZE; 318 } 319 320 if (zlib_deflate(zstream, Z_NO_FLUSH) != Z_OK) 321 return -EIO; 322 323 cond_resched(); 324 } while (zstream->avail_in); 325 326 /* Fallback to uncompressed if we increase size? */ 327 if (0 && zstream->total_out > zstream->total_in) 328 return -E2BIG; 329 330 return 0; 331 } 332 333 static int compress_flush(struct i915_vma_compress *c, 334 struct i915_vma_coredump *dst) 335 { 336 struct z_stream_s *zstream = &c->zstream; 337 338 do { 339 switch (zlib_deflate(zstream, Z_FINISH)) { 340 case Z_OK: /* more space requested */ 341 zstream->next_out = compress_next_page(c, dst); 342 if (IS_ERR(zstream->next_out)) 343 return PTR_ERR(zstream->next_out); 344 345 zstream->avail_out = PAGE_SIZE; 346 break; 347 348 case Z_STREAM_END: 349 goto end; 350 351 default: /* any error */ 352 return -EIO; 353 } 354 } while (1); 355 356 end: 357 memset(zstream->next_out, 0, zstream->avail_out); 358 dst->unused = zstream->avail_out; 359 return 0; 360 } 361 362 static void compress_finish(struct i915_vma_compress *c) 363 { 364 zlib_deflateEnd(&c->zstream); 365 } 366 367 static void compress_fini(struct i915_vma_compress *c) 368 { 369 kfree(c->zstream.workspace); 370 if (c->tmp) 371 pool_free(&c->pool, c->tmp); 372 pool_fini(&c->pool); 373 } 374 375 static void err_compression_marker(struct drm_i915_error_state_buf *m) 376 { 377 err_puts(m, ":"); 378 } 379 380 #else 381 382 struct i915_vma_compress { 383 struct pagevec pool; 384 }; 385 386 static bool compress_init(struct i915_vma_compress *c) 387 { 388 return pool_init(&c->pool, ALLOW_FAIL) == 0; 389 } 390 391 static bool compress_start(struct i915_vma_compress *c) 392 { 393 return true; 394 } 395 396 static int compress_page(struct i915_vma_compress *c, 397 void *src, 398 struct i915_vma_coredump *dst, 399 bool wc) 400 { 401 void *ptr; 402 403 ptr = pool_alloc(&c->pool, ALLOW_FAIL); 404 if (!ptr) 405 return -ENOMEM; 406 407 if (!(wc && i915_memcpy_from_wc(ptr, src, PAGE_SIZE))) 408 memcpy(ptr, src, PAGE_SIZE); 409 list_add_tail(&virt_to_page(ptr)->lru, &dst->page_list); 410 cond_resched(); 411 412 return 0; 413 } 414 415 static int compress_flush(struct i915_vma_compress *c, 416 struct i915_vma_coredump *dst) 417 { 418 return 0; 419 } 420 421 static void compress_finish(struct i915_vma_compress *c) 422 { 423 } 424 425 static void compress_fini(struct i915_vma_compress *c) 426 { 427 pool_fini(&c->pool); 428 } 429 430 static void err_compression_marker(struct drm_i915_error_state_buf *m) 431 { 432 err_puts(m, "~"); 433 } 434 435 #endif 436 437 static void error_print_instdone(struct drm_i915_error_state_buf *m, 438 const struct intel_engine_coredump *ee) 439 { 440 int slice; 441 int subslice; 442 int iter; 443 444 err_printf(m, " INSTDONE: 0x%08x\n", 445 ee->instdone.instdone); 446 447 if (ee->engine->class != RENDER_CLASS || GRAPHICS_VER(m->i915) <= 3) 448 return; 449 450 err_printf(m, " SC_INSTDONE: 0x%08x\n", 451 ee->instdone.slice_common); 452 453 if (GRAPHICS_VER(m->i915) <= 6) 454 return; 455 456 for_each_ss_steering(iter, ee->engine->gt, slice, subslice) 457 err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n", 458 slice, subslice, 459 ee->instdone.sampler[slice][subslice]); 460 461 for_each_ss_steering(iter, ee->engine->gt, slice, subslice) 462 err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n", 463 slice, subslice, 464 ee->instdone.row[slice][subslice]); 465 466 if (GRAPHICS_VER(m->i915) < 12) 467 return; 468 469 if (GRAPHICS_VER_FULL(m->i915) >= IP_VER(12, 55)) { 470 for_each_ss_steering(iter, ee->engine->gt, slice, subslice) 471 err_printf(m, " GEOM_SVGUNIT_INSTDONE[%d][%d]: 0x%08x\n", 472 slice, subslice, 473 ee->instdone.geom_svg[slice][subslice]); 474 } 475 476 err_printf(m, " SC_INSTDONE_EXTRA: 0x%08x\n", 477 ee->instdone.slice_common_extra[0]); 478 err_printf(m, " SC_INSTDONE_EXTRA2: 0x%08x\n", 479 ee->instdone.slice_common_extra[1]); 480 } 481 482 static void error_print_request(struct drm_i915_error_state_buf *m, 483 const char *prefix, 484 const struct i915_request_coredump *erq) 485 { 486 if (!erq->seqno) 487 return; 488 489 err_printf(m, "%s pid %d, seqno %8x:%08x%s%s, prio %d, head %08x, tail %08x\n", 490 prefix, erq->pid, erq->context, erq->seqno, 491 test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, 492 &erq->flags) ? "!" : "", 493 test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, 494 &erq->flags) ? "+" : "", 495 erq->sched_attr.priority, 496 erq->head, erq->tail); 497 } 498 499 static void error_print_context(struct drm_i915_error_state_buf *m, 500 const char *header, 501 const struct i915_gem_context_coredump *ctx) 502 { 503 err_printf(m, "%s%s[%d] prio %d, guilty %d active %d, runtime total %lluns, avg %lluns\n", 504 header, ctx->comm, ctx->pid, ctx->sched_attr.priority, 505 ctx->guilty, ctx->active, 506 ctx->total_runtime, ctx->avg_runtime); 507 } 508 509 static struct i915_vma_coredump * 510 __find_vma(struct i915_vma_coredump *vma, const char *name) 511 { 512 while (vma) { 513 if (strcmp(vma->name, name) == 0) 514 return vma; 515 vma = vma->next; 516 } 517 518 return NULL; 519 } 520 521 struct i915_vma_coredump * 522 intel_gpu_error_find_batch(const struct intel_engine_coredump *ee) 523 { 524 return __find_vma(ee->vma, "batch"); 525 } 526 527 static void error_print_engine(struct drm_i915_error_state_buf *m, 528 const struct intel_engine_coredump *ee) 529 { 530 struct i915_vma_coredump *batch; 531 int n; 532 533 err_printf(m, "%s command stream:\n", ee->engine->name); 534 err_printf(m, " CCID: 0x%08x\n", ee->ccid); 535 err_printf(m, " START: 0x%08x\n", ee->start); 536 err_printf(m, " HEAD: 0x%08x [0x%08x]\n", ee->head, ee->rq_head); 537 err_printf(m, " TAIL: 0x%08x [0x%08x, 0x%08x]\n", 538 ee->tail, ee->rq_post, ee->rq_tail); 539 err_printf(m, " CTL: 0x%08x\n", ee->ctl); 540 err_printf(m, " MODE: 0x%08x\n", ee->mode); 541 err_printf(m, " HWS: 0x%08x\n", ee->hws); 542 err_printf(m, " ACTHD: 0x%08x %08x\n", 543 (u32)(ee->acthd>>32), (u32)ee->acthd); 544 err_printf(m, " IPEIR: 0x%08x\n", ee->ipeir); 545 err_printf(m, " IPEHR: 0x%08x\n", ee->ipehr); 546 err_printf(m, " ESR: 0x%08x\n", ee->esr); 547 548 error_print_instdone(m, ee); 549 550 batch = intel_gpu_error_find_batch(ee); 551 if (batch) { 552 u64 start = batch->gtt_offset; 553 u64 end = start + batch->gtt_size; 554 555 err_printf(m, " batch: [0x%08x_%08x, 0x%08x_%08x]\n", 556 upper_32_bits(start), lower_32_bits(start), 557 upper_32_bits(end), lower_32_bits(end)); 558 } 559 if (GRAPHICS_VER(m->i915) >= 4) { 560 err_printf(m, " BBADDR: 0x%08x_%08x\n", 561 (u32)(ee->bbaddr>>32), (u32)ee->bbaddr); 562 err_printf(m, " BB_STATE: 0x%08x\n", ee->bbstate); 563 err_printf(m, " INSTPS: 0x%08x\n", ee->instps); 564 } 565 err_printf(m, " INSTPM: 0x%08x\n", ee->instpm); 566 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr), 567 lower_32_bits(ee->faddr)); 568 if (GRAPHICS_VER(m->i915) >= 6) { 569 err_printf(m, " RC PSMI: 0x%08x\n", ee->rc_psmi); 570 err_printf(m, " FAULT_REG: 0x%08x\n", ee->fault_reg); 571 } 572 if (GRAPHICS_VER(m->i915) >= 11) { 573 err_printf(m, " NOPID: 0x%08x\n", ee->nopid); 574 err_printf(m, " EXCC: 0x%08x\n", ee->excc); 575 err_printf(m, " CMD_CCTL: 0x%08x\n", ee->cmd_cctl); 576 err_printf(m, " CSCMDOP: 0x%08x\n", ee->cscmdop); 577 err_printf(m, " CTX_SR_CTL: 0x%08x\n", ee->ctx_sr_ctl); 578 err_printf(m, " DMA_FADDR_HI: 0x%08x\n", ee->dma_faddr_hi); 579 err_printf(m, " DMA_FADDR_LO: 0x%08x\n", ee->dma_faddr_lo); 580 } 581 if (HAS_PPGTT(m->i915)) { 582 err_printf(m, " GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode); 583 584 if (GRAPHICS_VER(m->i915) >= 8) { 585 int i; 586 for (i = 0; i < 4; i++) 587 err_printf(m, " PDP%d: 0x%016llx\n", 588 i, ee->vm_info.pdp[i]); 589 } else { 590 err_printf(m, " PP_DIR_BASE: 0x%08x\n", 591 ee->vm_info.pp_dir_base); 592 } 593 } 594 595 for (n = 0; n < ee->num_ports; n++) { 596 err_printf(m, " ELSP[%d]:", n); 597 error_print_request(m, " ", &ee->execlist[n]); 598 } 599 } 600 601 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) 602 { 603 va_list args; 604 605 va_start(args, f); 606 i915_error_vprintf(e, f, args); 607 va_end(args); 608 } 609 610 void intel_gpu_error_print_vma(struct drm_i915_error_state_buf *m, 611 const struct intel_engine_cs *engine, 612 const struct i915_vma_coredump *vma) 613 { 614 char out[ASCII85_BUFSZ]; 615 struct page *page; 616 617 if (!vma) 618 return; 619 620 err_printf(m, "%s --- %s = 0x%08x %08x\n", 621 engine ? engine->name : "global", vma->name, 622 upper_32_bits(vma->gtt_offset), 623 lower_32_bits(vma->gtt_offset)); 624 625 if (vma->gtt_page_sizes > I915_GTT_PAGE_SIZE_4K) 626 err_printf(m, "gtt_page_sizes = 0x%08x\n", vma->gtt_page_sizes); 627 628 err_compression_marker(m); 629 list_for_each_entry(page, &vma->page_list, lru) { 630 int i, len; 631 const u32 *addr = page_address(page); 632 633 len = PAGE_SIZE; 634 if (page == list_last_entry(&vma->page_list, typeof(*page), lru)) 635 len -= vma->unused; 636 len = ascii85_encode_len(len); 637 638 for (i = 0; i < len; i++) 639 err_puts(m, ascii85_encode(addr[i], out)); 640 } 641 err_puts(m, "\n"); 642 } 643 644 static void err_print_capabilities(struct drm_i915_error_state_buf *m, 645 struct i915_gpu_coredump *error) 646 { 647 struct drm_printer p = i915_error_printer(m); 648 649 intel_device_info_print_static(&error->device_info, &p); 650 intel_device_info_print_runtime(&error->runtime_info, &p); 651 intel_driver_caps_print(&error->driver_caps, &p); 652 } 653 654 static void err_print_params(struct drm_i915_error_state_buf *m, 655 const struct i915_params *params) 656 { 657 struct drm_printer p = i915_error_printer(m); 658 659 i915_params_dump(params, &p); 660 } 661 662 static void err_print_pciid(struct drm_i915_error_state_buf *m, 663 struct drm_i915_private *i915) 664 { 665 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 666 667 err_printf(m, "PCI ID: 0x%04x\n", pdev->device); 668 err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision); 669 err_printf(m, "PCI Subsystem: %04x:%04x\n", 670 pdev->subsystem_vendor, 671 pdev->subsystem_device); 672 } 673 674 static void err_print_guc_ctb(struct drm_i915_error_state_buf *m, 675 const char *name, 676 const struct intel_ctb_coredump *ctb) 677 { 678 if (!ctb->size) 679 return; 680 681 err_printf(m, "GuC %s CTB: raw: 0x%08X, 0x%08X/%08X, cached: 0x%08X/%08X, desc = 0x%08X, buf = 0x%08X x 0x%08X\n", 682 name, ctb->raw_status, ctb->raw_head, ctb->raw_tail, 683 ctb->head, ctb->tail, ctb->desc_offset, ctb->cmds_offset, ctb->size); 684 } 685 686 static void err_print_uc(struct drm_i915_error_state_buf *m, 687 const struct intel_uc_coredump *error_uc) 688 { 689 struct drm_printer p = i915_error_printer(m); 690 691 intel_uc_fw_dump(&error_uc->guc_fw, &p); 692 intel_uc_fw_dump(&error_uc->huc_fw, &p); 693 err_printf(m, "GuC timestamp: 0x%08x\n", error_uc->guc.timestamp); 694 intel_gpu_error_print_vma(m, NULL, error_uc->guc.vma_log); 695 err_printf(m, "GuC CTB fence: %d\n", error_uc->guc.last_fence); 696 err_print_guc_ctb(m, "Send", error_uc->guc.ctb + 0); 697 err_print_guc_ctb(m, "Recv", error_uc->guc.ctb + 1); 698 intel_gpu_error_print_vma(m, NULL, error_uc->guc.vma_ctb); 699 } 700 701 static void err_free_sgl(struct scatterlist *sgl) 702 { 703 while (sgl) { 704 struct scatterlist *sg; 705 706 for (sg = sgl; !sg_is_chain(sg); sg++) { 707 kfree(sg_virt(sg)); 708 if (sg_is_last(sg)) 709 break; 710 } 711 712 sg = sg_is_last(sg) ? NULL : sg_chain_ptr(sg); 713 free_page((unsigned long)sgl); 714 sgl = sg; 715 } 716 } 717 718 static void err_print_gt_info(struct drm_i915_error_state_buf *m, 719 struct intel_gt_coredump *gt) 720 { 721 struct drm_printer p = i915_error_printer(m); 722 723 intel_gt_info_print(>->info, &p); 724 intel_sseu_print_topology(gt->_gt->i915, >->info.sseu, &p); 725 } 726 727 static void err_print_gt_display(struct drm_i915_error_state_buf *m, 728 struct intel_gt_coredump *gt) 729 { 730 err_printf(m, "IER: 0x%08x\n", gt->ier); 731 err_printf(m, "DERRMR: 0x%08x\n", gt->derrmr); 732 } 733 734 static void err_print_gt_global_nonguc(struct drm_i915_error_state_buf *m, 735 struct intel_gt_coredump *gt) 736 { 737 int i; 738 739 err_printf(m, "GT awake: %s\n", str_yes_no(gt->awake)); 740 err_printf(m, "CS timestamp frequency: %u Hz, %d ns\n", 741 gt->clock_frequency, gt->clock_period_ns); 742 err_printf(m, "EIR: 0x%08x\n", gt->eir); 743 err_printf(m, "PGTBL_ER: 0x%08x\n", gt->pgtbl_er); 744 745 for (i = 0; i < gt->ngtier; i++) 746 err_printf(m, "GTIER[%d]: 0x%08x\n", i, gt->gtier[i]); 747 } 748 749 static void err_print_gt_global(struct drm_i915_error_state_buf *m, 750 struct intel_gt_coredump *gt) 751 { 752 err_printf(m, "FORCEWAKE: 0x%08x\n", gt->forcewake); 753 754 if (IS_GRAPHICS_VER(m->i915, 6, 11)) { 755 err_printf(m, "ERROR: 0x%08x\n", gt->error); 756 err_printf(m, "DONE_REG: 0x%08x\n", gt->done_reg); 757 } 758 759 if (GRAPHICS_VER(m->i915) >= 8) 760 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n", 761 gt->fault_data1, gt->fault_data0); 762 763 if (GRAPHICS_VER(m->i915) == 7) 764 err_printf(m, "ERR_INT: 0x%08x\n", gt->err_int); 765 766 if (IS_GRAPHICS_VER(m->i915, 8, 11)) 767 err_printf(m, "GTT_CACHE_EN: 0x%08x\n", gt->gtt_cache); 768 769 if (GRAPHICS_VER(m->i915) == 12) 770 err_printf(m, "AUX_ERR_DBG: 0x%08x\n", gt->aux_err); 771 772 if (GRAPHICS_VER(m->i915) >= 12) { 773 int i; 774 775 for (i = 0; i < I915_MAX_SFC; i++) { 776 /* 777 * SFC_DONE resides in the VD forcewake domain, so it 778 * only exists if the corresponding VCS engine is 779 * present. 780 */ 781 if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 || 782 !HAS_ENGINE(gt->_gt, _VCS(i * 2))) 783 continue; 784 785 err_printf(m, " SFC_DONE[%d]: 0x%08x\n", i, 786 gt->sfc_done[i]); 787 } 788 789 err_printf(m, " GAM_DONE: 0x%08x\n", gt->gam_done); 790 } 791 } 792 793 static void err_print_gt_fences(struct drm_i915_error_state_buf *m, 794 struct intel_gt_coredump *gt) 795 { 796 int i; 797 798 for (i = 0; i < gt->nfence; i++) 799 err_printf(m, " fence[%d] = %08llx\n", i, gt->fence[i]); 800 } 801 802 static void err_print_gt_engines(struct drm_i915_error_state_buf *m, 803 struct intel_gt_coredump *gt) 804 { 805 const struct intel_engine_coredump *ee; 806 807 for (ee = gt->engine; ee; ee = ee->next) { 808 const struct i915_vma_coredump *vma; 809 810 if (ee->guc_capture_node) 811 intel_guc_capture_print_engine_node(m, ee); 812 else 813 error_print_engine(m, ee); 814 815 err_printf(m, " hung: %u\n", ee->hung); 816 err_printf(m, " engine reset count: %u\n", ee->reset_count); 817 error_print_context(m, " Active context: ", &ee->context); 818 819 for (vma = ee->vma; vma; vma = vma->next) 820 intel_gpu_error_print_vma(m, ee->engine, vma); 821 } 822 823 } 824 825 static void __err_print_to_sgl(struct drm_i915_error_state_buf *m, 826 struct i915_gpu_coredump *error) 827 { 828 const struct intel_engine_coredump *ee; 829 struct timespec64 ts; 830 831 if (*error->error_msg) 832 err_printf(m, "%s\n", error->error_msg); 833 err_printf(m, "Kernel: %s %s\n", 834 init_utsname()->release, 835 init_utsname()->machine); 836 err_printf(m, "Driver: %s\n", DRIVER_DATE); 837 ts = ktime_to_timespec64(error->time); 838 err_printf(m, "Time: %lld s %ld us\n", 839 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 840 ts = ktime_to_timespec64(error->boottime); 841 err_printf(m, "Boottime: %lld s %ld us\n", 842 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 843 ts = ktime_to_timespec64(error->uptime); 844 err_printf(m, "Uptime: %lld s %ld us\n", 845 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 846 err_printf(m, "Capture: %lu jiffies; %d ms ago\n", 847 error->capture, jiffies_to_msecs(jiffies - error->capture)); 848 849 for (ee = error->gt ? error->gt->engine : NULL; ee; ee = ee->next) 850 err_printf(m, "Active process (on ring %s): %s [%d]\n", 851 ee->engine->name, 852 ee->context.comm, 853 ee->context.pid); 854 855 err_printf(m, "Reset count: %u\n", error->reset_count); 856 err_printf(m, "Suspend count: %u\n", error->suspend_count); 857 err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform)); 858 err_printf(m, "Subplatform: 0x%x\n", 859 intel_subplatform(&error->runtime_info, 860 error->device_info.platform)); 861 err_print_pciid(m, m->i915); 862 863 err_printf(m, "IOMMU enabled?: %d\n", error->iommu); 864 865 intel_dmc_print_error_state(m, m->i915); 866 867 err_printf(m, "RPM wakelock: %s\n", str_yes_no(error->wakelock)); 868 err_printf(m, "PM suspended: %s\n", str_yes_no(error->suspended)); 869 870 if (error->gt) { 871 bool print_guc_capture = false; 872 873 if (error->gt->uc && error->gt->uc->guc.is_guc_capture) 874 print_guc_capture = true; 875 876 err_print_gt_display(m, error->gt); 877 err_print_gt_global_nonguc(m, error->gt); 878 err_print_gt_fences(m, error->gt); 879 880 /* 881 * GuC dumped global, eng-class and eng-instance registers together 882 * as part of engine state dump so we print in err_print_gt_engines 883 */ 884 if (!print_guc_capture) 885 err_print_gt_global(m, error->gt); 886 887 err_print_gt_engines(m, error->gt); 888 889 if (error->gt->uc) 890 err_print_uc(m, error->gt->uc); 891 892 err_print_gt_info(m, error->gt); 893 } 894 895 if (error->overlay) 896 intel_overlay_print_error_state(m, error->overlay); 897 898 err_print_capabilities(m, error); 899 err_print_params(m, &error->params); 900 } 901 902 static int err_print_to_sgl(struct i915_gpu_coredump *error) 903 { 904 struct drm_i915_error_state_buf m; 905 906 if (IS_ERR(error)) 907 return PTR_ERR(error); 908 909 if (READ_ONCE(error->sgl)) 910 return 0; 911 912 memset(&m, 0, sizeof(m)); 913 m.i915 = error->i915; 914 915 __err_print_to_sgl(&m, error); 916 917 if (m.buf) { 918 __sg_set_buf(m.cur++, m.buf, m.bytes, m.iter); 919 m.bytes = 0; 920 m.buf = NULL; 921 } 922 if (m.cur) { 923 GEM_BUG_ON(m.end < m.cur); 924 sg_mark_end(m.cur - 1); 925 } 926 GEM_BUG_ON(m.sgl && !m.cur); 927 928 if (m.err) { 929 err_free_sgl(m.sgl); 930 return m.err; 931 } 932 933 if (cmpxchg(&error->sgl, NULL, m.sgl)) 934 err_free_sgl(m.sgl); 935 936 return 0; 937 } 938 939 ssize_t i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error, 940 char *buf, loff_t off, size_t rem) 941 { 942 struct scatterlist *sg; 943 size_t count; 944 loff_t pos; 945 int err; 946 947 if (!error || !rem) 948 return 0; 949 950 err = err_print_to_sgl(error); 951 if (err) 952 return err; 953 954 sg = READ_ONCE(error->fit); 955 if (!sg || off < sg->dma_address) 956 sg = error->sgl; 957 if (!sg) 958 return 0; 959 960 pos = sg->dma_address; 961 count = 0; 962 do { 963 size_t len, start; 964 965 if (sg_is_chain(sg)) { 966 sg = sg_chain_ptr(sg); 967 GEM_BUG_ON(sg_is_chain(sg)); 968 } 969 970 len = sg->length; 971 if (pos + len <= off) { 972 pos += len; 973 continue; 974 } 975 976 start = sg->offset; 977 if (pos < off) { 978 GEM_BUG_ON(off - pos > len); 979 len -= off - pos; 980 start += off - pos; 981 pos = off; 982 } 983 984 len = min(len, rem); 985 GEM_BUG_ON(!len || len > sg->length); 986 987 memcpy(buf, page_address(sg_page(sg)) + start, len); 988 989 count += len; 990 pos += len; 991 992 buf += len; 993 rem -= len; 994 if (!rem) { 995 WRITE_ONCE(error->fit, sg); 996 break; 997 } 998 } while (!sg_is_last(sg++)); 999 1000 return count; 1001 } 1002 1003 static void i915_vma_coredump_free(struct i915_vma_coredump *vma) 1004 { 1005 while (vma) { 1006 struct i915_vma_coredump *next = vma->next; 1007 struct page *page, *n; 1008 1009 list_for_each_entry_safe(page, n, &vma->page_list, lru) { 1010 list_del_init(&page->lru); 1011 __free_page(page); 1012 } 1013 1014 kfree(vma); 1015 vma = next; 1016 } 1017 } 1018 1019 static void cleanup_params(struct i915_gpu_coredump *error) 1020 { 1021 i915_params_free(&error->params); 1022 } 1023 1024 static void cleanup_uc(struct intel_uc_coredump *uc) 1025 { 1026 kfree(uc->guc_fw.file_selected.path); 1027 kfree(uc->huc_fw.file_selected.path); 1028 kfree(uc->guc_fw.file_wanted.path); 1029 kfree(uc->huc_fw.file_wanted.path); 1030 i915_vma_coredump_free(uc->guc.vma_log); 1031 i915_vma_coredump_free(uc->guc.vma_ctb); 1032 1033 kfree(uc); 1034 } 1035 1036 static void cleanup_gt(struct intel_gt_coredump *gt) 1037 { 1038 while (gt->engine) { 1039 struct intel_engine_coredump *ee = gt->engine; 1040 1041 gt->engine = ee->next; 1042 1043 i915_vma_coredump_free(ee->vma); 1044 intel_guc_capture_free_node(ee); 1045 kfree(ee); 1046 } 1047 1048 if (gt->uc) 1049 cleanup_uc(gt->uc); 1050 1051 kfree(gt); 1052 } 1053 1054 void __i915_gpu_coredump_free(struct kref *error_ref) 1055 { 1056 struct i915_gpu_coredump *error = 1057 container_of(error_ref, typeof(*error), ref); 1058 1059 while (error->gt) { 1060 struct intel_gt_coredump *gt = error->gt; 1061 1062 error->gt = gt->next; 1063 cleanup_gt(gt); 1064 } 1065 1066 kfree(error->overlay); 1067 1068 cleanup_params(error); 1069 1070 err_free_sgl(error->sgl); 1071 kfree(error); 1072 } 1073 1074 static struct i915_vma_coredump * 1075 i915_vma_coredump_create(const struct intel_gt *gt, 1076 const struct i915_vma_resource *vma_res, 1077 struct i915_vma_compress *compress, 1078 const char *name) 1079 1080 { 1081 struct i915_ggtt *ggtt = gt->ggtt; 1082 const u64 slot = ggtt->error_capture.start; 1083 struct i915_vma_coredump *dst; 1084 struct sgt_iter iter; 1085 int ret; 1086 1087 might_sleep(); 1088 1089 if (!vma_res || !vma_res->bi.pages || !compress) 1090 return NULL; 1091 1092 dst = kmalloc(sizeof(*dst), ALLOW_FAIL); 1093 if (!dst) 1094 return NULL; 1095 1096 if (!compress_start(compress)) { 1097 kfree(dst); 1098 return NULL; 1099 } 1100 1101 INIT_LIST_HEAD(&dst->page_list); 1102 strcpy(dst->name, name); 1103 dst->next = NULL; 1104 1105 dst->gtt_offset = vma_res->start; 1106 dst->gtt_size = vma_res->node_size; 1107 dst->gtt_page_sizes = vma_res->page_sizes_gtt; 1108 dst->unused = 0; 1109 1110 ret = -EINVAL; 1111 if (drm_mm_node_allocated(&ggtt->error_capture)) { 1112 void __iomem *s; 1113 dma_addr_t dma; 1114 1115 for_each_sgt_daddr(dma, iter, vma_res->bi.pages) { 1116 mutex_lock(&ggtt->error_mutex); 1117 if (ggtt->vm.raw_insert_page) 1118 ggtt->vm.raw_insert_page(&ggtt->vm, dma, slot, 1119 I915_CACHE_NONE, 0); 1120 else 1121 ggtt->vm.insert_page(&ggtt->vm, dma, slot, 1122 I915_CACHE_NONE, 0); 1123 mb(); 1124 1125 s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE); 1126 ret = compress_page(compress, 1127 (void __force *)s, dst, 1128 true); 1129 io_mapping_unmap(s); 1130 1131 mb(); 1132 ggtt->vm.clear_range(&ggtt->vm, slot, PAGE_SIZE); 1133 mutex_unlock(&ggtt->error_mutex); 1134 if (ret) 1135 break; 1136 } 1137 } else if (vma_res->bi.lmem) { 1138 struct intel_memory_region *mem = vma_res->mr; 1139 dma_addr_t dma; 1140 1141 for_each_sgt_daddr(dma, iter, vma_res->bi.pages) { 1142 dma_addr_t offset = dma - mem->region.start; 1143 void __iomem *s; 1144 1145 if (offset + PAGE_SIZE > mem->io_size) { 1146 ret = -EINVAL; 1147 break; 1148 } 1149 1150 s = io_mapping_map_wc(&mem->iomap, offset, PAGE_SIZE); 1151 ret = compress_page(compress, 1152 (void __force *)s, dst, 1153 true); 1154 io_mapping_unmap(s); 1155 if (ret) 1156 break; 1157 } 1158 } else { 1159 struct page *page; 1160 1161 for_each_sgt_page(page, iter, vma_res->bi.pages) { 1162 void *s; 1163 1164 drm_clflush_pages(&page, 1); 1165 1166 s = kmap(page); 1167 ret = compress_page(compress, s, dst, false); 1168 kunmap(page); 1169 1170 drm_clflush_pages(&page, 1); 1171 1172 if (ret) 1173 break; 1174 } 1175 } 1176 1177 if (ret || compress_flush(compress, dst)) { 1178 struct page *page, *n; 1179 1180 list_for_each_entry_safe_reverse(page, n, &dst->page_list, lru) { 1181 list_del_init(&page->lru); 1182 pool_free(&compress->pool, page_address(page)); 1183 } 1184 1185 kfree(dst); 1186 dst = NULL; 1187 } 1188 compress_finish(compress); 1189 1190 return dst; 1191 } 1192 1193 static void gt_record_fences(struct intel_gt_coredump *gt) 1194 { 1195 struct i915_ggtt *ggtt = gt->_gt->ggtt; 1196 struct intel_uncore *uncore = gt->_gt->uncore; 1197 int i; 1198 1199 if (GRAPHICS_VER(uncore->i915) >= 6) { 1200 for (i = 0; i < ggtt->num_fences; i++) 1201 gt->fence[i] = 1202 intel_uncore_read64(uncore, 1203 FENCE_REG_GEN6_LO(i)); 1204 } else if (GRAPHICS_VER(uncore->i915) >= 4) { 1205 for (i = 0; i < ggtt->num_fences; i++) 1206 gt->fence[i] = 1207 intel_uncore_read64(uncore, 1208 FENCE_REG_965_LO(i)); 1209 } else { 1210 for (i = 0; i < ggtt->num_fences; i++) 1211 gt->fence[i] = 1212 intel_uncore_read(uncore, FENCE_REG(i)); 1213 } 1214 gt->nfence = i; 1215 } 1216 1217 static void engine_record_registers(struct intel_engine_coredump *ee) 1218 { 1219 const struct intel_engine_cs *engine = ee->engine; 1220 struct drm_i915_private *i915 = engine->i915; 1221 1222 if (GRAPHICS_VER(i915) >= 6) { 1223 ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL); 1224 1225 if (GRAPHICS_VER(i915) >= 12) 1226 ee->fault_reg = intel_uncore_read(engine->uncore, 1227 GEN12_RING_FAULT_REG); 1228 else if (GRAPHICS_VER(i915) >= 8) 1229 ee->fault_reg = intel_uncore_read(engine->uncore, 1230 GEN8_RING_FAULT_REG); 1231 else 1232 ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine); 1233 } 1234 1235 if (GRAPHICS_VER(i915) >= 4) { 1236 ee->esr = ENGINE_READ(engine, RING_ESR); 1237 ee->faddr = ENGINE_READ(engine, RING_DMA_FADD); 1238 ee->ipeir = ENGINE_READ(engine, RING_IPEIR); 1239 ee->ipehr = ENGINE_READ(engine, RING_IPEHR); 1240 ee->instps = ENGINE_READ(engine, RING_INSTPS); 1241 ee->bbaddr = ENGINE_READ(engine, RING_BBADDR); 1242 ee->ccid = ENGINE_READ(engine, CCID); 1243 if (GRAPHICS_VER(i915) >= 8) { 1244 ee->faddr |= (u64)ENGINE_READ(engine, RING_DMA_FADD_UDW) << 32; 1245 ee->bbaddr |= (u64)ENGINE_READ(engine, RING_BBADDR_UDW) << 32; 1246 } 1247 ee->bbstate = ENGINE_READ(engine, RING_BBSTATE); 1248 } else { 1249 ee->faddr = ENGINE_READ(engine, DMA_FADD_I8XX); 1250 ee->ipeir = ENGINE_READ(engine, IPEIR); 1251 ee->ipehr = ENGINE_READ(engine, IPEHR); 1252 } 1253 1254 if (GRAPHICS_VER(i915) >= 11) { 1255 ee->cmd_cctl = ENGINE_READ(engine, RING_CMD_CCTL); 1256 ee->cscmdop = ENGINE_READ(engine, RING_CSCMDOP); 1257 ee->ctx_sr_ctl = ENGINE_READ(engine, RING_CTX_SR_CTL); 1258 ee->dma_faddr_hi = ENGINE_READ(engine, RING_DMA_FADD_UDW); 1259 ee->dma_faddr_lo = ENGINE_READ(engine, RING_DMA_FADD); 1260 ee->nopid = ENGINE_READ(engine, RING_NOPID); 1261 ee->excc = ENGINE_READ(engine, RING_EXCC); 1262 } 1263 1264 intel_engine_get_instdone(engine, &ee->instdone); 1265 1266 ee->instpm = ENGINE_READ(engine, RING_INSTPM); 1267 ee->acthd = intel_engine_get_active_head(engine); 1268 ee->start = ENGINE_READ(engine, RING_START); 1269 ee->head = ENGINE_READ(engine, RING_HEAD); 1270 ee->tail = ENGINE_READ(engine, RING_TAIL); 1271 ee->ctl = ENGINE_READ(engine, RING_CTL); 1272 if (GRAPHICS_VER(i915) > 2) 1273 ee->mode = ENGINE_READ(engine, RING_MI_MODE); 1274 1275 if (!HWS_NEEDS_PHYSICAL(i915)) { 1276 i915_reg_t mmio; 1277 1278 if (GRAPHICS_VER(i915) == 7) { 1279 switch (engine->id) { 1280 default: 1281 MISSING_CASE(engine->id); 1282 fallthrough; 1283 case RCS0: 1284 mmio = RENDER_HWS_PGA_GEN7; 1285 break; 1286 case BCS0: 1287 mmio = BLT_HWS_PGA_GEN7; 1288 break; 1289 case VCS0: 1290 mmio = BSD_HWS_PGA_GEN7; 1291 break; 1292 case VECS0: 1293 mmio = VEBOX_HWS_PGA_GEN7; 1294 break; 1295 } 1296 } else if (GRAPHICS_VER(engine->i915) == 6) { 1297 mmio = RING_HWS_PGA_GEN6(engine->mmio_base); 1298 } else { 1299 /* XXX: gen8 returns to sanity */ 1300 mmio = RING_HWS_PGA(engine->mmio_base); 1301 } 1302 1303 ee->hws = intel_uncore_read(engine->uncore, mmio); 1304 } 1305 1306 ee->reset_count = i915_reset_engine_count(&i915->gpu_error, engine); 1307 1308 if (HAS_PPGTT(i915)) { 1309 int i; 1310 1311 ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7); 1312 1313 if (GRAPHICS_VER(i915) == 6) { 1314 ee->vm_info.pp_dir_base = 1315 ENGINE_READ(engine, RING_PP_DIR_BASE_READ); 1316 } else if (GRAPHICS_VER(i915) == 7) { 1317 ee->vm_info.pp_dir_base = 1318 ENGINE_READ(engine, RING_PP_DIR_BASE); 1319 } else if (GRAPHICS_VER(i915) >= 8) { 1320 u32 base = engine->mmio_base; 1321 1322 for (i = 0; i < 4; i++) { 1323 ee->vm_info.pdp[i] = 1324 intel_uncore_read(engine->uncore, 1325 GEN8_RING_PDP_UDW(base, i)); 1326 ee->vm_info.pdp[i] <<= 32; 1327 ee->vm_info.pdp[i] |= 1328 intel_uncore_read(engine->uncore, 1329 GEN8_RING_PDP_LDW(base, i)); 1330 } 1331 } 1332 } 1333 } 1334 1335 static void record_request(const struct i915_request *request, 1336 struct i915_request_coredump *erq) 1337 { 1338 erq->flags = request->fence.flags; 1339 erq->context = request->fence.context; 1340 erq->seqno = request->fence.seqno; 1341 erq->sched_attr = request->sched.attr; 1342 erq->head = request->head; 1343 erq->tail = request->tail; 1344 1345 erq->pid = 0; 1346 rcu_read_lock(); 1347 if (!intel_context_is_closed(request->context)) { 1348 const struct i915_gem_context *ctx; 1349 1350 ctx = rcu_dereference(request->context->gem_context); 1351 if (ctx) 1352 erq->pid = pid_nr(ctx->pid); 1353 } 1354 rcu_read_unlock(); 1355 } 1356 1357 static void engine_record_execlists(struct intel_engine_coredump *ee) 1358 { 1359 const struct intel_engine_execlists * const el = &ee->engine->execlists; 1360 struct i915_request * const *port = el->active; 1361 unsigned int n = 0; 1362 1363 while (*port) 1364 record_request(*port++, &ee->execlist[n++]); 1365 1366 ee->num_ports = n; 1367 } 1368 1369 static bool record_context(struct i915_gem_context_coredump *e, 1370 const struct i915_request *rq) 1371 { 1372 struct i915_gem_context *ctx; 1373 struct task_struct *task; 1374 bool simulated; 1375 1376 rcu_read_lock(); 1377 ctx = rcu_dereference(rq->context->gem_context); 1378 if (ctx && !kref_get_unless_zero(&ctx->ref)) 1379 ctx = NULL; 1380 rcu_read_unlock(); 1381 if (!ctx) 1382 return true; 1383 1384 rcu_read_lock(); 1385 task = pid_task(ctx->pid, PIDTYPE_PID); 1386 if (task) { 1387 strcpy(e->comm, task->comm); 1388 e->pid = task->pid; 1389 } 1390 rcu_read_unlock(); 1391 1392 e->sched_attr = ctx->sched; 1393 e->guilty = atomic_read(&ctx->guilty_count); 1394 e->active = atomic_read(&ctx->active_count); 1395 1396 e->total_runtime = intel_context_get_total_runtime_ns(rq->context); 1397 e->avg_runtime = intel_context_get_avg_runtime_ns(rq->context); 1398 1399 simulated = i915_gem_context_no_error_capture(ctx); 1400 1401 i915_gem_context_put(ctx); 1402 return simulated; 1403 } 1404 1405 struct intel_engine_capture_vma { 1406 struct intel_engine_capture_vma *next; 1407 struct i915_vma_resource *vma_res; 1408 char name[16]; 1409 bool lockdep_cookie; 1410 }; 1411 1412 static struct intel_engine_capture_vma * 1413 capture_vma_snapshot(struct intel_engine_capture_vma *next, 1414 struct i915_vma_resource *vma_res, 1415 gfp_t gfp, const char *name) 1416 { 1417 struct intel_engine_capture_vma *c; 1418 1419 if (!vma_res) 1420 return next; 1421 1422 c = kmalloc(sizeof(*c), gfp); 1423 if (!c) 1424 return next; 1425 1426 if (!i915_vma_resource_hold(vma_res, &c->lockdep_cookie)) { 1427 kfree(c); 1428 return next; 1429 } 1430 1431 strcpy(c->name, name); 1432 c->vma_res = i915_vma_resource_get(vma_res); 1433 1434 c->next = next; 1435 return c; 1436 } 1437 1438 static struct intel_engine_capture_vma * 1439 capture_vma(struct intel_engine_capture_vma *next, 1440 struct i915_vma *vma, 1441 const char *name, 1442 gfp_t gfp) 1443 { 1444 if (!vma) 1445 return next; 1446 1447 /* 1448 * If the vma isn't pinned, then the vma should be snapshotted 1449 * to a struct i915_vma_snapshot at command submission time. 1450 * Not here. 1451 */ 1452 if (GEM_WARN_ON(!i915_vma_is_pinned(vma))) 1453 return next; 1454 1455 next = capture_vma_snapshot(next, vma->resource, gfp, name); 1456 1457 return next; 1458 } 1459 1460 static struct intel_engine_capture_vma * 1461 capture_user(struct intel_engine_capture_vma *capture, 1462 const struct i915_request *rq, 1463 gfp_t gfp) 1464 { 1465 struct i915_capture_list *c; 1466 1467 for (c = rq->capture_list; c; c = c->next) 1468 capture = capture_vma_snapshot(capture, c->vma_res, gfp, 1469 "user"); 1470 1471 return capture; 1472 } 1473 1474 static void add_vma(struct intel_engine_coredump *ee, 1475 struct i915_vma_coredump *vma) 1476 { 1477 if (vma) { 1478 vma->next = ee->vma; 1479 ee->vma = vma; 1480 } 1481 } 1482 1483 static struct i915_vma_coredump * 1484 create_vma_coredump(const struct intel_gt *gt, struct i915_vma *vma, 1485 const char *name, struct i915_vma_compress *compress) 1486 { 1487 struct i915_vma_coredump *ret = NULL; 1488 struct i915_vma_resource *vma_res; 1489 bool lockdep_cookie; 1490 1491 if (!vma) 1492 return NULL; 1493 1494 vma_res = vma->resource; 1495 1496 if (i915_vma_resource_hold(vma_res, &lockdep_cookie)) { 1497 ret = i915_vma_coredump_create(gt, vma_res, compress, name); 1498 i915_vma_resource_unhold(vma_res, lockdep_cookie); 1499 } 1500 1501 return ret; 1502 } 1503 1504 static void add_vma_coredump(struct intel_engine_coredump *ee, 1505 const struct intel_gt *gt, 1506 struct i915_vma *vma, 1507 const char *name, 1508 struct i915_vma_compress *compress) 1509 { 1510 add_vma(ee, create_vma_coredump(gt, vma, name, compress)); 1511 } 1512 1513 struct intel_engine_coredump * 1514 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp, u32 dump_flags) 1515 { 1516 struct intel_engine_coredump *ee; 1517 1518 ee = kzalloc(sizeof(*ee), gfp); 1519 if (!ee) 1520 return NULL; 1521 1522 ee->engine = engine; 1523 1524 if (!(dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE)) { 1525 engine_record_registers(ee); 1526 engine_record_execlists(ee); 1527 } 1528 1529 return ee; 1530 } 1531 1532 struct intel_engine_capture_vma * 1533 intel_engine_coredump_add_request(struct intel_engine_coredump *ee, 1534 struct i915_request *rq, 1535 gfp_t gfp) 1536 { 1537 struct intel_engine_capture_vma *vma = NULL; 1538 1539 ee->simulated |= record_context(&ee->context, rq); 1540 if (ee->simulated) 1541 return NULL; 1542 1543 /* 1544 * We need to copy these to an anonymous buffer 1545 * as the simplest method to avoid being overwritten 1546 * by userspace. 1547 */ 1548 vma = capture_vma_snapshot(vma, rq->batch_res, gfp, "batch"); 1549 vma = capture_user(vma, rq, gfp); 1550 vma = capture_vma(vma, rq->ring->vma, "ring", gfp); 1551 vma = capture_vma(vma, rq->context->state, "HW context", gfp); 1552 1553 ee->rq_head = rq->head; 1554 ee->rq_post = rq->postfix; 1555 ee->rq_tail = rq->tail; 1556 1557 return vma; 1558 } 1559 1560 void 1561 intel_engine_coredump_add_vma(struct intel_engine_coredump *ee, 1562 struct intel_engine_capture_vma *capture, 1563 struct i915_vma_compress *compress) 1564 { 1565 const struct intel_engine_cs *engine = ee->engine; 1566 1567 while (capture) { 1568 struct intel_engine_capture_vma *this = capture; 1569 struct i915_vma_resource *vma_res = this->vma_res; 1570 1571 add_vma(ee, 1572 i915_vma_coredump_create(engine->gt, vma_res, 1573 compress, this->name)); 1574 1575 i915_vma_resource_unhold(vma_res, this->lockdep_cookie); 1576 i915_vma_resource_put(vma_res); 1577 1578 capture = this->next; 1579 kfree(this); 1580 } 1581 1582 add_vma_coredump(ee, engine->gt, engine->status_page.vma, 1583 "HW Status", compress); 1584 1585 add_vma_coredump(ee, engine->gt, engine->wa_ctx.vma, 1586 "WA context", compress); 1587 } 1588 1589 static struct intel_engine_coredump * 1590 capture_engine(struct intel_engine_cs *engine, 1591 struct i915_vma_compress *compress, 1592 u32 dump_flags) 1593 { 1594 struct intel_engine_capture_vma *capture = NULL; 1595 struct intel_engine_coredump *ee; 1596 struct intel_context *ce; 1597 struct i915_request *rq = NULL; 1598 unsigned long flags; 1599 1600 ee = intel_engine_coredump_alloc(engine, ALLOW_FAIL, dump_flags); 1601 if (!ee) 1602 return NULL; 1603 1604 ce = intel_engine_get_hung_context(engine); 1605 if (ce) { 1606 intel_engine_clear_hung_context(engine); 1607 rq = intel_context_find_active_request(ce); 1608 if (!rq || !i915_request_started(rq)) 1609 goto no_request_capture; 1610 } else { 1611 /* 1612 * Getting here with GuC enabled means it is a forced error capture 1613 * with no actual hang. So, no need to attempt the execlist search. 1614 */ 1615 if (!intel_uc_uses_guc_submission(&engine->gt->uc)) { 1616 spin_lock_irqsave(&engine->sched_engine->lock, flags); 1617 rq = intel_engine_execlist_find_hung_request(engine); 1618 spin_unlock_irqrestore(&engine->sched_engine->lock, 1619 flags); 1620 } 1621 } 1622 if (rq) 1623 rq = i915_request_get_rcu(rq); 1624 1625 if (!rq) 1626 goto no_request_capture; 1627 1628 capture = intel_engine_coredump_add_request(ee, rq, ATOMIC_MAYFAIL); 1629 if (!capture) { 1630 i915_request_put(rq); 1631 goto no_request_capture; 1632 } 1633 if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE) 1634 intel_guc_capture_get_matching_node(engine->gt, ee, ce); 1635 1636 intel_engine_coredump_add_vma(ee, capture, compress); 1637 i915_request_put(rq); 1638 1639 return ee; 1640 1641 no_request_capture: 1642 kfree(ee); 1643 return NULL; 1644 } 1645 1646 static void 1647 gt_record_engines(struct intel_gt_coredump *gt, 1648 intel_engine_mask_t engine_mask, 1649 struct i915_vma_compress *compress, 1650 u32 dump_flags) 1651 { 1652 struct intel_engine_cs *engine; 1653 enum intel_engine_id id; 1654 1655 for_each_engine(engine, gt->_gt, id) { 1656 struct intel_engine_coredump *ee; 1657 1658 /* Refill our page pool before entering atomic section */ 1659 pool_refill(&compress->pool, ALLOW_FAIL); 1660 1661 ee = capture_engine(engine, compress, dump_flags); 1662 if (!ee) 1663 continue; 1664 1665 ee->hung = engine->mask & engine_mask; 1666 1667 gt->simulated |= ee->simulated; 1668 if (ee->simulated) { 1669 if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE) 1670 intel_guc_capture_free_node(ee); 1671 kfree(ee); 1672 continue; 1673 } 1674 1675 ee->next = gt->engine; 1676 gt->engine = ee; 1677 } 1678 } 1679 1680 static void gt_record_guc_ctb(struct intel_ctb_coredump *saved, 1681 const struct intel_guc_ct_buffer *ctb, 1682 const void *blob_ptr, struct intel_guc *guc) 1683 { 1684 if (!ctb || !ctb->desc) 1685 return; 1686 1687 saved->raw_status = ctb->desc->status; 1688 saved->raw_head = ctb->desc->head; 1689 saved->raw_tail = ctb->desc->tail; 1690 saved->head = ctb->head; 1691 saved->tail = ctb->tail; 1692 saved->size = ctb->size; 1693 saved->desc_offset = ((void *)ctb->desc) - blob_ptr; 1694 saved->cmds_offset = ((void *)ctb->cmds) - blob_ptr; 1695 } 1696 1697 static struct intel_uc_coredump * 1698 gt_record_uc(struct intel_gt_coredump *gt, 1699 struct i915_vma_compress *compress) 1700 { 1701 const struct intel_uc *uc = >->_gt->uc; 1702 struct intel_uc_coredump *error_uc; 1703 1704 error_uc = kzalloc(sizeof(*error_uc), ALLOW_FAIL); 1705 if (!error_uc) 1706 return NULL; 1707 1708 memcpy(&error_uc->guc_fw, &uc->guc.fw, sizeof(uc->guc.fw)); 1709 memcpy(&error_uc->huc_fw, &uc->huc.fw, sizeof(uc->huc.fw)); 1710 1711 error_uc->guc_fw.file_selected.path = kstrdup(uc->guc.fw.file_selected.path, ALLOW_FAIL); 1712 error_uc->huc_fw.file_selected.path = kstrdup(uc->huc.fw.file_selected.path, ALLOW_FAIL); 1713 error_uc->guc_fw.file_wanted.path = kstrdup(uc->guc.fw.file_wanted.path, ALLOW_FAIL); 1714 error_uc->huc_fw.file_wanted.path = kstrdup(uc->huc.fw.file_wanted.path, ALLOW_FAIL); 1715 1716 /* 1717 * Save the GuC log and include a timestamp reference for converting the 1718 * log times to system times (in conjunction with the error->boottime and 1719 * gt->clock_frequency fields saved elsewhere). 1720 */ 1721 error_uc->guc.timestamp = intel_uncore_read(gt->_gt->uncore, GUCPMTIMESTAMP); 1722 error_uc->guc.vma_log = create_vma_coredump(gt->_gt, uc->guc.log.vma, 1723 "GuC log buffer", compress); 1724 error_uc->guc.vma_ctb = create_vma_coredump(gt->_gt, uc->guc.ct.vma, 1725 "GuC CT buffer", compress); 1726 error_uc->guc.last_fence = uc->guc.ct.requests.last_fence; 1727 gt_record_guc_ctb(error_uc->guc.ctb + 0, &uc->guc.ct.ctbs.send, 1728 uc->guc.ct.ctbs.send.desc, (struct intel_guc *)&uc->guc); 1729 gt_record_guc_ctb(error_uc->guc.ctb + 1, &uc->guc.ct.ctbs.recv, 1730 uc->guc.ct.ctbs.send.desc, (struct intel_guc *)&uc->guc); 1731 1732 return error_uc; 1733 } 1734 1735 /* Capture display registers. */ 1736 static void gt_record_display_regs(struct intel_gt_coredump *gt) 1737 { 1738 struct intel_uncore *uncore = gt->_gt->uncore; 1739 struct drm_i915_private *i915 = uncore->i915; 1740 1741 if (GRAPHICS_VER(i915) >= 6) 1742 gt->derrmr = intel_uncore_read(uncore, DERRMR); 1743 1744 if (GRAPHICS_VER(i915) >= 8) 1745 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER); 1746 else if (IS_VALLEYVIEW(i915)) 1747 gt->ier = intel_uncore_read(uncore, VLV_IER); 1748 else if (HAS_PCH_SPLIT(i915)) 1749 gt->ier = intel_uncore_read(uncore, DEIER); 1750 else if (GRAPHICS_VER(i915) == 2) 1751 gt->ier = intel_uncore_read16(uncore, GEN2_IER); 1752 else 1753 gt->ier = intel_uncore_read(uncore, GEN2_IER); 1754 } 1755 1756 /* Capture all other registers that GuC doesn't capture. */ 1757 static void gt_record_global_nonguc_regs(struct intel_gt_coredump *gt) 1758 { 1759 struct intel_uncore *uncore = gt->_gt->uncore; 1760 struct drm_i915_private *i915 = uncore->i915; 1761 int i; 1762 1763 if (IS_VALLEYVIEW(i915)) { 1764 gt->gtier[0] = intel_uncore_read(uncore, GTIER); 1765 gt->ngtier = 1; 1766 } else if (GRAPHICS_VER(i915) >= 11) { 1767 gt->gtier[0] = 1768 intel_uncore_read(uncore, 1769 GEN11_RENDER_COPY_INTR_ENABLE); 1770 gt->gtier[1] = 1771 intel_uncore_read(uncore, GEN11_VCS_VECS_INTR_ENABLE); 1772 gt->gtier[2] = 1773 intel_uncore_read(uncore, GEN11_GUC_SG_INTR_ENABLE); 1774 gt->gtier[3] = 1775 intel_uncore_read(uncore, 1776 GEN11_GPM_WGBOXPERF_INTR_ENABLE); 1777 gt->gtier[4] = 1778 intel_uncore_read(uncore, 1779 GEN11_CRYPTO_RSVD_INTR_ENABLE); 1780 gt->gtier[5] = 1781 intel_uncore_read(uncore, 1782 GEN11_GUNIT_CSME_INTR_ENABLE); 1783 gt->ngtier = 6; 1784 } else if (GRAPHICS_VER(i915) >= 8) { 1785 for (i = 0; i < 4; i++) 1786 gt->gtier[i] = 1787 intel_uncore_read(uncore, GEN8_GT_IER(i)); 1788 gt->ngtier = 4; 1789 } else if (HAS_PCH_SPLIT(i915)) { 1790 gt->gtier[0] = intel_uncore_read(uncore, GTIER); 1791 gt->ngtier = 1; 1792 } 1793 1794 gt->eir = intel_uncore_read(uncore, EIR); 1795 gt->pgtbl_er = intel_uncore_read(uncore, PGTBL_ER); 1796 } 1797 1798 /* 1799 * Capture all registers that relate to workload submission. 1800 * NOTE: In GuC submission, when GuC resets an engine, it can dump these for us 1801 */ 1802 static void gt_record_global_regs(struct intel_gt_coredump *gt) 1803 { 1804 struct intel_uncore *uncore = gt->_gt->uncore; 1805 struct drm_i915_private *i915 = uncore->i915; 1806 int i; 1807 1808 /* 1809 * General organization 1810 * 1. Registers specific to a single generation 1811 * 2. Registers which belong to multiple generations 1812 * 3. Feature specific registers. 1813 * 4. Everything else 1814 * Please try to follow the order. 1815 */ 1816 1817 /* 1: Registers specific to a single generation */ 1818 if (IS_VALLEYVIEW(i915)) 1819 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_VLV); 1820 1821 if (GRAPHICS_VER(i915) == 7) 1822 gt->err_int = intel_uncore_read(uncore, GEN7_ERR_INT); 1823 1824 if (GRAPHICS_VER(i915) >= 12) { 1825 gt->fault_data0 = intel_uncore_read(uncore, 1826 GEN12_FAULT_TLB_DATA0); 1827 gt->fault_data1 = intel_uncore_read(uncore, 1828 GEN12_FAULT_TLB_DATA1); 1829 } else if (GRAPHICS_VER(i915) >= 8) { 1830 gt->fault_data0 = intel_uncore_read(uncore, 1831 GEN8_FAULT_TLB_DATA0); 1832 gt->fault_data1 = intel_uncore_read(uncore, 1833 GEN8_FAULT_TLB_DATA1); 1834 } 1835 1836 if (GRAPHICS_VER(i915) == 6) { 1837 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE); 1838 gt->gab_ctl = intel_uncore_read(uncore, GAB_CTL); 1839 gt->gfx_mode = intel_uncore_read(uncore, GFX_MODE); 1840 } 1841 1842 /* 2: Registers which belong to multiple generations */ 1843 if (GRAPHICS_VER(i915) >= 7) 1844 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_MT); 1845 1846 if (GRAPHICS_VER(i915) >= 6) { 1847 if (GRAPHICS_VER(i915) < 12) { 1848 gt->error = intel_uncore_read(uncore, ERROR_GEN6); 1849 gt->done_reg = intel_uncore_read(uncore, DONE_REG); 1850 } 1851 } 1852 1853 /* 3: Feature specific registers */ 1854 if (IS_GRAPHICS_VER(i915, 6, 7)) { 1855 gt->gam_ecochk = intel_uncore_read(uncore, GAM_ECOCHK); 1856 gt->gac_eco = intel_uncore_read(uncore, GAC_ECO_BITS); 1857 } 1858 1859 if (IS_GRAPHICS_VER(i915, 8, 11)) 1860 gt->gtt_cache = intel_uncore_read(uncore, HSW_GTT_CACHE_EN); 1861 1862 if (GRAPHICS_VER(i915) == 12) 1863 gt->aux_err = intel_uncore_read(uncore, GEN12_AUX_ERR_DBG); 1864 1865 if (GRAPHICS_VER(i915) >= 12) { 1866 for (i = 0; i < I915_MAX_SFC; i++) { 1867 /* 1868 * SFC_DONE resides in the VD forcewake domain, so it 1869 * only exists if the corresponding VCS engine is 1870 * present. 1871 */ 1872 if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 || 1873 !HAS_ENGINE(gt->_gt, _VCS(i * 2))) 1874 continue; 1875 1876 gt->sfc_done[i] = 1877 intel_uncore_read(uncore, GEN12_SFC_DONE(i)); 1878 } 1879 1880 gt->gam_done = intel_uncore_read(uncore, GEN12_GAM_DONE); 1881 } 1882 } 1883 1884 static void gt_record_info(struct intel_gt_coredump *gt) 1885 { 1886 memcpy(>->info, >->_gt->info, sizeof(struct intel_gt_info)); 1887 gt->clock_frequency = gt->_gt->clock_frequency; 1888 gt->clock_period_ns = gt->_gt->clock_period_ns; 1889 } 1890 1891 /* 1892 * Generate a semi-unique error code. The code is not meant to have meaning, The 1893 * code's only purpose is to try to prevent false duplicated bug reports by 1894 * grossly estimating a GPU error state. 1895 * 1896 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine 1897 * the hang if we could strip the GTT offset information from it. 1898 * 1899 * It's only a small step better than a random number in its current form. 1900 */ 1901 static u32 generate_ecode(const struct intel_engine_coredump *ee) 1902 { 1903 /* 1904 * IPEHR would be an ideal way to detect errors, as it's the gross 1905 * measure of "the command that hung." However, has some very common 1906 * synchronization commands which almost always appear in the case 1907 * strictly a client bug. Use instdone to differentiate those some. 1908 */ 1909 return ee ? ee->ipehr ^ ee->instdone.instdone : 0; 1910 } 1911 1912 static const char *error_msg(struct i915_gpu_coredump *error) 1913 { 1914 struct intel_engine_coredump *first = NULL; 1915 unsigned int hung_classes = 0; 1916 struct intel_gt_coredump *gt; 1917 int len; 1918 1919 for (gt = error->gt; gt; gt = gt->next) { 1920 struct intel_engine_coredump *cs; 1921 1922 for (cs = gt->engine; cs; cs = cs->next) { 1923 if (cs->hung) { 1924 hung_classes |= BIT(cs->engine->uabi_class); 1925 if (!first) 1926 first = cs; 1927 } 1928 } 1929 } 1930 1931 len = scnprintf(error->error_msg, sizeof(error->error_msg), 1932 "GPU HANG: ecode %d:%x:%08x", 1933 GRAPHICS_VER(error->i915), hung_classes, 1934 generate_ecode(first)); 1935 if (first && first->context.pid) { 1936 /* Just show the first executing process, more is confusing */ 1937 len += scnprintf(error->error_msg + len, 1938 sizeof(error->error_msg) - len, 1939 ", in %s [%d]", 1940 first->context.comm, first->context.pid); 1941 } 1942 1943 return error->error_msg; 1944 } 1945 1946 static void capture_gen(struct i915_gpu_coredump *error) 1947 { 1948 struct drm_i915_private *i915 = error->i915; 1949 1950 error->wakelock = atomic_read(&i915->runtime_pm.wakeref_count); 1951 error->suspended = i915->runtime_pm.suspended; 1952 1953 error->iommu = i915_vtd_active(i915); 1954 error->reset_count = i915_reset_count(&i915->gpu_error); 1955 error->suspend_count = i915->suspend_count; 1956 1957 i915_params_copy(&error->params, &i915->params); 1958 memcpy(&error->device_info, 1959 INTEL_INFO(i915), 1960 sizeof(error->device_info)); 1961 memcpy(&error->runtime_info, 1962 RUNTIME_INFO(i915), 1963 sizeof(error->runtime_info)); 1964 error->driver_caps = i915->caps; 1965 } 1966 1967 struct i915_gpu_coredump * 1968 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp) 1969 { 1970 struct i915_gpu_coredump *error; 1971 1972 if (!i915->params.error_capture) 1973 return NULL; 1974 1975 error = kzalloc(sizeof(*error), gfp); 1976 if (!error) 1977 return NULL; 1978 1979 kref_init(&error->ref); 1980 error->i915 = i915; 1981 1982 error->time = ktime_get_real(); 1983 error->boottime = ktime_get_boottime(); 1984 error->uptime = ktime_sub(ktime_get(), to_gt(i915)->last_init_time); 1985 error->capture = jiffies; 1986 1987 capture_gen(error); 1988 1989 return error; 1990 } 1991 1992 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x)) 1993 1994 struct intel_gt_coredump * 1995 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp, u32 dump_flags) 1996 { 1997 struct intel_gt_coredump *gc; 1998 1999 gc = kzalloc(sizeof(*gc), gfp); 2000 if (!gc) 2001 return NULL; 2002 2003 gc->_gt = gt; 2004 gc->awake = intel_gt_pm_is_awake(gt); 2005 2006 gt_record_display_regs(gc); 2007 gt_record_global_nonguc_regs(gc); 2008 2009 /* 2010 * GuC dumps global, eng-class and eng-instance registers 2011 * (that can change as part of engine state during execution) 2012 * before an engine is reset due to a hung context. 2013 * GuC captures and reports all three groups of registers 2014 * together as a single set before the engine is reset. 2015 * Thus, if GuC triggered the context reset we retrieve 2016 * the register values as part of gt_record_engines. 2017 */ 2018 if (!(dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE)) 2019 gt_record_global_regs(gc); 2020 2021 gt_record_fences(gc); 2022 2023 return gc; 2024 } 2025 2026 struct i915_vma_compress * 2027 i915_vma_capture_prepare(struct intel_gt_coredump *gt) 2028 { 2029 struct i915_vma_compress *compress; 2030 2031 compress = kmalloc(sizeof(*compress), ALLOW_FAIL); 2032 if (!compress) 2033 return NULL; 2034 2035 if (!compress_init(compress)) { 2036 kfree(compress); 2037 return NULL; 2038 } 2039 2040 return compress; 2041 } 2042 2043 void i915_vma_capture_finish(struct intel_gt_coredump *gt, 2044 struct i915_vma_compress *compress) 2045 { 2046 if (!compress) 2047 return; 2048 2049 compress_fini(compress); 2050 kfree(compress); 2051 } 2052 2053 static struct i915_gpu_coredump * 2054 __i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags) 2055 { 2056 struct drm_i915_private *i915 = gt->i915; 2057 struct i915_gpu_coredump *error; 2058 2059 /* Check if GPU capture has been disabled */ 2060 error = READ_ONCE(i915->gpu_error.first_error); 2061 if (IS_ERR(error)) 2062 return error; 2063 2064 error = i915_gpu_coredump_alloc(i915, ALLOW_FAIL); 2065 if (!error) 2066 return ERR_PTR(-ENOMEM); 2067 2068 error->gt = intel_gt_coredump_alloc(gt, ALLOW_FAIL, dump_flags); 2069 if (error->gt) { 2070 struct i915_vma_compress *compress; 2071 2072 compress = i915_vma_capture_prepare(error->gt); 2073 if (!compress) { 2074 kfree(error->gt); 2075 kfree(error); 2076 return ERR_PTR(-ENOMEM); 2077 } 2078 2079 if (INTEL_INFO(i915)->has_gt_uc) { 2080 error->gt->uc = gt_record_uc(error->gt, compress); 2081 if (error->gt->uc) { 2082 if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE) 2083 error->gt->uc->guc.is_guc_capture = true; 2084 else 2085 GEM_BUG_ON(error->gt->uc->guc.is_guc_capture); 2086 } 2087 } 2088 2089 gt_record_info(error->gt); 2090 gt_record_engines(error->gt, engine_mask, compress, dump_flags); 2091 2092 2093 i915_vma_capture_finish(error->gt, compress); 2094 2095 error->simulated |= error->gt->simulated; 2096 } 2097 2098 error->overlay = intel_overlay_capture_error_state(i915); 2099 2100 return error; 2101 } 2102 2103 struct i915_gpu_coredump * 2104 i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags) 2105 { 2106 static DEFINE_MUTEX(capture_mutex); 2107 int ret = mutex_lock_interruptible(&capture_mutex); 2108 struct i915_gpu_coredump *dump; 2109 2110 if (ret) 2111 return ERR_PTR(ret); 2112 2113 dump = __i915_gpu_coredump(gt, engine_mask, dump_flags); 2114 mutex_unlock(&capture_mutex); 2115 2116 return dump; 2117 } 2118 2119 void i915_error_state_store(struct i915_gpu_coredump *error) 2120 { 2121 struct drm_i915_private *i915; 2122 static bool warned; 2123 2124 if (IS_ERR_OR_NULL(error)) 2125 return; 2126 2127 i915 = error->i915; 2128 drm_info(&i915->drm, "%s\n", error_msg(error)); 2129 2130 if (error->simulated || 2131 cmpxchg(&i915->gpu_error.first_error, NULL, error)) 2132 return; 2133 2134 i915_gpu_coredump_get(error); 2135 2136 if (!xchg(&warned, true) && 2137 ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) { 2138 pr_info("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n"); 2139 pr_info("Please file a _new_ bug report at https://gitlab.freedesktop.org/drm/intel/issues/new.\n"); 2140 pr_info("Please see https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs for details.\n"); 2141 pr_info("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n"); 2142 pr_info("The GPU crash dump is required to analyze GPU hangs, so please always attach it.\n"); 2143 pr_info("GPU crash dump saved to /sys/class/drm/card%d/error\n", 2144 i915->drm.primary->index); 2145 } 2146 } 2147 2148 /** 2149 * i915_capture_error_state - capture an error record for later analysis 2150 * @gt: intel_gt which originated the hang 2151 * @engine_mask: hung engines 2152 * 2153 * 2154 * Should be called when an error is detected (either a hang or an error 2155 * interrupt) to capture error state from the time of the error. Fills 2156 * out a structure which becomes available in debugfs for user level tools 2157 * to pick up. 2158 */ 2159 void i915_capture_error_state(struct intel_gt *gt, 2160 intel_engine_mask_t engine_mask, u32 dump_flags) 2161 { 2162 struct i915_gpu_coredump *error; 2163 2164 error = i915_gpu_coredump(gt, engine_mask, dump_flags); 2165 if (IS_ERR(error)) { 2166 cmpxchg(>->i915->gpu_error.first_error, NULL, error); 2167 return; 2168 } 2169 2170 i915_error_state_store(error); 2171 i915_gpu_coredump_put(error); 2172 } 2173 2174 struct i915_gpu_coredump * 2175 i915_first_error_state(struct drm_i915_private *i915) 2176 { 2177 struct i915_gpu_coredump *error; 2178 2179 spin_lock_irq(&i915->gpu_error.lock); 2180 error = i915->gpu_error.first_error; 2181 if (!IS_ERR_OR_NULL(error)) 2182 i915_gpu_coredump_get(error); 2183 spin_unlock_irq(&i915->gpu_error.lock); 2184 2185 return error; 2186 } 2187 2188 void i915_reset_error_state(struct drm_i915_private *i915) 2189 { 2190 struct i915_gpu_coredump *error; 2191 2192 spin_lock_irq(&i915->gpu_error.lock); 2193 error = i915->gpu_error.first_error; 2194 if (error != ERR_PTR(-ENODEV)) /* if disabled, always disabled */ 2195 i915->gpu_error.first_error = NULL; 2196 spin_unlock_irq(&i915->gpu_error.lock); 2197 2198 if (!IS_ERR_OR_NULL(error)) 2199 i915_gpu_coredump_put(error); 2200 } 2201 2202 void i915_disable_error_state(struct drm_i915_private *i915, int err) 2203 { 2204 spin_lock_irq(&i915->gpu_error.lock); 2205 if (!i915->gpu_error.first_error) 2206 i915->gpu_error.first_error = ERR_PTR(err); 2207 spin_unlock_irq(&i915->gpu_error.lock); 2208 } 2209