1 /* 2 * Copyright (c) 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * Mika Kuoppala <mika.kuoppala@intel.com> 27 * 28 */ 29 30 #include <linux/ascii85.h> 31 #include <linux/nmi.h> 32 #include <linux/pagevec.h> 33 #include <linux/scatterlist.h> 34 #include <linux/utsname.h> 35 #include <linux/zlib.h> 36 37 #include <drm/drm_print.h> 38 39 #include "display/intel_atomic.h" 40 #include "display/intel_overlay.h" 41 42 #include "gem/i915_gem_context.h" 43 #include "gem/i915_gem_lmem.h" 44 45 #include "i915_drv.h" 46 #include "i915_gpu_error.h" 47 #include "i915_memcpy.h" 48 #include "i915_scatterlist.h" 49 #include "intel_csr.h" 50 51 #define ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN) 52 #define ATOMIC_MAYFAIL (GFP_ATOMIC | __GFP_NOWARN) 53 54 static void __sg_set_buf(struct scatterlist *sg, 55 void *addr, unsigned int len, loff_t it) 56 { 57 sg->page_link = (unsigned long)virt_to_page(addr); 58 sg->offset = offset_in_page(addr); 59 sg->length = len; 60 sg->dma_address = it; 61 } 62 63 static bool __i915_error_grow(struct drm_i915_error_state_buf *e, size_t len) 64 { 65 if (!len) 66 return false; 67 68 if (e->bytes + len + 1 <= e->size) 69 return true; 70 71 if (e->bytes) { 72 __sg_set_buf(e->cur++, e->buf, e->bytes, e->iter); 73 e->iter += e->bytes; 74 e->buf = NULL; 75 e->bytes = 0; 76 } 77 78 if (e->cur == e->end) { 79 struct scatterlist *sgl; 80 81 sgl = (typeof(sgl))__get_free_page(ALLOW_FAIL); 82 if (!sgl) { 83 e->err = -ENOMEM; 84 return false; 85 } 86 87 if (e->cur) { 88 e->cur->offset = 0; 89 e->cur->length = 0; 90 e->cur->page_link = 91 (unsigned long)sgl | SG_CHAIN; 92 } else { 93 e->sgl = sgl; 94 } 95 96 e->cur = sgl; 97 e->end = sgl + SG_MAX_SINGLE_ALLOC - 1; 98 } 99 100 e->size = ALIGN(len + 1, SZ_64K); 101 e->buf = kmalloc(e->size, ALLOW_FAIL); 102 if (!e->buf) { 103 e->size = PAGE_ALIGN(len + 1); 104 e->buf = kmalloc(e->size, GFP_KERNEL); 105 } 106 if (!e->buf) { 107 e->err = -ENOMEM; 108 return false; 109 } 110 111 return true; 112 } 113 114 __printf(2, 0) 115 static void i915_error_vprintf(struct drm_i915_error_state_buf *e, 116 const char *fmt, va_list args) 117 { 118 va_list ap; 119 int len; 120 121 if (e->err) 122 return; 123 124 va_copy(ap, args); 125 len = vsnprintf(NULL, 0, fmt, ap); 126 va_end(ap); 127 if (len <= 0) { 128 e->err = len; 129 return; 130 } 131 132 if (!__i915_error_grow(e, len)) 133 return; 134 135 GEM_BUG_ON(e->bytes >= e->size); 136 len = vscnprintf(e->buf + e->bytes, e->size - e->bytes, fmt, args); 137 if (len < 0) { 138 e->err = len; 139 return; 140 } 141 e->bytes += len; 142 } 143 144 static void i915_error_puts(struct drm_i915_error_state_buf *e, const char *str) 145 { 146 unsigned len; 147 148 if (e->err || !str) 149 return; 150 151 len = strlen(str); 152 if (!__i915_error_grow(e, len)) 153 return; 154 155 GEM_BUG_ON(e->bytes + len > e->size); 156 memcpy(e->buf + e->bytes, str, len); 157 e->bytes += len; 158 } 159 160 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) 161 #define err_puts(e, s) i915_error_puts(e, s) 162 163 static void __i915_printfn_error(struct drm_printer *p, struct va_format *vaf) 164 { 165 i915_error_vprintf(p->arg, vaf->fmt, *vaf->va); 166 } 167 168 static inline struct drm_printer 169 i915_error_printer(struct drm_i915_error_state_buf *e) 170 { 171 struct drm_printer p = { 172 .printfn = __i915_printfn_error, 173 .arg = e, 174 }; 175 return p; 176 } 177 178 /* single threaded page allocator with a reserved stash for emergencies */ 179 static void pool_fini(struct pagevec *pv) 180 { 181 pagevec_release(pv); 182 } 183 184 static int pool_refill(struct pagevec *pv, gfp_t gfp) 185 { 186 while (pagevec_space(pv)) { 187 struct page *p; 188 189 p = alloc_page(gfp); 190 if (!p) 191 return -ENOMEM; 192 193 pagevec_add(pv, p); 194 } 195 196 return 0; 197 } 198 199 static int pool_init(struct pagevec *pv, gfp_t gfp) 200 { 201 int err; 202 203 pagevec_init(pv); 204 205 err = pool_refill(pv, gfp); 206 if (err) 207 pool_fini(pv); 208 209 return err; 210 } 211 212 static void *pool_alloc(struct pagevec *pv, gfp_t gfp) 213 { 214 struct page *p; 215 216 p = alloc_page(gfp); 217 if (!p && pagevec_count(pv)) 218 p = pv->pages[--pv->nr]; 219 220 return p ? page_address(p) : NULL; 221 } 222 223 static void pool_free(struct pagevec *pv, void *addr) 224 { 225 struct page *p = virt_to_page(addr); 226 227 if (pagevec_space(pv)) 228 pagevec_add(pv, p); 229 else 230 __free_page(p); 231 } 232 233 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR 234 235 struct compress { 236 struct pagevec pool; 237 struct z_stream_s zstream; 238 void *tmp; 239 bool wc; 240 }; 241 242 static bool compress_init(struct compress *c) 243 { 244 struct z_stream_s *zstream = &c->zstream; 245 246 if (pool_init(&c->pool, ALLOW_FAIL)) 247 return false; 248 249 zstream->workspace = 250 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL), 251 ALLOW_FAIL); 252 if (!zstream->workspace) { 253 pool_fini(&c->pool); 254 return false; 255 } 256 257 c->tmp = NULL; 258 if (i915_has_memcpy_from_wc()) 259 c->tmp = pool_alloc(&c->pool, ALLOW_FAIL); 260 261 return true; 262 } 263 264 static bool compress_start(struct compress *c) 265 { 266 struct z_stream_s *zstream = &c->zstream; 267 void *workspace = zstream->workspace; 268 269 memset(zstream, 0, sizeof(*zstream)); 270 zstream->workspace = workspace; 271 272 return zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) == Z_OK; 273 } 274 275 static void *compress_next_page(struct compress *c, 276 struct drm_i915_error_object *dst) 277 { 278 void *page; 279 280 if (dst->page_count >= dst->num_pages) 281 return ERR_PTR(-ENOSPC); 282 283 page = pool_alloc(&c->pool, ALLOW_FAIL); 284 if (!page) 285 return ERR_PTR(-ENOMEM); 286 287 return dst->pages[dst->page_count++] = page; 288 } 289 290 static int compress_page(struct compress *c, 291 void *src, 292 struct drm_i915_error_object *dst) 293 { 294 struct z_stream_s *zstream = &c->zstream; 295 296 zstream->next_in = src; 297 if (c->wc && c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE)) 298 zstream->next_in = c->tmp; 299 zstream->avail_in = PAGE_SIZE; 300 301 do { 302 if (zstream->avail_out == 0) { 303 zstream->next_out = compress_next_page(c, dst); 304 if (IS_ERR(zstream->next_out)) 305 return PTR_ERR(zstream->next_out); 306 307 zstream->avail_out = PAGE_SIZE; 308 } 309 310 if (zlib_deflate(zstream, Z_NO_FLUSH) != Z_OK) 311 return -EIO; 312 } while (zstream->avail_in); 313 314 /* Fallback to uncompressed if we increase size? */ 315 if (0 && zstream->total_out > zstream->total_in) 316 return -E2BIG; 317 318 return 0; 319 } 320 321 static int compress_flush(struct compress *c, 322 struct drm_i915_error_object *dst) 323 { 324 struct z_stream_s *zstream = &c->zstream; 325 326 do { 327 switch (zlib_deflate(zstream, Z_FINISH)) { 328 case Z_OK: /* more space requested */ 329 zstream->next_out = compress_next_page(c, dst); 330 if (IS_ERR(zstream->next_out)) 331 return PTR_ERR(zstream->next_out); 332 333 zstream->avail_out = PAGE_SIZE; 334 break; 335 336 case Z_STREAM_END: 337 goto end; 338 339 default: /* any error */ 340 return -EIO; 341 } 342 } while (1); 343 344 end: 345 memset(zstream->next_out, 0, zstream->avail_out); 346 dst->unused = zstream->avail_out; 347 return 0; 348 } 349 350 static void compress_finish(struct compress *c) 351 { 352 zlib_deflateEnd(&c->zstream); 353 } 354 355 static void compress_fini(struct compress *c) 356 { 357 kfree(c->zstream.workspace); 358 if (c->tmp) 359 pool_free(&c->pool, c->tmp); 360 pool_fini(&c->pool); 361 } 362 363 static void err_compression_marker(struct drm_i915_error_state_buf *m) 364 { 365 err_puts(m, ":"); 366 } 367 368 #else 369 370 struct compress { 371 struct pagevec pool; 372 bool wc; 373 }; 374 375 static bool compress_init(struct compress *c) 376 { 377 return pool_init(&c->pool, ALLOW_FAIL) == 0; 378 } 379 380 static bool compress_start(struct compress *c) 381 { 382 return true; 383 } 384 385 static int compress_page(struct compress *c, 386 void *src, 387 struct drm_i915_error_object *dst) 388 { 389 void *ptr; 390 391 ptr = pool_alloc(&c->pool, ALLOW_FAIL); 392 if (!ptr) 393 return -ENOMEM; 394 395 if (!(c->wc && i915_memcpy_from_wc(ptr, src, PAGE_SIZE))) 396 memcpy(ptr, src, PAGE_SIZE); 397 dst->pages[dst->page_count++] = ptr; 398 399 return 0; 400 } 401 402 static int compress_flush(struct compress *c, 403 struct drm_i915_error_object *dst) 404 { 405 return 0; 406 } 407 408 static void compress_finish(struct compress *c) 409 { 410 } 411 412 static void compress_fini(struct compress *c) 413 { 414 pool_fini(&c->pool); 415 } 416 417 static void err_compression_marker(struct drm_i915_error_state_buf *m) 418 { 419 err_puts(m, "~"); 420 } 421 422 #endif 423 424 static void error_print_instdone(struct drm_i915_error_state_buf *m, 425 const struct drm_i915_error_engine *ee) 426 { 427 const struct sseu_dev_info *sseu = &RUNTIME_INFO(m->i915)->sseu; 428 int slice; 429 int subslice; 430 431 err_printf(m, " INSTDONE: 0x%08x\n", 432 ee->instdone.instdone); 433 434 if (ee->engine->class != RENDER_CLASS || INTEL_GEN(m->i915) <= 3) 435 return; 436 437 err_printf(m, " SC_INSTDONE: 0x%08x\n", 438 ee->instdone.slice_common); 439 440 if (INTEL_GEN(m->i915) <= 6) 441 return; 442 443 for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice) 444 err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n", 445 slice, subslice, 446 ee->instdone.sampler[slice][subslice]); 447 448 for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice) 449 err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n", 450 slice, subslice, 451 ee->instdone.row[slice][subslice]); 452 } 453 454 static void error_print_request(struct drm_i915_error_state_buf *m, 455 const char *prefix, 456 const struct drm_i915_error_request *erq, 457 const unsigned long epoch) 458 { 459 if (!erq->seqno) 460 return; 461 462 err_printf(m, "%s pid %d, seqno %8x:%08x%s%s, prio %d, emitted %dms, start %08x, head %08x, tail %08x\n", 463 prefix, erq->pid, erq->context, erq->seqno, 464 test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, 465 &erq->flags) ? "!" : "", 466 test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, 467 &erq->flags) ? "+" : "", 468 erq->sched_attr.priority, 469 jiffies_to_msecs(erq->jiffies - epoch), 470 erq->start, erq->head, erq->tail); 471 } 472 473 static void error_print_context(struct drm_i915_error_state_buf *m, 474 const char *header, 475 const struct drm_i915_error_context *ctx) 476 { 477 err_printf(m, "%s%s[%d] prio %d, guilty %d active %d\n", 478 header, ctx->comm, ctx->pid, ctx->sched_attr.priority, 479 ctx->guilty, ctx->active); 480 } 481 482 static void error_print_engine(struct drm_i915_error_state_buf *m, 483 const struct drm_i915_error_engine *ee, 484 const unsigned long epoch) 485 { 486 int n; 487 488 err_printf(m, "%s command stream:\n", ee->engine->name); 489 err_printf(m, " IDLE?: %s\n", yesno(ee->idle)); 490 err_printf(m, " START: 0x%08x\n", ee->start); 491 err_printf(m, " HEAD: 0x%08x [0x%08x]\n", ee->head, ee->rq_head); 492 err_printf(m, " TAIL: 0x%08x [0x%08x, 0x%08x]\n", 493 ee->tail, ee->rq_post, ee->rq_tail); 494 err_printf(m, " CTL: 0x%08x\n", ee->ctl); 495 err_printf(m, " MODE: 0x%08x\n", ee->mode); 496 err_printf(m, " HWS: 0x%08x\n", ee->hws); 497 err_printf(m, " ACTHD: 0x%08x %08x\n", 498 (u32)(ee->acthd>>32), (u32)ee->acthd); 499 err_printf(m, " IPEIR: 0x%08x\n", ee->ipeir); 500 err_printf(m, " IPEHR: 0x%08x\n", ee->ipehr); 501 502 error_print_instdone(m, ee); 503 504 if (ee->batchbuffer) { 505 u64 start = ee->batchbuffer->gtt_offset; 506 u64 end = start + ee->batchbuffer->gtt_size; 507 508 err_printf(m, " batch: [0x%08x_%08x, 0x%08x_%08x]\n", 509 upper_32_bits(start), lower_32_bits(start), 510 upper_32_bits(end), lower_32_bits(end)); 511 } 512 if (INTEL_GEN(m->i915) >= 4) { 513 err_printf(m, " BBADDR: 0x%08x_%08x\n", 514 (u32)(ee->bbaddr>>32), (u32)ee->bbaddr); 515 err_printf(m, " BB_STATE: 0x%08x\n", ee->bbstate); 516 err_printf(m, " INSTPS: 0x%08x\n", ee->instps); 517 } 518 err_printf(m, " INSTPM: 0x%08x\n", ee->instpm); 519 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr), 520 lower_32_bits(ee->faddr)); 521 if (INTEL_GEN(m->i915) >= 6) { 522 err_printf(m, " RC PSMI: 0x%08x\n", ee->rc_psmi); 523 err_printf(m, " FAULT_REG: 0x%08x\n", ee->fault_reg); 524 } 525 if (HAS_PPGTT(m->i915)) { 526 err_printf(m, " GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode); 527 528 if (INTEL_GEN(m->i915) >= 8) { 529 int i; 530 for (i = 0; i < 4; i++) 531 err_printf(m, " PDP%d: 0x%016llx\n", 532 i, ee->vm_info.pdp[i]); 533 } else { 534 err_printf(m, " PP_DIR_BASE: 0x%08x\n", 535 ee->vm_info.pp_dir_base); 536 } 537 } 538 err_printf(m, " ring->head: 0x%08x\n", ee->cpu_ring_head); 539 err_printf(m, " ring->tail: 0x%08x\n", ee->cpu_ring_tail); 540 err_printf(m, " engine reset count: %u\n", ee->reset_count); 541 542 for (n = 0; n < ee->num_ports; n++) { 543 err_printf(m, " ELSP[%d]:", n); 544 error_print_request(m, " ", &ee->execlist[n], epoch); 545 } 546 547 error_print_context(m, " Active context: ", &ee->context); 548 } 549 550 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) 551 { 552 va_list args; 553 554 va_start(args, f); 555 i915_error_vprintf(e, f, args); 556 va_end(args); 557 } 558 559 static void print_error_obj(struct drm_i915_error_state_buf *m, 560 const struct intel_engine_cs *engine, 561 const char *name, 562 const struct drm_i915_error_object *obj) 563 { 564 char out[ASCII85_BUFSZ]; 565 int page; 566 567 if (!obj) 568 return; 569 570 if (name) { 571 err_printf(m, "%s --- %s = 0x%08x %08x\n", 572 engine ? engine->name : "global", name, 573 upper_32_bits(obj->gtt_offset), 574 lower_32_bits(obj->gtt_offset)); 575 } 576 577 if (obj->gtt_page_sizes > I915_GTT_PAGE_SIZE_4K) 578 err_printf(m, "gtt_page_sizes = 0x%08x\n", obj->gtt_page_sizes); 579 580 err_compression_marker(m); 581 for (page = 0; page < obj->page_count; page++) { 582 int i, len; 583 584 len = PAGE_SIZE; 585 if (page == obj->page_count - 1) 586 len -= obj->unused; 587 len = ascii85_encode_len(len); 588 589 for (i = 0; i < len; i++) 590 err_puts(m, ascii85_encode(obj->pages[page][i], out)); 591 } 592 err_puts(m, "\n"); 593 } 594 595 static void err_print_capabilities(struct drm_i915_error_state_buf *m, 596 const struct intel_device_info *info, 597 const struct intel_runtime_info *runtime, 598 const struct intel_driver_caps *caps) 599 { 600 struct drm_printer p = i915_error_printer(m); 601 602 intel_device_info_print_static(info, &p); 603 intel_device_info_print_runtime(runtime, &p); 604 intel_device_info_print_topology(&runtime->sseu, &p); 605 intel_driver_caps_print(caps, &p); 606 } 607 608 static void err_print_params(struct drm_i915_error_state_buf *m, 609 const struct i915_params *params) 610 { 611 struct drm_printer p = i915_error_printer(m); 612 613 i915_params_dump(params, &p); 614 } 615 616 static void err_print_pciid(struct drm_i915_error_state_buf *m, 617 struct drm_i915_private *i915) 618 { 619 struct pci_dev *pdev = i915->drm.pdev; 620 621 err_printf(m, "PCI ID: 0x%04x\n", pdev->device); 622 err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision); 623 err_printf(m, "PCI Subsystem: %04x:%04x\n", 624 pdev->subsystem_vendor, 625 pdev->subsystem_device); 626 } 627 628 static void err_print_uc(struct drm_i915_error_state_buf *m, 629 const struct i915_error_uc *error_uc) 630 { 631 struct drm_printer p = i915_error_printer(m); 632 const struct i915_gpu_state *error = 633 container_of(error_uc, typeof(*error), uc); 634 635 if (!error->device_info.has_gt_uc) 636 return; 637 638 intel_uc_fw_dump(&error_uc->guc_fw, &p); 639 intel_uc_fw_dump(&error_uc->huc_fw, &p); 640 print_error_obj(m, NULL, "GuC log buffer", error_uc->guc_log); 641 } 642 643 static void err_free_sgl(struct scatterlist *sgl) 644 { 645 while (sgl) { 646 struct scatterlist *sg; 647 648 for (sg = sgl; !sg_is_chain(sg); sg++) { 649 kfree(sg_virt(sg)); 650 if (sg_is_last(sg)) 651 break; 652 } 653 654 sg = sg_is_last(sg) ? NULL : sg_chain_ptr(sg); 655 free_page((unsigned long)sgl); 656 sgl = sg; 657 } 658 } 659 660 static void __err_print_to_sgl(struct drm_i915_error_state_buf *m, 661 struct i915_gpu_state *error) 662 { 663 const struct drm_i915_error_engine *ee; 664 struct timespec64 ts; 665 int i, j; 666 667 if (*error->error_msg) 668 err_printf(m, "%s\n", error->error_msg); 669 err_printf(m, "Kernel: %s %s\n", 670 init_utsname()->release, 671 init_utsname()->machine); 672 err_printf(m, "Driver: %s\n", DRIVER_DATE); 673 ts = ktime_to_timespec64(error->time); 674 err_printf(m, "Time: %lld s %ld us\n", 675 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 676 ts = ktime_to_timespec64(error->boottime); 677 err_printf(m, "Boottime: %lld s %ld us\n", 678 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 679 ts = ktime_to_timespec64(error->uptime); 680 err_printf(m, "Uptime: %lld s %ld us\n", 681 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 682 err_printf(m, "Capture: %lu jiffies; %d ms ago\n", 683 error->capture, jiffies_to_msecs(jiffies - error->capture)); 684 685 for (ee = error->engine; ee; ee = ee->next) 686 err_printf(m, "Active process (on ring %s): %s [%d]\n", 687 ee->engine->name, 688 ee->context.comm, 689 ee->context.pid); 690 691 err_printf(m, "Reset count: %u\n", error->reset_count); 692 err_printf(m, "Suspend count: %u\n", error->suspend_count); 693 err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform)); 694 err_printf(m, "Subplatform: 0x%x\n", 695 intel_subplatform(&error->runtime_info, 696 error->device_info.platform)); 697 err_print_pciid(m, m->i915); 698 699 err_printf(m, "IOMMU enabled?: %d\n", error->iommu); 700 701 if (HAS_CSR(m->i915)) { 702 struct intel_csr *csr = &m->i915->csr; 703 704 err_printf(m, "DMC loaded: %s\n", 705 yesno(csr->dmc_payload != NULL)); 706 err_printf(m, "DMC fw version: %d.%d\n", 707 CSR_VERSION_MAJOR(csr->version), 708 CSR_VERSION_MINOR(csr->version)); 709 } 710 711 err_printf(m, "GT awake: %s\n", yesno(error->awake)); 712 err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock)); 713 err_printf(m, "PM suspended: %s\n", yesno(error->suspended)); 714 err_printf(m, "EIR: 0x%08x\n", error->eir); 715 err_printf(m, "IER: 0x%08x\n", error->ier); 716 for (i = 0; i < error->ngtier; i++) 717 err_printf(m, "GTIER[%d]: 0x%08x\n", i, error->gtier[i]); 718 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er); 719 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake); 720 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr); 721 err_printf(m, "CCID: 0x%08x\n", error->ccid); 722 723 for (i = 0; i < error->nfence; i++) 724 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]); 725 726 if (IS_GEN_RANGE(m->i915, 6, 11)) { 727 err_printf(m, "ERROR: 0x%08x\n", error->error); 728 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); 729 } 730 731 if (INTEL_GEN(m->i915) >= 8) 732 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n", 733 error->fault_data1, error->fault_data0); 734 735 if (IS_GEN(m->i915, 7)) 736 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int); 737 738 if (IS_GEN_RANGE(m->i915, 8, 11)) 739 err_printf(m, "GTT_CACHE_EN: 0x%08x\n", error->gtt_cache); 740 741 if (IS_GEN(m->i915, 12)) 742 err_printf(m, "AUX_ERR_DBG: 0x%08x\n", error->aux_err); 743 744 if (INTEL_GEN(m->i915) >= 12) { 745 int i; 746 747 for (i = 0; i < GEN12_SFC_DONE_MAX; i++) 748 err_printf(m, " SFC_DONE[%d]: 0x%08x\n", i, 749 error->sfc_done[i]); 750 751 err_printf(m, " GAM_DONE: 0x%08x\n", error->gam_done); 752 } 753 754 for (ee = error->engine; ee; ee = ee->next) 755 error_print_engine(m, ee, error->capture); 756 757 for (ee = error->engine; ee; ee = ee->next) { 758 const struct drm_i915_error_object *obj; 759 760 obj = ee->batchbuffer; 761 if (obj) { 762 err_puts(m, ee->engine->name); 763 if (ee->context.pid) 764 err_printf(m, " (submitted by %s [%d])", 765 ee->context.comm, 766 ee->context.pid); 767 err_printf(m, " --- gtt_offset = 0x%08x %08x\n", 768 upper_32_bits(obj->gtt_offset), 769 lower_32_bits(obj->gtt_offset)); 770 print_error_obj(m, ee->engine, NULL, obj); 771 } 772 773 for (j = 0; j < ee->user_bo_count; j++) 774 print_error_obj(m, ee->engine, "user", ee->user_bo[j]); 775 776 if (ee->num_requests) { 777 err_printf(m, "%s --- %d requests\n", 778 ee->engine->name, 779 ee->num_requests); 780 for (j = 0; j < ee->num_requests; j++) 781 error_print_request(m, " ", 782 &ee->requests[j], 783 error->capture); 784 } 785 786 print_error_obj(m, ee->engine, "ringbuffer", ee->ringbuffer); 787 print_error_obj(m, ee->engine, "HW Status", ee->hws_page); 788 print_error_obj(m, ee->engine, "HW context", ee->ctx); 789 print_error_obj(m, ee->engine, "WA context", ee->wa_ctx); 790 print_error_obj(m, ee->engine, 791 "WA batchbuffer", ee->wa_batchbuffer); 792 print_error_obj(m, ee->engine, 793 "NULL context", ee->default_state); 794 } 795 796 if (error->overlay) 797 intel_overlay_print_error_state(m, error->overlay); 798 799 if (error->display) 800 intel_display_print_error_state(m, error->display); 801 802 err_print_capabilities(m, &error->device_info, &error->runtime_info, 803 &error->driver_caps); 804 err_print_params(m, &error->params); 805 err_print_uc(m, &error->uc); 806 } 807 808 static int err_print_to_sgl(struct i915_gpu_state *error) 809 { 810 struct drm_i915_error_state_buf m; 811 812 if (IS_ERR(error)) 813 return PTR_ERR(error); 814 815 if (READ_ONCE(error->sgl)) 816 return 0; 817 818 memset(&m, 0, sizeof(m)); 819 m.i915 = error->i915; 820 821 __err_print_to_sgl(&m, error); 822 823 if (m.buf) { 824 __sg_set_buf(m.cur++, m.buf, m.bytes, m.iter); 825 m.bytes = 0; 826 m.buf = NULL; 827 } 828 if (m.cur) { 829 GEM_BUG_ON(m.end < m.cur); 830 sg_mark_end(m.cur - 1); 831 } 832 GEM_BUG_ON(m.sgl && !m.cur); 833 834 if (m.err) { 835 err_free_sgl(m.sgl); 836 return m.err; 837 } 838 839 if (cmpxchg(&error->sgl, NULL, m.sgl)) 840 err_free_sgl(m.sgl); 841 842 return 0; 843 } 844 845 ssize_t i915_gpu_state_copy_to_buffer(struct i915_gpu_state *error, 846 char *buf, loff_t off, size_t rem) 847 { 848 struct scatterlist *sg; 849 size_t count; 850 loff_t pos; 851 int err; 852 853 if (!error || !rem) 854 return 0; 855 856 err = err_print_to_sgl(error); 857 if (err) 858 return err; 859 860 sg = READ_ONCE(error->fit); 861 if (!sg || off < sg->dma_address) 862 sg = error->sgl; 863 if (!sg) 864 return 0; 865 866 pos = sg->dma_address; 867 count = 0; 868 do { 869 size_t len, start; 870 871 if (sg_is_chain(sg)) { 872 sg = sg_chain_ptr(sg); 873 GEM_BUG_ON(sg_is_chain(sg)); 874 } 875 876 len = sg->length; 877 if (pos + len <= off) { 878 pos += len; 879 continue; 880 } 881 882 start = sg->offset; 883 if (pos < off) { 884 GEM_BUG_ON(off - pos > len); 885 len -= off - pos; 886 start += off - pos; 887 pos = off; 888 } 889 890 len = min(len, rem); 891 GEM_BUG_ON(!len || len > sg->length); 892 893 memcpy(buf, page_address(sg_page(sg)) + start, len); 894 895 count += len; 896 pos += len; 897 898 buf += len; 899 rem -= len; 900 if (!rem) { 901 WRITE_ONCE(error->fit, sg); 902 break; 903 } 904 } while (!sg_is_last(sg++)); 905 906 return count; 907 } 908 909 static void i915_error_object_free(struct drm_i915_error_object *obj) 910 { 911 int page; 912 913 if (obj == NULL) 914 return; 915 916 for (page = 0; page < obj->page_count; page++) 917 free_page((unsigned long)obj->pages[page]); 918 919 kfree(obj); 920 } 921 922 923 static void cleanup_params(struct i915_gpu_state *error) 924 { 925 i915_params_free(&error->params); 926 } 927 928 static void cleanup_uc_state(struct i915_gpu_state *error) 929 { 930 struct i915_error_uc *error_uc = &error->uc; 931 932 kfree(error_uc->guc_fw.path); 933 kfree(error_uc->huc_fw.path); 934 i915_error_object_free(error_uc->guc_log); 935 } 936 937 void __i915_gpu_state_free(struct kref *error_ref) 938 { 939 struct i915_gpu_state *error = 940 container_of(error_ref, typeof(*error), ref); 941 long i; 942 943 while (error->engine) { 944 struct drm_i915_error_engine *ee = error->engine; 945 946 error->engine = ee->next; 947 948 for (i = 0; i < ee->user_bo_count; i++) 949 i915_error_object_free(ee->user_bo[i]); 950 kfree(ee->user_bo); 951 952 i915_error_object_free(ee->batchbuffer); 953 i915_error_object_free(ee->wa_batchbuffer); 954 i915_error_object_free(ee->ringbuffer); 955 i915_error_object_free(ee->hws_page); 956 i915_error_object_free(ee->ctx); 957 i915_error_object_free(ee->wa_ctx); 958 959 kfree(ee->requests); 960 kfree(ee); 961 } 962 963 kfree(error->overlay); 964 kfree(error->display); 965 966 cleanup_params(error); 967 cleanup_uc_state(error); 968 969 err_free_sgl(error->sgl); 970 kfree(error); 971 } 972 973 static struct drm_i915_error_object * 974 i915_error_object_create(struct drm_i915_private *i915, 975 struct i915_vma *vma, 976 struct compress *compress) 977 { 978 struct i915_ggtt *ggtt = &i915->ggtt; 979 const u64 slot = ggtt->error_capture.start; 980 struct drm_i915_error_object *dst; 981 unsigned long num_pages; 982 struct sgt_iter iter; 983 int ret; 984 985 might_sleep(); 986 987 if (!vma || !vma->pages) 988 return NULL; 989 990 num_pages = min_t(u64, vma->size, vma->obj->base.size) >> PAGE_SHIFT; 991 num_pages = DIV_ROUND_UP(10 * num_pages, 8); /* worstcase zlib growth */ 992 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), ALLOW_FAIL); 993 if (!dst) 994 return NULL; 995 996 if (!compress_start(compress)) { 997 kfree(dst); 998 return NULL; 999 } 1000 1001 dst->gtt_offset = vma->node.start; 1002 dst->gtt_size = vma->node.size; 1003 dst->gtt_page_sizes = vma->page_sizes.gtt; 1004 dst->num_pages = num_pages; 1005 dst->page_count = 0; 1006 dst->unused = 0; 1007 1008 compress->wc = i915_gem_object_is_lmem(vma->obj) || 1009 drm_mm_node_allocated(&ggtt->error_capture); 1010 1011 ret = -EINVAL; 1012 if (drm_mm_node_allocated(&ggtt->error_capture)) { 1013 void __iomem *s; 1014 dma_addr_t dma; 1015 1016 for_each_sgt_daddr(dma, iter, vma->pages) { 1017 ggtt->vm.insert_page(&ggtt->vm, dma, slot, 1018 I915_CACHE_NONE, 0); 1019 1020 s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE); 1021 ret = compress_page(compress, (void __force *)s, dst); 1022 io_mapping_unmap(s); 1023 if (ret) 1024 break; 1025 } 1026 } else if (i915_gem_object_is_lmem(vma->obj)) { 1027 struct intel_memory_region *mem = vma->obj->mm.region; 1028 dma_addr_t dma; 1029 1030 for_each_sgt_daddr(dma, iter, vma->pages) { 1031 void __iomem *s; 1032 1033 s = io_mapping_map_wc(&mem->iomap, dma, PAGE_SIZE); 1034 ret = compress_page(compress, (void __force *)s, dst); 1035 io_mapping_unmap(s); 1036 if (ret) 1037 break; 1038 } 1039 } else { 1040 struct page *page; 1041 1042 for_each_sgt_page(page, iter, vma->pages) { 1043 void *s; 1044 1045 drm_clflush_pages(&page, 1); 1046 1047 s = kmap(page); 1048 ret = compress_page(compress, s, dst); 1049 kunmap(page); 1050 1051 drm_clflush_pages(&page, 1); 1052 1053 if (ret) 1054 break; 1055 } 1056 } 1057 1058 if (ret || compress_flush(compress, dst)) { 1059 while (dst->page_count--) 1060 pool_free(&compress->pool, dst->pages[dst->page_count]); 1061 kfree(dst); 1062 dst = NULL; 1063 } 1064 compress_finish(compress); 1065 1066 return dst; 1067 } 1068 1069 /* 1070 * Generate a semi-unique error code. The code is not meant to have meaning, The 1071 * code's only purpose is to try to prevent false duplicated bug reports by 1072 * grossly estimating a GPU error state. 1073 * 1074 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine 1075 * the hang if we could strip the GTT offset information from it. 1076 * 1077 * It's only a small step better than a random number in its current form. 1078 */ 1079 static u32 i915_error_generate_code(struct i915_gpu_state *error) 1080 { 1081 const struct drm_i915_error_engine *ee = error->engine; 1082 1083 /* 1084 * IPEHR would be an ideal way to detect errors, as it's the gross 1085 * measure of "the command that hung." However, has some very common 1086 * synchronization commands which almost always appear in the case 1087 * strictly a client bug. Use instdone to differentiate those some. 1088 */ 1089 return ee ? ee->ipehr ^ ee->instdone.instdone : 0; 1090 } 1091 1092 static void gem_record_fences(struct i915_gpu_state *error) 1093 { 1094 struct drm_i915_private *dev_priv = error->i915; 1095 struct intel_uncore *uncore = &dev_priv->uncore; 1096 int i; 1097 1098 if (INTEL_GEN(dev_priv) >= 6) { 1099 for (i = 0; i < dev_priv->ggtt.num_fences; i++) 1100 error->fence[i] = 1101 intel_uncore_read64(uncore, 1102 FENCE_REG_GEN6_LO(i)); 1103 } else if (INTEL_GEN(dev_priv) >= 4) { 1104 for (i = 0; i < dev_priv->ggtt.num_fences; i++) 1105 error->fence[i] = 1106 intel_uncore_read64(uncore, 1107 FENCE_REG_965_LO(i)); 1108 } else { 1109 for (i = 0; i < dev_priv->ggtt.num_fences; i++) 1110 error->fence[i] = 1111 intel_uncore_read(uncore, FENCE_REG(i)); 1112 } 1113 error->nfence = i; 1114 } 1115 1116 static void error_record_engine_registers(struct i915_gpu_state *error, 1117 struct intel_engine_cs *engine, 1118 struct drm_i915_error_engine *ee) 1119 { 1120 struct drm_i915_private *dev_priv = engine->i915; 1121 1122 if (INTEL_GEN(dev_priv) >= 6) { 1123 ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL); 1124 1125 if (INTEL_GEN(dev_priv) >= 12) 1126 ee->fault_reg = I915_READ(GEN12_RING_FAULT_REG); 1127 else if (INTEL_GEN(dev_priv) >= 8) 1128 ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG); 1129 else 1130 ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine); 1131 } 1132 1133 if (INTEL_GEN(dev_priv) >= 4) { 1134 ee->faddr = ENGINE_READ(engine, RING_DMA_FADD); 1135 ee->ipeir = ENGINE_READ(engine, RING_IPEIR); 1136 ee->ipehr = ENGINE_READ(engine, RING_IPEHR); 1137 ee->instps = ENGINE_READ(engine, RING_INSTPS); 1138 ee->bbaddr = ENGINE_READ(engine, RING_BBADDR); 1139 if (INTEL_GEN(dev_priv) >= 8) { 1140 ee->faddr |= (u64)ENGINE_READ(engine, RING_DMA_FADD_UDW) << 32; 1141 ee->bbaddr |= (u64)ENGINE_READ(engine, RING_BBADDR_UDW) << 32; 1142 } 1143 ee->bbstate = ENGINE_READ(engine, RING_BBSTATE); 1144 } else { 1145 ee->faddr = ENGINE_READ(engine, DMA_FADD_I8XX); 1146 ee->ipeir = ENGINE_READ(engine, IPEIR); 1147 ee->ipehr = ENGINE_READ(engine, IPEHR); 1148 } 1149 1150 intel_engine_get_instdone(engine, &ee->instdone); 1151 1152 ee->instpm = ENGINE_READ(engine, RING_INSTPM); 1153 ee->acthd = intel_engine_get_active_head(engine); 1154 ee->start = ENGINE_READ(engine, RING_START); 1155 ee->head = ENGINE_READ(engine, RING_HEAD); 1156 ee->tail = ENGINE_READ(engine, RING_TAIL); 1157 ee->ctl = ENGINE_READ(engine, RING_CTL); 1158 if (INTEL_GEN(dev_priv) > 2) 1159 ee->mode = ENGINE_READ(engine, RING_MI_MODE); 1160 1161 if (!HWS_NEEDS_PHYSICAL(dev_priv)) { 1162 i915_reg_t mmio; 1163 1164 if (IS_GEN(dev_priv, 7)) { 1165 switch (engine->id) { 1166 default: 1167 MISSING_CASE(engine->id); 1168 /* fall through */ 1169 case RCS0: 1170 mmio = RENDER_HWS_PGA_GEN7; 1171 break; 1172 case BCS0: 1173 mmio = BLT_HWS_PGA_GEN7; 1174 break; 1175 case VCS0: 1176 mmio = BSD_HWS_PGA_GEN7; 1177 break; 1178 case VECS0: 1179 mmio = VEBOX_HWS_PGA_GEN7; 1180 break; 1181 } 1182 } else if (IS_GEN(engine->i915, 6)) { 1183 mmio = RING_HWS_PGA_GEN6(engine->mmio_base); 1184 } else { 1185 /* XXX: gen8 returns to sanity */ 1186 mmio = RING_HWS_PGA(engine->mmio_base); 1187 } 1188 1189 ee->hws = I915_READ(mmio); 1190 } 1191 1192 ee->idle = intel_engine_is_idle(engine); 1193 ee->reset_count = i915_reset_engine_count(&dev_priv->gpu_error, 1194 engine); 1195 1196 if (HAS_PPGTT(dev_priv)) { 1197 int i; 1198 1199 ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7); 1200 1201 if (IS_GEN(dev_priv, 6)) { 1202 ee->vm_info.pp_dir_base = 1203 ENGINE_READ(engine, RING_PP_DIR_BASE_READ); 1204 } else if (IS_GEN(dev_priv, 7)) { 1205 ee->vm_info.pp_dir_base = 1206 ENGINE_READ(engine, RING_PP_DIR_BASE); 1207 } else if (INTEL_GEN(dev_priv) >= 8) { 1208 u32 base = engine->mmio_base; 1209 1210 for (i = 0; i < 4; i++) { 1211 ee->vm_info.pdp[i] = 1212 I915_READ(GEN8_RING_PDP_UDW(base, i)); 1213 ee->vm_info.pdp[i] <<= 32; 1214 ee->vm_info.pdp[i] |= 1215 I915_READ(GEN8_RING_PDP_LDW(base, i)); 1216 } 1217 } 1218 } 1219 } 1220 1221 static void record_request(const struct i915_request *request, 1222 struct drm_i915_error_request *erq) 1223 { 1224 const struct i915_gem_context *ctx; 1225 1226 erq->flags = request->fence.flags; 1227 erq->context = request->fence.context; 1228 erq->seqno = request->fence.seqno; 1229 erq->sched_attr = request->sched.attr; 1230 erq->jiffies = request->emitted_jiffies; 1231 erq->start = i915_ggtt_offset(request->ring->vma); 1232 erq->head = request->head; 1233 erq->tail = request->tail; 1234 1235 erq->pid = 0; 1236 rcu_read_lock(); 1237 ctx = rcu_dereference(request->context->gem_context); 1238 if (ctx) 1239 erq->pid = pid_nr(ctx->pid); 1240 rcu_read_unlock(); 1241 } 1242 1243 static void engine_record_requests(struct intel_engine_cs *engine, 1244 struct i915_request *first, 1245 struct drm_i915_error_engine *ee) 1246 { 1247 struct i915_request *request; 1248 int count; 1249 1250 count = 0; 1251 request = first; 1252 list_for_each_entry_from(request, &engine->active.requests, sched.link) 1253 count++; 1254 if (!count) 1255 return; 1256 1257 ee->requests = kcalloc(count, sizeof(*ee->requests), ATOMIC_MAYFAIL); 1258 if (!ee->requests) 1259 return; 1260 1261 ee->num_requests = count; 1262 1263 count = 0; 1264 request = first; 1265 list_for_each_entry_from(request, 1266 &engine->active.requests, sched.link) { 1267 if (count >= ee->num_requests) { 1268 /* 1269 * If the ring request list was changed in 1270 * between the point where the error request 1271 * list was created and dimensioned and this 1272 * point then just exit early to avoid crashes. 1273 * 1274 * We don't need to communicate that the 1275 * request list changed state during error 1276 * state capture and that the error state is 1277 * slightly incorrect as a consequence since we 1278 * are typically only interested in the request 1279 * list state at the point of error state 1280 * capture, not in any changes happening during 1281 * the capture. 1282 */ 1283 break; 1284 } 1285 1286 record_request(request, &ee->requests[count++]); 1287 } 1288 ee->num_requests = count; 1289 } 1290 1291 static void error_record_engine_execlists(const struct intel_engine_cs *engine, 1292 struct drm_i915_error_engine *ee) 1293 { 1294 const struct intel_engine_execlists * const execlists = &engine->execlists; 1295 struct i915_request * const *port = execlists->active; 1296 unsigned int n = 0; 1297 1298 while (*port) 1299 record_request(*port++, &ee->execlist[n++]); 1300 1301 ee->num_ports = n; 1302 } 1303 1304 static bool record_context(struct drm_i915_error_context *e, 1305 const struct i915_request *rq) 1306 { 1307 struct i915_gem_context *ctx; 1308 struct task_struct *task; 1309 bool capture; 1310 1311 rcu_read_lock(); 1312 ctx = rcu_dereference(rq->context->gem_context); 1313 if (ctx && !kref_get_unless_zero(&ctx->ref)) 1314 ctx = NULL; 1315 rcu_read_unlock(); 1316 if (!ctx) 1317 return false; 1318 1319 rcu_read_lock(); 1320 task = pid_task(ctx->pid, PIDTYPE_PID); 1321 if (task) { 1322 strcpy(e->comm, task->comm); 1323 e->pid = task->pid; 1324 } 1325 rcu_read_unlock(); 1326 1327 e->sched_attr = ctx->sched; 1328 e->guilty = atomic_read(&ctx->guilty_count); 1329 e->active = atomic_read(&ctx->active_count); 1330 1331 capture = i915_gem_context_no_error_capture(ctx); 1332 1333 i915_gem_context_put(ctx); 1334 return capture; 1335 } 1336 1337 struct capture_vma { 1338 struct capture_vma *next; 1339 void **slot; 1340 }; 1341 1342 static struct capture_vma * 1343 capture_vma(struct capture_vma *next, 1344 struct i915_vma *vma, 1345 struct drm_i915_error_object **out) 1346 { 1347 struct capture_vma *c; 1348 1349 *out = NULL; 1350 if (!vma) 1351 return next; 1352 1353 c = kmalloc(sizeof(*c), ATOMIC_MAYFAIL); 1354 if (!c) 1355 return next; 1356 1357 if (!i915_active_acquire_if_busy(&vma->active)) { 1358 kfree(c); 1359 return next; 1360 } 1361 1362 c->slot = (void **)out; 1363 *c->slot = i915_vma_get(vma); 1364 1365 c->next = next; 1366 return c; 1367 } 1368 1369 static struct capture_vma * 1370 request_record_user_bo(struct i915_request *request, 1371 struct drm_i915_error_engine *ee, 1372 struct capture_vma *capture) 1373 { 1374 struct i915_capture_list *c; 1375 struct drm_i915_error_object **bo; 1376 long count, max; 1377 1378 max = 0; 1379 for (c = request->capture_list; c; c = c->next) 1380 max++; 1381 if (!max) 1382 return capture; 1383 1384 bo = kmalloc_array(max, sizeof(*bo), ATOMIC_MAYFAIL); 1385 if (!bo) { 1386 /* If we can't capture everything, try to capture something. */ 1387 max = min_t(long, max, PAGE_SIZE / sizeof(*bo)); 1388 bo = kmalloc_array(max, sizeof(*bo), ATOMIC_MAYFAIL); 1389 } 1390 if (!bo) 1391 return capture; 1392 1393 count = 0; 1394 for (c = request->capture_list; c; c = c->next) { 1395 capture = capture_vma(capture, c->vma, &bo[count]); 1396 if (++count == max) 1397 break; 1398 } 1399 1400 ee->user_bo = bo; 1401 ee->user_bo_count = count; 1402 1403 return capture; 1404 } 1405 1406 static struct drm_i915_error_object * 1407 capture_object(struct drm_i915_private *dev_priv, 1408 struct drm_i915_gem_object *obj, 1409 struct compress *compress) 1410 { 1411 if (obj && i915_gem_object_has_pages(obj)) { 1412 struct i915_vma fake = { 1413 .node = { .start = U64_MAX, .size = obj->base.size }, 1414 .size = obj->base.size, 1415 .pages = obj->mm.pages, 1416 .obj = obj, 1417 }; 1418 1419 return i915_error_object_create(dev_priv, &fake, compress); 1420 } else { 1421 return NULL; 1422 } 1423 } 1424 1425 static void 1426 gem_record_rings(struct i915_gpu_state *error, struct compress *compress) 1427 { 1428 struct drm_i915_private *i915 = error->i915; 1429 struct intel_engine_cs *engine; 1430 struct drm_i915_error_engine *ee; 1431 1432 ee = kzalloc(sizeof(*ee), GFP_KERNEL); 1433 if (!ee) 1434 return; 1435 1436 for_each_uabi_engine(engine, i915) { 1437 struct capture_vma *capture = NULL; 1438 struct i915_request *request; 1439 unsigned long flags; 1440 1441 /* Refill our page pool before entering atomic section */ 1442 pool_refill(&compress->pool, ALLOW_FAIL); 1443 1444 spin_lock_irqsave(&engine->active.lock, flags); 1445 request = intel_engine_find_active_request(engine); 1446 if (!request) { 1447 spin_unlock_irqrestore(&engine->active.lock, flags); 1448 continue; 1449 } 1450 1451 error->simulated |= record_context(&ee->context, request); 1452 1453 /* 1454 * We need to copy these to an anonymous buffer 1455 * as the simplest method to avoid being overwritten 1456 * by userspace. 1457 */ 1458 capture = capture_vma(capture, 1459 request->batch, 1460 &ee->batchbuffer); 1461 1462 if (HAS_BROKEN_CS_TLB(i915)) 1463 capture = capture_vma(capture, 1464 engine->gt->scratch, 1465 &ee->wa_batchbuffer); 1466 1467 capture = request_record_user_bo(request, ee, capture); 1468 1469 capture = capture_vma(capture, 1470 request->context->state, 1471 &ee->ctx); 1472 1473 capture = capture_vma(capture, 1474 request->ring->vma, 1475 &ee->ringbuffer); 1476 1477 ee->cpu_ring_head = request->ring->head; 1478 ee->cpu_ring_tail = request->ring->tail; 1479 1480 ee->rq_head = request->head; 1481 ee->rq_post = request->postfix; 1482 ee->rq_tail = request->tail; 1483 1484 engine_record_requests(engine, request, ee); 1485 spin_unlock_irqrestore(&engine->active.lock, flags); 1486 1487 error_record_engine_registers(error, engine, ee); 1488 error_record_engine_execlists(engine, ee); 1489 1490 while (capture) { 1491 struct capture_vma *this = capture; 1492 struct i915_vma *vma = *this->slot; 1493 1494 *this->slot = 1495 i915_error_object_create(i915, vma, compress); 1496 1497 i915_active_release(&vma->active); 1498 i915_vma_put(vma); 1499 1500 capture = this->next; 1501 kfree(this); 1502 } 1503 1504 ee->hws_page = 1505 i915_error_object_create(i915, 1506 engine->status_page.vma, 1507 compress); 1508 1509 ee->wa_ctx = 1510 i915_error_object_create(i915, 1511 engine->wa_ctx.vma, 1512 compress); 1513 1514 ee->default_state = 1515 capture_object(i915, engine->default_state, compress); 1516 1517 ee->engine = engine; 1518 1519 ee->next = error->engine; 1520 error->engine = ee; 1521 1522 ee = kzalloc(sizeof(*ee), GFP_KERNEL); 1523 if (!ee) 1524 return; 1525 } 1526 1527 kfree(ee); 1528 } 1529 1530 static void 1531 capture_uc_state(struct i915_gpu_state *error, struct compress *compress) 1532 { 1533 struct drm_i915_private *i915 = error->i915; 1534 struct i915_error_uc *error_uc = &error->uc; 1535 struct intel_uc *uc = &i915->gt.uc; 1536 1537 /* Capturing uC state won't be useful if there is no GuC */ 1538 if (!error->device_info.has_gt_uc) 1539 return; 1540 1541 memcpy(&error_uc->guc_fw, &uc->guc.fw, sizeof(uc->guc.fw)); 1542 memcpy(&error_uc->huc_fw, &uc->huc.fw, sizeof(uc->huc.fw)); 1543 1544 /* Non-default firmware paths will be specified by the modparam. 1545 * As modparams are generally accesible from the userspace make 1546 * explicit copies of the firmware paths. 1547 */ 1548 error_uc->guc_fw.path = kstrdup(uc->guc.fw.path, ALLOW_FAIL); 1549 error_uc->huc_fw.path = kstrdup(uc->huc.fw.path, ALLOW_FAIL); 1550 error_uc->guc_log = i915_error_object_create(i915, 1551 uc->guc.log.vma, 1552 compress); 1553 } 1554 1555 /* Capture all registers which don't fit into another category. */ 1556 static void capture_reg_state(struct i915_gpu_state *error) 1557 { 1558 struct drm_i915_private *i915 = error->i915; 1559 struct intel_uncore *uncore = &i915->uncore; 1560 int i; 1561 1562 /* General organization 1563 * 1. Registers specific to a single generation 1564 * 2. Registers which belong to multiple generations 1565 * 3. Feature specific registers. 1566 * 4. Everything else 1567 * Please try to follow the order. 1568 */ 1569 1570 /* 1: Registers specific to a single generation */ 1571 if (IS_VALLEYVIEW(i915)) { 1572 error->gtier[0] = intel_uncore_read(uncore, GTIER); 1573 error->ier = intel_uncore_read(uncore, VLV_IER); 1574 error->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_VLV); 1575 } 1576 1577 if (IS_GEN(i915, 7)) 1578 error->err_int = intel_uncore_read(uncore, GEN7_ERR_INT); 1579 1580 if (INTEL_GEN(i915) >= 12) { 1581 error->fault_data0 = intel_uncore_read(uncore, 1582 GEN12_FAULT_TLB_DATA0); 1583 error->fault_data1 = intel_uncore_read(uncore, 1584 GEN12_FAULT_TLB_DATA1); 1585 } else if (INTEL_GEN(i915) >= 8) { 1586 error->fault_data0 = intel_uncore_read(uncore, 1587 GEN8_FAULT_TLB_DATA0); 1588 error->fault_data1 = intel_uncore_read(uncore, 1589 GEN8_FAULT_TLB_DATA1); 1590 } 1591 1592 if (IS_GEN(i915, 6)) { 1593 error->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE); 1594 error->gab_ctl = intel_uncore_read(uncore, GAB_CTL); 1595 error->gfx_mode = intel_uncore_read(uncore, GFX_MODE); 1596 } 1597 1598 /* 2: Registers which belong to multiple generations */ 1599 if (INTEL_GEN(i915) >= 7) 1600 error->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_MT); 1601 1602 if (INTEL_GEN(i915) >= 6) { 1603 error->derrmr = intel_uncore_read(uncore, DERRMR); 1604 if (INTEL_GEN(i915) < 12) { 1605 error->error = intel_uncore_read(uncore, ERROR_GEN6); 1606 error->done_reg = intel_uncore_read(uncore, DONE_REG); 1607 } 1608 } 1609 1610 if (INTEL_GEN(i915) >= 5) 1611 error->ccid = intel_uncore_read(uncore, CCID(RENDER_RING_BASE)); 1612 1613 /* 3: Feature specific registers */ 1614 if (IS_GEN_RANGE(i915, 6, 7)) { 1615 error->gam_ecochk = intel_uncore_read(uncore, GAM_ECOCHK); 1616 error->gac_eco = intel_uncore_read(uncore, GAC_ECO_BITS); 1617 } 1618 1619 if (IS_GEN_RANGE(i915, 8, 11)) 1620 error->gtt_cache = intel_uncore_read(uncore, HSW_GTT_CACHE_EN); 1621 1622 if (IS_GEN(i915, 12)) 1623 error->aux_err = intel_uncore_read(uncore, GEN12_AUX_ERR_DBG); 1624 1625 if (INTEL_GEN(i915) >= 12) { 1626 for (i = 0; i < GEN12_SFC_DONE_MAX; i++) { 1627 error->sfc_done[i] = 1628 intel_uncore_read(uncore, GEN12_SFC_DONE(i)); 1629 } 1630 1631 error->gam_done = intel_uncore_read(uncore, GEN12_GAM_DONE); 1632 } 1633 1634 /* 4: Everything else */ 1635 if (INTEL_GEN(i915) >= 11) { 1636 error->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER); 1637 error->gtier[0] = 1638 intel_uncore_read(uncore, 1639 GEN11_RENDER_COPY_INTR_ENABLE); 1640 error->gtier[1] = 1641 intel_uncore_read(uncore, GEN11_VCS_VECS_INTR_ENABLE); 1642 error->gtier[2] = 1643 intel_uncore_read(uncore, GEN11_GUC_SG_INTR_ENABLE); 1644 error->gtier[3] = 1645 intel_uncore_read(uncore, 1646 GEN11_GPM_WGBOXPERF_INTR_ENABLE); 1647 error->gtier[4] = 1648 intel_uncore_read(uncore, 1649 GEN11_CRYPTO_RSVD_INTR_ENABLE); 1650 error->gtier[5] = 1651 intel_uncore_read(uncore, 1652 GEN11_GUNIT_CSME_INTR_ENABLE); 1653 error->ngtier = 6; 1654 } else if (INTEL_GEN(i915) >= 8) { 1655 error->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER); 1656 for (i = 0; i < 4; i++) 1657 error->gtier[i] = intel_uncore_read(uncore, 1658 GEN8_GT_IER(i)); 1659 error->ngtier = 4; 1660 } else if (HAS_PCH_SPLIT(i915)) { 1661 error->ier = intel_uncore_read(uncore, DEIER); 1662 error->gtier[0] = intel_uncore_read(uncore, GTIER); 1663 error->ngtier = 1; 1664 } else if (IS_GEN(i915, 2)) { 1665 error->ier = intel_uncore_read16(uncore, GEN2_IER); 1666 } else if (!IS_VALLEYVIEW(i915)) { 1667 error->ier = intel_uncore_read(uncore, GEN2_IER); 1668 } 1669 error->eir = intel_uncore_read(uncore, EIR); 1670 error->pgtbl_er = intel_uncore_read(uncore, PGTBL_ER); 1671 } 1672 1673 static const char * 1674 error_msg(struct i915_gpu_state *error, 1675 intel_engine_mask_t engines, const char *msg) 1676 { 1677 int len; 1678 1679 len = scnprintf(error->error_msg, sizeof(error->error_msg), 1680 "GPU HANG: ecode %d:%x:0x%08x", 1681 INTEL_GEN(error->i915), engines, 1682 i915_error_generate_code(error)); 1683 if (error->engine) { 1684 /* Just show the first executing process, more is confusing */ 1685 len += scnprintf(error->error_msg + len, 1686 sizeof(error->error_msg) - len, 1687 ", in %s [%d]", 1688 error->engine->context.comm, 1689 error->engine->context.pid); 1690 } 1691 if (msg) 1692 len += scnprintf(error->error_msg + len, 1693 sizeof(error->error_msg) - len, 1694 ", %s", msg); 1695 1696 return error->error_msg; 1697 } 1698 1699 static void capture_gen_state(struct i915_gpu_state *error) 1700 { 1701 struct drm_i915_private *i915 = error->i915; 1702 1703 error->awake = i915->gt.awake; 1704 error->wakelock = atomic_read(&i915->runtime_pm.wakeref_count); 1705 error->suspended = i915->runtime_pm.suspended; 1706 1707 error->iommu = -1; 1708 #ifdef CONFIG_INTEL_IOMMU 1709 error->iommu = intel_iommu_gfx_mapped; 1710 #endif 1711 error->reset_count = i915_reset_count(&i915->gpu_error); 1712 error->suspend_count = i915->suspend_count; 1713 1714 memcpy(&error->device_info, 1715 INTEL_INFO(i915), 1716 sizeof(error->device_info)); 1717 memcpy(&error->runtime_info, 1718 RUNTIME_INFO(i915), 1719 sizeof(error->runtime_info)); 1720 error->driver_caps = i915->caps; 1721 } 1722 1723 static void capture_params(struct i915_gpu_state *error) 1724 { 1725 i915_params_copy(&error->params, &i915_modparams); 1726 } 1727 1728 static void capture_finish(struct i915_gpu_state *error) 1729 { 1730 struct i915_ggtt *ggtt = &error->i915->ggtt; 1731 1732 if (drm_mm_node_allocated(&ggtt->error_capture)) { 1733 const u64 slot = ggtt->error_capture.start; 1734 1735 ggtt->vm.clear_range(&ggtt->vm, slot, PAGE_SIZE); 1736 } 1737 } 1738 1739 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x)) 1740 1741 struct i915_gpu_state * 1742 i915_capture_gpu_state(struct drm_i915_private *i915) 1743 { 1744 struct i915_gpu_state *error; 1745 struct compress compress; 1746 1747 /* Check if GPU capture has been disabled */ 1748 error = READ_ONCE(i915->gpu_error.first_error); 1749 if (IS_ERR(error)) 1750 return error; 1751 1752 error = kzalloc(sizeof(*error), ALLOW_FAIL); 1753 if (!error) { 1754 i915_disable_error_state(i915, -ENOMEM); 1755 return ERR_PTR(-ENOMEM); 1756 } 1757 1758 if (!compress_init(&compress)) { 1759 kfree(error); 1760 i915_disable_error_state(i915, -ENOMEM); 1761 return ERR_PTR(-ENOMEM); 1762 } 1763 1764 kref_init(&error->ref); 1765 error->i915 = i915; 1766 1767 error->time = ktime_get_real(); 1768 error->boottime = ktime_get_boottime(); 1769 error->uptime = ktime_sub(ktime_get(), i915->gt.last_init_time); 1770 error->capture = jiffies; 1771 1772 capture_params(error); 1773 capture_gen_state(error); 1774 capture_uc_state(error, &compress); 1775 capture_reg_state(error); 1776 gem_record_fences(error); 1777 gem_record_rings(error, &compress); 1778 1779 error->overlay = intel_overlay_capture_error_state(i915); 1780 error->display = intel_display_capture_error_state(i915); 1781 1782 capture_finish(error); 1783 compress_fini(&compress); 1784 1785 return error; 1786 } 1787 1788 /** 1789 * i915_capture_error_state - capture an error record for later analysis 1790 * @i915: i915 device 1791 * @engine_mask: the mask of engines triggering the hang 1792 * @msg: a message to insert into the error capture header 1793 * 1794 * Should be called when an error is detected (either a hang or an error 1795 * interrupt) to capture error state from the time of the error. Fills 1796 * out a structure which becomes available in debugfs for user level tools 1797 * to pick up. 1798 */ 1799 void i915_capture_error_state(struct drm_i915_private *i915, 1800 intel_engine_mask_t engine_mask, 1801 const char *msg) 1802 { 1803 static bool warned; 1804 struct i915_gpu_state *error; 1805 unsigned long flags; 1806 1807 if (!i915_modparams.error_capture) 1808 return; 1809 1810 if (READ_ONCE(i915->gpu_error.first_error)) 1811 return; 1812 1813 error = i915_capture_gpu_state(i915); 1814 if (IS_ERR(error)) 1815 return; 1816 1817 dev_info(i915->drm.dev, "%s\n", error_msg(error, engine_mask, msg)); 1818 1819 if (!error->simulated) { 1820 spin_lock_irqsave(&i915->gpu_error.lock, flags); 1821 if (!i915->gpu_error.first_error) { 1822 i915->gpu_error.first_error = error; 1823 error = NULL; 1824 } 1825 spin_unlock_irqrestore(&i915->gpu_error.lock, flags); 1826 } 1827 1828 if (error) { 1829 __i915_gpu_state_free(&error->ref); 1830 return; 1831 } 1832 1833 if (!xchg(&warned, true) && 1834 ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) { 1835 pr_info("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n"); 1836 pr_info("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n"); 1837 pr_info("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n"); 1838 pr_info("The GPU crash dump is required to analyze GPU hangs, so please always attach it.\n"); 1839 pr_info("GPU crash dump saved to /sys/class/drm/card%d/error\n", 1840 i915->drm.primary->index); 1841 } 1842 } 1843 1844 struct i915_gpu_state * 1845 i915_first_error_state(struct drm_i915_private *i915) 1846 { 1847 struct i915_gpu_state *error; 1848 1849 spin_lock_irq(&i915->gpu_error.lock); 1850 error = i915->gpu_error.first_error; 1851 if (!IS_ERR_OR_NULL(error)) 1852 i915_gpu_state_get(error); 1853 spin_unlock_irq(&i915->gpu_error.lock); 1854 1855 return error; 1856 } 1857 1858 void i915_reset_error_state(struct drm_i915_private *i915) 1859 { 1860 struct i915_gpu_state *error; 1861 1862 spin_lock_irq(&i915->gpu_error.lock); 1863 error = i915->gpu_error.first_error; 1864 if (error != ERR_PTR(-ENODEV)) /* if disabled, always disabled */ 1865 i915->gpu_error.first_error = NULL; 1866 spin_unlock_irq(&i915->gpu_error.lock); 1867 1868 if (!IS_ERR_OR_NULL(error)) 1869 i915_gpu_state_put(error); 1870 } 1871 1872 void i915_disable_error_state(struct drm_i915_private *i915, int err) 1873 { 1874 spin_lock_irq(&i915->gpu_error.lock); 1875 if (!i915->gpu_error.first_error) 1876 i915->gpu_error.first_error = ERR_PTR(err); 1877 spin_unlock_irq(&i915->gpu_error.lock); 1878 } 1879