1 /* 2 * Copyright (c) 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * Mika Kuoppala <mika.kuoppala@intel.com> 27 * 28 */ 29 30 #include <generated/utsrelease.h> 31 #include "i915_drv.h" 32 33 static const char *yesno(int v) 34 { 35 return v ? "yes" : "no"; 36 } 37 38 static const char *ring_str(int ring) 39 { 40 switch (ring) { 41 case RCS: return "render"; 42 case VCS: return "bsd"; 43 case BCS: return "blt"; 44 case VECS: return "vebox"; 45 default: return ""; 46 } 47 } 48 49 static const char *pin_flag(int pinned) 50 { 51 if (pinned > 0) 52 return " P"; 53 else if (pinned < 0) 54 return " p"; 55 else 56 return ""; 57 } 58 59 static const char *tiling_flag(int tiling) 60 { 61 switch (tiling) { 62 default: 63 case I915_TILING_NONE: return ""; 64 case I915_TILING_X: return " X"; 65 case I915_TILING_Y: return " Y"; 66 } 67 } 68 69 static const char *dirty_flag(int dirty) 70 { 71 return dirty ? " dirty" : ""; 72 } 73 74 static const char *purgeable_flag(int purgeable) 75 { 76 return purgeable ? " purgeable" : ""; 77 } 78 79 static bool __i915_error_ok(struct drm_i915_error_state_buf *e) 80 { 81 82 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) { 83 e->err = -ENOSPC; 84 return false; 85 } 86 87 if (e->bytes == e->size - 1 || e->err) 88 return false; 89 90 return true; 91 } 92 93 static bool __i915_error_seek(struct drm_i915_error_state_buf *e, 94 unsigned len) 95 { 96 if (e->pos + len <= e->start) { 97 e->pos += len; 98 return false; 99 } 100 101 /* First vsnprintf needs to fit in its entirety for memmove */ 102 if (len >= e->size) { 103 e->err = -EIO; 104 return false; 105 } 106 107 return true; 108 } 109 110 static void __i915_error_advance(struct drm_i915_error_state_buf *e, 111 unsigned len) 112 { 113 /* If this is first printf in this window, adjust it so that 114 * start position matches start of the buffer 115 */ 116 117 if (e->pos < e->start) { 118 const size_t off = e->start - e->pos; 119 120 /* Should not happen but be paranoid */ 121 if (off > len || e->bytes) { 122 e->err = -EIO; 123 return; 124 } 125 126 memmove(e->buf, e->buf + off, len - off); 127 e->bytes = len - off; 128 e->pos = e->start; 129 return; 130 } 131 132 e->bytes += len; 133 e->pos += len; 134 } 135 136 static void i915_error_vprintf(struct drm_i915_error_state_buf *e, 137 const char *f, va_list args) 138 { 139 unsigned len; 140 141 if (!__i915_error_ok(e)) 142 return; 143 144 /* Seek the first printf which is hits start position */ 145 if (e->pos < e->start) { 146 va_list tmp; 147 148 va_copy(tmp, args); 149 if (!__i915_error_seek(e, vsnprintf(NULL, 0, f, tmp))) 150 return; 151 } 152 153 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args); 154 if (len >= e->size - e->bytes) 155 len = e->size - e->bytes - 1; 156 157 __i915_error_advance(e, len); 158 } 159 160 static void i915_error_puts(struct drm_i915_error_state_buf *e, 161 const char *str) 162 { 163 unsigned len; 164 165 if (!__i915_error_ok(e)) 166 return; 167 168 len = strlen(str); 169 170 /* Seek the first printf which is hits start position */ 171 if (e->pos < e->start) { 172 if (!__i915_error_seek(e, len)) 173 return; 174 } 175 176 if (len >= e->size - e->bytes) 177 len = e->size - e->bytes - 1; 178 memcpy(e->buf + e->bytes, str, len); 179 180 __i915_error_advance(e, len); 181 } 182 183 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) 184 #define err_puts(e, s) i915_error_puts(e, s) 185 186 static void print_error_buffers(struct drm_i915_error_state_buf *m, 187 const char *name, 188 struct drm_i915_error_buffer *err, 189 int count) 190 { 191 err_printf(m, "%s [%d]:\n", name, count); 192 193 while (count--) { 194 err_printf(m, " %08x %8u %02x %02x %x %x", 195 err->gtt_offset, 196 err->size, 197 err->read_domains, 198 err->write_domain, 199 err->rseqno, err->wseqno); 200 err_puts(m, pin_flag(err->pinned)); 201 err_puts(m, tiling_flag(err->tiling)); 202 err_puts(m, dirty_flag(err->dirty)); 203 err_puts(m, purgeable_flag(err->purgeable)); 204 err_puts(m, err->ring != -1 ? " " : ""); 205 err_puts(m, ring_str(err->ring)); 206 err_puts(m, i915_cache_level_str(err->cache_level)); 207 208 if (err->name) 209 err_printf(m, " (name: %d)", err->name); 210 if (err->fence_reg != I915_FENCE_REG_NONE) 211 err_printf(m, " (fence: %d)", err->fence_reg); 212 213 err_puts(m, "\n"); 214 err++; 215 } 216 } 217 218 static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a) 219 { 220 switch (a) { 221 case HANGCHECK_IDLE: 222 return "idle"; 223 case HANGCHECK_WAIT: 224 return "wait"; 225 case HANGCHECK_ACTIVE: 226 return "active"; 227 case HANGCHECK_KICK: 228 return "kick"; 229 case HANGCHECK_HUNG: 230 return "hung"; 231 } 232 233 return "unknown"; 234 } 235 236 static void i915_ring_error_state(struct drm_i915_error_state_buf *m, 237 struct drm_device *dev, 238 struct drm_i915_error_state *error, 239 unsigned ring) 240 { 241 BUG_ON(ring >= I915_NUM_RINGS); /* shut up confused gcc */ 242 err_printf(m, "%s command stream:\n", ring_str(ring)); 243 err_printf(m, " HEAD: 0x%08x\n", error->head[ring]); 244 err_printf(m, " TAIL: 0x%08x\n", error->tail[ring]); 245 err_printf(m, " CTL: 0x%08x\n", error->ctl[ring]); 246 err_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]); 247 err_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]); 248 err_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]); 249 err_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]); 250 if (ring == RCS && INTEL_INFO(dev)->gen >= 4) 251 err_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr); 252 if (INTEL_INFO(dev)->gen >= 4) 253 err_printf(m, " BB_STATE: 0x%08x\n", error->bbstate[ring]); 254 if (INTEL_INFO(dev)->gen >= 4) 255 err_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]); 256 err_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]); 257 err_printf(m, " FADDR: 0x%08x\n", error->faddr[ring]); 258 if (INTEL_INFO(dev)->gen >= 6) { 259 err_printf(m, " RC PSMI: 0x%08x\n", error->rc_psmi[ring]); 260 err_printf(m, " FAULT_REG: 0x%08x\n", error->fault_reg[ring]); 261 err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n", 262 error->semaphore_mboxes[ring][0], 263 error->semaphore_seqno[ring][0]); 264 err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n", 265 error->semaphore_mboxes[ring][1], 266 error->semaphore_seqno[ring][1]); 267 if (HAS_VEBOX(dev)) { 268 err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n", 269 error->semaphore_mboxes[ring][2], 270 error->semaphore_seqno[ring][2]); 271 } 272 } 273 err_printf(m, " seqno: 0x%08x\n", error->seqno[ring]); 274 err_printf(m, " waiting: %s\n", yesno(error->waiting[ring])); 275 err_printf(m, " ring->head: 0x%08x\n", error->cpu_ring_head[ring]); 276 err_printf(m, " ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]); 277 err_printf(m, " hangcheck: %s [%d]\n", 278 hangcheck_action_to_str(error->hangcheck_action[ring]), 279 error->hangcheck_score[ring]); 280 } 281 282 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) 283 { 284 va_list args; 285 286 va_start(args, f); 287 i915_error_vprintf(e, f, args); 288 va_end(args); 289 } 290 291 int i915_error_state_to_str(struct drm_i915_error_state_buf *m, 292 const struct i915_error_state_file_priv *error_priv) 293 { 294 struct drm_device *dev = error_priv->dev; 295 drm_i915_private_t *dev_priv = dev->dev_private; 296 struct drm_i915_error_state *error = error_priv->error; 297 struct intel_ring_buffer *ring; 298 int i, j, page, offset, elt; 299 300 if (!error) { 301 err_printf(m, "no error state collected\n"); 302 goto out; 303 } 304 305 err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec, 306 error->time.tv_usec); 307 err_printf(m, "Kernel: " UTS_RELEASE "\n"); 308 err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device); 309 err_printf(m, "EIR: 0x%08x\n", error->eir); 310 err_printf(m, "IER: 0x%08x\n", error->ier); 311 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er); 312 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake); 313 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr); 314 err_printf(m, "CCID: 0x%08x\n", error->ccid); 315 err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings); 316 317 for (i = 0; i < dev_priv->num_fence_regs; i++) 318 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]); 319 320 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++) 321 err_printf(m, " INSTDONE_%d: 0x%08x\n", i, 322 error->extra_instdone[i]); 323 324 if (INTEL_INFO(dev)->gen >= 6) { 325 err_printf(m, "ERROR: 0x%08x\n", error->error); 326 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); 327 } 328 329 if (INTEL_INFO(dev)->gen == 7) 330 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int); 331 332 for_each_ring(ring, dev_priv, i) 333 i915_ring_error_state(m, dev, error, i); 334 335 if (error->active_bo) 336 print_error_buffers(m, "Active", 337 error->active_bo[0], 338 error->active_bo_count[0]); 339 340 if (error->pinned_bo) 341 print_error_buffers(m, "Pinned", 342 error->pinned_bo[0], 343 error->pinned_bo_count[0]); 344 345 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 346 struct drm_i915_error_object *obj; 347 348 if ((obj = error->ring[i].batchbuffer)) { 349 err_printf(m, "%s --- gtt_offset = 0x%08x\n", 350 dev_priv->ring[i].name, 351 obj->gtt_offset); 352 offset = 0; 353 for (page = 0; page < obj->page_count; page++) { 354 for (elt = 0; elt < PAGE_SIZE/4; elt++) { 355 err_printf(m, "%08x : %08x\n", offset, 356 obj->pages[page][elt]); 357 offset += 4; 358 } 359 } 360 } 361 362 if (error->ring[i].num_requests) { 363 err_printf(m, "%s --- %d requests\n", 364 dev_priv->ring[i].name, 365 error->ring[i].num_requests); 366 for (j = 0; j < error->ring[i].num_requests; j++) { 367 err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n", 368 error->ring[i].requests[j].seqno, 369 error->ring[i].requests[j].jiffies, 370 error->ring[i].requests[j].tail); 371 } 372 } 373 374 if ((obj = error->ring[i].ringbuffer)) { 375 err_printf(m, "%s --- ringbuffer = 0x%08x\n", 376 dev_priv->ring[i].name, 377 obj->gtt_offset); 378 offset = 0; 379 for (page = 0; page < obj->page_count; page++) { 380 for (elt = 0; elt < PAGE_SIZE/4; elt++) { 381 err_printf(m, "%08x : %08x\n", 382 offset, 383 obj->pages[page][elt]); 384 offset += 4; 385 } 386 } 387 } 388 389 obj = error->ring[i].ctx; 390 if (obj) { 391 err_printf(m, "%s --- HW Context = 0x%08x\n", 392 dev_priv->ring[i].name, 393 obj->gtt_offset); 394 offset = 0; 395 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) { 396 err_printf(m, "[%04x] %08x %08x %08x %08x\n", 397 offset, 398 obj->pages[0][elt], 399 obj->pages[0][elt+1], 400 obj->pages[0][elt+2], 401 obj->pages[0][elt+3]); 402 offset += 16; 403 } 404 } 405 } 406 407 if (error->overlay) 408 intel_overlay_print_error_state(m, error->overlay); 409 410 if (error->display) 411 intel_display_print_error_state(m, dev, error->display); 412 413 out: 414 if (m->bytes == 0 && m->err) 415 return m->err; 416 417 return 0; 418 } 419 420 int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf, 421 size_t count, loff_t pos) 422 { 423 memset(ebuf, 0, sizeof(*ebuf)); 424 425 /* We need to have enough room to store any i915_error_state printf 426 * so that we can move it to start position. 427 */ 428 ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE; 429 ebuf->buf = kmalloc(ebuf->size, 430 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN); 431 432 if (ebuf->buf == NULL) { 433 ebuf->size = PAGE_SIZE; 434 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY); 435 } 436 437 if (ebuf->buf == NULL) { 438 ebuf->size = 128; 439 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY); 440 } 441 442 if (ebuf->buf == NULL) 443 return -ENOMEM; 444 445 ebuf->start = pos; 446 447 return 0; 448 } 449 450 static void i915_error_object_free(struct drm_i915_error_object *obj) 451 { 452 int page; 453 454 if (obj == NULL) 455 return; 456 457 for (page = 0; page < obj->page_count; page++) 458 kfree(obj->pages[page]); 459 460 kfree(obj); 461 } 462 463 static void i915_error_state_free(struct kref *error_ref) 464 { 465 struct drm_i915_error_state *error = container_of(error_ref, 466 typeof(*error), ref); 467 int i; 468 469 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 470 i915_error_object_free(error->ring[i].batchbuffer); 471 i915_error_object_free(error->ring[i].ringbuffer); 472 i915_error_object_free(error->ring[i].ctx); 473 kfree(error->ring[i].requests); 474 } 475 476 kfree(error->active_bo); 477 kfree(error->overlay); 478 kfree(error->display); 479 kfree(error); 480 } 481 482 static struct drm_i915_error_object * 483 i915_error_object_create_sized(struct drm_i915_private *dev_priv, 484 struct drm_i915_gem_object *src, 485 const int num_pages) 486 { 487 struct drm_i915_error_object *dst; 488 int i; 489 u32 reloc_offset; 490 491 if (src == NULL || src->pages == NULL) 492 return NULL; 493 494 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC); 495 if (dst == NULL) 496 return NULL; 497 498 reloc_offset = dst->gtt_offset = i915_gem_obj_ggtt_offset(src); 499 for (i = 0; i < num_pages; i++) { 500 unsigned long flags; 501 void *d; 502 503 d = kmalloc(PAGE_SIZE, GFP_ATOMIC); 504 if (d == NULL) 505 goto unwind; 506 507 local_irq_save(flags); 508 if (reloc_offset < dev_priv->gtt.mappable_end && 509 src->has_global_gtt_mapping) { 510 void __iomem *s; 511 512 /* Simply ignore tiling or any overlapping fence. 513 * It's part of the error state, and this hopefully 514 * captures what the GPU read. 515 */ 516 517 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable, 518 reloc_offset); 519 memcpy_fromio(d, s, PAGE_SIZE); 520 io_mapping_unmap_atomic(s); 521 } else if (src->stolen) { 522 unsigned long offset; 523 524 offset = dev_priv->mm.stolen_base; 525 offset += src->stolen->start; 526 offset += i << PAGE_SHIFT; 527 528 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE); 529 } else { 530 struct page *page; 531 void *s; 532 533 page = i915_gem_object_get_page(src, i); 534 535 drm_clflush_pages(&page, 1); 536 537 s = kmap_atomic(page); 538 memcpy(d, s, PAGE_SIZE); 539 kunmap_atomic(s); 540 541 drm_clflush_pages(&page, 1); 542 } 543 local_irq_restore(flags); 544 545 dst->pages[i] = d; 546 547 reloc_offset += PAGE_SIZE; 548 } 549 dst->page_count = num_pages; 550 551 return dst; 552 553 unwind: 554 while (i--) 555 kfree(dst->pages[i]); 556 kfree(dst); 557 return NULL; 558 } 559 #define i915_error_object_create(dev_priv, src) \ 560 i915_error_object_create_sized((dev_priv), (src), \ 561 (src)->base.size>>PAGE_SHIFT) 562 563 static void capture_bo(struct drm_i915_error_buffer *err, 564 struct drm_i915_gem_object *obj) 565 { 566 err->size = obj->base.size; 567 err->name = obj->base.name; 568 err->rseqno = obj->last_read_seqno; 569 err->wseqno = obj->last_write_seqno; 570 err->gtt_offset = i915_gem_obj_ggtt_offset(obj); 571 err->read_domains = obj->base.read_domains; 572 err->write_domain = obj->base.write_domain; 573 err->fence_reg = obj->fence_reg; 574 err->pinned = 0; 575 if (obj->pin_count > 0) 576 err->pinned = 1; 577 if (obj->user_pin_count > 0) 578 err->pinned = -1; 579 err->tiling = obj->tiling_mode; 580 err->dirty = obj->dirty; 581 err->purgeable = obj->madv != I915_MADV_WILLNEED; 582 err->ring = obj->ring ? obj->ring->id : -1; 583 err->cache_level = obj->cache_level; 584 } 585 586 static u32 capture_active_bo(struct drm_i915_error_buffer *err, 587 int count, struct list_head *head) 588 { 589 struct i915_vma *vma; 590 int i = 0; 591 592 list_for_each_entry(vma, head, mm_list) { 593 capture_bo(err++, vma->obj); 594 if (++i == count) 595 break; 596 } 597 598 return i; 599 } 600 601 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err, 602 int count, struct list_head *head) 603 { 604 struct drm_i915_gem_object *obj; 605 int i = 0; 606 607 list_for_each_entry(obj, head, global_list) { 608 if (obj->pin_count == 0) 609 continue; 610 611 capture_bo(err++, obj); 612 if (++i == count) 613 break; 614 } 615 616 return i; 617 } 618 619 static void i915_gem_record_fences(struct drm_device *dev, 620 struct drm_i915_error_state *error) 621 { 622 struct drm_i915_private *dev_priv = dev->dev_private; 623 int i; 624 625 /* Fences */ 626 switch (INTEL_INFO(dev)->gen) { 627 case 8: 628 case 7: 629 case 6: 630 for (i = 0; i < dev_priv->num_fence_regs; i++) 631 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8)); 632 break; 633 case 5: 634 case 4: 635 for (i = 0; i < 16; i++) 636 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8)); 637 break; 638 case 3: 639 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) 640 for (i = 0; i < 8; i++) 641 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4)); 642 case 2: 643 for (i = 0; i < 8; i++) 644 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); 645 break; 646 647 default: 648 BUG(); 649 } 650 } 651 652 static struct drm_i915_error_object * 653 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv, 654 struct intel_ring_buffer *ring) 655 { 656 struct i915_address_space *vm; 657 struct i915_vma *vma; 658 struct drm_i915_gem_object *obj; 659 u32 seqno; 660 661 if (!ring->get_seqno) 662 return NULL; 663 664 if (HAS_BROKEN_CS_TLB(dev_priv->dev)) { 665 u32 acthd = I915_READ(ACTHD); 666 667 if (WARN_ON(ring->id != RCS)) 668 return NULL; 669 670 obj = ring->scratch.obj; 671 if (acthd >= i915_gem_obj_ggtt_offset(obj) && 672 acthd < i915_gem_obj_ggtt_offset(obj) + obj->base.size) 673 return i915_error_object_create(dev_priv, obj); 674 } 675 676 seqno = ring->get_seqno(ring, false); 677 list_for_each_entry(vm, &dev_priv->vm_list, global_link) { 678 list_for_each_entry(vma, &vm->active_list, mm_list) { 679 obj = vma->obj; 680 if (obj->ring != ring) 681 continue; 682 683 if (i915_seqno_passed(seqno, obj->last_read_seqno)) 684 continue; 685 686 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0) 687 continue; 688 689 /* We need to copy these to an anonymous buffer as the simplest 690 * method to avoid being overwritten by userspace. 691 */ 692 return i915_error_object_create(dev_priv, obj); 693 } 694 } 695 696 return NULL; 697 } 698 699 static void i915_record_ring_state(struct drm_device *dev, 700 struct drm_i915_error_state *error, 701 struct intel_ring_buffer *ring) 702 { 703 struct drm_i915_private *dev_priv = dev->dev_private; 704 705 if (INTEL_INFO(dev)->gen >= 6) { 706 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50); 707 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring)); 708 error->semaphore_mboxes[ring->id][0] 709 = I915_READ(RING_SYNC_0(ring->mmio_base)); 710 error->semaphore_mboxes[ring->id][1] 711 = I915_READ(RING_SYNC_1(ring->mmio_base)); 712 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0]; 713 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1]; 714 } 715 716 if (HAS_VEBOX(dev)) { 717 error->semaphore_mboxes[ring->id][2] = 718 I915_READ(RING_SYNC_2(ring->mmio_base)); 719 error->semaphore_seqno[ring->id][2] = ring->sync_seqno[2]; 720 } 721 722 if (INTEL_INFO(dev)->gen >= 4) { 723 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base)); 724 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base)); 725 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base)); 726 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base)); 727 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base)); 728 if (ring->id == RCS) 729 error->bbaddr = I915_READ64(BB_ADDR); 730 error->bbstate[ring->id] = I915_READ(RING_BBSTATE(ring->mmio_base)); 731 } else { 732 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX); 733 error->ipeir[ring->id] = I915_READ(IPEIR); 734 error->ipehr[ring->id] = I915_READ(IPEHR); 735 error->instdone[ring->id] = I915_READ(INSTDONE); 736 } 737 738 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue); 739 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base)); 740 error->seqno[ring->id] = ring->get_seqno(ring, false); 741 error->acthd[ring->id] = intel_ring_get_active_head(ring); 742 error->head[ring->id] = I915_READ_HEAD(ring); 743 error->tail[ring->id] = I915_READ_TAIL(ring); 744 error->ctl[ring->id] = I915_READ_CTL(ring); 745 746 error->cpu_ring_head[ring->id] = ring->head; 747 error->cpu_ring_tail[ring->id] = ring->tail; 748 749 error->hangcheck_score[ring->id] = ring->hangcheck.score; 750 error->hangcheck_action[ring->id] = ring->hangcheck.action; 751 } 752 753 754 static void i915_gem_record_active_context(struct intel_ring_buffer *ring, 755 struct drm_i915_error_state *error, 756 struct drm_i915_error_ring *ering) 757 { 758 struct drm_i915_private *dev_priv = ring->dev->dev_private; 759 struct drm_i915_gem_object *obj; 760 761 /* Currently render ring is the only HW context user */ 762 if (ring->id != RCS || !error->ccid) 763 return; 764 765 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { 766 if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) { 767 ering->ctx = i915_error_object_create_sized(dev_priv, 768 obj, 1); 769 break; 770 } 771 } 772 } 773 774 static void i915_gem_record_rings(struct drm_device *dev, 775 struct drm_i915_error_state *error) 776 { 777 struct drm_i915_private *dev_priv = dev->dev_private; 778 struct intel_ring_buffer *ring; 779 struct drm_i915_gem_request *request; 780 int i, count; 781 782 for_each_ring(ring, dev_priv, i) { 783 i915_record_ring_state(dev, error, ring); 784 785 error->ring[i].batchbuffer = 786 i915_error_first_batchbuffer(dev_priv, ring); 787 788 error->ring[i].ringbuffer = 789 i915_error_object_create(dev_priv, ring->obj); 790 791 792 i915_gem_record_active_context(ring, error, &error->ring[i]); 793 794 count = 0; 795 list_for_each_entry(request, &ring->request_list, list) 796 count++; 797 798 error->ring[i].num_requests = count; 799 error->ring[i].requests = 800 kcalloc(count, sizeof(*error->ring[i].requests), 801 GFP_ATOMIC); 802 if (error->ring[i].requests == NULL) { 803 error->ring[i].num_requests = 0; 804 continue; 805 } 806 807 count = 0; 808 list_for_each_entry(request, &ring->request_list, list) { 809 struct drm_i915_error_request *erq; 810 811 erq = &error->ring[i].requests[count++]; 812 erq->seqno = request->seqno; 813 erq->jiffies = request->emitted_jiffies; 814 erq->tail = request->tail; 815 } 816 } 817 } 818 819 /* FIXME: Since pin count/bound list is global, we duplicate what we capture per 820 * VM. 821 */ 822 static void i915_gem_capture_vm(struct drm_i915_private *dev_priv, 823 struct drm_i915_error_state *error, 824 struct i915_address_space *vm, 825 const int ndx) 826 { 827 struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL; 828 struct drm_i915_gem_object *obj; 829 struct i915_vma *vma; 830 int i; 831 832 i = 0; 833 list_for_each_entry(vma, &vm->active_list, mm_list) 834 i++; 835 error->active_bo_count[ndx] = i; 836 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) 837 if (obj->pin_count) 838 i++; 839 error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx]; 840 841 if (i) { 842 active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC); 843 if (active_bo) 844 pinned_bo = active_bo + error->active_bo_count[ndx]; 845 } 846 847 if (active_bo) 848 error->active_bo_count[ndx] = 849 capture_active_bo(active_bo, 850 error->active_bo_count[ndx], 851 &vm->active_list); 852 853 if (pinned_bo) 854 error->pinned_bo_count[ndx] = 855 capture_pinned_bo(pinned_bo, 856 error->pinned_bo_count[ndx], 857 &dev_priv->mm.bound_list); 858 error->active_bo[ndx] = active_bo; 859 error->pinned_bo[ndx] = pinned_bo; 860 } 861 862 static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv, 863 struct drm_i915_error_state *error) 864 { 865 struct i915_address_space *vm; 866 int cnt = 0, i = 0; 867 868 list_for_each_entry(vm, &dev_priv->vm_list, global_link) 869 cnt++; 870 871 if (WARN(cnt > 1, "Multiple VMs not yet supported\n")) 872 cnt = 1; 873 874 vm = &dev_priv->gtt.base; 875 876 error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC); 877 error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC); 878 error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count), 879 GFP_ATOMIC); 880 error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count), 881 GFP_ATOMIC); 882 883 list_for_each_entry(vm, &dev_priv->vm_list, global_link) 884 i915_gem_capture_vm(dev_priv, error, vm, i++); 885 } 886 887 /** 888 * i915_capture_error_state - capture an error record for later analysis 889 * @dev: drm device 890 * 891 * Should be called when an error is detected (either a hang or an error 892 * interrupt) to capture error state from the time of the error. Fills 893 * out a structure which becomes available in debugfs for user level tools 894 * to pick up. 895 */ 896 void i915_capture_error_state(struct drm_device *dev) 897 { 898 struct drm_i915_private *dev_priv = dev->dev_private; 899 struct drm_i915_error_state *error; 900 unsigned long flags; 901 int pipe; 902 903 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); 904 error = dev_priv->gpu_error.first_error; 905 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); 906 if (error) 907 return; 908 909 /* Account for pipe specific data like PIPE*STAT */ 910 error = kzalloc(sizeof(*error), GFP_ATOMIC); 911 if (!error) { 912 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); 913 return; 914 } 915 916 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", 917 dev->primary->index); 918 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n"); 919 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n"); 920 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n"); 921 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n"); 922 923 kref_init(&error->ref); 924 error->eir = I915_READ(EIR); 925 error->pgtbl_er = I915_READ(PGTBL_ER); 926 if (HAS_HW_CONTEXTS(dev)) 927 error->ccid = I915_READ(CCID); 928 929 if (HAS_PCH_SPLIT(dev)) 930 error->ier = I915_READ(DEIER) | I915_READ(GTIER); 931 else if (IS_VALLEYVIEW(dev)) 932 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER); 933 else if (IS_GEN2(dev)) 934 error->ier = I915_READ16(IER); 935 else 936 error->ier = I915_READ(IER); 937 938 if (INTEL_INFO(dev)->gen >= 6) 939 error->derrmr = I915_READ(DERRMR); 940 941 if (IS_VALLEYVIEW(dev)) 942 error->forcewake = I915_READ(FORCEWAKE_VLV); 943 else if (INTEL_INFO(dev)->gen >= 7) 944 error->forcewake = I915_READ(FORCEWAKE_MT); 945 else if (INTEL_INFO(dev)->gen == 6) 946 error->forcewake = I915_READ(FORCEWAKE); 947 948 if (!HAS_PCH_SPLIT(dev)) 949 for_each_pipe(pipe) 950 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe)); 951 952 if (INTEL_INFO(dev)->gen >= 6) { 953 error->error = I915_READ(ERROR_GEN6); 954 error->done_reg = I915_READ(DONE_REG); 955 } 956 957 if (INTEL_INFO(dev)->gen == 7) 958 error->err_int = I915_READ(GEN7_ERR_INT); 959 960 i915_get_extra_instdone(dev, error->extra_instdone); 961 962 i915_gem_capture_buffers(dev_priv, error); 963 i915_gem_record_fences(dev, error); 964 i915_gem_record_rings(dev, error); 965 966 do_gettimeofday(&error->time); 967 968 error->overlay = intel_overlay_capture_error_state(dev); 969 error->display = intel_display_capture_error_state(dev); 970 971 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); 972 if (dev_priv->gpu_error.first_error == NULL) { 973 dev_priv->gpu_error.first_error = error; 974 error = NULL; 975 } 976 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); 977 978 if (error) 979 i915_error_state_free(&error->ref); 980 } 981 982 void i915_error_state_get(struct drm_device *dev, 983 struct i915_error_state_file_priv *error_priv) 984 { 985 struct drm_i915_private *dev_priv = dev->dev_private; 986 unsigned long flags; 987 988 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); 989 error_priv->error = dev_priv->gpu_error.first_error; 990 if (error_priv->error) 991 kref_get(&error_priv->error->ref); 992 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); 993 994 } 995 996 void i915_error_state_put(struct i915_error_state_file_priv *error_priv) 997 { 998 if (error_priv->error) 999 kref_put(&error_priv->error->ref, i915_error_state_free); 1000 } 1001 1002 void i915_destroy_error_state(struct drm_device *dev) 1003 { 1004 struct drm_i915_private *dev_priv = dev->dev_private; 1005 struct drm_i915_error_state *error; 1006 unsigned long flags; 1007 1008 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); 1009 error = dev_priv->gpu_error.first_error; 1010 dev_priv->gpu_error.first_error = NULL; 1011 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); 1012 1013 if (error) 1014 kref_put(&error->ref, i915_error_state_free); 1015 } 1016 1017 const char *i915_cache_level_str(int type) 1018 { 1019 switch (type) { 1020 case I915_CACHE_NONE: return " uncached"; 1021 case I915_CACHE_LLC: return " snooped or LLC"; 1022 case I915_CACHE_L3_LLC: return " L3+LLC"; 1023 case I915_CACHE_WT: return " WT"; 1024 default: return ""; 1025 } 1026 } 1027 1028 /* NB: please notice the memset */ 1029 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone) 1030 { 1031 struct drm_i915_private *dev_priv = dev->dev_private; 1032 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG); 1033 1034 switch (INTEL_INFO(dev)->gen) { 1035 case 2: 1036 case 3: 1037 instdone[0] = I915_READ(INSTDONE); 1038 break; 1039 case 4: 1040 case 5: 1041 case 6: 1042 instdone[0] = I915_READ(INSTDONE_I965); 1043 instdone[1] = I915_READ(INSTDONE1); 1044 break; 1045 default: 1046 WARN_ONCE(1, "Unsupported platform\n"); 1047 case 7: 1048 case 8: 1049 instdone[0] = I915_READ(GEN7_INSTDONE_1); 1050 instdone[1] = I915_READ(GEN7_SC_INSTDONE); 1051 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE); 1052 instdone[3] = I915_READ(GEN7_ROW_INSTDONE); 1053 break; 1054 } 1055 } 1056