1 /* 2 * Copyright (c) 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * Mika Kuoppala <mika.kuoppala@intel.com> 27 * 28 */ 29 30 #include <linux/ascii85.h> 31 #include <linux/nmi.h> 32 #include <linux/pagevec.h> 33 #include <linux/scatterlist.h> 34 #include <linux/utsname.h> 35 #include <linux/zlib.h> 36 37 #include <drm/drm_print.h> 38 39 #include "display/intel_atomic.h" 40 #include "display/intel_csr.h" 41 #include "display/intel_overlay.h" 42 43 #include "gem/i915_gem_context.h" 44 #include "gem/i915_gem_lmem.h" 45 #include "gt/intel_gt.h" 46 #include "gt/intel_gt_pm.h" 47 48 #include "i915_drv.h" 49 #include "i915_gpu_error.h" 50 #include "i915_memcpy.h" 51 #include "i915_scatterlist.h" 52 53 #define ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN) 54 #define ATOMIC_MAYFAIL (GFP_ATOMIC | __GFP_NOWARN) 55 56 static void __sg_set_buf(struct scatterlist *sg, 57 void *addr, unsigned int len, loff_t it) 58 { 59 sg->page_link = (unsigned long)virt_to_page(addr); 60 sg->offset = offset_in_page(addr); 61 sg->length = len; 62 sg->dma_address = it; 63 } 64 65 static bool __i915_error_grow(struct drm_i915_error_state_buf *e, size_t len) 66 { 67 if (!len) 68 return false; 69 70 if (e->bytes + len + 1 <= e->size) 71 return true; 72 73 if (e->bytes) { 74 __sg_set_buf(e->cur++, e->buf, e->bytes, e->iter); 75 e->iter += e->bytes; 76 e->buf = NULL; 77 e->bytes = 0; 78 } 79 80 if (e->cur == e->end) { 81 struct scatterlist *sgl; 82 83 sgl = (typeof(sgl))__get_free_page(ALLOW_FAIL); 84 if (!sgl) { 85 e->err = -ENOMEM; 86 return false; 87 } 88 89 if (e->cur) { 90 e->cur->offset = 0; 91 e->cur->length = 0; 92 e->cur->page_link = 93 (unsigned long)sgl | SG_CHAIN; 94 } else { 95 e->sgl = sgl; 96 } 97 98 e->cur = sgl; 99 e->end = sgl + SG_MAX_SINGLE_ALLOC - 1; 100 } 101 102 e->size = ALIGN(len + 1, SZ_64K); 103 e->buf = kmalloc(e->size, ALLOW_FAIL); 104 if (!e->buf) { 105 e->size = PAGE_ALIGN(len + 1); 106 e->buf = kmalloc(e->size, GFP_KERNEL); 107 } 108 if (!e->buf) { 109 e->err = -ENOMEM; 110 return false; 111 } 112 113 return true; 114 } 115 116 __printf(2, 0) 117 static void i915_error_vprintf(struct drm_i915_error_state_buf *e, 118 const char *fmt, va_list args) 119 { 120 va_list ap; 121 int len; 122 123 if (e->err) 124 return; 125 126 va_copy(ap, args); 127 len = vsnprintf(NULL, 0, fmt, ap); 128 va_end(ap); 129 if (len <= 0) { 130 e->err = len; 131 return; 132 } 133 134 if (!__i915_error_grow(e, len)) 135 return; 136 137 GEM_BUG_ON(e->bytes >= e->size); 138 len = vscnprintf(e->buf + e->bytes, e->size - e->bytes, fmt, args); 139 if (len < 0) { 140 e->err = len; 141 return; 142 } 143 e->bytes += len; 144 } 145 146 static void i915_error_puts(struct drm_i915_error_state_buf *e, const char *str) 147 { 148 unsigned len; 149 150 if (e->err || !str) 151 return; 152 153 len = strlen(str); 154 if (!__i915_error_grow(e, len)) 155 return; 156 157 GEM_BUG_ON(e->bytes + len > e->size); 158 memcpy(e->buf + e->bytes, str, len); 159 e->bytes += len; 160 } 161 162 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) 163 #define err_puts(e, s) i915_error_puts(e, s) 164 165 static void __i915_printfn_error(struct drm_printer *p, struct va_format *vaf) 166 { 167 i915_error_vprintf(p->arg, vaf->fmt, *vaf->va); 168 } 169 170 static inline struct drm_printer 171 i915_error_printer(struct drm_i915_error_state_buf *e) 172 { 173 struct drm_printer p = { 174 .printfn = __i915_printfn_error, 175 .arg = e, 176 }; 177 return p; 178 } 179 180 /* single threaded page allocator with a reserved stash for emergencies */ 181 static void pool_fini(struct pagevec *pv) 182 { 183 pagevec_release(pv); 184 } 185 186 static int pool_refill(struct pagevec *pv, gfp_t gfp) 187 { 188 while (pagevec_space(pv)) { 189 struct page *p; 190 191 p = alloc_page(gfp); 192 if (!p) 193 return -ENOMEM; 194 195 pagevec_add(pv, p); 196 } 197 198 return 0; 199 } 200 201 static int pool_init(struct pagevec *pv, gfp_t gfp) 202 { 203 int err; 204 205 pagevec_init(pv); 206 207 err = pool_refill(pv, gfp); 208 if (err) 209 pool_fini(pv); 210 211 return err; 212 } 213 214 static void *pool_alloc(struct pagevec *pv, gfp_t gfp) 215 { 216 struct page *p; 217 218 p = alloc_page(gfp); 219 if (!p && pagevec_count(pv)) 220 p = pv->pages[--pv->nr]; 221 222 return p ? page_address(p) : NULL; 223 } 224 225 static void pool_free(struct pagevec *pv, void *addr) 226 { 227 struct page *p = virt_to_page(addr); 228 229 if (pagevec_space(pv)) 230 pagevec_add(pv, p); 231 else 232 __free_page(p); 233 } 234 235 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR 236 237 struct i915_vma_compress { 238 struct pagevec pool; 239 struct z_stream_s zstream; 240 void *tmp; 241 }; 242 243 static bool compress_init(struct i915_vma_compress *c) 244 { 245 struct z_stream_s *zstream = &c->zstream; 246 247 if (pool_init(&c->pool, ALLOW_FAIL)) 248 return false; 249 250 zstream->workspace = 251 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL), 252 ALLOW_FAIL); 253 if (!zstream->workspace) { 254 pool_fini(&c->pool); 255 return false; 256 } 257 258 c->tmp = NULL; 259 if (i915_has_memcpy_from_wc()) 260 c->tmp = pool_alloc(&c->pool, ALLOW_FAIL); 261 262 return true; 263 } 264 265 static bool compress_start(struct i915_vma_compress *c) 266 { 267 struct z_stream_s *zstream = &c->zstream; 268 void *workspace = zstream->workspace; 269 270 memset(zstream, 0, sizeof(*zstream)); 271 zstream->workspace = workspace; 272 273 return zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) == Z_OK; 274 } 275 276 static void *compress_next_page(struct i915_vma_compress *c, 277 struct i915_vma_coredump *dst) 278 { 279 void *page; 280 281 if (dst->page_count >= dst->num_pages) 282 return ERR_PTR(-ENOSPC); 283 284 page = pool_alloc(&c->pool, ALLOW_FAIL); 285 if (!page) 286 return ERR_PTR(-ENOMEM); 287 288 return dst->pages[dst->page_count++] = page; 289 } 290 291 static int compress_page(struct i915_vma_compress *c, 292 void *src, 293 struct i915_vma_coredump *dst, 294 bool wc) 295 { 296 struct z_stream_s *zstream = &c->zstream; 297 298 zstream->next_in = src; 299 if (wc && c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE)) 300 zstream->next_in = c->tmp; 301 zstream->avail_in = PAGE_SIZE; 302 303 do { 304 if (zstream->avail_out == 0) { 305 zstream->next_out = compress_next_page(c, dst); 306 if (IS_ERR(zstream->next_out)) 307 return PTR_ERR(zstream->next_out); 308 309 zstream->avail_out = PAGE_SIZE; 310 } 311 312 if (zlib_deflate(zstream, Z_NO_FLUSH) != Z_OK) 313 return -EIO; 314 } while (zstream->avail_in); 315 316 /* Fallback to uncompressed if we increase size? */ 317 if (0 && zstream->total_out > zstream->total_in) 318 return -E2BIG; 319 320 return 0; 321 } 322 323 static int compress_flush(struct i915_vma_compress *c, 324 struct i915_vma_coredump *dst) 325 { 326 struct z_stream_s *zstream = &c->zstream; 327 328 do { 329 switch (zlib_deflate(zstream, Z_FINISH)) { 330 case Z_OK: /* more space requested */ 331 zstream->next_out = compress_next_page(c, dst); 332 if (IS_ERR(zstream->next_out)) 333 return PTR_ERR(zstream->next_out); 334 335 zstream->avail_out = PAGE_SIZE; 336 break; 337 338 case Z_STREAM_END: 339 goto end; 340 341 default: /* any error */ 342 return -EIO; 343 } 344 } while (1); 345 346 end: 347 memset(zstream->next_out, 0, zstream->avail_out); 348 dst->unused = zstream->avail_out; 349 return 0; 350 } 351 352 static void compress_finish(struct i915_vma_compress *c) 353 { 354 zlib_deflateEnd(&c->zstream); 355 } 356 357 static void compress_fini(struct i915_vma_compress *c) 358 { 359 kfree(c->zstream.workspace); 360 if (c->tmp) 361 pool_free(&c->pool, c->tmp); 362 pool_fini(&c->pool); 363 } 364 365 static void err_compression_marker(struct drm_i915_error_state_buf *m) 366 { 367 err_puts(m, ":"); 368 } 369 370 #else 371 372 struct i915_vma_compress { 373 struct pagevec pool; 374 }; 375 376 static bool compress_init(struct i915_vma_compress *c) 377 { 378 return pool_init(&c->pool, ALLOW_FAIL) == 0; 379 } 380 381 static bool compress_start(struct i915_vma_compress *c) 382 { 383 return true; 384 } 385 386 static int compress_page(struct i915_vma_compress *c, 387 void *src, 388 struct i915_vma_coredump *dst, 389 bool wc) 390 { 391 void *ptr; 392 393 ptr = pool_alloc(&c->pool, ALLOW_FAIL); 394 if (!ptr) 395 return -ENOMEM; 396 397 if (!(wc && i915_memcpy_from_wc(ptr, src, PAGE_SIZE))) 398 memcpy(ptr, src, PAGE_SIZE); 399 dst->pages[dst->page_count++] = ptr; 400 401 return 0; 402 } 403 404 static int compress_flush(struct i915_vma_compress *c, 405 struct i915_vma_coredump *dst) 406 { 407 return 0; 408 } 409 410 static void compress_finish(struct i915_vma_compress *c) 411 { 412 } 413 414 static void compress_fini(struct i915_vma_compress *c) 415 { 416 pool_fini(&c->pool); 417 } 418 419 static void err_compression_marker(struct drm_i915_error_state_buf *m) 420 { 421 err_puts(m, "~"); 422 } 423 424 #endif 425 426 static void error_print_instdone(struct drm_i915_error_state_buf *m, 427 const struct intel_engine_coredump *ee) 428 { 429 const struct sseu_dev_info *sseu = &ee->engine->gt->info.sseu; 430 int slice; 431 int subslice; 432 433 err_printf(m, " INSTDONE: 0x%08x\n", 434 ee->instdone.instdone); 435 436 if (ee->engine->class != RENDER_CLASS || INTEL_GEN(m->i915) <= 3) 437 return; 438 439 err_printf(m, " SC_INSTDONE: 0x%08x\n", 440 ee->instdone.slice_common); 441 442 if (INTEL_GEN(m->i915) <= 6) 443 return; 444 445 for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice) 446 err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n", 447 slice, subslice, 448 ee->instdone.sampler[slice][subslice]); 449 450 for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice) 451 err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n", 452 slice, subslice, 453 ee->instdone.row[slice][subslice]); 454 455 if (INTEL_GEN(m->i915) < 12) 456 return; 457 458 err_printf(m, " SC_INSTDONE_EXTRA: 0x%08x\n", 459 ee->instdone.slice_common_extra[0]); 460 err_printf(m, " SC_INSTDONE_EXTRA2: 0x%08x\n", 461 ee->instdone.slice_common_extra[1]); 462 } 463 464 static void error_print_request(struct drm_i915_error_state_buf *m, 465 const char *prefix, 466 const struct i915_request_coredump *erq) 467 { 468 if (!erq->seqno) 469 return; 470 471 err_printf(m, "%s pid %d, seqno %8x:%08x%s%s, prio %d, head %08x, tail %08x\n", 472 prefix, erq->pid, erq->context, erq->seqno, 473 test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, 474 &erq->flags) ? "!" : "", 475 test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, 476 &erq->flags) ? "+" : "", 477 erq->sched_attr.priority, 478 erq->head, erq->tail); 479 } 480 481 static void error_print_context(struct drm_i915_error_state_buf *m, 482 const char *header, 483 const struct i915_gem_context_coredump *ctx) 484 { 485 const u32 period = RUNTIME_INFO(m->i915)->cs_timestamp_period_ns; 486 487 err_printf(m, "%s%s[%d] prio %d, guilty %d active %d, runtime total %lluns, avg %lluns\n", 488 header, ctx->comm, ctx->pid, ctx->sched_attr.priority, 489 ctx->guilty, ctx->active, 490 ctx->total_runtime * period, 491 mul_u32_u32(ctx->avg_runtime, period)); 492 } 493 494 static struct i915_vma_coredump * 495 __find_vma(struct i915_vma_coredump *vma, const char *name) 496 { 497 while (vma) { 498 if (strcmp(vma->name, name) == 0) 499 return vma; 500 vma = vma->next; 501 } 502 503 return NULL; 504 } 505 506 static struct i915_vma_coredump * 507 find_batch(const struct intel_engine_coredump *ee) 508 { 509 return __find_vma(ee->vma, "batch"); 510 } 511 512 static void error_print_engine(struct drm_i915_error_state_buf *m, 513 const struct intel_engine_coredump *ee) 514 { 515 struct i915_vma_coredump *batch; 516 int n; 517 518 err_printf(m, "%s command stream:\n", ee->engine->name); 519 err_printf(m, " CCID: 0x%08x\n", ee->ccid); 520 err_printf(m, " START: 0x%08x\n", ee->start); 521 err_printf(m, " HEAD: 0x%08x [0x%08x]\n", ee->head, ee->rq_head); 522 err_printf(m, " TAIL: 0x%08x [0x%08x, 0x%08x]\n", 523 ee->tail, ee->rq_post, ee->rq_tail); 524 err_printf(m, " CTL: 0x%08x\n", ee->ctl); 525 err_printf(m, " MODE: 0x%08x\n", ee->mode); 526 err_printf(m, " HWS: 0x%08x\n", ee->hws); 527 err_printf(m, " ACTHD: 0x%08x %08x\n", 528 (u32)(ee->acthd>>32), (u32)ee->acthd); 529 err_printf(m, " IPEIR: 0x%08x\n", ee->ipeir); 530 err_printf(m, " IPEHR: 0x%08x\n", ee->ipehr); 531 err_printf(m, " ESR: 0x%08x\n", ee->esr); 532 533 error_print_instdone(m, ee); 534 535 batch = find_batch(ee); 536 if (batch) { 537 u64 start = batch->gtt_offset; 538 u64 end = start + batch->gtt_size; 539 540 err_printf(m, " batch: [0x%08x_%08x, 0x%08x_%08x]\n", 541 upper_32_bits(start), lower_32_bits(start), 542 upper_32_bits(end), lower_32_bits(end)); 543 } 544 if (INTEL_GEN(m->i915) >= 4) { 545 err_printf(m, " BBADDR: 0x%08x_%08x\n", 546 (u32)(ee->bbaddr>>32), (u32)ee->bbaddr); 547 err_printf(m, " BB_STATE: 0x%08x\n", ee->bbstate); 548 err_printf(m, " INSTPS: 0x%08x\n", ee->instps); 549 } 550 err_printf(m, " INSTPM: 0x%08x\n", ee->instpm); 551 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr), 552 lower_32_bits(ee->faddr)); 553 if (INTEL_GEN(m->i915) >= 6) { 554 err_printf(m, " RC PSMI: 0x%08x\n", ee->rc_psmi); 555 err_printf(m, " FAULT_REG: 0x%08x\n", ee->fault_reg); 556 } 557 if (HAS_PPGTT(m->i915)) { 558 err_printf(m, " GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode); 559 560 if (INTEL_GEN(m->i915) >= 8) { 561 int i; 562 for (i = 0; i < 4; i++) 563 err_printf(m, " PDP%d: 0x%016llx\n", 564 i, ee->vm_info.pdp[i]); 565 } else { 566 err_printf(m, " PP_DIR_BASE: 0x%08x\n", 567 ee->vm_info.pp_dir_base); 568 } 569 } 570 err_printf(m, " engine reset count: %u\n", ee->reset_count); 571 572 for (n = 0; n < ee->num_ports; n++) { 573 err_printf(m, " ELSP[%d]:", n); 574 error_print_request(m, " ", &ee->execlist[n]); 575 } 576 577 error_print_context(m, " Active context: ", &ee->context); 578 } 579 580 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) 581 { 582 va_list args; 583 584 va_start(args, f); 585 i915_error_vprintf(e, f, args); 586 va_end(args); 587 } 588 589 static void print_error_vma(struct drm_i915_error_state_buf *m, 590 const struct intel_engine_cs *engine, 591 const struct i915_vma_coredump *vma) 592 { 593 char out[ASCII85_BUFSZ]; 594 int page; 595 596 if (!vma) 597 return; 598 599 err_printf(m, "%s --- %s = 0x%08x %08x\n", 600 engine ? engine->name : "global", vma->name, 601 upper_32_bits(vma->gtt_offset), 602 lower_32_bits(vma->gtt_offset)); 603 604 if (vma->gtt_page_sizes > I915_GTT_PAGE_SIZE_4K) 605 err_printf(m, "gtt_page_sizes = 0x%08x\n", vma->gtt_page_sizes); 606 607 err_compression_marker(m); 608 for (page = 0; page < vma->page_count; page++) { 609 int i, len; 610 611 len = PAGE_SIZE; 612 if (page == vma->page_count - 1) 613 len -= vma->unused; 614 len = ascii85_encode_len(len); 615 616 for (i = 0; i < len; i++) 617 err_puts(m, ascii85_encode(vma->pages[page][i], out)); 618 } 619 err_puts(m, "\n"); 620 } 621 622 static void err_print_capabilities(struct drm_i915_error_state_buf *m, 623 struct i915_gpu_coredump *error) 624 { 625 struct drm_printer p = i915_error_printer(m); 626 627 intel_device_info_print_static(&error->device_info, &p); 628 intel_device_info_print_runtime(&error->runtime_info, &p); 629 intel_driver_caps_print(&error->driver_caps, &p); 630 } 631 632 static void err_print_params(struct drm_i915_error_state_buf *m, 633 const struct i915_params *params) 634 { 635 struct drm_printer p = i915_error_printer(m); 636 637 i915_params_dump(params, &p); 638 } 639 640 static void err_print_pciid(struct drm_i915_error_state_buf *m, 641 struct drm_i915_private *i915) 642 { 643 struct pci_dev *pdev = i915->drm.pdev; 644 645 err_printf(m, "PCI ID: 0x%04x\n", pdev->device); 646 err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision); 647 err_printf(m, "PCI Subsystem: %04x:%04x\n", 648 pdev->subsystem_vendor, 649 pdev->subsystem_device); 650 } 651 652 static void err_print_uc(struct drm_i915_error_state_buf *m, 653 const struct intel_uc_coredump *error_uc) 654 { 655 struct drm_printer p = i915_error_printer(m); 656 657 intel_uc_fw_dump(&error_uc->guc_fw, &p); 658 intel_uc_fw_dump(&error_uc->huc_fw, &p); 659 print_error_vma(m, NULL, error_uc->guc_log); 660 } 661 662 static void err_free_sgl(struct scatterlist *sgl) 663 { 664 while (sgl) { 665 struct scatterlist *sg; 666 667 for (sg = sgl; !sg_is_chain(sg); sg++) { 668 kfree(sg_virt(sg)); 669 if (sg_is_last(sg)) 670 break; 671 } 672 673 sg = sg_is_last(sg) ? NULL : sg_chain_ptr(sg); 674 free_page((unsigned long)sgl); 675 sgl = sg; 676 } 677 } 678 679 static void err_print_gt_info(struct drm_i915_error_state_buf *m, 680 struct intel_gt_coredump *gt) 681 { 682 struct drm_printer p = i915_error_printer(m); 683 684 intel_gt_info_print(>->info, &p); 685 intel_sseu_print_topology(>->info.sseu, &p); 686 } 687 688 static void err_print_gt(struct drm_i915_error_state_buf *m, 689 struct intel_gt_coredump *gt) 690 { 691 const struct intel_engine_coredump *ee; 692 int i; 693 694 err_printf(m, "GT awake: %s\n", yesno(gt->awake)); 695 err_printf(m, "EIR: 0x%08x\n", gt->eir); 696 err_printf(m, "IER: 0x%08x\n", gt->ier); 697 for (i = 0; i < gt->ngtier; i++) 698 err_printf(m, "GTIER[%d]: 0x%08x\n", i, gt->gtier[i]); 699 err_printf(m, "PGTBL_ER: 0x%08x\n", gt->pgtbl_er); 700 err_printf(m, "FORCEWAKE: 0x%08x\n", gt->forcewake); 701 err_printf(m, "DERRMR: 0x%08x\n", gt->derrmr); 702 703 for (i = 0; i < gt->nfence; i++) 704 err_printf(m, " fence[%d] = %08llx\n", i, gt->fence[i]); 705 706 if (IS_GEN_RANGE(m->i915, 6, 11)) { 707 err_printf(m, "ERROR: 0x%08x\n", gt->error); 708 err_printf(m, "DONE_REG: 0x%08x\n", gt->done_reg); 709 } 710 711 if (INTEL_GEN(m->i915) >= 8) 712 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n", 713 gt->fault_data1, gt->fault_data0); 714 715 if (IS_GEN(m->i915, 7)) 716 err_printf(m, "ERR_INT: 0x%08x\n", gt->err_int); 717 718 if (IS_GEN_RANGE(m->i915, 8, 11)) 719 err_printf(m, "GTT_CACHE_EN: 0x%08x\n", gt->gtt_cache); 720 721 if (IS_GEN(m->i915, 12)) 722 err_printf(m, "AUX_ERR_DBG: 0x%08x\n", gt->aux_err); 723 724 if (INTEL_GEN(m->i915) >= 12) { 725 int i; 726 727 for (i = 0; i < GEN12_SFC_DONE_MAX; i++) 728 err_printf(m, " SFC_DONE[%d]: 0x%08x\n", i, 729 gt->sfc_done[i]); 730 731 err_printf(m, " GAM_DONE: 0x%08x\n", gt->gam_done); 732 } 733 734 for (ee = gt->engine; ee; ee = ee->next) { 735 const struct i915_vma_coredump *vma; 736 737 error_print_engine(m, ee); 738 for (vma = ee->vma; vma; vma = vma->next) 739 print_error_vma(m, ee->engine, vma); 740 } 741 742 if (gt->uc) 743 err_print_uc(m, gt->uc); 744 745 err_print_gt_info(m, gt); 746 } 747 748 static void __err_print_to_sgl(struct drm_i915_error_state_buf *m, 749 struct i915_gpu_coredump *error) 750 { 751 const struct intel_engine_coredump *ee; 752 struct timespec64 ts; 753 754 if (*error->error_msg) 755 err_printf(m, "%s\n", error->error_msg); 756 err_printf(m, "Kernel: %s %s\n", 757 init_utsname()->release, 758 init_utsname()->machine); 759 err_printf(m, "Driver: %s\n", DRIVER_DATE); 760 ts = ktime_to_timespec64(error->time); 761 err_printf(m, "Time: %lld s %ld us\n", 762 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 763 ts = ktime_to_timespec64(error->boottime); 764 err_printf(m, "Boottime: %lld s %ld us\n", 765 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 766 ts = ktime_to_timespec64(error->uptime); 767 err_printf(m, "Uptime: %lld s %ld us\n", 768 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 769 err_printf(m, "Capture: %lu jiffies; %d ms ago\n", 770 error->capture, jiffies_to_msecs(jiffies - error->capture)); 771 772 for (ee = error->gt ? error->gt->engine : NULL; ee; ee = ee->next) 773 err_printf(m, "Active process (on ring %s): %s [%d]\n", 774 ee->engine->name, 775 ee->context.comm, 776 ee->context.pid); 777 778 err_printf(m, "Reset count: %u\n", error->reset_count); 779 err_printf(m, "Suspend count: %u\n", error->suspend_count); 780 err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform)); 781 err_printf(m, "Subplatform: 0x%x\n", 782 intel_subplatform(&error->runtime_info, 783 error->device_info.platform)); 784 err_print_pciid(m, m->i915); 785 786 err_printf(m, "IOMMU enabled?: %d\n", error->iommu); 787 788 if (HAS_CSR(m->i915)) { 789 struct intel_csr *csr = &m->i915->csr; 790 791 err_printf(m, "DMC loaded: %s\n", 792 yesno(csr->dmc_payload != NULL)); 793 err_printf(m, "DMC fw version: %d.%d\n", 794 CSR_VERSION_MAJOR(csr->version), 795 CSR_VERSION_MINOR(csr->version)); 796 } 797 798 err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock)); 799 err_printf(m, "PM suspended: %s\n", yesno(error->suspended)); 800 801 if (error->gt) 802 err_print_gt(m, error->gt); 803 804 if (error->overlay) 805 intel_overlay_print_error_state(m, error->overlay); 806 807 if (error->display) 808 intel_display_print_error_state(m, error->display); 809 810 err_print_capabilities(m, error); 811 err_print_params(m, &error->params); 812 } 813 814 static int err_print_to_sgl(struct i915_gpu_coredump *error) 815 { 816 struct drm_i915_error_state_buf m; 817 818 if (IS_ERR(error)) 819 return PTR_ERR(error); 820 821 if (READ_ONCE(error->sgl)) 822 return 0; 823 824 memset(&m, 0, sizeof(m)); 825 m.i915 = error->i915; 826 827 __err_print_to_sgl(&m, error); 828 829 if (m.buf) { 830 __sg_set_buf(m.cur++, m.buf, m.bytes, m.iter); 831 m.bytes = 0; 832 m.buf = NULL; 833 } 834 if (m.cur) { 835 GEM_BUG_ON(m.end < m.cur); 836 sg_mark_end(m.cur - 1); 837 } 838 GEM_BUG_ON(m.sgl && !m.cur); 839 840 if (m.err) { 841 err_free_sgl(m.sgl); 842 return m.err; 843 } 844 845 if (cmpxchg(&error->sgl, NULL, m.sgl)) 846 err_free_sgl(m.sgl); 847 848 return 0; 849 } 850 851 ssize_t i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error, 852 char *buf, loff_t off, size_t rem) 853 { 854 struct scatterlist *sg; 855 size_t count; 856 loff_t pos; 857 int err; 858 859 if (!error || !rem) 860 return 0; 861 862 err = err_print_to_sgl(error); 863 if (err) 864 return err; 865 866 sg = READ_ONCE(error->fit); 867 if (!sg || off < sg->dma_address) 868 sg = error->sgl; 869 if (!sg) 870 return 0; 871 872 pos = sg->dma_address; 873 count = 0; 874 do { 875 size_t len, start; 876 877 if (sg_is_chain(sg)) { 878 sg = sg_chain_ptr(sg); 879 GEM_BUG_ON(sg_is_chain(sg)); 880 } 881 882 len = sg->length; 883 if (pos + len <= off) { 884 pos += len; 885 continue; 886 } 887 888 start = sg->offset; 889 if (pos < off) { 890 GEM_BUG_ON(off - pos > len); 891 len -= off - pos; 892 start += off - pos; 893 pos = off; 894 } 895 896 len = min(len, rem); 897 GEM_BUG_ON(!len || len > sg->length); 898 899 memcpy(buf, page_address(sg_page(sg)) + start, len); 900 901 count += len; 902 pos += len; 903 904 buf += len; 905 rem -= len; 906 if (!rem) { 907 WRITE_ONCE(error->fit, sg); 908 break; 909 } 910 } while (!sg_is_last(sg++)); 911 912 return count; 913 } 914 915 static void i915_vma_coredump_free(struct i915_vma_coredump *vma) 916 { 917 while (vma) { 918 struct i915_vma_coredump *next = vma->next; 919 int page; 920 921 for (page = 0; page < vma->page_count; page++) 922 free_page((unsigned long)vma->pages[page]); 923 924 kfree(vma); 925 vma = next; 926 } 927 } 928 929 static void cleanup_params(struct i915_gpu_coredump *error) 930 { 931 i915_params_free(&error->params); 932 } 933 934 static void cleanup_uc(struct intel_uc_coredump *uc) 935 { 936 kfree(uc->guc_fw.path); 937 kfree(uc->huc_fw.path); 938 i915_vma_coredump_free(uc->guc_log); 939 940 kfree(uc); 941 } 942 943 static void cleanup_gt(struct intel_gt_coredump *gt) 944 { 945 while (gt->engine) { 946 struct intel_engine_coredump *ee = gt->engine; 947 948 gt->engine = ee->next; 949 950 i915_vma_coredump_free(ee->vma); 951 kfree(ee); 952 } 953 954 if (gt->uc) 955 cleanup_uc(gt->uc); 956 957 kfree(gt); 958 } 959 960 void __i915_gpu_coredump_free(struct kref *error_ref) 961 { 962 struct i915_gpu_coredump *error = 963 container_of(error_ref, typeof(*error), ref); 964 965 while (error->gt) { 966 struct intel_gt_coredump *gt = error->gt; 967 968 error->gt = gt->next; 969 cleanup_gt(gt); 970 } 971 972 kfree(error->overlay); 973 kfree(error->display); 974 975 cleanup_params(error); 976 977 err_free_sgl(error->sgl); 978 kfree(error); 979 } 980 981 static struct i915_vma_coredump * 982 i915_vma_coredump_create(const struct intel_gt *gt, 983 const struct i915_vma *vma, 984 const char *name, 985 struct i915_vma_compress *compress) 986 { 987 struct i915_ggtt *ggtt = gt->ggtt; 988 const u64 slot = ggtt->error_capture.start; 989 struct i915_vma_coredump *dst; 990 unsigned long num_pages; 991 struct sgt_iter iter; 992 int ret; 993 994 might_sleep(); 995 996 if (!vma || !vma->pages || !compress) 997 return NULL; 998 999 num_pages = min_t(u64, vma->size, vma->obj->base.size) >> PAGE_SHIFT; 1000 num_pages = DIV_ROUND_UP(10 * num_pages, 8); /* worstcase zlib growth */ 1001 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), ALLOW_FAIL); 1002 if (!dst) 1003 return NULL; 1004 1005 if (!compress_start(compress)) { 1006 kfree(dst); 1007 return NULL; 1008 } 1009 1010 strcpy(dst->name, name); 1011 dst->next = NULL; 1012 1013 dst->gtt_offset = vma->node.start; 1014 dst->gtt_size = vma->node.size; 1015 dst->gtt_page_sizes = vma->page_sizes.gtt; 1016 dst->num_pages = num_pages; 1017 dst->page_count = 0; 1018 dst->unused = 0; 1019 1020 ret = -EINVAL; 1021 if (drm_mm_node_allocated(&ggtt->error_capture)) { 1022 void __iomem *s; 1023 dma_addr_t dma; 1024 1025 for_each_sgt_daddr(dma, iter, vma->pages) { 1026 ggtt->vm.insert_page(&ggtt->vm, dma, slot, 1027 I915_CACHE_NONE, 0); 1028 mb(); 1029 1030 s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE); 1031 ret = compress_page(compress, 1032 (void __force *)s, dst, 1033 true); 1034 io_mapping_unmap(s); 1035 if (ret) 1036 break; 1037 } 1038 } else if (i915_gem_object_is_lmem(vma->obj)) { 1039 struct intel_memory_region *mem = vma->obj->mm.region; 1040 dma_addr_t dma; 1041 1042 for_each_sgt_daddr(dma, iter, vma->pages) { 1043 void __iomem *s; 1044 1045 s = io_mapping_map_wc(&mem->iomap, dma, PAGE_SIZE); 1046 ret = compress_page(compress, 1047 (void __force *)s, dst, 1048 true); 1049 io_mapping_unmap(s); 1050 if (ret) 1051 break; 1052 } 1053 } else { 1054 struct page *page; 1055 1056 for_each_sgt_page(page, iter, vma->pages) { 1057 void *s; 1058 1059 drm_clflush_pages(&page, 1); 1060 1061 s = kmap(page); 1062 ret = compress_page(compress, s, dst, false); 1063 kunmap(page); 1064 1065 drm_clflush_pages(&page, 1); 1066 1067 if (ret) 1068 break; 1069 } 1070 } 1071 1072 if (ret || compress_flush(compress, dst)) { 1073 while (dst->page_count--) 1074 pool_free(&compress->pool, dst->pages[dst->page_count]); 1075 kfree(dst); 1076 dst = NULL; 1077 } 1078 compress_finish(compress); 1079 1080 return dst; 1081 } 1082 1083 static void gt_record_fences(struct intel_gt_coredump *gt) 1084 { 1085 struct i915_ggtt *ggtt = gt->_gt->ggtt; 1086 struct intel_uncore *uncore = gt->_gt->uncore; 1087 int i; 1088 1089 if (INTEL_GEN(uncore->i915) >= 6) { 1090 for (i = 0; i < ggtt->num_fences; i++) 1091 gt->fence[i] = 1092 intel_uncore_read64(uncore, 1093 FENCE_REG_GEN6_LO(i)); 1094 } else if (INTEL_GEN(uncore->i915) >= 4) { 1095 for (i = 0; i < ggtt->num_fences; i++) 1096 gt->fence[i] = 1097 intel_uncore_read64(uncore, 1098 FENCE_REG_965_LO(i)); 1099 } else { 1100 for (i = 0; i < ggtt->num_fences; i++) 1101 gt->fence[i] = 1102 intel_uncore_read(uncore, FENCE_REG(i)); 1103 } 1104 gt->nfence = i; 1105 } 1106 1107 static void engine_record_registers(struct intel_engine_coredump *ee) 1108 { 1109 const struct intel_engine_cs *engine = ee->engine; 1110 struct drm_i915_private *i915 = engine->i915; 1111 1112 if (INTEL_GEN(i915) >= 6) { 1113 ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL); 1114 1115 if (INTEL_GEN(i915) >= 12) 1116 ee->fault_reg = intel_uncore_read(engine->uncore, 1117 GEN12_RING_FAULT_REG); 1118 else if (INTEL_GEN(i915) >= 8) 1119 ee->fault_reg = intel_uncore_read(engine->uncore, 1120 GEN8_RING_FAULT_REG); 1121 else 1122 ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine); 1123 } 1124 1125 if (INTEL_GEN(i915) >= 4) { 1126 ee->esr = ENGINE_READ(engine, RING_ESR); 1127 ee->faddr = ENGINE_READ(engine, RING_DMA_FADD); 1128 ee->ipeir = ENGINE_READ(engine, RING_IPEIR); 1129 ee->ipehr = ENGINE_READ(engine, RING_IPEHR); 1130 ee->instps = ENGINE_READ(engine, RING_INSTPS); 1131 ee->bbaddr = ENGINE_READ(engine, RING_BBADDR); 1132 ee->ccid = ENGINE_READ(engine, CCID); 1133 if (INTEL_GEN(i915) >= 8) { 1134 ee->faddr |= (u64)ENGINE_READ(engine, RING_DMA_FADD_UDW) << 32; 1135 ee->bbaddr |= (u64)ENGINE_READ(engine, RING_BBADDR_UDW) << 32; 1136 } 1137 ee->bbstate = ENGINE_READ(engine, RING_BBSTATE); 1138 } else { 1139 ee->faddr = ENGINE_READ(engine, DMA_FADD_I8XX); 1140 ee->ipeir = ENGINE_READ(engine, IPEIR); 1141 ee->ipehr = ENGINE_READ(engine, IPEHR); 1142 } 1143 1144 intel_engine_get_instdone(engine, &ee->instdone); 1145 1146 ee->instpm = ENGINE_READ(engine, RING_INSTPM); 1147 ee->acthd = intel_engine_get_active_head(engine); 1148 ee->start = ENGINE_READ(engine, RING_START); 1149 ee->head = ENGINE_READ(engine, RING_HEAD); 1150 ee->tail = ENGINE_READ(engine, RING_TAIL); 1151 ee->ctl = ENGINE_READ(engine, RING_CTL); 1152 if (INTEL_GEN(i915) > 2) 1153 ee->mode = ENGINE_READ(engine, RING_MI_MODE); 1154 1155 if (!HWS_NEEDS_PHYSICAL(i915)) { 1156 i915_reg_t mmio; 1157 1158 if (IS_GEN(i915, 7)) { 1159 switch (engine->id) { 1160 default: 1161 MISSING_CASE(engine->id); 1162 /* fall through */ 1163 case RCS0: 1164 mmio = RENDER_HWS_PGA_GEN7; 1165 break; 1166 case BCS0: 1167 mmio = BLT_HWS_PGA_GEN7; 1168 break; 1169 case VCS0: 1170 mmio = BSD_HWS_PGA_GEN7; 1171 break; 1172 case VECS0: 1173 mmio = VEBOX_HWS_PGA_GEN7; 1174 break; 1175 } 1176 } else if (IS_GEN(engine->i915, 6)) { 1177 mmio = RING_HWS_PGA_GEN6(engine->mmio_base); 1178 } else { 1179 /* XXX: gen8 returns to sanity */ 1180 mmio = RING_HWS_PGA(engine->mmio_base); 1181 } 1182 1183 ee->hws = intel_uncore_read(engine->uncore, mmio); 1184 } 1185 1186 ee->reset_count = i915_reset_engine_count(&i915->gpu_error, engine); 1187 1188 if (HAS_PPGTT(i915)) { 1189 int i; 1190 1191 ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7); 1192 1193 if (IS_GEN(i915, 6)) { 1194 ee->vm_info.pp_dir_base = 1195 ENGINE_READ(engine, RING_PP_DIR_BASE_READ); 1196 } else if (IS_GEN(i915, 7)) { 1197 ee->vm_info.pp_dir_base = 1198 ENGINE_READ(engine, RING_PP_DIR_BASE); 1199 } else if (INTEL_GEN(i915) >= 8) { 1200 u32 base = engine->mmio_base; 1201 1202 for (i = 0; i < 4; i++) { 1203 ee->vm_info.pdp[i] = 1204 intel_uncore_read(engine->uncore, 1205 GEN8_RING_PDP_UDW(base, i)); 1206 ee->vm_info.pdp[i] <<= 32; 1207 ee->vm_info.pdp[i] |= 1208 intel_uncore_read(engine->uncore, 1209 GEN8_RING_PDP_LDW(base, i)); 1210 } 1211 } 1212 } 1213 } 1214 1215 static void record_request(const struct i915_request *request, 1216 struct i915_request_coredump *erq) 1217 { 1218 erq->flags = request->fence.flags; 1219 erq->context = request->fence.context; 1220 erq->seqno = request->fence.seqno; 1221 erq->sched_attr = request->sched.attr; 1222 erq->head = request->head; 1223 erq->tail = request->tail; 1224 1225 erq->pid = 0; 1226 rcu_read_lock(); 1227 if (!intel_context_is_closed(request->context)) { 1228 const struct i915_gem_context *ctx; 1229 1230 ctx = rcu_dereference(request->context->gem_context); 1231 if (ctx) 1232 erq->pid = pid_nr(ctx->pid); 1233 } 1234 rcu_read_unlock(); 1235 } 1236 1237 static void engine_record_execlists(struct intel_engine_coredump *ee) 1238 { 1239 const struct intel_engine_execlists * const el = &ee->engine->execlists; 1240 struct i915_request * const *port = el->active; 1241 unsigned int n = 0; 1242 1243 while (*port) 1244 record_request(*port++, &ee->execlist[n++]); 1245 1246 ee->num_ports = n; 1247 } 1248 1249 static bool record_context(struct i915_gem_context_coredump *e, 1250 const struct i915_request *rq) 1251 { 1252 struct i915_gem_context *ctx; 1253 struct task_struct *task; 1254 bool simulated; 1255 1256 rcu_read_lock(); 1257 ctx = rcu_dereference(rq->context->gem_context); 1258 if (ctx && !kref_get_unless_zero(&ctx->ref)) 1259 ctx = NULL; 1260 rcu_read_unlock(); 1261 if (!ctx) 1262 return true; 1263 1264 rcu_read_lock(); 1265 task = pid_task(ctx->pid, PIDTYPE_PID); 1266 if (task) { 1267 strcpy(e->comm, task->comm); 1268 e->pid = task->pid; 1269 } 1270 rcu_read_unlock(); 1271 1272 e->sched_attr = ctx->sched; 1273 e->guilty = atomic_read(&ctx->guilty_count); 1274 e->active = atomic_read(&ctx->active_count); 1275 1276 e->total_runtime = rq->context->runtime.total; 1277 e->avg_runtime = ewma_runtime_read(&rq->context->runtime.avg); 1278 1279 simulated = i915_gem_context_no_error_capture(ctx); 1280 1281 i915_gem_context_put(ctx); 1282 return simulated; 1283 } 1284 1285 struct intel_engine_capture_vma { 1286 struct intel_engine_capture_vma *next; 1287 struct i915_vma *vma; 1288 char name[16]; 1289 }; 1290 1291 static struct intel_engine_capture_vma * 1292 capture_vma(struct intel_engine_capture_vma *next, 1293 struct i915_vma *vma, 1294 const char *name, 1295 gfp_t gfp) 1296 { 1297 struct intel_engine_capture_vma *c; 1298 1299 if (!vma) 1300 return next; 1301 1302 c = kmalloc(sizeof(*c), gfp); 1303 if (!c) 1304 return next; 1305 1306 if (!i915_active_acquire_if_busy(&vma->active)) { 1307 kfree(c); 1308 return next; 1309 } 1310 1311 strcpy(c->name, name); 1312 c->vma = i915_vma_get(vma); 1313 1314 c->next = next; 1315 return c; 1316 } 1317 1318 static struct intel_engine_capture_vma * 1319 capture_user(struct intel_engine_capture_vma *capture, 1320 const struct i915_request *rq, 1321 gfp_t gfp) 1322 { 1323 struct i915_capture_list *c; 1324 1325 for (c = rq->capture_list; c; c = c->next) 1326 capture = capture_vma(capture, c->vma, "user", gfp); 1327 1328 return capture; 1329 } 1330 1331 static void add_vma(struct intel_engine_coredump *ee, 1332 struct i915_vma_coredump *vma) 1333 { 1334 if (vma) { 1335 vma->next = ee->vma; 1336 ee->vma = vma; 1337 } 1338 } 1339 1340 struct intel_engine_coredump * 1341 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp) 1342 { 1343 struct intel_engine_coredump *ee; 1344 1345 ee = kzalloc(sizeof(*ee), gfp); 1346 if (!ee) 1347 return NULL; 1348 1349 ee->engine = engine; 1350 1351 engine_record_registers(ee); 1352 engine_record_execlists(ee); 1353 1354 return ee; 1355 } 1356 1357 struct intel_engine_capture_vma * 1358 intel_engine_coredump_add_request(struct intel_engine_coredump *ee, 1359 struct i915_request *rq, 1360 gfp_t gfp) 1361 { 1362 struct intel_engine_capture_vma *vma = NULL; 1363 1364 ee->simulated |= record_context(&ee->context, rq); 1365 if (ee->simulated) 1366 return NULL; 1367 1368 /* 1369 * We need to copy these to an anonymous buffer 1370 * as the simplest method to avoid being overwritten 1371 * by userspace. 1372 */ 1373 vma = capture_vma(vma, rq->batch, "batch", gfp); 1374 vma = capture_user(vma, rq, gfp); 1375 vma = capture_vma(vma, rq->ring->vma, "ring", gfp); 1376 vma = capture_vma(vma, rq->context->state, "HW context", gfp); 1377 1378 ee->rq_head = rq->head; 1379 ee->rq_post = rq->postfix; 1380 ee->rq_tail = rq->tail; 1381 1382 return vma; 1383 } 1384 1385 void 1386 intel_engine_coredump_add_vma(struct intel_engine_coredump *ee, 1387 struct intel_engine_capture_vma *capture, 1388 struct i915_vma_compress *compress) 1389 { 1390 const struct intel_engine_cs *engine = ee->engine; 1391 1392 while (capture) { 1393 struct intel_engine_capture_vma *this = capture; 1394 struct i915_vma *vma = this->vma; 1395 1396 add_vma(ee, 1397 i915_vma_coredump_create(engine->gt, 1398 vma, this->name, 1399 compress)); 1400 1401 i915_active_release(&vma->active); 1402 i915_vma_put(vma); 1403 1404 capture = this->next; 1405 kfree(this); 1406 } 1407 1408 add_vma(ee, 1409 i915_vma_coredump_create(engine->gt, 1410 engine->status_page.vma, 1411 "HW Status", 1412 compress)); 1413 1414 add_vma(ee, 1415 i915_vma_coredump_create(engine->gt, 1416 engine->wa_ctx.vma, 1417 "WA context", 1418 compress)); 1419 } 1420 1421 static struct intel_engine_coredump * 1422 capture_engine(struct intel_engine_cs *engine, 1423 struct i915_vma_compress *compress) 1424 { 1425 struct intel_engine_capture_vma *capture = NULL; 1426 struct intel_engine_coredump *ee; 1427 struct i915_request *rq; 1428 unsigned long flags; 1429 1430 ee = intel_engine_coredump_alloc(engine, GFP_KERNEL); 1431 if (!ee) 1432 return NULL; 1433 1434 spin_lock_irqsave(&engine->active.lock, flags); 1435 rq = intel_engine_find_active_request(engine); 1436 if (rq) 1437 capture = intel_engine_coredump_add_request(ee, rq, 1438 ATOMIC_MAYFAIL); 1439 spin_unlock_irqrestore(&engine->active.lock, flags); 1440 if (!capture) { 1441 kfree(ee); 1442 return NULL; 1443 } 1444 1445 intel_engine_coredump_add_vma(ee, capture, compress); 1446 1447 return ee; 1448 } 1449 1450 static void 1451 gt_record_engines(struct intel_gt_coredump *gt, 1452 struct i915_vma_compress *compress) 1453 { 1454 struct intel_engine_cs *engine; 1455 enum intel_engine_id id; 1456 1457 for_each_engine(engine, gt->_gt, id) { 1458 struct intel_engine_coredump *ee; 1459 1460 /* Refill our page pool before entering atomic section */ 1461 pool_refill(&compress->pool, ALLOW_FAIL); 1462 1463 ee = capture_engine(engine, compress); 1464 if (!ee) 1465 continue; 1466 1467 gt->simulated |= ee->simulated; 1468 if (ee->simulated) { 1469 kfree(ee); 1470 continue; 1471 } 1472 1473 ee->next = gt->engine; 1474 gt->engine = ee; 1475 } 1476 } 1477 1478 static struct intel_uc_coredump * 1479 gt_record_uc(struct intel_gt_coredump *gt, 1480 struct i915_vma_compress *compress) 1481 { 1482 const struct intel_uc *uc = >->_gt->uc; 1483 struct intel_uc_coredump *error_uc; 1484 1485 error_uc = kzalloc(sizeof(*error_uc), ALLOW_FAIL); 1486 if (!error_uc) 1487 return NULL; 1488 1489 memcpy(&error_uc->guc_fw, &uc->guc.fw, sizeof(uc->guc.fw)); 1490 memcpy(&error_uc->huc_fw, &uc->huc.fw, sizeof(uc->huc.fw)); 1491 1492 /* Non-default firmware paths will be specified by the modparam. 1493 * As modparams are generally accesible from the userspace make 1494 * explicit copies of the firmware paths. 1495 */ 1496 error_uc->guc_fw.path = kstrdup(uc->guc.fw.path, ALLOW_FAIL); 1497 error_uc->huc_fw.path = kstrdup(uc->huc.fw.path, ALLOW_FAIL); 1498 error_uc->guc_log = 1499 i915_vma_coredump_create(gt->_gt, 1500 uc->guc.log.vma, "GuC log buffer", 1501 compress); 1502 1503 return error_uc; 1504 } 1505 1506 static void gt_capture_prepare(struct intel_gt_coredump *gt) 1507 { 1508 struct i915_ggtt *ggtt = gt->_gt->ggtt; 1509 1510 mutex_lock(&ggtt->error_mutex); 1511 } 1512 1513 static void gt_capture_finish(struct intel_gt_coredump *gt) 1514 { 1515 struct i915_ggtt *ggtt = gt->_gt->ggtt; 1516 1517 if (drm_mm_node_allocated(&ggtt->error_capture)) 1518 ggtt->vm.clear_range(&ggtt->vm, 1519 ggtt->error_capture.start, 1520 PAGE_SIZE); 1521 1522 mutex_unlock(&ggtt->error_mutex); 1523 } 1524 1525 /* Capture all registers which don't fit into another category. */ 1526 static void gt_record_regs(struct intel_gt_coredump *gt) 1527 { 1528 struct intel_uncore *uncore = gt->_gt->uncore; 1529 struct drm_i915_private *i915 = uncore->i915; 1530 int i; 1531 1532 /* 1533 * General organization 1534 * 1. Registers specific to a single generation 1535 * 2. Registers which belong to multiple generations 1536 * 3. Feature specific registers. 1537 * 4. Everything else 1538 * Please try to follow the order. 1539 */ 1540 1541 /* 1: Registers specific to a single generation */ 1542 if (IS_VALLEYVIEW(i915)) { 1543 gt->gtier[0] = intel_uncore_read(uncore, GTIER); 1544 gt->ier = intel_uncore_read(uncore, VLV_IER); 1545 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_VLV); 1546 } 1547 1548 if (IS_GEN(i915, 7)) 1549 gt->err_int = intel_uncore_read(uncore, GEN7_ERR_INT); 1550 1551 if (INTEL_GEN(i915) >= 12) { 1552 gt->fault_data0 = intel_uncore_read(uncore, 1553 GEN12_FAULT_TLB_DATA0); 1554 gt->fault_data1 = intel_uncore_read(uncore, 1555 GEN12_FAULT_TLB_DATA1); 1556 } else if (INTEL_GEN(i915) >= 8) { 1557 gt->fault_data0 = intel_uncore_read(uncore, 1558 GEN8_FAULT_TLB_DATA0); 1559 gt->fault_data1 = intel_uncore_read(uncore, 1560 GEN8_FAULT_TLB_DATA1); 1561 } 1562 1563 if (IS_GEN(i915, 6)) { 1564 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE); 1565 gt->gab_ctl = intel_uncore_read(uncore, GAB_CTL); 1566 gt->gfx_mode = intel_uncore_read(uncore, GFX_MODE); 1567 } 1568 1569 /* 2: Registers which belong to multiple generations */ 1570 if (INTEL_GEN(i915) >= 7) 1571 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_MT); 1572 1573 if (INTEL_GEN(i915) >= 6) { 1574 gt->derrmr = intel_uncore_read(uncore, DERRMR); 1575 if (INTEL_GEN(i915) < 12) { 1576 gt->error = intel_uncore_read(uncore, ERROR_GEN6); 1577 gt->done_reg = intel_uncore_read(uncore, DONE_REG); 1578 } 1579 } 1580 1581 /* 3: Feature specific registers */ 1582 if (IS_GEN_RANGE(i915, 6, 7)) { 1583 gt->gam_ecochk = intel_uncore_read(uncore, GAM_ECOCHK); 1584 gt->gac_eco = intel_uncore_read(uncore, GAC_ECO_BITS); 1585 } 1586 1587 if (IS_GEN_RANGE(i915, 8, 11)) 1588 gt->gtt_cache = intel_uncore_read(uncore, HSW_GTT_CACHE_EN); 1589 1590 if (IS_GEN(i915, 12)) 1591 gt->aux_err = intel_uncore_read(uncore, GEN12_AUX_ERR_DBG); 1592 1593 if (INTEL_GEN(i915) >= 12) { 1594 for (i = 0; i < GEN12_SFC_DONE_MAX; i++) { 1595 gt->sfc_done[i] = 1596 intel_uncore_read(uncore, GEN12_SFC_DONE(i)); 1597 } 1598 1599 gt->gam_done = intel_uncore_read(uncore, GEN12_GAM_DONE); 1600 } 1601 1602 /* 4: Everything else */ 1603 if (INTEL_GEN(i915) >= 11) { 1604 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER); 1605 gt->gtier[0] = 1606 intel_uncore_read(uncore, 1607 GEN11_RENDER_COPY_INTR_ENABLE); 1608 gt->gtier[1] = 1609 intel_uncore_read(uncore, GEN11_VCS_VECS_INTR_ENABLE); 1610 gt->gtier[2] = 1611 intel_uncore_read(uncore, GEN11_GUC_SG_INTR_ENABLE); 1612 gt->gtier[3] = 1613 intel_uncore_read(uncore, 1614 GEN11_GPM_WGBOXPERF_INTR_ENABLE); 1615 gt->gtier[4] = 1616 intel_uncore_read(uncore, 1617 GEN11_CRYPTO_RSVD_INTR_ENABLE); 1618 gt->gtier[5] = 1619 intel_uncore_read(uncore, 1620 GEN11_GUNIT_CSME_INTR_ENABLE); 1621 gt->ngtier = 6; 1622 } else if (INTEL_GEN(i915) >= 8) { 1623 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER); 1624 for (i = 0; i < 4; i++) 1625 gt->gtier[i] = 1626 intel_uncore_read(uncore, GEN8_GT_IER(i)); 1627 gt->ngtier = 4; 1628 } else if (HAS_PCH_SPLIT(i915)) { 1629 gt->ier = intel_uncore_read(uncore, DEIER); 1630 gt->gtier[0] = intel_uncore_read(uncore, GTIER); 1631 gt->ngtier = 1; 1632 } else if (IS_GEN(i915, 2)) { 1633 gt->ier = intel_uncore_read16(uncore, GEN2_IER); 1634 } else if (!IS_VALLEYVIEW(i915)) { 1635 gt->ier = intel_uncore_read(uncore, GEN2_IER); 1636 } 1637 gt->eir = intel_uncore_read(uncore, EIR); 1638 gt->pgtbl_er = intel_uncore_read(uncore, PGTBL_ER); 1639 } 1640 1641 static void gt_record_info(struct intel_gt_coredump *gt) 1642 { 1643 memcpy(>->info, >->_gt->info, sizeof(struct intel_gt_info)); 1644 } 1645 1646 /* 1647 * Generate a semi-unique error code. The code is not meant to have meaning, The 1648 * code's only purpose is to try to prevent false duplicated bug reports by 1649 * grossly estimating a GPU error state. 1650 * 1651 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine 1652 * the hang if we could strip the GTT offset information from it. 1653 * 1654 * It's only a small step better than a random number in its current form. 1655 */ 1656 static u32 generate_ecode(const struct intel_engine_coredump *ee) 1657 { 1658 /* 1659 * IPEHR would be an ideal way to detect errors, as it's the gross 1660 * measure of "the command that hung." However, has some very common 1661 * synchronization commands which almost always appear in the case 1662 * strictly a client bug. Use instdone to differentiate those some. 1663 */ 1664 return ee ? ee->ipehr ^ ee->instdone.instdone : 0; 1665 } 1666 1667 static const char *error_msg(struct i915_gpu_coredump *error) 1668 { 1669 struct intel_engine_coredump *first = NULL; 1670 struct intel_gt_coredump *gt; 1671 intel_engine_mask_t engines; 1672 int len; 1673 1674 engines = 0; 1675 for (gt = error->gt; gt; gt = gt->next) { 1676 struct intel_engine_coredump *cs; 1677 1678 if (gt->engine && !first) 1679 first = gt->engine; 1680 1681 for (cs = gt->engine; cs; cs = cs->next) 1682 engines |= cs->engine->mask; 1683 } 1684 1685 len = scnprintf(error->error_msg, sizeof(error->error_msg), 1686 "GPU HANG: ecode %d:%x:%08x", 1687 INTEL_GEN(error->i915), engines, 1688 generate_ecode(first)); 1689 if (first && first->context.pid) { 1690 /* Just show the first executing process, more is confusing */ 1691 len += scnprintf(error->error_msg + len, 1692 sizeof(error->error_msg) - len, 1693 ", in %s [%d]", 1694 first->context.comm, first->context.pid); 1695 } 1696 1697 return error->error_msg; 1698 } 1699 1700 static void capture_gen(struct i915_gpu_coredump *error) 1701 { 1702 struct drm_i915_private *i915 = error->i915; 1703 1704 error->wakelock = atomic_read(&i915->runtime_pm.wakeref_count); 1705 error->suspended = i915->runtime_pm.suspended; 1706 1707 error->iommu = -1; 1708 #ifdef CONFIG_INTEL_IOMMU 1709 error->iommu = intel_iommu_gfx_mapped; 1710 #endif 1711 error->reset_count = i915_reset_count(&i915->gpu_error); 1712 error->suspend_count = i915->suspend_count; 1713 1714 i915_params_copy(&error->params, &i915->params); 1715 memcpy(&error->device_info, 1716 INTEL_INFO(i915), 1717 sizeof(error->device_info)); 1718 memcpy(&error->runtime_info, 1719 RUNTIME_INFO(i915), 1720 sizeof(error->runtime_info)); 1721 error->driver_caps = i915->caps; 1722 } 1723 1724 struct i915_gpu_coredump * 1725 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp) 1726 { 1727 struct i915_gpu_coredump *error; 1728 1729 if (!i915->params.error_capture) 1730 return NULL; 1731 1732 error = kzalloc(sizeof(*error), gfp); 1733 if (!error) 1734 return NULL; 1735 1736 kref_init(&error->ref); 1737 error->i915 = i915; 1738 1739 error->time = ktime_get_real(); 1740 error->boottime = ktime_get_boottime(); 1741 error->uptime = ktime_sub(ktime_get(), i915->gt.last_init_time); 1742 error->capture = jiffies; 1743 1744 capture_gen(error); 1745 1746 return error; 1747 } 1748 1749 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x)) 1750 1751 struct intel_gt_coredump * 1752 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp) 1753 { 1754 struct intel_gt_coredump *gc; 1755 1756 gc = kzalloc(sizeof(*gc), gfp); 1757 if (!gc) 1758 return NULL; 1759 1760 gc->_gt = gt; 1761 gc->awake = intel_gt_pm_is_awake(gt); 1762 1763 gt_record_regs(gc); 1764 gt_record_fences(gc); 1765 1766 return gc; 1767 } 1768 1769 struct i915_vma_compress * 1770 i915_vma_capture_prepare(struct intel_gt_coredump *gt) 1771 { 1772 struct i915_vma_compress *compress; 1773 1774 compress = kmalloc(sizeof(*compress), ALLOW_FAIL); 1775 if (!compress) 1776 return NULL; 1777 1778 if (!compress_init(compress)) { 1779 kfree(compress); 1780 return NULL; 1781 } 1782 1783 gt_capture_prepare(gt); 1784 1785 return compress; 1786 } 1787 1788 void i915_vma_capture_finish(struct intel_gt_coredump *gt, 1789 struct i915_vma_compress *compress) 1790 { 1791 if (!compress) 1792 return; 1793 1794 gt_capture_finish(gt); 1795 1796 compress_fini(compress); 1797 kfree(compress); 1798 } 1799 1800 struct i915_gpu_coredump *i915_gpu_coredump(struct drm_i915_private *i915) 1801 { 1802 struct i915_gpu_coredump *error; 1803 1804 /* Check if GPU capture has been disabled */ 1805 error = READ_ONCE(i915->gpu_error.first_error); 1806 if (IS_ERR(error)) 1807 return error; 1808 1809 error = i915_gpu_coredump_alloc(i915, ALLOW_FAIL); 1810 if (!error) 1811 return ERR_PTR(-ENOMEM); 1812 1813 error->gt = intel_gt_coredump_alloc(&i915->gt, ALLOW_FAIL); 1814 if (error->gt) { 1815 struct i915_vma_compress *compress; 1816 1817 compress = i915_vma_capture_prepare(error->gt); 1818 if (!compress) { 1819 kfree(error->gt); 1820 kfree(error); 1821 return ERR_PTR(-ENOMEM); 1822 } 1823 1824 gt_record_info(error->gt); 1825 gt_record_engines(error->gt, compress); 1826 1827 if (INTEL_INFO(i915)->has_gt_uc) 1828 error->gt->uc = gt_record_uc(error->gt, compress); 1829 1830 i915_vma_capture_finish(error->gt, compress); 1831 1832 error->simulated |= error->gt->simulated; 1833 } 1834 1835 error->overlay = intel_overlay_capture_error_state(i915); 1836 error->display = intel_display_capture_error_state(i915); 1837 1838 return error; 1839 } 1840 1841 void i915_error_state_store(struct i915_gpu_coredump *error) 1842 { 1843 struct drm_i915_private *i915; 1844 static bool warned; 1845 1846 if (IS_ERR_OR_NULL(error)) 1847 return; 1848 1849 i915 = error->i915; 1850 drm_info(&i915->drm, "%s\n", error_msg(error)); 1851 1852 if (error->simulated || 1853 cmpxchg(&i915->gpu_error.first_error, NULL, error)) 1854 return; 1855 1856 i915_gpu_coredump_get(error); 1857 1858 if (!xchg(&warned, true) && 1859 ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) { 1860 pr_info("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n"); 1861 pr_info("Please file a _new_ bug report at https://gitlab.freedesktop.org/drm/intel/issues/new.\n"); 1862 pr_info("Please see https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs for details.\n"); 1863 pr_info("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n"); 1864 pr_info("The GPU crash dump is required to analyze GPU hangs, so please always attach it.\n"); 1865 pr_info("GPU crash dump saved to /sys/class/drm/card%d/error\n", 1866 i915->drm.primary->index); 1867 } 1868 } 1869 1870 /** 1871 * i915_capture_error_state - capture an error record for later analysis 1872 * @i915: i915 device 1873 * 1874 * Should be called when an error is detected (either a hang or an error 1875 * interrupt) to capture error state from the time of the error. Fills 1876 * out a structure which becomes available in debugfs for user level tools 1877 * to pick up. 1878 */ 1879 void i915_capture_error_state(struct drm_i915_private *i915) 1880 { 1881 struct i915_gpu_coredump *error; 1882 1883 error = i915_gpu_coredump(i915); 1884 if (IS_ERR(error)) { 1885 cmpxchg(&i915->gpu_error.first_error, NULL, error); 1886 return; 1887 } 1888 1889 i915_error_state_store(error); 1890 i915_gpu_coredump_put(error); 1891 } 1892 1893 struct i915_gpu_coredump * 1894 i915_first_error_state(struct drm_i915_private *i915) 1895 { 1896 struct i915_gpu_coredump *error; 1897 1898 spin_lock_irq(&i915->gpu_error.lock); 1899 error = i915->gpu_error.first_error; 1900 if (!IS_ERR_OR_NULL(error)) 1901 i915_gpu_coredump_get(error); 1902 spin_unlock_irq(&i915->gpu_error.lock); 1903 1904 return error; 1905 } 1906 1907 void i915_reset_error_state(struct drm_i915_private *i915) 1908 { 1909 struct i915_gpu_coredump *error; 1910 1911 spin_lock_irq(&i915->gpu_error.lock); 1912 error = i915->gpu_error.first_error; 1913 if (error != ERR_PTR(-ENODEV)) /* if disabled, always disabled */ 1914 i915->gpu_error.first_error = NULL; 1915 spin_unlock_irq(&i915->gpu_error.lock); 1916 1917 if (!IS_ERR_OR_NULL(error)) 1918 i915_gpu_coredump_put(error); 1919 } 1920 1921 void i915_disable_error_state(struct drm_i915_private *i915, int err) 1922 { 1923 spin_lock_irq(&i915->gpu_error.lock); 1924 if (!i915->gpu_error.first_error) 1925 i915->gpu_error.first_error = ERR_PTR(err); 1926 spin_unlock_irq(&i915->gpu_error.lock); 1927 } 1928